lab6ALUpart3.vhd.bak

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity lab6ALU is 
port(Clk: in std_logic;---input clock signal
		A,B : in unsigned(7 downto 0); ---8 bit inputs from latches a and b
		--student_id : in unsigned(3 downto 0); --4 bit student id from fsm 
		OP : in unsigned(15 downto 0);-- 16 bit selector for operation from decoder 
		Neg : out std_logic;--is the result negative? set -ve bit output
		R1 : out unsigned(3 downto 0); -- lower 4bits of 8 bit result output
		R2 : out unsigned(3 downto 0)); -- higher 4bits of 8 bit result output
end lab6ALU;
architecture calculation of lab6ALU is --temporary signal declarations 
signal Reg1, Reg2, Result: unsigned(7 downto 0) := (others => '0');
--signal Reg4: unsigned (0 to 7);
begin
Reg1 <= A; --temporary store A in reg1 local variable
Reg2 <= B; --temporary store B in reg2 local variable
process(Clk,OP)
begin 
	if(rising_edge(Clk))THEN --Do the calculation @ positive edge of clock cycle 
		case OP is 
			WHEN "0000000000000001" =>
				--Do addition for Reg1 and Reg2
				Result <= (Reg1 + Reg2);
				Neg <= '0';
			
			WHEN "0000000000000010" =>
				--Do subtraction 
				--"Neg" bit set if required
				if(Reg2 > Reg1)then
					Result <= Reg1 + (NOT(Reg2+1));
					Neg <= '1'; 
				else
					Result <= Reg1 - Reg2;
					Neg <= '0'; 
				end if; 

			WHEN "0000000000000100" =>
				--Do inverse
				Result <= (NOT(Reg1));
				Neg <= '0';
			
			WHEN "0000000000001000" =>
				--Do Boolean Nand
				Result <= (Reg1 NAND Reg2);
				Neg <= '0';
				
			WHEN "0000000000010000" =>
				--Do boolean NOR
				Result <= (Reg1 NOR Reg2);
				Neg <= '0';

			WHEN "0000000000100000" =>
				--Do Boolean AND
				Result <= (Reg1 AND Reg2);
				Neg <= '0';

			WHEN "0000000001000000" =>
				--Do Boolean XOR
				Result <= (Reg1 XOR Reg2);
				Neg <= '0';
				
			WHEN "0000000010000000" =>
				--Do Boolean OR
				Result <= (Reg1 OR Reg2);
				Neg <= '0';
			
			WHEN "0000000100000000" =>
				--Do Boolean XNOR
				Result <= (Reg1 XNOR Reg2);
				Neg <= '0';
				
			WHEN OTHERS =>
				--Dont care; do nothing
				Result <= "--------";
				Neg <= '0';
				
		end case;
	end if;
end process;
R1 <= Result(3 downto 0); -- since the output seven segments can
R2 <= Result(7 downto 4); -- only 4 bits split the 8 bit to two 4 bis
end calculation;