An experiment in hardware accelerated DSLs and parallel algorithms for signal processing applications. Written in Rust. Uses the Calyx IR backend.
- Verilog test module from: https://brng.dev/blog/technical/tutorial/2019/05/11/icarus_gtkwave/
- Chisel demo from Prof Scott Beamer: https://github.com/agile-hw/lectures
Why the name "Zinnia"? We use Calyx, which is also the collective name for the petals of a flower. Zinnias are one species of flowers. It also sounds kind of like Zyria, which is a language we took inspiration from.
