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Overview

Driven by increasingly complex use cases, modern GPUs are evolving from a constrained programming model to something more sophisticated and general purpose. This project approaches the problem from the opposite direction, starting with a very general purpose architecture and adding parallel processing capabilities. While this can run graphical programs, it is not optimized for that, as it doesn't have the fixed function hardware that a traditional GPU has. It is focused on computation heavy use cases. It is capable of operating as a coprocessor or a standalone processor. High level features include:

• Multiple cores with cache coherence
• Hardware multithreading
• Wide vector floating point SIMD with predicated execution
• Virtual memory

When synthesized for a Cyclone IV FPGA, this takes ~74k logic elements and has a maximum frequency of ~54 MHz. When synthesized for ASIC using the NanGate 45 nm cell library and Syopsys Design Compiler, estimates show a maximum frequency of 671 MHz, and, for each core, 1.84 mm2 of area and 329 mW power usage.

Documentation

• Instruction Set
• Microarchitecture
• Compiler/ABI
• Test SOC Register Map
• How To Add An Instruction
• Memory Mapped Peripherals
• V2 Microarchitecture Changes
• Compiling Parallel Kernels in Rust
• XV6 Operating System Port
• HDL Conventions
• JTAG On Chip Debugging Support
• DE2 115 Setup

Misc

• Gallery
• ISPASS 2015 Paper (Microarchitectural details are for older v1 architecture)
• ISPASS 2016 Paper
• Similar Projects