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Overview

This processor is a hybrid architecture that combines GPU architectural concepts with a general purpose instruction set. The hardware implementation is focused more on computation than graphics, as it currently lacks fixed function graphics hardware. It is capable of operating as a coprocessor or a standalone processor. It includes support for:

• Multiple cores with cache coherence
• Hardware multithreading
• Wide vector floating point SIMD with predicated execution
• Virtual memory

When synthesized for a Cyclone IV FPGA, this takes ~74k logic elements and has a maximum frequency of ~54 MHz. When synthesized for ASIC using the NanGate 45 nm cell library and Syopsys Design Compiler, estimates show a maximum frequency of 671 MHz. Each core takes 1.84 mm2 of area and uses 329 mW.

Documentation

• Instruction Set
• Microarchitecture
• Compiler/ABI
• Test SOC Register Map
• How To Add An Instruction
• Memory Mapped Peripherals
• V2 Microarchitecture Changes
• Compiling Parallel Kernels in Rust
• HDL Conventions
• JTAG On Chip Debugging Support
• Performance Counters

Misc

• Gallery
• ISPASS 2015 Paper (Microarchitectural details are for older v1 architecture)
• ISPASS 2016 Paper
• Similar Projects