From f5c80157ffef8371acb93880cf6f344a7b805275 Mon Sep 17 00:00:00 2001 From: jchabloz Date: Fri, 8 Mar 2024 23:04:53 +0100 Subject: [PATCH] Updated docs - Alternative simulators + misc --- docs/src/intro.rst | 32 ++++++++++++++++++++++++-------- docs/src/release_notes.rst | 12 ++++++++---- 2 files changed, 32 insertions(+), 12 deletions(-) diff --git a/docs/src/intro.rst b/docs/src/intro.rst index 6c79e17..897b88c 100644 --- a/docs/src/intro.rst +++ b/docs/src/intro.rst @@ -21,7 +21,7 @@ to trying and compile Verisocks: packaged version provided with your favorite distro. * GCC C or C++ compiler -.. note:: +.. note:: Older GCC versions will most likely complain about the variadic macros used for logging purposes. These warnings can normally be safely ignored... @@ -68,6 +68,11 @@ not to impact your system's Python packages. pip install /python +.. note:: + + The main advantage of Verisock's socket interface is its versatility. The + Python client provided with the code can serve as a reference implementation + that can easily be replicated in any language with an API for TCP sockets. Run the examples ---------------- @@ -138,12 +143,23 @@ have to typically be: variable rising edge), * etc... -.. note:: +.. _sec_alternative_simulators: + +Alternative simulators +********************** - Note that while the Verisocks PLI application has been developed targeting - specifically Icarus as a verilog simulator, there is no known reason that - it would not be working as well with any other simulator that is supporting - the VPI interface standard, including mainstream commercial simulators. I - will gladly accept any contribution that may confirm or infirm this - statement... +While the Verisocks PLI application has been developed targeting specifically +Icarus as a verilog simulator, there is no known reason that it would not be +working as well with any other simulator that is supporting the VPI normative +interface (as defined in `IEEE Std 1364 +`_ and `IEEE Std 1800 +`_), including mainstream +commercial simulators. +.. note:: + I will gladly accept any contribution to test Verisocks with other + simulators. + As of now, I have only successfully tested it with Cadence's XCelium 64 + 29.03. As soon as I get more material, I will make a short tutorial for it. + My next target will be Tachyon's CVC. If anybody is able to test it with + QuestaSim... diff --git a/docs/src/release_notes.rst b/docs/src/release_notes.rst index 00986d0..84d03f2 100644 --- a/docs/src/release_notes.rst +++ b/docs/src/release_notes.rst @@ -11,11 +11,15 @@ version numbering system follows the `semantic versioning 1.1.1 - Ongoing *************** -* Modified :py:meth:`Verisocks.connect() - ` method to include multiple, delayed - connection trials. Examples and test have been simplified accordingly. +* Modified :py:class:`Verisocks` constructor and + :py:meth:`Verisocks.connect() ` method + to include arguments for multiple, delayed connection trials. Examples and + test have been simplified accordingly. * Added correct management of system call interrupts while waiting on client - connection in the server code. + connection in the server code (see + https://www.gnu.org/software/libc/manual/html_node/Interrupted-Primitives.html + for details). +* Added section :ref:`sec_alternative_simulators`. 1.1.0 - 2024-02-07 ******************