lights.syr

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.10 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.10 secs
 
--> Reading design: lights.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lights.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lights"
Output Format                      : NGC
Target Device                      : xc7a100t-3-csg324

---- Source Options
Top Module Name                    : lights
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "\\thayerfs.thayer.dartmouth.edu\f0019x8\ENGS31\Lab3\lights.vhd" into library work
Parsing entity <lights>.
Parsing architecture <Behavioral> of entity <lights>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <lights> (architecture <Behavioral>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lights>.
    Related source file is "\\thayerfs.thayer.dartmouth.edu\f0019x8\ENGS31\Lab3\lights.vhd".
WARNING:Xst:647 - Input <Hazard> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <PS>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <lights> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 2-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 2
 Flip-Flops                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lights> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lights, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2
 Flip-Flops                                            : 2

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : lights.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 2
#      LUT4                        : 2
# FlipFlops/Latches                : 2
#      FD                          : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 4
#      IBUF                        : 2
#      OBUF                        : 2

Device utilization summary:
---------------------------

Selected Device : 7a100tcsg324-3 


Slice Logic Utilization: 
 Number of Slice Registers:               2  out of  126800     0%  
 Number of Slice LUTs:                    2  out of  63400     0%  
    Number used as Logic:                 2  out of  63400     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:      4
   Number with an unused Flip Flop:       2  out of      4    50%  
   Number with an unused LUT:             2  out of      4    50%  
   Number of fully used LUT-FF pairs:     0  out of      4     0%  
   Number of unique control sets:         1

IO Utilization: 
 Number of IOs:                           6
 Number of bonded IOBs:                   5  out of    210     2%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 0.855ns (Maximum Frequency: 1169.454MHz)
   Minimum input arrival time before clock: 0.667ns
   Maximum output required time after clock: 0.650ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 0.855ns (frequency: 1169.454MHz)
  Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay:               0.855ns (Levels of Logic = 1)
  Source:            PS_1 (FF)
  Destination:       PS_1 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: PS_1 to PS_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.361   0.389  PS_1 (PS_1)
     LUT4:I2->O            1   0.097   0.000  PS_0_rstpot (PS_0_rstpot)
     FD:D                      0.008          PS_0
    ----------------------------------------
    Total                      0.855ns (0.466ns logic, 0.389ns route)
                                       (54.5% logic, 45.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Offset:              0.667ns (Levels of Logic = 2)
  Source:            OnOff (PAD)
  Destination:       PS_1 (FF)
  Destination Clock: CLK rising

  Data Path: OnOff to PS_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.001   0.561  OnOff_IBUF (OnOff_IBUF)
     LUT4:I0->O            1   0.097   0.000  PS_0_rstpot (PS_0_rstpot)
     FD:D                      0.008          PS_0
    ----------------------------------------
    Total                      0.667ns (0.106ns logic, 0.561ns route)
                                       (15.9% logic, 84.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              0.650ns (Levels of Logic = 1)
  Source:            PS_0 (FF)
  Destination:       LightL (PAD)
  Source Clock:      CLK rising

  Data Path: PS_0 to LightL
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.361   0.289  PS_0 (PS_0)
     OBUF:I->O                 0.000          LightL_OBUF (LightL)
    ----------------------------------------
    Total                      0.650ns (0.361ns logic, 0.289ns route)
                                       (55.5% logic, 44.5% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    0.855|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.31 secs
 
--> 

Total memory usage is 447008 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)