fuse.log

Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib secureip -o O:/engs31/lab6final2/lab6tb_isim_beh.exe -prj O:/engs31/lab6final2/lab6tb_beh.prj work.lab6tb 
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "O:/engs31/lab6final2/SerialTx.vhd" into library work
Parsing VHDL file "O:/engs31/lab6final2/SerialRX.vhd" into library work
Parsing VHDL file "O:/engs31/lab6final2/mux7seg.vhd" into library work
Parsing VHDL file "O:/engs31/lab6final2/MemoryReceiver.vhd" into library work
Parsing VHDL file "O:/engs31/lab6final2/lab5top.vhd" into library work
Parsing VHDL file "O:/engs31/lab6final2/lab6tb.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package vcomponents
Compiling architecture bufg_v of entity BUFG [bufg_default]
Compiling architecture behavioral of entity SerialRX [serialrx_default]
Compiling architecture behavioral of entity mux7seg [mux7seg_default]
Compiling architecture behavioral of entity SerialTx [serialtx_default]
Compiling architecture behavioral of entity MemoryReceiver [memoryreceiver_default]
Compiling architecture structural of entity lab5top [lab5top_default]
Compiling architecture behavior of entity lab6tb
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 17 VHDL Units
Built simulation executable O:/engs31/lab6final2/lab6tb_isim_beh.exe
Fuse Memory Usage: 48528 KB
Fuse CPU Usage: 795 ms