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Instructionset.txt
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Byte order:
Little endian
Registers:
A, B, C, D 8-bit general purpose regbank
E 8-bit page pointer regbank
IR 8-bit instruction register control unit
PC 16-bit program counter regbank
MR 16-bit address buffer regbank
Flags (1 bit):
Carry, Zero, Sign regbank
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Instruction entry format:
(aa)bbbbbbbb ccc ddd, ... eee fff ggg nnn
a: Decimal value of the first four bits.
b: instruction opcode, full 8-bits with argument bits as letters
if the first 4 bits are not written, they are same as preceeding line(s)
X or XX = 1 or 2 bits to select destination register,
Y or YY = 1 or 2 bits to select modifier or source register,
R or RR = 1 or 2 bits to select register for operation,
F = 1 bit to match against flag register
c: Mnemonic for the instruction
d: arguments for the instruction
e: number of bytes for opcode + arguments
f: number of SYSCLK cycles to execute
g: order of bytes for opcode and arguments
n: extra explanations
Mnemonics for conditional jumps is listed as "Jcc" to cover both variants.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
( 0)00000000 JMP imm16 3 3 OP|IMM_LO8|IMM_HI8 *
0001 MOV imm16, MR 3 3 OP|IMM_LO8|IMM_HI8 Load address into MR
001F Jcc imm16 3 3 OP|IMM_LO8|IMM_HI8 * JNC, JC: if Carry=F
010F Jcc imm16 3 3 OP|IMM_LO8|IMM_HI8 * JNZ, JZ: if Zero=F
011F Jcc imm16 3 3 OP|IMM_LO8|IMM_HI8 * JNS, JS: if Sign=F
* copies PC to MR when jumping
1000 JMP rel8 2 2 OP|REL8
1001 MOV imm8, MR 2 2 OP|IMM8 Load imm8 into MR, zero extended
101F Jcc rel8 2 2 OP|REL8 if Carry=F, JNC, JC
110F Jcc rel8 2 2 OP|REL8 if Zero=F, JNZ, JZ
111F Jcc rel8 2 2 OP|REL8 if Sign=F, JNS, JS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
( 1)000100XX LD [imm16], dst 3 4 OP|IMM_LO8|IMM_HI8 Overwrites MR
01YY ST src, [imm16] 3 4 OP|IMM_LO8|IMM_HI8 Overwrites MR
10XX LD [E:imm8], dst 2 3 OP|IMM8 Overwrites MR
11YY ST src, [E:imm8] 2 3 OP|IMM8 Overwrites MR
( 2)00100RXX LD [E:reg], dst 1 2 OP Reg must be C or D
1RYY ST src, [E:reg] 1 2 OP Reg must be C or D
( 3)0011000X LD [MR], dst 1 2 OP Dst must be A or B
001X LDI [MR], dst 1 2 OP Dst must be A or B
010Y ST src, [MR] 1 2 OP Src must be A or B
011Y STI src, [MR] 1 2 OP Src must be A or B
100X LD [C:D], dst 1 2 OP Dst must be A or B
101X LDI [C:D], dst 1 2 OP Dst must be A or B
110Y ST src, [C:D] 1 2 OP Src must be A or B
111Y STI src, [C:D] 1 2 OP Src must be A or B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
( 4)0100#### ...
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
( 5)010100RR SHR reg 1 1 OP ** Shift 1 bit Right, msb = 0
01RR SHL reg 1 1 OP ** Shift 1 bit Left, lsb = 0
10RR RCR reg 1 1 OP ** Shift 1 bit Right, msb = Carry
11RR RCL reg 1 1 OP ** Shift 1 bit Left, lsb = Carry
** Shifted out bit is stored in Carry
( 6)0110000X MOV E, dst 1 1 OP Dst must be C or D
001Y MOV src, E 1 1 OP Src must be C or D
0100 MOV MR, C:D 1 1 OP
0101 JMP C:D 1 1 OP
0110 JMP MR 1 1 OP
0111 AFX 1 1 OP Swap A<=>Flags
10RR INC reg 1 1 OP
11RR DEC reg 1 1 OP
( 7)0111XXYY XOR mod, dst 1 1 OP XOR is a special case with no IMM8 variant
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
( 8)1000XXYY ADD mod, dst 1 1 OP
ADD imm8, dst 2 2 OP|IMM8 if mod = dst
( 9)1001XXYY AND mod, dst 1 1 OP
AND imm8, dst 2 2 OP|IMM8 if mod = dst
(10)1010XXYY OR mod, dst 1 1 OP
OR imm8, dst 2 2 OP|IMM8 if mod = dst
(11)1011XXYY ADC mod, dst 1 1 OP
ADC imm8, dst 2 2 OP|IMM8 if mod = dst
(12)1100XXYY CMP mod, dst 1 1 OP
CMP imm8, dst 2 2 OP|IMM8 if mod = dst
(13)1101XXYY SUB mod, dst 1 1 OP
SUB imm8, dst 2 2 OP|IMM8 if mod = dst
(14)1110XXYY SBC mod, dst 1 1 OP
SBC imm8, dst 2 2 OP|IMM8 if mod = dst
(15)1111XXYY MOV src, dst 1 1 OP
MOV imm8, dst 2 2 OP|IMM8 if src = dst
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Unmapped/unimplemented instructions/ideas
(may or may not be implemented)
Remaining available opcodes: 33 (out of 256)
00YY ...
01YY SIC reg Set reg to $01 if Carry=1
10YY SIZ reg Set reg to $01 if Zero=1
11YY SIS reg Set reg to $01 if Sign=1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~