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disas.cpp
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//
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2018 Western Digital Corporation or its affiliates.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program. If not, see <https://www.gnu.org/licenses/>.
//
#include <iomanip>
#include <iostream>
#include <sstream>
#include "Hart.hpp"
#include "instforms.hpp"
using namespace WdRiscv;
static
std::string
roundingModeString(RoundingMode mode)
{
switch (mode)
{
case RoundingMode::NearestEven: return "rne";
case RoundingMode::Zero: return "rtz";
case RoundingMode::Down: return "rdn";
case RoundingMode::Up: return "rup";
case RoundingMode::NearestMax: return "rmm";
case RoundingMode::Invalid1: return "inv1";
case RoundingMode::Invalid2: return "inv2";
case RoundingMode::Dynamic: return "dyn";
default: return "inv";
}
return "inv";
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst rd, rs1, rs2
template <typename URV>
static
void
printRdRs1Rs2(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1(), rs2 = di.op2();
// Print instruction in a 9 character field.
stream << std::left << std::setw(9) << inst;
stream << hart.intRegName(rd) << ", " << hart.intRegName(rs1) << ", "
<< hart.intRegName(rs2);
}
/// Helper to disassemble method. Print on the given stream given
/// 2-operand floating point instruction.
template <typename URV>
static
void
printFp2(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
stream << std::left << std::setw(9) << inst << hart.fpRegName(di.op0())
<< ", " << hart.fpRegName(di.op1());
}
/// Helper to disassemble method. Print on the given stream given
/// 3-operand floating point instruction.
template <typename URV>
static
void
printFp3(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
stream << std::left << std::setw(9) << inst << hart.fpRegName(di.op0())
<< ", " << hart.fpRegName(di.op1())
<< ", " << hart.fpRegName(di.op3());
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst rd, rs1
template <typename URV>
static
void
printRdRs1(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
// Print instruction in a 9 character field.
stream << std::left << std::setw(9) << inst;
stream << hart.intRegName(rd) << ", " << hart.intRegName(rs1);
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: csrinst rd, csrn, rs1
template <typename URV>
static
void
printCsr(Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), csrn = di.op2();
stream << std::left << std::setw(9) << inst;
stream << hart.intRegName(rd) << ", ";
auto csr = hart.findCsr(CsrNumber(csrn));
if (csr)
stream << csr->getName();
else
stream << "illegal";
if (di.ithOperandType(1) == OperandType::Imm)
stream << ", 0x" << std::hex << di.op1() << std::dec;
else
stream << ", " << hart.intRegName(di.op1());
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg1, imm(reg2)
template <typename URV>
static
void
printLdSt(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
int32_t imm = di.op2As<int32_t>();
stream << std::left << std::setw(8) << inst << ' ';
const char* sign = imm < 0? "-" : "";
if (imm < 0)
imm = -imm;
// Keep least sig 12 bits.
imm = imm & 0xfff;
stream << hart.intRegName(rd) << ", " << sign << "0x"
<< std::hex << imm << "(" << hart.intRegName(rs1) << ")" << std::dec;
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg1, imm(reg2) where inst
/// is a floating point ld/st instruction.
template <typename URV>
static
void
printFpLdSt(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
int32_t imm = di.op2As<int32_t>();
stream << std::left << std::setw(8) << inst << ' ';
const char* sign = imm < 0? "-" : "";
if (imm < 0)
imm = -imm;
// Keep least sig 12 bits.
imm = imm & 0xfff;
stream << hart.fpRegName(rd) << ", " << sign << "0x" << std::hex << imm
<< std::dec << "(" << hart.intRegName(rs1) << ")";
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg, reg, imm where inst is
/// a shift instruction.
template <typename URV>
static
void
printShiftImm(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
int32_t imm = di.op2As<int32_t>();
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rd) << ", " << hart.intRegName(rs1)
<< ", 0x" << std::hex << imm << std::dec;
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg, reg, imm where imm is
/// a 12 bit constant.
template <typename URV>
static
void
printRegRegImm12(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
int32_t imm = di.op2As<int32_t>();
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rd) << ", " << hart.intRegName(rs1) << ", ";
if (imm < 0)
stream << "-0x" << std::hex << ((-imm) & 0xfff) << std::dec;
else
stream << "0x" << std::hex << (imm & 0xfff) << std::dec;
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg, reg, uimm where uimm is
/// a 12 bit constant.
template <typename URV>
static
void
printRegRegUimm12(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
uint32_t rd = di.op0(), rs1 = di.op1(), imm = di.op2();
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rd) << ", " << hart.intRegName(rs1) << ", ";
stream << "0x" << std::hex << (imm & 0xfff) << std::dec;
}
/// Helper to disassemble method. Print on the given stream given
/// instruction which is of the form: inst reg, imm where inst is a
/// compressed instruction.
template <typename URV>
static
void
printRegImm(const Hart<URV>& hart, std::ostream& stream, const char* inst,
unsigned rs1, int32_t imm)
{
// Print instruction in a 8 character field.
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rs1) << ", ";
if (imm < 0)
stream << "-0x" << std::hex << (-imm) << std::dec;
else
stream << "0x" << std::hex << imm << std::dec;
}
/// Helper to disassemble method. Print on the given stream given 3
/// operand branch instruction which is of the form: inst reg, reg,
/// imm where imm is a 12 bit constant.
template <typename URV>
static
void
printBranch3(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rs1 = di.op0(), rs2 = di.op1();
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rs1) << ", " << hart.intRegName(rs2) << ", . ";
char sign = '+';
int32_t imm = di.op2As<int32_t>();
if (imm < 0)
{
sign = '-';
imm = -imm;
}
stream << sign << " 0x" << std::hex << imm << std::dec;
}
/// Helper to disassemble method. Print on the given stream given
/// 2 operand branch instruction which is of the form: inst reg, imm.
template <typename URV>
static
void
printBranch2(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rs1 = di.op0();
int32_t imm = di.op2As<int32_t>();
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.intRegName(rs1) << ", . ";
char sign = '+';
if (imm < 0)
{
sign = '-';
imm = -imm;
}
stream << sign << " 0x" << std::hex << imm << std::dec;
}
/// Helper to disassemble method.
template <typename URV>
static
void
printAmo(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1(), rs2 = di.op2();
bool aq = di.isAtomicAcquire(), rl = di.isAtomicRelease();
stream << inst;
if (aq)
stream << ".aq";
if (rl)
stream << ".rl";
stream << ' ' << hart.intRegName(rd) << ", " << hart.intRegName(rs2) << ", ("
<< hart.intRegName(rs1) << ")";
}
/// Helper to disassemble method.
template <typename URV>
static
void
printLr(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1();
bool aq = di.isAtomicAcquire(), rl = di.isAtomicRelease();
stream << inst;
if (aq)
stream << ".aq";
if (rl)
stream << ".rl";
stream << ' ' << hart.intRegName(rd) << ", (" << hart.intRegName(rs1) << ")";
}
/// Helper to disassemble method.
template <typename URV>
static
void
printSc(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
unsigned rd = di.op0(), rs1 = di.op1(), rs2 = di.op2();
bool aq = di.isAtomicAcquire(), rl = di.isAtomicRelease();
stream << inst;
if (aq)
stream << ".aq";
if (rl)
stream << ".rl";
stream << ' ' << hart.intRegName(rd) << ", " << hart.intRegName(rs2)
<< ", (" << hart.intRegName(rs1) << ")";
}
/// Helper to disassemble methods. Print a floating point instruction
/// with 4 operands and the rounding mode.
template <typename URV>
static
void
printFp4Rm(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
// Print instruction in a 8 character field.
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.fpRegName(di.op0()) << ", " << hart.fpRegName(di.op1())
<< ", " << hart.fpRegName(di.op2()) << hart.fpRegName(di.op3())
<< ", " << roundingModeString(di.roundingMode());
}
/// Helper to disassemble methods. Print a floating point instruction
/// with 3 operands and the rounding mode.
template <typename URV>
static
void
printFp3Rm(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
// Print instruction in a 8 character field.
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.fpRegName(di.op0()) << ", " << hart.fpRegName(di.op1())
<< ", " << hart.fpRegName(di.op2())
<< ", " << roundingModeString(di.roundingMode());
}
/// Helper to disassemble methods. Print a floating point instruction
/// with 2 operands and the rounding mode.
template <typename URV>
static
void
printFp2Rm(const Hart<URV>& hart, std::ostream& stream, const char* inst,
const DecodedInst& di)
{
// Print instruction in a 8 character field.
stream << std::left << std::setw(8) << inst << ' ';
stream << hart.fpRegName(di.op0()) << ", " << hart.fpRegName(di.op1())
<< ", " << roundingModeString(di.roundingMode());
}
template <typename URV>
void
Hart<URV>::disassembleInst(uint32_t inst, std::ostream& stream)
{
DecodedInst di;
decode(pc_, inst, di);
disassembleInst(di, stream);
}
template <typename URV>
void
Hart<URV>::disassembleInst(uint32_t inst, std::string& str)
{
str.clear();
std::ostringstream oss;
disassembleInst(inst, oss);
str = oss.str();
}
template <typename URV>
void
Hart<URV>::disassembleInst(const DecodedInst& di, std::ostream& out)
{
InstId id = di.instEntry()->instId();
switch(id)
{
case InstId::illegal:
out << "illegal";
break;
case InstId::lui:
printRegImm(*this, out, "lui", di.op0(), di.op1As<int32_t>() >> 12);
break;
case InstId::auipc:
out << "auipc " << intRegName(di.op0())
<< ", 0x" << std::hex << ((di.op1() >> 12) & 0xfffff) << std::dec;
break;
case InstId::jal:
{
if (di.op0() == 0)
out << "j ";
else
out << "jal " << intRegName(di.op0()) << ", ";
char sign = '+';
int32_t imm = di.op1As<int32_t>();
if (imm < 0) { sign = '-'; imm = -imm; }
out << ". " << sign << " 0x" << std::hex << (imm & 0xfffff) << std::dec;
}
break;
case InstId::jalr:
printLdSt(*this, out, "jalr", di);
break;
case InstId::beq:
printBranch3(*this, out, "beq", di);
break;
case InstId::bne:
printBranch3(*this, out, "bne", di);
break;
case InstId::blt:
printBranch3(*this, out, "blt", di);
break;
case InstId::bge:
printBranch3(*this, out, "bge", di);
break;
case InstId::bltu:
printBranch3(*this, out, "bltu", di);
break;
case InstId::bgeu:
printBranch3(*this, out, "bgeu", di);
break;
case InstId::lb:
printLdSt(*this, out, "lb", di);
break;
case InstId::lh:
printLdSt(*this, out, "lh", di);
break;
case InstId::lw:
printLdSt(*this, out, "lw", di);
break;
case InstId::lbu:
printLdSt(*this, out, "lbu", di);
break;
case InstId::lhu:
printLdSt(*this, out, "lhu", di);
break;
case InstId::sb:
printLdSt(*this, out, "sb", di);
break;
case InstId::sh:
printLdSt(*this, out, "sh", di);
break;
case InstId::sw:
printLdSt(*this, out, "sw", di);
break;
case InstId::addi:
printRegRegImm12(*this, out, "addi", di);
break;
case InstId::slti:
printRegRegImm12(*this, out, "slti", di);
break;
case InstId::sltiu:
printRegRegUimm12(*this, out, "sltiu", di);
break;
case InstId::xori:
printRegRegImm12(*this, out, "xori", di);
break;
case InstId::ori:
printRegRegImm12(*this, out, "ori", di);
break;
case InstId::andi:
printRegRegImm12(*this, out, "andi", di);
break;
case InstId::slli:
printShiftImm(*this, out, "slli", di);
break;
case InstId::srli:
printShiftImm(*this, out, "srli", di);
break;
case InstId::srai:
printShiftImm(*this, out, "srai", di);
break;
case InstId::add:
printRdRs1Rs2(*this, out, "add", di);
break;
case InstId::sub:
printRdRs1Rs2(*this, out, "sub", di);
break;
case InstId::sll:
printRdRs1Rs2(*this, out, "sll", di);
break;
case InstId::slt:
printRdRs1Rs2(*this, out, "slt", di);
break;
case InstId::sltu:
printRdRs1Rs2(*this, out, "sltu", di);
break;
case InstId::xor_:
printRdRs1Rs2(*this, out, "xor", di);
break;
case InstId::srl:
printRdRs1Rs2(*this, out, "srl", di);
break;
case InstId::sra:
printRdRs1Rs2(*this, out, "sra", di);
break;
case InstId::or_:
printRdRs1Rs2(*this, out, "or", di);
break;
case InstId::and_:
printRdRs1Rs2(*this, out, "and", di);
break;
case InstId::fence:
out << "fence";
break;
case InstId::fencei:
out << "fencei";
break;
case InstId::ecall:
out << "ecall";
break;
case InstId::ebreak:
out << "ebreak";
break;
case InstId::csrrw:
printCsr(*this, out, "csrrw", di);
break;
case InstId::csrrs:
printCsr(*this, out, "csrrs", di);
break;
case InstId::csrrc:
printCsr(*this, out, "csrrc", di);
break;
case InstId::csrrwi:
printCsr(*this, out, "csrrwi", di);
break;
case InstId::csrrsi:
printCsr(*this, out, "csrrsi", di);
break;
case InstId::csrrci:
printCsr(*this, out, "csrrci", di);
break;
case InstId::lwu:
printLdSt(*this, out, "lwu", di);
break;
case InstId::ld:
printLdSt(*this, out, "ld", di);
break;
case InstId::sd:
printLdSt(*this, out, "sd", di);
break;
case InstId::addiw:
printRegRegImm12(*this, out, "addiw", di);
break;
case InstId::slliw:
printShiftImm(*this, out, "slliw", di);
break;
case InstId::srliw:
printShiftImm(*this, out, "srliw", di);
break;
case InstId::sraiw:
printShiftImm(*this, out, "sraiw", di);
break;
case InstId::addw:
printRdRs1Rs2(*this, out, "addw", di);
break;
case InstId::subw:
printRdRs1Rs2(*this, out, "subw", di);
break;
case InstId::sllw:
printRdRs1Rs2(*this, out, "sllw", di);
break;
case InstId::srlw:
printRdRs1Rs2(*this, out, "srlw", di);
break;
case InstId::sraw:
printRdRs1Rs2(*this, out, "sraw", di);
break;
case InstId::mul:
printRdRs1Rs2(*this, out, "mul", di);
break;
case InstId::mulh:
printRdRs1Rs2(*this, out, "mulh", di);
break;
case InstId::mulhsu:
printRdRs1Rs2(*this, out, "mulhsu", di);
break;
case InstId::mulhu:
printRdRs1Rs2(*this, out, "mulhu", di);
break;
case InstId::div:
printRdRs1Rs2(*this, out, "div", di);
break;
case InstId::divu:
printRdRs1Rs2(*this, out, "divu", di);
break;
case InstId::rem:
printRdRs1Rs2(*this, out, "rem", di);
break;
case InstId::remu:
printRdRs1Rs2(*this, out, "remu", di);
break;
case InstId::mulw:
printRdRs1Rs2(*this, out, "mulw", di);
break;
case InstId::divw:
printRdRs1Rs2(*this, out, "divw", di);
break;
case InstId::divuw:
printRdRs1Rs2(*this, out, "divuw", di);
break;
case InstId::remw:
printRdRs1Rs2(*this, out, "remw", di);
break;
case InstId::remuw:
printRdRs1Rs2(*this, out, "remuw", di);
break;
case InstId::lr_w:
printLr(*this, out, "lr.w", di);
break;
case InstId::sc_w:
printSc(*this, out, "sc.w", di);
break;
case InstId::amoswap_w:
printAmo(*this, out, "amoswap.w", di);
break;
case InstId::amoadd_w:
printAmo(*this, out, "amoadd.w", di);
break;
case InstId::amoxor_w:
printAmo(*this, out, "amoxor.w", di);
break;
case InstId::amoand_w:
printAmo(*this, out, "amoand.w", di);
break;
case InstId::amoor_w:
printAmo(*this, out, "amoor.w", di);
break;
case InstId::amomin_w:
printAmo(*this, out, "amomin.w", di);
break;
case InstId::amomax_w:
printAmo(*this, out, "amomax.w", di);
break;
case InstId::amominu_w:
printAmo(*this, out, "amominu.w", di);
break;
case InstId::amomaxu_w:
printAmo(*this, out, "amomaxu.w", di);
break;
case InstId::lr_d:
printLr(*this, out, "lr.d", di);
break;
case InstId::sc_d:
printSc(*this, out, "sc.d", di);
break;
case InstId::amoswap_d:
printAmo(*this, out, "amoswap.d", di);
break;
case InstId::amoadd_d:
printAmo(*this, out, "amoadd.d", di);
break;
case InstId::amoxor_d:
printAmo(*this, out, "amoxor.d", di);
break;
case InstId::amoand_d:
printAmo(*this, out, "amoand.d", di);
break;
case InstId::amoor_d:
printAmo(*this, out, "amoor.d", di);
break;
case InstId::amomin_d:
printAmo(*this, out, "amomin.d", di);
break;
case InstId::amomax_d:
printAmo(*this, out, "amomax.d", di);
break;
case InstId::amominu_d:
printAmo(*this, out, "amominu.d", di);
break;
case InstId::amomaxu_d:
printAmo(*this, out, "amomaxu.d", di);
break;
case InstId::flw:
printFpLdSt(*this, out, "flw", di);
break;
case InstId::fsw:
printFpLdSt(*this, out, "fsw", di);
break;
case InstId::fmadd_s:
printFp4Rm(*this, out, "fmadd.s", di);
break;
case InstId::fmsub_s:
printFp4Rm(*this, out, "fmsub.s", di);
break;
case InstId::fnmsub_s:
printFp4Rm(*this, out, "fnmsub.s", di);
break;
case InstId::fnmadd_s:
printFp4Rm(*this, out, "fnmadd.s", di);
break;
case InstId::fadd_s:
printFp2Rm(*this, out, "fadd.s", di);
break;
case InstId::fsub_s:
printFp2Rm(*this, out, "fsub.s", di);
break;
case InstId::fmul_s:
printFp2Rm(*this, out, "fmul.s", di);
break;
case InstId::fdiv_s:
printFp2Rm(*this, out, "fdiv.s", di);
break;
case InstId::fsqrt_s:
printFp2(*this, out, "fsqrt.s", di);
break;
case InstId::fsgnj_s:
printFp2(*this, out, "fsgnj.s", di);
break;
case InstId::fsgnjn_s:
printFp2(*this, out, "fsgnjn.s", di);
break;
case InstId::fsgnjx_s:
printFp2(*this, out, "fsgnjx.s", di);
break;
case InstId::fmin_s:
printFp3(*this, out, "fmin.s", di);
break;
case InstId::fmax_s:
printFp3(*this, out, "fmax.s", di);
break;
case InstId::fcvt_w_s:
out << "fcvt.w.s " << intRegName(di.op0()) << ", "
<< fpRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fcvt_wu_s:
out << "fcvt.wu.s " << intRegName(di.op0()) << ", "
<< fpRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fmv_x_w:
out << "fmv.x.w " << intRegName(di.op0()) << ", " << fpRegName(di.op1());
break;
case InstId::feq_s:
out << "feq.s " << intRegName(di.op0()) << ", " << fpRegName(di.op1())
<< ", " << fpRegName(di.op2());
break;
case InstId::flt_s:
out << "flt.s " << intRegName(di.op0()) << ", " << fpRegName(di.op1())
<< ", " << fpRegName(di.op2());
break;
case InstId::fle_s:
out << "fle.s " << intRegName(di.op0()) << ", " << fpRegName(di.op1())
<< ", " << fpRegName(di.op2());
break;
case InstId::fclass_s:
out << "fclass.s " << intRegName(di.op0()) << ", " << fpRegName(di.op1());
break;
case InstId::fcvt_s_w:
out << "fcvt.s.w " << ", " << fpRegName(di.op0()) << ", "
<< intRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fcvt_s_wu:
out << "fcvt.s.wu " << fpRegName(di.op0()) << ", "
<< intRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fmv_w_x:
out << "fmv.w.x "<< ", " << fpRegName(di.op0())
<< ", " << intRegName(di.op1());
break;
case InstId::fcvt_l_s:
out << "fcvt.l.s " << intRegName(di.op0()) << ", "
<< fpRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fcvt_lu_s:
out << "fcvt.lu.s " << intRegName(di.op0()) << ", "
<< fpRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fcvt_s_l:
out << "fcvt.s.l " << ", " << fpRegName(di.op0()) << ", "
<< intRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fcvt_s_lu:
out << "fcvt.s.lu " << fpRegName(di.op0()) << ", "
<< intRegName(di.op1()) << ", "
<< roundingModeString(di.roundingMode());
break;
case InstId::fld:
printFpLdSt(*this, out, "fld", di);
break;