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config.toml
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# Author: Jude de Villiers
# Origin: E&E Engineering - Stellenbosch University
# For: Supertools, Coldflux Project - IARPA
# Created: 2019-05-09
# Modified:
# license:
# Description: Configuration file for defining stuffs
# File: config.toml
[PARAMETERS]
time_step = 0.1 # Time step in picoseconds(ps)
time_duration = 3100.0 # Time duration in picoseconds(ps)
speedConstant = 95.1 # um / ps
dangling_net_name = "0"
force_PTL_Length = false
force_PTL_length_value = 100000.0 # sets a fixed track length
input_name_keys = ["IN", "In", "in", "a", "b", "A", "B"]
output_names_keys = ["SUM", "Sum", "sum", "OUT", "Out", "out", "q", "m"] # Primarily used
clock_names_keys = ["CLK", "Clk", "clk", "CLOCK", "Clock", "clock"]
topModuleName = "KSA4"
timescale = "1ps/100fs"
[INPUT_PATTERN] # Input pattern/parameters
clock_freq = 15.0 # [GHz] [float]
input_peak = 600 # [uA] [integer]
input_peak_time = 1000 # [ps] [integer]
type = 'random' # {vecfile,random,exhaustive}
vec_file_path = '/home/edrich/asdf.txt' # vecfile path
seed = 100 # the seed to give to a RNG for reproduceability
num_random = 100 # the amount of random patterns to test
ac_delay = 66 # time delay (ps) after clock pulse to wait before inserting pattern
bp_delay = 1 # number of clock pulses between test patterns
[VERILOG_MODULE_LOCATIONS]
LSmitll_JTLT = "data/modules/LSmitll_JTLT_v2p1_selfcontained.v"
LSmitll_MERGET = "data/modules/LSmitll_MERGET_v2p1_selfcontained.v"
LSmitll_SPLITT = "data/modules/LSmitll_SPLITT_v2p1_selfcontained.v"
LSmitll_DFFT = "data/modules/LSmitll_DFFT_v2p1_selfcontained.v"
LSmitll_NOTT = "data/modules/LSmitll_NOTT_v2p1_selfcontained.v"
LSmitll_AND2T = "data/modules/LSmitll_AND2T_v2p1_selfcontained.v"
LSmitll_OR2T = "data/modules/LSmitll_OR2T_v2p1_selfcontained.v"
LSmitll_XORT = "data/modules/LSmitll_XORT_v2p1_selfcontained.v"
LSmitll_buff = "data/modules/LSmitll_BUFFT_v2p1_selfcontained.v"
LSmitll_CLKSPLIT = "data/modules/LSmitll_SPLITT_v2p1_selfcontained.v"
[NETLIST_LOCATIONS]
LSmitll_AND2T = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_AND2T_v1p5.cir"
LSmitll_bufft = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_bufft_v1p5.cir"
LSmitll_buff = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_buff_v1p5.cir"
LSMITLL_CLKSPLTT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_CLKSPLTT_v1p5.cir"
LSMITLL_CLKSPLT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_CLKSPLT_v1p5.cir"
LSmitll_DCSFQ_PTLTX = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_DCSFQ_PTLTX_v1p5.cir"
LSmitll_DCSFQ = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_DCSFQ_v1p5.cir"
LSmitll_DFFT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_DFFT_v1p5.cir"
LSmitll_JTLT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_JTLT_v1p5.cir"
LSmitll_MERGET = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_MERGET_v1p5.cir"
LSmitll_NDROT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_NDROT_v1p5.cir"
LSmitll_NOTT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_NOTT_v1p5.cir"
LSmitll_OR2T = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_OR2T_v1p5.cir"
LSmitll_PTLRX_SFQDC = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_PTLRX_SFQDC_v1p5.cir"
LSmitll_PLTRX = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_ptlrx_v1p5.cir"
LSmitll_PLTTX = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_ptltx_v1p5.cir"
LSmitll_SFQDC = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_SFQDC_v1p5.cir"
LSmitll_SPLITT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_SPLITT_v1p5.cir"
LSmitll_XORT = "data/cell_lib/RSFQ_LS_MITLL_v1p5p1/LSmitll_XORT_v1p5.cir"
# The arrays shows the pins of the cells for the SPICE sub-circuits.
# The order of the pins/ports are important due to mapping
[GATE_NETLIST]
LSmitll_AND2T = ["a", "b", "clk", "q"]
LSmitll_DCSFQ = ["a", "q"]
LSmitll_DFFT = ["a", "clk", "q"]
LSmitll_JTLT = ["a", "q"]
LSmitll_MERGET = ["a", "b", "q"]
LSmitll_NDROT = ["a", "b", "clk", "q"] # a - IN_SET; b - IN_RESET
LSmitll_NOTT = ["a", "clk", "q"]
LSmitll_OR2T = ["a", "b", "clk", "q"]
LSmitll_SPLITT = ["a", "q", "m"]
LSmitll_XORT = ["a", "b", "clk", "q"]
PAD = ["P1"] # does NOT EXIST, used for mapping in/out pins
LSmitll_bufft = ["a", "q"]
LSmitll_buff = ["a", "q"]
LSMITLL_CLKSPLTT = ["a", "q", "m"]
LSMITLL_CLKSPLT = ["a", "q", "m"]
LSmitll_DCSFQ_PTLTX = ["a", "q"]
LSmitll_PTLRX_SFQDC = ["a", "q"]
LSmitll_SFQDC = ["a", "q"]
[TRANSLATION_TABLE]
#############################################
#################### SUN ####################
#############################################
JTLT = "LSmitll_JTLT"
MERGET = "LSmitll_MERGET"
SPLIT = "LSmitll_SPLITT"
DFF = "LSmitll_DFFT"
NOTT = "LSmitll_NOTT"
AND2T = "LSmitll_AND2T"
OR2T = "LSmitll_OR2T"
XOR2T = "LSmitll_XORT"
PAD = "PAD"
CLKBUFF = "LSmitll_buff"
CLKSPLIT = "LSMITLL_CLKSPLTT"
# Pins
INOUT_1 = "P1" # just for pads
IN_1 = "a"
IN_2 = "b"
OUT_1 = "q"
OUT_2 = "m"
CLK = "clk"
# DCSFQ = "LSmitll_DCSFQ"
# NDROT = "LSmitll_NDROT"
# bufft = "LSmitll_bufft"
# buff = "LSmitll_buff"
# CLKSPLTT = "LSMITLL_CLKSPLTT"
# CLKSPLT = "LSMITLL_CLKSPLT"
# DCSFQ_PTLTX = "LSmitll_DCSFQ_PTLTX"
# PTLRX_SFQDC = "LSmitll_PTLRX_SFQDC"
# SFQDC = "LSmitll_SFQDC"
#############################################
#################### USC ####################
#############################################
# AND2 = "LSmitll_AND2T"
# # DCSFQT = "LSmitll_DCSFQ"
# DFF = "LSmitll_DFFT"
# JTLT = "LSmitll_JTLT"
# Merge = "LSmitll_MERGET"
# # NDROT = "LSMITLL_NDROT"
# NOT = "LSmitll_NOTT"
# OR2 = "LSmitll_OR2T"
# # SFQDCT = "LSmitll_SFQDC1"
# XOR2a = "LSmitll_XORT"
# SPLITT = "LSmitll_SPLITT"
# SPLITCLK0 = "LSmitll_SPLITT"
# SPLITCLK1 = "LSmitll_SPLITT"
# SPLITCLK2 = "LSmitll_SPLITT"
# SPLITCLK3 = "LSmitll_SPLITT"
# SPLITCLK4 = "LSmitll_SPLITT"
# SPLITCLK5 = "LSmitll_SPLITT"
# SPLITCLK6 = "LSmitll_SPLITT"
# SPLITCLK7 = "LSmitll_SPLITT"
# SPLITTER = "LSmitll_SPLITT"
# IN_A = "a"
# IN_B = "b"
# OUT_OUT = "q"
# IN_CLK = "clk"
# IN_SET = "a"
# OUT_CLK1 = "q"
# OUT_CLK2 = "r"
# OUT_OUT1 = "q"
# OUT_OUT2 = "r"
# IN_IN = "a"
# PAD = "PAD"
# P1 = "P1"