JTAG_BoundaryScan Debug.cfg

# This is an STM32_JTAG board with a single STM32F103C8Tx chip
#
# Generated by System Workbench for STM32
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)

source [find interface/stlink.cfg]

set WORKAREASIZE 0x5000

transport select "hla_swd"

set CHIPNAME STM32F103C8Tx
set BOARDNAME STM32_JTAG

# CHIPNAMES state
set CHIPNAME_CPU0_ACTIVATED 1

# Enable debug when in low power modes
set ENABLE_LOW_POWER 1

# Stop Watchdog counters when halt
set STOP_WATCHDOG 1

# STlink Debug clock frequency
set CLOCK_FREQ 8000

# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1

# BCTM CPU variables



source [find target/stm32f1x.cfg]