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spec

  • For the full microarchitecture specification, read ARCH.md.
  • For the full instruction set specification, read ISA.md.
  • For detailed instruction information, refer to the manual pages in inst/.

Instructions

Below is a directory is all currently supported instructions. They are divided into four categories:

  • Alias: alternate name and interface for another instruction.
  • Base: a common implementation for a group of instruction variants; cannot use directly.
  • Core: an instruction whose operation is directly implemented; may have variants.
  • Pseudo: an instruction implemented via another; a shorthand.
  • Variant: a variation on another instruction.

Only core instructions have their own designated opcode. Variants are implemented within the namespace of their corresponding core instruction.

Instruction Description Type
ADD Arithmetic Add Core
AND Logical AND Core
ASL Arithmetic Shift Left Variant
ASR Arithmetic Shift Right Variant
BRA Branch Base
CALL Call (branch + link) Variant
CMN Compare by ADD Variant
CMP Compare by SUB Core
GOTO Goto (branch) Alias
HLT Halt Core
IFF Conditional If Core
LDR Load Core
LSL Logical Shift Left Variant
LSR Logical Shift Right Variant
MOV Move Core
MUL Arithmetic Multiply Core
NEG Arithmetic Negate Variant
NOP No Operation Pseudo
NOT Logical NOT Variant
ORR Logical OR Core
POP Pop Register Variant
PUSH Push Register Variant
RSB Reverse SUB Variant
ROL Rotate Left Variant
ROR Rotate Right Variant
SHF Shift Base
STR Store Core
SUB Arithmetic Subtract Core
SYS System (reserved) Core
TEQ Compare by XOR Variant
TST Compare by AND Variant
XOR Logical XOR Core

Registers

Register Alias Use Responsibility
R0 A0 Argument 0 —
R1 A1 Argument 1 —
R2 A2 Argument 2 —
R3 A3 Argument 3 —
R4...R12 G0...G8 General Purpose Callee
R13 SP Stack Pointer Callee
R14 LR Link Register Caller
R15 PC Program Counter —
— SR Status Register —

Argument Registers

While the argument registers do not hold any specific meaning to the processor itself, it is the convention of LANv1 that arguments to procedures be placed in the argument registers, A0 to A3, also knows as R0 to R3. Callers of a procedure cannot expect data to remain within these registers after the procedure completes. Additionally, the argument registers may optionally be used to return data from a procedure. This should be outlined specifically in by the procedure's author.

General Registers

The general registers, G0 to G8, also known as R4 to R12, do not have any special use. Rather, as general purpose registers their usage within a program is up to the programmer. It is important to note that if they are modified within in a procedure, the previous values must be restored by the callee before returning. To easily save and restored a register's value, use the PUSH and POP instructions respectively.

Stack Pointer

The stack pointer (SP), also known as R13, tracks the bottom of the hardware stack. When calling a procedure, the callee is responsible for restoring the stack pointer to its previous value.

Link Register

The link register (LR), also known as R14, holds the return address to branch to after a procedure. Before calling a procedure, the caller is responsible for setting the link register to the desired return address (usually the program counter). This allows the procedure to know where to return to, which can be accomplished with an instruction such as B LR. This can be handled by calling the BL instruction to perform a branch and link.

Program Counter

The program counter (PC), also known as R15, performs one of the most important functions of any register: it keeps track of the current instruction within the running program, and increments ("counts") to the next instruction every cycle. While it can be written to as with any other register, it is typically only modified by the programmer through the BRA family of instructions.

Status Register

The status register (SR) is responsible for maintaining current status of the processor, and is different from other registers in several regards. Unlike any of the numbered registers, the status register is not addressable by the processor; this means it cannot be read or modified directly. Rather, it is updated automatically to reflect the current processor status. Several instructions update the condition code flags, which are read by conditional BRA instructions.

Layout:

│15           4│ 3 │ 2 │ 1 │ 0 │
┌──────────────┬───┬───┬───┬───┐
│ ------------ │ C │ V │ N │ Z │
└──────────────┴───┴───┴───┴───┘

Legend:

Format Use
C Carry flag
N Negative flag
V Overflow flag
Z Zero flag
- Unused