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irsnd.cpp
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/*---------------------------------------------------------------------------------------------------------------------------------------------------
* @file irsnd.c
*
* Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de
*
* Supported AVR mikrocontrollers:
*
* ATtiny87, ATtiny167
* ATtiny45, ATtiny85
* ATtiny44 ATtiny84
* ATtiny2313 ATtiny4313
* ATmega8, ATmega16, ATmega32
* ATmega162
* ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P
* ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P
*
* $Id: irsnd.c,v 1.103 2017/02/17 09:13:06 fm Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
#include "irsnd.h"
#ifndef F_CPU
# error F_CPU unkown
#endif
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* ATtiny pin definition of OC0A / OC0B
* ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7
# if IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 2
# elif IRSND_OCx == IRSND_OC0B // OC0B
# define IRSND_PORT_LETTER A
# define IRSND_BIT_NUMBER 7
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1
# if IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 0
# elif IRSND_OCx == IRSND_OC0B // OC0B
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 1
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny4313__) // ATtiny2313/4313 uses OC0A = PB2 or OC0B = PD5
# if IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 2
# elif IRSND_OCx == IRSND_OC0B // OC0B
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 5
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2
# if IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER A
# define IRSND_BIT_NUMBER 2
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3
# if IRSND_OCx == IRSND_OC2 // OC2
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 3
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC0 = PB3 or OC2 = PD7
# if IRSND_OCx == IRSND_OC2 // OC2
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 7
# elif IRSND_OCx == IRSND_OC0 // OC0
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 3
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0
# if IRSND_OCx == IRSND_OC2 // OC2
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 1
# elif IRSND_OCx == IRSND_OC0 // OC0
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 0
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega164__) \
|| defined (__AVR_ATmega324__) \
|| defined (__AVR_ATmega644__) \
|| defined (__AVR_ATmega644P__) \
|| defined (__AVR_ATmega1284__) \
|| defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4
# if IRSND_OCx == IRSND_OC2A // OC2A
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 7
# elif IRSND_OCx == IRSND_OC2B // OC2B
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 6
# elif IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 3
# elif IRSND_OCx == IRSND_OC0B // OC0B
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 4
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega48__) \
|| defined (__AVR_ATmega88__) \
|| defined (__AVR_ATmega88P__) \
|| defined (__AVR_ATmega168__) \
|| defined (__AVR_ATmega168P__) \
|| defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5
# if IRSND_OCx == IRSND_OC2A // OC2A
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 3
# elif IRSND_OCx == IRSND_OC2B // OC2B
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 3
# elif IRSND_OCx == IRSND_OC0A // OC0A
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 6
# elif IRSND_OCx == IRSND_OC0B // OC0B
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 5
# else
# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2
# if IRSND_OCx == IRSND_OC0
# define IRSND_PORT_LETTER B
# define IRSND_BIT_NUMBER 0
# elif IRSND_OCx == IRSND_OC1A
# define IRSND_PORT_LETTER D
# define IRSND_BIT_NUMBER 5
# elif IRSND_OCx == IRSND_OC1B
# define IRSND_PORT_LETTER E
# define IRSND_BIT_NUMBER 2
# endif // IRSND_OCx
#elif defined (__AVR_XMEGA__) // ATxmega
# if IRSND_OCx == IRSND_XMEGA_OC0A
# define IRSND_BIT_NUMBER 0
# elif IRSND_OCx == IRSND_XMEGA_OC0B
# define IRSND_BIT_NUMBER 1
# elif IRSND_OCx == IRSND_XMEGA_OC0C
# define IRSND_BIT_NUMBER 2
# elif IRSND_OCx == IRSND_XMEGA_OC0D
# define IRSND_BIT_NUMBER 3
# elif IRSND_OCx == IRSND_XMEGA_OC1A
# define IRSND_BIT_NUMBER 4
# elif IRSND_OCx == IRSND_XMEGA_OC1B
# define IRSND_BIT_NUMBER 5
# else
# error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h
# endif // IRSND_OCx
#elif defined (PIC_C18) // Microchip C18 compiler
//Nothing here to do here -> See irsndconfig.h
#elif defined (ARM_STM32) // STM32
//Nothing here to do here -> See irsndconfig.h
#elif defined (__xtensa__) // ESP8266
//Nothing here to do here -> See irsndconfig.h
#elif defined(BOARD_generic_stm32f103c)
//Nothing here to do here -> See irsndconfig.h
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* Macro digitalPinHasPWM bothers PIC_C18 compiler, but why?
*
* #elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3
* # if !digitalPinHasPWM(IRSND_PIN)
* # error need pin with PWM output.
* # endif
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
#else
# if !defined (unix) && !defined (WIN32)
# error mikrocontroller not defined, please fill in definitions here.
# endif // unix, WIN32
#endif // __AVR...
#if defined(__AVR_XMEGA__)
# define _CONCAT(a,b) a##b
# define CONCAT(a,b) _CONCAT(a,b)
# define IRSND_PORT IRSND_PORT_PRE.OUT
# define IRSND_DDR IRSND_PORT_PRE.DIR
# define IRSND_PIN IRSND_PORT_PRE.IN
# define IRSND_BIT IRSND_BIT_NUMBER
#elif defined(ATMEL_AVR)
# define _CONCAT(a,b) a##b
# define CONCAT(a,b) _CONCAT(a,b)
# define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)
# define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)
# define IRSND_BIT IRSND_BIT_NUMBER
#endif
#if IRSND_SUPPORT_NIKON_PROTOCOL == 1
typedef uint16_t IRSND_PAUSE_LEN;
#else
typedef uint8_t IRSND_PAUSE_LEN;
#endif
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* IR timings
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
#define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)
#define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)
#define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)
#define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)
#define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)
#define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)
#define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)
#define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)
#define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)
#define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)
#define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)
#define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)
#define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)
#define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)
#define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)
#define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)
#define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)
#define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)
#define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)
#define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)
#define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)
#define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)
#define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)
#define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)
#define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)
#define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)
#define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)
#define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)
#define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)
#define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)
#define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define MITSU_HEAVY_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PULSE_TIME + 0.5)
#define MITSU_HEAVY_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PAUSE_TIME + 0.5)
#define MITSU_HEAVY_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_PULSE_TIME + 0.5)
#define MITSU_HEAVY_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_1_PAUSE_TIME + 0.5)
#define MITSU_HEAVY_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_0_PAUSE_TIME + 0.5)
#define MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MITSU_HEAVY_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)
#define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)
#define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)
#define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)
#define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)
#define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
#define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
#define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)
#define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)
#define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)
#define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)
#define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)
#define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)
#define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)
#define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)
#define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)
#define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)
#define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)
#define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)
#define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)
#define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)
#define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)
#define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)
#define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)
#define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)
#define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)
#define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)
#define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)
#define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)
#define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)
#define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)
#define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)
#define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)
#define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)
#define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)
#define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)
#define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)
#define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)
#define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)
#define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)
#define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)
#define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)
#define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)
#define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)
#define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)
#define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)
#define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)
#define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)
#define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)
#define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)
#define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)
#define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)
#define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)
#define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)
#define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)
#define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)
#define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)
#define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)
#define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
#define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
#define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
#define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
#define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)
#define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
#define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)
#define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#ifdef PIC_C18 // PIC C18
# define IRSND_FREQ_TYPE uint8_t
# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
#elif defined (ARM_STM32) // STM32
# define IRSND_FREQ_TYPE uint32_t
# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
#elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
# define IRSND_FREQ_TYPE float
# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
#elif defined (__xtensa__) || defined (BOARD_generic_stm32f103c) // ESP8266
# define IRSND_FREQ_TYPE float
# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
#else // AVR
# if F_CPU >= 16000000L
# define AVR_PRESCALER 8
# else
# define AVR_PRESCALER 1
# endif
# define IRSND_FREQ_TYPE uint8_t
# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)
#endif
#define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)
#define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)
#define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)
#define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)
#define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)
#define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)
#define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)
#define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)
#define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)
#define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)
#define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)
#define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)
#define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)
#define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)
#define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)
#define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)
#define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)
#define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)
#define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)
#define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)
#define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)
#define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)
#define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)
#define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)
#define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)
#define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)
#define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)
#define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)
#define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)
#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)
#define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)
#define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)
#define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)
#define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)
#define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)
#define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)
#define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)
#define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)
#define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)
#define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)
#define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
#define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)
#define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)
#define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)
#define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)
#define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)
#define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)
#define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
static volatile uint8_t irsnd_busy = 0;
static volatile uint8_t irsnd_protocol = 0;
static volatile uint8_t irsnd_buffer[11] = {0};
static volatile uint8_t irsnd_repeat = 0;
static volatile uint8_t irsnd_is_on = FALSE;
#if IRSND_USE_CALLBACK == 1
static void (*irsnd_callback_ptr) (uint8_t);
#endif // IRSND_USE_CALLBACK == 1
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* Switch PWM on
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
static void
irsnd_on (void)
{
if (! irsnd_is_on)
{
#ifndef ANALYZE
# if defined(PIC_C18) // PIC C18
PWMon();
// IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)
# elif defined (ARM_STM32) // STM32
TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode
TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter
# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%
# elif defined (__xtensa__) // ESP8266 (Arduino)
analogWrite(IRSND_PIN, 33 * 1023 / 100); // pwm 33%
# elif defined (BOARD_generic_stm32f103c) // ESP8266 (Arduino)
analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%
# elif defined (__AVR_XMEGA__)
# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A
# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B
# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C
# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D
# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A
# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B
# else
# error wrong value of IRSND_OCx
# endif // IRSND_OCx
# else // AVR
# if IRSND_OCx == IRSND_OC2 // use OC2
TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2
# elif IRSND_OCx == IRSND_OC2A // use OC2A
TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A
# elif IRSND_OCx == IRSND_OC2B // use OC2B
TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)
# elif IRSND_OCx == IRSND_OC0 // use OC0
TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0
# elif IRSND_OCx == IRSND_OC0A // use OC0A
TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A
# elif IRSND_OCx == IRSND_OC0B // use OC0B
TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)
# else
# error wrong value of IRSND_OCx
# endif // IRSND_OCx
# endif // C18
#endif // ANALYZE
#if IRSND_USE_CALLBACK == 1
if (irsnd_callback_ptr)
{
(*irsnd_callback_ptr) (TRUE);
}
#endif // IRSND_USE_CALLBACK == 1
irsnd_is_on = TRUE;
}
}
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* Switch PWM off
* @details Switches PWM off
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
static void
irsnd_off (void)
{
if (irsnd_is_on)
{
#ifndef ANALYZE
# if defined(PIC_C18) // PIC C18
PWMoff();
// IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)
# elif defined (ARM_STM32) // STM32
TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter
TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive
TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
TIM_SetCounter(IRSND_TIMER, 0); // reset counter value
# elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
analogWrite(IRSND_PIN, 0); // pwm off, LOW level
# elif defined (__xtensa__) || defined (BOARD_generic_stm32f103c) // ESP8266
analogWrite(IRSND_PIN, 0); // pwm off, LOW level
# elif defined (__AVR_XMEGA__)
# if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected
# elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected
# elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected
# elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected
# elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected
# elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected
# else
# error wrong value of IRSND_OCx
# endif // IRSND_OCx
# else //AVR
# if IRSND_OCx == IRSND_OC2 // use OC2
TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.
# elif IRSND_OCx == IRSND_OC2A // use OC2A
TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.
# elif IRSND_OCx == IRSND_OC2B // use OC2B
TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.
# elif IRSND_OCx == IRSND_OC0 // use OC0
TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.
# elif IRSND_OCx == IRSND_OC0A // use OC0A
TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.
# elif IRSND_OCx == IRSND_OC0B // use OC0B
TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.
# else
# error wrong value of IRSND_OCx
# endif // IRSND_OCx
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
# endif //C18
#endif // ANALYZE
#if IRSND_USE_CALLBACK == 1
if (irsnd_callback_ptr)
{
(*irsnd_callback_ptr) (FALSE);
}
#endif // IRSND_USE_CALLBACK == 1
irsnd_is_on = FALSE;
}
}
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* Set PWM frequency
* @details sets pwm frequency
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
#if defined(__12F1840)
extern void pwm_init(uint16_t freq);
#include <stdio.h>
#endif
static void
irsnd_set_freq (IRSND_FREQ_TYPE freq)
{
#ifndef ANALYZE
# if defined(PIC_C18) // PIC C18 or XC8
# if defined(__12F1840) // XC8
TRISA2=0;
PR2=freq;
CCP1M0=1;
CCP1M1=1;
CCP1M2=1;
CCP1M3=1;
DC1B0=1;
DC1B1=0;
CCPR1L = 0b01101001;
TMR2IF = 0;
TMR2ON=1;
CCP1CON &=(~0b0011); // p 197 "active high"
# else // PIC C18
OpenPWM(freq);
SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%
# endif
PWMoff();
# elif defined (ARM_STM32) // STM32
static uint32_t TimeBaseFreq = 0;
if (TimeBaseFreq == 0)
{
RCC_ClocksTypeDef RCC_ClocksStructure;
/* Get system clocks and store timer clock in variable */
RCC_GetClocksFreq(&RCC_ClocksStructure);
# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)
{
TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;
}
else
{
TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;
}
# else
if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)
{
TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;
}
else
{
TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;
}
# endif
}
freq = TimeBaseFreq/freq;
/* Set frequency */
TIM_SetAutoreload(IRSND_TIMER, freq - 1);
/* Set duty cycle */
TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);
# elif defined (TEENSY_ARM_CORTEX_M4)
analogWriteResolution(8); // 8 bit
analogWriteFrequency(IRSND_PIN, freq);
analogWrite(IRSND_PIN, 0); // pwm off, LOW level
#elif defined (__xtensa__)
// analogWriteRange(255);
analogWriteFreq(freq);
analogWrite(IRSND_PIN, 0); // pwm off, LOW level
#elif defined (BOARD_generic_stm32f103c)
timer_init(IRSND_TIMER_NUMBER);
timer_pause(IRSND_TIMER_NUMBER);
timer_set_mode(IRSND_TIMER_NUMBER, IRSND_TIMER_CHANNEL_NUMBER, TIMER_OUTPUT_COMPARE);
timer_set_prescaler(IRSND_TIMER_NUMBER, ((F_CPU / freq)/8) - 1);
timer_set_reload(IRSND_TIMER_NUMBER, 7);
timer_resume(IRSND_TIMER_NUMBER);
analogWrite(IRSND_PIN, 0); // pwm off, LOW level
# elif defined (__AVR_XMEGA__)
XMEGA_Timer.CCA = freq;
# else // AVR
# if IRSND_OCx == IRSND_OC2
OCR2 = freq; // use register OCR2 for OC2
# elif IRSND_OCx == IRSND_OC2A // use OC2A
OCR2A = freq; // use register OCR2A for OC2A and OC2B!
# elif IRSND_OCx == IRSND_OC2B // use OC2B
OCR2A = freq; // use register OCR2A for OC2A and OC2B!
# elif IRSND_OCx == IRSND_OC0 // use OC0
OCR0 = freq; // use register OCR2 for OC2
# elif IRSND_OCx == IRSND_OC0A // use OC0A
OCR0A = freq; // use register OCR0A for OC0A and OC0B!
# elif IRSND_OCx == IRSND_OC0B // use OC0B
OCR0A = freq; // use register OCR0A for OC0A and OC0B!
# else
# error wrong value of IRSND_OCx
# endif
# endif //PIC_C18
#endif // ANALYZE
}
/*---------------------------------------------------------------------------------------------------------------------------------------------------
* Initialize the PWM
* @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
void
irsnd_init (void)
{
#ifndef ANALYZE
# if defined(PIC_C18) // PIC C18 or XC8 compiler
# if ! defined(__12F1840) // only C18:
OpenTimer;
# endif
irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
IRSND_PIN = 0; // set IO to outout
PWMoff();
# elif defined (ARM_STM32) // STM32
GPIO_InitTypeDef GPIO_InitStructure;
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
/* GPIOx clock enable */
# if defined (ARM_STM32L1XX)
RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);
# elif defined (ARM_STM32F10X)
RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping
# elif defined (ARM_STM32F4XX)
RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
# endif
/* GPIO Configuration */
GPIO_InitStructure.GPIO_Pin = IRSND_BIT;
# if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);
# elif defined (ARM_STM32F10X)
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
// GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping
# endif
/* TIMx clock enable */
# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
# else
RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
# endif
/* Time base configuration */
TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);
/* PWM1 Mode configuration */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);
/* Preload configuration */
TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);
TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);
irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency
# elif defined (TEENSY_ARM_CORTEX_M4)
if (!digitalPinHasPWM(IRSND_PIN))
{
return;
}
# elif defined (__xtensa__)
pinMode(IRSND_PIN, OUTPUT);
irsnd_set_freq (IRSND_FREQ_36_KHZ);
# elif defined (BOARD_generic_stm32f103c)
pinMode(IRSND_PIN, PWM);
irsnd_set_freq (IRSND_FREQ_36_KHZ);
# elif defined (__AVR_XMEGA__)
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
XMEGA_Timer.PER = 0xFFFF; //Topwert
XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC
# if AVR_PRESCALER == 8
XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8
# else
XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1
# endif
# else // AVR
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
# if IRSND_OCx == IRSND_OC2 // use OC2
TCCR2 = (1<<WGM21); // CTC mode
# if AVR_PRESCALER == 8
TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8
# else
TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1
# endif
# elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B
TCCR2A = (1<<WGM21); // CTC mode
# if AVR_PRESCALER == 8
TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8
# else
TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1
# endif
# elif IRSND_OCx == IRSND_OC0 // use OC0
TCCR0 = (1<<WGM01); // CTC mode
# if AVR_PRESCALER == 8
TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8
# else
TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1
# endif
# elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B
TCCR0A = (1<<WGM01); // CTC mode
# if AVR_PRESCALER == 8
TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8
# else
TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1
# endif
# else
# error wrong value of IRSND_OCx
# endif
irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
# endif //PIC_C18
#endif // ANALYZE
}
#if IRSND_USE_CALLBACK == 1
void
irsnd_set_callback_ptr (void (*cb)(uint8_t))
{
irsnd_callback_ptr = cb;
}
#endif // IRSND_USE_CALLBACK == 1
uint8_t
irsnd_is_busy (void)
{
return irsnd_busy;
}
static uint16_t
bitsrevervse (uint16_t x, uint8_t len)
{
uint16_t xx = 0;
while(len)
{
xx <<= 1;
if (x & 1)
{
xx |= 1;
}
x >>= 1;
len--;
}
return xx;
}
#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
static uint8_t sircs_additional_bitlen;
#endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1
uint8_t
irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)
{
#if IRSND_SUPPORT_RECS80_PROTOCOL == 1
static uint8_t toggle_bit_recs80;
#endif
#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
static uint8_t toggle_bit_recs80ext;
#endif
#if IRSND_SUPPORT_RC5_PROTOCOL == 1
static uint8_t toggle_bit_rc5;
#endif
#if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
static uint8_t toggle_bit_rc6;
#endif
#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
static uint8_t toggle_bit_thomson;
#endif
uint16_t address;
uint16_t command;
if (do_wait)
{
while (irsnd_busy)
{
// do nothing;
}
}
else if (irsnd_busy)
{
return (FALSE);