Misc notes on CPU design.
Where instructions are listed, they may not be exhaustive. Only significantly different instructions are listed.
All jump targets:
- PC+imm (JAL, BRANCH)
- rs1+imm (JALR)
All register write sources:
- rs1#r2 (OP)
- rs1#imm (OP-IMM)
- load-data (STORE)
- PC+4 (JAL, JALR)
- imm (LUI)
- PC+imm (AUIPC)
Some instructions need to do multiple operations, which an ALU could do. Thus, there's a need to choose which operation the ALU is used for.
Instructions that require multiple operations:
- JAL: PC+imm & PC+4
- JALR: r1+imm & PC+4
- BRANCH: r1?r2 & PC+imm
Choice primarily depends on the BRANCH instruction. Either r1?r2 or PC+imm needs a separate component.
Separate r1?r2 advantages:
- Could potentially be faster than an adder?
- This could potentially allow for EX stage to be faster. This depends on timing of various pieces though.
Separate PC+imm advantages:
- Could potentially be calculated in the ID stage already.
- This could allow JAL to jump faster, reducing pipeline bubbles.
- Doesn't require a subtractor.