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z80.c
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z80.c
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/* Caprice32 - Amstrad CPC Emulator
(c) Copyright 1997-2004 Ulrich Doewich
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Zilog Z80A Microprocessor emulation
(c) Copyright 1997-2003 Ulrich Doewich
code portions and ideas taken from the Z80 emulations by:
Juergen Buchmueller (MAME Z80 core v3.3)
Marat Fayzullin
and my own Z80 x86 assembly code (Caprice32 up to version 2.00b2)
Oct 03, 2000 - 18:56 all un-prefixed opcodes done
Oct 07, 2000 - 11:04 all CB opcodes done
Oct 07, 2000 - 15:06 all DD opcodes done
Oct 07, 2000 - 15:23 all DD CB opcodes done
Oct 09, 2000 - 12:41 all ED, FD, and FD CB opcodes done
Oct 14, 2000 - 17:48 added interrupt processing to z80_getopcode
Oct 22, 2000 - 19:18 removed R register update from DDCB and FDCB opcode handlers
Oct 22, 2000 - 19:43 added break-point and trace capabilities
Oct 24, 2000 - 17:57 changed math based opcodes to always work with unsigned parameters
Oct 29, 2000 - 20:46 fixed 16 bit memory read/write opcodes (read both halves from the low byte!)
Oct 29, 2000 - 20:51 fixed LD L,byte; RRC r (used wrong registers - forgot to change them after copy!)
Nov 06, 2000 - 21:08 fixed a couple of IX/IY instructions (forgot to change a few I?h/I?l related opcodes!)
Nov 06, 2000 - 21:20 fixed some DDCB/FDCB instructions (one too many M cycles for BIT (I?+o) & co.)
Nov 07, 2000 - 18:58 complete overhaul of DDCB/FDCB instructions (offset byte handling was wrong!)
Jan 24, 2001 - 18:26 fixed LD (IX/IY + o), L and LD (IX/IY + o), H (uses L and H, not I?l and I?h!)
Feb 19, 2001 - 18:37 removed machine cycle specific code; added cycle count tables and 'wait state' routine
Mar 05, 2001 - 22:58 reworked all cycle count tables - verfied with the real CPC & an oscilloscope
Mar 29, 2001 - 19:10 fixed the timing problem (z80_wait_states was called after interrupts even if they were disabled!)
Apr 03, 2001 - 18:25 incorporated the changes from the MAME Z80 core v3.1 to v3.2 update
Apr 09, 2001 - 19:30 fixed the problem with some CPC programs crashing (offset for IX/IY instructions was unsigned!)
Jul 31, 2001 - 23:34 put the 'old' NOP cycle timing table back in
Nov 12, 2001 - 18:15 incorporated the changes from the MAME Z80 core v3.2 to v3.3 update
Nov 14, 2002 - 21:39 changed the length of processing an interrupt in IM2 from 28T to 76T
Feb 10, 2003 - 18:24 corrected the cycle count of CPI/CPIR & CPD/CPDR with the help of Richard's PlusTest
Feb 12, 2003 - 17:29 added the wait state adjustment on interrupts for a specific number of instructions
(see Richard's document on andercheran for the complete list)
Apr 07, 2003 - 19:10 added z80_mf2stop to emulate the NMI caused by the stop button of the MF2
Apr 07, 2003 - 22:48 added code to z80_execute to monitor when the MF2 finishes and has to be made 'invisible'
May 10, 2003 - 19:12 fixed the unofficial DDCB/FDCB RES/SET instructions: the unaltered value was
stored in the associated register; some minor code clean up
May 15, 2003 - 23:19 "Thomas the Tank Engine", "N.E.X.O.R." and "Jocky Wilson's Darts Compendium" work now:
DI did not clear the z80.EI_issued counter
*/
#include "z80.h"
#include "cap32.h"
#include "tape.h"
extern t_CPC CPC;
extern t_FDC FDC;
extern t_GateArray GateArray;
extern t_PSG PSG;
extern t_VDU VDU;
extern byte *pbTapeImage;
extern dword dwMF2Flags;
extern dword dwMF2ExitAddr;
extern int iTapeCycleCount;
#ifdef DEBUG_Z80
extern FILE *pfoDebug;
unsigned int dbg_z80_lastPC, dbg_z80_diff;
#endif
enum opcodes {
nop, ld_bc_word, ld_mbc_a, inc_bc, inc_b, dec_b, ld_b_byte, rlca,
ex_af_af, add_hl_bc, ld_a_mbc, dec_bc, inc_c, dec_c, ld_c_byte, rrca,
djnz, ld_de_word, ld_mde_a, inc_de, inc_d, dec_d, ld_d_byte, rla,
jr, add_hl_de, ld_a_mde, dec_de, inc_e, dec_e, ld_e_byte, rra,
jr_nz, ld_hl_word, ld_mword_hl, inc_hl, inc_h, dec_h, ld_h_byte, daa,
jr_z, add_hl_hl, ld_hl_mword, dec_hl, inc_l, dec_l, ld_l_byte, cpl,
jr_nc, ld_sp_word, ld_mword_a, inc_sp, inc_mhl, dec_mhl, ld_mhl_byte, scf,
jr_c, add_hl_sp, ld_a_mword, dec_sp, inc_a, dec_a, ld_a_byte, ccf,
ld_b_b, ld_b_c, ld_b_d, ld_b_e, ld_b_h, ld_b_l, ld_b_mhl, ld_b_a,
ld_c_b, ld_c_c, ld_c_d, ld_c_e, ld_c_h, ld_c_l, ld_c_mhl, ld_c_a,
ld_d_b, ld_d_c, ld_d_d, ld_d_e, ld_d_h, ld_d_l, ld_d_mhl, ld_d_a,
ld_e_b, ld_e_c, ld_e_d, ld_e_e, ld_e_h, ld_e_l, ld_e_mhl, ld_e_a,
ld_h_b, ld_h_c, ld_h_d, ld_h_e, ld_h_h, ld_h_l, ld_h_mhl, ld_h_a,
ld_l_b, ld_l_c, ld_l_d, ld_l_e, ld_l_h, ld_l_l, ld_l_mhl, ld_l_a,
ld_mhl_b, ld_mhl_c, ld_mhl_d, ld_mhl_e, ld_mhl_h, ld_mhl_l, halt, ld_mhl_a,
ld_a_b, ld_a_c, ld_a_d, ld_a_e, ld_a_h, ld_a_l, ld_a_mhl, ld_a_a,
add_b, add_c, add_d, add_e, add_h, add_l, add_mhl, add_a,
adc_b, adc_c, adc_d, adc_e, adc_h, adc_l, adc_mhl, adc_a,
sub_b, sub_c, sub_d, sub_e, sub_h, sub_l, sub_mhl, sub_a,
sbc_b, sbc_c, sbc_d, sbc_e, sbc_h, sbc_l, sbc_mhl, sbc_a,
and_b, and_c, and_d, and_e, and_h, and_l, and_mhl, and_a,
xor_b, xor_c, xor_d, xor_e, xor_h, xor_l, xor_mhl, xor_a,
or_b, or_c, or_d, or_e, or_h, or_l, or_mhl, or_a,
cp_b, cp_c, cp_d, cp_e, cp_h, cp_l, cp_mhl, cp_a,
ret_nz, pop_bc, jp_nz, jp, call_nz, push_bc, add_byte, rst00,
ret_z, ret, jp_z, pfx_cb, call_z, call, adc_byte, rst08,
ret_nc, pop_de, jp_nc, outa, call_nc, push_de, sub_byte, rst10,
ret_c, exx, jp_c, ina, call_c, pfx_dd, sbc_byte, rst18,
ret_po, pop_hl, jp_po, ex_msp_hl, call_po, push_hl, and_byte, rst20,
ret_pe, ld_pc_hl, jp_pe, ex_de_hl, call_pe, pfx_ed, xor_byte, rst28,
ret_p, pop_af, jp_p, di, call_p, push_af, or_byte, rst30,
ret_m, ld_sp_hl, jp_m, ei, call_m, pfx_fd, cp_byte, rst38
};
enum CBcodes {
rlc_b, rlc_c, rlc_d, rlc_e, rlc_h, rlc_l, rlc_mhl, rlc_a,
rrc_b, rrc_c, rrc_d, rrc_e, rrc_h, rrc_l, rrc_mhl, rrc_a,
rl_b, rl_c, rl_d, rl_e, rl_h, rl_l, rl_mhl, rl_a,
rr_b, rr_c, rr_d, rr_e, rr_h, rr_l, rr_mhl, rr_a,
sla_b, sla_c, sla_d, sla_e, sla_h, sla_l, sla_mhl, sla_a,
sra_b, sra_c, sra_d, sra_e, sra_h, sra_l, sra_mhl, sra_a,
sll_b, sll_c, sll_d, sll_e, sll_h, sll_l, sll_mhl, sll_a,
srl_b, srl_c, srl_d, srl_e, srl_h, srl_l, srl_mhl, srl_a,
bit0_b, bit0_c, bit0_d, bit0_e, bit0_h, bit0_l, bit0_mhl, bit0_a,
bit1_b, bit1_c, bit1_d, bit1_e, bit1_h, bit1_l, bit1_mhl, bit1_a,
bit2_b, bit2_c, bit2_d, bit2_e, bit2_h, bit2_l, bit2_mhl, bit2_a,
bit3_b, bit3_c, bit3_d, bit3_e, bit3_h, bit3_l, bit3_mhl, bit3_a,
bit4_b, bit4_c, bit4_d, bit4_e, bit4_h, bit4_l, bit4_mhl, bit4_a,
bit5_b, bit5_c, bit5_d, bit5_e, bit5_h, bit5_l, bit5_mhl, bit5_a,
bit6_b, bit6_c, bit6_d, bit6_e, bit6_h, bit6_l, bit6_mhl, bit6_a,
bit7_b, bit7_c, bit7_d, bit7_e, bit7_h, bit7_l, bit7_mhl, bit7_a,
res0_b, res0_c, res0_d, res0_e, res0_h, res0_l, res0_mhl, res0_a,
res1_b, res1_c, res1_d, res1_e, res1_h, res1_l, res1_mhl, res1_a,
res2_b, res2_c, res2_d, res2_e, res2_h, res2_l, res2_mhl, res2_a,
res3_b, res3_c, res3_d, res3_e, res3_h, res3_l, res3_mhl, res3_a,
res4_b, res4_c, res4_d, res4_e, res4_h, res4_l, res4_mhl, res4_a,
res5_b, res5_c, res5_d, res5_e, res5_h, res5_l, res5_mhl, res5_a,
res6_b, res6_c, res6_d, res6_e, res6_h, res6_l, res6_mhl, res6_a,
res7_b, res7_c, res7_d, res7_e, res7_h, res7_l, res7_mhl, res7_a,
set0_b, set0_c, set0_d, set0_e, set0_h, set0_l, set0_mhl, set0_a,
set1_b, set1_c, set1_d, set1_e, set1_h, set1_l, set1_mhl, set1_a,
set2_b, set2_c, set2_d, set2_e, set2_h, set2_l, set2_mhl, set2_a,
set3_b, set3_c, set3_d, set3_e, set3_h, set3_l, set3_mhl, set3_a,
set4_b, set4_c, set4_d, set4_e, set4_h, set4_l, set4_mhl, set4_a,
set5_b, set5_c, set5_d, set5_e, set5_h, set5_l, set5_mhl, set5_a,
set6_b, set6_c, set6_d, set6_e, set6_h, set6_l, set6_mhl, set6_a,
set7_b, set7_c, set7_d, set7_e, set7_h, set7_l, set7_mhl, set7_a
};
enum EDcodes {
ed_00, ed_01, ed_02, ed_03, ed_04, ed_05, ed_06, ed_07,
ed_08, ed_09, ed_0a, ed_0b, ed_0c, ed_0d, ed_0e, ed_0f,
ed_10, ed_11, ed_12, ed_13, ed_14, ed_15, ed_16, ed_17,
ed_18, ed_19, ed_1a, ed_1b, ed_1c, ed_1d, ed_1e, ed_1f,
ed_20, ed_21, ed_22, ed_23, ed_24, ed_25, ed_26, ed_27,
ed_28, ed_29, ed_2a, ed_2b, ed_2c, ed_2d, ed_2e, ed_2f,
ed_30, ed_31, ed_32, ed_33, ed_34, ed_35, ed_36, ed_37,
ed_38, ed_39, ed_3a, ed_3b, ed_3c, ed_3d, ed_3e, ed_3f,
in_b_c, out_c_b, sbc_hl_bc, ld_EDmword_bc, neg, retn, im_0, ld_i_a,
in_c_c, out_c_c, adc_hl_bc, ld_EDbc_mword, neg_1, reti, im_0_1, ld_r_a,
in_d_c, out_c_d, sbc_hl_de, ld_EDmword_de, neg_2, retn_1, im_1, ld_a_i,
in_e_c, out_c_e, adc_hl_de, ld_EDde_mword, neg_3, reti_1, im_2, ld_a_r,
in_h_c, out_c_h, sbc_hl_hl, ld_EDmword_hl, neg_4, retn_2, im_0_2, rrd,
in_l_c, out_c_l, adc_hl_hl, ld_EDhl_mword, neg_5, reti_2, im_0_3, rld,
in_0_c, out_c_0, sbc_hl_sp, ld_EDmword_sp, neg_6, retn_3, im_1_1, ed_77,
in_a_c, out_c_a, adc_hl_sp, ld_EDsp_mword, neg_7, reti_3, im_2_1, ed_7f,
ed_80, ed_81, ed_82, ed_83, ed_84, ed_85, ed_86, ed_87,
ed_88, ed_89, ed_8a, ed_8b, ed_8c, ed_8d, ed_8e, ed_8f,
ed_90, ed_91, ed_92, ed_93, ed_94, ed_95, ed_96, ed_97,
ed_98, ed_99, ed_9a, ed_9b, ed_9c, ed_9d, ed_9e, ed_9f,
ldi, cpi, ini, outi, ed_a4, ed_a5, ed_a6, ed_a7,
ldd, cpd, ind, outd, ed_ac, ed_ad, ed_ae, ed_af,
ldir, cpir, inir, otir, ed_b4, ed_b5, ed_b6, ed_b7,
lddr, cpdr, indr, otdr, ed_bc, ed_bd, ed_be, ed_bf,
ed_c0, ed_c1, ed_c2, ed_c3, ed_c4, ed_c5, ed_c6, ed_c7,
ed_c8, ed_c9, ed_ca, ed_cb, ed_cc, ed_cd, ed_ce, ed_cf,
ed_d0, ed_d1, ed_d2, ed_d3, ed_d4, ed_d5, ed_d6, ed_d7,
ed_d8, ed_d9, ed_da, ed_db, ed_dc, ed_dd, ed_de, ed_df,
ed_e0, ed_e1, ed_e2, ed_e3, ed_e4, ed_e5, ed_e6, ed_e7,
ed_e8, ed_e9, ed_ea, ed_eb, ed_ec, ed_ed, ed_ee, ed_ef,
ed_f0, ed_f1, ed_f2, ed_f3, ed_f4, ed_f5, ed_f6, ed_f7,
ed_f8, ed_f9, ed_fa, ed_fb, ed_fc, ed_fd, ed_fe, ed_ff
};
t_z80regs z80;
int iCycleCount, iWSAdjust;
static byte SZ[256]; // zero and sign flags
static byte SZ_BIT[256]; // zero, sign and parity/overflow (=zero) flags for BIT opcode
static byte SZP[256]; // zero, sign and parity flags
static byte SZHV_inc[256]; // zero, sign, half carry and overflow flags INC r8
static byte SZHV_dec[256]; // zero, sign, half carry and overflow flags DEC r8
#include "z80daa.h"
static byte irep_tmp1[4][4] = {
{0, 0, 1, 0}, {0, 1, 0, 1}, {1, 0, 1, 1}, {0, 1, 1, 0}
};
/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */
static byte drep_tmp1[4][4] = {
{0, 1, 0, 0}, {1, 0, 0, 1}, {0, 0, 1, 0}, {0, 1, 0, 1}
};
/* tmp2 value for all in/out repeated opcodes for B.7-0 */
static byte breg_tmp2[256] = {
0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1
};
static byte cc_op[256] = {
4, 12, 8, 8, 4, 4, 8, 4, 4, 12, 8, 8, 4, 4, 8, 4,
12, 12, 8, 8, 4, 4, 8, 4, 12, 12, 8, 8, 4, 4, 8, 4,
8, 12, 20, 8, 4, 4, 8, 4, 8, 12, 20, 8, 4, 4, 8, 4,
8, 12, 16, 8, 12, 12, 12, 4, 8, 12, 16, 8, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
8, 12, 12, 12, 12, 16, 8, 16, 8, 12, 12, 4, 12, 20, 8, 16,
8, 12, 12, 12, 12, 16, 8, 16, 8, 4, 12, 12, 12, 4, 8, 16,
8, 12, 12, 24, 12, 16, 8, 16, 8, 4, 12, 4, 12, 4, 8, 16,
8, 12, 12, 4, 12, 16, 8, 16, 8, 8, 12, 4, 12, 4, 8, 16
};
static byte cc_cb[256] = {
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4
};
static byte cc_ed[256] = {
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
12, 12, 12, 20, 4, 12, 4, 8, 12, 12, 12, 20, 4, 12, 4, 8,
12, 12, 12, 20, 4, 12, 4, 8, 12, 12, 12, 20, 4, 12, 4, 8,
12, 12, 12, 20, 4, 12, 4, 16, 12, 12, 12, 20, 4, 12, 4, 16,
12, 12, 12, 20, 4, 12, 4, 4, 12, 12, 12, 20, 4, 12, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
16, 12, 16, 16, 4, 4, 4, 4, 16, 12, 16, 16, 4, 4, 4, 4,
16, 12, 16, 16, 4, 4, 4, 4, 16, 12, 16, 16, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
static byte cc_xy[256] = {
4, 12, 8, 8, 4, 4, 8, 4, 4, 12, 8, 8, 4, 4, 8, 4,
12, 12, 8, 8, 4, 4, 8, 4, 12, 12, 8, 8, 4, 4, 8, 4,
8, 12, 20, 8, 4, 4, 8, 4, 8, 12, 20, 8, 4, 4, 8, 4,
8, 12, 16, 8, 20, 20, 20, 4, 8, 12, 16, 8, 4, 4, 8, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
16, 16, 16, 16, 16, 16, 4, 16, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
8, 12, 12, 12, 12, 16, 8, 16, 8, 12, 12, 4, 12, 20, 8, 16,
8, 12, 12, 12, 12, 16, 8, 16, 8, 4, 12, 12, 12, 4, 8, 16,
8, 12, 12, 24, 12, 16, 8, 16, 8, 4, 12, 4, 12, 4, 8, 16,
8, 12, 12, 4, 12, 16, 8, 16, 8, 8, 12, 4, 12, 4, 8, 16
};
static byte cc_xycb[256] = {
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20
};
static byte cc_ex[256] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 8, 4, 4, 0, 0, 0, 0, 4, 8, 4, 4, 0, 0, 0, 0,
8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0
};
extern byte *membank_read[4], *membank_write[4];
inline byte read_mem(word addr) {
return (*(membank_read[addr >> 14] + (addr & 0x3fff))); // returns a byte from a 16KB memory bank
}
inline void write_mem(word addr, byte val) {
*(membank_write[addr >> 14] + (addr & 0x3fff)) = val; // writes a byte to a 16KB memory bank
}
#define z80_wait_states \
{ \
access_video_memory(iCycleCount >> 2); \
if (CPC.snd_enabled) { \
PSG.cycle_count.high += iCycleCount; \
if (PSG.cycle_count.high >= CPC.snd_cycle_count_init.high) { \
PSG.cycle_count.both -= CPC.snd_cycle_count_init.both; \
PSG.Synthesizer(); \
} \
} \
if (FDC.phase == EXEC_PHASE) { \
FDC.timeout -= iCycleCount; \
if (FDC.timeout <= 0) { \
FDC.flags |= OVERRUN_flag; \
if (FDC.cmd_direction == FDC_TO_CPU) { \
fdc_read_data(); \
} \
else { \
fdc_write_data(0xff); \
} \
} \
} \
if ((CPC.tape_motor) && (CPC.tape_play_button)) { \
iTapeCycleCount -= iCycleCount; \
if (iTapeCycleCount <= 0) { \
Tape_UpdateLevel(); \
} \
} \
CPC.cycle_count -= iCycleCount; \
}
#define ADC(value) \
{ \
unsigned val = value; \
unsigned res = _A + val + (_F & Cflag); \
_F = SZ[res & 0xff] | ((res >> 8) & Cflag) | ((_A ^ res ^ val) & Hflag) | \
(((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \
_A = res; \
}
#define ADD(value) \
{ \
unsigned val = value; \
unsigned res = _A + val; \
_F = SZ[(byte)res] | ((res >> 8) & Cflag) | ((_A ^ res ^ val) & Hflag) | \
(((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \
_A = (byte)res; \
}
#define ADD16(dest, src) \
{ \
dword res = z80.dest.d + z80.src.d; \
_F = (_F & (Sflag | Zflag | Vflag)) | (((z80.dest.d ^ res ^ z80.src.d) >> 8) & Hflag) | \
((res >> 16) & Cflag) | ((res >> 8) & Xflags); \
z80.dest.w.l = (word)res; \
}
#define AND(val) \
{ \
_A &= val; \
_F = SZP[_A] | Hflag; \
}
#define CALL \
{ \
reg_pair dest; \
dest.b.l = read_mem(_PC++); /* subroutine address low byte */ \
dest.b.h = read_mem(_PC++); /* subroutine address high byte */ \
write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
_PC = dest.w.l; /* continue execution at subroutine */ \
}
#define CP(value) \
{ \
unsigned val = value; \
unsigned res = _A - val; \
_F = (SZ[res & 0xff] & (Sflag | Zflag)) | (val & Xflags) | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
((((val ^ _A) & (_A ^ res)) >> 5) & Vflag); \
}
#define DAA \
{ \
int idx = _A; \
if(_F & Cflag) \
idx |= 0x100; \
if(_F & Hflag) \
idx |= 0x200; \
if(_F & Nflag) \
idx |= 0x400; \
_AF = DAATable[idx]; \
}
#define DEC(reg) \
{ \
reg--; \
_F = (_F & Cflag) | SZHV_dec[reg]; \
}
#define JR \
{ \
signed char offset; \
offset = (signed char)(read_mem(_PC)); /* grab signed jump offset */ \
_PC += offset + 1; /* add offset & correct PC */ \
}
#define EXX \
{ \
reg_pair temp; \
temp = z80.BCx; \
z80.BCx = z80.BC; \
z80.BC = temp; \
temp = z80.DEx; \
z80.DEx = z80.DE; \
z80.DE = temp; \
temp = z80.HLx; \
z80.HLx = z80.HL; \
z80.HL = temp; \
}
#define EX(op1, op2) \
{ \
reg_pair temp; \
temp = op1; \
op1 = op2; \
op2 = temp; \
}
#define EX_SP(reg) \
{ \
reg_pair temp; \
temp.b.l = read_mem(_SP++); \
temp.b.h = read_mem(_SP); \
write_mem(_SP--, z80.reg.b.h); \
write_mem(_SP, z80.reg.b.l); \
z80.reg.w.l = temp.w.l; \
}
#define INC(reg) \
{ \
reg++; \
_F = (_F & Cflag) | SZHV_inc[reg]; \
}
#define JP \
{ \
reg_pair addr; \
addr.b.l = read_mem(_PC++); \
addr.b.h = read_mem(_PC); \
_PC = addr.w.l; \
}
#define LD16_MEM(reg) \
{ \
reg_pair addr; \
addr.b.l = read_mem(_PC++); \
addr.b.h = read_mem(_PC++); \
z80.reg.b.l = read_mem(addr.w.l); \
z80.reg.b.h = read_mem(addr.w.l+1); \
}
#define LDMEM_16(reg) \
{ \
reg_pair addr; \
addr.b.l = read_mem(_PC++); \
addr.b.h = read_mem(_PC++); \
write_mem(addr.w.l, z80.reg.b.l); \
write_mem(addr.w.l+1, z80.reg.b.h); \
}
#define OR(val) \
{ \
_A |= val; \
_F = SZP[_A]; \
}
#define POP(reg) \
{ \
z80.reg.b.l = read_mem(_SP++); \
z80.reg.b.h = read_mem(_SP++); \
}
#define PUSH(reg) \
{ \
write_mem(--_SP, z80.reg.b.h); \
write_mem(--_SP, z80.reg.b.l); \
}
#define RET \
{ \
z80.PC.b.l = read_mem(_SP++); \
z80.PC.b.h = read_mem(_SP++); \
}
#define RLA \
{ \
byte res = (_A << 1) | (_F & Cflag); \
byte carry = (_A & 0x80) ? Cflag : 0; \
_F = (_F & (Sflag | Zflag | Pflag)) | carry | (res & Xflags); \
_A = res; \
}
#define RLCA \
{ \
_A = (_A << 1) | (_A >> 7); \
_F = (_F & (Sflag | Zflag | Pflag)) | (_A & (Xflags | Cflag)); \
}
#define RRA \
{ \
byte res = (_A >> 1) | (_F << 7); \
byte carry = (_A & 0x01) ? Cflag : 0; \
_F = (_F & (Sflag | Zflag | Pflag)) | carry | (res & Xflags); \
_A = res; \
}
#define RRCA \
{ \
_F = (_F & (Sflag | Zflag | Pflag)) | (_A & Cflag); \
_A = (_A >> 1) | (_A << 7); \
_F |= (_A & Xflags); \
}
#define RST(addr) \
{ \
write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
_PC = addr; /* continue execution at restart address */ \
}
#define SBC(value) \
{ \
unsigned val = value; \
unsigned res = _A - val - (_F & Cflag); \
_F = SZ[res & 0xff] | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
(((val ^ _A) & (_A ^ res) & 0x80) >> 5); \
_A = res; \
}
#define SUB(value) \
{ \
unsigned val = value; \
unsigned res = _A - val; \
_F = SZ[res & 0xff] | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
(((val ^ _A) & (_A ^ res) & 0x80) >> 5); \
_A = res; \
}
#define XOR(val) \
{ \
_A ^= val; \
_F = SZP[_A]; \
}
#define BIT(bit, reg) \
_F = (_F & Cflag) | Hflag | SZ_BIT[reg & (1 << bit)]
#define BIT_XY BIT
inline byte RES(byte bit, byte val) {
return val & ~(1 << bit);
}
inline byte RLC(byte val) {
unsigned res = val;
unsigned carry = (res & 0x80) ? Cflag : 0;
res = ((res << 1) | (res >> 7)) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte RL(byte val) {
unsigned res = val;
unsigned carry = (res & 0x80) ? Cflag : 0;
res = ((res << 1) | (_F & Cflag)) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte RRC(byte val) {
unsigned res = val;
unsigned carry = (res & 0x01) ? Cflag : 0;
res = ((res >> 1) | (res << 7)) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte RR(byte val) {
unsigned res = val;
unsigned carry = (res & 0x01) ? Cflag : 0;
res = ((res >> 1) | (_F << 7)) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte SET(byte bit, byte val) {
return val | (1 << bit);
}
inline byte SLA(byte val) {
unsigned res = val;
unsigned carry = (res & 0x80) ? Cflag : 0;
res = (res << 1) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte SLL(byte val) {
unsigned res = val;
unsigned carry = (res & 0x80) ? Cflag : 0;
res = ((res << 1) | 0x01) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte SRA(byte val) {
unsigned res = val;
unsigned carry = (res & 0x01) ? Cflag : 0;
res = ((res >> 1) | (res & 0x80)) & 0xff;
_F = SZP[res] | carry;
return res;
}
inline byte SRL(byte val) {
unsigned res = val;
unsigned carry = (res & 0x01) ? Cflag : 0;
res = (res >> 1) & 0xff;
_F = SZP[res] | carry;
return res;
}
#define ADC16(reg) \
{ \
dword res = _HLdword + z80.reg.d + (_F & Cflag); \
_F = (((_HLdword ^ res ^ z80.reg.d) >> 8) & Hflag) | \
((res >> 16) & Cflag) | \
((res >> 8) & (Sflag | Xflags)) | \
((res & 0xffff) ? 0 : Zflag) | \
(((z80.reg.d ^ _HLdword ^ 0x8000) & (z80.reg.d ^ res) & 0x8000) >> 13); \
_HL = (word)res; \
}
#define CPD \
{ \
byte val = read_mem(_HL); \
byte res = _A - val; \
_HL--; \
_BC--; \
_F = (_F & Cflag) | (SZ[res] & ~Xflags) | ((_A ^ val ^ res) & Hflag) | Nflag; \
if(_F & Hflag) res -= 1; \
if(res & 0x02) _F |= 0x20; \
if(res & 0x08) _F |= 0x08; \
if(_BC) _F |= Vflag; \
}
#define CPDR \
CPD; \
if(_BC && !(_F & Zflag)) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
iWSAdjust++; \
}
#define CPI \
{ \
byte val = read_mem(_HL); \
byte res = _A - val; \
_HL++; \
_BC--; \
_F = (_F & Cflag) | (SZ[res] & ~Xflags) | ((_A ^ val ^ res) & Hflag) | Nflag; \
if(_F & Hflag) res -= 1; \
if(res & 0x02) _F |= 0x20; \
if(res & 0x08) _F |= 0x08; \
if(_BC) _F |= Vflag; \
}
#define CPIR \
CPI; \
if(_BC && !(_F & Zflag)) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
iWSAdjust++; \
}
#define IND \
{ \
byte io = z80_IN_handler(z80.BC); \
_B--; \
write_mem(_HL, io); \
_HL--; \
_F = SZ[_B]; \
if(io & Sflag) _F |= Nflag; \
if((((_C - 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
if((drep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
_F |= Pflag; \
}
#define INDR \
IND; \
if(_B) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define INI \
{ \
byte io = z80_IN_handler(z80.BC); \
_B--; \
write_mem(_HL, io); \
_HL++; \
_F = SZ[_B]; \
if(io & Sflag) _F |= Nflag; \
if((((_C + 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
if((irep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
_F |= Pflag; \
}
#define INIR \
INI; \
if(_B) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define LDD \
{ \
byte io = read_mem(_HL); \
write_mem(_DE, io); \
_F &= Sflag | Zflag | Cflag; \
if((_A + io) & 0x02) _F |= 0x20; \
if((_A + io) & 0x08) _F |= 0x08; \
_HL--; \
_DE--; \
_BC--; \
if(_BC) _F |= Vflag; \
}
#define LDDR \
LDD; \
if(_BC) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define LDI \
{ \
byte io = read_mem(_HL); \
write_mem(_DE, io); \
_F &= Sflag | Zflag | Cflag; \
if((_A + io) & 0x02) _F |= 0x20; \
if((_A + io) & 0x08) _F |= 0x08; \
_HL++; \
_DE++; \
_BC--; \
if(_BC) _F |= Vflag; \
}
#define LDIR \
LDI; \
if(_BC) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define NEG \
{ \
byte value = _A; \
_A = 0; \
SUB(value); \
}
#define OUTD \
{ \
byte io = read_mem(_HL); \
_B--; \
z80_OUT_handler(z80.BC, io); \
_HL--; \
_F = SZ[_B]; \
if(io & Sflag) _F |= Nflag; \
if((((_C - 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
if((drep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
_F |= Pflag; \
}
#define OTDR \
OUTD; \
if(_B) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define OUTI \
{ \
byte io = read_mem(_HL); \
_B--; \
z80_OUT_handler(z80.BC, io); \
_HL++; \
_F = SZ[_B]; \
if(io & Sflag) _F |= Nflag; \
if((((_C + 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
if((irep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
_F |= Pflag; \
}
#define OTIR \
OUTI; \
if(_B) \
{ \
iCycleCount += cc_ex[bOpCode]; \
_PC -= 2; \
}
#define RLD \
{ \
byte n = read_mem(_HL); \
write_mem(_HL, (n << 4) | (_A & 0x0f)); \
_A = (_A & 0xf0) | (n >> 4); \
_F = (_F & Cflag) | SZP[_A]; \
}
#define RRD \
{ \
byte n = read_mem(_HL); \
write_mem(_HL, (n >> 4) | (_A << 4)); \
_A = (_A & 0xf0) | (n & 0x0f); \
_F = (_F & Cflag) | SZP[_A]; \
}
#define SBC16(reg) \
{ \
dword res = _HLdword - z80.reg.d - (_F & Cflag); \
_F = (((_HLdword ^ res ^ z80.reg.d) >> 8) & Hflag) | Nflag | \
((res >> 16) & Cflag) | \
((res >> 8) & (Sflag | Xflags)) | \
((res & 0xffff) ? 0 : Zflag) | \
(((z80.reg.d ^ _HLdword) & (_HLdword ^ res) &0x8000) >> 13); \
_HL = (word)res; \
}
#define z80_int_handler \
{ \
if (_IFF1) { /* process interrupts? */ \
_R++; \
_IFF1 = _IFF2 = 0; /* clear interrupt flip-flops */ \
z80.int_pending = 0; \
GateArray.sl_count &= 0xdf; /* clear bit 5 of GA scanline counter */ \
if (_HALT) { /* HALT instruction active? */ \
_HALT = 0; /* exit HALT 'loop' */ \
_PC++; /* correct PC */ \
} \
if (_IM < 2) { /* interrupt mode 0 or 1? (IM0 = IM1 on the CPC) */ \
iCycleCount = 20; \
if (iWSAdjust) { \
iCycleCount -= 4; \
} \
RST(0x0038); \
z80_wait_states \
} \
else { /* interrupt mode 2 */ \
reg_pair addr; \
iCycleCount = 28; /* was 76 */ \
if (iWSAdjust) { \
iCycleCount -= 4; \
} \
write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
addr.b.l = 0xff; /* assemble pointer */ \
addr.b.h = _I; \
z80.PC.b.l = read_mem(addr.w.l); /* retrieve low byte of vector */ \
z80.PC.b.h = read_mem(addr.w.l+1); /* retrieve high byte of vector */ \
z80_wait_states \
} \
} \
}
void z80_init_tables(void)
{
int i, p;
for (i = 0; i < 256; i++) {
p = 0;
if(i & 0x01) ++p;
if(i & 0x02) ++p;
if(i & 0x04) ++p;
if(i & 0x08) ++p;
if(i & 0x10) ++p;
if(i & 0x20) ++p;
if(i & 0x40) ++p;
if(i & 0x80) ++p;
SZ[i] = i ? i & Sflag : Zflag;
SZ[i] |= (i & Xflags);
SZ_BIT[i] = i ? i & Sflag : Zflag | Pflag;
SZ_BIT[i] |= (i & Xflags);
SZP[i] = SZ[i] | ((p & 1) ? 0 : Pflag);
SZHV_inc[i] = SZ[i];
if(i == 0x80) SZHV_inc[i] |= Vflag;
if((i & 0x0f) == 0x00) SZHV_inc[i] |= Hflag;
SZHV_dec[i] = SZ[i] | Nflag;
if(i == 0x7f) SZHV_dec[i] |= Vflag;
if((i & 0x0f) == 0x0f) SZHV_dec[i] |= Hflag;
}
}
void z80_mf2stop(void)
{
_R++;
_IFF1 = 0;
z80.EI_issued = 0;
iCycleCount = 20;
if (iWSAdjust) {
iCycleCount -= 4;
}
dwMF2ExitAddr = _PCdword;
RST(0x0066); // MF2 stop button causes a Z80 NMI
z80_wait_states
dwMF2Flags = MF2_ACTIVE | MF2_RUNNING;
}
int z80_execute(void)
{
byte bOpCode;
while (_PCdword != z80.break_point) { // loop until break point
#ifdef DEBUG_Z80
dbg_z80_diff = abs(dbg_z80_lastPC - _PC);
if (dbg_z80_diff > 0x100) {
fprintf(pfoDebug, "\n%04x ", _PC);
}
// else {
// fprintf(pfoDebug, "%04x ", _PC);