From 55521e9b9eb3fc87d0e2efb4b0890737d73d3f79 Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Fri, 22 Nov 2024 16:27:04 +0100 Subject: [PATCH 01/14] Small fix to tutorial Makefile --- examples/tutorial/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/tutorial/Makefile b/examples/tutorial/Makefile index 3b84f32e3..96d0ef8ff 100644 --- a/examples/tutorial/Makefile +++ b/examples/tutorial/Makefile @@ -1,11 +1,11 @@ MAKEFILE_DIRS=1-code 3-exec 8-symbexec -HOLMAKEFILE_DIRS=2-lift 4-bir-to-arm 5-wp 6-smt 7-composition support support2 +HOLMAKEFILE_DIRS=2-lift 4-bir-to-arm 5-wp 6-smt 7-composition ########################################################## .DEFAULT_GOAL := all -all: 7-composition support2 +all: 7-composition ########################################################## From 26c51081a5f255fc72c22c5ee42e4dda5eecd9fc Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Wed, 21 Oct 2020 14:37:27 +0200 Subject: [PATCH 02/14] Changed installation script to install branch from kth-step fork instead --- scripts/setup/install_hol4.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/setup/install_hol4.sh b/scripts/setup/install_hol4.sh index 8afc748d6..61bccb357 100755 --- a/scripts/setup/install_hol4.sh +++ b/scripts/setup/install_hol4.sh @@ -117,4 +117,3 @@ do cd "${HOL4_DIR}/${dir}" ${HOL4_DIR}/bin/Holmake done - From d7eca9e61722385a26a8fef17ac26d893e94081d Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Tue, 27 Oct 2020 16:25:55 +0100 Subject: [PATCH 03/14] Bugfix for alternate branch-specific HOL4, small changes in RISC-V self-test --- .../lifter/bir_lifting_machinesScript.sml | 2 +- src/tools/lifter/selftestLib.sml | 5 ++-- src/tools/lifter/selftest_riscv.log | 24 +++++++++---------- src/tools/lifter/selftest_riscv.sml | 24 ++++++++++--------- 4 files changed, 29 insertions(+), 26 deletions(-) diff --git a/src/theory/tools/lifter/bir_lifting_machinesScript.sml b/src/theory/tools/lifter/bir_lifting_machinesScript.sml index 61278149d..190355bb0 100644 --- a/src/theory/tools/lifter/bir_lifting_machinesScript.sml +++ b/src/theory/tools/lifter/bir_lifting_machinesScript.sml @@ -1028,7 +1028,7 @@ Definition riscv_bmr_def: * OK state is now minimal. *) bmr_extra := \ms. riscv_state_is_OK ms; (* Registers are the 32 general-purpose registers as well as the - * 32 fprs (fpr = floating point register?). *) + * 32 floating-point registers. *) bmr_imms := (riscv_GPRS_lifted_imms_LIST++riscv_FPRS_lifted_imms_LIST); (* Done! *) bmr_mem := riscv_lifted_mem; diff --git a/src/tools/lifter/selftestLib.sml b/src/tools/lifter/selftestLib.sml index 469948cfe..ef4fb5aea 100644 --- a/src/tools/lifter/selftestLib.sml +++ b/src/tools/lifter/selftestLib.sml @@ -145,8 +145,9 @@ end; fun final_results name expected_failed_hexcodes = let - val _ = print_log_with_style sty_HEADER true ("\n\n\nSUMMARY FAILING HEXCODES " ^ name ^ "\n\n"); - val _ = print_log true "\n"; + val _ = print_log true "\n\n\n"; + val _ = print_log_with_style selftestLib.sty_HEADER true ("SUMMARY FAILING HEXCODES " ^ name); + val _ = print_log true "\n\n\n"; val failing_l = op_mk_set (fn (x, _, _) => fn (y, _, _) => (x = y)) (!failed_hexcodes_list) val ok_l = op_mk_set (fn (x, _, _) => fn (y, _, _) => (x = y)) (!success_hexcodes_list) diff --git a/src/tools/lifter/selftest_riscv.log b/src/tools/lifter/selftest_riscv.log index de2f431b2..a364b40b8 100644 --- a/src/tools/lifter/selftest_riscv.log +++ b/src/tools/lifter/selftest_riscv.log @@ -928,22 +928,22 @@ FENCE.I x0, x0, 0: 0000100F @ 0x10030 - FAILED RV64 Zicsr Standard Extension CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - FAILED - bmr_step_hex failed + lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed RV64M Standard Extension (instructions inherited from RV32M) @@ -1294,12 +1294,12 @@ SUMMARY FAILING HEXCODES RISC-V Instructions FAILED: 10/77 - "3400F0F3" (* bmr_step_hex failed *), - "3400E0F3" (* bmr_step_hex failed *), - "3400D0F3" (* bmr_step_hex failed *), - "340130F3" (* bmr_step_hex failed *), - "340120F3" (* bmr_step_hex failed *), - "340110F3" (* bmr_step_hex failed *), + "3400F0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), + "3400E0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), + "3400D0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), + "340130F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), + "340120F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), + "340110F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), "0000100F" (* bmr_step_hex failed *), "00100073" (* bmr_step_hex failed *), "00000073" (* bmr_step_hex failed *), diff --git a/src/tools/lifter/selftest_riscv.sml b/src/tools/lifter/selftest_riscv.sml index 6e4e35c0a..afef5d575 100644 --- a/src/tools/lifter/selftest_riscv.sml +++ b/src/tools/lifter/selftest_riscv.sml @@ -67,8 +67,10 @@ val riscv_test_asms = map riscv_test_asm (* Tests *) (*********) val _ = print_msg "\n"; -val _ = print_header "MANUAL TESTS (HEX) - RISC-V\nRV64I Base Instruction Set (instructions inherited from RV32I)\n"; +val _ = print_header "MANUAL TESTS (HEX) - RISC-V"; val _ = print_msg "\n"; +val _ = print_header "RV64I Base Instruction Set (instructions inherited from RV32I)"; +val _ = print_msg "\n\n"; (* Good presentation of RISC-V instructions at https://inst.eecs.berkeley.edu/~cs61c/sp19/lectures/lec05.pdf *) (* 75 instructions in initial scope (including M extension) *) (* 10 still TODO: @@ -245,8 +247,8 @@ val _ = fail_with_msg "EBREAK not yet supported by stepLib"; val _ = riscv_test_hex_print_asm "EBREAK" "00100073"; val _ = print_msg "\n"; -val _ = print_header "RV64I Base Instruction Set (instructions added to RV32I)\n"; -val _ = print_msg "\n"; +val _ = print_header "RV64I Base Instruction Set (instructions added to RV32I)"; +val _ = print_msg "\n\n"; (* I-type load variants *) val _ = riscv_test_asms [ @@ -288,8 +290,8 @@ val _ = print_msg "\n"; ]; val _ = print_msg "\n"; -val _ = print_header "RV64 Zifencei Standard Extension\n"; -val _ = print_msg "\n"; +val _ = print_header "RV64 Zifencei Standard Extension"; +val _ = print_msg "\n\n"; (* FENCE.I x0, x0, 0 : 000000000000 00000 001 00000 0001111 @@ -302,8 +304,8 @@ val _ = fail_with_msg "FENCE.I not yet supported by stepLib"; val _ = riscv_test_hex_print_asm "FENCE.I x0, x0, 0" "0000100F"; val _ = print_msg "\n"; -val _ = print_header "RV64 Zicsr Standard Extension\n"; -val _ = print_msg "\n"; +val _ = print_header "RV64 Zicsr Standard Extension"; +val _ = print_msg "\n\n"; (* CSR instructions (opcode SYSTEM) *) (* TODO: Note that machine mode is currently assumed for these instructions @@ -352,8 +354,8 @@ val _ = riscv_test_hex_print_asm "CSRRSI x1, mscratch(0x340), 0x1" "3400E0F3"; val _ = riscv_test_hex_print_asm "CSRRCI x1, mscratch(0x340), 0x1" "3400F0F3"; val _ = print_msg "\n"; -val _ = print_header "RV64M Standard Extension (instructions inherited from RV32M)\n"; -val _ = print_msg "\n"; +val _ = print_header "RV64M Standard Extension (instructions inherited from RV32M)"; +val _ = print_msg "\n\n"; (* R-type variants (opcode OP) *) val _ = riscv_test_asms [ @@ -376,8 +378,8 @@ val _ = print_msg "\n"; ]; val _ = print_msg "\n"; -val _ = print_header "RV64M Standard Extension (instructions added to RV32M)\n"; -val _ = print_msg "\n"; +val _ = print_header "RV64M Standard Extension (instructions added to RV32M)"; +val _ = print_msg "\n\n"; (* R-type variants (opcode OP-32) *) val _ = riscv_test_asms [ From 41a1c371b6bdb8f0b2f640faf40d759bd99b1d80 Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Wed, 28 Oct 2020 09:18:43 +0100 Subject: [PATCH 04/14] Small changes to selftests, some work on CSR instruction lifting --- .../lifter/bir_lifting_machinesScript.sml | 59 ++++++++++++++++--- .../tools/lifter/bir_riscv_extrasScript.sml | 34 ++++++++++- src/tools/lifter/bir_inst_liftingLib.sml | 30 ++++++---- src/tools/lifter/selftestLib.sml | 28 +++++---- src/tools/lifter/selftest_riscv.log | 30 +++++----- 5 files changed, 132 insertions(+), 49 deletions(-) diff --git a/src/theory/tools/lifter/bir_lifting_machinesScript.sml b/src/theory/tools/lifter/bir_lifting_machinesScript.sml index 190355bb0..d11d69675 100644 --- a/src/theory/tools/lifter/bir_lifting_machinesScript.sml +++ b/src/theory/tools/lifter/bir_lifting_machinesScript.sml @@ -607,13 +607,29 @@ Definition arm8_lifted_pc_def: (\ms:arm8_state. Imm64 (ms.PC)) End -(* Well defined state *) +(* Well-defined state *) +(* https://static.docs.arm.com/100878/0100/fundamentals_of_armv8_a_100878_0100_en.pdf + * tells us that + * ELn: Exception level n. EL0 is user, EL1 kernel, EL2 Hypervisor, EL3 firmware (p. 4 of PDF). + * SCTLR: System control register; for EL1, EL2 and EL3 (p. 24 of PDF). + * PSTATE: Processor state flags, accessed through special-purpose registers. (p. 16 of PDF) + * TCR: Translation Control Register; for EL1, EL2 and EL3. Determines + * Translation Table Base Register. *) Definition arm8_state_is_OK_def: - arm8_state_is_OK (ms:arm8_state) <=> ( - ~ms.SCTLR_EL1.E0E ∧ (ms.PSTATE.EL = 0w) ∧ (ms.exception = NoException) /\ - ~ms.SCTLR_EL1.SA0 /\ - ~ms.TCR_EL1.TBI0 /\ - ~ms.TCR_EL1.TBI1) + (* Explicit data accesses at EL0 MUST be little-endian. *) + ~ms.SCTLR_EL1.E0E /\ + (* Exception level must be 0 (user) *) + (ms.PSTATE.EL = 0w) /\ + (* Exception must be NoException (as opposed to ALIGNMENT_FAULT, + * UNDEFINED_FAULT and ASSERT).*) + (ms.exception = NoException) /\ + (* Stack Alignment Check MUST NOT be enabled for EL0. *) + ~ms.SCTLR_EL1.SA0 /\ + (* Translation control register for EL1 must not be TBI0 or TBI1, + * meaning it must be "tcr_el1'rst", which is a 62-bit field. + * TODO: What is TBI0 and TBI1? *) + ~ms.TCR_EL1.TBI0 /\ + ~ms.TCR_EL1.TBI1 End Definition arm8_bmr_def: @@ -759,10 +775,16 @@ Definition m0_lifted_pc_def: (\ms:m0_state. Imm32 (ms.REG RName_PC)) End +(* AIRCR: Application Interrupt and Reset Control Register. + * CONTROL: Special register in Cortex-M processor. Can be accessed using MSR and MRS. *) Definition m0_state_is_OK_def: m0_state_is_OK (ef, sel) (s:m0_state) = - ((s.AIRCR.ENDIANNESS <=> ef) /\ (s.CONTROL.SPSEL <=> sel) /\ - (s.exception = NoException)) + (* Endianness must match argument ef. *) + ((s.AIRCR.ENDIANNESS <=> ef) /\ + (* Stack pointer selection bit in the control register must match argument sel. *) + (s.CONTROL.SPSEL <=> sel) /\ + (* Exception must be NoException. *) + (s.exception = NoException)) End (* Just a dummy for now *) @@ -1001,6 +1023,24 @@ Definition riscv_FPRS_lifted_imms_LIST_def: End Theorem riscv_FPRS_lifted_imms_LIST_EVAL = EVAL ``riscv_FPRS_lifted_imms_LIST`` +(* NOTE: Since the L3 model uses separate immediate values for the fields + * of a single system register (instead of letting the entire system register + * be represented as one immediate), we do so here as well. *) +val riscv_sysregs_lifted_imms_LIST_def = Define ` + riscv_sysregs_lifted_imms_LIST = [ + (* MPRV (from the mstatus register) is really a 2-bit value, + * but is represented as an 8-bit immediate *) + (BMLI (BVar "MPRV" (BType_Imm Bit8)) + (\ms:riscv_state. Imm8 (w2w((ms.c_MCSR ms.procID).mstatus.MPRV))) + ); + (BMLI (BVar "mscratch" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 ((ms.c_MCSR ms.procID).mscratch)) + ) + ] +`; +val riscv_sysregs_lifted_imms_LIST_EVAL = save_thm("riscv_sysregs_lifted_imms_LIST_EVAL", + EVAL ``riscv_sysregs_lifted_imms_LIST`` +); (* Note: For some reason, MEM is named MEM8 in the RISC-V state. * Since memory is shared between processes, this does not require @@ -1029,7 +1069,7 @@ Definition riscv_bmr_def: bmr_extra := \ms. riscv_state_is_OK ms; (* Registers are the 32 general-purpose registers as well as the * 32 floating-point registers. *) - bmr_imms := (riscv_GPRS_lifted_imms_LIST++riscv_FPRS_lifted_imms_LIST); + bmr_imms := (riscv_GPRS_lifted_imms_LIST++riscv_FPRS_lifted_imms_LIST++riscv_sysregs_lifted_imms_LIST); (* Done! *) bmr_mem := riscv_lifted_mem; (* Done! *) @@ -1042,6 +1082,7 @@ End (* Evaluation theorem of RISC-V BMR. *) Theorem riscv_bmr_EVAL = SIMP_CONV list_ss [riscv_bmr_def, riscv_state_is_OK_def, riscv_GPRS_lifted_imms_LIST_EVAL, riscv_FPRS_lifted_imms_LIST_EVAL, + riscv_sysregs_lifted_imms_LIST_EVAL, riscv_lifted_mem_def, riscv_lifted_pc_def, bir_temp_var_name_def] ``riscv_bmr`` diff --git a/src/theory/tools/lifter/bir_riscv_extrasScript.sml b/src/theory/tools/lifter/bir_riscv_extrasScript.sml index b60a204f0..04ca6952d 100644 --- a/src/theory/tools/lifter/bir_riscv_extrasScript.sml +++ b/src/theory/tools/lifter/bir_riscv_extrasScript.sml @@ -795,6 +795,35 @@ in thm2 end) +(****************************************) +(* Lifting 2-word predicates *) +(* (related to system register entries) *) +(****************************************) + +(* This is a very ugly solution, since we don't have 2-bit + * immediates... *) +(* TODO: Instantiate this with all possible concrete values *) +val riscv_is_lifted_imm_exp_2EQ = store_thm ("riscv_is_lifted_imm_exp_2EQ", + ``!env w1 e1 e2. + bir_is_lifted_imm_exp env e1 (Imm8 (w2w w1)) ==> + bir_is_lifted_imm_exp env e2 (Imm8 3w) ==> + bir_is_lifted_imm_exp env (BExp_BinPred BIExp_Equal e1 e2) + (bool2b (w1 = (3w:word2)))``, + +cheat +); + +(* +val w2w_word2_to_word8 = store_thm ("w2w_word2_to_word8", + ``((w2w (0w:word2)):word8) = (0w:word8) /\ + ((w2w (1w:word2)):word8) = (1w:word8) /\ + ((w2w (2w:word2)):word8) = (2w:word8) /\ + ((w2w (3w:word2)):word8) = (3w:word8)``, + +blastLib.BBLAST_TAC +); +*) + (*******************************************************) (* RISC-V predicates are usually cast to 64-bit format *) (*******************************************************) @@ -830,7 +859,7 @@ REPEAT STRIP_TAC >> ( QED -val riscv_is_lifted_imm_exp_BIN_PRED = save_thm ("bir_is_lifted_imm_exp_BIN_PRED", +val riscv_is_lifted_imm_exp_BIN_PRED = save_thm ("riscv_is_lifted_imm_exp_BIN_PRED", let val thm0 = riscv_is_lifted_imm_exp_BIN_PRED0 val thm1 = SIMP_RULE (std_ss++DatatypeSimps.expand_type_quants_ss [``:bir_bin_pred_t``]) [ @@ -860,7 +889,8 @@ Theorem riscv_extra_LIFTS = LIST_CONJ [ riscv_is_lifted_imm_exp_32LSBsLC, riscv_is_lifted_imm_exp_64MSBs, riscv_is_lifted_imm_exp_GE, - riscv_is_lifted_imm_exp_GEU] + riscv_is_lifted_imm_exp_GEU, + riscv_is_lifted_imm_exp_2EQ] Theorem riscv_CHANGE_INTERVAL_THMS = LIST_CONJ [riscv_LIFT_STORE_DWORD_CHANGE_INTERVAL, diff --git a/src/tools/lifter/bir_inst_liftingLib.sml b/src/tools/lifter/bir_inst_liftingLib.sml index 944d1b5a5..b21b472aa 100644 --- a/src/tools/lifter/bir_inst_liftingLib.sml +++ b/src/tools/lifter/bir_inst_liftingLib.sml @@ -35,6 +35,7 @@ open bir_inst_liftingLibTypes structure MD = struct val mr = m0_mod_bmr_rec false true end; structure MD = struct val mr = riscv_bmr_rec end; + (* PC and memory regions: *) val pc = Arbnum.fromInt 0x10000 val (mu_b, mu_e) = (Arbnum.fromInt 0x1000, Arbnum.fromInt 0x100000) val (_, mu_thm) = mk_WI_end_of_nums_WFE ``:64`` (Arbnum.fromInt 0x1000) (Arbnum.fromInt 0x100000) @@ -236,7 +237,8 @@ open bir_inst_liftingLibTypes (* For debugging RISC-V: (* TODO: Make shortcuts for debugging other things than preconds *) - val hex_code = String.map Char.toUpper "FCE0879B"; (* "addiw x15,x1,-50" *) + val hex_code = String.map Char.toUpper "340110F3"; (* CSR *) + val hex_code = String.map Char.toUpper "00E13423"; (* Working store *) val hex_code_desc = hex_code; val (next_thms, mm_tm, label_tm) = mk_inst_lifting_theorems hex_code hex_code_desc @@ -245,8 +247,9 @@ open bir_inst_liftingLibTypes val (preconds, next_tm) = strip_imp_only (concl next_thm0) val tm = (* Put term returned by exception here, don't forget type information... *) -val tm = ``Imm64 - (w2w ((riscv_mem_half ms.MEM8 (ms.c_gpr ms.procID 2w - 50w)):word16))``; +(* Examples: *) +val tm = ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w``; +val tm = ``aligned 3 (ms.c_gpr ms.procID 2w)``; (* In case of several preconds, continue with the following for 2, 3, 4, ...*) (* val tm = el 2 preconds *) @@ -444,7 +447,9 @@ fun get_patched_step_hex ms_v hex_code = in (* For debugging RISC-V: - val hex_code = String.map Char.toUpper "00E13423"; + val hex_code = String.map Char.toUpper "00E13423"; (* Working store *) + + val hex_code = String.map Char.toUpper "340110F3"; (* Non-working CSR instr *) val hex_code_desc = hex_code; val (next_thms, mm_tm, label_tm) = mk_inst_lifting_theorems hex_code hex_code_desc val (lb, ms_case_cond_t, next_thm) = el 1 (preprocess_next_thms label_tm next_thms) @@ -459,7 +464,7 @@ fun get_patched_step_hex ms_v hex_code = val ms'_t = rand (rhs (next_tm)) (* lift all preconds *) - (* TODO: Should the below be empty list? *) + (* TODO: Something goes wrong here... *) val lift_thms = map exp_lift_fn preconds val assert_ok_thms = map (MATCH_MP bir_assert_desc_OK_via_lifting) lift_thms val al_step_l = map (fn thm => (rand (concl thm))) assert_ok_thms @@ -1157,10 +1162,11 @@ fun get_patched_step_hex ms_v hex_code = val (lb, ms_case_cond_t, next_thm) = el 1 sub_block_work_list *) -(* For debugging RISC-V: +(* For debugging RISC-V from scratch: val (mu_thm:thm, mm_precond_thm:thm) = test_RISCV.bir_lift_instr_prepare_mu_thms (mu_b, mu_e) - val hex_code = String.map Char.toUpper "007302B3"; + val hex_code = String.map Char.toUpper "340110F3"; (* CSR *) + val hex_code = String.map Char.toUpper "00E13423"; (* Working Store *) val hex_code_desc = hex_code; val (next_thms, mm_tm, label_tm) = mk_inst_lifting_theorems hex_code hex_code_desc val bir_is_lifted_inst_block_COMPUTE_precond_tm_mr = @@ -1204,6 +1210,7 @@ fun get_patched_step_hex ms_v hex_code = fun raiseErr s = raise (bir_inst_liftingAuxExn (BILED_msg s)); (* compute ms' and al_step *) + (* TODO: CSR: Something goes wrong here... *) val (ms'_t, al_step_t, ms'_thm) = compute_al_step_ms' next_thm0 handle HOL_ERR _ => raiseErr "computing al_step and ms' failed"; @@ -1365,15 +1372,16 @@ fun get_patched_step_hex ms_v hex_code = (* For debugging RISC-V: val (mu_thm:thm, mm_precond_thm:thm) = test_RISCV.bir_lift_instr_prepare_mu_thms (mu_b, mu_e) - val hex_code = String.map Char.toUpper "007302B3"; + val hex_code = String.map Char.toUpper "340110F3"; + val hex_code_desc = hex_code; + + val hex_code = String.map Char.toUpper "00E13423"; val hex_code_desc = hex_code; *) fun bir_lift_instr_mu_gen_pc_compute (mu_thm:thm, mm_precond_thm : thm) hex_code hex_code_desc = let (* call step lib to generate step theorems, compute mm and label *) - (* TODO: Does this work correctly for RISC-V? Probably, but usage of "+=" as "assign" is funny. - * Also see if it is necessary to use a static procID. *) val (next_thms, mm_tm, label_tm) = mk_inst_lifting_theorems hex_code hex_code_desc (* instantiate inst theorem *) @@ -1407,7 +1415,7 @@ fun get_patched_step_hex ms_v hex_code = handle HOL_ERR _ => raise bir_inst_liftingAuxExn (BILED_msg ("preprocessing next theorems failed")); - (* TODO: Here, something fails... *) + (* TODO: Something goes wrong here... *) val sub_block_thms = map (lift_single_block inst_lift_thm0 bir_is_lifted_inst_block_COMPUTE_precond_tm0 mu_thm) sub_block_work_list val prog_thm = merge_block_thms sub_block_thms handle HOL_ERR _ => diff --git a/src/tools/lifter/selftestLib.sml b/src/tools/lifter/selftestLib.sml index ef4fb5aea..e4893a0a0 100644 --- a/src/tools/lifter/selftestLib.sml +++ b/src/tools/lifter/selftestLib.sml @@ -169,18 +169,22 @@ end; | (NONE, SOME d') => (" (* " ^ (bir_inst_liftingExn_data_to_string d') ^ " *)") | (SOME d, SOME d') => (" (* " ^ d ^ "; "^(bir_inst_liftingExn_data_to_string d') ^ " *)"); - fun print_failed [] = () - | print_failed ((hex_code, desc, ed_opt, broken)::l) = - let - (* print the ones that failed, but were not excepted to in red *) - val st = if broken then sty_FAIL else []; - val _ = print_log true " "; - val _ = print_log_with_style st true ("\""^hex_code^"\""); - - val _ = print_log_with_style st true (comment_of_failing desc ed_opt) - - in if List.null l then (print_log true "\n]\n\n") else - (print_log true ",\n"; print_failed l) + local + fun print_failed' [] = () + | print_failed' ((hex_code, desc, ed_opt, broken)::l) = + let + (* print the ones that failed, but were not excepted to in red *) + val st = if broken then selftestLib.sty_FAIL else []; + val _ = print_log true " "; + val _ = print_log_with_style st true ("\""^hex_code^"\""); + + val _ = print_log_with_style st true (comment_of_failing desc ed_opt) + + in if List.null l then (print_log true "\n]\n\n") else + (print_log true ",\n"; print_failed' l) + end + in + fun print_failed failing_l = print_failed' (rev failing_l) end; val _ = if List.null failing_l' then () else (print "[\n"; print_failed failing_l'); diff --git a/src/tools/lifter/selftest_riscv.log b/src/tools/lifter/selftest_riscv.log index a364b40b8..252614fa0 100644 --- a/src/tools/lifter/selftest_riscv.log +++ b/src/tools/lifter/selftest_riscv.log @@ -928,22 +928,22 @@ FENCE.I x0, x0, 0: 0000100F @ 0x10030 - FAILED RV64 Zicsr Standard Extension CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - FAILED - lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed + computing al_step and ms' failed RV64M Standard Extension (instructions inherited from RV32M) @@ -1294,16 +1294,16 @@ SUMMARY FAILING HEXCODES RISC-V Instructions FAILED: 10/77 - "3400F0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "3400E0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "3400D0F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "340130F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "340120F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "340110F3" (* lifting of ``(ms.c_MCSR ms.procID).mstatus.MPRV = 3w`` failed *), - "0000100F" (* bmr_step_hex failed *), - "00100073" (* bmr_step_hex failed *), + "0881008F" (* bmr_step_hex failed *), "00000073" (* bmr_step_hex failed *), - "0881008F" (* bmr_step_hex failed *) + "00100073" (* bmr_step_hex failed *), + "0000100F" (* bmr_step_hex failed *), + "340110F3" (* computing al_step and ms' failed *), + "340120F3" (* computing al_step and ms' failed *), + "340130F3" (* computing al_step and ms' failed *), + "3400D0F3" (* computing al_step and ms' failed *), + "3400E0F3" (* computing al_step and ms' failed *), + "3400F0F3" (* computing al_step and ms' failed *) ] Instructions FIXED: 0 From 4d178e48962b7b71b56ba038e65449d353c9961a Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Wed, 28 Oct 2020 13:59:45 +0100 Subject: [PATCH 05/14] CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI and CSRRCI instructions now lifting properly for mscratch --- .../tools/lifter/bir_riscv_extrasScript.sml | 89 +++++++++-- .../bir_lifting_machinesLib_instances.sml | 3 +- src/tools/lifter/selftest_riscv.log | 144 +++++++++++++++--- 3 files changed, 198 insertions(+), 38 deletions(-) diff --git a/src/theory/tools/lifter/bir_riscv_extrasScript.sml b/src/theory/tools/lifter/bir_riscv_extrasScript.sml index 04ca6952d..aef144125 100644 --- a/src/theory/tools/lifter/bir_riscv_extrasScript.sml +++ b/src/theory/tools/lifter/bir_riscv_extrasScript.sml @@ -799,30 +799,85 @@ end) (* Lifting 2-word predicates *) (* (related to system register entries) *) (****************************************) - (* This is a very ugly solution, since we don't have 2-bit * immediates... *) -(* TODO: Instantiate this with all possible concrete values *) -val riscv_is_lifted_imm_exp_2EQ = store_thm ("riscv_is_lifted_imm_exp_2EQ", - ``!env w1 e1 e2. +(* TODO: Do the same for 5-bit immediates (mstatus.VM) *) + +(* For specialisation of theorem with concrete values. + * Apparently it doesn't work with an abstract :word2... *) +local + fun power b e = + if e = 0 + then 1 + else b * power b (e-1); + + fun specialise_word' word_size thm 0 thm_acc = + let + val word = wordsSyntax.mk_wordii(0, word_size) + val new_thm = + SPEC word thm + in + (new_thm::thm_acc) + end + | specialise_word' word_size thm value thm_acc = + let + val word = wordsSyntax.mk_wordii(value, word_size) + val new_thm = + SPEC word thm + in + specialise_word' word_size thm (value-1) (new_thm::thm_acc) + end + +in +fun specialise_word thm = + let + val word_size = + (Arbnum.toInt o wordsSyntax.size_of o fst o + dest_forall o concl) thm + val max_val = (power 2 word_size) - 1 + in + LIST_CONJ (specialise_word' word_size thm max_val []) + end +end; + +val riscv_is_lifted_imm_exp_2EQ_GEN = + store_thm ("riscv_is_lifted_imm_exp_2EQ_GEN", + ``!w2 env w1 e1 e2. bir_is_lifted_imm_exp env e1 (Imm8 (w2w w1)) ==> - bir_is_lifted_imm_exp env e2 (Imm8 3w) ==> + bir_is_lifted_imm_exp env e2 (Imm8 (w2w w2)) ==> bir_is_lifted_imm_exp env (BExp_BinPred BIExp_Equal e1 e2) - (bool2b (w1 = (3w:word2)))``, + (bool2b (w1 = (w2:word2)))``, -cheat +wordsLib.Cases_word_value >> ( + SIMP_TAC (std_ss++holBACore_ss) [bir_is_lifted_imm_exp_def, + bir_env_oldTheory.bir_env_vars_are_initialised_UNION, + BType_Bool_def] >> + blastLib.BBLAST_TAC +) ); -(* -val w2w_word2_to_word8 = store_thm ("w2w_word2_to_word8", - ``((w2w (0w:word2)):word8) = (0w:word8) /\ - ((w2w (1w:word2)):word8) = (1w:word8) /\ - ((w2w (2w:word2)):word8) = (2w:word8) /\ - ((w2w (3w:word2)):word8) = (3w:word8)``, +val riscv_is_lifted_imm_exp_2EQ = + SIMP_RULE (std_ss++wordsLib.WORD_ss) [] (specialise_word riscv_is_lifted_imm_exp_2EQ_GEN); -blastLib.BBLAST_TAC +(* 0 -> 31 *) +val riscv_is_lifted_imm_exp_5EQ_GEN = + store_thm ("riscv_is_lifted_imm_exp_5EQ_GEN", + ``!w2 env w1 e1 e2. + bir_is_lifted_imm_exp env e1 (Imm8 (w2w w1)) ==> + bir_is_lifted_imm_exp env e2 (Imm8 (w2w w2)) ==> + bir_is_lifted_imm_exp env (BExp_BinPred BIExp_Equal e1 e2) + (bool2b (w1 = (w2:word5)))``, + +wordsLib.Cases_word_value >> ( + SIMP_TAC (std_ss++holBACore_ss) [bir_is_lifted_imm_exp_def, + bir_env_oldTheory.bir_env_vars_are_initialised_UNION, + BType_Bool_def] >> + blastLib.BBLAST_TAC +) ); -*) + +val riscv_is_lifted_imm_exp_5EQ = + SIMP_RULE (std_ss++wordsLib.WORD_ss) [] (specialise_word riscv_is_lifted_imm_exp_5EQ_GEN); (*******************************************************) (* RISC-V predicates are usually cast to 64-bit format *) @@ -890,7 +945,9 @@ Theorem riscv_extra_LIFTS = LIST_CONJ [ riscv_is_lifted_imm_exp_64MSBs, riscv_is_lifted_imm_exp_GE, riscv_is_lifted_imm_exp_GEU, - riscv_is_lifted_imm_exp_2EQ] + (* CSR stuff *) + riscv_is_lifted_imm_exp_2EQ, + riscv_is_lifted_imm_exp_5EQ] Theorem riscv_CHANGE_INTERVAL_THMS = LIST_CONJ [riscv_LIFT_STORE_DWORD_CHANGE_INTERVAL, diff --git a/src/tools/lifter/bir_lifting_machinesLib_instances.sml b/src/tools/lifter/bir_lifting_machinesLib_instances.sml index bfbea4e15..80c42194f 100644 --- a/src/tools/lifter/bir_lifting_machinesLib_instances.sml +++ b/src/tools/lifter/bir_lifting_machinesLib_instances.sml @@ -619,7 +619,8 @@ val _ = assert bmr_rec_sanity_check (m0_mod_bmr_rec_LittleEnd_Main) (* Type rewrites as a list of theorems (ARM8 also had rewrites * for ``:ProcState``)... *) val riscv_REWRS = ( - (type_rws ``:riscv_state``) + (type_rws ``:riscv_state``)@ + (type_rws ``:MachineCSR``) ); (* ... and as a simplification set. *) diff --git a/src/tools/lifter/selftest_riscv.log b/src/tools/lifter/selftest_riscv.log index 252614fa0..54d519499 100644 --- a/src/tools/lifter/selftest_riscv.log +++ b/src/tools/lifter/selftest_riscv.log @@ -927,23 +927,125 @@ FENCE.I x0, x0, 0: 0000100F @ 0x10030 - FAILED RV64 Zicsr Standard Extension -CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 16w; 1w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "340110F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_Den (BVar "x2" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) -CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 32w; 1w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "340120F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_BinExp BIExp_Or + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) + (BExp_Den (BVar "x2" (BType_Imm Bit64))))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) -CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 48w; 1w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "340130F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_BinExp BIExp_And + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) + (BExp_BinExp BIExp_Minus + (BExp_BinExp BIExp_Mult + (BExp_Const (Imm64 18446744073709551615w)) + (BExp_Den (BVar "x2" (BType_Imm Bit64)))) + (BExp_Const (Imm64 1w))))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) -CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 208w; 0w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "3400D0F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_Const (Imm64 1w))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) -CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 224w; 0w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "3400E0F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_BinExp BIExp_Or + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) + (BExp_Const (Imm64 1w)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) -CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - FAILED - computing al_step and ms' failed +CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) + (65584w,[243w; 240w; 0w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 65584w) "3400F0F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x1" (BType_Imm Bit64)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); + BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) + (BExp_BinExp BIExp_And + (BExp_Const (Imm64 18446744073709551614w)) + (BExp_Den (BVar "mscratch" (BType_Imm Bit64))))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) RV64M Standard Extension (instructions inherited from RV32M) @@ -1292,22 +1394,22 @@ REMUW x5, x6, x7: 027372BB @ 0x10030 - OK SUMMARY FAILING HEXCODES RISC-V -Instructions FAILED: 10/77 +Instructions FAILED: 4/72 "0881008F" (* bmr_step_hex failed *), "00000073" (* bmr_step_hex failed *), "00100073" (* bmr_step_hex failed *), - "0000100F" (* bmr_step_hex failed *), - "340110F3" (* computing al_step and ms' failed *), - "340120F3" (* computing al_step and ms' failed *), - "340130F3" (* computing al_step and ms' failed *), - "3400D0F3" (* computing al_step and ms' failed *), - "3400E0F3" (* computing al_step and ms' failed *), - "3400F0F3" (* computing al_step and ms' failed *) + "0000100F" (* bmr_step_hex failed *) ] -Instructions FIXED: 0 +Instructions FIXED: 6 + 340110F3 + 340120F3 + 340130F3 + 3400D0F3 + 3400E0F3 + 3400F0F3 Instructions BROKEN: 0 From 10ace80249704a96e8d2a864b554e07dccbc7180 Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Wed, 28 Oct 2020 14:15:51 +0100 Subject: [PATCH 06/14] Typos --- src/tools/lifter/selftest_riscv.log | 10 ++---- src/tools/lifter/selftest_riscv.sml | 56 +++++------------------------ 2 files changed, 11 insertions(+), 55 deletions(-) diff --git a/src/tools/lifter/selftest_riscv.log b/src/tools/lifter/selftest_riscv.log index 54d519499..6af9da80c 100644 --- a/src/tools/lifter/selftest_riscv.log +++ b/src/tools/lifter/selftest_riscv.log @@ -1402,14 +1402,8 @@ Instructions FAILED: 4/72 "0000100F" (* bmr_step_hex failed *) ] -Instructions FIXED: 6 - - 340110F3 - 340120F3 - 340130F3 - 3400D0F3 - 3400E0F3 - 3400F0F3 +Instructions FIXED: 0 + Instructions BROKEN: 0 diff --git a/src/tools/lifter/selftest_riscv.sml b/src/tools/lifter/selftest_riscv.sml index afef5d575..5f1bcb2d8 100644 --- a/src/tools/lifter/selftest_riscv.sml +++ b/src/tools/lifter/selftest_riscv.sml @@ -73,10 +73,9 @@ val _ = print_header "RV64I Base Instruction Set (instructions inherited from RV val _ = print_msg "\n\n"; (* Good presentation of RISC-V instructions at https://inst.eecs.berkeley.edu/~cs61c/sp19/lectures/lec05.pdf *) (* 75 instructions in initial scope (including M extension) *) -(* 10 still TODO: +(* 4 still TODO: * 2 fences - * environment call and breakpoint - * 6 CSR instructions *) + * environment call and breakpoint *) (* TODO: Instructions from privileged instruction set: MRET (exists in latest L3 version), SRET (S ext., exists in latest L3 version), URET (N ext., exists in latest L3 version) *) (* TODO: Most important extensions: A (atomics), C (compressed) *) (* TODO: Are NOPs in riscv_stepLib correct? *) @@ -310,47 +309,17 @@ val _ = print_msg "\n\n"; (* CSR instructions (opcode SYSTEM) *) (* TODO: Note that machine mode is currently assumed for these instructions * (see bottom of riscv_stepScript.sml) *) -(* CSRRW x1, mscratch(0x340), x2 : 001101000000 00010 001000011110011 - - open riscv_stepLib; - val _ = riscv_step_hex "340110F3"; - -*) +(* CSRRW x1, mscratch(0x340), x2 : 001101000000 00010 001000011110011 *) val _ = riscv_test_hex_print_asm "CSRRW x1, mscratch(0x340), x2" "340110F3"; -(* CSRRS x1, mscratch(0x340), x2 : 001101000000 00010 010000011110011 - - open riscv_stepLib; - val test = riscv_step_hex "340120F3"; - -*) +(* CSRRS x1, mscratch(0x340), x2 : 001101000000 00010 010000011110011 *) val _ = riscv_test_hex_print_asm "CSRRS x1, mscratch(0x340), x2" "340120F3"; -(* CSRRC x1, mscratch(0x340), x2 : 001101000000 00010 011000011110011 - - open riscv_stepLib; - val test = riscv_step_hex "340130F3"; - -*) +(* CSRRC x1, mscratch(0x340), x2 : 001101000000 00010 011000011110011 *) val _ = riscv_test_hex_print_asm "CSRRC x1, mscratch(0x340), x2" "340130F3"; -(* CSRRWI x1, mscratch(0x340), 0x1 : 001101000000 00001 101 000011110011 - - open riscv_stepLib; - val _ = riscv_step_hex "3400D0F3"; - -*) +(* CSRRWI x1, mscratch(0x340), 0x1 : 001101000000 00001 101 000011110011 *) val _ = riscv_test_hex_print_asm "CSRRWI x1, mscratch(0x340), 0x1" "3400D0F3"; -(* CSRRSI x1, mscratch(0x340), 0x1 : 001101000000 00001 110 00001 1110011 - - open riscv_stepLib; - val test = riscv_step_hex "3400E0F3"; - -*) +(* CSRRSI x1, mscratch(0x340), 0x1 : 001101000000 00001 110 00001 1110011 *) val _ = riscv_test_hex_print_asm "CSRRSI x1, mscratch(0x340), 0x1" "3400E0F3"; -(* CSRRCI x1, mscratch(0x340), 0x1 : 001101000000 00001 111 000011110011 - - open riscv_stepLib; - val test = riscv_step_hex "3400F0F3"; - -*) +(* CSRRCI x1, mscratch(0x340), 0x1 : 001101000000 00001 111 000011110011 *) val _ = riscv_test_hex_print_asm "CSRRCI x1, mscratch(0x340), 0x1" "3400F0F3"; val _ = print_msg "\n"; @@ -403,14 +372,7 @@ val riscv_expected_failed_hexcodes:string list = "00000073" (* ECALL *), "00100073" (* EBREAK *), (* Zifencei *) - "0000100F" (* FENCE.I *), - (* Zicsr *) - "340110F3" (* CSRRW x1, mscratch(0x340), x2 *), - "340120F3" (* CSRRS x1, mscratch(0x340), x2 *), - "340130F3" (* CSRRC x1, mscratch(0x340), x2 *), - "3400D0F3" (* CSRRWI x1, mscratch(0x340), 0x1 *), - "3400E0F3" (* CSRRWI x1, mscratch(0x340), 0x1 *), - "3400F0F3" (* CSRRCI x1, mscratch(0x340), 0x1 *) + "0000100F" (* FENCE.I *) ]; val _ = test_RISCV.final_results "RISC-V" riscv_expected_failed_hexcodes; From cae4f3ed3ed3a9e4daefa8ce62d5180074d2955e Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Mon, 2 Dec 2024 11:39:48 +0100 Subject: [PATCH 07/14] Fixing rebase typo --- src/tools/lifter/selftestLib.sml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/tools/lifter/selftestLib.sml b/src/tools/lifter/selftestLib.sml index e4893a0a0..37100fa21 100644 --- a/src/tools/lifter/selftestLib.sml +++ b/src/tools/lifter/selftestLib.sml @@ -146,7 +146,7 @@ end; fun final_results name expected_failed_hexcodes = let val _ = print_log true "\n\n\n"; - val _ = print_log_with_style selftestLib.sty_HEADER true ("SUMMARY FAILING HEXCODES " ^ name); + val _ = print_log_with_style sty_HEADER true ("SUMMARY FAILING HEXCODES " ^ name); val _ = print_log true "\n\n\n"; val failing_l = op_mk_set (fn (x, _, _) => fn (y, _, _) => (x = y)) (!failed_hexcodes_list) val ok_l = op_mk_set (fn (x, _, _) => fn (y, _, _) => (x = y)) (!success_hexcodes_list) @@ -174,7 +174,7 @@ end; | print_failed' ((hex_code, desc, ed_opt, broken)::l) = let (* print the ones that failed, but were not excepted to in red *) - val st = if broken then selftestLib.sty_FAIL else []; + val st = if broken then sty_FAIL else []; val _ = print_log true " "; val _ = print_log_with_style st true ("\""^hex_code^"\""); From f922ca75ca8a5f53b8815e499d70781940949d9f Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Mon, 2 Dec 2024 15:32:16 +0100 Subject: [PATCH 08/14] Typo fix + backlifter fix for latest RISC-V L3 model --- .../backlifter/bir_riscv_backlifterScript.sml | 120 +++++++++++++++++- .../lifter/bir_lifting_machinesScript.sml | 29 +++-- 2 files changed, 130 insertions(+), 19 deletions(-) diff --git a/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml b/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml index a566ec229..605503b5e 100644 --- a/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml +++ b/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml @@ -408,15 +408,31 @@ Definition default_riscv_bir_env_GPRS_tmp_def: env_map))))))))))))))))))))))))))))))) End +Definition default_riscv_bir_env_CSRS_def: + default_riscv_bir_env_CSRS ms env_map = + ("MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) + (("mscratch" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mscratch )))) + env_map) +End + +Definition default_riscv_bir_env_CSRS_tmp_def: + default_riscv_bir_env_CSRS_tmp ms env_map = + ("tmp_MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) + (("tmp_mscratch" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mscratch )))) + env_map) +End + Definition default_riscv_bir_state_def: default_riscv_bir_state ms = <| bst_pc := bir_block_pc (BL_Address (Imm64 (ms.c_PC ms.procID))) ; bst_environ := BEnv - (default_riscv_bir_env_GPRS ms - (default_riscv_bir_env_GPRS_tmp ms - (default_riscv_bir_env_FPRS ms - (default_riscv_bir_env_FPRS_tmp ms - (default_riscv_bir_env_basic ms bir_env_map_empty))))); + (default_riscv_bir_env_CSRS ms + (default_riscv_bir_env_CSRS_tmp ms + (default_riscv_bir_env_GPRS ms + (default_riscv_bir_env_GPRS_tmp ms + (default_riscv_bir_env_FPRS ms + (default_riscv_bir_env_FPRS_tmp ms + (default_riscv_bir_env_basic ms bir_env_map_empty))))))); bst_status := BST_Running |> End @@ -489,6 +505,8 @@ Theorem default_riscv_bir_state_GPRS_read[local]: SOME (BVal_Imm (Imm64 (ms.c_gpr ms.procID 31w))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, bir_envTheory.bir_env_read_UPDATE, bir_envTheory.bir_var_name_def, @@ -567,6 +585,8 @@ Theorem default_riscv_bir_state_GPRS_read_tmp[local]: SOME (BVal_Imm (Imm64 (ms.c_gpr ms.procID 31w))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, bir_envTheory.bir_env_read_UPDATE, @@ -646,6 +666,8 @@ Theorem default_riscv_bir_state_GPRS_lookup_type[local]: SOME (bir_var_type (BVar "x31" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, bir_env_oldTheory.bir_env_var_is_declared_def, bir_envTheory.bir_var_name_def, @@ -726,6 +748,8 @@ Theorem default_riscv_bir_state_GPRS_lookup_type_tmp[local]: SOME (bir_var_type (BVar "tmp_x31" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, bir_env_oldTheory.bir_env_var_is_declared_def, @@ -807,6 +831,8 @@ Theorem default_riscv_bir_state_FPRS_read[local]: SOME (BVal_Imm (Imm64 (ms.c_fpr ms.procID 31w))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -887,6 +913,8 @@ Theorem default_riscv_bir_state_FPRS_read_tmp[local]: SOME (BVal_Imm (Imm64 (ms.c_fpr ms.procID 31w))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -968,6 +996,8 @@ Theorem default_riscv_bir_state_FPRS_lookup_type[local]: SOME (bir_var_type (BVar "f31" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -1050,6 +1080,8 @@ Theorem default_riscv_bir_state_FPRS_lookup_type_tmp[local]: SOME (bir_var_type (BVar "tmp_f31" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -1065,12 +1097,85 @@ Proof type_of_bir_imm_def] QED +Theorem default_riscv_bir_state_MCSRS_read[local]: + !ms. + bir_env_read (BVar "MPRV" (BType_Imm Bit8)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm8 (w2w (ms.c_MCSR ms.procID).mstatus.MPRV))) /\ + bir_env_read (BVar "mscratch" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mscratch)) +Proof + rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, + default_riscv_bir_env_GPRS_def, + default_riscv_bir_env_GPRS_tmp_def, + default_riscv_bir_env_FPRS_def, + bir_envTheory.bir_env_read_UPDATE, + bir_envTheory.bir_var_name_def, + bir_envTheory.bir_env_lookup_UPDATE, + bir_envTheory.bir_var_type_def, + bir_valuesTheory.type_of_bir_val_def, + type_of_bir_imm_def, + bir_immTheory.type_of_bool2b] +QED + +Theorem default_riscv_bir_state_MCSRS_lookup_type[local]: + !ms. + bir_env_lookup_type "MPRV" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "MPRV" (BType_Imm Bit8))) /\ + bir_env_lookup_type "mscratch" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mscratch" (BType_Imm Bit64))) +Proof + rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, + default_riscv_bir_env_GPRS_def, + default_riscv_bir_env_GPRS_tmp_def, + default_riscv_bir_env_FPRS_def, + bir_env_oldTheory.bir_env_var_is_declared_def, + bir_envTheory.bir_var_name_def, + bir_envTheory.bir_env_read_UPDATE, + bir_envTheory.bir_var_name_def, + bir_envTheory.bir_env_lookup_UPDATE, + bir_envTheory.bir_var_type_def, + bir_envTheory.bir_env_lookup_type_def, + bir_valuesTheory.type_of_bir_val_def, + type_of_bir_imm_def] +QED + +Theorem default_riscv_bir_state_MCSRS_lookup_type_tmp[local]: + !ms. + bir_env_lookup_type "tmp_MPRV" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_MPRV" (BType_Imm Bit8))) /\ + bir_env_lookup_type "tmp_mscratch" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mscratch" (BType_Imm Bit64))) +Proof + rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, + default_riscv_bir_env_GPRS_def, + default_riscv_bir_env_GPRS_tmp_def, + default_riscv_bir_env_FPRS_def, + bir_env_oldTheory.bir_env_var_is_declared_def, + bir_envTheory.bir_var_name_def, + bir_envTheory.bir_env_read_UPDATE, + bir_envTheory.bir_var_name_def, + bir_envTheory.bir_env_lookup_UPDATE, + bir_envTheory.bir_var_type_def, + bir_envTheory.bir_env_lookup_type_def, + bir_valuesTheory.type_of_bir_val_def, + type_of_bir_imm_def] +QED + + Theorem default_riscv_bir_state_basic_env_read[local]: !ms. bir_env_read (BVar "MEM8" (BType_Mem Bit64 Bit8)) (default_riscv_bir_state ms).bst_environ = SOME (BVal_Mem Bit64 Bit8 (bir_mmap_w_w2n (bir_mf2mm ms.MEM8))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -1095,6 +1200,8 @@ Theorem default_riscv_bir_state_basic_lookup_type[local]: SOME (bir_var_type (BVar "tmp_COND" (BType_Imm Bit1))) Proof rw [default_riscv_bir_state_def, + default_riscv_bir_env_CSRS_def, + default_riscv_bir_env_CSRS_tmp_def, default_riscv_bir_env_GPRS_def, default_riscv_bir_env_GPRS_tmp_def, default_riscv_bir_env_FPRS_def, @@ -1119,6 +1226,9 @@ strip_tac >> strip_tac >> FULL_SIMP_TAC std_ss [bir_lifting_machinesTheory.riscv_bmr_rel_EVAL, bir_env_oldTheory.bir_env_var_is_declared_def,bir_envTheory.bir_var_name_def] >> fs [ + default_riscv_bir_state_MCSRS_read, + default_riscv_bir_state_MCSRS_lookup_type, + default_riscv_bir_state_MCSRS_lookup_type_tmp, default_riscv_bir_state_GPRS_read, default_riscv_bir_state_GPRS_read_tmp, default_riscv_bir_state_GPRS_lookup_type, diff --git a/src/theory/tools/lifter/bir_lifting_machinesScript.sml b/src/theory/tools/lifter/bir_lifting_machinesScript.sml index d11d69675..4eafd9e29 100644 --- a/src/theory/tools/lifter/bir_lifting_machinesScript.sml +++ b/src/theory/tools/lifter/bir_lifting_machinesScript.sml @@ -616,20 +616,21 @@ End * TCR: Translation Control Register; for EL1, EL2 and EL3. Determines * Translation Table Base Register. *) Definition arm8_state_is_OK_def: - (* Explicit data accesses at EL0 MUST be little-endian. *) - ~ms.SCTLR_EL1.E0E /\ - (* Exception level must be 0 (user) *) - (ms.PSTATE.EL = 0w) /\ - (* Exception must be NoException (as opposed to ALIGNMENT_FAULT, - * UNDEFINED_FAULT and ASSERT).*) - (ms.exception = NoException) /\ - (* Stack Alignment Check MUST NOT be enabled for EL0. *) - ~ms.SCTLR_EL1.SA0 /\ - (* Translation control register for EL1 must not be TBI0 or TBI1, - * meaning it must be "tcr_el1'rst", which is a 62-bit field. - * TODO: What is TBI0 and TBI1? *) - ~ms.TCR_EL1.TBI0 /\ - ~ms.TCR_EL1.TBI1 + arm8_state_is_OK (ms:arm8_state) <=> + (* Explicit data accesses at EL0 MUST be little-endian. *) + ~ms.SCTLR_EL1.E0E /\ + (* Exception level must be 0 (user) *) + (ms.PSTATE.EL = 0w) /\ + (* Exception must be NoException (as opposed to ALIGNMENT_FAULT, + * UNDEFINED_FAULT and ASSERT).*) + (ms.exception = NoException) /\ + (* Stack Alignment Check MUST NOT be enabled for EL0. *) + ~ms.SCTLR_EL1.SA0 /\ + (* Translation control register for EL1 must not be TBI0 or TBI1, + * meaning it must be "tcr_el1'rst", which is a 62-bit field. + * TODO: What is TBI0 and TBI1? *) + ~ms.TCR_EL1.TBI0 /\ + ~ms.TCR_EL1.TBI1 End Definition arm8_bmr_def: From 9a76df95e63d4a1ea43b4fce8f83854b4b5e780c Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Thu, 5 Dec 2024 15:26:01 +0100 Subject: [PATCH 09/14] Added support for more CSR registers in RISC-V lifter and backlifter --- .../backlifter/bir_riscv_backlifterScript.sml | 58 ++++++-- .../lifter/bir_lifting_machinesScript.sml | 15 ++ src/tools/lifter/examples/Holmakefile | 2 +- src/tools/lifter/selftest_riscv.log | 134 ++++++++++++++---- src/tools/lifter/selftest_riscv.sml | 20 +++ 5 files changed, 192 insertions(+), 37 deletions(-) diff --git a/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml b/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml index 605503b5e..f37242f58 100644 --- a/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml +++ b/src/theory/tools/backlifter/bir_riscv_backlifterScript.sml @@ -410,16 +410,26 @@ End Definition default_riscv_bir_env_CSRS_def: default_riscv_bir_env_CSRS ms env_map = - ("MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) + ("mhartid" =+ SOME (BVal_Imm (Imm64 ( ((ms.c_MCSR ms.procID).mhartid) )))) + (("MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) (("mscratch" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mscratch )))) - env_map) + (("mepc" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mepc )))) + (("mcause" =+ SOME (BVal_Imm (Imm64 ( reg'mcause $ (ms.c_MCSR ms.procID).mcause )))) + (("mtval" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mtval )))) + (("mip" =+ SOME (BVal_Imm (Imm64 ( reg'mip $ (ms.c_MCSR ms.procID).mip )))) + env_map)))))) End Definition default_riscv_bir_env_CSRS_tmp_def: default_riscv_bir_env_CSRS_tmp ms env_map = - ("tmp_MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) + ("tmp_mhartid" =+ SOME (BVal_Imm (Imm64 ( ((ms.c_MCSR ms.procID).mhartid) )))) + (("tmp_MPRV" =+ SOME (BVal_Imm (Imm8 ( w2w((ms.c_MCSR ms.procID).mstatus.MPRV) )))) (("tmp_mscratch" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mscratch )))) - env_map) + (("tmp_mepc" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mepc )))) + (("tmp_mcause" =+ SOME (BVal_Imm (Imm64 ( reg'mcause $ (ms.c_MCSR ms.procID).mcause )))) + (("tmp_mtval" =+ SOME (BVal_Imm (Imm64 ( (ms.c_MCSR ms.procID).mtval )))) + (("tmp_mip" =+ SOME (BVal_Imm (Imm64 ( reg'mip $ (ms.c_MCSR ms.procID).mip )))) + env_map)))))) End Definition default_riscv_bir_state_def: @@ -1099,10 +1109,20 @@ QED Theorem default_riscv_bir_state_MCSRS_read[local]: !ms. + bir_env_read (BVar "mhartid" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mhartid)) /\ bir_env_read (BVar "MPRV" (BType_Imm Bit8)) (default_riscv_bir_state ms).bst_environ = SOME (BVal_Imm (Imm8 (w2w (ms.c_MCSR ms.procID).mstatus.MPRV))) /\ bir_env_read (BVar "mscratch" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = - SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mscratch)) + SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mscratch)) /\ + bir_env_read (BVar "mepc" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mepc)) /\ + bir_env_read (BVar "mcause" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 $ reg'mcause (ms.c_MCSR ms.procID).mcause)) /\ + bir_env_read (BVar "mtval" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 (ms.c_MCSR ms.procID).mtval)) /\ + bir_env_read (BVar "mip" (BType_Imm Bit64)) (default_riscv_bir_state ms).bst_environ = + SOME (BVal_Imm (Imm64 $ reg'mip (ms.c_MCSR ms.procID).mip)) Proof rw [default_riscv_bir_state_def, default_riscv_bir_env_CSRS_def, @@ -1121,10 +1141,20 @@ QED Theorem default_riscv_bir_state_MCSRS_lookup_type[local]: !ms. + bir_env_lookup_type "mhartid" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mhartid" (BType_Imm Bit64))) /\ bir_env_lookup_type "MPRV" (default_riscv_bir_state ms).bst_environ = - SOME (bir_var_type (BVar "MPRV" (BType_Imm Bit8))) /\ + SOME (bir_var_type (BVar "MPRV" (BType_Imm Bit8))) /\ bir_env_lookup_type "mscratch" (default_riscv_bir_state ms).bst_environ = - SOME (bir_var_type (BVar "mscratch" (BType_Imm Bit64))) + SOME (bir_var_type (BVar "mscratch" (BType_Imm Bit64))) /\ + bir_env_lookup_type "mepc" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mepc" (BType_Imm Bit64))) /\ + bir_env_lookup_type "mcause" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mcause" (BType_Imm Bit64))) /\ + bir_env_lookup_type "mtval" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mtval" (BType_Imm Bit64))) /\ + bir_env_lookup_type "mip" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "mip" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, default_riscv_bir_env_CSRS_def, @@ -1145,10 +1175,20 @@ QED Theorem default_riscv_bir_state_MCSRS_lookup_type_tmp[local]: !ms. + bir_env_lookup_type "tmp_mhartid" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mhartid" (BType_Imm Bit64))) /\ bir_env_lookup_type "tmp_MPRV" (default_riscv_bir_state ms).bst_environ = - SOME (bir_var_type (BVar "tmp_MPRV" (BType_Imm Bit8))) /\ + SOME (bir_var_type (BVar "tmp_MPRV" (BType_Imm Bit8))) /\ bir_env_lookup_type "tmp_mscratch" (default_riscv_bir_state ms).bst_environ = - SOME (bir_var_type (BVar "tmp_mscratch" (BType_Imm Bit64))) + SOME (bir_var_type (BVar "tmp_mscratch" (BType_Imm Bit64))) /\ + bir_env_lookup_type "tmp_mepc" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mepc" (BType_Imm Bit64))) /\ + bir_env_lookup_type "tmp_mcause" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mcause" (BType_Imm Bit64))) /\ + bir_env_lookup_type "tmp_mtval" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mtval" (BType_Imm Bit64))) /\ + bir_env_lookup_type "tmp_mip" (default_riscv_bir_state ms).bst_environ = + SOME (bir_var_type (BVar "tmp_mip" (BType_Imm Bit64))) Proof rw [default_riscv_bir_state_def, default_riscv_bir_env_CSRS_def, diff --git a/src/theory/tools/lifter/bir_lifting_machinesScript.sml b/src/theory/tools/lifter/bir_lifting_machinesScript.sml index 4eafd9e29..8f456b022 100644 --- a/src/theory/tools/lifter/bir_lifting_machinesScript.sml +++ b/src/theory/tools/lifter/bir_lifting_machinesScript.sml @@ -1029,6 +1029,9 @@ Theorem riscv_FPRS_lifted_imms_LIST_EVAL = EVAL ``riscv_FPRS_lifted_imms_LIST`` * be represented as one immediate), we do so here as well. *) val riscv_sysregs_lifted_imms_LIST_def = Define ` riscv_sysregs_lifted_imms_LIST = [ + (BMLI (BVar "mhartid" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 ((ms.c_MCSR ms.procID).mhartid)) + ); (* MPRV (from the mstatus register) is really a 2-bit value, * but is represented as an 8-bit immediate *) (BMLI (BVar "MPRV" (BType_Imm Bit8)) @@ -1036,6 +1039,18 @@ val riscv_sysregs_lifted_imms_LIST_def = Define ` ); (BMLI (BVar "mscratch" (BType_Imm Bit64)) (\ms:riscv_state. Imm64 ((ms.c_MCSR ms.procID).mscratch)) + ); + (BMLI (BVar "mepc" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 ((ms.c_MCSR ms.procID).mepc)) + ); + (BMLI (BVar "mcause" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 $ reg'mcause ((ms.c_MCSR ms.procID).mcause)) + ); + (BMLI (BVar "mtval" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 ((ms.c_MCSR ms.procID).mtval)) + ); + (BMLI (BVar "mip" (BType_Imm Bit64)) + (\ms:riscv_state. Imm64 $ reg'mip ((ms.c_MCSR ms.procID).mip)) ) ] `; diff --git a/src/tools/lifter/examples/Holmakefile b/src/tools/lifter/examples/Holmakefile index ca65b65ea..c0386f478 100644 --- a/src/tools/lifter/examples/Holmakefile +++ b/src/tools/lifter/examples/Holmakefile @@ -1,4 +1,4 @@ -INCLUDES = +INCLUDES = .. all: $(DEFAULT_TARGETS) .PHONY: all diff --git a/src/tools/lifter/selftest_riscv.log b/src/tools/lifter/selftest_riscv.log index 6af9da80c..1f1e23d22 100644 --- a/src/tools/lifter/selftest_riscv.log +++ b/src/tools/lifter/selftest_riscv.log @@ -929,10 +929,10 @@ RV64 Zicsr Standard Extension CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 16w; 1w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 16w; 1w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "340110F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "340110F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -943,14 +943,14 @@ CSRRW x1, mscratch(0x340), x2: 340110F3 @ 0x10030 - OK BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) (BExp_Den (BVar "x2" (BType_Imm Bit64)))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 32w; 1w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 32w; 1w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "340120F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "340120F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -963,14 +963,14 @@ CSRRS x1, mscratch(0x340), x2: 340120F3 @ 0x10030 - OK (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) (BExp_Den (BVar "x2" (BType_Imm Bit64))))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 48w; 1w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 48w; 1w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "340130F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "340130F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -983,18 +983,18 @@ CSRRC x1, mscratch(0x340), x2: 340130F3 @ 0x10030 - OK (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) (BExp_BinExp BIExp_Minus (BExp_BinExp BIExp_Mult - (BExp_Const (Imm64 18446744073709551615w)) + (BExp_Const (Imm64 0xFFFFFFFFFFFFFFFFw)) (BExp_Den (BVar "x2" (BType_Imm Bit64)))) (BExp_Const (Imm64 1w))))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 208w; 0w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 208w; 0w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "3400D0F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "3400D0F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -1005,14 +1005,14 @@ CSRRWI x1, mscratch(0x340), 0x1: 3400D0F3 @ 0x10030 - OK BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) (BExp_Const (Imm64 1w))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 224w; 0w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 224w; 0w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "3400E0F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "3400E0F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -1025,14 +1025,14 @@ CSRRSI x1, mscratch(0x340), 0x1: 3400E0F3 @ 0x10030 - OK (BExp_Den (BVar "mscratch" (BType_Imm Bit64))) (BExp_Const (Imm64 1w)))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - OK [] -|- bir_is_lifted_inst_prog riscv_bmr (Imm64 65584w) (WI_end 0w 16777216w) - (65584w,[243w; 240w; 0w; 52w]) +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 240w; 0w; 52w]) (BirProgram - [<|bb_label := BL_Address_HC (Imm64 65584w) "3400F0F3"; + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "3400F0F3"; bb_statements := [BStmt_Assert (BExp_BinPred BIExp_Equal @@ -1042,10 +1042,90 @@ CSRRCI x1, mscratch(0x340), 0x1: 3400F0F3 @ 0x10030 - OK (BExp_Den (BVar "mscratch" (BType_Imm Bit64))); BStmt_Assign (BVar "mscratch" (BType_Imm Bit64)) (BExp_BinExp BIExp_And - (BExp_Const (Imm64 18446744073709551614w)) + (BExp_Const (Imm64 0xFFFFFFFFFFFFFFFEw)) (BExp_Den (BVar "mscratch" (BType_Imm Bit64))))]; bb_last_statement := - BStmt_Jmp (BLE_Label (BL_Address (Imm64 65588w)))|>]) + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) + +CSRR a2, mhartid(0xF14): F1402673 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[115w; 38w; 64w; 241w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "F1402673"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x12" (BType_Imm Bit64)) + (BExp_Den (BVar "mhartid" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) + +CSRR a5, mepc(0x341): 341027F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 39w; 16w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "341027F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x15" (BType_Imm Bit64)) + (BExp_Den (BVar "mepc" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) + +CSRR a5, mcause(0x342): 342027F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 39w; 32w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "342027F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x15" (BType_Imm Bit64)) + (BExp_Den (BVar "mcause" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) + +CSRR a5, mtval(0x343): 343027F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 39w; 48w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "343027F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x15" (BType_Imm Bit64)) + (BExp_Den (BVar "mtval" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) + +CSRR a5, mip(0x344): 344027F3 @ 0x10030 - OK + [] +|- bir_is_lifted_inst_prog riscv_bmr (Imm64 0x10030w) (WI_end 0w 0x1000000w) + (0x10030w,[243w; 39w; 64w; 52w]) + (BirProgram + [<|bb_label := BL_Address_HC (Imm64 0x10030w) "344027F3"; + bb_statements := + [BStmt_Assert + (BExp_BinPred BIExp_Equal + (BExp_Den (BVar "MPRV" (BType_Imm Bit8))) + (BExp_Const (Imm8 3w))); + BStmt_Assign (BVar "x15" (BType_Imm Bit64)) + (BExp_Den (BVar "mip" (BType_Imm Bit64)))]; + bb_last_statement := + BStmt_Jmp (BLE_Label (BL_Address (Imm64 0x10034w)))|>]) RV64M Standard Extension (instructions inherited from RV32M) @@ -1394,7 +1474,7 @@ REMUW x5, x6, x7: 027372BB @ 0x10030 - OK SUMMARY FAILING HEXCODES RISC-V -Instructions FAILED: 4/72 +Instructions FAILED: 4/82 "0881008F" (* bmr_step_hex failed *), "00000073" (* bmr_step_hex failed *), diff --git a/src/tools/lifter/selftest_riscv.sml b/src/tools/lifter/selftest_riscv.sml index 5f1bcb2d8..8f09521b0 100644 --- a/src/tools/lifter/selftest_riscv.sml +++ b/src/tools/lifter/selftest_riscv.sml @@ -322,6 +322,26 @@ val _ = riscv_test_hex_print_asm "CSRRSI x1, mscratch(0x340), 0x1" "3400E0F3"; (* CSRRCI x1, mscratch(0x340), 0x1 : 001101000000 00001 111 000011110011 *) val _ = riscv_test_hex_print_asm "CSRRCI x1, mscratch(0x340), 0x1" "3400F0F3"; +val _ = riscv_test_hex_print_asm "CSRR a2, mhartid(0xF14)" "F1402673"; + +val _ = riscv_test_hex_print_asm "CSRR a5, mepc(0x341)" "341027F3"; + +val _ = riscv_test_hex_print_asm "CSRR a5, mcause(0x342)" "342027F3"; + +val _ = riscv_test_hex_print_asm "CSRR a5, mtval(0x343)" "343027F3"; + +val _ = riscv_test_hex_print_asm "CSRR a5, mip(0x344)" "344027F3"; + +(* TODO: These fail in riscv_stepLib for some reason... + +val _ = riscv_test_hex_print_asm "CSRW mie(0x304), 0" "30405073"; +val _ = riscv_test_hex_print_asm "CSRW mstatus(0x300), 0" "30005073"; + +open riscv_stepLib; +val _ = riscv_step_hex "30405073"; + +*) + val _ = print_msg "\n"; val _ = print_header "RV64M Standard Extension (instructions inherited from RV32M)"; val _ = print_msg "\n\n"; From 541d525dbcd6c1a118a5b87cfd6def7d2ff1d20d Mon Sep 17 00:00:00 2001 From: Karl Palmskog Date: Thu, 5 Dec 2024 17:16:52 +0100 Subject: [PATCH 10/14] bundled version of l3 riscv model and step from trindemossen-1 --- examples/aes/Holmakefile | 4 +- examples/aes/exec/Holmakefile | 4 +- examples/aes/lifter/Holmakefile | 4 +- examples/aes/wp/Holmakefile | 4 +- examples/bsl-wp-smt/Holmakefile | 4 +- examples/nic/Holmakefile | 4 +- examples/riscv/aes-unopt/Holmakefile | 4 +- examples/riscv/aes/Holmakefile | 4 +- examples/riscv/chacha/Holmakefile | 4 +- examples/riscv/chachapoly/Holmakefile | 4 +- examples/riscv/ifelse/Holmakefile | 4 +- examples/riscv/incr-mem/Holmakefile | 4 +- examples/riscv/incr/Holmakefile | 4 +- examples/riscv/isqrt/Holmakefile | 4 +- examples/riscv/kernel/Holmakefile | 4 +- examples/riscv/mod2-mem/Holmakefile | 4 +- examples/riscv/mod2/Holmakefile | 4 +- examples/riscv/modexp/Holmakefile | 4 +- examples/riscv/motor/Holmakefile | 4 +- examples/riscv/perftest/Holmakefile | 4 +- examples/riscv/poly1305-inlined/Holmakefile | 4 +- examples/riscv/poly1305/Holmakefile | 4 +- examples/riscv/swap/Holmakefile | 4 +- examples/riscv/symbexectests/Holmakefile | 4 +- examples/tutorial/2-lift/Holmakefile | 4 +- examples/tutorial/4-bir-to-arm/Holmakefile | 4 +- examples/tutorial/5-wp/Holmakefile | 4 +- examples/tutorial/6-smt/Holmakefile | 4 +- examples/tutorial/7-composition/Holmakefile | 4 +- examples/tutorial/8-symbexec/Holmakefile | 4 +- src/shared/l3-machine-code/COPYRIGHT | 32 + .../l3-machine-code/riscv/model/Holmakefile | 7 + .../l3-machine-code/riscv/model/riscv.sig | 1135 + .../l3-machine-code/riscv/model/riscv.sml | 14707 +++++++++++ .../l3-machine-code/riscv/model/riscvLib.sig | 5 + .../l3-machine-code/riscv/model/riscvLib.sml | 9 + .../riscv/model/riscvScript.sml | 21999 ++++++++++++++++ .../l3-machine-code/riscv/step/Holmakefile | 4 + .../riscv/step/riscv_stepLib.sig | 9 + .../riscv/step/riscv_stepLib.sml | 370 + .../riscv/step/riscv_stepScript.sml | 899 + src/theory/tools/lifter/Holmakefile | 4 +- src/tools/backlifter/Holmakefile | 4 +- src/tools/comp/Holmakefile | 4 +- src/tools/lifter/Holmakefile | 4 +- .../symbexec/examples/minimal/Holmakefile | 4 +- src/tools/wp/Holmakefile | 4 +- src/tools/wp/benchmark/binaries/Holmakefile | 4 +- 48 files changed, 39250 insertions(+), 74 deletions(-) create mode 100644 src/shared/l3-machine-code/COPYRIGHT create mode 100644 src/shared/l3-machine-code/riscv/model/Holmakefile create mode 100644 src/shared/l3-machine-code/riscv/model/riscv.sig create mode 100644 src/shared/l3-machine-code/riscv/model/riscv.sml create mode 100644 src/shared/l3-machine-code/riscv/model/riscvLib.sig create mode 100644 src/shared/l3-machine-code/riscv/model/riscvLib.sml create mode 100644 src/shared/l3-machine-code/riscv/model/riscvScript.sml create mode 100644 src/shared/l3-machine-code/riscv/step/Holmakefile create mode 100644 src/shared/l3-machine-code/riscv/step/riscv_stepLib.sig create mode 100644 src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml create mode 100644 src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml diff --git a/examples/aes/Holmakefile b/examples/aes/Holmakefile index 5d74ab5d2..de458fbd3 100644 --- a/examples/aes/Holmakefile +++ b/examples/aes/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/aes/exec/Holmakefile b/examples/aes/exec/Holmakefile index 15f025422..83cf5d3dc 100644 --- a/examples/aes/exec/Holmakefile +++ b/examples/aes/exec/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/tools/lifter \ diff --git a/examples/aes/lifter/Holmakefile b/examples/aes/lifter/Holmakefile index 584aded12..5a8e04c45 100644 --- a/examples/aes/lifter/Holmakefile +++ b/examples/aes/lifter/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/tools/exec \ $(HOLBADIR)/src/tools/lifter diff --git a/examples/aes/wp/Holmakefile b/examples/aes/wp/Holmakefile index fc69878a4..c71498820 100644 --- a/examples/aes/wp/Holmakefile +++ b/examples/aes/wp/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/bsl-wp-smt/Holmakefile b/examples/bsl-wp-smt/Holmakefile index 4bddc6f87..e4649124b 100644 --- a/examples/bsl-wp-smt/Holmakefile +++ b/examples/bsl-wp-smt/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared/smt \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ diff --git a/examples/nic/Holmakefile b/examples/nic/Holmakefile index f197463c5..b24b85e1a 100644 --- a/examples/nic/Holmakefile +++ b/examples/nic/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared/smt \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ diff --git a/examples/riscv/aes-unopt/Holmakefile b/examples/riscv/aes-unopt/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/aes-unopt/Holmakefile +++ b/examples/riscv/aes-unopt/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/aes/Holmakefile b/examples/riscv/aes/Holmakefile index f0de51fdd..21b1153cc 100644 --- a/examples/riscv/aes/Holmakefile +++ b/examples/riscv/aes/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/chacha/Holmakefile b/examples/riscv/chacha/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/chacha/Holmakefile +++ b/examples/riscv/chacha/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/chachapoly/Holmakefile b/examples/riscv/chachapoly/Holmakefile index 7e04a3a61..33c69472f 100644 --- a/examples/riscv/chachapoly/Holmakefile +++ b/examples/riscv/chachapoly/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/ifelse/Holmakefile b/examples/riscv/ifelse/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/ifelse/Holmakefile +++ b/examples/riscv/ifelse/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/incr-mem/Holmakefile b/examples/riscv/incr-mem/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/incr-mem/Holmakefile +++ b/examples/riscv/incr-mem/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/incr/Holmakefile b/examples/riscv/incr/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/incr/Holmakefile +++ b/examples/riscv/incr/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/isqrt/Holmakefile b/examples/riscv/isqrt/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/isqrt/Holmakefile +++ b/examples/riscv/isqrt/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/kernel/Holmakefile b/examples/riscv/kernel/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/kernel/Holmakefile +++ b/examples/riscv/kernel/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/mod2-mem/Holmakefile b/examples/riscv/mod2-mem/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/mod2-mem/Holmakefile +++ b/examples/riscv/mod2-mem/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/mod2/Holmakefile b/examples/riscv/mod2/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/mod2/Holmakefile +++ b/examples/riscv/mod2/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/modexp/Holmakefile b/examples/riscv/modexp/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/modexp/Holmakefile +++ b/examples/riscv/modexp/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/motor/Holmakefile b/examples/riscv/motor/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/motor/Holmakefile +++ b/examples/riscv/motor/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/perftest/Holmakefile b/examples/riscv/perftest/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/perftest/Holmakefile +++ b/examples/riscv/perftest/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/poly1305-inlined/Holmakefile b/examples/riscv/poly1305-inlined/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/poly1305-inlined/Holmakefile +++ b/examples/riscv/poly1305-inlined/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/poly1305/Holmakefile b/examples/riscv/poly1305/Holmakefile index 4d9d7dbfe..d79e4e0a2 100644 --- a/examples/riscv/poly1305/Holmakefile +++ b/examples/riscv/poly1305/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/swap/Holmakefile b/examples/riscv/swap/Holmakefile index d3e07e06b..0fce79323 100644 --- a/examples/riscv/swap/Holmakefile +++ b/examples/riscv/swap/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/riscv/symbexectests/Holmakefile b/examples/riscv/symbexectests/Holmakefile index a4e3a5025..dbaa352bd 100644 --- a/examples/riscv/symbexectests/Holmakefile +++ b/examples/riscv/symbexectests/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/program_logic \ diff --git a/examples/tutorial/2-lift/Holmakefile b/examples/tutorial/2-lift/Holmakefile index 75b7a3daf..08455b9e1 100644 --- a/examples/tutorial/2-lift/Holmakefile +++ b/examples/tutorial/2-lift/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/tutorial/4-bir-to-arm/Holmakefile b/examples/tutorial/4-bir-to-arm/Holmakefile index 0d5c42d30..00f68237b 100644 --- a/examples/tutorial/4-bir-to-arm/Holmakefile +++ b/examples/tutorial/4-bir-to-arm/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/tutorial/5-wp/Holmakefile b/examples/tutorial/5-wp/Holmakefile index fdbac2ec4..99226f798 100644 --- a/examples/tutorial/5-wp/Holmakefile +++ b/examples/tutorial/5-wp/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/tutorial/6-smt/Holmakefile b/examples/tutorial/6-smt/Holmakefile index fb98aaafe..4b597188b 100644 --- a/examples/tutorial/6-smt/Holmakefile +++ b/examples/tutorial/6-smt/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/tutorial/7-composition/Holmakefile b/examples/tutorial/7-composition/Holmakefile index 23557f863..c2678cd56 100644 --- a/examples/tutorial/7-composition/Holmakefile +++ b/examples/tutorial/7-composition/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/examples/tutorial/8-symbexec/Holmakefile b/examples/tutorial/8-symbexec/Holmakefile index aa451a20a..47b18e35e 100644 --- a/examples/tutorial/8-symbexec/Holmakefile +++ b/examples/tutorial/8-symbexec/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/tools/symbexec \ $(HOLBADIR)/examples/tutorial/2-lift \ diff --git a/src/shared/l3-machine-code/COPYRIGHT b/src/shared/l3-machine-code/COPYRIGHT new file mode 100644 index 000000000..2423778e9 --- /dev/null +++ b/src/shared/l3-machine-code/COPYRIGHT @@ -0,0 +1,32 @@ +HOL COPYRIGHT NOTICE, LICENSE AND DISCLAIMER. + +Copyright 1985--2023 by the HOL4 CONTRIBUTORS + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * The names of the copyright holders and contributors may not be + used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR +TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +DAMAGE. diff --git a/src/shared/l3-machine-code/riscv/model/Holmakefile b/src/shared/l3-machine-code/riscv/model/Holmakefile new file mode 100644 index 000000000..0df5af49d --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/Holmakefile @@ -0,0 +1,7 @@ +INCLUDES = $(HOLDIR)/examples/l3-machine-code/common $(HOLDIR)/examples/l3-machine-code/lib + +all: $(DEFAULT_TARGETS) +.PHONY: all + +riscv.uo: $(HOLDIR)/examples/l3-machine-code/lib/assemblerLib.uo $(HOLDIR)/examples/l3-machine-code/lib/MutableMap16.uo riscv.sml riscv.ui + $(HOLMOSMLC) -c -toplevel assemblerLib.uo MutableMap16.ui riscv.sml diff --git a/src/shared/l3-machine-code/riscv/model/riscv.sig b/src/shared/l3-machine-code/riscv/model/riscv.sig new file mode 100644 index 000000000..f9bdb331e --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/riscv.sig @@ -0,0 +1,1135 @@ +(* riscv - generated by L3 - Mon Sep 18 10:41:50 2017 *) + +signature riscv = +sig + +structure Map : Map + +(* ------------------------------------------------------------------------- + Types + ------------------------------------------------------------------------- *) + +datatype accessType = Read | Write + +datatype fetchType = Instruction | Data + +datatype Architecture = RV32I | RV64I | RV128I + +datatype Privilege = User | Supervisor | Hypervisor | Machine + +datatype VM_Mode = Mbare | Mbb | Mbbid | Sv32 | Sv39 | Sv48 | Sv57 | Sv64 + +datatype ExtStatus = Off | Initial | Clean | Dirty + +datatype Interrupt = Software | Timer + +datatype ExceptionType + = Fetch_Misaligned | Fetch_Fault | Illegal_Instr | Breakpoint + | Load_Fault | AMO_Misaligned | Store_AMO_Fault | UMode_Env_Call + | SMode_Env_Call | HMode_Env_Call | MMode_Env_Call + +type mcpuid = + { ArchBase: BitsN.nbit, I: bool, M: bool, S: bool, U: bool, + mcpuid'rst: BitsN.nbit } + +type mimpid = { RVImpl: BitsN.nbit, RVSource: BitsN.nbit } + +type mstatus = + { MFS: BitsN.nbit, MIE: bool, MIE1: bool, MIE2: bool, MIE3: bool, + MMPRV: bool, MPRV: BitsN.nbit, MPRV1: BitsN.nbit, MPRV2: BitsN.nbit, + MPRV3: BitsN.nbit, MSD: bool, MXS: BitsN.nbit, VM: BitsN.nbit, + mstatus'rst: BitsN.nbit } + +type mtdeleg = { Exc_deleg: BitsN.nbit, Intr_deleg: BitsN.nbit } + +type mip = + { HSIP: bool, HTIP: bool, MSIP: bool, MTIP: bool, SSIP: bool, + STIP: bool, mip'rst: BitsN.nbit } + +type mie = + { HSIE: bool, HTIE: bool, MSIE: bool, MTIE: bool, SSIE: bool, + STIE: bool, mie'rst: BitsN.nbit } + +type mcause = { EC: BitsN.nbit, Int: bool, mcause'rst: BitsN.nbit } + +type MachineCSR = + { mbadaddr: BitsN.nbit, mbase: BitsN.nbit, mbound: BitsN.nbit, + mcause: mcause, mcpuid: mcpuid, mdbase: BitsN.nbit, + mdbound: BitsN.nbit, mepc: BitsN.nbit, mfromhost: BitsN.nbit, + mhartid: BitsN.nbit, mibase: BitsN.nbit, mibound: BitsN.nbit, + mie: mie, mimpid: mimpid, mip: mip, mscratch: BitsN.nbit, + mstatus: mstatus, mtdeleg: mtdeleg, mtime_delta: BitsN.nbit, + mtimecmp: BitsN.nbit, mtohost: BitsN.nbit, mtvec: BitsN.nbit } + +type HypervisorCSR = + { hbadaddr: BitsN.nbit, hcause: mcause, hepc: BitsN.nbit, + hscratch: BitsN.nbit, hstatus: mstatus, htdeleg: mtdeleg, + htime_delta: BitsN.nbit, htimecmp: BitsN.nbit, htvec: BitsN.nbit } + +type sstatus = + { SFS: BitsN.nbit, SIE: bool, SMPRV: bool, SPIE: bool, SPS: bool, + SSD: bool, SXS: BitsN.nbit, sstatus'rst: BitsN.nbit } + +type sip = { SSIP: bool, STIP: bool, sip'rst: BitsN.nbit } + +type sie = { SSIE: bool, STIE: bool, sie'rst: BitsN.nbit } + +type SupervisorCSR = + { sasid: BitsN.nbit, sbadaddr: BitsN.nbit, scause: mcause, + sepc: BitsN.nbit, sptbr: BitsN.nbit, sscratch: BitsN.nbit, + stime_delta: BitsN.nbit, stimecmp: BitsN.nbit, stvec: BitsN.nbit } + +type FPCSR = + { DZ: bool, FRM: BitsN.nbit, NV: bool, NX: bool, OF: bool, UF: bool, + fpcsr'rst: BitsN.nbit } + +type UserCSR = + { cycle_delta: BitsN.nbit, fpcsr: FPCSR, instret_delta: BitsN.nbit, + time_delta: BitsN.nbit } + +type SynchronousTrap = { badaddr: BitsN.nbit option, trap: ExceptionType } + +datatype TransferControl + = BranchTo of BitsN.nbit | Ereturn | Mrts | Trap of SynchronousTrap + +datatype Rounding = RNE | RTZ | RDN | RUP | RMM | RDYN + +type StateDelta = + { addr: BitsN.nbit option, data1: BitsN.nbit option, + data2: BitsN.nbit option, exc_taken: bool, fetch_exc: bool, + fp_data: BitsN.nbit option, pc: BitsN.nbit, rinstr: BitsN.nbit, + st_width: BitsN.nbit option } + +type SV_PTE = + { PTE_D: bool, PTE_PPNi: BitsN.nbit, PTE_R: bool, PTE_SW: BitsN.nbit, + PTE_T: BitsN.nbit, PTE_V: bool, sv_pte'rst: BitsN.nbit } + +type SV_Vaddr = + { Sv_PgOfs: BitsN.nbit, Sv_VPNi: BitsN.nbit, sv_vaddr'rst: BitsN.nbit } + +type TLBEntry = + { age: BitsN.nbit, asid: BitsN.nbit, global: bool, pAddr: BitsN.nbit, + pte: SV_PTE, pteAddr: BitsN.nbit, vAddr: BitsN.nbit, + vAddrMask: BitsN.nbit, vMatchMask: BitsN.nbit } + +datatype Internal + = FETCH_FAULT of BitsN.nbit | FETCH_MISALIGNED of BitsN.nbit + +datatype System + = CSRRC of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRCI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRS of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRSI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRWI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | EBREAK + | ECALL + | ERET + | MRTS + | SFENCE_VM of BitsN.nbit + | WFI + +datatype FConv + = FCLASS_D of BitsN.nbit * BitsN.nbit + | FCLASS_S of BitsN.nbit * BitsN.nbit + | FCVT_D_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_LU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_LU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_L_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_L_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_WU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_WU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_W_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_W_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMV_D_X of BitsN.nbit * BitsN.nbit + | FMV_S_X of BitsN.nbit * BitsN.nbit + | FMV_X_D of BitsN.nbit * BitsN.nbit + | FMV_X_S of BitsN.nbit * BitsN.nbit + | FSGNJN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype FArith + = FADD_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FADD_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FDIV_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FDIV_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FEQ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FEQ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLE_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLE_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMADD_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMAX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMAX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMIN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMIN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMSUB_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMSUB_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMUL_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FMUL_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FNMADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMADD_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMSUB_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMSUB_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FSQRT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSQRT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSUB_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FSUB_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + +datatype FPStore + = FSD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype FPLoad + = FLD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype AMO + = AMOADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOADD_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOAND_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOAND_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAXU_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAXU_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAX_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAX_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMINU_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMINU_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMIN_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMIN_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOOR_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOOR_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOSWAP_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOSWAP_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOXOR_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOXOR_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | LR_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | LR_W of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | SC_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | SC_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + +datatype Store + = SB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Load + = LB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LWU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Branch + = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BGE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BGEU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BNE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | JAL of BitsN.nbit * BitsN.nbit + | JALR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype MulDiv + = DIV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MUL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULHSU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REM of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Shift + = SLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype ArithR + = ADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ADDW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | AND of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | OR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SUBW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | XOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype ArithI + = ADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ADDIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ANDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | AUIPC of BitsN.nbit * BitsN.nbit + | LUI of BitsN.nbit * BitsN.nbit + | ORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | XORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype instruction + = AMO of AMO + | ArithI of ArithI + | ArithR of ArithR + | Branch of Branch + | FArith of FArith + | FConv of FConv + | FENCE of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FENCE_I of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FPLoad of FPLoad + | FPStore of FPStore + | Internal of Internal + | Load of Load + | MulDiv of MulDiv + | Shift of Shift + | Store of Store + | System of System + | UnknownInstruction + +datatype FetchResult = F_Error of instruction | F_Result of BitsN.nbit + +(* ------------------------------------------------------------------------- + Exceptions + ------------------------------------------------------------------------- *) + +exception INTERNAL_ERROR of string + +exception UNDEFINED of string + +(* ------------------------------------------------------------------------- + Functions + ------------------------------------------------------------------------- *) + +structure Cast: +sig + +val natToaccessType: Nat.nat -> accessType +val accessTypeToNat: accessType -> Nat.nat +val stringToaccessType: string -> accessType +val accessTypeToString: accessType -> string +val natTofetchType: Nat.nat -> fetchType +val fetchTypeToNat: fetchType -> Nat.nat +val stringTofetchType: string -> fetchType +val fetchTypeToString: fetchType -> string +val natToArchitecture: Nat.nat -> Architecture +val ArchitectureToNat: Architecture -> Nat.nat +val stringToArchitecture: string -> Architecture +val ArchitectureToString: Architecture -> string +val natToPrivilege: Nat.nat -> Privilege +val PrivilegeToNat: Privilege -> Nat.nat +val stringToPrivilege: string -> Privilege +val PrivilegeToString: Privilege -> string +val natToVM_Mode: Nat.nat -> VM_Mode +val VM_ModeToNat: VM_Mode -> Nat.nat +val stringToVM_Mode: string -> VM_Mode +val VM_ModeToString: VM_Mode -> string +val natToExtStatus: Nat.nat -> ExtStatus +val ExtStatusToNat: ExtStatus -> Nat.nat +val stringToExtStatus: string -> ExtStatus +val ExtStatusToString: ExtStatus -> string +val natToInterrupt: Nat.nat -> Interrupt +val InterruptToNat: Interrupt -> Nat.nat +val stringToInterrupt: string -> Interrupt +val InterruptToString: Interrupt -> string +val natToExceptionType: Nat.nat -> ExceptionType +val ExceptionTypeToNat: ExceptionType -> Nat.nat +val stringToExceptionType: string -> ExceptionType +val ExceptionTypeToString: ExceptionType -> string +val natToRounding: Nat.nat -> Rounding +val RoundingToNat: Rounding -> Nat.nat +val stringToRounding: string -> Rounding +val RoundingToString: Rounding -> string + +end + +val MEM8: (BitsN.nbit Map.map) ref +val c_ExitCode: (BitsN.nbit Map.map) ref +val c_HCSR: (HypervisorCSR Map.map) ref +val c_MCSR: (MachineCSR Map.map) ref +val c_NextFetch: ((TransferControl option) Map.map) ref +val c_PC: (BitsN.nbit Map.map) ref +val c_ReserveLoad: ((BitsN.nbit option) Map.map) ref +val c_SCSR: (SupervisorCSR Map.map) ref +val c_UCSR: (UserCSR Map.map) ref +val c_cycles: (BitsN.nbit Map.map) ref +val c_fpr: ((BitsN.nbit Map.map) Map.map) ref +val c_gpr: ((BitsN.nbit Map.map) Map.map) ref +val c_instret: (BitsN.nbit Map.map) ref +val c_tlb: (((TLBEntry option) Map.map) Map.map) ref +val c_update: (StateDelta Map.map) ref +val clock: BitsN.nbit ref +val done: bool ref +val log: ((Nat.nat * string) list) ref +val procID: BitsN.nbit ref +val totalCore: Nat.nat ref +val mcpuid_ArchBase_rupd: mcpuid * BitsN.nbit -> mcpuid +val mcpuid_I_rupd: mcpuid * bool -> mcpuid +val mcpuid_M_rupd: mcpuid * bool -> mcpuid +val mcpuid_S_rupd: mcpuid * bool -> mcpuid +val mcpuid_U_rupd: mcpuid * bool -> mcpuid +val mcpuid_mcpuid'rst_rupd: mcpuid * BitsN.nbit -> mcpuid +val mimpid_RVImpl_rupd: mimpid * BitsN.nbit -> mimpid +val mimpid_RVSource_rupd: mimpid * BitsN.nbit -> mimpid +val mstatus_MFS_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_MIE_rupd: mstatus * bool -> mstatus +val mstatus_MIE1_rupd: mstatus * bool -> mstatus +val mstatus_MIE2_rupd: mstatus * bool -> mstatus +val mstatus_MIE3_rupd: mstatus * bool -> mstatus +val mstatus_MMPRV_rupd: mstatus * bool -> mstatus +val mstatus_MPRV_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_MPRV1_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_MPRV2_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_MPRV3_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_MSD_rupd: mstatus * bool -> mstatus +val mstatus_MXS_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_VM_rupd: mstatus * BitsN.nbit -> mstatus +val mstatus_mstatus'rst_rupd: mstatus * BitsN.nbit -> mstatus +val mtdeleg_Exc_deleg_rupd: mtdeleg * BitsN.nbit -> mtdeleg +val mtdeleg_Intr_deleg_rupd: mtdeleg * BitsN.nbit -> mtdeleg +val mip_HSIP_rupd: mip * bool -> mip +val mip_HTIP_rupd: mip * bool -> mip +val mip_MSIP_rupd: mip * bool -> mip +val mip_MTIP_rupd: mip * bool -> mip +val mip_SSIP_rupd: mip * bool -> mip +val mip_STIP_rupd: mip * bool -> mip +val mip_mip'rst_rupd: mip * BitsN.nbit -> mip +val mie_HSIE_rupd: mie * bool -> mie +val mie_HTIE_rupd: mie * bool -> mie +val mie_MSIE_rupd: mie * bool -> mie +val mie_MTIE_rupd: mie * bool -> mie +val mie_SSIE_rupd: mie * bool -> mie +val mie_STIE_rupd: mie * bool -> mie +val mie_mie'rst_rupd: mie * BitsN.nbit -> mie +val mcause_EC_rupd: mcause * BitsN.nbit -> mcause +val mcause_Int_rupd: mcause * bool -> mcause +val mcause_mcause'rst_rupd: mcause * BitsN.nbit -> mcause +val MachineCSR_mbadaddr_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mbase_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mbound_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mcause_rupd: MachineCSR * mcause -> MachineCSR +val MachineCSR_mcpuid_rupd: MachineCSR * mcpuid -> MachineCSR +val MachineCSR_mdbase_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mdbound_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mepc_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mfromhost_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mhartid_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mibase_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mibound_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mie_rupd: MachineCSR * mie -> MachineCSR +val MachineCSR_mimpid_rupd: MachineCSR * mimpid -> MachineCSR +val MachineCSR_mip_rupd: MachineCSR * mip -> MachineCSR +val MachineCSR_mscratch_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mstatus_rupd: MachineCSR * mstatus -> MachineCSR +val MachineCSR_mtdeleg_rupd: MachineCSR * mtdeleg -> MachineCSR +val MachineCSR_mtime_delta_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mtimecmp_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mtohost_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val MachineCSR_mtvec_rupd: MachineCSR * BitsN.nbit -> MachineCSR +val HypervisorCSR_hbadaddr_rupd: + HypervisorCSR * BitsN.nbit -> HypervisorCSR +val HypervisorCSR_hcause_rupd: HypervisorCSR * mcause -> HypervisorCSR +val HypervisorCSR_hepc_rupd: HypervisorCSR * BitsN.nbit -> HypervisorCSR +val HypervisorCSR_hscratch_rupd: + HypervisorCSR * BitsN.nbit -> HypervisorCSR +val HypervisorCSR_hstatus_rupd: HypervisorCSR * mstatus -> HypervisorCSR +val HypervisorCSR_htdeleg_rupd: HypervisorCSR * mtdeleg -> HypervisorCSR +val HypervisorCSR_htime_delta_rupd: + HypervisorCSR * BitsN.nbit -> HypervisorCSR +val HypervisorCSR_htimecmp_rupd: + HypervisorCSR * BitsN.nbit -> HypervisorCSR +val HypervisorCSR_htvec_rupd: HypervisorCSR * BitsN.nbit -> HypervisorCSR +val sstatus_SFS_rupd: sstatus * BitsN.nbit -> sstatus +val sstatus_SIE_rupd: sstatus * bool -> sstatus +val sstatus_SMPRV_rupd: sstatus * bool -> sstatus +val sstatus_SPIE_rupd: sstatus * bool -> sstatus +val sstatus_SPS_rupd: sstatus * bool -> sstatus +val sstatus_SSD_rupd: sstatus * bool -> sstatus +val sstatus_SXS_rupd: sstatus * BitsN.nbit -> sstatus +val sstatus_sstatus'rst_rupd: sstatus * BitsN.nbit -> sstatus +val sip_SSIP_rupd: sip * bool -> sip +val sip_STIP_rupd: sip * bool -> sip +val sip_sip'rst_rupd: sip * BitsN.nbit -> sip +val sie_SSIE_rupd: sie * bool -> sie +val sie_STIE_rupd: sie * bool -> sie +val sie_sie'rst_rupd: sie * BitsN.nbit -> sie +val SupervisorCSR_sasid_rupd: SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_sbadaddr_rupd: + SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_scause_rupd: SupervisorCSR * mcause -> SupervisorCSR +val SupervisorCSR_sepc_rupd: SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_sptbr_rupd: SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_sscratch_rupd: + SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_stime_delta_rupd: + SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_stimecmp_rupd: + SupervisorCSR * BitsN.nbit -> SupervisorCSR +val SupervisorCSR_stvec_rupd: SupervisorCSR * BitsN.nbit -> SupervisorCSR +val FPCSR_DZ_rupd: FPCSR * bool -> FPCSR +val FPCSR_FRM_rupd: FPCSR * BitsN.nbit -> FPCSR +val FPCSR_NV_rupd: FPCSR * bool -> FPCSR +val FPCSR_NX_rupd: FPCSR * bool -> FPCSR +val FPCSR_OF_rupd: FPCSR * bool -> FPCSR +val FPCSR_UF_rupd: FPCSR * bool -> FPCSR +val FPCSR_fpcsr'rst_rupd: FPCSR * BitsN.nbit -> FPCSR +val UserCSR_cycle_delta_rupd: UserCSR * BitsN.nbit -> UserCSR +val UserCSR_fpcsr_rupd: UserCSR * FPCSR -> UserCSR +val UserCSR_instret_delta_rupd: UserCSR * BitsN.nbit -> UserCSR +val UserCSR_time_delta_rupd: UserCSR * BitsN.nbit -> UserCSR +val SynchronousTrap_badaddr_rupd: + SynchronousTrap * (BitsN.nbit option) -> SynchronousTrap +val SynchronousTrap_trap_rupd: + SynchronousTrap * ExceptionType -> SynchronousTrap +val StateDelta_addr_rupd: StateDelta * (BitsN.nbit option) -> StateDelta +val StateDelta_data1_rupd: StateDelta * (BitsN.nbit option) -> StateDelta +val StateDelta_data2_rupd: StateDelta * (BitsN.nbit option) -> StateDelta +val StateDelta_exc_taken_rupd: StateDelta * bool -> StateDelta +val StateDelta_fetch_exc_rupd: StateDelta * bool -> StateDelta +val StateDelta_fp_data_rupd: + StateDelta * (BitsN.nbit option) -> StateDelta +val StateDelta_pc_rupd: StateDelta * BitsN.nbit -> StateDelta +val StateDelta_rinstr_rupd: StateDelta * BitsN.nbit -> StateDelta +val StateDelta_st_width_rupd: + StateDelta * (BitsN.nbit option) -> StateDelta +val SV_PTE_PTE_D_rupd: SV_PTE * bool -> SV_PTE +val SV_PTE_PTE_PPNi_rupd: SV_PTE * BitsN.nbit -> SV_PTE +val SV_PTE_PTE_R_rupd: SV_PTE * bool -> SV_PTE +val SV_PTE_PTE_SW_rupd: SV_PTE * BitsN.nbit -> SV_PTE +val SV_PTE_PTE_T_rupd: SV_PTE * BitsN.nbit -> SV_PTE +val SV_PTE_PTE_V_rupd: SV_PTE * bool -> SV_PTE +val SV_PTE_sv_pte'rst_rupd: SV_PTE * BitsN.nbit -> SV_PTE +val SV_Vaddr_Sv_PgOfs_rupd: SV_Vaddr * BitsN.nbit -> SV_Vaddr +val SV_Vaddr_Sv_VPNi_rupd: SV_Vaddr * BitsN.nbit -> SV_Vaddr +val SV_Vaddr_sv_vaddr'rst_rupd: SV_Vaddr * BitsN.nbit -> SV_Vaddr +val TLBEntry_age_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_asid_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_global_rupd: TLBEntry * bool -> TLBEntry +val TLBEntry_pAddr_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_pte_rupd: TLBEntry * SV_PTE -> TLBEntry +val TLBEntry_pteAddr_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_vAddr_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_vAddrMask_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val TLBEntry_vMatchMask_rupd: TLBEntry * BitsN.nbit -> TLBEntry +val boolify'32: + BitsN.nbit -> + bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * + (bool * (bool * (bool * (bool * bool)))))))))))))))))))))))))))))) +val ASID_SIZE: Nat.nat +val PAGESIZE_BITS: Nat.nat +val LEVEL_BITS: Nat.nat +val BYTE: BitsN.nbit +val HALFWORD: BitsN.nbit +val WORD: BitsN.nbit +val DOUBLEWORD: BitsN.nbit +val archBase: Architecture -> BitsN.nbit +val architecture: BitsN.nbit -> Architecture +val archName: Architecture -> string +val privLevel: Privilege -> BitsN.nbit +val privilege: BitsN.nbit -> Privilege +val privName: Privilege -> string +val vmType: BitsN.nbit -> VM_Mode +val isValidVM: BitsN.nbit -> bool +val vmMode: VM_Mode -> BitsN.nbit +val vmModeName: VM_Mode -> string +val ext_status: ExtStatus -> BitsN.nbit +val extStatus: BitsN.nbit -> ExtStatus +val extStatusName: ExtStatus -> string +val interruptIndex: Interrupt -> BitsN.nbit +val excCode: ExceptionType -> BitsN.nbit +val excType: BitsN.nbit -> ExceptionType +val excName: ExceptionType -> string +val rec'mcpuid: BitsN.nbit -> mcpuid +val reg'mcpuid: mcpuid -> BitsN.nbit +val write'rec'mcpuid: (BitsN.nbit * mcpuid) -> BitsN.nbit +val write'reg'mcpuid: (mcpuid * BitsN.nbit) -> mcpuid +val rec'mimpid: BitsN.nbit -> mimpid +val reg'mimpid: mimpid -> BitsN.nbit +val write'rec'mimpid: (BitsN.nbit * mimpid) -> BitsN.nbit +val write'reg'mimpid: (mimpid * BitsN.nbit) -> mimpid +val rec'mstatus: BitsN.nbit -> mstatus +val reg'mstatus: mstatus -> BitsN.nbit +val write'rec'mstatus: (BitsN.nbit * mstatus) -> BitsN.nbit +val write'reg'mstatus: (mstatus * BitsN.nbit) -> mstatus +val rec'mtdeleg: BitsN.nbit -> mtdeleg +val reg'mtdeleg: mtdeleg -> BitsN.nbit +val write'rec'mtdeleg: (BitsN.nbit * mtdeleg) -> BitsN.nbit +val write'reg'mtdeleg: (mtdeleg * BitsN.nbit) -> mtdeleg +val rec'mip: BitsN.nbit -> mip +val reg'mip: mip -> BitsN.nbit +val write'rec'mip: (BitsN.nbit * mip) -> BitsN.nbit +val write'reg'mip: (mip * BitsN.nbit) -> mip +val rec'mie: BitsN.nbit -> mie +val reg'mie: mie -> BitsN.nbit +val write'rec'mie: (BitsN.nbit * mie) -> BitsN.nbit +val write'reg'mie: (mie * BitsN.nbit) -> mie +val rec'mcause: BitsN.nbit -> mcause +val reg'mcause: mcause -> BitsN.nbit +val write'rec'mcause: (BitsN.nbit * mcause) -> BitsN.nbit +val write'reg'mcause: (mcause * BitsN.nbit) -> mcause +val rec'sstatus: BitsN.nbit -> sstatus +val reg'sstatus: sstatus -> BitsN.nbit +val write'rec'sstatus: (BitsN.nbit * sstatus) -> BitsN.nbit +val write'reg'sstatus: (sstatus * BitsN.nbit) -> sstatus +val rec'sip: BitsN.nbit -> sip +val reg'sip: sip -> BitsN.nbit +val write'rec'sip: (BitsN.nbit * sip) -> BitsN.nbit +val write'reg'sip: (sip * BitsN.nbit) -> sip +val rec'sie: BitsN.nbit -> sie +val reg'sie: sie -> BitsN.nbit +val write'rec'sie: (BitsN.nbit * sie) -> BitsN.nbit +val write'reg'sie: (sie * BitsN.nbit) -> sie +val rec'FPCSR: BitsN.nbit -> FPCSR +val reg'FPCSR: FPCSR -> BitsN.nbit +val write'rec'FPCSR: (BitsN.nbit * FPCSR) -> BitsN.nbit +val write'reg'FPCSR: (FPCSR * BitsN.nbit) -> FPCSR +val lift_mip_sip: mip -> sip +val lift_mie_sie: mie -> sie +val lower_sip_mip: (sip * mip) -> mip +val lower_sie_mie: (sie * mie) -> mie +val update_mstatus: (mstatus * mstatus) -> mstatus +val lift_mstatus_sstatus: mstatus -> sstatus +val lower_sstatus_mstatus: (sstatus * mstatus) -> mstatus +val popPrivilegeStack: mstatus -> mstatus +val pushPrivilegeStack: (mstatus * Privilege) -> mstatus +val scheduleCore: Nat.nat -> unit +val gpr: BitsN.nbit -> BitsN.nbit +val write'gpr: (BitsN.nbit * BitsN.nbit) -> unit +val fcsr: unit -> FPCSR +val write'fcsr: FPCSR -> unit +val fpr: BitsN.nbit -> BitsN.nbit +val write'fpr: (BitsN.nbit * BitsN.nbit) -> unit +val PC: unit -> BitsN.nbit +val write'PC: BitsN.nbit -> unit +val UCSR: unit -> UserCSR +val write'UCSR: UserCSR -> unit +val SCSR: unit -> SupervisorCSR +val write'SCSR: SupervisorCSR -> unit +val HCSR: unit -> HypervisorCSR +val write'HCSR: HypervisorCSR -> unit +val MCSR: unit -> MachineCSR +val write'MCSR: MachineCSR -> unit +val NextFetch: unit -> (TransferControl option) +val write'NextFetch: (TransferControl option) -> unit +val ReserveLoad: unit -> (BitsN.nbit option) +val write'ReserveLoad: (BitsN.nbit option) -> unit +val ExitCode: unit -> BitsN.nbit +val write'ExitCode: BitsN.nbit -> unit +val curArch: unit -> Architecture +val in32BitMode: unit -> bool +val curPrivilege: unit -> Privilege +val curEPC: unit -> BitsN.nbit +val sendIPI: BitsN.nbit -> unit +val rnd_mode_static: BitsN.nbit -> (Rounding option) +val rnd_mode_dynamic: BitsN.nbit -> (Rounding option) +val l3round: Rounding -> (IEEEReal.rounding_mode option) +val round: BitsN.nbit -> (IEEEReal.rounding_mode option) +val RV32_CanonicalNan: BitsN.nbit +val RV64_CanonicalNan: BitsN.nbit +val FP32_IsSignalingNan: BitsN.nbit -> bool +val FP64_IsSignalingNan: BitsN.nbit -> bool +val FP32_Sign: BitsN.nbit -> bool +val FP64_Sign: BitsN.nbit -> bool +val setFP_Invalid: unit -> unit +val setFP_DivZero: unit -> unit +val setFP_Overflow: unit -> unit +val setFP_Underflow: unit -> unit +val setFP_Inexact: unit -> unit +val csrRW: BitsN.nbit -> BitsN.nbit +val csrPR: BitsN.nbit -> BitsN.nbit +val check_CSR_access: + (BitsN.nbit * (BitsN.nbit * (Privilege * accessType))) -> bool +val is_CSR_defined: BitsN.nbit -> bool +val CSRMap: BitsN.nbit -> BitsN.nbit +val write'CSRMap: (BitsN.nbit * BitsN.nbit) -> unit +val csrName: BitsN.nbit -> string +val Delta: unit -> StateDelta +val write'Delta: StateDelta -> unit +val hex32: BitsN.nbit -> string +val hex64: BitsN.nbit -> string +val log_w_csr: (BitsN.nbit * BitsN.nbit) -> string +val reg: BitsN.nbit -> string +val fpreg: BitsN.nbit -> string +val log_w_gpr: (BitsN.nbit * BitsN.nbit) -> string +val log_w_fprs: (BitsN.nbit * BitsN.nbit) -> string +val log_w_fprd: (BitsN.nbit * BitsN.nbit) -> string +val log_w_mem_mask: + (BitsN.nbit * + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))))) -> + string +val log_w_mem_mask_misaligned: + (BitsN.nbit * + (BitsN.nbit * + (BitsN.nbit * (BitsN.nbit * (Nat.nat * (BitsN.nbit * BitsN.nbit)))))) -> + string +val log_w_mem: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> string +val log_r_mem: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> string +val log_exc: ExceptionType -> string +val log_tohost: BitsN.nbit -> string +val clear_logs: unit -> unit +val setTrap: (ExceptionType * (BitsN.nbit option)) -> unit +val signalException: ExceptionType -> unit +val signalAddressException: (ExceptionType * BitsN.nbit) -> unit +val signalEnvCall: unit -> unit +val checkDelegation: (Privilege * (bool * BitsN.nbit)) -> Privilege +val checkPrivInterrupt: Privilege -> ((Interrupt * Privilege) option) +val checkInterrupts: unit -> ((Interrupt * Privilege) option) +val takeTrap: + (bool * (BitsN.nbit * (BitsN.nbit * ((BitsN.nbit option) * Privilege)))) -> + unit +val CSR: BitsN.nbit -> BitsN.nbit +val write'CSR: (BitsN.nbit * BitsN.nbit) -> unit +val writeCSR: (BitsN.nbit * BitsN.nbit) -> unit +val GPR: BitsN.nbit -> BitsN.nbit +val write'GPR: (BitsN.nbit * BitsN.nbit) -> unit +val FPRS: BitsN.nbit -> BitsN.nbit +val write'FPRS: (BitsN.nbit * BitsN.nbit) -> unit +val FPRD: BitsN.nbit -> BitsN.nbit +val write'FPRD: (BitsN.nbit * BitsN.nbit) -> unit +val writeFPRS: (BitsN.nbit * BitsN.nbit) -> unit +val writeFPRD: (BitsN.nbit * BitsN.nbit) -> unit +val MEM: BitsN.nbit -> BitsN.nbit +val write'MEM: (BitsN.nbit * BitsN.nbit) -> unit +val rawReadData: BitsN.nbit -> BitsN.nbit +val rawWriteData: (BitsN.nbit * (BitsN.nbit * Nat.nat)) -> unit +val rawReadInst: BitsN.nbit -> BitsN.nbit +val rawWriteMem: (BitsN.nbit * BitsN.nbit) -> unit +val checkMemPermission: + (fetchType * (accessType * (Privilege * BitsN.nbit))) -> bool +val isGlobal: BitsN.nbit -> bool +val rec'SV_PTE: BitsN.nbit -> SV_PTE +val reg'SV_PTE: SV_PTE -> BitsN.nbit +val write'rec'SV_PTE: (BitsN.nbit * SV_PTE) -> BitsN.nbit +val write'reg'SV_PTE: (SV_PTE * BitsN.nbit) -> SV_PTE +val rec'SV_Vaddr: BitsN.nbit -> SV_Vaddr +val reg'SV_Vaddr: SV_Vaddr -> BitsN.nbit +val write'rec'SV_Vaddr: (BitsN.nbit * SV_Vaddr) -> BitsN.nbit +val write'reg'SV_Vaddr: (SV_Vaddr * BitsN.nbit) -> SV_Vaddr +val walk64: + (BitsN.nbit * + (fetchType * (accessType * (Privilege * (BitsN.nbit * Nat.nat))))) -> + ((BitsN.nbit * (SV_PTE * (Nat.nat * (bool * BitsN.nbit)))) option) +val curASID: unit -> BitsN.nbit +val mkTLBEntry: + (BitsN.nbit * + (bool * (BitsN.nbit * (BitsN.nbit * (SV_PTE * (Nat.nat * BitsN.nbit)))))) -> + TLBEntry +val TLBEntries: Nat.nat +val lookupTLB: + (BitsN.nbit * (BitsN.nbit * ((TLBEntry option) Map.map))) -> + ((TLBEntry * BitsN.nbit) option) +val addToTLB: + (BitsN.nbit * + (BitsN.nbit * + (BitsN.nbit * + (SV_PTE * + (BitsN.nbit * (Nat.nat * (bool * ((TLBEntry option) Map.map)))))))) -> + ((TLBEntry option) Map.map) +val flushTLB: + (BitsN.nbit * ((BitsN.nbit option) * ((TLBEntry option) Map.map))) -> + ((TLBEntry option) Map.map) +val TLB: unit -> ((TLBEntry option) Map.map) +val write'TLB: ((TLBEntry option) Map.map) -> unit +val translate64: + (BitsN.nbit * (fetchType * (accessType * (Privilege * Nat.nat)))) -> + (BitsN.nbit option) +val translateAddr: + (BitsN.nbit * (fetchType * accessType)) -> (BitsN.nbit option) +val matchLoadReservation: BitsN.nbit -> bool +val branchTo: BitsN.nbit -> unit +val dfn'ADDI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'ADDIW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLTI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLTIU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'ANDI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'ORI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'XORI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLLI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRLI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRAI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLLIW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRLIW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRAIW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LUI: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'AUIPC: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'ADD: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'ADDW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SUB: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SUBW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLT: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLTU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'AND: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'OR: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'XOR: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLL: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SLLW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRL: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRLW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRA: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SRAW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'MUL: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'MULH: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'MULHU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'MULHSU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'MULW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'DIV: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'REM: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'DIVU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'REMU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'DIVW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'REMW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'DIVUW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'REMUW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'JAL: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'JALR: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BEQ: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BNE: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BLT: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BLTU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BGE: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'BGEU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LWU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LH: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LHU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LB: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LBU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LD: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SH: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SB: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SD: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FENCE: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FENCE_I: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'LR_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'LR_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'SC_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'SC_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOSWAP_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOSWAP_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOADD_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOADD_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOXOR_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOXOR_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOAND_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOAND_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOOR_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOOR_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMIN_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMIN_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMAX_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMAX_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMINU_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMINU_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMAXU_W: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'AMOMAXU_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FLW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FADD_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FSUB_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FMUL_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FDIV_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FSQRT_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMIN_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMAX_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMADD_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FMSUB_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FNMADD_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FNMSUB_S: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FCVT_S_W: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_S_WU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_W_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_WU_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_S_L: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_S_LU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_L_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_LU_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJ_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJN_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJX_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMV_X_S: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'FMV_S_X: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'FEQ_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FLT_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FLE_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCLASS_S: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'FLD: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSD: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FADD_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FSUB_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FMUL_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FDIV_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> unit +val dfn'FSQRT_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMIN_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMAX_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMADD_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FMSUB_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FNMADD_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FNMSUB_D: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + unit +val dfn'FCVT_D_W: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_D_WU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_W_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_WU_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_D_L: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_D_LU: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_L_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_LU_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_S_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCVT_D_S: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJ_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJN_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FSGNJX_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FMV_X_D: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'FMV_D_X: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'FEQ_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FLT_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FLE_D: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'FCLASS_D: (BitsN.nbit * BitsN.nbit) -> unit +val dfn'ECALL: unit -> unit +val dfn'EBREAK: unit -> unit +val dfn'ERET: unit -> unit +val dfn'MRTS: unit -> unit +val dfn'WFI: unit +val checkCSROp: (BitsN.nbit * (BitsN.nbit * accessType)) -> bool +val dfn'CSRRW: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'CSRRS: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'CSRRC: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'CSRRWI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'CSRRSI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'CSRRCI: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> unit +val dfn'SFENCE_VM: BitsN.nbit -> unit +val dfn'UnknownInstruction: unit -> unit +val dfn'FETCH_MISALIGNED: BitsN.nbit -> unit +val dfn'FETCH_FAULT: BitsN.nbit -> unit +val Run: instruction -> unit +val Fetch: unit -> FetchResult +val asImm12: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> BitsN.nbit +val asImm20: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> BitsN.nbit +val asSImm12: (BitsN.nbit * BitsN.nbit) -> BitsN.nbit +val Decode: BitsN.nbit -> instruction +val imm: Nat.nat -> BitsN.nbit -> string +val instr: string -> string +val amotype: (BitsN.nbit * BitsN.nbit) -> string +val pRtype: (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pARtype: + (string * + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))))) -> + string +val pLRtype: + (string * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + string +val pItype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pCSRtype: + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pCSRItype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pStype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pSBtype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pUtype: Nat.nat -> (string * (BitsN.nbit * BitsN.nbit)) -> string +val pUJtype: Nat.nat -> (string * (BitsN.nbit * BitsN.nbit)) -> string +val pN0type: string -> string +val pN1type: (string * BitsN.nbit) -> string +val pFRtype: (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pFR1type: (string * (BitsN.nbit * BitsN.nbit)) -> string +val pFR3type: + (string * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + string +val pFItype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pFStype: Nat.nat -> + (string * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) -> string +val pCFItype: (string * (BitsN.nbit * BitsN.nbit)) -> string +val pCIFtype: (string * (BitsN.nbit * BitsN.nbit)) -> string +val instructionToString: instruction -> string +val Rtype: + (BitsN.nbit * + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))))) -> + BitsN.nbit +val R4type: + (BitsN.nbit * + (BitsN.nbit * + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))))) -> + BitsN.nbit +val Itype: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + BitsN.nbit +val Stype: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + BitsN.nbit +val SBtype: + (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)))) -> + BitsN.nbit +val Utype: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> BitsN.nbit +val UJtype: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> BitsN.nbit +val opc: BitsN.nbit -> BitsN.nbit +val amofunc: (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) -> BitsN.nbit +val Encode: instruction -> BitsN.nbit +val log_instruction: (BitsN.nbit * instruction) -> string +val exitCode: unit -> Nat.nat +val CYCLES_PER_TIMER_TICK: Nat.nat +val tickClock: unit -> unit +val incrInstret: unit -> unit +val checkTimers: unit -> unit +val Next: unit -> unit +val initIdent: Architecture -> unit +val initMachine: BitsN.nbit -> unit +val initRegs: Nat.nat -> unit + +end \ No newline at end of file diff --git a/src/shared/l3-machine-code/riscv/model/riscv.sml b/src/shared/l3-machine-code/riscv/model/riscv.sml new file mode 100644 index 000000000..ef8f65050 --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/riscv.sml @@ -0,0 +1,14707 @@ +(* riscv - generated by L3 - Mon Jul 03 10:14:12 2017 *) + +structure riscv :> riscv = +struct + +structure Map = MutableMap + +(* ------------------------------------------------------------------------- + Type declarations + ------------------------------------------------------------------------- *) + +datatype accessType = Read | Write + +datatype fetchType = Instruction | Data + +datatype Architecture = RV32I | RV64I | RV128I + +datatype Privilege = User | Supervisor | Hypervisor | Machine + +datatype VM_Mode = Mbare | Mbb | Mbbid | Sv32 | Sv39 | Sv48 | Sv57 | Sv64 + +datatype ExtStatus = Off | Initial | Clean | Dirty + +datatype Interrupt = Software | Timer + +datatype ExceptionType + = Fetch_Misaligned | Fetch_Fault | Illegal_Instr | Breakpoint + | Load_Fault | AMO_Misaligned | Store_AMO_Fault | UMode_Env_Call + | SMode_Env_Call | HMode_Env_Call | MMode_Env_Call + +type mcpuid = + { ArchBase: BitsN.nbit, I: bool, M: bool, S: bool, U: bool, + mcpuid'rst: BitsN.nbit } + +type mimpid = { RVImpl: BitsN.nbit, RVSource: BitsN.nbit } + +type mstatus = + { MFS: BitsN.nbit, MIE: bool, MIE1: bool, MIE2: bool, MIE3: bool, + MMPRV: bool, MPRV: BitsN.nbit, MPRV1: BitsN.nbit, MPRV2: BitsN.nbit, + MPRV3: BitsN.nbit, MSD: bool, MXS: BitsN.nbit, VM: BitsN.nbit, + mstatus'rst: BitsN.nbit } + +type mtdeleg = { Exc_deleg: BitsN.nbit, Intr_deleg: BitsN.nbit } + +type mip = + { HSIP: bool, HTIP: bool, MSIP: bool, MTIP: bool, SSIP: bool, + STIP: bool, mip'rst: BitsN.nbit } + +type mie = + { HSIE: bool, HTIE: bool, MSIE: bool, MTIE: bool, SSIE: bool, + STIE: bool, mie'rst: BitsN.nbit } + +type mcause = { EC: BitsN.nbit, Int: bool, mcause'rst: BitsN.nbit } + +type MachineCSR = + { mbadaddr: BitsN.nbit, mbase: BitsN.nbit, mbound: BitsN.nbit, + mcause: mcause, mcpuid: mcpuid, mdbase: BitsN.nbit, + mdbound: BitsN.nbit, mepc: BitsN.nbit, mfromhost: BitsN.nbit, + mhartid: BitsN.nbit, mibase: BitsN.nbit, mibound: BitsN.nbit, + mie: mie, mimpid: mimpid, mip: mip, mscratch: BitsN.nbit, + mstatus: mstatus, mtdeleg: mtdeleg, mtime_delta: BitsN.nbit, + mtimecmp: BitsN.nbit, mtohost: BitsN.nbit, mtvec: BitsN.nbit } + +type HypervisorCSR = + { hbadaddr: BitsN.nbit, hcause: mcause, hepc: BitsN.nbit, + hscratch: BitsN.nbit, hstatus: mstatus, htdeleg: mtdeleg, + htime_delta: BitsN.nbit, htimecmp: BitsN.nbit, htvec: BitsN.nbit } + +type sstatus = + { SFS: BitsN.nbit, SIE: bool, SMPRV: bool, SPIE: bool, SPS: bool, + SSD: bool, SXS: BitsN.nbit, sstatus'rst: BitsN.nbit } + +type sip = { SSIP: bool, STIP: bool, sip'rst: BitsN.nbit } + +type sie = { SSIE: bool, STIE: bool, sie'rst: BitsN.nbit } + +type SupervisorCSR = + { sasid: BitsN.nbit, sbadaddr: BitsN.nbit, scause: mcause, + sepc: BitsN.nbit, sptbr: BitsN.nbit, sscratch: BitsN.nbit, + stime_delta: BitsN.nbit, stimecmp: BitsN.nbit, stvec: BitsN.nbit } + +type FPCSR = + { DZ: bool, FRM: BitsN.nbit, NV: bool, NX: bool, OF: bool, UF: bool, + fpcsr'rst: BitsN.nbit } + +type UserCSR = + { cycle_delta: BitsN.nbit, fpcsr: FPCSR, instret_delta: BitsN.nbit, + time_delta: BitsN.nbit } + +type SynchronousTrap = { badaddr: BitsN.nbit option, trap: ExceptionType } + +datatype TransferControl + = BranchTo of BitsN.nbit | Ereturn | Mrts | Trap of SynchronousTrap + +datatype Rounding = RNE | RTZ | RDN | RUP | RMM | RDYN + +type StateDelta = + { addr: BitsN.nbit option, data1: BitsN.nbit option, + data2: BitsN.nbit option, exc_taken: bool, fetch_exc: bool, + fp_data: BitsN.nbit option, pc: BitsN.nbit, rinstr: BitsN.nbit, + st_width: BitsN.nbit option } + +type SV_PTE = + { PTE_D: bool, PTE_PPNi: BitsN.nbit, PTE_R: bool, PTE_SW: BitsN.nbit, + PTE_T: BitsN.nbit, PTE_V: bool, sv_pte'rst: BitsN.nbit } + +type SV_Vaddr = + { Sv_PgOfs: BitsN.nbit, Sv_VPNi: BitsN.nbit, sv_vaddr'rst: BitsN.nbit } + +type TLBEntry = + { age: BitsN.nbit, asid: BitsN.nbit, global: bool, pAddr: BitsN.nbit, + pte: SV_PTE, pteAddr: BitsN.nbit, vAddr: BitsN.nbit, + vAddrMask: BitsN.nbit, vMatchMask: BitsN.nbit } + +datatype Internal + = FETCH_FAULT of BitsN.nbit | FETCH_MISALIGNED of BitsN.nbit + +datatype System + = CSRRC of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRCI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRS of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRSI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | CSRRWI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | EBREAK + | ECALL + | ERET + | MRTS + | SFENCE_VM of BitsN.nbit + | WFI + +datatype FConv + = FCLASS_D of BitsN.nbit * BitsN.nbit + | FCLASS_S of BitsN.nbit * BitsN.nbit + | FCVT_D_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_D_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_LU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_LU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_L_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_L_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_S_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_WU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_WU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_W_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FCVT_W_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMV_D_X of BitsN.nbit * BitsN.nbit + | FMV_S_X of BitsN.nbit * BitsN.nbit + | FMV_X_D of BitsN.nbit * BitsN.nbit + | FMV_X_S of BitsN.nbit * BitsN.nbit + | FSGNJN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSGNJ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype FArith + = FADD_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FADD_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FDIV_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FDIV_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FEQ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FEQ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLE_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLE_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMADD_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMAX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMAX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMIN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMIN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FMSUB_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMSUB_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FMUL_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FMUL_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FNMADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMADD_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMSUB_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FNMSUB_S of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | FSQRT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSQRT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSUB_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FSUB_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + +datatype FPStore + = FSD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FSW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype FPLoad + = FLD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype AMO + = AMOADD_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOADD_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOAND_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOAND_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAXU_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAXU_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAX_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMAX_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMINU_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMINU_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMIN_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOMIN_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOOR_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOOR_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOSWAP_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOSWAP_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOXOR_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | AMOXOR_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | LR_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | LR_W of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | SC_D of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + | SC_W of + BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) + +datatype Store + = SB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Load + = LB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | LWU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Branch + = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BGE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BGEU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | BNE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | JAL of BitsN.nbit * BitsN.nbit + | JALR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype MulDiv + = DIV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | DIVW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MUL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULHSU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | MULW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REM of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | REMW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype Shift + = SLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRAW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SRLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype ArithR + = ADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ADDW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | AND of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | OR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SUBW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | XOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype ArithI + = ADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ADDIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | ANDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | AUIPC of BitsN.nbit * BitsN.nbit + | LUI of BitsN.nbit * BitsN.nbit + | ORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | SLTIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | XORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + +datatype instruction + = AMO of AMO + | ArithI of ArithI + | ArithR of ArithR + | Branch of Branch + | FArith of FArith + | FConv of FConv + | FENCE of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) + | FENCE_I of BitsN.nbit * (BitsN.nbit * BitsN.nbit) + | FPLoad of FPLoad + | FPStore of FPStore + | Internal of Internal + | Load of Load + | MulDiv of MulDiv + | Shift of Shift + | Store of Store + | System of System + | UnknownInstruction + +datatype FetchResult = F_Error of instruction | F_Result of BitsN.nbit + +(* ------------------------------------------------------------------------- + Casting maps (for enumerated types) + ------------------------------------------------------------------------- *) + +structure Cast = +struct +fun natToaccessType x = + case Nat.toInt x of + 0 => Read | 1 => Write | _ => raise Fail "natToaccessType" + +fun natTofetchType x = + case Nat.toInt x of + 0 => Instruction | 1 => Data | _ => raise Fail "natTofetchType" + +fun natToArchitecture x = + case Nat.toInt x of + 0 => RV32I + | 1 => RV64I + | 2 => RV128I + | _ => raise Fail "natToArchitecture" + +fun natToPrivilege x = + case Nat.toInt x of + 0 => User + | 1 => Supervisor + | 2 => Hypervisor + | 3 => Machine + | _ => raise Fail "natToPrivilege" + +fun natToVM_Mode x = + case Nat.toInt x of + 0 => Mbare + | 1 => Mbb + | 2 => Mbbid + | 3 => Sv32 + | 4 => Sv39 + | 5 => Sv48 + | 6 => Sv57 + | 7 => Sv64 + | _ => raise Fail "natToVM_Mode" + +fun natToExtStatus x = + case Nat.toInt x of + 0 => Off + | 1 => Initial + | 2 => Clean + | 3 => Dirty + | _ => raise Fail "natToExtStatus" + +fun natToInterrupt x = + case Nat.toInt x of + 0 => Software | 1 => Timer | _ => raise Fail "natToInterrupt" + +fun natToExceptionType x = + case Nat.toInt x of + 0 => Fetch_Misaligned + | 1 => Fetch_Fault + | 2 => Illegal_Instr + | 3 => Breakpoint + | 4 => Load_Fault + | 5 => AMO_Misaligned + | 6 => Store_AMO_Fault + | 7 => UMode_Env_Call + | 8 => SMode_Env_Call + | 9 => HMode_Env_Call + | 10 => MMode_Env_Call + | _ => raise Fail "natToExceptionType" + +fun natToRounding x = + case Nat.toInt x of + 0 => RNE + | 1 => RTZ + | 2 => RDN + | 3 => RUP + | 4 => RMM + | 5 => RDYN + | _ => raise Fail "natToRounding" + +fun accessTypeToNat x = + case x of + Read => 0 | Write => 1 + +fun fetchTypeToNat x = + case x of + Instruction => 0 | Data => 1 + +fun ArchitectureToNat x = + case x of + RV32I => 0 | RV64I => 1 | RV128I => 2 + +fun PrivilegeToNat x = + case x of + User => 0 | Supervisor => 1 | Hypervisor => 2 | Machine => 3 + +fun VM_ModeToNat x = + case x of + Mbare => 0 + | Mbb => 1 + | Mbbid => 2 + | Sv32 => 3 + | Sv39 => 4 + | Sv48 => 5 + | Sv57 => 6 + | Sv64 => 7 + +fun ExtStatusToNat x = + case x of + Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 + +fun InterruptToNat x = + case x of + Software => 0 | Timer => 1 + +fun ExceptionTypeToNat x = + case x of + Fetch_Misaligned => 0 + | Fetch_Fault => 1 + | Illegal_Instr => 2 + | Breakpoint => 3 + | Load_Fault => 4 + | AMO_Misaligned => 5 + | Store_AMO_Fault => 6 + | UMode_Env_Call => 7 + | SMode_Env_Call => 8 + | HMode_Env_Call => 9 + | MMode_Env_Call => 10 + +fun RoundingToNat x = + case x of + RNE => 0 | RTZ => 1 | RDN => 2 | RUP => 3 | RMM => 4 | RDYN => 5 + +fun accessTypeToString x = + case x of + Read => "Read" | Write => "Write" + +fun fetchTypeToString x = + case x of + Instruction => "Instruction" | Data => "Data" + +fun ArchitectureToString x = + case x of + RV32I => "RV32I" | RV64I => "RV64I" | RV128I => "RV128I" + +fun PrivilegeToString x = + case x of + User => "User" + | Supervisor => "Supervisor" + | Hypervisor => "Hypervisor" + | Machine => "Machine" + +fun VM_ModeToString x = + case x of + Mbare => "Mbare" + | Mbb => "Mbb" + | Mbbid => "Mbbid" + | Sv32 => "Sv32" + | Sv39 => "Sv39" + | Sv48 => "Sv48" + | Sv57 => "Sv57" + | Sv64 => "Sv64" + +fun ExtStatusToString x = + case x of + Off => "Off" + | Initial => "Initial" + | Clean => "Clean" + | Dirty => "Dirty" + +fun InterruptToString x = + case x of + Software => "Software" | Timer => "Timer" + +fun ExceptionTypeToString x = + case x of + Fetch_Misaligned => "Fetch_Misaligned" + | Fetch_Fault => "Fetch_Fault" + | Illegal_Instr => "Illegal_Instr" + | Breakpoint => "Breakpoint" + | Load_Fault => "Load_Fault" + | AMO_Misaligned => "AMO_Misaligned" + | Store_AMO_Fault => "Store_AMO_Fault" + | UMode_Env_Call => "UMode_Env_Call" + | SMode_Env_Call => "SMode_Env_Call" + | HMode_Env_Call => "HMode_Env_Call" + | MMode_Env_Call => "MMode_Env_Call" + +fun RoundingToString x = + case x of + RNE => "RNE" + | RTZ => "RTZ" + | RDN => "RDN" + | RUP => "RUP" + | RMM => "RMM" + | RDYN => "RDYN" + +fun stringToaccessType x = + case x of + "Read" => Read + | "Write" => Write + | _ => raise Fail "stringToaccessType" + +fun stringTofetchType x = + case x of + "Instruction" => Instruction + | "Data" => Data + | _ => raise Fail "stringTofetchType" + +fun stringToArchitecture x = + case x of + "RV32I" => RV32I + | "RV64I" => RV64I + | "RV128I" => RV128I + | _ => raise Fail "stringToArchitecture" + +fun stringToPrivilege x = + case x of + "User" => User + | "Supervisor" => Supervisor + | "Hypervisor" => Hypervisor + | "Machine" => Machine + | _ => raise Fail "stringToPrivilege" + +fun stringToVM_Mode x = + case x of + "Mbare" => Mbare + | "Mbb" => Mbb + | "Mbbid" => Mbbid + | "Sv32" => Sv32 + | "Sv39" => Sv39 + | "Sv48" => Sv48 + | "Sv57" => Sv57 + | "Sv64" => Sv64 + | _ => raise Fail "stringToVM_Mode" + +fun stringToExtStatus x = + case x of + "Off" => Off + | "Initial" => Initial + | "Clean" => Clean + | "Dirty" => Dirty + | _ => raise Fail "stringToExtStatus" + +fun stringToInterrupt x = + case x of + "Software" => Software + | "Timer" => Timer + | _ => raise Fail "stringToInterrupt" + +fun stringToExceptionType x = + case x of + "Fetch_Misaligned" => Fetch_Misaligned + | "Fetch_Fault" => Fetch_Fault + | "Illegal_Instr" => Illegal_Instr + | "Breakpoint" => Breakpoint + | "Load_Fault" => Load_Fault + | "AMO_Misaligned" => AMO_Misaligned + | "Store_AMO_Fault" => Store_AMO_Fault + | "UMode_Env_Call" => UMode_Env_Call + | "SMode_Env_Call" => SMode_Env_Call + | "HMode_Env_Call" => HMode_Env_Call + | "MMode_Env_Call" => MMode_Env_Call + | _ => raise Fail "stringToExceptionType" + +fun stringToRounding x = + case x of + "RNE" => RNE + | "RTZ" => RTZ + | "RDN" => RDN + | "RUP" => RUP + | "RMM" => RMM + | "RDYN" => RDYN + | _ => raise Fail "stringToRounding" +end + +(* ------------------------------------------------------------------------- + Record update functions + ------------------------------------------------------------------------- *) + +fun mcpuid_ArchBase_rupd ({ArchBase, I, M, S, U, mcpuid'rst} + : mcpuid, x') = + {ArchBase = x', I = I, M = M, S = S, U = U, mcpuid'rst = mcpuid'rst} + : mcpuid + +fun mcpuid_I_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = + {ArchBase = ArchBase, I = x', M = M, S = S, U = U, + mcpuid'rst = mcpuid'rst}: mcpuid + +fun mcpuid_M_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = + {ArchBase = ArchBase, I = I, M = x', S = S, U = U, + mcpuid'rst = mcpuid'rst}: mcpuid + +fun mcpuid_S_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = + {ArchBase = ArchBase, I = I, M = M, S = x', U = U, + mcpuid'rst = mcpuid'rst}: mcpuid + +fun mcpuid_U_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = + {ArchBase = ArchBase, I = I, M = M, S = S, U = x', + mcpuid'rst = mcpuid'rst}: mcpuid + +fun mcpuid_mcpuid'rst_rupd ({ArchBase, I, M, S, U, mcpuid'rst} + : mcpuid, x') = + {ArchBase = ArchBase, I = I, M = M, S = S, U = U, mcpuid'rst = x'} + : mcpuid + +fun mimpid_RVImpl_rupd ({RVImpl, RVSource}: mimpid, x') = + {RVImpl = x', RVSource = RVSource}: mimpid + +fun mimpid_RVSource_rupd ({RVImpl, RVSource}: mimpid, x') = + {RVImpl = RVImpl, RVSource = x'}: mimpid + +fun mstatus_MFS_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = x', MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MIE_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = x', MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MIE1_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = x', MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MIE2_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = x', MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MIE3_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = x', + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MMPRV_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = x', MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = MPRV3, + MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus + +fun mstatus_MPRV_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = x', MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = MPRV3, + MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus + +fun mstatus_MPRV1_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = x', MPRV2 = MPRV2, MPRV3 = MPRV3, + MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus + +fun mstatus_MPRV2_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = x', MPRV3 = MPRV3, + MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus + +fun mstatus_MPRV3_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = x', + MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus + +fun mstatus_MSD_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = x', MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_MXS_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = x', VM = VM, mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_VM_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, + MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = x', mstatus'rst = mstatus'rst} + : mstatus + +fun mstatus_mstatus'rst_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, + MPRV1, MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = x'} + : mstatus + +fun mtdeleg_Exc_deleg_rupd ({Exc_deleg, Intr_deleg}: mtdeleg, x') = + {Exc_deleg = x', Intr_deleg = Intr_deleg}: mtdeleg + +fun mtdeleg_Intr_deleg_rupd ({Exc_deleg, Intr_deleg}: mtdeleg, x') = + {Exc_deleg = Exc_deleg, Intr_deleg = x'}: mtdeleg + +fun mip_HSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = x', HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, + STIP = STIP, mip'rst = mip'rst}: mip + +fun mip_HTIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = x', MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, + STIP = STIP, mip'rst = mip'rst}: mip + +fun mip_MSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = HTIP, MSIP = x', MTIP = MTIP, SSIP = SSIP, + STIP = STIP, mip'rst = mip'rst}: mip + +fun mip_MTIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = x', SSIP = SSIP, + STIP = STIP, mip'rst = mip'rst}: mip + +fun mip_SSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = x', + STIP = STIP, mip'rst = mip'rst}: mip + +fun mip_STIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, + STIP = x', mip'rst = mip'rst}: mip + +fun mip_mip'rst_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} + : mip, x') = + {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, + STIP = STIP, mip'rst = x'}: mip + +fun mie_HSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = x', HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, + STIE = STIE, mie'rst = mie'rst}: mie + +fun mie_HTIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = x', MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, + STIE = STIE, mie'rst = mie'rst}: mie + +fun mie_MSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = HTIE, MSIE = x', MTIE = MTIE, SSIE = SSIE, + STIE = STIE, mie'rst = mie'rst}: mie + +fun mie_MTIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = x', SSIE = SSIE, + STIE = STIE, mie'rst = mie'rst}: mie + +fun mie_SSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = x', + STIE = STIE, mie'rst = mie'rst}: mie + +fun mie_STIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, + STIE = x', mie'rst = mie'rst}: mie + +fun mie_mie'rst_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} + : mie, x') = + {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, + STIE = STIE, mie'rst = x'}: mie + +fun mcause_EC_rupd ({EC, Int, mcause'rst}: mcause, x') = + {EC = x', Int = Int, mcause'rst = mcause'rst}: mcause + +fun mcause_Int_rupd ({EC, Int, mcause'rst}: mcause, x') = + {EC = EC, Int = x', mcause'rst = mcause'rst}: mcause + +fun mcause_mcause'rst_rupd ({EC, Int, mcause'rst}: mcause, x') = + {EC = EC, Int = Int, mcause'rst = x'}: mcause + +fun MachineCSR_mbadaddr_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = x', mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mbase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = x', mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mbound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = x', mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mcause_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = x', + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mcpuid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = x', mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mdbase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = x', mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mdbound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = x', mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mepc_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = x', + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mfromhost_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = x', mhartid = mhartid, mibase = mibase, mibound = mibound, + mie = mie, mimpid = mimpid, mip = mip, mscratch = mscratch, + mstatus = mstatus, mtdeleg = mtdeleg, mtime_delta = mtime_delta, + mtimecmp = mtimecmp, mtohost = mtohost, mtvec = mtvec}: MachineCSR + +fun MachineCSR_mhartid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = x', mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mibase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = x', + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mibound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = x', mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mie_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, mdbase, + mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, mimpid, mip, + mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, mtohost, mtvec} + : MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = x', mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mimpid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = x', mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mip_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, mdbase, + mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, mimpid, mip, + mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, mtohost, mtvec} + : MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = x', + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mscratch_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = x', mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mstatus_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = x', mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mtdeleg_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = x', + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mtime_delta_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = x', mtimecmp = mtimecmp, mtohost = mtohost, mtvec = mtvec} + : MachineCSR + +fun MachineCSR_mtimecmp_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = x', mtohost = mtohost, + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mtohost_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = x', + mtvec = mtvec}: MachineCSR + +fun MachineCSR_mtvec_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, + mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, + mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, + mtohost, mtvec}: MachineCSR, x') = + {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, + mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, + mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, + mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, + mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, + mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, + mtvec = x'}: MachineCSR + +fun HypervisorCSR_hbadaddr_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = x', hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_hcause_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, + htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = x', hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_hepc_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, + htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = x', hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_hscratch_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = x', + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_hstatus_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = x', htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_htdeleg_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = x', htime_delta = htime_delta, + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_htime_delta_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = x', + htimecmp = htimecmp, htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_htimecmp_rupd ({hbadaddr, hcause, hepc, hscratch, + hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = x', htvec = htvec}: HypervisorCSR + +fun HypervisorCSR_htvec_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, + htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = + {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, + hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, + htimecmp = htimecmp, htvec = x'}: HypervisorCSR + +fun sstatus_SFS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = x', SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SIE_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = x', SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SMPRV_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = x', SPIE = SPIE, SPS = SPS, SSD = SSD, + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SPIE_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = x', SPS = SPS, SSD = SSD, + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SPS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = x', SSD = SSD, + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SSD_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = x', + SXS = SXS, sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_SXS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} + : sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, + SXS = x', sstatus'rst = sstatus'rst}: sstatus + +fun sstatus_sstatus'rst_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, + sstatus'rst}: sstatus, x') = + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, + SXS = SXS, sstatus'rst = x'}: sstatus + +fun sip_SSIP_rupd ({SSIP, STIP, sip'rst}: sip, x') = + {SSIP = x', STIP = STIP, sip'rst = sip'rst}: sip + +fun sip_STIP_rupd ({SSIP, STIP, sip'rst}: sip, x') = + {SSIP = SSIP, STIP = x', sip'rst = sip'rst}: sip + +fun sip_sip'rst_rupd ({SSIP, STIP, sip'rst}: sip, x') = + {SSIP = SSIP, STIP = STIP, sip'rst = x'}: sip + +fun sie_SSIE_rupd ({SSIE, STIE, sie'rst}: sie, x') = + {SSIE = x', STIE = STIE, sie'rst = sie'rst}: sie + +fun sie_STIE_rupd ({SSIE, STIE, sie'rst}: sie, x') = + {SSIE = SSIE, STIE = x', sie'rst = sie'rst}: sie + +fun sie_sie'rst_rupd ({SSIE, STIE, sie'rst}: sie, x') = + {SSIE = SSIE, STIE = STIE, sie'rst = x'}: sie + +fun SupervisorCSR_sasid_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = x', sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_sbadaddr_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = x', scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_scause_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = x', sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_sepc_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = x', + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_sptbr_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = x', sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_sscratch_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = x', stime_delta = stime_delta, + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_stime_delta_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = x', + stimecmp = stimecmp, stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_stimecmp_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = x', stvec = stvec}: SupervisorCSR + +fun SupervisorCSR_stvec_rupd ({sasid, sbadaddr, scause, sepc, sptbr, + sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = + {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, + sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, + stimecmp = stimecmp, stvec = x'}: SupervisorCSR + +fun FPCSR_DZ_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = x', FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_FRM_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = DZ, FRM = x', NV = NV, NX = NX, OF = OF, UF = UF, + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_NV_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = DZ, FRM = FRM, NV = x', NX = NX, OF = OF, UF = UF, + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_NX_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = DZ, FRM = FRM, NV = NV, NX = x', OF = OF, UF = UF, + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_OF_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = x', UF = UF, + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_UF_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = + {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = x', + fpcsr'rst = fpcsr'rst}: FPCSR + +fun FPCSR_fpcsr'rst_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst} + : FPCSR, x') = + {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, fpcsr'rst = x'} + : FPCSR + +fun UserCSR_cycle_delta_rupd ({cycle_delta, fpcsr, instret_delta, + time_delta}: UserCSR, x') = + {cycle_delta = x', fpcsr = fpcsr, instret_delta = instret_delta, + time_delta = time_delta}: UserCSR + +fun UserCSR_fpcsr_rupd ({cycle_delta, fpcsr, instret_delta, time_delta} + : UserCSR, x') = + {cycle_delta = cycle_delta, fpcsr = x', instret_delta = instret_delta, + time_delta = time_delta}: UserCSR + +fun UserCSR_instret_delta_rupd ({cycle_delta, fpcsr, instret_delta, + time_delta}: UserCSR, x') = + {cycle_delta = cycle_delta, fpcsr = fpcsr, instret_delta = x', + time_delta = time_delta}: UserCSR + +fun UserCSR_time_delta_rupd ({cycle_delta, fpcsr, instret_delta, + time_delta}: UserCSR, x') = + {cycle_delta = cycle_delta, fpcsr = fpcsr, + instret_delta = instret_delta, time_delta = x'}: UserCSR + +fun SynchronousTrap_badaddr_rupd ({badaddr, trap}: SynchronousTrap, x') = + {badaddr = x', trap = trap}: SynchronousTrap + +fun SynchronousTrap_trap_rupd ({badaddr, trap}: SynchronousTrap, x') = + {badaddr = badaddr, trap = x'}: SynchronousTrap + +fun StateDelta_addr_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = x', data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_data1_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = x', data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_data2_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = x', exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_exc_taken_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = x', + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_fetch_exc_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = x', fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_fp_data_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = x', pc = pc, rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_pc_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = x', rinstr = rinstr, + st_width = st_width}: StateDelta + +fun StateDelta_rinstr_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = x', + st_width = st_width}: StateDelta + +fun StateDelta_st_width_rupd ({addr, data1, data2, exc_taken, fetch_exc, + fp_data, pc, rinstr, st_width}: StateDelta, x') = + {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, + fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, + st_width = x'}: StateDelta + +fun SV_PTE_PTE_D_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = x', PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_PTE_PPNi_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = x', PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_PTE_R_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = x', PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_PTE_SW_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = x', + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_PTE_T_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = x', PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_PTE_V_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = x', sv_pte'rst = sv_pte'rst}: SV_PTE + +fun SV_PTE_sv_pte'rst_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, + sv_pte'rst}: SV_PTE, x') = + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = x'}: SV_PTE + +fun SV_Vaddr_Sv_PgOfs_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} + : SV_Vaddr, x') = + {Sv_PgOfs = x', Sv_VPNi = Sv_VPNi, sv_vaddr'rst = sv_vaddr'rst} + : SV_Vaddr + +fun SV_Vaddr_Sv_VPNi_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} + : SV_Vaddr, x') = + {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = x', sv_vaddr'rst = sv_vaddr'rst} + : SV_Vaddr + +fun SV_Vaddr_sv_vaddr'rst_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} + : SV_Vaddr, x') = + {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = Sv_VPNi, sv_vaddr'rst = x'}: SV_Vaddr + +fun TLBEntry_age_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = x', asid = asid, global = global, pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_asid_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = x', global = global, pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_global_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = x', pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_pAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = x', pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_pte_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = pAddr, pte = x', + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_pteAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, + pteAddr = x', vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_vAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, + vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = x', vAddrMask = vAddrMask, + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_vAddrMask_rupd ({age, asid, global, pAddr, pte, pteAddr, + vAddr, vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = x', + vMatchMask = vMatchMask}: TLBEntry + +fun TLBEntry_vMatchMask_rupd ({age, asid, global, pAddr, pte, pteAddr, + vAddr, vAddrMask, vMatchMask}: TLBEntry, x') = + {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, + pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, + vMatchMask = x'}: TLBEntry + +(* ------------------------------------------------------------------------- + Exceptions + ------------------------------------------------------------------------- *) + +exception INTERNAL_ERROR of string + +exception UNDEFINED of string + +(* ------------------------------------------------------------------------- + Global variables (state) + ------------------------------------------------------------------------- *) + +val MEM8 = ref (Map.mkMap(SOME 18446744073709551616,BitsN.B(0x0,8))) + : (BitsN.nbit Map.map) ref + +val c_ExitCode = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) + : (BitsN.nbit Map.map) ref + +val c_HCSR = ref + (Map.mkMap + (SOME 256, + {hbadaddr = BitsN.B(0x0,64), + hcause = + {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, + hepc = BitsN.B(0x0,64), hscratch = BitsN.B(0x0,64), + hstatus = + {MFS = BitsN.B(0x0,2), MIE = false, MIE1 = false, MIE2 = false, + MIE3 = false, MMPRV = false, MPRV = BitsN.B(0x0,2), + MPRV1 = BitsN.B(0x0,2), MPRV2 = BitsN.B(0x0,2), + MPRV3 = BitsN.B(0x0,2), MSD = false, MXS = BitsN.B(0x0,2), + VM = BitsN.B(0x0,5), mstatus'rst = BitsN.B(0x0,41)}, + htdeleg = + {Exc_deleg = BitsN.B(0x0,16), Intr_deleg = BitsN.B(0x0,48)}, + htime_delta = BitsN.B(0x0,64), htimecmp = BitsN.B(0x0,64), + htvec = BitsN.B(0x0,64)})): (HypervisorCSR Map.map) ref + +val c_MCSR = ref + (Map.mkMap + (SOME 256, + {mbadaddr = BitsN.B(0x0,64), mbase = BitsN.B(0x0,64), + mbound = BitsN.B(0x0,64), + mcause = + {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, + mcpuid = + {ArchBase = BitsN.B(0x0,2), I = false, M = false, S = false, + U = false, mcpuid'rst = BitsN.B(0x0,58)}, + mdbase = BitsN.B(0x0,64), mdbound = BitsN.B(0x0,64), + mepc = BitsN.B(0x0,64), mfromhost = BitsN.B(0x0,64), + mhartid = BitsN.B(0x0,64), mibase = BitsN.B(0x0,64), + mibound = BitsN.B(0x0,64), + mie = + {HSIE = false, HTIE = false, MSIE = false, MTIE = false, + SSIE = false, STIE = false, mie'rst = BitsN.B(0x0,58)}, + mimpid = {RVImpl = BitsN.B(0x0,48), RVSource = BitsN.B(0x0,16)}, + mip = + {HSIP = false, HTIP = false, MSIP = false, MTIP = false, + SSIP = false, STIP = false, mip'rst = BitsN.B(0x0,58)}, + mscratch = BitsN.B(0x0,64), + mstatus = + {MFS = BitsN.B(0x0,2), MIE = false, MIE1 = false, MIE2 = false, + MIE3 = false, MMPRV = false, MPRV = BitsN.B(0x0,2), + MPRV1 = BitsN.B(0x0,2), MPRV2 = BitsN.B(0x0,2), + MPRV3 = BitsN.B(0x0,2), MSD = false, MXS = BitsN.B(0x0,2), + VM = BitsN.B(0x0,5), mstatus'rst = BitsN.B(0x0,41)}, + mtdeleg = + {Exc_deleg = BitsN.B(0x0,16), Intr_deleg = BitsN.B(0x0,48)}, + mtime_delta = BitsN.B(0x0,64), mtimecmp = BitsN.B(0x0,64), + mtohost = BitsN.B(0x0,64), mtvec = BitsN.B(0x0,64)})) + : (MachineCSR Map.map) ref + +val c_NextFetch = ref (Map.mkMap(SOME 256,NONE)) + : ((TransferControl option) Map.map) ref + +val c_PC = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) + : (BitsN.nbit Map.map) ref + +val c_ReserveLoad = ref (Map.mkMap(SOME 256,NONE)) + : ((BitsN.nbit option) Map.map) ref + +val c_SCSR = ref + (Map.mkMap + (SOME 256, + {sasid = BitsN.B(0x0,64), sbadaddr = BitsN.B(0x0,64), + scause = + {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, + sepc = BitsN.B(0x0,64), sptbr = BitsN.B(0x0,64), + sscratch = BitsN.B(0x0,64), stime_delta = BitsN.B(0x0,64), + stimecmp = BitsN.B(0x0,64), stvec = BitsN.B(0x0,64)})) + : (SupervisorCSR Map.map) ref + +val c_UCSR = ref + (Map.mkMap + (SOME 256, + {cycle_delta = BitsN.B(0x0,64), + fpcsr = + {DZ = false, FRM = BitsN.B(0x0,3), NV = false, NX = false, + OF = false, UF = false, fpcsr'rst = BitsN.B(0x0,24)}, + instret_delta = BitsN.B(0x0,64), time_delta = BitsN.B(0x0,64)})) + : (UserCSR Map.map) ref + +val c_cycles = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) + : (BitsN.nbit Map.map) ref + +val c_fpr = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 32,BitsN.B(0x0,64)))) + : ((BitsN.nbit Map.map) Map.map) ref + +val c_gpr = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 32,BitsN.B(0x0,64)))) + : ((BitsN.nbit Map.map) Map.map) ref + +val c_instret = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) + : (BitsN.nbit Map.map) ref + +val c_tlb = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 16,NONE))) + : (((TLBEntry option) Map.map) Map.map) ref + +val c_update = ref + (Map.mkMap + (SOME 256, + {addr = NONE, data1 = NONE, data2 = NONE, exc_taken = false, + fetch_exc = false, fp_data = NONE, pc = BitsN.B(0x0,64), + rinstr = BitsN.B(0x0,32), st_width = NONE})) + : (StateDelta Map.map) ref + +val clock = ref (BitsN.B(0x0,64)): BitsN.nbit ref + +val done = ref (false): bool ref + +val log = ref ([]): ((Nat.nat * string) list) ref + +val procID = ref (BitsN.B(0x0,8)): BitsN.nbit ref + +val totalCore = ref (0): Nat.nat ref + +(* ------------------------------------------------------------------------- + Main specification + ------------------------------------------------------------------------- *) + +local + fun tuple'32 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, + t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, + t31] = + (t0, + (t1, + (t2, + (t3, + (t4, + (t5, + (t6, + (t7, + (t8, + (t9, + (t10, + (t11, + (t12, + (t13, + (t14, + (t15, + (t16, + (t17, + (t18, + (t19, + (t20, + (t21, + (t22, + (t23, + (t24,(t25,(t26,(t27,(t28,(t29,(t30,t31))))))))))))))))))))))))))))))) + | tuple'32 (_: bool list) = raise Fail "tuple'32" +in + val boolify'32 = tuple'32 o BitsN.toList +end + +val ASID_SIZE = 6 + +val PAGESIZE_BITS = 12 + +val LEVEL_BITS = 9 + +val BYTE = BitsN.B(0x0,3) + +val HALFWORD = BitsN.B(0x1,3) + +val WORD = BitsN.B(0x3,3) + +val DOUBLEWORD = BitsN.B(0x7,3) + +fun archBase a = + case a of + RV32I => BitsN.B(0x0,2) + | RV64I => BitsN.B(0x2,2) + | RV128I => BitsN.B(0x3,2); + +fun architecture ab = + case ab of + BitsN.B(0x0,_) => RV32I + | BitsN.B(0x2,_) => RV64I + | BitsN.B(0x3,_) => RV128I + | _ => + raise UNDEFINED + ("Unknown architecture: " ^ (Nat.toString(BitsN.toNat ab))); + +fun archName a = + case a of RV32I => "RV32I" | RV64I => "RV64I" | RV128I => "RV128I"; + +fun privLevel p = + case p of + User => BitsN.B(0x0,2) + | Supervisor => BitsN.B(0x1,2) + | Hypervisor => BitsN.B(0x2,2) + | Machine => BitsN.B(0x3,2); + +fun privilege p = + case p of + BitsN.B(0x0,_) => User + | BitsN.B(0x1,_) => Supervisor + | BitsN.B(0x2,_) => Hypervisor + | BitsN.B(0x3,_) => Machine + | _ => raise General.Bind; + +fun privName p = + case p of + User => "U" + | Supervisor => "S" + | Hypervisor => "H" + | Machine => "M"; + +fun vmType vm = + case vm of + BitsN.B(0x0,_) => Mbare + | BitsN.B(0x1,_) => Mbb + | BitsN.B(0x2,_) => Mbbid + | BitsN.B(0x8,_) => Sv32 + | BitsN.B(0x9,_) => Sv39 + | BitsN.B(0xA,_) => Sv48 + | BitsN.B(0xB,_) => Sv57 + | BitsN.B(0xC,_) => Sv64 + | _ => + raise UNDEFINED + ("Unknown address translation mode: " + ^ + (Nat.toString(BitsN.toNat vm))); + +fun isValidVM vm = + case vm of + BitsN.B(0x0,_) => true + | BitsN.B(0x1,_) => true + | BitsN.B(0x2,_) => true + | BitsN.B(0x8,_) => true + | BitsN.B(0x9,_) => true + | BitsN.B(0xA,_) => true + | BitsN.B(0xB,_) => true + | BitsN.B(0xC,_) => true + | _ => false; + +fun vmMode vm = + case vm of + Mbare => BitsN.B(0x0,5) + | Mbb => BitsN.B(0x1,5) + | Mbbid => BitsN.B(0x2,5) + | Sv32 => BitsN.B(0x8,5) + | Sv39 => BitsN.B(0x9,5) + | Sv48 => BitsN.B(0xA,5) + | Sv57 => BitsN.B(0xB,5) + | Sv64 => BitsN.B(0xC,5); + +fun vmModeName vm = + case vm of + Mbare => "Mbare" + | Mbb => "Mbb" + | Mbbid => "Mbbid" + | Sv32 => "Sv32" + | Sv39 => "Sv39" + | Sv48 => "Sv48" + | Sv57 => "Sv57" + | Sv64 => "Sv64"; + +fun ext_status e = + case e of + Off => BitsN.B(0x0,2) + | Initial => BitsN.B(0x1,2) + | Clean => BitsN.B(0x2,2) + | Dirty => BitsN.B(0x3,2); + +fun extStatus e = + case e of + BitsN.B(0x0,_) => Off + | BitsN.B(0x1,_) => Initial + | BitsN.B(0x2,_) => Clean + | BitsN.B(0x3,_) => Dirty + | _ => raise General.Bind; + +fun extStatusName e = + case e of + Off => "Off" + | Initial => "Initial" + | Clean => "Clean" + | Dirty => "Dirty"; + +fun interruptIndex i = + case i of Software => BitsN.B(0x0,4) | Timer => BitsN.B(0x1,4); + +fun excCode e = + case e of + Fetch_Misaligned => BitsN.B(0x0,4) + | Fetch_Fault => BitsN.B(0x1,4) + | Illegal_Instr => BitsN.B(0x2,4) + | Breakpoint => BitsN.B(0x3,4) + | Load_Fault => BitsN.B(0x5,4) + | AMO_Misaligned => BitsN.B(0x6,4) + | Store_AMO_Fault => BitsN.B(0x7,4) + | UMode_Env_Call => BitsN.B(0x8,4) + | SMode_Env_Call => BitsN.B(0x9,4) + | HMode_Env_Call => BitsN.B(0xA,4) + | MMode_Env_Call => BitsN.B(0xB,4); + +fun excType e = + case e of + BitsN.B(0x0,_) => Fetch_Misaligned + | BitsN.B(0x1,_) => Fetch_Fault + | BitsN.B(0x2,_) => Illegal_Instr + | BitsN.B(0x3,_) => Breakpoint + | BitsN.B(0x5,_) => Load_Fault + | BitsN.B(0x6,_) => AMO_Misaligned + | BitsN.B(0x7,_) => Store_AMO_Fault + | BitsN.B(0x8,_) => UMode_Env_Call + | BitsN.B(0x9,_) => SMode_Env_Call + | BitsN.B(0xA,_) => HMode_Env_Call + | BitsN.B(0xB,_) => MMode_Env_Call + | _ => + raise UNDEFINED + ("Unknown exception: " ^ (Nat.toString(BitsN.toNat e))); + +fun excName e = + case e of + Fetch_Misaligned => "MISALIGNED_FETCH" + | Fetch_Fault => "FAULT_FETCH" + | Illegal_Instr => "ILLEGAL_INSTRUCTION" + | Breakpoint => "BREAKPOINT" + | Load_Fault => "FAULT_LOAD" + | AMO_Misaligned => "MISALIGNED_AMO" + | Store_AMO_Fault => "FAULT_STORE_AMO" + | UMode_Env_Call => "U-EnvCall" + | SMode_Env_Call => "S-EnvCall" + | HMode_Env_Call => "H-EnvCall" + | MMode_Env_Call => "M-EnvCall"; + +fun rec'mcpuid x = + {ArchBase = BitsN.bits(63,62) x, I = BitsN.bit(x,8), + M = BitsN.bit(x,12), S = BitsN.bit(x,18), U = BitsN.bit(x,20), + mcpuid'rst = + BitsN.concat + [BitsN.bits(7,0) x,BitsN.bits(11,9) x,BitsN.bits(17,13) x, + BitsN.bits(19,19) x,BitsN.bits(61,21) x]}; + +fun reg'mcpuid x = + case x of + {ArchBase = ArchBase, I = I, M = M, S = S, U = U, + mcpuid'rst = mcpuid'rst} => + BitsN.concat + [ArchBase,BitsN.bits(40,0) mcpuid'rst,BitsN.fromBit U, + BitsN.bits(41,41) mcpuid'rst,BitsN.fromBit S, + BitsN.bits(46,42) mcpuid'rst,BitsN.fromBit M, + BitsN.bits(49,47) mcpuid'rst,BitsN.fromBit I, + BitsN.bits(57,50) mcpuid'rst]; + +fun write'rec'mcpuid (_,x) = reg'mcpuid x; + +fun write'reg'mcpuid (_,x) = rec'mcpuid x; + +fun rec'mimpid x = + {RVImpl = BitsN.bits(63,16) x, RVSource = BitsN.bits(15,0) x}; + +fun reg'mimpid x = + case x of + {RVImpl = RVImpl, RVSource = RVSource} => BitsN.@@(RVImpl,RVSource); + +fun write'rec'mimpid (_,x) = reg'mimpid x; + +fun write'reg'mimpid (_,x) = rec'mimpid x; + +fun rec'mstatus x = + {MFS = BitsN.bits(13,12) x, MIE = BitsN.bit(x,0), MIE1 = BitsN.bit(x,3), + MIE2 = BitsN.bit(x,6), MIE3 = BitsN.bit(x,9), MMPRV = BitsN.bit(x,16), + MPRV = BitsN.bits(2,1) x, MPRV1 = BitsN.bits(5,4) x, + MPRV2 = BitsN.bits(8,7) x, MPRV3 = BitsN.bits(11,10) x, + MSD = BitsN.bit(x,63), MXS = BitsN.bits(15,14) x, + VM = BitsN.bits(21,17) x, mstatus'rst = BitsN.bits(62,22) x}; + +fun reg'mstatus x = + case x of + {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, + MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, + MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, + mstatus'rst = mstatus'rst} => + BitsN.concat + [BitsN.fromBit MSD,mstatus'rst,VM,BitsN.fromBit MMPRV,MXS,MFS, + MPRV3,BitsN.fromBit MIE3,MPRV2,BitsN.fromBit MIE2,MPRV1, + BitsN.fromBit MIE1,MPRV,BitsN.fromBit MIE]; + +fun write'rec'mstatus (_,x) = reg'mstatus x; + +fun write'reg'mstatus (_,x) = rec'mstatus x; + +fun rec'mtdeleg x = + {Exc_deleg = BitsN.bits(15,0) x, Intr_deleg = BitsN.bits(63,16) x}; + +fun reg'mtdeleg x = + case x of + {Exc_deleg = Exc_deleg, Intr_deleg = Intr_deleg} => + BitsN.@@(Intr_deleg,Exc_deleg); + +fun write'rec'mtdeleg (_,x) = reg'mtdeleg x; + +fun write'reg'mtdeleg (_,x) = rec'mtdeleg x; + +fun rec'mip x = + {HSIP = BitsN.bit(x,2), HTIP = BitsN.bit(x,6), MSIP = BitsN.bit(x,3), + MTIP = BitsN.bit(x,7), SSIP = BitsN.bit(x,1), STIP = BitsN.bit(x,5), + mip'rst = + BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,4) x,BitsN.bits(63,8) x]}; + +fun reg'mip x = + case x of + {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, + STIP = STIP, mip'rst = mip'rst} => + BitsN.concat + [BitsN.bits(55,0) mip'rst,BitsN.fromBit MTIP,BitsN.fromBit HTIP, + BitsN.fromBit STIP,BitsN.bits(56,56) mip'rst,BitsN.fromBit MSIP, + BitsN.fromBit HSIP,BitsN.fromBit SSIP,BitsN.bits(57,57) mip'rst]; + +fun write'rec'mip (_,x) = reg'mip x; + +fun write'reg'mip (_,x) = rec'mip x; + +fun rec'mie x = + {HSIE = BitsN.bit(x,2), HTIE = BitsN.bit(x,6), MSIE = BitsN.bit(x,3), + MTIE = BitsN.bit(x,7), SSIE = BitsN.bit(x,1), STIE = BitsN.bit(x,5), + mie'rst = + BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,4) x,BitsN.bits(63,8) x]}; + +fun reg'mie x = + case x of + {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, + STIE = STIE, mie'rst = mie'rst} => + BitsN.concat + [BitsN.bits(55,0) mie'rst,BitsN.fromBit MTIE,BitsN.fromBit HTIE, + BitsN.fromBit STIE,BitsN.bits(56,56) mie'rst,BitsN.fromBit MSIE, + BitsN.fromBit HSIE,BitsN.fromBit SSIE,BitsN.bits(57,57) mie'rst]; + +fun write'rec'mie (_,x) = reg'mie x; + +fun write'reg'mie (_,x) = rec'mie x; + +fun rec'mcause x = + {EC = BitsN.bits(3,0) x, Int = BitsN.bit(x,63), + mcause'rst = BitsN.bits(62,4) x}; + +fun reg'mcause x = + case x of + {EC = EC, Int = Int, mcause'rst = mcause'rst} => + BitsN.concat[BitsN.fromBit Int,mcause'rst,EC]; + +fun write'rec'mcause (_,x) = reg'mcause x; + +fun write'reg'mcause (_,x) = rec'mcause x; + +fun rec'sstatus x = + {SFS = BitsN.bits(13,12) x, SIE = BitsN.bit(x,0), + SMPRV = BitsN.bit(x,16), SPIE = BitsN.bit(x,3), SPS = BitsN.bit(x,4), + SSD = BitsN.bit(x,63), SXS = BitsN.bits(15,14) x, + sstatus'rst = + BitsN.concat + [BitsN.bits(2,1) x,BitsN.bits(11,5) x,BitsN.bits(62,17) x]}; + +fun reg'sstatus x = + case x of + {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, + SSD = SSD, SXS = SXS, sstatus'rst = sstatus'rst} => + BitsN.concat + [BitsN.fromBit SSD,BitsN.bits(45,0) sstatus'rst, + BitsN.fromBit SMPRV,SXS,SFS,BitsN.bits(52,46) sstatus'rst, + BitsN.fromBit SPS,BitsN.fromBit SPIE, + BitsN.bits(54,53) sstatus'rst,BitsN.fromBit SIE]; + +fun write'rec'sstatus (_,x) = reg'sstatus x; + +fun write'reg'sstatus (_,x) = rec'sstatus x; + +fun rec'sip x = + {SSIP = BitsN.bit(x,1), STIP = BitsN.bit(x,5), + sip'rst = + BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,2) x,BitsN.bits(63,6) x]}; + +fun reg'sip x = + case x of + {SSIP = SSIP, STIP = STIP, sip'rst = sip'rst} => + BitsN.concat + [BitsN.bits(57,0) sip'rst,BitsN.fromBit STIP, + BitsN.bits(60,58) sip'rst,BitsN.fromBit SSIP, + BitsN.bits(61,61) sip'rst]; + +fun write'rec'sip (_,x) = reg'sip x; + +fun write'reg'sip (_,x) = rec'sip x; + +fun rec'sie x = + {SSIE = BitsN.bit(x,1), STIE = BitsN.bit(x,5), + sie'rst = + BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,2) x,BitsN.bits(63,6) x]}; + +fun reg'sie x = + case x of + {SSIE = SSIE, STIE = STIE, sie'rst = sie'rst} => + BitsN.concat + [BitsN.bits(57,0) sie'rst,BitsN.fromBit STIE, + BitsN.bits(60,58) sie'rst,BitsN.fromBit SSIE, + BitsN.bits(61,61) sie'rst]; + +fun write'rec'sie (_,x) = reg'sie x; + +fun write'reg'sie (_,x) = rec'sie x; + +fun rec'FPCSR x = + {DZ = BitsN.bit(x,3), FRM = BitsN.bits(7,5) x, NV = BitsN.bit(x,4), + NX = BitsN.bit(x,0), OF = BitsN.bit(x,2), UF = BitsN.bit(x,1), + fpcsr'rst = BitsN.bits(31,8) x}; + +fun reg'FPCSR x = + case x of + {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, + fpcsr'rst = fpcsr'rst} => + BitsN.concat + [fpcsr'rst,FRM,BitsN.fromBit NV,BitsN.fromBit DZ, + BitsN.fromBit OF,BitsN.fromBit UF,BitsN.fromBit NX]; + +fun write'rec'FPCSR (_,x) = reg'FPCSR x; + +fun write'reg'FPCSR (_,x) = rec'FPCSR x; + +fun lift_mip_sip mip = + let + val sip = ref (rec'sip(BitsN.B(0x0,64))) + in + ( sip := (sip_STIP_rupd((!sip),#STIP(mip : mip))) + ; sip := (sip_SSIP_rupd((!sip),#SSIP(mip : mip))) + ; (!sip) + ) + end; + +fun lift_mie_sie mie = + let + val sie = ref (rec'sie(BitsN.B(0x0,64))) + in + ( sie := (sie_STIE_rupd((!sie),#STIE(mie : mie))) + ; sie := (sie_SSIE_rupd((!sie),#SSIE(mie : mie))) + ; (!sie) + ) + end; + +fun lower_sip_mip (sip,mip) = + let + val m = ref mip + in + ( m := (mip_STIP_rupd((!m),#STIP(sip : sip))) + ; m := (mip_SSIP_rupd((!m),#SSIP(sip : sip))) + ; (!m) + ) + end; + +fun lower_sie_mie (sie,mie) = + let + val m = ref mie + in + ( m := (mie_STIE_rupd((!m),#STIE(sie : sie))) + ; m := (mie_SSIE_rupd((!m),#SSIE(sie : sie))) + ; (!m) + ) + end; + +fun update_mstatus (orig,v) = + let + val mt = ref orig + in + ( mt := (mstatus_MIE_rupd((!mt),#MIE(v : mstatus))) + ; mt := (mstatus_MPRV_rupd((!mt),#MPRV(v : mstatus))) + ; mt := (mstatus_MIE1_rupd((!mt),#MIE1(v : mstatus))) + ; mt := (mstatus_MPRV1_rupd((!mt),#MPRV1(v : mstatus))) + ; mt := (mstatus_MIE2_rupd((!mt),#MIE2(v : mstatus))) + ; mt := (mstatus_MPRV2_rupd((!mt),#MPRV2(v : mstatus))) + ; mt := (mstatus_MIE3_rupd((!mt),#MIE3(v : mstatus))) + ; mt := (mstatus_MPRV3_rupd((!mt),#MPRV3(v : mstatus))) + ; if isValidVM(#VM(v : mstatus)) + then mt := (mstatus_VM_rupd((!mt),#VM(v : mstatus))) + else () + ; mt := (mstatus_MMPRV_rupd((!mt),#MMPRV(v : mstatus))) + ; mt := (mstatus_MFS_rupd((!mt),#MFS(v : mstatus))) + ; mt := (mstatus_MXS_rupd((!mt),#MXS(v : mstatus))) + ; mt := + (mstatus_MSD_rupd + ((!mt), + ((extStatus(#MXS(v : mstatus))) = Dirty) orelse + ((extStatus(#MFS(v : mstatus))) = Dirty))) + ; (!mt) + ) + end; + +fun lift_mstatus_sstatus mst = + let + val st = ref (rec'sstatus(BitsN.B(0x0,64))) + in + ( st := (sstatus_SMPRV_rupd((!st),#MMPRV(mst : mstatus))) + ; st := (sstatus_SXS_rupd((!st),#MXS(mst : mstatus))) + ; st := (sstatus_SFS_rupd((!st),#MFS(mst : mstatus))) + ; st := + (sstatus_SSD_rupd + ((!st), + ((extStatus(#MXS(mst : mstatus))) = Dirty) orelse + ((extStatus(#MFS(mst : mstatus))) = Dirty))) + ; st := + (sstatus_SPS_rupd + ((!st),not((privilege(#MPRV1(mst : mstatus))) = User))) + ; st := (sstatus_SPIE_rupd((!st),#MIE1(mst : mstatus))) + ; st := (sstatus_SIE_rupd((!st),#MIE(mst : mstatus))) + ; (!st) + ) + end; + +fun lower_sstatus_mstatus (sst,mst) = + let + val mt = ref (rec'mstatus(reg'mstatus mst)) + in + ( mt := (mstatus_MMPRV_rupd((!mt),#SMPRV(sst : sstatus))) + ; mt := (mstatus_MXS_rupd((!mt),#SXS(sst : sstatus))) + ; mt := (mstatus_MFS_rupd((!mt),#SFS(sst : sstatus))) + ; mt := + (mstatus_MPRV1_rupd + ((!mt), + privLevel(if #SPS(sst : sstatus) then Supervisor else User))) + ; mt := (mstatus_MIE1_rupd((!mt),#SPIE(sst : sstatus))) + ; mt := (mstatus_MIE_rupd((!mt),#SIE(sst : sstatus))) + ; update_mstatus(mst,(!mt)) + ) + end; + +fun popPrivilegeStack mst = + let + val st = ref mst + in + ( st := (mstatus_MIE_rupd((!st),#MIE1(mst : mstatus))) + ; st := (mstatus_MPRV_rupd((!st),#MPRV1(mst : mstatus))) + ; st := (mstatus_MIE1_rupd((!st),#MIE2(mst : mstatus))) + ; st := (mstatus_MPRV1_rupd((!st),#MPRV2(mst : mstatus))) + ; st := (mstatus_MIE2_rupd((!st),true)) + ; st := (mstatus_MPRV2_rupd((!st),privLevel User)) + ; (!st) + ) + end; + +fun pushPrivilegeStack (mst,p) = + let + val st = ref mst + in + ( st := (mstatus_MIE2_rupd((!st),#MIE1(mst : mstatus))) + ; st := (mstatus_MPRV2_rupd((!st),#MPRV1(mst : mstatus))) + ; st := (mstatus_MIE1_rupd((!st),#MIE(mst : mstatus))) + ; st := (mstatus_MPRV1_rupd((!st),#MPRV(mst : mstatus))) + ; st := (mstatus_MIE_rupd((!st),false)) + ; st := (mstatus_MPRV_rupd((!st),privLevel p)) + ; (!st) + ) + end; + +fun scheduleCore id = + if Nat.<(id,(!totalCore)) then procID := (BitsN.fromNat(id,8)) else (); + +fun gpr n = + let + val m = Map.copy(Map.lookup((!c_gpr),BitsN.toNat (!procID))) + in + Map.lookup(m,BitsN.toNat n) + end; + +fun write'gpr (value,n) = + let + val m = ref (Map.copy(Map.lookup((!c_gpr),BitsN.toNat (!procID)))) + in + ( m := (Map.update((!m),BitsN.toNat n,value)) + ; c_gpr := (Map.update((!c_gpr),BitsN.toNat (!procID),Map.copy (!m))) + ) + end; + +fun fcsr () = + #fpcsr((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR); + +fun write'fcsr value = + ( let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID),UserCSR_fpcsr_rupd(x0,value))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) + end + ); + +fun fpr n = + let + val m = Map.copy(Map.lookup((!c_fpr),BitsN.toNat (!procID))) + in + Map.lookup(m,BitsN.toNat n) + end; + +fun write'fpr (value,n) = + let + val m = ref (Map.copy(Map.lookup((!c_fpr),BitsN.toNat (!procID)))) + in + ( m := (Map.update((!m),BitsN.toNat n,value)) + ; c_fpr := (Map.update((!c_fpr),BitsN.toNat (!procID),Map.copy (!m))) + ) + end; + +fun PC () = Map.lookup((!c_PC),BitsN.toNat (!procID)); + +fun write'PC value = + c_PC := (Map.update((!c_PC),BitsN.toNat (!procID),value)); + +fun UCSR () = Map.lookup((!c_UCSR),BitsN.toNat (!procID)); + +fun write'UCSR value = + c_UCSR := (Map.update((!c_UCSR),BitsN.toNat (!procID),value)); + +fun SCSR () = Map.lookup((!c_SCSR),BitsN.toNat (!procID)); + +fun write'SCSR value = + c_SCSR := (Map.update((!c_SCSR),BitsN.toNat (!procID),value)); + +fun HCSR () = Map.lookup((!c_HCSR),BitsN.toNat (!procID)); + +fun write'HCSR value = + c_HCSR := (Map.update((!c_HCSR),BitsN.toNat (!procID),value)); + +fun MCSR () = Map.lookup((!c_MCSR),BitsN.toNat (!procID)); + +fun write'MCSR value = + c_MCSR := (Map.update((!c_MCSR),BitsN.toNat (!procID),value)); + +fun NextFetch () = Map.lookup((!c_NextFetch),BitsN.toNat (!procID)); + +fun write'NextFetch value = + c_NextFetch := (Map.update((!c_NextFetch),BitsN.toNat (!procID),value)); + +fun ReserveLoad () = Map.lookup((!c_ReserveLoad),BitsN.toNat (!procID)); + +fun write'ReserveLoad value = + c_ReserveLoad := + (Map.update((!c_ReserveLoad),BitsN.toNat (!procID),value)); + +fun ExitCode () = Map.lookup((!c_ExitCode),BitsN.toNat (!procID)); + +fun write'ExitCode value = + c_ExitCode := (Map.update((!c_ExitCode),BitsN.toNat (!procID),value)); + +fun curArch () = + architecture(#ArchBase((#mcpuid((MCSR ()) : MachineCSR)) : mcpuid)); + +fun in32BitMode () = (curArch ()) = RV32I; + +fun curPrivilege () = + privilege(#MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)); + +fun curEPC () = + case curPrivilege () of + User => raise INTERNAL_ERROR "No EPC in U-mode" + | Supervisor => #sepc((SCSR ()) : SupervisorCSR) + | Hypervisor => #hepc((HCSR ()) : HypervisorCSR) + | Machine => #mepc((MCSR ()) : MachineCSR); + +fun sendIPI core = + let + val id = BitsN.fromNat(BitsN.toNat core,8) + in + if Nat.<(BitsN.toNat id,(!totalCore)) + then let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat id) + val x1 = #mip(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat id, + MachineCSR_mip_rupd(x0,mip_MSIP_rupd(x1,true)))) + end + else () + end; + +fun rnd_mode_static rnd = + case rnd of + BitsN.B(0x0,_) => Option.SOME RNE + | BitsN.B(0x1,_) => Option.SOME RTZ + | BitsN.B(0x2,_) => Option.SOME RDN + | BitsN.B(0x3,_) => Option.SOME RUP + | BitsN.B(0x4,_) => Option.SOME RMM + | BitsN.B(0x7,_) => Option.SOME RDYN + | _ => NONE; + +fun rnd_mode_dynamic rnd = + case rnd of + BitsN.B(0x0,_) => Option.SOME RNE + | BitsN.B(0x1,_) => Option.SOME RTZ + | BitsN.B(0x2,_) => Option.SOME RDN + | BitsN.B(0x3,_) => Option.SOME RUP + | BitsN.B(0x4,_) => Option.SOME RMM + | _ => NONE; + +fun l3round rnd = + case rnd of + RNE => Option.SOME IEEEReal.TO_NEAREST + | RTZ => Option.SOME IEEEReal.TO_ZERO + | RDN => Option.SOME IEEEReal.TO_NEGINF + | RUP => Option.SOME IEEEReal.TO_POSINF + | RMM => NONE + | RDYN => NONE; + +fun round rnd = + case rnd_mode_static rnd of + Option.SOME RDYN => + (case rnd_mode_dynamic(#FRM((fcsr ()) : FPCSR)) of + Option.SOME frm => l3round frm + | NONE => NONE) + | Option.SOME frm => l3round frm + | NONE => NONE; + +val RV32_CanonicalNan = BitsN.B(0x7FC00000,32) + +val RV64_CanonicalNan = BitsN.B(0x7FF8000000000000,64) + +fun FP32_IsSignalingNan x = + ((BitsN.bits(30,23) x) = (BitsN.B(0xFF,8))) andalso + (((BitsN.bit(x,22)) = false) andalso + (not((BitsN.bits(21,0) x) = (BitsN.B(0x0,22))))); + +fun FP64_IsSignalingNan x = + ((BitsN.bits(62,52) x) = (BitsN.B(0x7FF,11))) andalso + (((BitsN.bit(x,51)) = false) andalso + (not((BitsN.bits(50,0) x) = (BitsN.B(0x0,51))))); + +fun FP32_Sign x = BitsN.bit(x,31); + +fun FP64_Sign x = BitsN.bit(x,63); + +fun setFP_Invalid () = + let val x = fcsr () in write'fcsr(FPCSR_NV_rupd(x,true)) end; + +fun setFP_DivZero () = + let val x = fcsr () in write'fcsr(FPCSR_DZ_rupd(x,true)) end; + +fun setFP_Overflow () = + let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; + +fun setFP_Underflow () = + let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; + +fun setFP_Inexact () = + let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; + +fun csrRW csr = BitsN.bits(11,10) csr; + +fun csrPR csr = BitsN.bits(9,8) csr; + +fun check_CSR_access (rw,(pr,(p,a))) = + ((a = Read) orelse (not(rw = (BitsN.B(0x3,2))))) andalso + (BitsN.>=+(privLevel p,pr)); + +fun is_CSR_defined csr = + ((BitsN.>=(csr,BitsN.B(0x1,12))) andalso (BitsN.<=(csr,BitsN.B(0x3,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0xC00,12))) andalso + (BitsN.<=(csr,BitsN.B(0xC02,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0xC80,12))) andalso + ((BitsN.<=(csr,BitsN.B(0xC82,12))) andalso (in32BitMode ()))) orelse + (((BitsN.>=(csr,BitsN.B(0x100,12))) andalso + (BitsN.<=(csr,BitsN.B(0x101,12)))) orelse + ((csr = (BitsN.B(0x104,12))) orelse + ((csr = (BitsN.B(0x121,12))) orelse + ((csr = (BitsN.B(0xD01,12))) orelse + (((csr = (BitsN.B(0xD81,12))) andalso (in32BitMode ())) orelse + (((BitsN.>=(csr,BitsN.B(0x140,12))) andalso + (BitsN.<=(csr,BitsN.B(0x141,12)))) orelse + ((csr = (BitsN.B(0x144,12))) orelse + (((BitsN.>=(csr,BitsN.B(0xD42,12))) andalso + (BitsN.<=(csr,BitsN.B(0xD43,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0x180,12))) andalso + (BitsN.<=(csr,BitsN.B(0x181,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0x900,12))) andalso + (BitsN.<=(csr,BitsN.B(0x902,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0x980,12))) andalso + ((BitsN.<=(csr,BitsN.B(0x982,12))) andalso + (in32BitMode ()))) orelse + (((BitsN.>=(csr,BitsN.B(0xF00,12))) andalso + (BitsN.<=(csr,BitsN.B(0xF01,12)))) orelse + ((csr = (BitsN.B(0xF10,12))) orelse + (((BitsN.>=(csr,BitsN.B(0x300,12))) andalso + (BitsN.<=(csr,BitsN.B(0x302,12)))) orelse + ((csr = (BitsN.B(0x304,12))) orelse + ((csr = (BitsN.B(0x321,12))) orelse + ((csr = (BitsN.B(0x701,12))) orelse + (((csr = (BitsN.B(0x741,12))) andalso + (in32BitMode ())) orelse + (((BitsN.>=(csr,BitsN.B(0x340,12))) andalso + (BitsN.<=(csr,BitsN.B(0x344,12)))) orelse + (((BitsN.>=(csr,BitsN.B(0x380,12))) andalso + (BitsN.<=(csr,BitsN.B(0x385,12)))) orelse + ((BitsN.>=(csr,BitsN.B(0xB01,12))) orelse + (((csr = (BitsN.B(0xB81,12))) andalso + (in32BitMode ())) orelse + ((BitsN.>=(csr,BitsN.B(0x780,12))) andalso + ((BitsN.<=(csr,BitsN.B(0x783,12))) andalso + (not(csr = (BitsN.B(0x782,12)))))))))))))))))))))))))))))); + +fun CSRMap csr = + case csr of + BitsN.B(0x1,_) => + BitsN.zeroExtend 64 + (BitsN.bits(4,0) + (reg'FPCSR + (#fpcsr + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0x2,_) => + BitsN.zeroExtend 64 + (#FRM + ((#fpcsr + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) : + FPCSR)) + | BitsN.B(0x3,_) => + BitsN.zeroExtend 64 + (BitsN.bits(7,0) + (reg'FPCSR + (#fpcsr + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0xC00,_) => + BitsN.+ + (Map.lookup((!c_cycles),BitsN.toNat (!procID)), + #cycle_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0xC01,_) => + BitsN.+ + ((!clock), + #time_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0xC02,_) => + BitsN.+ + (Map.lookup((!c_instret),BitsN.toNat (!procID)), + #instret_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0xC80,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + (Map.lookup((!c_cycles),BitsN.toNat (!procID)), + #cycle_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0xC81,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #time_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0xC82,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + (Map.lookup((!c_instret),BitsN.toNat (!procID)), + #instret_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0x100,_) => + reg'sstatus + (lift_mstatus_sstatus + (#mstatus + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) + | BitsN.B(0x101,_) => + #stvec((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0x104,_) => + reg'sie + (lift_mie_sie + (#mie + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) + | BitsN.B(0x121,_) => + #stimecmp + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0xD01,_) => + BitsN.+ + ((!clock), + #stime_delta + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) + | BitsN.B(0xD81,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #stime_delta + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : + SupervisorCSR)))) + | BitsN.B(0x140,_) => + #sscratch + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0x141,_) => + #sepc((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0xD42,_) => + reg'mcause + (#scause + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) + | BitsN.B(0xD43,_) => + #sbadaddr + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0x144,_) => + reg'sip + (lift_mip_sip + (#mip + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) + | BitsN.B(0x180,_) => + #sptbr((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0x181,_) => + #sasid((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) + | BitsN.B(0x900,_) => + BitsN.+ + (Map.lookup((!c_cycles),BitsN.toNat (!procID)), + #cycle_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0x901,_) => + BitsN.+ + ((!clock), + #time_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0x902,_) => + BitsN.+ + (Map.lookup((!c_instret),BitsN.toNat (!procID)), + #instret_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) + | BitsN.B(0x980,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + (Map.lookup((!c_cycles),BitsN.toNat (!procID)), + #cycle_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0x981,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #time_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0x982,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + (Map.lookup((!c_instret),BitsN.toNat (!procID)), + #instret_delta + ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) + | BitsN.B(0x200,_) => + reg'mstatus + (#hstatus + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) + | BitsN.B(0x201,_) => + #htvec((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) + | BitsN.B(0x202,_) => + reg'mtdeleg + (#htdeleg + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) + | BitsN.B(0x221,_) => + #htimecmp + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) + | BitsN.B(0xE01,_) => + BitsN.+ + ((!clock), + #htime_delta + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) + | BitsN.B(0xE81,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #htime_delta + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : + HypervisorCSR)))) + | BitsN.B(0x240,_) => + #hscratch + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) + | BitsN.B(0x241,_) => + #hepc((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) + | BitsN.B(0x242,_) => + reg'mcause + (#hcause + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) + | BitsN.B(0x243,_) => + #hbadaddr + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) + | BitsN.B(0xA01,_) => + BitsN.+ + ((!clock), + #stime_delta + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) + | BitsN.B(0xA81,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #stime_delta + ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : + SupervisorCSR)))) + | BitsN.B(0xF00,_) => + reg'mcpuid + (#mcpuid + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0xF01,_) => + reg'mimpid + (#mimpid + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0xF10,_) => + #mhartid((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x300,_) => + reg'mstatus + (#mstatus + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x301,_) => + #mtvec((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x302,_) => + reg'mtdeleg + (#mtdeleg + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x304,_) => + reg'mie + (#mie((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x321,_) => + #mtimecmp((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x701,_) => + BitsN.+ + ((!clock), + #mtime_delta + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x741,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #mtime_delta + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : + MachineCSR)))) + | BitsN.B(0x340,_) => + #mscratch((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x341,_) => + #mepc((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x342,_) => + reg'mcause + (#mcause + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x343,_) => + #mbadaddr((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x344,_) => + reg'mip + (#mip((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) + | BitsN.B(0x380,_) => + #mbase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x381,_) => + #mbound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x382,_) => + #mibase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x383,_) => + #mibound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x384,_) => + #mdbase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x385,_) => + #mdbound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0xB01,_) => + BitsN.+ + ((!clock), + #htime_delta + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) + | BitsN.B(0xB81,_) => + BitsN.signExtend 64 + (BitsN.bits(63,32) + (BitsN.+ + ((!clock), + #htime_delta + ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : + HypervisorCSR)))) + | BitsN.B(0x780,_) => + #mtohost((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x781,_) => + #mfromhost + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) + | BitsN.B(0x783,_) => BitsN.B(0x0,64) + | _ => + raise UNDEFINED ("unexpected CSR read at " ^ (BitsN.toHexString csr)); + +fun write'CSRMap (value,csr) = + case csr of + BitsN.B(0x1,_) => + ( let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val x1 = #fpcsr(x0 : UserCSR) + val w = reg'FPCSR x1 + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_fpcsr_rupd + (x0, + write'reg'FPCSR + (x1, + BitsN.bitFieldInsert(4,0) (w,BitsN.bits(4,0) value))))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) + end + ) + | BitsN.B(0x2,_) => + ( let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val x1 = #fpcsr(x0 : UserCSR) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_fpcsr_rupd + (x0,FPCSR_FRM_rupd(x1,BitsN.bits(2,0) value)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) + end + ) + | BitsN.B(0x3,_) => + ( let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val x1 = #fpcsr(x0 : UserCSR) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_fpcsr_rupd + (x0,write'reg'FPCSR(x1,BitsN.bits(31,0) value)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mstatus(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) + end + ) + | BitsN.B(0x100,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0, + lower_sstatus_mstatus + (rec'sstatus value, + #mstatus + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : + MachineCSR))))) + end + | BitsN.B(0x101,_) => + let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_stvec_rupd(x0,value))) + end + | BitsN.B(0x104,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mie_rupd + (x0, + lower_sie_mie + (rec'sie value, + #mie + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : + MachineCSR))))) + end + | BitsN.B(0x121,_) => + ( let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_stimecmp_rupd(x0,value))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mip(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mip_rupd(x0,mip_STIP_rupd(x1,false)))) + end + ) + | BitsN.B(0x140,_) => + let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_sscratch_rupd(x0,value))) + end + | BitsN.B(0x141,_) => + let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_sepc_rupd + (x0,BitsN.&&(value,BitsN.signExtend 64 (BitsN.B(0x4,3)))))) + end + | BitsN.B(0x144,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mip_rupd + (x0, + lower_sip_mip + (rec'sip value, + #mip + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : + MachineCSR))))) + end + | BitsN.B(0x180,_) => + let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_sptbr_rupd(x0,value))) + end + | BitsN.B(0x181,_) => + let + val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) + in + c_SCSR := + (Map.update + ((!c_SCSR),BitsN.toNat (!procID), + SupervisorCSR_sasid_rupd(x0,value))) + end + | BitsN.B(0x900,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_cycle_delta_rupd + (x0, + BitsN.-(value,Map.lookup((!c_cycles),BitsN.toNat (!procID)))))) + end + | BitsN.B(0x901,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_time_delta_rupd(x0,BitsN.-(value,(!clock))))) + end + | BitsN.B(0x902,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_instret_delta_rupd + (x0, + BitsN.- + (value,Map.lookup((!c_instret),BitsN.toNat (!procID)))))) + end + | BitsN.B(0x980,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val w = #cycle_delta(x0 : UserCSR) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_cycle_delta_rupd + (x0, + BitsN.bitFieldInsert(63,32) + (w, + BitsN.<< + (BitsN.- + (BitsN.bits(31,0) value, + BitsN.bits(63,32) + (Map.lookup((!c_cycles),BitsN.toNat (!procID)))), + 32))))) + end + | BitsN.B(0x981,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val w = #time_delta(x0 : UserCSR) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_time_delta_rupd + (x0, + BitsN.bitFieldInsert(63,32) + (w, + BitsN.<< + (BitsN.- + (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), + 32))))) + end + | BitsN.B(0x982,_) => + let + val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) + val w = #instret_delta(x0 : UserCSR) + in + c_UCSR := + (Map.update + ((!c_UCSR),BitsN.toNat (!procID), + UserCSR_instret_delta_rupd + (x0, + BitsN.bitFieldInsert(63,32) + (w, + BitsN.<< + (BitsN.- + (BitsN.bits(31,0) value, + BitsN.bits(63,32) + (Map.lookup((!c_instret),BitsN.toNat (!procID)))), + 32))))) + end + | BitsN.B(0x300,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mstatus_rupd + (x0, + update_mstatus + (#mstatus + ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : + MachineCSR),rec'mstatus value)))) + end + | BitsN.B(0x301,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID),MachineCSR_mtvec_rupd(x0,value))) + end + | BitsN.B(0x302,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mtdeleg_rupd(x0,rec'mtdeleg value))) + end + | BitsN.B(0x304,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mie_rupd(x0,rec'mie value))) + end + | BitsN.B(0x321,_) => + ( let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mtimecmp_rupd(x0,value))) + end + ; let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val x1 = #mip(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mip_rupd(x0,mip_MTIP_rupd(x1,false)))) + end + ) + | BitsN.B(0x701,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mtime_delta_rupd(x0,BitsN.-(value,(!clock))))) + end + | BitsN.B(0x741,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + val w = #mtime_delta(x0 : MachineCSR) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mtime_delta_rupd + (x0, + BitsN.bitFieldInsert(63,32) + (w, + BitsN.<< + (BitsN.- + (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), + 32))))) + end + | BitsN.B(0x340,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mscratch_rupd(x0,value))) + end + | BitsN.B(0x341,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mepc_rupd + (x0,BitsN.&&(value,BitsN.signExtend 64 (BitsN.B(0x4,3)))))) + end + | BitsN.B(0x342,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mcause_rupd(x0,rec'mcause value))) + end + | BitsN.B(0x343,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mbadaddr_rupd(x0,value))) + end + | BitsN.B(0x344,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mip_rupd(x0,rec'mip value))) + end + | BitsN.B(0x380,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID),MachineCSR_mbase_rupd(x0,value))) + end + | BitsN.B(0x381,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mbound_rupd(x0,value))) + end + | BitsN.B(0x382,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mibase_rupd(x0,value))) + end + | BitsN.B(0x383,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mibound_rupd(x0,value))) + end + | BitsN.B(0x384,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mdbase_rupd(x0,value))) + end + | BitsN.B(0x385,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mdbound_rupd(x0,value))) + end + | BitsN.B(0xB01,_) => + let + val x0 = Map.lookup((!c_HCSR),BitsN.toNat (!procID)) + in + c_HCSR := + (Map.update + ((!c_HCSR),BitsN.toNat (!procID), + HypervisorCSR_htime_delta_rupd(x0,BitsN.-(value,(!clock))))) + end + | BitsN.B(0xB81,_) => + let + val x0 = Map.lookup((!c_HCSR),BitsN.toNat (!procID)) + val w = #htime_delta(x0 : HypervisorCSR) + in + c_HCSR := + (Map.update + ((!c_HCSR),BitsN.toNat (!procID), + HypervisorCSR_htime_delta_rupd + (x0, + BitsN.bitFieldInsert(63,32) + (w, + BitsN.<< + (BitsN.- + (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), + 32))))) + end + | BitsN.B(0x780,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mtohost_rupd(x0,value))) + end + | BitsN.B(0x781,_) => + let + val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) + in + c_MCSR := + (Map.update + ((!c_MCSR),BitsN.toNat (!procID), + MachineCSR_mfromhost_rupd(x0,value))) + end + | BitsN.B(0x783,_) => sendIPI value + | _ => + raise INTERNAL_ERROR + ("unexpected CSR write to " ^ (BitsN.toHexString csr)); + +fun csrName csr = + case csr of + BitsN.B(0x1,_) => "fflags" + | BitsN.B(0x2,_) => "frm" + | BitsN.B(0x3,_) => "fcsr" + | BitsN.B(0xC00,_) => "cycle" + | BitsN.B(0xC01,_) => "time" + | BitsN.B(0xC02,_) => "instret" + | BitsN.B(0xC80,_) => "cycleh" + | BitsN.B(0xC81,_) => "timeh" + | BitsN.B(0xC82,_) => "instreth" + | BitsN.B(0x100,_) => "sstatus" + | BitsN.B(0x101,_) => "stvec" + | BitsN.B(0x104,_) => "sie" + | BitsN.B(0x121,_) => "stimecmp" + | BitsN.B(0xD01,_) => "stime" + | BitsN.B(0xD81,_) => "stimeh" + | BitsN.B(0x140,_) => "sscratch" + | BitsN.B(0x141,_) => "sepc" + | BitsN.B(0xD42,_) => "scause" + | BitsN.B(0xD43,_) => "sbadaddr" + | BitsN.B(0x144,_) => "mip" + | BitsN.B(0x180,_) => "sptbr" + | BitsN.B(0x181,_) => "sasid" + | BitsN.B(0x900,_) => "cycle" + | BitsN.B(0x901,_) => "time" + | BitsN.B(0x902,_) => "instret" + | BitsN.B(0x980,_) => "cycleh" + | BitsN.B(0x981,_) => "timeh" + | BitsN.B(0x982,_) => "instreth" + | BitsN.B(0x200,_) => "hstatus" + | BitsN.B(0x201,_) => "htvec" + | BitsN.B(0x202,_) => "htdeleg" + | BitsN.B(0x221,_) => "htimecmp" + | BitsN.B(0xE01,_) => "htime" + | BitsN.B(0xE81,_) => "htimeh" + | BitsN.B(0x240,_) => "hscratch" + | BitsN.B(0x241,_) => "hepc" + | BitsN.B(0x242,_) => "hcause" + | BitsN.B(0x243,_) => "hbadaddr" + | BitsN.B(0xA01,_) => "stime" + | BitsN.B(0xA81,_) => "stimeh" + | BitsN.B(0xF00,_) => "mcpuid" + | BitsN.B(0xF01,_) => "mimpid" + | BitsN.B(0xF10,_) => "mhartid" + | BitsN.B(0x300,_) => "mstatus" + | BitsN.B(0x301,_) => "mtvec" + | BitsN.B(0x302,_) => "mtdeleg" + | BitsN.B(0x304,_) => "mie" + | BitsN.B(0x321,_) => "mtimecmp" + | BitsN.B(0x701,_) => "mtime" + | BitsN.B(0x741,_) => "mtimeh" + | BitsN.B(0x340,_) => "mscratch" + | BitsN.B(0x341,_) => "mepc" + | BitsN.B(0x342,_) => "mcause" + | BitsN.B(0x343,_) => "mbadaddr" + | BitsN.B(0x344,_) => "mip" + | BitsN.B(0x380,_) => "mbase" + | BitsN.B(0x381,_) => "mbound" + | BitsN.B(0x382,_) => "mibase" + | BitsN.B(0x383,_) => "mibound" + | BitsN.B(0x384,_) => "mdbase" + | BitsN.B(0x385,_) => "mdbound" + | BitsN.B(0xB01,_) => "htime" + | BitsN.B(0xB81,_) => "htimeh" + | BitsN.B(0x780,_) => "mtohost" + | BitsN.B(0x781,_) => "mfromhost" + | BitsN.B(0x783,_) => "send_ipi" + | _ => "UNKNOWN"; + +fun Delta () = Map.lookup((!c_update),BitsN.toNat (!procID)); + +fun write'Delta value = + c_update := (Map.update((!c_update),BitsN.toNat (!procID),value)); + +fun hex32 x = L3.padLeftString(#"0",(8,BitsN.toHexString x)); + +fun hex64 x = L3.padLeftString(#"0",(16,BitsN.toHexString x)); + +fun log_w_csr (csr,data) = + String.concat["CSR (",csrName csr,") <- 0x",hex64 data]; + +fun reg r = + if r = (BitsN.B(0x0,5)) + then "$0" + else if r = (BitsN.B(0x1,5)) + then "ra" + else if r = (BitsN.B(0x2,5)) + then "sp" + else if r = (BitsN.B(0x3,5)) + then "gp" + else if r = (BitsN.B(0x4,5)) + then "tp" + else if r = (BitsN.B(0x5,5)) + then "t0" + else if r = (BitsN.B(0x6,5)) + then "t1" + else if r = (BitsN.B(0x7,5)) + then "t2" + else if r = (BitsN.B(0x8,5)) + then "fp" + else if r = (BitsN.B(0x9,5)) + then "s1" + else if r = (BitsN.B(0xA,5)) + then "a0" + else if r = (BitsN.B(0xB,5)) + then "a1" + else if r = (BitsN.B(0xC,5)) + then "a2" + else if r = (BitsN.B(0xD,5)) + then "a3" + else if r = (BitsN.B(0xE,5)) + then "a4" + else if r = (BitsN.B(0xF,5)) + then "a5" + else if r = (BitsN.B(0x10,5)) + then "a6" + else if r = (BitsN.B(0x11,5)) + then "a7" + else if r = (BitsN.B(0x12,5)) + then "s2" + else if r = (BitsN.B(0x13,5)) + then "s3" + else if r = (BitsN.B(0x14,5)) + then "s4" + else if r = (BitsN.B(0x15,5)) + then "s5" + else if r = (BitsN.B(0x16,5)) + then "s6" + else if r = (BitsN.B(0x17,5)) + then "s7" + else if r = (BitsN.B(0x18,5)) + then "s8" + else if r = (BitsN.B(0x19,5)) + then "s9" + else if r = (BitsN.B(0x1A,5)) + then "s10" + else if r = (BitsN.B(0x1B,5)) + then "s11" + else if r = (BitsN.B(0x1C,5)) + then "t3" + else if r = (BitsN.B(0x1D,5)) + then "t4" + else if r = (BitsN.B(0x1E,5)) then "t5" else "t6"; + +fun fpreg r = + if r = (BitsN.B(0x0,5)) + then "fs0" + else if r = (BitsN.B(0x1,5)) + then "fs1" + else if r = (BitsN.B(0x2,5)) + then "fs2" + else if r = (BitsN.B(0x3,5)) + then "fs3" + else if r = (BitsN.B(0x4,5)) + then "fs4" + else if r = (BitsN.B(0x5,5)) + then "fs5" + else if r = (BitsN.B(0x6,5)) + then "fs6" + else if r = (BitsN.B(0x7,5)) + then "fs7" + else if r = (BitsN.B(0x8,5)) + then "fs8" + else if r = (BitsN.B(0x9,5)) + then "fs9" + else if r = (BitsN.B(0xA,5)) + then "fs10" + else if r = (BitsN.B(0xB,5)) + then "fs11" + else if r = (BitsN.B(0xC,5)) + then "fs12" + else if r = (BitsN.B(0xD,5)) + then "fs13" + else if r = (BitsN.B(0xE,5)) + then "fs14" + else if r = (BitsN.B(0xF,5)) + then "fs15" + else if r = (BitsN.B(0x10,5)) + then "fv0" + else if r = (BitsN.B(0x11,5)) + then "fv1" + else if r = (BitsN.B(0x12,5)) + then "fa0" + else if r = (BitsN.B(0x13,5)) + then "fa1" + else if r = (BitsN.B(0x14,5)) + then "fa2" + else if r = (BitsN.B(0x15,5)) + then "fa3" + else if r = (BitsN.B(0x16,5)) + then "fa4" + else if r = (BitsN.B(0x17,5)) + then "fa5" + else if r = (BitsN.B(0x18,5)) + then "fa6" + else if r = (BitsN.B(0x19,5)) + then "fa7" + else if r = (BitsN.B(0x1A,5)) + then "ft0" + else if r = (BitsN.B(0x1B,5)) + then "ft1" + else if r = (BitsN.B(0x1C,5)) + then "ft2" + else if r = (BitsN.B(0x1D,5)) + then "ft3" + else if r = (BitsN.B(0x1E,5)) then "ft4" else "ft5"; + +fun log_w_gpr (r,data) = + String.concat + ["Reg ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex64 data]; + +fun log_w_fprs (r,data) = + String.concat + ["FPR ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex32 data]; + +fun log_w_fprd (r,data) = + String.concat + ["FPR ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex64 data]; + +fun log_w_mem_mask (pAddrIdx,(vAddr,(mask,(data,(old,new))))) = + String.concat + ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", + hex64 vAddr,"] <- (data: 0x",hex64 data,", mask: 0x",hex64 mask, + ", old: 0x",hex64 old,", new: 0x",hex64 new,")"]; + +fun log_w_mem_mask_misaligned + (pAddrIdx,(vAddr,(mask,(data,(align,(old,new)))))) = + String.concat + ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", + hex64 vAddr,"/ misaligned@",Nat.toString align,"] <- (data: 0x", + hex64 data,", mask: 0x",hex64 mask,", old: 0x",hex64 old,", new: 0x", + hex64 new,")"]; + +fun log_w_mem (pAddrIdx,(vAddr,data)) = + String.concat + ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", + hex64 vAddr,"] <- (data: 0x",hex64 data,")"]; + +fun log_r_mem (pAddrIdx,(vAddr,data)) = + String.concat + ["data <- MEM[0x", + L3.padLeftString(#"0",(10,BitsN.toHexString pAddrIdx)),"/", + hex64 vAddr,"]: 0x",hex64 data]; + +fun log_exc e = String.concat[" Exception ",excName e," raised!"]; + +fun log_tohost tohost = + "-> host: " + ^ + (String.str((L3.chr o BitsN.toNat) (BitsN.bits(7,0) tohost))); + +fun clear_logs () = log := []; + +fun setTrap (e,badaddr) = + let + val trap = ref {badaddr = NONE, trap = AMO_Misaligned} + in + ( trap := (SynchronousTrap_trap_rupd((!trap),e)) + ; trap := (SynchronousTrap_badaddr_rupd((!trap),badaddr)) + ; write'NextFetch(Option.SOME(Trap (!trap))) + ) + end; + +fun signalException e = + ( log := ((1,"signalling exception " ^ (excName e)) :: (!log)) + ; setTrap(e,NONE) + ; let + val x = Delta () + in + write'Delta(StateDelta_exc_taken_rupd(x,true)) + end + ); + +fun signalAddressException (e,vAddr) = + ( log := + ((1, + String.concat + ["signalling address exception ",excName e," at ", + BitsN.toHexString vAddr]) + :: + (!log)) + ; setTrap(e,Option.SOME vAddr) + ; let + val x = Delta () + in + write'Delta(StateDelta_exc_taken_rupd(x,true)) + end + ); + +fun signalEnvCall () = + let + val e = + case privilege(#MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) of + User => UMode_Env_Call + | Supervisor => SMode_Env_Call + | Hypervisor => HMode_Env_Call + | Machine => MMode_Env_Call + in + signalException e + end; + +fun checkDelegation (curPriv,(intr,ec)) = + let + val e = BitsN.toNat ec + in + case curPriv of + User => raise INTERNAL_ERROR "No user-level delegation!" + | Supervisor => + raise INTERNAL_ERROR "No supervisor-level delegation!" + | Hypervisor => + if (intr andalso + (BitsN.bit + (#Intr_deleg + ((#htdeleg((HCSR ()) : HypervisorCSR)) : mtdeleg),e))) orelse + ((not intr) andalso + (BitsN.bit + (#Exc_deleg((#htdeleg((HCSR ()) : HypervisorCSR)) : mtdeleg), + e))) + then Supervisor + else curPriv + | Machine => + if (intr andalso + (BitsN.bit + (#Intr_deleg((#mtdeleg((MCSR ()) : MachineCSR)) : mtdeleg),e))) orelse + ((not intr) andalso + (BitsN.bit + (#Exc_deleg((#mtdeleg((MCSR ()) : MachineCSR)) : mtdeleg),e))) + then checkDelegation(Hypervisor,(intr,ec)) + else curPriv + end; + +fun checkPrivInterrupt curPriv = + let + val ip = #mip((MCSR ()) : MachineCSR) + val ie = #mie((MCSR ()) : MachineCSR) + in + case curPriv of + User => raise INTERNAL_ERROR "No user-level interrupts!" + | Supervisor => + if (#STIP(ip : mip)) andalso (#STIE(ie : mie)) + then Option.SOME(Timer,curPriv) + else if (#SSIP(ip : mip)) andalso (#SSIE(ie : mie)) + then Option.SOME(Software,curPriv) + else NONE + | Hypervisor => + if (#HTIP(ip : mip)) andalso (#HTIE(ie : mie)) + then Option.SOME(Timer,curPriv) + else if (#HSIP(ip : mip)) andalso (#HSIE(ie : mie)) + then Option.SOME(Software,curPriv) + else NONE + | Machine => + if (#MTIP(ip : mip)) andalso (#MTIE(ie : mie)) + then Option.SOME(Timer,curPriv) + else if (#MSIP(ip : mip)) andalso (#MSIE(ie : mie)) + then Option.SOME(Software,curPriv) + else NONE + end; + +fun checkInterrupts () = + let + val curIE = #MIE((#mstatus((MCSR ()) : MachineCSR)) : mstatus) + val p = curPrivilege () + in + case p of + User => + (case checkPrivInterrupt Machine of + NONE => + (case checkPrivInterrupt Hypervisor of + NONE => + if (p = User) orelse curIE + then checkPrivInterrupt Supervisor + else NONE + | i => i) + | i => i) + | Supervisor => + (case checkPrivInterrupt Machine of + NONE => + (case checkPrivInterrupt Hypervisor of + NONE => + if (p = User) orelse curIE + then checkPrivInterrupt Supervisor + else NONE + | i => i) + | i => i) + | Hypervisor => + (case checkPrivInterrupt Machine of + NONE => if curIE then checkPrivInterrupt Hypervisor else NONE + | i => i) + | Machine => if curIE then checkPrivInterrupt Machine else NONE + end; + +fun takeTrap (intr,(ec,(epc,(badaddr,toPriv)))) = + let + val fromP = curPrivilege () + in + ( log := + ((1, + String.concat + ["trapping from ",privName fromP," to ",privName toPriv, + " at pc ",BitsN.toHexString epc, + if intr then " [intr] " else " [exc] ", + Nat.toString(BitsN.toNat ec)]) + :: + (!log)) + ; write'ReserveLoad NONE + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd(x,mstatus_MMPRV_rupd(x0,false))) + end + ; let + val x = MCSR () + in + write'MCSR + (MachineCSR_mstatus_rupd + (x, + pushPrivilegeStack(#mstatus((MCSR ()) : MachineCSR),toPriv))) + end + ; case toPriv of + User => raise INTERNAL_ERROR "Illegal trap to U-mode" + | Supervisor => + ( let + val x = SCSR () + val x0 = #scause(x : SupervisorCSR) + in + write'SCSR + (SupervisorCSR_scause_rupd(x,mcause_Int_rupd(x0,intr))) + end + ; let + val x = SCSR () + val x0 = #scause(x : SupervisorCSR) + in + write'SCSR + (SupervisorCSR_scause_rupd(x,mcause_EC_rupd(x0,ec))) + end + ; let + val x = SCSR () + in + write'SCSR(SupervisorCSR_sepc_rupd(x,epc)) + end + ; if Option.isSome badaddr + then let + val x = SCSR () + in + write'SCSR + (SupervisorCSR_sbadaddr_rupd(x,Option.valOf badaddr)) + end + else () + ; write'PC(#stvec((SCSR ()) : SupervisorCSR)) + ) + | Hypervisor => raise INTERNAL_ERROR "Unsupported trap to H-mode" + | Machine => + ( let + val x = MCSR () + val x0 = #mcause(x : MachineCSR) + in + write'MCSR + (MachineCSR_mcause_rupd(x,mcause_Int_rupd(x0,intr))) + end + ; let + val x = MCSR () + val x0 = #mcause(x : MachineCSR) + in + write'MCSR(MachineCSR_mcause_rupd(x,mcause_EC_rupd(x0,ec))) + end + ; let + val x = MCSR () + in + write'MCSR(MachineCSR_mepc_rupd(x,epc)) + end + ; if Option.isSome badaddr + then let + val x = MCSR () + in + write'MCSR + (MachineCSR_mbadaddr_rupd(x,Option.valOf badaddr)) + end + else () + ; write'PC + (BitsN.+ + (#mtvec((MCSR ()) : MachineCSR), + BitsN.* + (BitsN.fromNat(BitsN.toNat(privLevel fromP),64), + BitsN.B(0x40,64)))) + ) + ) + end; + +fun CSR n = CSRMap n; + +fun write'CSR (value,n) = + ( write'CSRMap(value,n); log := ((2,log_w_csr(n,value)) :: (!log)) ); + +fun writeCSR (csr,val') = + ( write'CSR(val',csr) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME(BitsN.zeroExtend 64 csr))) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME(CSR csr))) + end + ); + +fun GPR n = if n = (BitsN.B(0x0,5)) then BitsN.B(0x0,64) else gpr n; + +fun write'GPR (value,n) = + if not(n = (BitsN.B(0x0,5))) + then ( write'gpr(value,n); log := ((2,log_w_gpr(n,value)) :: (!log)) ) + else (); + +fun FPRS n = BitsN.bits(31,0) (fpr n); + +fun write'FPRS (value,n) = + ( let + val w = fpr n + in + write'fpr(BitsN.bitFieldInsert(31,0) (w,value),n) + end + ; log := ((2,log_w_fprs(n,value)) :: (!log)) + ); + +fun FPRD n = fpr n; + +fun write'FPRD (value,n) = + ( write'fpr(value,n); log := ((2,log_w_fprd(n,value)) :: (!log)) ); + +fun writeFPRS (rd,val') = + ( write'FPRS(val',rd) + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd(x,mstatus_MFS_rupd(x0,ext_status Dirty))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,true))) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.zeroExtend 64 val'))) + end + ); + +fun writeFPRD (rd,val') = + ( write'FPRD(val',rd) + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd(x,mstatus_MFS_rupd(x0,ext_status Dirty))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,true))) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ); + +fun MEM a = + let + val b = BitsN.<<(BitsN.fromNat(BitsN.toNat a,64),3) + in + BitsN.concat + [Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x7,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x6,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x5,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x4,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x3,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x2,64)))), + Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x1,64)))), + Map.lookup((!MEM8),BitsN.toNat b)] + end; + +fun write'MEM (val',a) = + let + val b = BitsN.<<(BitsN.fromNat(BitsN.toNat a,64),3) + in + ( let + val x = BitsN.+(b,BitsN.B(0x7,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(63,56) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x6,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(55,48) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x5,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(47,40) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x4,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(39,32) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x3,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(31,24) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x2,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(23,16) val')) + end + ; let + val x = BitsN.+(b,BitsN.B(0x1,64)) + in + MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(15,8) val')) + end + ; MEM8 := (Map.update((!MEM8),BitsN.toNat b,BitsN.bits(7,0) val')) + ) + end; + +fun rawReadData pAddr = + let + val pAddrIdx = BitsN.bits(63,3) pAddr + val align = BitsN.toNat(BitsN.bits(2,0) pAddr) + in + if align = 0 + then let + val data = MEM pAddrIdx + in + ( log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) + ; data + ) + end + else let + val dw0 = MEM pAddrIdx + val dw1 = MEM(BitsN.+(pAddrIdx,BitsN.B(0x1,61))) + val ddw = BitsN.>>(BitsN.@@(dw1,dw0),Nat.*(align,8)) + val data = BitsN.bits(63,0) ddw + in + ( log := ((3,log_r_mem(pAddrIdx,(pAddr,dw0))) :: (!log)) + ; log := + ((3,log_r_mem(BitsN.+(pAddrIdx,BitsN.B(0x1,61)),(pAddr,dw1))) + :: + (!log)) + ; log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) + ; data + ) + end + end; + +fun rawWriteData (pAddr,(data,nbytes)) = + let + val mask = + BitsN.- + (BitsN.<<(BitsN.zeroExtend 64 (BitsN.B(0x1,1)),Nat.*(nbytes,8)), + BitsN.B(0x1,64)) + val pAddrIdx = BitsN.bits(63,3) pAddr + val align = BitsN.toNat(BitsN.bits(2,0) pAddr) + val old = MEM pAddrIdx + in + ( log := ((3,log_r_mem(pAddrIdx,(pAddr,old))) :: (!log)) + ; if align = 0 + then let + val new = + BitsN.||(BitsN.&&(old,BitsN.~ mask),BitsN.&&(data,mask)) + in + ( write'MEM(new,pAddrIdx) + ; log := + ((3, + log_w_mem_mask + (pAddrIdx,(pAddr,(mask,(data,(old,new)))))) + :: + (!log)) + ) + end + else if Nat.<=(Nat.+(align,nbytes),Nat.div(BitsN.size mask,8)) + then let + val new = + BitsN.|| + (BitsN.&&(old,BitsN.~(BitsN.<<(mask,Nat.*(align,8)))), + BitsN.<<(BitsN.&&(data,mask),Nat.*(align,8))) + in + ( write'MEM(new,pAddrIdx) + ; log := + ((3, + log_w_mem_mask_misaligned + (pAddrIdx,(pAddr,(mask,(data,(align,(old,new))))))) + :: + (!log)) + ) + end + else let + val dw_old = + BitsN.@@(MEM(BitsN.+(pAddrIdx,BitsN.B(0x1,61))),old) + val dw_data = + BitsN.<<(BitsN.zeroExtend 128 data,Nat.*(align,8)) + val dw_mask = + BitsN.<<(BitsN.zeroExtend 128 mask,Nat.*(align,8)) + val dw_new = + BitsN.|| + (BitsN.&&(dw_old,BitsN.~ dw_mask), + BitsN.&&(dw_data,dw_mask)) + in + ( let + val x = BitsN.+(pAddrIdx,BitsN.B(0x1,61)) + in + write'MEM + (BitsN.resize 64 + (BitsN.bits + (Nat.-(Nat.*(2,BitsN.size data),1), + BitsN.size data) + dw_new),x) + end + ; write'MEM + (BitsN.resize 64 + (BitsN.bits(Nat.-(BitsN.size data,1),0) dw_new), + pAddrIdx) + ) + end + ) + end; + +fun rawReadInst pAddr = + let + val pAddrIdx = BitsN.bits(63,3) pAddr + val data = MEM pAddrIdx + in + ( log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) + ; if BitsN.bit(pAddr,2) + then BitsN.bits(63,32) data + else BitsN.bits(31,0) data + ) + end; + +fun rawWriteMem (pAddr,data) = + let + val pAddrIdx = BitsN.bits(63,3) pAddr + in + ( write'MEM(data,pAddrIdx) + ; log := ((3,log_w_mem(pAddrIdx,(pAddr,data))) :: (!log)) + ) + end; + +fun checkMemPermission (ft,(ac,(priv,perm))) = + case perm of + BitsN.B(0x0,_) => + raise INTERNAL_ERROR "Checking perm on Page-Table pointer!" + | BitsN.B(0x1,_) => + raise INTERNAL_ERROR "Checking perm on Page-Table pointer!" + | BitsN.B(0x2,_) => + if priv = User + then not(ac = Write) + else (ac = Read) andalso (ft = Data) + | BitsN.B(0x3,_) => if priv = User then true else not(ft = Instruction) + | BitsN.B(0x4,_) => (ac = Read) andalso (ft = Data) + | BitsN.B(0x5,_) => not(ft = Instruction) + | BitsN.B(0x6,_) => not(ac = Write) + | BitsN.B(0x7,_) => true + | BitsN.B(0x8,_) => + (not(priv = User)) andalso ((ac = Read) andalso (ft = Data)) + | BitsN.B(0x9,_) => (not(priv = User)) andalso (not(ft = Instruction)) + | BitsN.B(0xA,_) => (not(priv = User)) andalso (not(ac = Write)) + | BitsN.B(0xB,_) => not(priv = User) + | BitsN.B(0xC,_) => + (not(priv = User)) andalso ((ac = Read) andalso (ft = Data)) + | BitsN.B(0xD,_) => (not(priv = User)) andalso (not(ft = Instruction)) + | BitsN.B(0xE,_) => (not(priv = User)) andalso (not(ac = Write)) + | BitsN.B(0xF,_) => not(priv = User) + | _ => raise General.Bind; + +fun isGlobal perm = (BitsN.bits(3,2) perm) = (BitsN.B(0x3,2)); + +fun rec'SV_PTE x = + {PTE_D = BitsN.bit(x,6), PTE_PPNi = BitsN.bits(47,10) x, + PTE_R = BitsN.bit(x,5), PTE_SW = BitsN.bits(9,7) x, + PTE_T = BitsN.bits(4,1) x, PTE_V = BitsN.bit(x,0), + sv_pte'rst = BitsN.bits(63,48) x}; + +fun reg'SV_PTE x = + case x of + {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, + PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst} => + BitsN.concat + [sv_pte'rst,PTE_PPNi,PTE_SW,BitsN.fromBit PTE_D, + BitsN.fromBit PTE_R,PTE_T,BitsN.fromBit PTE_V]; + +fun write'rec'SV_PTE (_,x) = reg'SV_PTE x; + +fun write'reg'SV_PTE (_,x) = rec'SV_PTE x; + +fun rec'SV_Vaddr x = + {Sv_PgOfs = BitsN.bits(11,0) x, Sv_VPNi = BitsN.bits(47,12) x, + sv_vaddr'rst = BitsN.bits(63,48) x}; + +fun reg'SV_Vaddr x = + case x of + {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = Sv_VPNi, sv_vaddr'rst = sv_vaddr'rst} => + BitsN.concat[sv_vaddr'rst,Sv_VPNi,Sv_PgOfs]; + +fun write'rec'SV_Vaddr (_,x) = reg'SV_Vaddr x; + +fun write'reg'SV_Vaddr (_,x) = rec'SV_Vaddr x; + +fun walk64 (vAddr,(ft,(ac,(priv,(ptb,level))))) = + let + val va = rec'SV_Vaddr vAddr + val pt_ofs = + BitsN.<< + (BitsN.zeroExtend 64 + (BitsN.bits(Nat.-(LEVEL_BITS,1),0) + (BitsN.>>+(#Sv_VPNi(va : SV_Vaddr),Nat.*(level,LEVEL_BITS)))), + 3) + val pte_addr = BitsN.+(ptb,pt_ofs) + val pte = rec'SV_PTE(rawReadData pte_addr) + in + ( log := + ((4, + String.concat + ["translate(vaddr=0x", + L3.padLeftString(#"0",(16,BitsN.toHexString vAddr)), + "): level=",Nat.toString level," pt_base=0x", + L3.padLeftString(#"0",(16,BitsN.toHexString ptb))," pt_ofs=", + Nat.toString(BitsN.toNat pt_ofs)," pte_addr=0x", + L3.padLeftString(#"0",(16,BitsN.toHexString pte_addr)), + " pte=0x", + L3.padLeftString(#"0",(16,BitsN.toHexString(reg'SV_PTE pte)))]) + :: + (!log)) + ; if not(#PTE_V(pte : SV_PTE)) + then ( log := ((4,"addr_translate: invalid PTE") :: (!log)) + ; NONE + ) + else if ((#PTE_T(pte : SV_PTE)) = (BitsN.B(0x0,4))) orelse + ((#PTE_T(pte : SV_PTE)) = (BitsN.B(0x1,4))) + then if level = 0 + then ( log := + ((4,"last-level pt contains a pointer PTE!") + :: + (!log)) + ; NONE + ) + else walk64 + (vAddr, + (ft, + (ac, + (priv, + (BitsN.zeroExtend 64 + (BitsN.<< + (#PTE_PPNi(pte : SV_PTE),PAGESIZE_BITS)), + Nat.-(level,1)))))) + else if not(checkMemPermission(ft,(ac,(priv,#PTE_T(pte : SV_PTE))))) + then ( log := ((4,"PTE permission check failure!") :: (!log)) + ; NONE + ) + else let + val pte_w = ref pte + in + let + val old_r = #PTE_R(pte : SV_PTE) + val old_d = #PTE_D(pte : SV_PTE) + in + ( pte_w := (SV_PTE_PTE_R_rupd((!pte_w),true)) + ; if ac = Write + then pte_w := (SV_PTE_PTE_D_rupd((!pte_w),true)) + else () + ; if (not(old_r = (#PTE_R((!pte_w) : SV_PTE)))) orelse + (not(old_d = (#PTE_D((!pte_w) : SV_PTE)))) + then rawWriteData(pte_addr,(reg'SV_PTE (!pte_w),8)) + else () + ; let + val ppn = + if Nat.>(level,0) + then BitsN.|| + (BitsN.zeroExtend 38 + (BitsN.<< + (BitsN.>>+ + (#PTE_PPNi(pte : SV_PTE), + Nat.*(level,LEVEL_BITS)), + Nat.*(level,LEVEL_BITS))), + BitsN.zeroExtend 38 + (BitsN.&& + (#Sv_VPNi(va : SV_Vaddr), + BitsN.- + (BitsN.<< + (BitsN.B(0x1,36), + Nat.*(level,LEVEL_BITS)), + BitsN.B(0x1,36))))) + else #PTE_PPNi(pte : SV_PTE) + in + Option.SOME + (BitsN.zeroExtend 64 + (BitsN.@@(ppn,#Sv_PgOfs(va : SV_Vaddr))), + ((!pte_w), + (level,(isGlobal(#PTE_T(pte : SV_PTE)),pte_addr)))) + end + ) + end + end + ) + end; + +fun curASID () = + BitsN.bits(Nat.-(ASID_SIZE,1),0) (#sasid((SCSR ()) : SupervisorCSR)); + +fun mkTLBEntry (asid,(global,(vAddr,(pAddr,(pte,(i,pteAddr)))))) = + let + val ent = ref {age = BitsN.B(0x0,64), asid = BitsN.B(0x0,6), + global = false, pAddr = BitsN.B(0x0,64), + pte = + {PTE_D = false, PTE_PPNi = BitsN.B(0x0,38), PTE_R = false, + PTE_SW = BitsN.B(0x0,3), PTE_T = BitsN.B(0x0,4), PTE_V = false, + sv_pte'rst = BitsN.B(0x0,16)}, pteAddr = BitsN.B(0x0,64), + vAddr = BitsN.B(0x0,64), vAddrMask = BitsN.B(0x0,64), + vMatchMask = BitsN.B(0x0,64)} + in + ( ent := (TLBEntry_asid_rupd((!ent),asid)) + ; ent := (TLBEntry_global_rupd((!ent),global)) + ; ent := (TLBEntry_pte_rupd((!ent),pte)) + ; ent := (TLBEntry_pteAddr_rupd((!ent),pteAddr)) + ; ent := + (TLBEntry_vAddrMask_rupd + ((!ent), + BitsN.- + (BitsN.<< + (BitsN.B(0x1,64),Nat.+(Nat.*(LEVEL_BITS,i),PAGESIZE_BITS)), + BitsN.B(0x1,64)))) + ; ent := + (TLBEntry_vMatchMask_rupd + ((!ent), + BitsN.?? + (BitsN.signExtend 64 (BitsN.B(0x1,1)), + #vAddrMask((!ent) : TLBEntry)))) + ; ent := + (TLBEntry_vAddr_rupd + ((!ent),BitsN.&&(vAddr,#vMatchMask((!ent) : TLBEntry)))) + ; ent := + (TLBEntry_pAddr_rupd + ((!ent), + BitsN.<< + (BitsN.>>(pAddr,Nat.+(PAGESIZE_BITS,Nat.*(LEVEL_BITS,i))), + Nat.+(PAGESIZE_BITS,Nat.*(LEVEL_BITS,i))))) + ; ent := + (TLBEntry_age_rupd + ((!ent),Map.lookup((!c_cycles),BitsN.toNat (!procID)))) + ; (!ent) + ) + end; + +val TLBEntries = 16 + +fun lookupTLB (asid,(vAddr,tlb)) = + let + val ent = ref NONE + in + ( L3.for + (0,Nat.-(TLBEntries,1), + fn i => + case Map.lookup(tlb,BitsN.toNat(BitsN.fromNat(i,4))) of + Option.SOME e => + (if ((!ent) = NONE) andalso + (((#global(e : TLBEntry)) orelse + ((#asid(e : TLBEntry)) = asid)) andalso + ((#vAddr(e : TLBEntry)) = + (BitsN.&&(vAddr,#vMatchMask(e : TLBEntry))))) + then ent := (Option.SOME(e,BitsN.fromNat(i,4))) + else ()) + | NONE => ()) + ; (!ent) + ) + end; + +fun addToTLB (asid,(vAddr,(pAddr,(pte,(pteAddr,(i,(global,curTLB))))))) = + let + val ent = ref (mkTLBEntry + (asid,(global,(vAddr,(pAddr,(pte,(i,pteAddr))))))) + in + let + val tlb = ref (Map.copy curTLB) + in + let + val oldest = ref (BitsN.signExtend 64 (BitsN.B(0x1,1))) + in + let + val addIdx = ref 0 + in + let + val added = ref false + in + ( L3.for + (0,Nat.-(TLBEntries,1), + fn i => + case Map.lookup((!tlb),BitsN.toNat(BitsN.fromNat(i,4))) of + Option.SOME e => + (if BitsN.<+(#age(e : TLBEntry),(!oldest)) + then ( oldest := (#age(e : TLBEntry)) + ; addIdx := i + ) + else ()) + | NONE => + if not (!added) + then ( let + val x = BitsN.fromNat(i,4) + in + tlb := + (Map.update + ((!tlb),BitsN.toNat x, + Option.SOME (!ent))) + end + ; added := true + ) + else ()) + ; if not (!added) + then let + val x = BitsN.fromNat((!addIdx),4) + in + tlb := + (Map.update + ((!tlb),BitsN.toNat x,Option.SOME (!ent))) + end + else () + ; (!tlb) + ) + end + end + end + end + end; + +fun flushTLB (asid,(addr,curTLB)) = + let + val tlb = ref (Map.copy curTLB) + in + ( L3.for + (0,Nat.-(TLBEntries,1), + fn i => + case (Map.lookup((!tlb),BitsN.toNat(BitsN.fromNat(i,4))),addr) of + (Option.SOME e,Option.SOME va) => + (if ((asid = (BitsN.B(0x0,6))) orelse + ((asid = (#asid(e : TLBEntry))) andalso + (not(#global(e : TLBEntry))))) andalso + ((#vAddr(e : TLBEntry)) = + (BitsN.&&(va,#vMatchMask(e : TLBEntry)))) + then let + val x = BitsN.fromNat(i,4) + in + tlb := (Map.update((!tlb),BitsN.toNat x,NONE)) + end + else ()) + | (Option.SOME e,NONE) => + (if (asid = (BitsN.B(0x0,6))) orelse + ((asid = (#asid(e : TLBEntry))) andalso + (not(#global(e : TLBEntry)))) + then let + val x = BitsN.fromNat(i,4) + in + tlb := (Map.update((!tlb),BitsN.toNat x,NONE)) + end + else ()) + | (NONE,_) => ()) + ; (!tlb) + ) + end; + +fun TLB () = Map.lookup((!c_tlb),BitsN.toNat (!procID)); + +fun write'TLB value = + c_tlb := (Map.update((!c_tlb),BitsN.toNat (!procID),Map.copy value)); + +fun translate64 (vAddr,(ft,(ac,(priv,level)))) = + let + val asid = curASID () + in + case lookupTLB(asid,(vAddr,TLB ())) of + Option.SOME(e,idx) => + (if checkMemPermission + (ft,(ac,(priv,#PTE_T((#pte(e : TLBEntry)) : SV_PTE)))) + then ( log := ((4,"TLB hit!") :: (!log)) + ; if (ac = Write) andalso + (not(#PTE_D((#pte(e : TLBEntry)) : SV_PTE))) + then let + val ent = ref e + in + ( let + val x0 = #pte((!ent) : TLBEntry) + in + ent := + (TLBEntry_pte_rupd + ((!ent),SV_PTE_PTE_D_rupd(x0,true))) + end + ; rawWriteData + (#pteAddr((!ent) : TLBEntry), + (reg'SV_PTE(#pte((!ent) : TLBEntry)),8)) + ; let + val tlb = ref (Map.copy(TLB ())) + in + ( let + val x = idx + in + tlb := + (Map.update + ((!tlb),BitsN.toNat x, + Option.SOME (!ent))) + end + ; write'TLB (!tlb) + ) + end + ) + end + else () + ; Option.SOME + (BitsN.|| + (#pAddr(e : TLBEntry), + BitsN.&&(vAddr,#vAddrMask(e : TLBEntry)))) + ) + else ( log := ((4,"TLB permission check failure") :: (!log)) + ; NONE + )) + | NONE => + ( log := ((4,"TLB miss!") :: (!log)) + ; case walk64 + (vAddr, + (ft,(ac,(priv,(#sptbr((SCSR ()) : SupervisorCSR),level))))) of + Option.SOME(pAddr,(pte,(i,(global,pteAddr)))) => + ( write'TLB + (addToTLB + (asid, + (vAddr,(pAddr,(pte,(pteAddr,(i,(global,TLB ())))))))) + ; Option.SOME pAddr + ) + | NONE => NONE + ) + end; + +fun translateAddr (vAddr,(ft,ac)) = + let + val priv = + privilege + (if (#MMPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) andalso + (ft = Data) + then #MPRV1((#mstatus((MCSR ()) : MachineCSR)) : mstatus) + else #MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) + in + case (vmType(#VM((#mstatus((MCSR ()) : MachineCSR)) : mstatus)),priv) of + (Mbare,_) => Option.SOME vAddr + | (_,Machine) => Option.SOME vAddr + | (Sv39,_) => translate64(vAddr,(ft,(ac,(priv,2)))) + | (Sv48,_) => translate64(vAddr,(ft,(ac,(priv,3)))) + | _ => NONE + end; + +fun matchLoadReservation vAddr = + (Option.isSome(ReserveLoad ())) andalso + ((Option.valOf(ReserveLoad ())) = vAddr); + +fun branchTo newPC = + ( write'NextFetch(Option.SOME(BranchTo newPC)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME newPC)) + end + ); + +fun dfn'ADDI (rd,(rs1,imm)) = + ( write'GPR(BitsN.+(GPR rs1,BitsN.signExtend 64 imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.+(GPR rs1,BitsN.signExtend 64 imm)))) + end + ); + +fun dfn'ADDIW (rd,(rs1,imm)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val temp = BitsN.+(GPR rs1,BitsN.signExtend 64 imm) + in + ( write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.bits(31,0) temp)))) + end + ) + end; + +fun dfn'SLTI (rd,(rs1,imm)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + in + ( write'GPR + (BitsN.fromBool 64 (BitsN.<(v1,BitsN.signExtend 64 imm)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.fromBool 64 (BitsN.<(v1,BitsN.signExtend 64 imm))))) + end + ) + end; + +fun dfn'SLTIU (rd,(rs1,imm)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + in + ( write'GPR + (BitsN.fromBool 64 (BitsN.<+(v1,BitsN.signExtend 64 imm)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.fromBool 64 (BitsN.<+(v1,BitsN.signExtend 64 imm))))) + end + ) + end; + +fun dfn'ANDI (rd,(rs1,imm)) = + ( write'GPR(BitsN.&&(GPR rs1,BitsN.signExtend 64 imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.&&(GPR rs1,BitsN.signExtend 64 imm)))) + end + ); + +fun dfn'ORI (rd,(rs1,imm)) = + ( write'GPR(BitsN.||(GPR rs1,BitsN.signExtend 64 imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.||(GPR rs1,BitsN.signExtend 64 imm)))) + end + ); + +fun dfn'XORI (rd,(rs1,imm)) = + ( write'GPR(BitsN.??(GPR rs1,BitsN.signExtend 64 imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.??(GPR rs1,BitsN.signExtend 64 imm)))) + end + ); + +fun dfn'SLLI (rd,(rs1,imm)) = + if (in32BitMode ()) andalso (BitsN.bit(imm,5)) + then signalException Illegal_Instr + else ( write'GPR(BitsN.<<(GPR rs1,BitsN.toNat imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.<<(GPR rs1,BitsN.toNat imm)))) + end + ); + +fun dfn'SRLI (rd,(rs1,imm)) = + if (in32BitMode ()) andalso (BitsN.bit(imm,5)) + then signalException Illegal_Instr + else let + val v1 = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + in + ( write'GPR(BitsN.>>+(v1,BitsN.toNat imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.>>+(v1,BitsN.toNat imm)))) + end + ) + end; + +fun dfn'SRAI (rd,(rs1,imm)) = + if (in32BitMode ()) andalso (BitsN.bit(imm,5)) + then signalException Illegal_Instr + else let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + in + ( write'GPR(BitsN.>>(v1,BitsN.toNat imm),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.>>(v1,BitsN.toNat imm)))) + end + ) + end; + +fun dfn'SLLIW (rd,(rs1,imm)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.<<(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.<< + (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) + end + ); + +fun dfn'SRLIW (rd,(rs1,imm)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.>>+(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.>>+ + (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) + end + ); + +fun dfn'SRAIW (rd,(rs1,imm)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.>>(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.>> + (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) + end + ); + +fun dfn'LUI (rd,imm) = + ( write'GPR(BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12)))))) + end + ); + +fun dfn'AUIPC (rd,imm) = + ( write'GPR + (BitsN.+(PC (),BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12)))), + rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.+ + (PC (), + BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12))))))) + end + ); + +fun dfn'ADD (rd,(rs1,rs2)) = + ( write'GPR(BitsN.+(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.+(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'ADDW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.+ + (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))), + rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.+ + (BitsN.bits(31,0) (GPR rs1), + BitsN.bits(31,0) (GPR rs2)))))) + end + ); + +fun dfn'SUB (rd,(rs1,rs2)) = + ( write'GPR(BitsN.-(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.-(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'SUBW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.- + (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))), + rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.- + (BitsN.bits(31,0) (GPR rs1), + BitsN.bits(31,0) (GPR rs2)))))) + end + ); + +fun dfn'SLT (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + ( write'GPR(BitsN.fromBool 64 (BitsN.<(v1,v2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.fromBool 64 (BitsN.<(v1,v2))))) + end + ) + end; + +fun dfn'SLTU (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + ( write'GPR(BitsN.fromBool 64 (BitsN.<+(v1,v2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.fromBool 64 (BitsN.<+(v1,v2))))) + end + ) + end; + +fun dfn'AND (rd,(rs1,rs2)) = + ( write'GPR(BitsN.&&(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.&&(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'OR (rd,(rs1,rs2)) = + ( write'GPR(BitsN.||(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.||(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'XOR (rd,(rs1,rs2)) = + ( write'GPR(BitsN.??(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.??(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'SLL (rd,(rs1,rs2)) = + if in32BitMode () + then ( write'GPR + (BitsN.<<^ + (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(4,0) (GPR rs2))), + rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.<<^ + (GPR rs1, + BitsN.zeroExtend 64 (BitsN.bits(4,0) (GPR rs2)))))) + end + ) + else ( write'GPR + (BitsN.<<^ + (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.<<^ + (GPR rs1, + BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) + end + ); + +fun dfn'SLLW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.<<^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.<<^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) + end + ); + +fun dfn'SRL (rd,(rs1,rs2)) = + if in32BitMode () + then ( write'GPR + (BitsN.zeroExtend 64 + (BitsN.>>+^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.zeroExtend 64 + (BitsN.>>+^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 + (BitsN.bits(4,0) (GPR rs2))))))) + end + ) + else ( write'GPR + (BitsN.>>+^ + (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.>>+^ + (GPR rs1, + BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) + end + ); + +fun dfn'SRLW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.>>+^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.>>+^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) + end + ); + +fun dfn'SRA (rd,(rs1,rs2)) = + if in32BitMode () + then ( write'GPR + (BitsN.signExtend 64 + (BitsN.>>^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.>>^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 + (BitsN.bits(4,0) (GPR rs2))))))) + end + ) + else ( write'GPR + (BitsN.>>^ + (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.>>^ + (GPR rs1, + BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) + end + ); + +fun dfn'SRAW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else ( write'GPR + (BitsN.signExtend 64 + (BitsN.>>^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.>>^ + (BitsN.bits(31,0) (GPR rs1), + BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) + end + ); + +fun dfn'MUL (rd,(rs1,rs2)) = + ( write'GPR(BitsN.*(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.*(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'MULH (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + val prod = BitsN.*(BitsN.signExtend 128 v1,BitsN.signExtend 128 v2) + val res = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(63,32) prod) + else BitsN.signExtend 64 (BitsN.bits(127,64) prod) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end; + +fun dfn'MULHU (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs1)) + else BitsN.zeroExtend 128 (GPR rs1) + val v2 = + if in32BitMode () + then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs2)) + else BitsN.zeroExtend 128 (GPR rs2) + val prod = BitsN.*(v1,v2) + val res = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(63,32) prod) + else BitsN.bits(127,64) prod + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end; + +fun dfn'MULHSU (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 128 (BitsN.bits(31,0) (GPR rs1)) + else BitsN.signExtend 128 (GPR rs1) + val v2 = + if in32BitMode () + then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs2)) + else BitsN.zeroExtend 128 (GPR rs2) + val prod = BitsN.*(v1,v2) + val res = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(63,32) prod) + else BitsN.bits(127,64) prod + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end; + +fun dfn'MULW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val prod = + BitsN.signExtend 64 + (BitsN.* + (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))) + in + ( write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) prod),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.bits(31,0) prod)))) + end + ) + end; + +fun dfn'DIV (rd,(rs1,rs2)) = + if (GPR rs2) = (BitsN.B(0x0,64)) + then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.signExtend 64 (BitsN.B(0x1,1))))) + end + ) + else ( write'GPR(BitsN.quot(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.quot(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'REM (rd,(rs1,rs2)) = + if (GPR rs2) = (BitsN.B(0x0,64)) + then ( write'GPR(GPR rs1,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME(GPR rs1))) + end + ) + else ( write'GPR(BitsN.rem(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.rem(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'DIVU (rd,(rs1,rs2)) = + let + val v1 = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if v2 = (BitsN.B(0x0,64)) + then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.signExtend 64 (BitsN.B(0x1,1))))) + end + ) + else ( write'GPR(BitsN.div(v1,v2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.div(v1,v2)))) + end + ) + end; + +fun dfn'REMU (rd,(rs1,rs2)) = + if (GPR rs2) = (BitsN.B(0x0,64)) + then ( write'GPR(GPR rs1,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME(GPR rs1))) + end + ) + else ( write'GPR(BitsN.mod(GPR rs1,GPR rs2),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.mod(GPR rs1,GPR rs2)))) + end + ); + +fun dfn'DIVW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val s1 = BitsN.bits(31,0) (GPR rs1) + val s2 = BitsN.bits(31,0) (GPR rs2) + in + if s2 = (BitsN.B(0x0,32)) + then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.B(0x1,1))))) + end + ) + else ( write'GPR(BitsN.signExtend 64 (BitsN.quot(s1,s2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.quot(s1,s2))))) + end + ) + end; + +fun dfn'REMW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val s1 = BitsN.bits(31,0) (GPR rs1) + val s2 = BitsN.bits(31,0) (GPR rs2) + in + if s2 = (BitsN.B(0x0,32)) + then ( write'GPR(BitsN.signExtend 64 s1,rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.signExtend 64 s1))) + end + ) + else ( write'GPR(BitsN.signExtend 64 (BitsN.rem(s1,s2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.rem(s1,s2))))) + end + ) + end; + +fun dfn'DIVUW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val s1 = BitsN.bits(31,0) (GPR rs1) + val s2 = BitsN.bits(31,0) (GPR rs2) + in + if s2 = (BitsN.B(0x0,32)) + then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.B(0x1,1))))) + end + ) + else ( write'GPR(BitsN.signExtend 64 (BitsN.div(s1,s2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.div(s1,s2))))) + end + ) + end; + +fun dfn'REMUW (rd,(rs1,rs2)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val s1 = BitsN.bits(31,0) (GPR rs1) + val s2 = BitsN.bits(31,0) (GPR rs2) + in + if s2 = (BitsN.B(0x0,32)) + then ( write'GPR(BitsN.signExtend 64 s1,rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.signExtend 64 s1))) + end + ) + else ( write'GPR(BitsN.signExtend 64 (BitsN.mod(s1,s2)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 (BitsN.mod(s1,s2))))) + end + ) + end; + +fun dfn'JAL (rd,imm) = + let + val addr = BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 imm,1)) + in + if not((BitsN.bits(1,0) addr) = (BitsN.B(0x0,2))) + then signalAddressException(Fetch_Misaligned,addr) + else ( ( write'GPR(BitsN.+(PC (),BitsN.B(0x4,64)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + ) + ; branchTo addr + ) + end; + +fun dfn'JALR (rd,(rs1,imm)) = + let + val addr = + BitsN.&& + (BitsN.+(GPR rs1,BitsN.signExtend 64 imm), + BitsN.signExtend 64 (BitsN.B(0x2,2))) + in + if not((BitsN.bits(1,0) addr) = (BitsN.B(0x0,2))) + then signalAddressException(Fetch_Misaligned,addr) + else ( ( write'GPR(BitsN.+(PC (),BitsN.B(0x4,64)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + ) + ; branchTo addr + ) + end; + +fun dfn'BEQ (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if v1 = v2 + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'BNE (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if not(v1 = v2) + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'BLT (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if BitsN.<(v1,v2) + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'BLTU (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if BitsN.<+(v1,v2) + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'BGE (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if BitsN.>=(v1,v2) + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'BGEU (rs1,(rs2,offs)) = + let + val v1 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) + else GPR rs1 + val v2 = + if in32BitMode () + then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) + else GPR rs2 + in + if BitsN.>=+(v1,v2) + then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) + else let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd + (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) + end + end; + +fun dfn'LW (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.signExtend 64 (BitsN.bits(31,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LWU (rd,(rs1,offs)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.zeroExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LH (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.signExtend 64 (BitsN.bits(15,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LHU (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.zeroExtend 64 (BitsN.bits(15,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LB (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.signExtend 64 (BitsN.bits(7,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LBU (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = + BitsN.zeroExtend 64 (BitsN.bits(7,0) (rawReadData pAddr)) + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LD (rd,(rs1,offs)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = rawReadData pAddr + in + ( write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'SW (rs1,(rs2,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,4)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'SH (rs1,(rs2,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,2)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x2,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'SB (rs1,(rs2,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,1)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x1,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'SD (rs1,(rs2,offs)) = + if in32BitMode () + then signalException Illegal_Instr + else let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,8)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'FENCE (rd,(rs1,(pred,succ))) = (); + +fun dfn'FENCE_I (rd,(rs1,imm)) = (); + +fun dfn'LR_W (aq,(rl,(rd,rs1))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + ( ( write'GPR + (BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x, + Option.SOME + (BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr))))) + end + ) + ; write'ReserveLoad(Option.SOME vAddr) + ) + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'LR_D (aq,(rl,(rd,rs1))) = + if in32BitMode () + then signalException Illegal_Instr + else let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + ( ( write'GPR(rawReadData pAddr,rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(rawReadData pAddr))) + end + ) + ; write'ReserveLoad(Option.SOME vAddr) + ) + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'SC_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else if not(matchLoadReservation vAddr) + then ( write'GPR(BitsN.B(0x1,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x1,64)))) + end + ) + else case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + ; ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; write'ReserveLoad NONE + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'SC_D (aq,(rl,(rd,(rs1,rs2)))) = + if in32BitMode () + then signalException Illegal_Instr + else let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else if not(matchLoadReservation vAddr) + then ( write'GPR(BitsN.B(0x1,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.B(0x1,64)))) + end + ) + else case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val data = GPR rs2 + in + ( rawWriteData(pAddr,(data,8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + ; ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; write'ReserveLoad NONE + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOSWAP_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; rawWriteData(pAddr,(data,4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOSWAP_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; rawWriteData(pAddr,(data,8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOADD_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.+(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOADD_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.+(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOXOR_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.??(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOXOR_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.??(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOAND_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.&&(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOAND_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.&&(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOOR_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.||(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOOR_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.||(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMIN_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.smin(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMIN_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.smin(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMAX_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.smax(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMAX_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.smax(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMINU_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.min(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMINU_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.min(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMAXU_W (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = + BitsN.signExtend 64 + (BitsN.bits(31,0) (rawReadData pAddr)) + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.max(data,memv) + in + ( rawWriteData(pAddr,(val',4)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'AMOMAXU_D (aq,(rl,(rd,(rs1,rs2)))) = + let + val vAddr = GPR rs1 + in + if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) + then signalAddressException(AMO_Misaligned,vAddr) + else case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val memv = rawReadData pAddr + val data = GPR rs2 + in + ( write'GPR(memv,rd) + ; let + val val' = BitsN.max(data,memv) + in + ( rawWriteData(pAddr,(val',8)) + ; ( let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME memv)) + end + ) + ; let + val x = Delta () + in + write'Delta + (StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd(x,Option.SOME val')) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd + (x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'FLW (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = BitsN.bits(31,0) (rawReadData pAddr) + in + ( write'FPRS(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.zeroExtend 64 val'))) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'FSW (rs1,(rs2,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = FPRS rs2 + in + ( rawWriteData(pAddr,(BitsN.zeroExtend 64 data,4)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_data2_rupd + (x,Option.SOME(BitsN.zeroExtend 64 data))) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x4,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'FADD_S (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRS(rd,(L3.snd o FP32.add) (r,(FPRS rs1,FPRS rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FSUB_S (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRS(rd,(L3.snd o FP32.sub) (r,(FPRS rs1,FPRS rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FMUL_S (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRS(rd,(L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FDIV_S (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRS(rd,(L3.snd o FP32.div) (r,(FPRS rs1,FPRS rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FSQRT_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRS(rd,(L3.snd o FP32.sqrt) (r,FPRS rs)) + | NONE => signalException Illegal_Instr; + +fun dfn'FMIN_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + val res = + case FP32.compare(f1,f2) of + IEEEReal.LESS => f1 + | IEEEReal.EQUAL => f1 + | IEEEReal.GREATER => f2 + | IEEEReal.UNORDERED => + if ((FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2)) orelse + ((f1 = RV32_CanonicalNan) andalso (f2 = RV32_CanonicalNan)) + then RV32_CanonicalNan + else if f1 = RV32_CanonicalNan then f2 else f1 + in + writeFPRS(rd,res) + end; + +fun dfn'FMAX_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + val res = + case FP32.compare(f1,f2) of + IEEEReal.LESS => f2 + | IEEEReal.EQUAL => f2 + | IEEEReal.GREATER => f1 + | IEEEReal.UNORDERED => + if ((FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2)) orelse + ((f1 = RV32_CanonicalNan) andalso (f2 = RV32_CanonicalNan)) + then RV32_CanonicalNan + else if f1 = RV32_CanonicalNan then f2 else f1 + in + writeFPRS(rd,res) + end; + +fun dfn'FMADD_S (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd, + (L3.snd o FP32.add) + (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3))) + | NONE => signalException Illegal_Instr; + +fun dfn'FMSUB_S (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd, + (L3.snd o FP32.sub) + (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3))) + | NONE => signalException Illegal_Instr; + +fun dfn'FNMADD_S (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd, + FP32.neg + ((L3.snd o FP32.add) + (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FNMSUB_S (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd, + FP32.neg + ((L3.snd o FP32.sub) + (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_S_W (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd,FP32.fromInt(r,BitsN.toInt(BitsN.bits(31,0) (GPR rs)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_S_WU (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd, + FP32.fromInt + (r, + BitsN.toInt + (BitsN.@@(BitsN.B(0x0,1),BitsN.bits(31,0) (GPR rs))))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_W_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRS rs + val val' = Option.valOf(FP32.toInt(r,inp)) + val res = + if (FP32.isNan inp) orelse (inp = FP32.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) + else if inp = FP32.negInf + then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,31),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) + else if IntInf.<(val',IntInf.~(IntInf.pow(2,31))) + then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_WU_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRS rs + val val' = Option.valOf(FP32.toInt(r,inp)) + val res = + if (FP32.isNan inp) orelse (inp = FP32.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) + else if inp = FP32.negInf + then BitsN.B(0x0,64) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,32),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) + else if IntInf.<(val',0) + then BitsN.B(0x0,64) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_S_L (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRS(rd,FP32.fromInt(r,BitsN.toInt(GPR rs))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_S_LU (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRS + (rd,FP32.fromInt(r,BitsN.toInt(BitsN.@@(BitsN.B(0x0,1),GPR rs)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_L_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRS rs + val val' = Option.valOf(FP32.toInt(r,inp)) + val res = + if (FP32.isNan inp) orelse (inp = FP32.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) + else if inp = FP32.negInf + then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,63),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) + else if IntInf.<(val',IntInf.~(IntInf.pow(2,63))) + then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_LU_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRS rs + val val' = Option.valOf(FP32.toInt(r,inp)) + val res = + if (FP32.isNan inp) orelse (inp = FP32.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) + else if inp = FP32.negInf + then BitsN.B(0x0,64) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,64),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) + else if IntInf.<(val',0) + then BitsN.B(0x0,64) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FSGNJ_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + writeFPRS + (rd,BitsN.@@(BitsN.fromBit(FP32_Sign f2),BitsN.bits(30,0) f1)) + end; + +fun dfn'FSGNJN_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + writeFPRS + (rd,BitsN.@@(BitsN.fromBit(not(FP32_Sign f2)),BitsN.bits(30,0) f1)) + end; + +fun dfn'FSGNJX_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + writeFPRS + (rd, + BitsN.@@ + (BitsN.?? + (BitsN.fromBit(FP32_Sign f2),BitsN.fromBit(FP32_Sign f1)), + BitsN.bits(30,0) f1)) + end; + +fun dfn'FMV_X_S (rd,rs) = write'GPR(BitsN.signExtend 64 (FPRS rs),rd); + +fun dfn'FMV_S_X (rd,rs) = writeFPRS(rd,BitsN.bits(31,0) (GPR rs)); + +fun dfn'FEQ_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + if (FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP32.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x0,64) + | IEEEReal.EQUAL => BitsN.B(0x1,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FLT_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + if (FP32.isNan f1) orelse (FP32.isNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP32.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x1,64) + | IEEEReal.EQUAL => BitsN.B(0x0,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FLE_S (rd,(rs1,rs2)) = + let + val f1 = FPRS rs1 + val f2 = FPRS rs2 + in + if (FP32.isNan f1) orelse (FP32.isNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP32.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x1,64) + | IEEEReal.EQUAL => BitsN.B(0x1,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FCLASS_S (rd,rs) = + let + val ret = ref (BitsN.B(0x0,10)) + in + let + val val' = FPRS rs + in + ( ret := + (BitsN.bitFieldInsert(0,0) + ((!ret),BitsN.fromBit(val' = FP32.negInf))) + ; ret := + (BitsN.bitFieldInsert(1,1) + ((!ret), + BitsN.fromBit((FP32_Sign val') andalso (FP32.isNormal val')))) + ; ret := + (BitsN.bitFieldInsert(2,2) + ((!ret), + BitsN.fromBit + ((FP32_Sign val') andalso (FP32.isSubnormal val')))) + ; ret := + (BitsN.bitFieldInsert(3,3) + ((!ret),BitsN.fromBit(val' = FP32.negZero))) + ; ret := + (BitsN.bitFieldInsert(4,4) + ((!ret),BitsN.fromBit(val' = FP32.posZero))) + ; ret := + (BitsN.bitFieldInsert(5,5) + ((!ret), + BitsN.fromBit + ((not(FP32_Sign val')) andalso (FP32.isSubnormal val')))) + ; ret := + (BitsN.bitFieldInsert(6,6) + ((!ret), + BitsN.fromBit + ((not(FP32_Sign val')) andalso (FP32.isNormal val')))) + ; ret := + (BitsN.bitFieldInsert(7,7) + ((!ret),BitsN.fromBit(val' = FP32.posInf))) + ; ret := + (BitsN.bitFieldInsert(8,8) + ((!ret),BitsN.fromBit(FP32_IsSignalingNan val'))) + ; ret := + (BitsN.bitFieldInsert(9,9) + ((!ret),BitsN.fromBit(val' = RV32_CanonicalNan))) + ; write'GPR(BitsN.zeroExtend 64 (!ret),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.zeroExtend 64 (!ret)))) + end + ) + end + end; + +fun dfn'FLD (rd,(rs1,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Read)) of + Option.SOME pAddr => + let + val val' = rawReadData pAddr + in + ( write'FPRD(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + | NONE => signalAddressException(Load_Fault,vAddr) + end; + +fun dfn'FSD (rs1,(rs2,offs)) = + let + val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) + in + case translateAddr(vAddr,(Data,Write)) of + Option.SOME pAddr => + let + val data = FPRD rs2 + in + ( rawWriteData(pAddr,(data,8)) + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) + end + ; let + val x = Delta () + in + write'Delta + (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x8,32)))) + end + ) + end + | NONE => signalAddressException(Store_AMO_Fault,vAddr) + end; + +fun dfn'FADD_D (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRD(rd,(L3.snd o FP64.add) (r,(FPRD rs1,FPRD rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FSUB_D (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRD(rd,(L3.snd o FP64.sub) (r,(FPRD rs1,FPRD rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FMUL_D (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRD(rd,(L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FDIV_D (rd,(rs1,(rs2,fprnd))) = + case round fprnd of + Option.SOME r => + writeFPRD(rd,(L3.snd o FP64.div) (r,(FPRD rs1,FPRD rs2))) + | NONE => signalException Illegal_Instr; + +fun dfn'FSQRT_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRD(rd,(L3.snd o FP64.sqrt) (r,FPRD rs)) + | NONE => signalException Illegal_Instr; + +fun dfn'FMIN_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + val res = + case FP64.compare(f1,f2) of + IEEEReal.LESS => f1 + | IEEEReal.EQUAL => f1 + | IEEEReal.GREATER => f2 + | IEEEReal.UNORDERED => + if ((FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2)) orelse + ((f1 = RV64_CanonicalNan) andalso (f2 = RV64_CanonicalNan)) + then RV64_CanonicalNan + else if f1 = RV64_CanonicalNan then f2 else f1 + in + writeFPRD(rd,res) + end; + +fun dfn'FMAX_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + val res = + case FP64.compare(f1,f2) of + IEEEReal.LESS => f2 + | IEEEReal.EQUAL => f2 + | IEEEReal.GREATER => f1 + | IEEEReal.UNORDERED => + if ((FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2)) orelse + ((f1 = RV64_CanonicalNan) andalso (f2 = RV64_CanonicalNan)) + then RV64_CanonicalNan + else if f1 = RV64_CanonicalNan then f2 else f1 + in + writeFPRD(rd,res) + end; + +fun dfn'FMADD_D (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd, + (L3.snd o FP64.add) + (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3))) + | NONE => signalException Illegal_Instr; + +fun dfn'FMSUB_D (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd, + (L3.snd o FP64.sub) + (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3))) + | NONE => signalException Illegal_Instr; + +fun dfn'FNMADD_D (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd, + FP64.neg + ((L3.snd o FP64.add) + (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FNMSUB_D (rd,(rs1,(rs2,(rs3,fprnd)))) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd, + FP64.neg + ((L3.snd o FP64.sub) + (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_D_W (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd,FP64.fromInt(r,BitsN.toInt(BitsN.bits(31,0) (GPR rs)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_D_WU (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd, + FP64.fromInt + (r, + BitsN.toInt + (BitsN.@@(BitsN.B(0x0,1),BitsN.bits(31,0) (GPR rs))))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_W_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRD rs + val val' = Option.valOf(FP64.toInt(r,inp)) + val res = + if (FP64.isNan inp) orelse (inp = FP64.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) + else if inp = FP64.negInf + then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,31),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) + else if IntInf.<(val',IntInf.~(IntInf.pow(2,31))) + then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_WU_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRD rs + val val' = Option.valOf(FP64.toInt(r,inp)) + val res = + if (FP64.isNan inp) orelse (inp = FP64.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) + else if inp = FP64.negInf + then BitsN.B(0x0,64) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,32),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) + else if IntInf.<(val',0) + then BitsN.B(0x0,64) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_D_L (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRD(rd,FP64.fromInt(r,BitsN.toInt(GPR rs))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_D_LU (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + writeFPRD + (rd,FP64.fromInt(r,BitsN.toInt(BitsN.@@(BitsN.B(0x0,1),GPR rs)))) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_L_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRD rs + val val' = Option.valOf(FP64.toInt(r,inp)) + val res = + if (FP64.isNan inp) orelse (inp = FP64.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) + else if inp = FP64.negInf + then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,63),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) + else if IntInf.<(val',IntInf.~(IntInf.pow(2,63))) + then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_LU_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => + let + val inp = FPRD rs + val val' = Option.valOf(FP64.toInt(r,inp)) + val res = + if (FP64.isNan inp) orelse (inp = FP64.posInf) + then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) + else if inp = FP64.negInf + then BitsN.B(0x0,64) + else if IntInf.>(val',IntInf.-(IntInf.pow(2,64),1)) + then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) + else if IntInf.<(val',0) + then BitsN.B(0x0,64) + else BitsN.fromInt(val',64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_S_D (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRS(rd,FPConvert.fp64_to_fp32(r,FPRD rs)) + | NONE => signalException Illegal_Instr; + +fun dfn'FCVT_D_S (rd,(rs,fprnd)) = + case round fprnd of + Option.SOME r => writeFPRD(rd,FPConvert.fp32_to_fp64(FPRS rs)) + | NONE => signalException Illegal_Instr; + +fun dfn'FSGNJ_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + writeFPRD + (rd,BitsN.@@(BitsN.fromBit(FP64_Sign f2),BitsN.bits(62,0) f1)) + end; + +fun dfn'FSGNJN_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + writeFPRD + (rd,BitsN.@@(BitsN.fromBit(not(FP64_Sign f2)),BitsN.bits(62,0) f1)) + end; + +fun dfn'FSGNJX_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + writeFPRD + (rd, + BitsN.@@ + (BitsN.?? + (BitsN.fromBit(FP64_Sign f2),BitsN.fromBit(FP64_Sign f1)), + BitsN.bits(62,0) f1)) + end; + +fun dfn'FMV_X_D (rd,rs) = write'GPR(BitsN.signExtend 64 (FPRD rs),rd); + +fun dfn'FMV_D_X (rd,rs) = writeFPRD(rd,GPR rs); + +fun dfn'FEQ_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + if (FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP64.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x0,64) + | IEEEReal.EQUAL => BitsN.B(0x1,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FLT_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + if (FP64.isNan f1) orelse (FP64.isNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP64.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x1,64) + | IEEEReal.EQUAL => BitsN.B(0x0,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FLE_D (rd,(rs1,rs2)) = + let + val f1 = FPRD rs1 + val f2 = FPRD rs2 + in + if (FP64.isNan f1) orelse (FP64.isNan f2) + then ( ( write'GPR(BitsN.B(0x0,64),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) + end + ) + ; setFP_Invalid () + ) + else let + val res = + case FP64.compare(f1,f2) of + IEEEReal.LESS => BitsN.B(0x1,64) + | IEEEReal.EQUAL => BitsN.B(0x1,64) + | IEEEReal.GREATER => BitsN.B(0x0,64) + | IEEEReal.UNORDERED => BitsN.B(0x0,64) + in + ( write'GPR(res,rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) + end + ) + end + end; + +fun dfn'FCLASS_D (rd,rs) = + let + val ret = ref (BitsN.B(0x0,10)) + in + let + val val' = FPRD rs + in + ( ret := + (BitsN.bitFieldInsert(0,0) + ((!ret),BitsN.fromBit(val' = FP64.negInf))) + ; ret := + (BitsN.bitFieldInsert(1,1) + ((!ret), + BitsN.fromBit((FP64_Sign val') andalso (FP64.isNormal val')))) + ; ret := + (BitsN.bitFieldInsert(2,2) + ((!ret), + BitsN.fromBit + ((FP64_Sign val') andalso (FP64.isSubnormal val')))) + ; ret := + (BitsN.bitFieldInsert(3,3) + ((!ret),BitsN.fromBit(val' = FP64.negZero))) + ; ret := + (BitsN.bitFieldInsert(4,4) + ((!ret),BitsN.fromBit(val' = FP64.posZero))) + ; ret := + (BitsN.bitFieldInsert(5,5) + ((!ret), + BitsN.fromBit + ((not(FP64_Sign val')) andalso (FP64.isSubnormal val')))) + ; ret := + (BitsN.bitFieldInsert(6,6) + ((!ret), + BitsN.fromBit + ((not(FP64_Sign val')) andalso (FP64.isNormal val')))) + ; ret := + (BitsN.bitFieldInsert(7,7) + ((!ret),BitsN.fromBit(val' = FP64.posInf))) + ; ret := + (BitsN.bitFieldInsert(8,8) + ((!ret),BitsN.fromBit(FP64_IsSignalingNan val'))) + ; ret := + (BitsN.bitFieldInsert(9,9) + ((!ret),BitsN.fromBit(val' = RV64_CanonicalNan))) + ; write'GPR(BitsN.zeroExtend 64 (!ret),rd) + ; let + val x = Delta () + in + write'Delta + (StateDelta_data1_rupd + (x,Option.SOME(BitsN.zeroExtend 64 (!ret)))) + end + ) + end + end; + +fun dfn'ECALL () = signalEnvCall (); + +fun dfn'EBREAK () = signalException Breakpoint; + +fun dfn'ERET () = write'NextFetch(Option.SOME Ereturn); + +fun dfn'MRTS () = + ( let + val x = SCSR () + in + write'SCSR + (SupervisorCSR_scause_rupd(x,#mcause((MCSR ()) : MachineCSR))) + end + ; let + val x = SCSR () + in + write'SCSR + (SupervisorCSR_sbadaddr_rupd(x,#mbadaddr((MCSR ()) : MachineCSR))) + end + ; let + val x = SCSR () + in + write'SCSR(SupervisorCSR_sepc_rupd(x,#mepc((MCSR ()) : MachineCSR))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd + (x,mstatus_MPRV_rupd(x0,privLevel Supervisor))) + end + ; write'NextFetch(Option.SOME Mrts) + ); + +val dfn'WFI = () + +fun checkCSROp (csr,(rs1,a)) = + (is_CSR_defined csr) andalso + (check_CSR_access(csrRW csr,(csrPR csr,(curPrivilege (),a)))); + +fun dfn'CSRRW (rd,(rs1,csr)) = + if checkCSROp(csr,(rs1,Write)) + then let + val val' = CSR csr + in + ( writeCSR(csr,GPR rs1) + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'CSRRS (rd,(rs1,csr)) = + if checkCSROp(csr,(rs1,if rs1 = (BitsN.B(0x0,5)) then Read else Write)) + then let + val val' = CSR csr + in + ( if not(rs1 = (BitsN.B(0x0,5))) + then writeCSR(csr,BitsN.||(val',GPR rs1)) + else () + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'CSRRC (rd,(rs1,csr)) = + if checkCSROp(csr,(rs1,if rs1 = (BitsN.B(0x0,5)) then Read else Write)) + then let + val val' = CSR csr + in + ( if not(rs1 = (BitsN.B(0x0,5))) + then writeCSR(csr,BitsN.&&(val',BitsN.~(GPR rs1))) + else () + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'CSRRWI (rd,(zimm,csr)) = + if checkCSROp + (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) + then let + val val' = CSR csr + in + ( if not(zimm = (BitsN.B(0x0,5))) + then writeCSR(csr,BitsN.zeroExtend 64 zimm) + else () + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'CSRRSI (rd,(zimm,csr)) = + if checkCSROp + (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) + then let + val val' = CSR csr + in + ( if not(zimm = (BitsN.B(0x0,5))) + then writeCSR(csr,BitsN.||(val',BitsN.zeroExtend 64 zimm)) + else () + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'CSRRCI (rd,(zimm,csr)) = + if checkCSROp + (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) + then let + val val' = CSR csr + in + ( if not(zimm = (BitsN.B(0x0,5))) + then writeCSR + (csr, + BitsN.&&(val',BitsN.~(BitsN.zeroExtend 64 zimm))) + else () + ; write'GPR(val',rd) + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) + end + ) + end + else signalException Illegal_Instr; + +fun dfn'SFENCE_VM rs1 = + let + val addr = + if rs1 = (BitsN.B(0x0,5)) then NONE else Option.SOME(GPR rs1) + in + write'TLB(flushTLB(curASID (),(addr,TLB ()))) + end; + +fun dfn'UnknownInstruction () = signalException Illegal_Instr; + +fun dfn'FETCH_MISALIGNED addr = + ( signalAddressException(Fetch_Misaligned,addr) + ; let + val x = Delta () + in + write'Delta(StateDelta_fetch_exc_rupd(x,true)) + end + ; let val x = Delta () in write'Delta(StateDelta_pc_rupd(x,addr)) end + ); + +fun dfn'FETCH_FAULT addr = + ( signalAddressException(Fetch_Fault,addr) + ; let + val x = Delta () + in + write'Delta(StateDelta_fetch_exc_rupd(x,true)) + end + ; let val x = Delta () in write'Delta(StateDelta_pc_rupd(x,addr)) end + ); + +fun Run v0 = + case v0 of + UnknownInstruction => dfn'UnknownInstruction () + | FENCE v170 => dfn'FENCE v170 + | FENCE_I v171 => dfn'FENCE_I v171 + | AMO v1 => + (case v1 of + AMOADD_D v2 => dfn'AMOADD_D v2 + | AMOADD_W v3 => dfn'AMOADD_W v3 + | AMOAND_D v4 => dfn'AMOAND_D v4 + | AMOAND_W v5 => dfn'AMOAND_W v5 + | AMOMAXU_D v6 => dfn'AMOMAXU_D v6 + | AMOMAXU_W v7 => dfn'AMOMAXU_W v7 + | AMOMAX_D v8 => dfn'AMOMAX_D v8 + | AMOMAX_W v9 => dfn'AMOMAX_W v9 + | AMOMINU_D v10 => dfn'AMOMINU_D v10 + | AMOMINU_W v11 => dfn'AMOMINU_W v11 + | AMOMIN_D v12 => dfn'AMOMIN_D v12 + | AMOMIN_W v13 => dfn'AMOMIN_W v13 + | AMOOR_D v14 => dfn'AMOOR_D v14 + | AMOOR_W v15 => dfn'AMOOR_W v15 + | AMOSWAP_D v16 => dfn'AMOSWAP_D v16 + | AMOSWAP_W v17 => dfn'AMOSWAP_W v17 + | AMOXOR_D v18 => dfn'AMOXOR_D v18 + | AMOXOR_W v19 => dfn'AMOXOR_W v19 + | LR_D v20 => dfn'LR_D v20 + | LR_W v21 => dfn'LR_W v21 + | SC_D v22 => dfn'SC_D v22 + | SC_W v23 => dfn'SC_W v23) + | ArithI v24 => + (case v24 of + ADDI v25 => dfn'ADDI v25 + | ADDIW v26 => dfn'ADDIW v26 + | ANDI v27 => dfn'ANDI v27 + | AUIPC v28 => dfn'AUIPC v28 + | LUI v29 => dfn'LUI v29 + | ORI v30 => dfn'ORI v30 + | SLTI v31 => dfn'SLTI v31 + | SLTIU v32 => dfn'SLTIU v32 + | XORI v33 => dfn'XORI v33) + | ArithR v34 => + (case v34 of + ADD v35 => dfn'ADD v35 + | ADDW v36 => dfn'ADDW v36 + | AND v37 => dfn'AND v37 + | OR v38 => dfn'OR v38 + | SLT v39 => dfn'SLT v39 + | SLTU v40 => dfn'SLTU v40 + | SUB v41 => dfn'SUB v41 + | SUBW v42 => dfn'SUBW v42 + | XOR v43 => dfn'XOR v43) + | Branch v44 => + (case v44 of + BEQ v45 => dfn'BEQ v45 + | BGE v46 => dfn'BGE v46 + | BGEU v47 => dfn'BGEU v47 + | BLT v48 => dfn'BLT v48 + | BLTU v49 => dfn'BLTU v49 + | BNE v50 => dfn'BNE v50 + | JAL v51 => dfn'JAL v51 + | JALR v52 => dfn'JALR v52) + | FArith v53 => + (case v53 of + FADD_D v54 => dfn'FADD_D v54 + | FADD_S v55 => dfn'FADD_S v55 + | FDIV_D v56 => dfn'FDIV_D v56 + | FDIV_S v57 => dfn'FDIV_S v57 + | FEQ_D v58 => dfn'FEQ_D v58 + | FEQ_S v59 => dfn'FEQ_S v59 + | FLE_D v60 => dfn'FLE_D v60 + | FLE_S v61 => dfn'FLE_S v61 + | FLT_D v62 => dfn'FLT_D v62 + | FLT_S v63 => dfn'FLT_S v63 + | FMADD_D v64 => dfn'FMADD_D v64 + | FMADD_S v65 => dfn'FMADD_S v65 + | FMAX_D v66 => dfn'FMAX_D v66 + | FMAX_S v67 => dfn'FMAX_S v67 + | FMIN_D v68 => dfn'FMIN_D v68 + | FMIN_S v69 => dfn'FMIN_S v69 + | FMSUB_D v70 => dfn'FMSUB_D v70 + | FMSUB_S v71 => dfn'FMSUB_S v71 + | FMUL_D v72 => dfn'FMUL_D v72 + | FMUL_S v73 => dfn'FMUL_S v73 + | FNMADD_D v74 => dfn'FNMADD_D v74 + | FNMADD_S v75 => dfn'FNMADD_S v75 + | FNMSUB_D v76 => dfn'FNMSUB_D v76 + | FNMSUB_S v77 => dfn'FNMSUB_S v77 + | FSQRT_D v78 => dfn'FSQRT_D v78 + | FSQRT_S v79 => dfn'FSQRT_S v79 + | FSUB_D v80 => dfn'FSUB_D v80 + | FSUB_S v81 => dfn'FSUB_S v81) + | FConv v82 => + (case v82 of + FCLASS_D v83 => dfn'FCLASS_D v83 + | FCLASS_S v84 => dfn'FCLASS_S v84 + | FCVT_D_L v85 => dfn'FCVT_D_L v85 + | FCVT_D_LU v86 => dfn'FCVT_D_LU v86 + | FCVT_D_S v87 => dfn'FCVT_D_S v87 + | FCVT_D_W v88 => dfn'FCVT_D_W v88 + | FCVT_D_WU v89 => dfn'FCVT_D_WU v89 + | FCVT_LU_D v90 => dfn'FCVT_LU_D v90 + | FCVT_LU_S v91 => dfn'FCVT_LU_S v91 + | FCVT_L_D v92 => dfn'FCVT_L_D v92 + | FCVT_L_S v93 => dfn'FCVT_L_S v93 + | FCVT_S_D v94 => dfn'FCVT_S_D v94 + | FCVT_S_L v95 => dfn'FCVT_S_L v95 + | FCVT_S_LU v96 => dfn'FCVT_S_LU v96 + | FCVT_S_W v97 => dfn'FCVT_S_W v97 + | FCVT_S_WU v98 => dfn'FCVT_S_WU v98 + | FCVT_WU_D v99 => dfn'FCVT_WU_D v99 + | FCVT_WU_S v100 => dfn'FCVT_WU_S v100 + | FCVT_W_D v101 => dfn'FCVT_W_D v101 + | FCVT_W_S v102 => dfn'FCVT_W_S v102 + | FMV_D_X v103 => dfn'FMV_D_X v103 + | FMV_S_X v104 => dfn'FMV_S_X v104 + | FMV_X_D v105 => dfn'FMV_X_D v105 + | FMV_X_S v106 => dfn'FMV_X_S v106 + | FSGNJN_D v107 => dfn'FSGNJN_D v107 + | FSGNJN_S v108 => dfn'FSGNJN_S v108 + | FSGNJX_D v109 => dfn'FSGNJX_D v109 + | FSGNJX_S v110 => dfn'FSGNJX_S v110 + | FSGNJ_D v111 => dfn'FSGNJ_D v111 + | FSGNJ_S v112 => dfn'FSGNJ_S v112) + | FPLoad v113 => + (case v113 of FLD v114 => dfn'FLD v114 | FLW v115 => dfn'FLW v115) + | FPStore v116 => + (case v116 of FSD v117 => dfn'FSD v117 | FSW v118 => dfn'FSW v118) + | Internal v119 => + (case v119 of + FETCH_FAULT v120 => dfn'FETCH_FAULT v120 + | FETCH_MISALIGNED v121 => dfn'FETCH_MISALIGNED v121) + | Load v122 => + (case v122 of + LB v123 => dfn'LB v123 + | LBU v124 => dfn'LBU v124 + | LD v125 => dfn'LD v125 + | LH v126 => dfn'LH v126 + | LHU v127 => dfn'LHU v127 + | LW v128 => dfn'LW v128 + | LWU v129 => dfn'LWU v129) + | MulDiv v130 => + (case v130 of + DIV v131 => dfn'DIV v131 + | DIVU v132 => dfn'DIVU v132 + | DIVUW v133 => dfn'DIVUW v133 + | DIVW v134 => dfn'DIVW v134 + | MUL v135 => dfn'MUL v135 + | MULH v136 => dfn'MULH v136 + | MULHSU v137 => dfn'MULHSU v137 + | MULHU v138 => dfn'MULHU v138 + | MULW v139 => dfn'MULW v139 + | REM v140 => dfn'REM v140 + | REMU v141 => dfn'REMU v141 + | REMUW v142 => dfn'REMUW v142 + | REMW v143 => dfn'REMW v143) + | Shift v144 => + (case v144 of + SLL v145 => dfn'SLL v145 + | SLLI v146 => dfn'SLLI v146 + | SLLIW v147 => dfn'SLLIW v147 + | SLLW v148 => dfn'SLLW v148 + | SRA v149 => dfn'SRA v149 + | SRAI v150 => dfn'SRAI v150 + | SRAIW v151 => dfn'SRAIW v151 + | SRAW v152 => dfn'SRAW v152 + | SRL v153 => dfn'SRL v153 + | SRLI v154 => dfn'SRLI v154 + | SRLIW v155 => dfn'SRLIW v155 + | SRLW v156 => dfn'SRLW v156) + | Store v157 => + (case v157 of + SB v158 => dfn'SB v158 + | SD v159 => dfn'SD v159 + | SH v160 => dfn'SH v160 + | SW v161 => dfn'SW v161) + | System v162 => + (case v162 of + EBREAK => dfn'EBREAK () + | ECALL => dfn'ECALL () + | ERET => dfn'ERET () + | MRTS => dfn'MRTS () + | WFI => dfn'WFI + | CSRRC v163 => dfn'CSRRC v163 + | CSRRCI v164 => dfn'CSRRCI v164 + | CSRRS v165 => dfn'CSRRS v165 + | CSRRSI v166 => dfn'CSRRSI v166 + | CSRRW v167 => dfn'CSRRW v167 + | CSRRWI v168 => dfn'CSRRWI v168 + | SFENCE_VM v169 => dfn'SFENCE_VM v169); + +fun Fetch () = + let + val vPC = PC () + in + if not((BitsN.bits(1,0) vPC) = (BitsN.B(0x0,2))) + then F_Error(Internal(FETCH_MISALIGNED vPC)) + else case translateAddr(vPC,(Instruction,Read)) of + Option.SOME pPC => + let + val instw = rawReadInst pPC + in + ( ( let + val x = Delta () + in + write'Delta(StateDelta_exc_taken_rupd(x,false)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_fetch_exc_rupd(x,false)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_pc_rupd(x,vPC)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_rinstr_rupd(x,instw)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_addr_rupd(x,NONE)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data1_rupd(x,NONE)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_data2_rupd(x,NONE)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_fp_data_rupd(x,NONE)) + end + ; let + val x = Delta () + in + write'Delta(StateDelta_st_width_rupd(x,NONE)) + end + ) + ; F_Result instw + ) + end + | NONE => F_Error(Internal(FETCH_FAULT vPC)) + end; + +fun asImm12 (imm12,(imm11,(immhi,immlo))) = + BitsN.concat[imm12,imm11,immhi,immlo]; + +fun asImm20 (imm20,(immhi,(imm11,immlo))) = + BitsN.concat[imm20,immhi,imm11,immlo]; + +fun asSImm12 (immhi,immlo) = BitsN.@@(immhi,immlo); + +fun Decode w = + case boolify'32 w of + (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BEQ(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BNE(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BLT(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BGE(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BLTU + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (i12'0, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (true, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (true, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Branch + (BGEU + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asImm12 + (BitsN.fromBitstring([i12'0],1), + (BitsN.fromBitstring([i11'0],1), + (BitsN.fromBitstring + ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), + BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + Branch + (JALR + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (i20'0, + (ilo'9, + (ilo'8, + (ilo'7, + (ilo'6, + (ilo'5, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (i11'0, + (ihi'7, + (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true,(true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + Branch + (JAL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + asImm20 + (BitsN.fromBitstring([i20'0],1), + (BitsN.fromBitstring + ([ihi'7,ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],8), + (BitsN.fromBitstring([i11'0],1), + BitsN.fromBitstring + ([ilo'9,ilo'8,ilo'7,ilo'6,ilo'5,ilo'4,ilo'3,ilo'2, + ilo'1,ilo'0],10)))))) + | (imm'19, + (imm'18, + (imm'17, + (imm'16, + (imm'15, + (imm'14, + (imm'13, + (imm'12, + (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => + ArithI + (LUI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring + ([imm'19,imm'18,imm'17,imm'16,imm'15,imm'14,imm'13,imm'12, + imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],20))) + | (imm'19, + (imm'18, + (imm'17, + (imm'16, + (imm'15, + (imm'14, + (imm'13, + (imm'12, + (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => + ArithI + (AUIPC + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring + ([imm'19,imm'18,imm'17,imm'16,imm'15,imm'14,imm'13,imm'12, + imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],20))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (ADDI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (shamt'5, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SLLI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (SLTI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (SLTIU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (XORI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (shamt'5, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRLI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (shamt'5, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRAI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (ORI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (ANDI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (ADD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (SUB(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SLL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (SLT(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (SLTU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (XOR(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRA(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (OR(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (AND(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + ArithI + (ADDIW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SLLIW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRLIW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (shamt'4, + (shamt'3, + (shamt'2, + (shamt'1, + (shamt'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRAIW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (ADDW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + ArithR + (SUBW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SLLW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRLW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + Shift + (SRAW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (MUL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (MULH + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (MULHSU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (MULHU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (DIV(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (DIVU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (REM(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (REMU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (MULW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (DIVW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (DIVUW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (REMW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => + MulDiv + (REMUW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LB(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LH(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LW(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LBU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LHU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Load + (LWU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Store + (SB(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Store + (SH(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Store + (SW(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + Store + (SD(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (_, + (_, + (_, + (_, + (pred'3, + (pred'2, + (pred'1, + (pred'0, + (succ'3, + (succ'2, + (succ'1, + (succ'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + FENCE + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([pred'3,pred'2,pred'1,pred'0],4), + BitsN.fromBitstring([succ'3,succ'2,succ'1,succ'0],4)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + FENCE_I + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMADD_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMSUB_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FNMSUB_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + FArith + (FNMADD_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FADD_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (false, + (true, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FSUB_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (true, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMUL_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (true, + (true, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FDIV_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (true, + (false, + (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FSQRT_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (false, + (false, + (true, + (false, + (true, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMIN_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (true, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMAX_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FEQ_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FLT_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FLE_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJ_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJN_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (false, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJX_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_W_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_WU_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FMV_X_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (true, + (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCLASS_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (true, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_S_W + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_S_WU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FMV_S_X + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMADD_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMSUB_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FNMSUB_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (rs3'4, + (rs3'3, + (rs3'2, + (rs3'1, + (rs3'0, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + FArith + (FNMADD_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) + | (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FADD_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (false, + (true, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FSUB_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (true, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMUL_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (false, + (false, + (true, + (true, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FDIV_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) + | (false, + (true, + (false, + (true, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FSQRT_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (false, + (false, + (true, + (false, + (true, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMIN_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (true, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FMAX_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FEQ_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FLT_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FArith + (FLE_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJ_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJN_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (false, + (false, + (true, + (false, + (false, + (false, + (true, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FSGNJX_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_W_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_WU_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (true, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCLASS_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (true, + (true, + (false, + (true, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_D_W + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_D_WU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_L_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_LU_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_S_L + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_S_LU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (true, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_L_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (true, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_LU_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (true, + (false, + (false, + (false, + (true, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_D_L + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (false, + (true, + (false, + (false, + (true, + (false, + (false, + (false, + (true, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_D_LU + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (true, + (true, + (true, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FMV_X_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (true, + (true, + (true, + (true, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FMV_D_X + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_S_D + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (false, + (true, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (frm'2, + (frm'1, + (frm'0, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + FConv + (FCVT_D_S + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FPLoad + (FLW(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (imm'11, + (imm'10, + (imm'9, + (imm'8, + (imm'7, + (imm'6, + (imm'5, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FPLoad + (FLD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, + imm'2,imm'1,imm'0],12)))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FPStore + (FSW(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (ihi'6, + (ihi'5, + (ihi'4, + (ihi'3, + (ihi'2, + (ihi'1, + (ihi'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (ilo'4, + (ilo'3, + (ilo'2, + (ilo'1, + (ilo'0, + (false, + (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => + FPStore + (FSD(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), + asSImm12 + (BitsN.fromBitstring + ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), + BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) + | (false, + (false, + (false, + (true, + (false, + (aq'0, + (rl'0, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(LR_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))))) + | (false, + (false, + (false, + (true, + (false, + (aq'0, + (rl'0, + (false, + (false, + (false, + (false, + (false, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(LR_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))))) + | (false, + (false, + (false, + (true, + (true, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(SC_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (false, + (true, + (true, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(SC_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (false, + (false, + (true, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOSWAP_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOADD_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOXOR_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (true, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOAND_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (true, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOOR_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (false, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMIN_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (false, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMAX_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (true, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMINU_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (true, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMAXU_W + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (false, + (false, + (true, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOSWAP_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOADD_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (false, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOXOR_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (true, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOAND_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (false, + (true, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOOR_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (false, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMIN_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (false, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMAX_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (true, + (false, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMINU_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (true, + (true, + (true, + (false, + (false, + (aq'0, + (rl'0, + (rs2'4, + (rs2'3, + (rs2'2, + (rs2'1, + (rs2'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (false, + (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => + AMO(AMOMAXU_D + (BitsN.fromBitstring([aq'0],1), + (BitsN.fromBitstring([rl'0],1), + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRW + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRS + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRC + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (true, + (false, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRWI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (true, + (true, + (false, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRSI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (csr'11, + (csr'10, + (csr'9, + (csr'8, + (csr'7, + (csr'6, + (csr'5, + (csr'4, + (csr'3, + (csr'2, + (csr'1, + (csr'0, + (imm'4, + (imm'3, + (imm'2, + (imm'1, + (imm'0, + (true, + (true, + (true, + (rd'4, + (rd'3, + (rd'2, + (rd'1, + (rd'0, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (CSRRCI + (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), + (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), + BitsN.fromBitstring + ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, + csr'2,csr'1,csr'0],12)))) + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System ECALL + | (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System EBREAK + | (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System ERET + | (false, + (false, + (true, + (true, + (false, + (false, + (false, + (false, + (false, + (true, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System MRTS + | (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System WFI + | (false, + (false, + (false, + (true, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (rs1'4, + (rs1'3, + (rs1'2, + (rs1'1, + (rs1'0, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (false, + (true, + (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => + System + (SFENCE_VM(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) + | _ => UnknownInstruction; + +fun imm N i = "0x" ^ (BitsN.toHexString i); + +fun instr o' = L3.padRightString(#" ",(12,o')); + +fun amotype (aq,rl) = + case (aq,rl) of + (BitsN.B(0x0,_),BitsN.B(0x0,_)) => "" + | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => ".aq" + | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => ".rl" + | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => ".sc"; + +fun pRtype (o',(rd,(rs1,rs2))) = + String.concat[instr o'," ",reg rd,", ",reg rs1,", ",reg rs2]; + +fun pARtype (o',(aq,(rl,(rd,(rs1,rs2))))) = + pRtype(o' ^ (amotype(aq,rl)),(rd,(rs1,rs2))); + +fun pLRtype (o',(aq,(rl,(rd,rs1)))) = + String.concat[instr(o' ^ (amotype(aq,rl)))," ",reg rd,", ",reg rs1]; + +fun pItype N (o',(rd,(rs1,i))) = + String.concat[instr o'," ",reg rd,", ",reg rs1,", ",imm N i]; + +fun pCSRtype (o',(rd,(rs1,csr))) = + String.concat[instr o'," ",reg rd,", ",reg rs1,", ",csrName csr]; + +fun pCSRItype N (o',(rd,(i,csr))) = + String.concat[instr o'," ",reg rd,", ",imm N i,", ",csrName csr]; + +fun pStype N (o',(rs1,(rs2,i))) = + String.concat[instr o'," ",reg rs2,", ",reg rs1,", ",imm N i]; + +fun pSBtype N (o',(rs1,(rs2,i))) = + String.concat + [instr o'," ",reg rs1,", ",reg rs2,", ",imm N (BitsN.<<(i,1))]; + +fun pUtype N (o',(rd,i)) = + String.concat[instr o'," ",reg rd,", ",imm N i]; + +fun pUJtype N (o',(rd,i)) = + String.concat[instr o'," ",reg rd,", ",imm N (BitsN.<<(i,1))]; + +fun pN0type o' = instr o'; + +fun pN1type (o',r) = String.concat[instr o'," ",reg r]; + +fun pFRtype (o',(rd,(rs1,rs2))) = + String.concat[instr o'," ",fpreg rd,", ",fpreg rs1,", ",fpreg rs2]; + +fun pFR1type (o',(rd,rs)) = + String.concat[instr o'," ",fpreg rd,", ",fpreg rs]; + +fun pFR3type (o',(rd,(rs1,(rs2,rs3)))) = + String.concat + [instr o'," ",fpreg rd,", ",fpreg rs1,", ",fpreg rs2,", ",fpreg rs3]; + +fun pFItype N (o',(rd,(rs1,i))) = + String.concat[instr o'," ",fpreg rd,", ",reg rs1,", ",imm N i]; + +fun pFStype N (o',(rs1,(rs2,i))) = + String.concat[instr o'," ",fpreg rs2,", ",reg rs1,", ",imm N i]; + +fun pCFItype (o',(rd,rs)) = + String.concat[instr o'," ",fpreg rd,", ",reg rs]; + +fun pCIFtype (o',(rd,rs)) = + String.concat[instr o'," ",reg rd,", ",fpreg rs]; + +fun instructionToString i = + case i of + Branch(BEQ(rs1,(rs2,imm))) => pSBtype 12 ("BEQ",(rs1,(rs2,imm))) + | Branch(BNE(rs1,(rs2,imm))) => pSBtype 12 ("BNE",(rs1,(rs2,imm))) + | Branch(BLT(rs1,(rs2,imm))) => pSBtype 12 ("BLT",(rs1,(rs2,imm))) + | Branch(BGE(rs1,(rs2,imm))) => pSBtype 12 ("BGE",(rs1,(rs2,imm))) + | Branch(BLTU(rs1,(rs2,imm))) => pSBtype 12 ("BLTU",(rs1,(rs2,imm))) + | Branch(BGEU(rs1,(rs2,imm))) => pSBtype 12 ("BGEU",(rs1,(rs2,imm))) + | Branch(JALR(rd,(rs1,imm))) => pItype 12 ("JALR",(rd,(rs1,imm))) + | Branch(JAL(rd,imm)) => pUJtype 20 ("JAL",(rd,imm)) + | ArithI(LUI(rd,imm)) => pUtype 20 ("LUI",(rd,imm)) + | ArithI(AUIPC(rd,imm)) => pUtype 20 ("AUIPC",(rd,imm)) + | ArithI(ADDI(rd,(rs1,imm))) => pItype 12 ("ADDI",(rd,(rs1,imm))) + | Shift(SLLI(rd,(rs1,imm))) => pItype 6 ("SLLI",(rd,(rs1,imm))) + | ArithI(SLTI(rd,(rs1,imm))) => pItype 12 ("SLTI",(rd,(rs1,imm))) + | ArithI(SLTIU(rd,(rs1,imm))) => pItype 12 ("SLTIU",(rd,(rs1,imm))) + | ArithI(XORI(rd,(rs1,imm))) => pItype 12 ("XORI",(rd,(rs1,imm))) + | Shift(SRLI(rd,(rs1,imm))) => pItype 6 ("SRLI",(rd,(rs1,imm))) + | Shift(SRAI(rd,(rs1,imm))) => pItype 6 ("SRAI",(rd,(rs1,imm))) + | ArithI(ORI(rd,(rs1,imm))) => pItype 12 ("ORI",(rd,(rs1,imm))) + | ArithI(ANDI(rd,(rs1,imm))) => pItype 12 ("ANDI",(rd,(rs1,imm))) + | ArithR(ADD(rd,(rs1,rs2))) => pRtype("ADD",(rd,(rs1,rs2))) + | ArithR(SUB(rd,(rs1,rs2))) => pRtype("SUB",(rd,(rs1,rs2))) + | Shift(SLL(rd,(rs1,rs2))) => pRtype("SLL",(rd,(rs1,rs2))) + | ArithR(SLT(rd,(rs1,rs2))) => pRtype("SLT",(rd,(rs1,rs2))) + | ArithR(SLTU(rd,(rs1,rs2))) => pRtype("SLTU",(rd,(rs1,rs2))) + | ArithR(XOR(rd,(rs1,rs2))) => pRtype("XOR",(rd,(rs1,rs2))) + | Shift(SRL(rd,(rs1,rs2))) => pRtype("SRL",(rd,(rs1,rs2))) + | Shift(SRA(rd,(rs1,rs2))) => pRtype("SRA",(rd,(rs1,rs2))) + | ArithR(OR(rd,(rs1,rs2))) => pRtype("OR",(rd,(rs1,rs2))) + | ArithR(AND(rd,(rs1,rs2))) => pRtype("AND",(rd,(rs1,rs2))) + | ArithI(ADDIW(rd,(rs1,imm))) => pItype 12 ("ADDIW",(rd,(rs1,imm))) + | Shift(SLLIW(rd,(rs1,imm))) => pItype 5 ("SLLIW",(rd,(rs1,imm))) + | Shift(SRLIW(rd,(rs1,imm))) => pItype 5 ("SRLIW",(rd,(rs1,imm))) + | Shift(SRAIW(rd,(rs1,imm))) => pItype 5 ("SRAIW",(rd,(rs1,imm))) + | ArithR(ADDW(rd,(rs1,rs2))) => pRtype("ADDW",(rd,(rs1,rs2))) + | ArithR(SUBW(rd,(rs1,rs2))) => pRtype("SUBW",(rd,(rs1,rs2))) + | Shift(SLLW(rd,(rs1,rs2))) => pRtype("SLLW",(rd,(rs1,rs2))) + | Shift(SRLW(rd,(rs1,rs2))) => pRtype("SRLW",(rd,(rs1,rs2))) + | Shift(SRAW(rd,(rs1,rs2))) => pRtype("SRAW",(rd,(rs1,rs2))) + | MulDiv(MUL(rd,(rs1,rs2))) => pRtype("MUL",(rd,(rs1,rs2))) + | MulDiv(MULH(rd,(rs1,rs2))) => pRtype("MULH",(rd,(rs1,rs2))) + | MulDiv(MULHSU(rd,(rs1,rs2))) => pRtype("MULHSU",(rd,(rs1,rs2))) + | MulDiv(MULHU(rd,(rs1,rs2))) => pRtype("MULHU",(rd,(rs1,rs2))) + | MulDiv(DIV(rd,(rs1,rs2))) => pRtype("DIV",(rd,(rs1,rs2))) + | MulDiv(DIVU(rd,(rs1,rs2))) => pRtype("DIVU",(rd,(rs1,rs2))) + | MulDiv(REM(rd,(rs1,rs2))) => pRtype("REM",(rd,(rs1,rs2))) + | MulDiv(REMU(rd,(rs1,rs2))) => pRtype("REMU",(rd,(rs1,rs2))) + | MulDiv(MULW(rd,(rs1,rs2))) => pRtype("MULW",(rd,(rs1,rs2))) + | MulDiv(DIVW(rd,(rs1,rs2))) => pRtype("DIVW",(rd,(rs1,rs2))) + | MulDiv(DIVUW(rd,(rs1,rs2))) => pRtype("DIVUW",(rd,(rs1,rs2))) + | MulDiv(REMW(rd,(rs1,rs2))) => pRtype("REMW",(rd,(rs1,rs2))) + | MulDiv(REMUW(rd,(rs1,rs2))) => pRtype("REMUW",(rd,(rs1,rs2))) + | Load(LB(rd,(rs1,imm))) => pItype 12 ("LB",(rd,(rs1,imm))) + | Load(LH(rd,(rs1,imm))) => pItype 12 ("LH",(rd,(rs1,imm))) + | Load(LW(rd,(rs1,imm))) => pItype 12 ("LW",(rd,(rs1,imm))) + | Load(LD(rd,(rs1,imm))) => pItype 12 ("LD",(rd,(rs1,imm))) + | Load(LBU(rd,(rs1,imm))) => pItype 12 ("LBU",(rd,(rs1,imm))) + | Load(LHU(rd,(rs1,imm))) => pItype 12 ("LHU",(rd,(rs1,imm))) + | Load(LWU(rd,(rs1,imm))) => pItype 12 ("LWU",(rd,(rs1,imm))) + | Store(SB(rs1,(rs2,imm))) => pStype 12 ("SB",(rs1,(rs2,imm))) + | Store(SH(rs1,(rs2,imm))) => pStype 12 ("SH",(rs1,(rs2,imm))) + | Store(SW(rs1,(rs2,imm))) => pStype 12 ("SW",(rs1,(rs2,imm))) + | Store(SD(rs1,(rs2,imm))) => pStype 12 ("SD",(rs1,(rs2,imm))) + | FENCE(rd,(rs1,(pred,succ))) => pN0type "FENCE" + | FENCE_I(rd,(rs1,imm)) => pN0type "FENCE.I" + | FArith(FADD_S(rd,(rs1,(rs2,frm)))) => + pFRtype("FADD.S",(rd,(rs1,rs2))) + | FArith(FSUB_S(rd,(rs1,(rs2,frm)))) => + pFRtype("FSUB.S",(rd,(rs1,rs2))) + | FArith(FMUL_S(rd,(rs1,(rs2,frm)))) => + pFRtype("FMUL.S",(rd,(rs1,rs2))) + | FArith(FDIV_S(rd,(rs1,(rs2,frm)))) => + pFRtype("FDIV.S",(rd,(rs1,rs2))) + | FArith(FSQRT_S(rd,(rs,frm))) => pFR1type("FSQRT.S",(rd,rs)) + | FArith(FMIN_S(rd,(rs1,rs2))) => pFRtype("FMIN.S",(rd,(rs1,rs2))) + | FArith(FMAX_S(rd,(rs1,rs2))) => pFRtype("FMAX.S",(rd,(rs1,rs2))) + | FArith(FEQ_S(rd,(rs1,rs2))) => pFRtype("FEQ.S",(rd,(rs1,rs2))) + | FArith(FLT_S(rd,(rs1,rs2))) => pFRtype("FLT.S",(rd,(rs1,rs2))) + | FArith(FLE_S(rd,(rs1,rs2))) => pFRtype("FLE.S",(rd,(rs1,rs2))) + | FArith(FMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FMADD.S",(rd,(rs1,(rs2,rs3)))) + | FArith(FMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FMSUB.S",(rd,(rs1,(rs2,rs3)))) + | FArith(FNMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FNMADD.S",(rd,(rs1,(rs2,rs3)))) + | FArith(FNMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FNMSUB.S",(rd,(rs1,(rs2,rs3)))) + | FArith(FADD_D(rd,(rs1,(rs2,frm)))) => + pFRtype("FADD.D",(rd,(rs1,rs2))) + | FArith(FSUB_D(rd,(rs1,(rs2,frm)))) => + pFRtype("FSUB.D",(rd,(rs1,rs2))) + | FArith(FMUL_D(rd,(rs1,(rs2,frm)))) => + pFRtype("FMUL.D",(rd,(rs1,rs2))) + | FArith(FDIV_D(rd,(rs1,(rs2,frm)))) => + pFRtype("FDIV.D",(rd,(rs1,rs2))) + | FArith(FSQRT_D(rd,(rs,frm))) => pFR1type("FSQRT.D",(rd,rs)) + | FArith(FMIN_D(rd,(rs1,rs2))) => pFRtype("FMIN.D",(rd,(rs1,rs2))) + | FArith(FMAX_D(rd,(rs1,rs2))) => pFRtype("FMAX.D",(rd,(rs1,rs2))) + | FArith(FEQ_D(rd,(rs1,rs2))) => pFRtype("FEQ.D",(rd,(rs1,rs2))) + | FArith(FLT_D(rd,(rs1,rs2))) => pFRtype("FLT.D",(rd,(rs1,rs2))) + | FArith(FLE_D(rd,(rs1,rs2))) => pFRtype("FLE.D",(rd,(rs1,rs2))) + | FArith(FMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FMADD.D",(rd,(rs1,(rs2,rs3)))) + | FArith(FMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FMSUB.D",(rd,(rs1,(rs2,rs3)))) + | FArith(FNMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FNMADD.D",(rd,(rs1,(rs2,rs3)))) + | FArith(FNMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => + pFR3type("FNMSUB.D",(rd,(rs1,(rs2,rs3)))) + | FConv(FSGNJ_S(rd,(rs1,rs2))) => pFRtype("FSGNJ.S",(rd,(rs1,rs2))) + | FConv(FSGNJN_S(rd,(rs1,rs2))) => pFRtype("FSGNJN.S",(rd,(rs1,rs2))) + | FConv(FSGNJX_S(rd,(rs1,rs2))) => pFRtype("FSGNJX.S",(rd,(rs1,rs2))) + | FConv(FCVT_W_S(rd,(rs,frm))) => pCIFtype("FCVT.W.S",(rd,rs)) + | FConv(FCVT_WU_S(rd,(rs,frm))) => pCIFtype("FCVT.WU.S",(rd,rs)) + | FConv(FMV_X_S(rd,rs)) => pCIFtype("FMV.X.S",(rd,rs)) + | FConv(FCLASS_S(rd,rs)) => pCIFtype("FCLASS.S",(rd,rs)) + | FConv(FCVT_S_W(rd,(rs,frm))) => pCFItype("FCVT.S.W",(rd,rs)) + | FConv(FCVT_S_WU(rd,(rs,frm))) => pCFItype("FCVT.S.WU",(rd,rs)) + | FConv(FMV_S_X(rd,rs)) => pCFItype("FMV.S.X",(rd,rs)) + | FConv(FSGNJ_D(rd,(rs1,rs2))) => pFRtype("FSGNJ.D",(rd,(rs1,rs2))) + | FConv(FSGNJN_D(rd,(rs1,rs2))) => pFRtype("FSGNJN.D",(rd,(rs1,rs2))) + | FConv(FSGNJX_D(rd,(rs1,rs2))) => pFRtype("FSGNJX.D",(rd,(rs1,rs2))) + | FConv(FCVT_W_D(rd,(rs,frm))) => pCIFtype("FCVT.W.D",(rd,rs)) + | FConv(FCVT_WU_D(rd,(rs,frm))) => pCIFtype("FCVT.WU.D",(rd,rs)) + | FConv(FCLASS_D(rd,rs)) => pCIFtype("FCLASS.D",(rd,rs)) + | FConv(FCVT_D_W(rd,(rs,frm))) => pCFItype("FCVT.D.W",(rd,rs)) + | FConv(FCVT_D_WU(rd,(rs,frm))) => pCFItype("FCVT.D.WU",(rd,rs)) + | FConv(FCVT_L_S(rd,(rs,frm))) => pCIFtype("FCVT.L.S",(rd,rs)) + | FConv(FCVT_LU_S(rd,(rs,frm))) => pCIFtype("FCVT.LU.S",(rd,rs)) + | FConv(FCVT_S_L(rd,(rs,frm))) => pCFItype("FCVT.S.L",(rd,rs)) + | FConv(FCVT_S_LU(rd,(rs,frm))) => pCFItype("FCVT.S.LU",(rd,rs)) + | FConv(FCVT_L_D(rd,(rs,frm))) => pCIFtype("FCVT.L.D",(rd,rs)) + | FConv(FCVT_LU_D(rd,(rs,frm))) => pCIFtype("FCVT.LU.D",(rd,rs)) + | FConv(FMV_X_D(rd,rs)) => pCIFtype("FMV.X.D",(rd,rs)) + | FConv(FCVT_D_L(rd,(rs,frm))) => pCFItype("FCVT.D.L",(rd,rs)) + | FConv(FCVT_D_LU(rd,(rs,frm))) => pCFItype("FCVT.D.LU",(rd,rs)) + | FConv(FMV_D_X(rd,rs)) => pCFItype("FMV.D.X",(rd,rs)) + | FConv(FCVT_D_S(rd,(rs,frm))) => pCFItype("FCVT.D.S",(rd,rs)) + | FConv(FCVT_S_D(rd,(rs,frm))) => pCFItype("FCVT.S.D",(rd,rs)) + | FPLoad(FLW(rd,(rs1,imm))) => pFItype 12 ("FLW",(rd,(rs1,imm))) + | FPLoad(FLD(rd,(rs1,imm))) => pFItype 12 ("FLD",(rd,(rs1,imm))) + | FPStore(FSW(rs1,(rs2,imm))) => pFStype 12 ("FSW",(rs1,(rs2,imm))) + | FPStore(FSD(rs1,(rs2,imm))) => pFStype 12 ("FSD",(rs1,(rs2,imm))) + | AMO(LR_W(aq,(rl,(rd,rs1)))) => pLRtype("LR.W",(aq,(rl,(rd,rs1)))) + | AMO(LR_D(aq,(rl,(rd,rs1)))) => pLRtype("LR.D",(aq,(rl,(rd,rs1)))) + | AMO(SC_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("SC.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(SC_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("SC.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOSWAP_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOSWAP.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOADD_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOADD.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOXOR_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOXOR.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOAND_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOAND.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOOR_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOOR.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMIN_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMIN.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMAX_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMAX.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMINU_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMINU.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMAXU_W(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMAXU.W",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOSWAP_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOSWAP.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOADD_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOADD.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOXOR_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOXOR.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOAND_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOAND.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOOR_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOOR.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMIN_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMIN.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMAX_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMAX.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMINU_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMINU.D",(aq,(rl,(rd,(rs1,rs2))))) + | AMO(AMOMAXU_D(aq,(rl,(rd,(rs1,rs2))))) => + pARtype("AMOMAXU.D",(aq,(rl,(rd,(rs1,rs2))))) + | System ECALL => pN0type "ECALL" + | System EBREAK => pN0type "EBREAK" + | System ERET => pN0type "ERET" + | System MRTS => pN0type "MRTS" + | System WFI => pN0type "WFI" + | System(CSRRW(rd,(rs1,csr))) => pCSRtype("CSRRW",(rd,(rs1,csr))) + | System(CSRRS(rd,(rs1,csr))) => pCSRtype("CSRRS",(rd,(rs1,csr))) + | System(CSRRC(rd,(rs1,csr))) => pCSRtype("CSRRC",(rd,(rs1,csr))) + | System(CSRRWI(rd,(imm,csr))) => pCSRItype 5 ("CSRRWI",(rd,(imm,csr))) + | System(CSRRSI(rd,(imm,csr))) => pCSRItype 5 ("CSRRSI",(rd,(imm,csr))) + | System(CSRRCI(rd,(imm,csr))) => pCSRItype 5 ("CSRRCI",(rd,(imm,csr))) + | System(SFENCE_VM rs1) => pN1type("SFENCE.VM",rs1) + | UnknownInstruction => pN0type "UNKNOWN" + | Internal(FETCH_MISALIGNED _) => pN0type "FETCH_MISALIGNED" + | Internal(FETCH_FAULT _) => pN0type "FETCH_FAULT"; + +fun Rtype (o',(f3,(rd,(rs1,(rs2,f7))))) = + BitsN.concat[f7,rs2,rs1,f3,rd,o']; + +fun R4type (o',(f3,(rd,(rs1,(rs2,(rs3,f2)))))) = + BitsN.concat[rs3,f2,rs2,rs1,f3,rd,o']; + +fun Itype (o',(f3,(rd,(rs1,imm)))) = BitsN.concat[imm,rs1,f3,rd,o']; + +fun Stype (o',(f3,(rs1,(rs2,imm)))) = + BitsN.concat[BitsN.bits(11,5) imm,rs2,rs1,f3,BitsN.bits(4,0) imm,o']; + +fun SBtype (o',(f3,(rs1,(rs2,imm)))) = + BitsN.concat + [BitsN.fromBit(BitsN.bit(imm,11)),BitsN.bits(9,4) imm,rs2,rs1,f3, + BitsN.bits(3,0) imm,BitsN.fromBit(BitsN.bit(imm,10)),o']; + +fun Utype (o',(rd,imm)) = BitsN.concat[imm,rd,o']; + +fun UJtype (o',(rd,imm)) = + BitsN.concat + [BitsN.fromBit(BitsN.bit(imm,19)),BitsN.bits(9,0) imm, + BitsN.fromBit(BitsN.bit(imm,10)),BitsN.bits(18,11) imm,rd,o']; + +fun opc code = BitsN.@@(BitsN.bits(4,0) code,BitsN.B(0x3,2)); + +fun amofunc (code,(aq,rl)) = BitsN.concat[code,aq,rl]; + +fun Encode i = + case i of + Branch(BEQ(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x0,3),(rs1,(rs2,imm)))) + | Branch(BNE(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x1,3),(rs1,(rs2,imm)))) + | Branch(BLT(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x4,3),(rs1,(rs2,imm)))) + | Branch(BGE(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x5,3),(rs1,(rs2,imm)))) + | Branch(BLTU(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x6,3),(rs1,(rs2,imm)))) + | Branch(BGEU(rs1,(rs2,imm))) => + SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x7,3),(rs1,(rs2,imm)))) + | Branch(JALR(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x19,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) + | Branch(JAL(rd,imm)) => UJtype(opc(BitsN.B(0x1B,8)),(rd,imm)) + | ArithI(LUI(rd,imm)) => Utype(opc(BitsN.B(0xD,8)),(rd,imm)) + | ArithI(AUIPC(rd,imm)) => Utype(opc(BitsN.B(0x5,8)),(rd,imm)) + | ArithI(ADDI(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) + | Shift(SLLI(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x4,8)), + (BitsN.B(0x1,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,6),imm))))) + | ArithI(SLTI(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) + | ArithI(SLTIU(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) + | ArithI(XORI(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x4,3),(rd,(rs1,imm)))) + | Shift(SRLI(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x4,8)), + (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,6),imm))))) + | Shift(SRAI(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x4,8)), + (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x10,6),imm))))) + | ArithI(ORI(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x6,3),(rd,(rs1,imm)))) + | ArithI(ANDI(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x7,3),(rd,(rs1,imm)))) + | ArithR(ADD(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(SUB(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) + | Shift(SLL(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(SLT(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(SLTU(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(XOR(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | Shift(SRL(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | Shift(SRA(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) + | ArithR(OR(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(AND(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithI(ADDIW(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x6,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) + | Shift(SLLIW(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x6,8)), + (BitsN.B(0x1,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,7),imm))))) + | Shift(SRLIW(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x6,8)), + (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,7),imm))))) + | Shift(SRAIW(rd,(rs1,imm))) => + Itype + (opc(BitsN.B(0x6,8)), + (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x20,7),imm))))) + | ArithR(ADDW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | ArithR(SUBW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) + | Shift(SLLW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | Shift(SRLW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | Shift(SRAW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) + | MulDiv(MUL(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(MULH(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(MULHSU(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(MULHU(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(DIV(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(DIVU(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(REM(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(REMU(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xC,8)), + (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(MULW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(DIVW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(DIVUW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(REMW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | MulDiv(REMUW(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0xE,8)), + (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | Load(LB(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) + | Load(LH(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x1,3),(rd,(rs1,imm)))) + | Load(LW(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) + | Load(LD(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) + | Load(LBU(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x4,3),(rd,(rs1,imm)))) + | Load(LHU(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x5,3),(rd,(rs1,imm)))) + | Load(LWU(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x6,3),(rd,(rs1,imm)))) + | Store(SB(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x0,3),(rs1,(rs2,imm)))) + | Store(SH(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x1,3),(rs1,(rs2,imm)))) + | Store(SW(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x2,3),(rs1,(rs2,imm)))) + | Store(SD(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x3,3),(rs1,(rs2,imm)))) + | FENCE(rd,(rs1,(pred,succ))) => + Itype + (opc(BitsN.B(0x3,8)), + (BitsN.B(0x0,3),(rd,(rs1,BitsN.concat[BitsN.B(0x0,4),pred,succ])))) + | FENCE_I(rd,(rs1,imm)) => + Itype(opc(BitsN.B(0x3,8)),(BitsN.B(0x1,3),(rd,(rs1,imm)))) + | FArith(FADD_S(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) + | FArith(FSUB_S(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x4,7)))))) + | FArith(FMUL_S(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x8,7)))))) + | FArith(FDIV_S(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0xC,7)))))) + | FArith(FSQRT_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x2C,7)))))) + | FArith(FMIN_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x14,7)))))) + | FArith(FMAX_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x14,7)))))) + | FArith(FEQ_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) + | FArith(FLT_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) + | FArith(FLE_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) + | FArith(FADD_D(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) + | FArith(FSUB_D(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x5,7)))))) + | FArith(FMUL_D(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x9,7)))))) + | FArith(FDIV_D(rd,(rs1,(rs2,frm)))) => + Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0xD,7)))))) + | FArith(FSQRT_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x2D,7)))))) + | FArith(FMIN_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x15,7)))))) + | FArith(FMAX_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x15,7)))))) + | FArith(FEQ_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) + | FArith(FLT_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) + | FArith(FLE_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) + | FPLoad(FLW(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x1,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) + | FPLoad(FLD(rd,(rs1,imm))) => + Itype(opc(BitsN.B(0x1,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) + | FPStore(FSW(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x9,8)),(BitsN.B(0x2,3),(rs1,(rs2,imm)))) + | FPStore(FSD(rs1,(rs2,imm))) => + Stype(opc(BitsN.B(0x9,8)),(BitsN.B(0x3,3),(rs1,(rs2,imm)))) + | FArith(FMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x10,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) + | FArith(FMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x11,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) + | FArith(FNMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x12,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) + | FArith(FNMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x13,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) + | FArith(FMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x10,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) + | FArith(FMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x11,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) + | FArith(FNMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x12,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) + | FArith(FNMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => + R4type + (opc(BitsN.B(0x13,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) + | FConv(FSGNJ_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) + | FConv(FSGNJN_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) + | FConv(FSGNJX_S(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) + | FConv(FCVT_W_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x60,7)))))) + | FConv(FCVT_WU_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x60,7)))))) + | FConv(FMV_X_S(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x70,7)))))) + | FConv(FCLASS_S(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x70,7)))))) + | FConv(FCVT_S_W(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x68,7)))))) + | FConv(FCVT_S_WU(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x68,7)))))) + | FConv(FMV_S_X(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x78,7)))))) + | FConv(FSGNJ_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) + | FConv(FSGNJN_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) + | FConv(FSGNJX_D(rd,(rs1,rs2))) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) + | FConv(FCVT_W_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x61,7)))))) + | FConv(FCVT_WU_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x61,7)))))) + | FConv(FCLASS_D(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x1,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x71,7)))))) + | FConv(FCVT_D_W(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x69,7)))))) + | FConv(FCVT_D_WU(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x69,7)))))) + | FConv(FCVT_S_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x20,7)))))) + | FConv(FCVT_D_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x21,7)))))) + | FConv(FCVT_L_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x60,7)))))) + | FConv(FCVT_LU_S(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x60,7)))))) + | FConv(FCVT_S_L(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x68,7)))))) + | FConv(FCVT_S_LU(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x68,7)))))) + | FConv(FCVT_L_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x61,7)))))) + | FConv(FCVT_LU_D(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x61,7)))))) + | FConv(FMV_X_D(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x71,7)))))) + | FConv(FCVT_D_L(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x69,7)))))) + | FConv(FCVT_D_LU(rd,(rs,frm))) => + Rtype + (opc(BitsN.B(0x14,8)), + (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x69,7)))))) + | FConv(FMV_D_X(rd,rs)) => + Rtype + (opc(BitsN.B(0x14,8)), + (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x79,7)))))) + | AMO(LR_W(aq,(rl,(rd,rs1)))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3), + (rd,(rs1,(BitsN.B(0x0,5),amofunc(BitsN.B(0x2,5),(aq,rl))))))) + | AMO(LR_D(aq,(rl,(rd,rs1)))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3), + (rd,(rs1,(BitsN.B(0x0,5),amofunc(BitsN.B(0x2,5),(aq,rl))))))) + | AMO(SC_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x3,5),(aq,rl))))))) + | AMO(SC_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x2,5),(aq,rl))))))) + | AMO(AMOSWAP_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1,5),(aq,rl))))))) + | AMO(AMOADD_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x0,5),(aq,rl))))))) + | AMO(AMOXOR_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x4,5),(aq,rl))))))) + | AMO(AMOAND_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0xC,5),(aq,rl))))))) + | AMO(AMOOR_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x8,5),(aq,rl))))))) + | AMO(AMOMIN_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x10,5),(aq,rl))))))) + | AMO(AMOMAX_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x14,5),(aq,rl))))))) + | AMO(AMOMINU_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x18,5),(aq,rl))))))) + | AMO(AMOMAXU_W(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1C,5),(aq,rl))))))) + | AMO(AMOSWAP_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1,5),(aq,rl))))))) + | AMO(AMOADD_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x0,5),(aq,rl))))))) + | AMO(AMOXOR_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x4,5),(aq,rl))))))) + | AMO(AMOAND_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0xC,5),(aq,rl))))))) + | AMO(AMOOR_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x8,5),(aq,rl))))))) + | AMO(AMOMIN_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x10,5),(aq,rl))))))) + | AMO(AMOMAX_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x14,5),(aq,rl))))))) + | AMO(AMOMINU_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x18,5),(aq,rl))))))) + | AMO(AMOMAXU_D(aq,(rl,(rd,(rs1,rs2))))) => + Rtype + (opc(BitsN.B(0xB,8)), + (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1C,5),(aq,rl))))))) + | System ECALL => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,12))))) + | System EBREAK => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,12))))) + | System ERET => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3), + (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x100,12))))) + | System MRTS => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3), + (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x305,12))))) + | System WFI => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3), + (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x102,12))))) + | System(SFENCE_VM rs1) => + Itype + (opc(BitsN.B(0x1C,8)), + (BitsN.B(0x0,3),(BitsN.B(0x0,5),(rs1,BitsN.B(0x101,12))))) + | System(CSRRW(rd,(rs1,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x1,3),(rd,(rs1,csr)))) + | System(CSRRS(rd,(rs1,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x2,3),(rd,(rs1,csr)))) + | System(CSRRC(rd,(rs1,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x3,3),(rd,(rs1,csr)))) + | System(CSRRWI(rd,(imm,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x5,3),(rd,(imm,csr)))) + | System(CSRRSI(rd,(imm,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x6,3),(rd,(imm,csr)))) + | System(CSRRCI(rd,(imm,csr))) => + Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x7,3),(rd,(imm,csr)))) + | UnknownInstruction => BitsN.B(0x0,32) + | Internal(FETCH_MISALIGNED _) => BitsN.B(0x0,32) + | Internal(FETCH_FAULT _) => BitsN.B(0x0,32); + +fun log_instruction (w,inst) = + String.concat + ["instr ",BitsN.toHexString (!procID)," ", + Nat.toString + (BitsN.toNat(Map.lookup((!c_instret),BitsN.toNat (!procID)))), + " 0x",hex64(PC ())," : ",hex32 w," ",instructionToString inst]; + +fun exitCode () = BitsN.toNat(ExitCode ()); + +val CYCLES_PER_TIMER_TICK = 200 + +fun tickClock () = + let + val cycles = + BitsN.+ + (Map.lookup((!c_cycles),BitsN.toNat (!procID)),BitsN.B(0x1,64)) + in + ( c_cycles := (Map.update((!c_cycles),BitsN.toNat (!procID),cycles)) + ; clock := (BitsN.div(cycles,BitsN.fromNat(CYCLES_PER_TIMER_TICK,64))) + ) + end; + +fun incrInstret () = + c_instret := + (Map.update + ((!c_instret),BitsN.toNat (!procID), + BitsN.+ + (Map.lookup((!c_instret),BitsN.toNat (!procID)),BitsN.B(0x1,64)))); + +fun checkTimers () = + ( if BitsN.>+ + ((!clock), + BitsN.+ + (#mtimecmp((MCSR ()) : MachineCSR), + #mtime_delta((MCSR ()) : MachineCSR))) + then let + val x = MCSR () + val x0 = #mip(x : MachineCSR) + in + write'MCSR(MachineCSR_mip_rupd(x,mip_MTIP_rupd(x0,true))) + end + else () + ; if BitsN.>+ + ((!clock), + BitsN.+ + (#stimecmp((SCSR ()) : SupervisorCSR), + #stime_delta((SCSR ()) : SupervisorCSR))) + then let + val x = MCSR () + val x0 = #mip(x : MachineCSR) + in + write'MCSR(MachineCSR_mip_rupd(x,mip_STIP_rupd(x0,true))) + end + else () + ); + +fun Next () = + ( clear_logs () + ; if not((#mtohost((MCSR ()) : MachineCSR)) = (BitsN.B(0x0,64))) + then ( log := + ((0,log_tohost(#mtohost((MCSR ()) : MachineCSR))) :: (!log)) + ; if BitsN.bit(#mtohost((MCSR ()) : MachineCSR),0) + then ( done := true + ; write'ExitCode + (BitsN.>>(#mtohost((MCSR ()) : MachineCSR),1)) + ) + else let + val x = MCSR () + in + write'MCSR(MachineCSR_mtohost_rupd(x,BitsN.B(0x0,64))) + end + ) + else () + ; case Fetch () of + F_Result w => + let + val inst = Decode w + in + ( log := ((1,log_instruction(w,inst)) :: (!log)); Run inst ) + end + | F_Error inst => + ( log := ((1,log_instruction(BitsN.B(0x0,32),inst)) :: (!log)) + ; Run inst + ) + ; checkTimers () + ; case (NextFetch (),checkInterrupts ()) of + (NONE,NONE) => + ( incrInstret (); write'PC(BitsN.+(PC (),BitsN.B(0x4,64))) ) + | (NONE,Option.SOME(i,p)) => + ( incrInstret () + ; takeTrap + (true, + (interruptIndex i,(BitsN.+(PC (),BitsN.B(0x4,64)),(NONE,p)))) + ) + | (Option.SOME(BranchTo addr),_) => + ( incrInstret (); write'NextFetch NONE; write'PC addr ) + | (Option.SOME Ereturn,_) => + ( incrInstret () + ; write'NextFetch NONE + ; write'PC(curEPC ()) + ; let + val from = curPrivilege () + in + ( let + val x = MCSR () + in + write'MCSR + (MachineCSR_mstatus_rupd + (x,popPrivilegeStack(#mstatus((MCSR ()) : MachineCSR)))) + end + ; let + val to = curPrivilege () + in + log := + ((1, + String.concat + ["exception return from ",privName from," to ", + privName to]) + :: + (!log)) + end + ) + end + ) + | (Option.SOME(Trap t),_) => + ( write'NextFetch NONE + ; takeTrap + (false, + (excCode(#trap(t : SynchronousTrap)), + (PC (),(#badaddr(t : SynchronousTrap),Machine)))) + ) + | (Option.SOME Mrts,_) => + ( incrInstret () + ; write'NextFetch NONE + ; write'PC(#stvec((SCSR ()) : SupervisorCSR)) + ) + ; tickClock () + ); + +fun initIdent arch = + ( let + val x = MCSR () + val x0 = #mcpuid(x : MachineCSR) + in + write'MCSR + (MachineCSR_mcpuid_rupd(x,mcpuid_ArchBase_rupd(x0,archBase arch))) + end + ; let + val x = MCSR () + val x0 = #mcpuid(x : MachineCSR) + in + write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_U_rupd(x0,true))) + end + ; let + val x = MCSR () + val x0 = #mcpuid(x : MachineCSR) + in + write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_S_rupd(x0,true))) + end + ; let + val x = MCSR () + val x0 = #mcpuid(x : MachineCSR) + in + write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_M_rupd(x0,true))) + end + ; let + val x = MCSR () + val x0 = #mcpuid(x : MachineCSR) + in + write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_I_rupd(x0,true))) + end + ; let + val x = MCSR () + val x0 = #mimpid(x : MachineCSR) + in + write'MCSR + (MachineCSR_mimpid_rupd + (x,mimpid_RVSource_rupd(x0,BitsN.B(0x8000,16)))) + end + ; let + val x = MCSR () + val x0 = #mimpid(x : MachineCSR) + in + write'MCSR + (MachineCSR_mimpid_rupd(x,mimpid_RVImpl_rupd(x0,BitsN.B(0x0,48)))) + end + ); + +fun initMachine hartid = + ( let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd(x,mstatus_VM_rupd(x0,vmMode Mbare))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd + (x,mstatus_MPRV_rupd(x0,privLevel Machine))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MIE_rupd(x0,false))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd + (x,mstatus_MFS_rupd(x0,ext_status Initial))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR + (MachineCSR_mstatus_rupd(x,mstatus_MXS_rupd(x0,ext_status Off))) + end + ; let + val x = MCSR () + val x0 = #mstatus(x : MachineCSR) + in + write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,false))) + end + ; let + val x = MCSR () + in + write'MCSR(MachineCSR_mhartid_rupd(x,BitsN.zeroExtend 64 hartid)) + end + ; let + val x = MCSR () + in + write'MCSR + (MachineCSR_mtvec_rupd(x,BitsN.zeroExtend 64 (BitsN.B(0x100,16)))) + end + ); + +fun initRegs pc = + ( L3.for + (0,31, + fn i => + let + val x = BitsN.fromNat(i,5) + in + write'gpr(BitsN.B(0x0,64),x) + end) + ; L3.for + (0,31, + fn i => + let + val x = BitsN.fromNat(i,5) + in + write'fpr(BitsN.B(0x0,64),x) + end) + ; write'PC(BitsN.fromNat(pc,64)) + ; write'NextFetch NONE + ; done := false + ); + +end \ No newline at end of file diff --git a/src/shared/l3-machine-code/riscv/model/riscvLib.sig b/src/shared/l3-machine-code/riscv/model/riscvLib.sig new file mode 100644 index 000000000..6e7269db2 --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/riscvLib.sig @@ -0,0 +1,5 @@ +(* riscvLib - generated by L3 - Mon Jun 01 11:52:39 2020 *) +signature riscvLib = +sig + val riscv_compset: Thm.thm list -> computeLib.compset +end \ No newline at end of file diff --git a/src/shared/l3-machine-code/riscv/model/riscvLib.sml b/src/shared/l3-machine-code/riscv/model/riscvLib.sml new file mode 100644 index 000000000..40e42f3f3 --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/riscvLib.sml @@ -0,0 +1,9 @@ +(* riscvLib - generated by L3 - Mon Jun 01 11:52:39 2020 *) +structure riscvLib :> riscvLib = +struct +open HolKernel boolLib bossLib +open utilsLib riscvTheory +val () = (numLib.prefer_num (); wordsLib.prefer_word ()) +fun riscv_compset thms = + utilsLib.theory_compset (thms, riscvTheory.inventory) +end \ No newline at end of file diff --git a/src/shared/l3-machine-code/riscv/model/riscvScript.sml b/src/shared/l3-machine-code/riscv/model/riscvScript.sml new file mode 100644 index 000000000..6559814bd --- /dev/null +++ b/src/shared/l3-machine-code/riscv/model/riscvScript.sml @@ -0,0 +1,21999 @@ +(* riscvScript.sml - generated by L3 - Mon Jun 01 11:52:39 2020 *) +open HolKernel boolLib bossLib Import + +val () = Import.start "riscv" + +val _ = Construct [("rawInstType",[("Half",[F16]),("Word",[F32])])] +; +val _ = Construct [("accessType",[("Read",[]),("Write",[])])] +; +val _ = Construct [("fetchType",[("Instruction",[]),("Data",[])])] +; +val _ = Construct + [("Architecture",[("RV32I",[]),("RV64I",[]),("RV128I",[])])] +; +val _ = Construct + [("Privilege", + [("User",[]),("Supervisor",[]),("Hypervisor",[]),("Machine",[])])] +; +val _ = Construct + [("VM_Mode", + [("Mbare",[]),("Mbb",[]),("Mbbid",[]),("Sv32",[]),("Sv39",[]), + ("Sv48",[]),("Sv57",[]),("Sv64",[])])] +; +val _ = Construct + [("ExtStatus",[("Off",[]),("Initial",[]),("Clean",[]),("Dirty",[])])] +; +val _ = Construct [("Interrupt",[("Software",[]),("Timer",[])])] +; +val _ = Construct + [("ExceptionType", + [("Fetch_Misaligned",[]),("Fetch_Fault",[]),("Illegal_Instr",[]), + ("Breakpoint",[]),("Load_Fault",[]),("AMO_Misaligned",[]), + ("Store_AMO_Fault",[]),("UMode_Env_Call",[]),("SMode_Env_Call",[]), + ("HMode_Env_Call",[]),("MMode_Env_Call",[])])] +; +val _ = Record + ("mcpuid", + [("ArchBase",FTy 2),("I",bTy),("M",bTy),("S",bTy),("U",bTy), + ("mcpuid'rst",FTy 58)]) +; +val _ = Record ("mimpid",[("RVImpl",FTy 48),("RVSource",F16)]) +; +val _ = Record + ("mstatus", + [("MFS",FTy 2),("MIE",bTy),("MIE1",bTy),("MIE2",bTy),("MIE3",bTy), + ("MMPRV",bTy),("MPRV",FTy 2),("MPRV1",FTy 2),("MPRV2",FTy 2), + ("MPRV3",FTy 2),("MSD",bTy),("MXS",FTy 2),("VM",FTy 5), + ("mstatus'rst",FTy 41)]) +; +val _ = Record ("mtdeleg",[("Exc_deleg",F16),("Intr_deleg",FTy 48)]) +; +val _ = Record + ("mip", + [("HSIP",bTy),("HTIP",bTy),("MSIP",bTy),("MTIP",bTy),("SSIP",bTy), + ("STIP",bTy),("mip'rst",FTy 58)]) +; +val _ = Record + ("mie", + [("HSIE",bTy),("HTIE",bTy),("MSIE",bTy),("MTIE",bTy),("SSIE",bTy), + ("STIE",bTy),("mie'rst",FTy 58)]) +; +val _ = Record ("mcause",[("EC",F4),("Int",bTy),("mcause'rst",FTy 59)]) +; +val _ = Record + ("MachineCSR", + [("mbadaddr",F64),("mbase",F64),("mbound",F64),("mcause",CTy"mcause"), + ("mcpuid",CTy"mcpuid"),("mdbase",F64),("mdbound",F64),("mepc",F64), + ("mfromhost",F64),("mhartid",F64),("mibase",F64),("mibound",F64), + ("mie",CTy"mie"),("mimpid",CTy"mimpid"),("mip",CTy"mip"), + ("mscratch",F64),("mstatus",CTy"mstatus"),("mtdeleg",CTy"mtdeleg"), + ("mtime_delta",F64),("mtimecmp",F64),("mtohost",F64),("mtvec",F64)]) +; +val _ = Record + ("HypervisorCSR", + [("hbadaddr",F64),("hcause",CTy"mcause"),("hepc",F64),("hscratch",F64), + ("hstatus",CTy"mstatus"),("htdeleg",CTy"mtdeleg"),("htime_delta",F64), + ("htimecmp",F64),("htvec",F64)]) +; +val _ = Record + ("sstatus", + [("SFS",FTy 2),("SIE",bTy),("SMPRV",bTy),("SPIE",bTy),("SPS",bTy), + ("SSD",bTy),("SXS",FTy 2),("sstatus'rst",FTy 55)]) +; +val _ = Record ("sip",[("SSIP",bTy),("STIP",bTy),("sip'rst",FTy 62)]) +; +val _ = Record ("sie",[("SSIE",bTy),("STIE",bTy),("sie'rst",FTy 62)]) +; +val _ = Record + ("SupervisorCSR", + [("sasid",F64),("sbadaddr",F64),("scause",CTy"mcause"),("sepc",F64), + ("sptbr",F64),("sscratch",F64),("stime_delta",F64),("stimecmp",F64), + ("stvec",F64)]) +; +val _ = Record + ("FPCSR", + [("DZ",bTy),("FRM",FTy 3),("NV",bTy),("NX",bTy),("OF",bTy),("UF",bTy), + ("fpcsr'rst",FTy 24)]) +; +val _ = Record + ("UserCSR", + [("cycle_delta",F64),("fpcsr",CTy"FPCSR"),("instret_delta",F64), + ("time_delta",F64)]) +; +val _ = Record + ("SynchronousTrap",[("badaddr",OTy F64),("trap",CTy"ExceptionType")]) +; +val _ = Construct + [("TransferControl", + [("BranchTo",[F64]),("Ereturn",[]),("Mrts",[]), + ("Trap",[CTy"SynchronousTrap"])])] +; +val _ = Construct + [("Rounding", + [("RNE",[]),("RTZ",[]),("RDN",[]),("RUP",[]),("RMM",[]),("RDYN",[])])] +; +val _ = Record + ("StateDelta", + [("addr",OTy F64),("data1",OTy F64),("data2",OTy F64), + ("exc_taken",bTy),("fetch_exc",bTy),("fp_data",OTy F64),("pc",F64), + ("rinstr",CTy"rawInstType"),("st_width",OTy F32)]) +; +val _ = Record + ("SV_PTE", + [("PTE_D",bTy),("PTE_PPNi",FTy 38),("PTE_R",bTy),("PTE_SW",FTy 3), + ("PTE_T",F4),("PTE_V",bTy),("sv_pte'rst",F16)]) +; +val _ = Record + ("SV_Vaddr", + [("Sv_PgOfs",FTy 12),("Sv_VPNi",FTy 36),("sv_vaddr'rst",F16)]) +; +val _ = Record + ("TLBEntry", + [("age",F64),("asid",FTy 6),("global",bTy),("pAddr",F64), + ("pte",CTy"SV_PTE"),("pteAddr",F64),("vAddr",F64),("vAddrMask",F64), + ("vMatchMask",F64)]) +; +val _ = Construct + [("Internal",[("FETCH_FAULT",[F64]),("FETCH_MISALIGNED",[F64])])] +; +val _ = Construct + [("System", + [("CSRRC",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("CSRRCI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("CSRRS",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("CSRRSI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("CSRRW",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("CSRRWI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]),("EBREAK",[]),("ECALL",[]), + ("ERET",[]),("MRTS",[]),("SFENCE_VM",[FTy 5]),("WFI",[])])] +; +val _ = Construct + [("FConv", + [("FCLASS_D",[PTy(FTy 5,FTy 5)]),("FCLASS_S",[PTy(FTy 5,FTy 5)]), + ("FCVT_D_L",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_D_LU",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_D_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_D_W",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_D_WU",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_LU_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_LU_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_L_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_L_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_S_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_S_L",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_S_LU",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_S_W",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_S_WU",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_WU_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_WU_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_W_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FCVT_W_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FMV_D_X",[PTy(FTy 5,FTy 5)]),("FMV_S_X",[PTy(FTy 5,FTy 5)]), + ("FMV_X_D",[PTy(FTy 5,FTy 5)]),("FMV_X_S",[PTy(FTy 5,FTy 5)]), + ("FSGNJN_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FSGNJN_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FSGNJX_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FSGNJX_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FSGNJ_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FSGNJ_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("FArith", + [("FADD_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FADD_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FDIV_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FDIV_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FEQ_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FEQ_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FLE_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FLE_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FLT_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FLT_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FMADD_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FMADD_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FMAX_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FMAX_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FMIN_D",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FMIN_S",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("FMSUB_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FMSUB_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FMUL_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FMUL_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FNMADD_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FNMADD_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FNMSUB_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FNMSUB_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))]), + ("FSQRT_D",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FSQRT_S",[PTy(FTy 5,PTy(FTy 5,FTy 3))]), + ("FSUB_D",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))]), + ("FSUB_S",[PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))])])] +; +val _ = Construct + [("FPStore", + [("FSD",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("FSW",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("FPLoad", + [("FLD",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("FLW",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("AMO", + [("AMOADD_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOADD_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOAND_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOAND_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMAXU_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMAXU_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMAX_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMAX_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMINU_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMINU_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMIN_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOMIN_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOOR_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOOR_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOSWAP_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOSWAP_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOXOR_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("AMOXOR_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("LR_D",[PTy(F1,PTy(F1,PTy(FTy 5,FTy 5)))]), + ("LR_W",[PTy(F1,PTy(F1,PTy(FTy 5,FTy 5)))]), + ("SC_D",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))]), + ("SC_W",[PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5))))])])] +; +val _ = Construct + [("Store", + [("SB",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("SD",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("SH",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("SW",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("Load", + [("LB",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LBU",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LD",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LH",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LHU",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LW",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("LWU",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("Branch", + [("BEQ",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("BGE",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("BGEU",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("BLT",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("BLTU",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("BNE",[PTy(FTy 5,PTy(FTy 5,FTy 12))]),("JAL",[PTy(FTy 5,FTy 20)]), + ("JALR",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("MulDiv", + [("DIV",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DIVU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DIVUW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("DIVW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MUL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MULH",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MULHSU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MULHU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("MULW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("REM",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("REMU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("REMUW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("REMW",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("Shift", + [("SLL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLLI",[PTy(FTy 5,PTy(FTy 5,FTy 6))]), + ("SLLIW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLLW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRA",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRAI",[PTy(FTy 5,PTy(FTy 5,FTy 6))]), + ("SRAIW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRAW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRL",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRLI",[PTy(FTy 5,PTy(FTy 5,FTy 6))]), + ("SRLIW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SRLW",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("ArithR", + [("ADD",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("ADDW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("AND",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("OR",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLT",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SLTU",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SUB",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("SUBW",[PTy(FTy 5,PTy(FTy 5,FTy 5))]), + ("XOR",[PTy(FTy 5,PTy(FTy 5,FTy 5))])])] +; +val _ = Construct + [("ArithI", + [("ADDI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("ADDIW",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("ANDI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("AUIPC",[PTy(FTy 5,FTy 20)]),("LUI",[PTy(FTy 5,FTy 20)]), + ("ORI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("SLTI",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("SLTIU",[PTy(FTy 5,PTy(FTy 5,FTy 12))]), + ("XORI",[PTy(FTy 5,PTy(FTy 5,FTy 12))])])] +; +val _ = Construct + [("instruction", + [("AMO",[CTy"AMO"]),("ArithI",[CTy"ArithI"]),("ArithR",[CTy"ArithR"]), + ("Branch",[CTy"Branch"]),("FArith",[CTy"FArith"]), + ("FConv",[CTy"FConv"]),("FENCE",[PTy(FTy 5,PTy(FTy 5,PTy(F4,F4)))]), + ("FENCE_I",[PTy(FTy 5,PTy(FTy 5,FTy 12))]),("FPLoad",[CTy"FPLoad"]), + ("FPStore",[CTy"FPStore"]),("Internal",[CTy"Internal"]), + ("Load",[CTy"Load"]),("MulDiv",[CTy"MulDiv"]),("Shift",[CTy"Shift"]), + ("Store",[CTy"Store"]),("System",[CTy"System"]), + ("UnknownInstruction",[])])] +; +val _ = Construct + [("FetchResult", + [("F_Error",[CTy"instruction"]),("F_Result",[CTy"rawInstType"])])] +; +val _ = Construct [("rvc",[("Comp",[F16]),("Full",[F32])])] +; +val _ = Construct + [("exception", + [("INTERNAL_ERROR",[sTy]),("NoException",[]),("UNDEFINED",[sTy])])] +; +val _ = Record + ("riscv_state", + [("MEM8",ATy(F64,F8)),("c_ExitCode",ATy(F8,F64)), + ("c_HCSR",ATy(F8,CTy"HypervisorCSR")), + ("c_MCSR",ATy(F8,CTy"MachineCSR")), + ("c_NextFetch",ATy(F8,OTy(CTy"TransferControl"))), + ("c_PC",ATy(F8,F64)),("c_ReserveLoad",ATy(F8,OTy F64)), + ("c_SCSR",ATy(F8,CTy"SupervisorCSR")),("c_Skip",ATy(F8,F64)), + ("c_UCSR",ATy(F8,CTy"UserCSR")),("c_cycles",ATy(F8,F64)), + ("c_fpr",ATy(F8,ATy(FTy 5,F64))),("c_gpr",ATy(F8,ATy(FTy 5,F64))), + ("c_instret",ATy(F8,F64)), + ("c_tlb",ATy(F8,ATy(F4,OTy(CTy"TLBEntry")))), + ("c_update",ATy(F8,CTy"StateDelta")),("clock",F64),("done",bTy), + ("exception",CTy"exception"),("log",LTy(PTy(nTy,sTy))),("procID",F8), + ("totalCore",nTy)]) +; +val qTy = CTy "riscv_state"; +fun qVar v = Term.mk_var (v, ParseDatatype.pretypeToType qTy); +val raise'exception_def = Def + ("raise'exception",Var("e",CTy"exception"), + Close + (qVar"state", + TP[LX(VTy"a"), + ITE(EQ(Dest("exception",CTy"exception",qVar"state"), + Const("NoException",CTy"exception")), + Rupd("exception",TP[qVar"state",Var("e",CTy"exception")]), + qVar"state")])) +; +val ASID_SIZE_def = Def0 ("ASID_SIZE",LN 6) +; +val PAGESIZE_BITS_def = Def0 ("PAGESIZE_BITS",LN 12) +; +val LEVEL_BITS_def = Def0 ("LEVEL_BITS",LN 9) +; +val BYTE_def = Def0 ("BYTE",LW(0,3)) +; +val HALFWORD_def = Def0 ("HALFWORD",LW(1,3)) +; +val WORD_def = Def0 ("WORD",LW(3,3)) +; +val DOUBLEWORD_def = Def0 ("DOUBLEWORD",LW(7,3)) +; +val archBase_def = Def + ("archBase",Var("a",CTy"Architecture"), + CS(Var("a",CTy"Architecture"), + [(LC("RV32I",CTy"Architecture"),LW(0,2)), + (LC("RV64I",CTy"Architecture"),LW(2,2)), + (LC("RV128I",CTy"Architecture"),LW(3,2))])) +; +val architecture_def = Def + ("architecture",Var("ab",FTy 2), + Close + (qVar"state", + CS(Var("ab",FTy 2), + [(LW(0,2),TP[LC("RV32I",CTy"Architecture"),qVar"state"]), + (LW(2,2),TP[LC("RV64I",CTy"Architecture"),qVar"state"]), + (LW(3,2),TP[LC("RV128I",CTy"Architecture"),qVar"state"]), + (AVar(FTy 2), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(CTy"Architecture",qTy)), + Call + ("UNDEFINED",CTy"exception", + CC[LS"Unknown architecture: ", + Mop(Cast sTy,Mop(Cast nTy,Var("ab",FTy 2)))])), + qVar"state"))]))) +; +val archName_def = Def + ("archName",Var("a",CTy"Architecture"), + CS(Var("a",CTy"Architecture"), + [(LC("RV32I",CTy"Architecture"),LS"RV32I"), + (LC("RV64I",CTy"Architecture"),LS"RV64I"), + (LC("RV128I",CTy"Architecture"),LS"RV128I")])) +; +val privLevel_def = Def + ("privLevel",Var("p",CTy"Privilege"), + CS(Var("p",CTy"Privilege"), + [(LC("User",CTy"Privilege"),LW(0,2)), + (LC("Supervisor",CTy"Privilege"),LW(1,2)), + (LC("Hypervisor",CTy"Privilege"),LW(2,2)), + (LC("Machine",CTy"Privilege"),LW(3,2))])) +; +val privilege_def = Def + ("privilege",Var("p",FTy 2), + CS(Var("p",FTy 2), + [(LW(0,2),LC("User",CTy"Privilege")), + (LW(1,2),LC("Supervisor",CTy"Privilege")), + (LW(2,2),LC("Hypervisor",CTy"Privilege")), + (LW(3,2),LC("Machine",CTy"Privilege"))])) +; +val privName_def = Def + ("privName",Var("p",CTy"Privilege"), + CS(Var("p",CTy"Privilege"), + [(LC("User",CTy"Privilege"),LS"U"), + (LC("Supervisor",CTy"Privilege"),LS"S"), + (LC("Hypervisor",CTy"Privilege"),LS"H"), + (LC("Machine",CTy"Privilege"),LS"M")])) +; +val vmType_def = Def + ("vmType",Var("vm",FTy 5), + Close + (qVar"state", + CS(Var("vm",FTy 5), + [(LW(0,5),TP[LC("Mbare",CTy"VM_Mode"),qVar"state"]), + (LW(1,5),TP[LC("Mbb",CTy"VM_Mode"),qVar"state"]), + (LW(2,5),TP[LC("Mbbid",CTy"VM_Mode"),qVar"state"]), + (LW(8,5),TP[LC("Sv32",CTy"VM_Mode"),qVar"state"]), + (LW(9,5),TP[LC("Sv39",CTy"VM_Mode"),qVar"state"]), + (LW(10,5),TP[LC("Sv48",CTy"VM_Mode"),qVar"state"]), + (LW(11,5),TP[LC("Sv57",CTy"VM_Mode"),qVar"state"]), + (LW(12,5),TP[LC("Sv64",CTy"VM_Mode"),qVar"state"]), + (AVar(FTy 5), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(CTy"VM_Mode",qTy)), + Call + ("UNDEFINED",CTy"exception", + CC[LS"Unknown address translation mode: ", + Mop(Cast sTy,Mop(Cast nTy,Var("vm",FTy 5)))])), + qVar"state"))]))) +; +val isValidVM_def = Def + ("isValidVM",Var("vm",FTy 5), + CS(Var("vm",FTy 5), + [(LW(0,5),LT),(LW(1,5),LT),(LW(2,5),LT),(LW(8,5),LT),(LW(9,5),LT), + (LW(10,5),LT),(LW(11,5),LT),(LW(12,5),LT),(AVar(FTy 5),LF)])) +; +val vmMode_def = Def + ("vmMode",Var("vm",CTy"VM_Mode"), + CS(Var("vm",CTy"VM_Mode"), + [(LC("Mbare",CTy"VM_Mode"),LW(0,5)), + (LC("Mbb",CTy"VM_Mode"),LW(1,5)), + (LC("Mbbid",CTy"VM_Mode"),LW(2,5)), + (LC("Sv32",CTy"VM_Mode"),LW(8,5)), + (LC("Sv39",CTy"VM_Mode"),LW(9,5)), + (LC("Sv48",CTy"VM_Mode"),LW(10,5)), + (LC("Sv57",CTy"VM_Mode"),LW(11,5)), + (LC("Sv64",CTy"VM_Mode"),LW(12,5))])) +; +val vmModeName_def = Def + ("vmModeName",Var("vm",CTy"VM_Mode"), + CS(Var("vm",CTy"VM_Mode"), + [(LC("Mbare",CTy"VM_Mode"),LS"Mbare"), + (LC("Mbb",CTy"VM_Mode"),LS"Mbb"), + (LC("Mbbid",CTy"VM_Mode"),LS"Mbbid"), + (LC("Sv32",CTy"VM_Mode"),LS"Sv32"), + (LC("Sv39",CTy"VM_Mode"),LS"Sv39"), + (LC("Sv48",CTy"VM_Mode"),LS"Sv48"), + (LC("Sv57",CTy"VM_Mode"),LS"Sv57"), + (LC("Sv64",CTy"VM_Mode"),LS"Sv64")])) +; +val ext_status_def = Def + ("ext_status",Var("e",CTy"ExtStatus"), + CS(Var("e",CTy"ExtStatus"), + [(LC("Off",CTy"ExtStatus"),LW(0,2)), + (LC("Initial",CTy"ExtStatus"),LW(1,2)), + (LC("Clean",CTy"ExtStatus"),LW(2,2)), + (LC("Dirty",CTy"ExtStatus"),LW(3,2))])) +; +val extStatus_def = Def + ("extStatus",Var("e",FTy 2), + CS(Var("e",FTy 2), + [(LW(0,2),LC("Off",CTy"ExtStatus")), + (LW(1,2),LC("Initial",CTy"ExtStatus")), + (LW(2,2),LC("Clean",CTy"ExtStatus")), + (LW(3,2),LC("Dirty",CTy"ExtStatus"))])) +; +val extStatusName_def = Def + ("extStatusName",Var("e",CTy"ExtStatus"), + CS(Var("e",CTy"ExtStatus"), + [(LC("Off",CTy"ExtStatus"),LS"Off"), + (LC("Initial",CTy"ExtStatus"),LS"Initial"), + (LC("Clean",CTy"ExtStatus"),LS"Clean"), + (LC("Dirty",CTy"ExtStatus"),LS"Dirty")])) +; +val interruptIndex_def = Def + ("interruptIndex",Var("i",CTy"Interrupt"), + CS(Var("i",CTy"Interrupt"), + [(LC("Software",CTy"Interrupt"),LW(0,4)), + (LC("Timer",CTy"Interrupt"),LW(1,4))])) +; +val excCode_def = Def + ("excCode",Var("e",CTy"ExceptionType"), + CS(Var("e",CTy"ExceptionType"), + [(LC("Fetch_Misaligned",CTy"ExceptionType"),LW(0,4)), + (LC("Fetch_Fault",CTy"ExceptionType"),LW(1,4)), + (LC("Illegal_Instr",CTy"ExceptionType"),LW(2,4)), + (LC("Breakpoint",CTy"ExceptionType"),LW(3,4)), + (LC("Load_Fault",CTy"ExceptionType"),LW(5,4)), + (LC("AMO_Misaligned",CTy"ExceptionType"),LW(6,4)), + (LC("Store_AMO_Fault",CTy"ExceptionType"),LW(7,4)), + (LC("UMode_Env_Call",CTy"ExceptionType"),LW(8,4)), + (LC("SMode_Env_Call",CTy"ExceptionType"),LW(9,4)), + (LC("HMode_Env_Call",CTy"ExceptionType"),LW(10,4)), + (LC("MMode_Env_Call",CTy"ExceptionType"),LW(11,4))])) +; +val excType_def = Def + ("excType",Var("e",F4), + Close + (qVar"state", + CS(Var("e",F4), + [(LW(0,4), + TP[LC("Fetch_Misaligned",CTy"ExceptionType"),qVar"state"]), + (LW(1,4),TP[LC("Fetch_Fault",CTy"ExceptionType"),qVar"state"]), + (LW(2,4),TP[LC("Illegal_Instr",CTy"ExceptionType"),qVar"state"]), + (LW(3,4),TP[LC("Breakpoint",CTy"ExceptionType"),qVar"state"]), + (LW(5,4),TP[LC("Load_Fault",CTy"ExceptionType"),qVar"state"]), + (LW(6,4),TP[LC("AMO_Misaligned",CTy"ExceptionType"),qVar"state"]), + (LW(7,4), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"),qVar"state"]), + (LW(8,4),TP[LC("UMode_Env_Call",CTy"ExceptionType"),qVar"state"]), + (LW(9,4),TP[LC("SMode_Env_Call",CTy"ExceptionType"),qVar"state"]), + (LW(10,4), + TP[LC("HMode_Env_Call",CTy"ExceptionType"),qVar"state"]), + (LW(11,4), + TP[LC("MMode_Env_Call",CTy"ExceptionType"),qVar"state"]), + (AVar F4, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(CTy"ExceptionType",qTy)), + Call + ("UNDEFINED",CTy"exception", + CC[LS"Unknown exception: ", + Mop(Cast sTy,Mop(Cast nTy,Var("e",F4)))])), + qVar"state"))]))) +; +val excName_def = Def + ("excName",Var("e",CTy"ExceptionType"), + CS(Var("e",CTy"ExceptionType"), + [(LC("Fetch_Misaligned",CTy"ExceptionType"),LS"MISALIGNED_FETCH"), + (LC("Fetch_Fault",CTy"ExceptionType"),LS"FAULT_FETCH"), + (LC("Illegal_Instr",CTy"ExceptionType"),LS"ILLEGAL_INSTRUCTION"), + (LC("Breakpoint",CTy"ExceptionType"),LS"BREAKPOINT"), + (LC("Load_Fault",CTy"ExceptionType"),LS"FAULT_LOAD"), + (LC("AMO_Misaligned",CTy"ExceptionType"),LS"MISALIGNED_AMO"), + (LC("Store_AMO_Fault",CTy"ExceptionType"),LS"FAULT_STORE_AMO"), + (LC("UMode_Env_Call",CTy"ExceptionType"),LS"U-EnvCall"), + (LC("SMode_Env_Call",CTy"ExceptionType"),LS"S-EnvCall"), + (LC("HMode_Env_Call",CTy"ExceptionType"),LS"H-EnvCall"), + (LC("MMode_Env_Call",CTy"ExceptionType"),LS"M-EnvCall")])) +; +val rec'mcpuid_def = Def + ("rec'mcpuid",Var("x",F64), + Rec(CTy"mcpuid", + [EX(Var("x",F64),LN 63,LN 62,FTy 2),Bop(Bit,Var("x",F64),LN 8), + Bop(Bit,Var("x",F64),LN 12),Bop(Bit,Var("x",F64),LN 18), + Bop(Bit,Var("x",F64),LN 20), + CC[EX(Var("x",F64),LN 7,LN 0,F8), + EX(Var("x",F64),LN 11,LN 9,FTy 3), + EX(Var("x",F64),LN 17,LN 13,FTy 5), + EX(Var("x",F64),LN 19,LN 19,F1), + EX(Var("x",F64),LN 61,LN 21,FTy 41)]])) +; +val reg'mcpuid_def = Def + ("reg'mcpuid",Var("x",CTy"mcpuid"), + CS(Var("x",CTy"mcpuid"), + [(Rec(CTy"mcpuid", + [Var("ArchBase",FTy 2),bVar"I",bVar"M",bVar"S",bVar"U", + Var("mcpuid'rst",FTy 58)]), + CC[Var("ArchBase",FTy 2), + EX(Var("mcpuid'rst",FTy 58),LN 40,LN 0,FTy 41), + Mop(Cast F1,bVar"U"), + EX(Var("mcpuid'rst",FTy 58),LN 41,LN 41,F1), + Mop(Cast F1,bVar"S"), + EX(Var("mcpuid'rst",FTy 58),LN 46,LN 42,FTy 5), + Mop(Cast F1,bVar"M"), + EX(Var("mcpuid'rst",FTy 58),LN 49,LN 47,FTy 3), + Mop(Cast F1,bVar"I"), + EX(Var("mcpuid'rst",FTy 58),LN 57,LN 50,F8)])])) +; +val write'rec'mcpuid_def = Def + ("write'rec'mcpuid",TP[AVar F64,Var("x",CTy"mcpuid")], + Call("reg'mcpuid",F64,Var("x",CTy"mcpuid"))) +; +val write'reg'mcpuid_def = Def + ("write'reg'mcpuid",TP[AVar(CTy"mcpuid"),Var("x",F64)], + Call("rec'mcpuid",CTy"mcpuid",Var("x",F64))) +; +val rec'mimpid_def = Def + ("rec'mimpid",Var("x",F64), + Rec(CTy"mimpid", + [EX(Var("x",F64),LN 63,LN 16,FTy 48), + EX(Var("x",F64),LN 15,LN 0,F16)])) +; +val reg'mimpid_def = Def + ("reg'mimpid",Var("x",CTy"mimpid"), + CS(Var("x",CTy"mimpid"), + [(Rec(CTy"mimpid",[Var("RVImpl",FTy 48),Var("RVSource",F16)]), + CC[Var("RVImpl",FTy 48),Var("RVSource",F16)])])) +; +val write'rec'mimpid_def = Def + ("write'rec'mimpid",TP[AVar F64,Var("x",CTy"mimpid")], + Call("reg'mimpid",F64,Var("x",CTy"mimpid"))) +; +val write'reg'mimpid_def = Def + ("write'reg'mimpid",TP[AVar(CTy"mimpid"),Var("x",F64)], + Call("rec'mimpid",CTy"mimpid",Var("x",F64))) +; +val rec'mstatus_def = Def + ("rec'mstatus",Var("x",F64), + Rec(CTy"mstatus", + [EX(Var("x",F64),LN 13,LN 12,FTy 2),Bop(Bit,Var("x",F64),LN 0), + Bop(Bit,Var("x",F64),LN 3),Bop(Bit,Var("x",F64),LN 6), + Bop(Bit,Var("x",F64),LN 9),Bop(Bit,Var("x",F64),LN 16), + EX(Var("x",F64),LN 2,LN 1,FTy 2),EX(Var("x",F64),LN 5,LN 4,FTy 2), + EX(Var("x",F64),LN 8,LN 7,FTy 2), + EX(Var("x",F64),LN 11,LN 10,FTy 2),Bop(Bit,Var("x",F64),LN 63), + EX(Var("x",F64),LN 15,LN 14,FTy 2), + EX(Var("x",F64),LN 21,LN 17,FTy 5), + EX(Var("x",F64),LN 62,LN 22,FTy 41)])) +; +val reg'mstatus_def = Def + ("reg'mstatus",Var("x",CTy"mstatus"), + CS(Var("x",CTy"mstatus"), + [(Rec(CTy"mstatus", + [Var("MFS",FTy 2),bVar"MIE",bVar"MIE1",bVar"MIE2",bVar"MIE3", + bVar"MMPRV",Var("MPRV",FTy 2),Var("MPRV1",FTy 2), + Var("MPRV2",FTy 2),Var("MPRV3",FTy 2),bVar"MSD", + Var("MXS",FTy 2),Var("VM",FTy 5),Var("mstatus'rst",FTy 41)]), + CC[Mop(Cast F1,bVar"MSD"),Var("mstatus'rst",FTy 41), + Var("VM",FTy 5),Mop(Cast F1,bVar"MMPRV"),Var("MXS",FTy 2), + Var("MFS",FTy 2),Var("MPRV3",FTy 2),Mop(Cast F1,bVar"MIE3"), + Var("MPRV2",FTy 2),Mop(Cast F1,bVar"MIE2"),Var("MPRV1",FTy 2), + Mop(Cast F1,bVar"MIE1"),Var("MPRV",FTy 2), + Mop(Cast F1,bVar"MIE")])])) +; +val write'rec'mstatus_def = Def + ("write'rec'mstatus",TP[AVar F64,Var("x",CTy"mstatus")], + Call("reg'mstatus",F64,Var("x",CTy"mstatus"))) +; +val write'reg'mstatus_def = Def + ("write'reg'mstatus",TP[AVar(CTy"mstatus"),Var("x",F64)], + Call("rec'mstatus",CTy"mstatus",Var("x",F64))) +; +val rec'mtdeleg_def = Def + ("rec'mtdeleg",Var("x",F64), + Rec(CTy"mtdeleg", + [EX(Var("x",F64),LN 15,LN 0,F16), + EX(Var("x",F64),LN 63,LN 16,FTy 48)])) +; +val reg'mtdeleg_def = Def + ("reg'mtdeleg",Var("x",CTy"mtdeleg"), + CS(Var("x",CTy"mtdeleg"), + [(Rec(CTy"mtdeleg",[Var("Exc_deleg",F16),Var("Intr_deleg",FTy 48)]), + CC[Var("Intr_deleg",FTy 48),Var("Exc_deleg",F16)])])) +; +val write'rec'mtdeleg_def = Def + ("write'rec'mtdeleg",TP[AVar F64,Var("x",CTy"mtdeleg")], + Call("reg'mtdeleg",F64,Var("x",CTy"mtdeleg"))) +; +val write'reg'mtdeleg_def = Def + ("write'reg'mtdeleg",TP[AVar(CTy"mtdeleg"),Var("x",F64)], + Call("rec'mtdeleg",CTy"mtdeleg",Var("x",F64))) +; +val rec'mip_def = Def + ("rec'mip",Var("x",F64), + Rec(CTy"mip", + [Bop(Bit,Var("x",F64),LN 2),Bop(Bit,Var("x",F64),LN 6), + Bop(Bit,Var("x",F64),LN 3),Bop(Bit,Var("x",F64),LN 7), + Bop(Bit,Var("x",F64),LN 1),Bop(Bit,Var("x",F64),LN 5), + CC[EX(Var("x",F64),LN 0,LN 0,F1),EX(Var("x",F64),LN 4,LN 4,F1), + EX(Var("x",F64),LN 63,LN 8,FTy 56)]])) +; +val reg'mip_def = Def + ("reg'mip",Var("x",CTy"mip"), + CS(Var("x",CTy"mip"), + [(Rec(CTy"mip", + [bVar"HSIP",bVar"HTIP",bVar"MSIP",bVar"MTIP",bVar"SSIP", + bVar"STIP",Var("mip'rst",FTy 58)]), + CC[EX(Var("mip'rst",FTy 58),LN 55,LN 0,FTy 56), + Mop(Cast F1,bVar"MTIP"),Mop(Cast F1,bVar"HTIP"), + Mop(Cast F1,bVar"STIP"), + EX(Var("mip'rst",FTy 58),LN 56,LN 56,F1), + Mop(Cast F1,bVar"MSIP"),Mop(Cast F1,bVar"HSIP"), + Mop(Cast F1,bVar"SSIP"), + EX(Var("mip'rst",FTy 58),LN 57,LN 57,F1)])])) +; +val write'rec'mip_def = Def + ("write'rec'mip",TP[AVar F64,Var("x",CTy"mip")], + Call("reg'mip",F64,Var("x",CTy"mip"))) +; +val write'reg'mip_def = Def + ("write'reg'mip",TP[AVar(CTy"mip"),Var("x",F64)], + Call("rec'mip",CTy"mip",Var("x",F64))) +; +val rec'mie_def = Def + ("rec'mie",Var("x",F64), + Rec(CTy"mie", + [Bop(Bit,Var("x",F64),LN 2),Bop(Bit,Var("x",F64),LN 6), + Bop(Bit,Var("x",F64),LN 3),Bop(Bit,Var("x",F64),LN 7), + Bop(Bit,Var("x",F64),LN 1),Bop(Bit,Var("x",F64),LN 5), + CC[EX(Var("x",F64),LN 0,LN 0,F1),EX(Var("x",F64),LN 4,LN 4,F1), + EX(Var("x",F64),LN 63,LN 8,FTy 56)]])) +; +val reg'mie_def = Def + ("reg'mie",Var("x",CTy"mie"), + CS(Var("x",CTy"mie"), + [(Rec(CTy"mie", + [bVar"HSIE",bVar"HTIE",bVar"MSIE",bVar"MTIE",bVar"SSIE", + bVar"STIE",Var("mie'rst",FTy 58)]), + CC[EX(Var("mie'rst",FTy 58),LN 55,LN 0,FTy 56), + Mop(Cast F1,bVar"MTIE"),Mop(Cast F1,bVar"HTIE"), + Mop(Cast F1,bVar"STIE"), + EX(Var("mie'rst",FTy 58),LN 56,LN 56,F1), + Mop(Cast F1,bVar"MSIE"),Mop(Cast F1,bVar"HSIE"), + Mop(Cast F1,bVar"SSIE"), + EX(Var("mie'rst",FTy 58),LN 57,LN 57,F1)])])) +; +val write'rec'mie_def = Def + ("write'rec'mie",TP[AVar F64,Var("x",CTy"mie")], + Call("reg'mie",F64,Var("x",CTy"mie"))) +; +val write'reg'mie_def = Def + ("write'reg'mie",TP[AVar(CTy"mie"),Var("x",F64)], + Call("rec'mie",CTy"mie",Var("x",F64))) +; +val rec'mcause_def = Def + ("rec'mcause",Var("x",F64), + Rec(CTy"mcause", + [EX(Var("x",F64),LN 3,LN 0,F4),Bop(Bit,Var("x",F64),LN 63), + EX(Var("x",F64),LN 62,LN 4,FTy 59)])) +; +val reg'mcause_def = Def + ("reg'mcause",Var("x",CTy"mcause"), + CS(Var("x",CTy"mcause"), + [(Rec(CTy"mcause",[Var("EC",F4),bVar"Int",Var("mcause'rst",FTy 59)]), + CC[Mop(Cast F1,bVar"Int"),Var("mcause'rst",FTy 59),Var("EC",F4)])])) +; +val write'rec'mcause_def = Def + ("write'rec'mcause",TP[AVar F64,Var("x",CTy"mcause")], + Call("reg'mcause",F64,Var("x",CTy"mcause"))) +; +val write'reg'mcause_def = Def + ("write'reg'mcause",TP[AVar(CTy"mcause"),Var("x",F64)], + Call("rec'mcause",CTy"mcause",Var("x",F64))) +; +val rec'sstatus_def = Def + ("rec'sstatus",Var("x",F64), + Rec(CTy"sstatus", + [EX(Var("x",F64),LN 13,LN 12,FTy 2),Bop(Bit,Var("x",F64),LN 0), + Bop(Bit,Var("x",F64),LN 16),Bop(Bit,Var("x",F64),LN 3), + Bop(Bit,Var("x",F64),LN 4),Bop(Bit,Var("x",F64),LN 63), + EX(Var("x",F64),LN 15,LN 14,FTy 2), + CC[EX(Var("x",F64),LN 2,LN 1,FTy 2), + EX(Var("x",F64),LN 11,LN 5,FTy 7), + EX(Var("x",F64),LN 62,LN 17,FTy 46)]])) +; +val reg'sstatus_def = Def + ("reg'sstatus",Var("x",CTy"sstatus"), + CS(Var("x",CTy"sstatus"), + [(Rec(CTy"sstatus", + [Var("SFS",FTy 2),bVar"SIE",bVar"SMPRV",bVar"SPIE",bVar"SPS", + bVar"SSD",Var("SXS",FTy 2),Var("sstatus'rst",FTy 55)]), + CC[Mop(Cast F1,bVar"SSD"), + EX(Var("sstatus'rst",FTy 55),LN 45,LN 0,FTy 46), + Mop(Cast F1,bVar"SMPRV"),Var("SXS",FTy 2),Var("SFS",FTy 2), + EX(Var("sstatus'rst",FTy 55),LN 52,LN 46,FTy 7), + Mop(Cast F1,bVar"SPS"),Mop(Cast F1,bVar"SPIE"), + EX(Var("sstatus'rst",FTy 55),LN 54,LN 53,FTy 2), + Mop(Cast F1,bVar"SIE")])])) +; +val write'rec'sstatus_def = Def + ("write'rec'sstatus",TP[AVar F64,Var("x",CTy"sstatus")], + Call("reg'sstatus",F64,Var("x",CTy"sstatus"))) +; +val write'reg'sstatus_def = Def + ("write'reg'sstatus",TP[AVar(CTy"sstatus"),Var("x",F64)], + Call("rec'sstatus",CTy"sstatus",Var("x",F64))) +; +val rec'sip_def = Def + ("rec'sip",Var("x",F64), + Rec(CTy"sip", + [Bop(Bit,Var("x",F64),LN 1),Bop(Bit,Var("x",F64),LN 5), + CC[EX(Var("x",F64),LN 0,LN 0,F1),EX(Var("x",F64),LN 4,LN 2,FTy 3), + EX(Var("x",F64),LN 63,LN 6,FTy 58)]])) +; +val reg'sip_def = Def + ("reg'sip",Var("x",CTy"sip"), + CS(Var("x",CTy"sip"), + [(Rec(CTy"sip",[bVar"SSIP",bVar"STIP",Var("sip'rst",FTy 62)]), + CC[EX(Var("sip'rst",FTy 62),LN 57,LN 0,FTy 58), + Mop(Cast F1,bVar"STIP"), + EX(Var("sip'rst",FTy 62),LN 60,LN 58,FTy 3), + Mop(Cast F1,bVar"SSIP"), + EX(Var("sip'rst",FTy 62),LN 61,LN 61,F1)])])) +; +val write'rec'sip_def = Def + ("write'rec'sip",TP[AVar F64,Var("x",CTy"sip")], + Call("reg'sip",F64,Var("x",CTy"sip"))) +; +val write'reg'sip_def = Def + ("write'reg'sip",TP[AVar(CTy"sip"),Var("x",F64)], + Call("rec'sip",CTy"sip",Var("x",F64))) +; +val rec'sie_def = Def + ("rec'sie",Var("x",F64), + Rec(CTy"sie", + [Bop(Bit,Var("x",F64),LN 1),Bop(Bit,Var("x",F64),LN 5), + CC[EX(Var("x",F64),LN 0,LN 0,F1),EX(Var("x",F64),LN 4,LN 2,FTy 3), + EX(Var("x",F64),LN 63,LN 6,FTy 58)]])) +; +val reg'sie_def = Def + ("reg'sie",Var("x",CTy"sie"), + CS(Var("x",CTy"sie"), + [(Rec(CTy"sie",[bVar"SSIE",bVar"STIE",Var("sie'rst",FTy 62)]), + CC[EX(Var("sie'rst",FTy 62),LN 57,LN 0,FTy 58), + Mop(Cast F1,bVar"STIE"), + EX(Var("sie'rst",FTy 62),LN 60,LN 58,FTy 3), + Mop(Cast F1,bVar"SSIE"), + EX(Var("sie'rst",FTy 62),LN 61,LN 61,F1)])])) +; +val write'rec'sie_def = Def + ("write'rec'sie",TP[AVar F64,Var("x",CTy"sie")], + Call("reg'sie",F64,Var("x",CTy"sie"))) +; +val write'reg'sie_def = Def + ("write'reg'sie",TP[AVar(CTy"sie"),Var("x",F64)], + Call("rec'sie",CTy"sie",Var("x",F64))) +; +val rec'FPCSR_def = Def + ("rec'FPCSR",Var("x",F32), + Rec(CTy"FPCSR", + [Bop(Bit,Var("x",F32),LN 3),EX(Var("x",F32),LN 7,LN 5,FTy 3), + Bop(Bit,Var("x",F32),LN 4),Bop(Bit,Var("x",F32),LN 0), + Bop(Bit,Var("x",F32),LN 2),Bop(Bit,Var("x",F32),LN 1), + EX(Var("x",F32),LN 31,LN 8,FTy 24)])) +; +val reg'FPCSR_def = Def + ("reg'FPCSR",Var("x",CTy"FPCSR"), + CS(Var("x",CTy"FPCSR"), + [(Rec(CTy"FPCSR", + [bVar"DZ",Var("FRM",FTy 3),bVar"NV",bVar"NX",bVar"OF", + bVar"UF",Var("fpcsr'rst",FTy 24)]), + CC[Var("fpcsr'rst",FTy 24),Var("FRM",FTy 3),Mop(Cast F1,bVar"NV"), + Mop(Cast F1,bVar"DZ"),Mop(Cast F1,bVar"OF"), + Mop(Cast F1,bVar"UF"),Mop(Cast F1,bVar"NX")])])) +; +val write'rec'FPCSR_def = Def + ("write'rec'FPCSR",TP[AVar F32,Var("x",CTy"FPCSR")], + Call("reg'FPCSR",F32,Var("x",CTy"FPCSR"))) +; +val write'reg'FPCSR_def = Def + ("write'reg'FPCSR",TP[AVar(CTy"FPCSR"),Var("x",F32)], + Call("rec'FPCSR",CTy"FPCSR",Var("x",F32))) +; +val lift_mip_sip_def = Def + ("lift_mip_sip",Var("mip",CTy"mip"), + Rupd + ("SSIP", + TP[Rupd + ("STIP", + TP[Call("rec'sip",CTy"sip",LW(0,64)), + Dest("STIP",bTy,Var("mip",CTy"mip"))]), + Dest("SSIP",bTy,Var("mip",CTy"mip"))])) +; +val lift_mie_sie_def = Def + ("lift_mie_sie",Var("mie",CTy"mie"), + Rupd + ("SSIE", + TP[Rupd + ("STIE", + TP[Call("rec'sie",CTy"sie",LW(0,64)), + Dest("STIE",bTy,Var("mie",CTy"mie"))]), + Dest("SSIE",bTy,Var("mie",CTy"mie"))])) +; +val lower_sip_mip_def = Def + ("lower_sip_mip",TP[Var("sip",CTy"sip"),Var("mip",CTy"mip")], + Rupd + ("SSIP", + TP[Rupd + ("STIP", + TP[Var("mip",CTy"mip"),Dest("STIP",bTy,Var("sip",CTy"sip"))]), + Dest("SSIP",bTy,Var("sip",CTy"sip"))])) +; +val lower_sie_mie_def = Def + ("lower_sie_mie",TP[Var("sie",CTy"sie"),Var("mie",CTy"mie")], + Rupd + ("SSIE", + TP[Rupd + ("STIE", + TP[Var("mie",CTy"mie"),Dest("STIE",bTy,Var("sie",CTy"sie"))]), + Dest("SSIE",bTy,Var("sie",CTy"sie"))])) +; +val update_mstatus_def = Def + ("update_mstatus",TP[Var("orig",CTy"mstatus"),Var("v",CTy"mstatus")], + Let(Var("s0",CTy"mstatus"), + Rupd + ("MPRV3", + TP[Rupd + ("MIE3", + TP[Rupd + ("MPRV2", + TP[Rupd + ("MIE2", + TP[Rupd + ("MPRV1", + TP[Rupd + ("MIE1", + TP[Rupd + ("MPRV", + TP[Rupd + ("MIE", + TP[Var("orig", + CTy"mstatus"), + Dest + ("MIE",bTy, + Var("v", + CTy"mstatus"))]), + Dest + ("MPRV",FTy 2, + Var("v",CTy"mstatus"))]), + Dest + ("MIE1",bTy, + Var("v",CTy"mstatus"))]), + Dest + ("MPRV1",FTy 2, + Var("v",CTy"mstatus"))]), + Dest("MIE2",bTy,Var("v",CTy"mstatus"))]), + Dest("MPRV2",FTy 2,Var("v",CTy"mstatus"))]), + Dest("MIE3",bTy,Var("v",CTy"mstatus"))]), + Dest("MPRV3",FTy 2,Var("v",CTy"mstatus"))]), + Rupd + ("MSD", + TP[Rupd + ("MXS", + TP[Rupd + ("MFS", + TP[Rupd + ("MMPRV", + TP[ITE(Call + ("isValidVM",bTy, + Dest + ("VM",FTy 5,Var("v",CTy"mstatus"))), + Rupd + ("VM", + TP[Var("s0",CTy"mstatus"), + Dest + ("VM",FTy 5, + Var("v",CTy"mstatus"))]), + Var("s0",CTy"mstatus")), + Dest("MMPRV",bTy,Var("v",CTy"mstatus"))]), + Dest("MFS",FTy 2,Var("v",CTy"mstatus"))]), + Dest("MXS",FTy 2,Var("v",CTy"mstatus"))]), + Bop(Or, + EQ(Call + ("extStatus",CTy"ExtStatus", + Dest("MXS",FTy 2,Var("v",CTy"mstatus"))), + LC("Dirty",CTy"ExtStatus")), + EQ(Call + ("extStatus",CTy"ExtStatus", + Dest("MFS",FTy 2,Var("v",CTy"mstatus"))), + LC("Dirty",CTy"ExtStatus")))]))) +; +val lift_mstatus_sstatus_def = Def + ("lift_mstatus_sstatus",Var("mst",CTy"mstatus"), + Rupd + ("SIE", + TP[Rupd + ("SPIE", + TP[Rupd + ("SPS", + TP[Rupd + ("SSD", + TP[Rupd + ("SFS", + TP[Rupd + ("SXS", + TP[Rupd + ("SMPRV", + TP[Call + ("rec'sstatus", + CTy"sstatus",LW(0,64)), + Dest + ("MMPRV",bTy, + Var("mst",CTy"mstatus"))]), + Dest + ("MXS",FTy 2, + Var("mst",CTy"mstatus"))]), + Dest("MFS",FTy 2,Var("mst",CTy"mstatus"))]), + Bop(Or, + EQ(Call + ("extStatus",CTy"ExtStatus", + Dest + ("MXS",FTy 2, + Var("mst",CTy"mstatus"))), + LC("Dirty",CTy"ExtStatus")), + EQ(Call + ("extStatus",CTy"ExtStatus", + Dest + ("MFS",FTy 2, + Var("mst",CTy"mstatus"))), + LC("Dirty",CTy"ExtStatus")))]), + Mop(Not, + EQ(Call + ("privilege",CTy"Privilege", + Dest("MPRV1",FTy 2,Var("mst",CTy"mstatus"))), + LC("User",CTy"Privilege")))]), + Dest("MIE1",bTy,Var("mst",CTy"mstatus"))]), + Dest("MIE",bTy,Var("mst",CTy"mstatus"))])) +; +val lower_sstatus_mstatus_def = Def + ("lower_sstatus_mstatus", + TP[Var("sst",CTy"sstatus"),Var("mst",CTy"mstatus")], + Call + ("update_mstatus",CTy"mstatus", + TP[Var("mst",CTy"mstatus"), + Rupd + ("MIE", + TP[Rupd + ("MIE1", + TP[Rupd + ("MPRV1", + TP[Rupd + ("MFS", + TP[Rupd + ("MXS", + TP[Rupd + ("MMPRV", + TP[Call + ("rec'mstatus", + CTy"mstatus", + Call + ("reg'mstatus",F64, + Var("mst",CTy"mstatus"))), + Dest + ("SMPRV",bTy, + Var("sst",CTy"sstatus"))]), + Dest + ("SXS",FTy 2, + Var("sst",CTy"sstatus"))]), + Dest("SFS",FTy 2,Var("sst",CTy"sstatus"))]), + Call + ("privLevel",FTy 2, + ITE(Dest("SPS",bTy,Var("sst",CTy"sstatus")), + LC("Supervisor",CTy"Privilege"), + LC("User",CTy"Privilege")))]), + Dest("SPIE",bTy,Var("sst",CTy"sstatus"))]), + Dest("SIE",bTy,Var("sst",CTy"sstatus"))])])) +; +val popPrivilegeStack_def = Def + ("popPrivilegeStack",Var("mst",CTy"mstatus"), + Rupd + ("MPRV2", + TP[Rupd + ("MIE2", + TP[Rupd + ("MPRV1", + TP[Rupd + ("MIE1", + TP[Rupd + ("MPRV", + TP[Rupd + ("MIE", + TP[Var("mst",CTy"mstatus"), + Dest + ("MIE1",bTy, + Var("mst",CTy"mstatus"))]), + Dest + ("MPRV1",FTy 2,Var("mst",CTy"mstatus"))]), + Dest("MIE2",bTy,Var("mst",CTy"mstatus"))]), + Dest("MPRV2",FTy 2,Var("mst",CTy"mstatus"))]),LT]), + Call("privLevel",FTy 2,LC("User",CTy"Privilege"))])) +; +val pushPrivilegeStack_def = Def + ("pushPrivilegeStack", + TP[Var("mst",CTy"mstatus"),Var("p",CTy"Privilege")], + Rupd + ("MPRV", + TP[Rupd + ("MIE", + TP[Rupd + ("MPRV1", + TP[Rupd + ("MIE1", + TP[Rupd + ("MPRV2", + TP[Rupd + ("MIE2", + TP[Var("mst",CTy"mstatus"), + Dest + ("MIE1",bTy, + Var("mst",CTy"mstatus"))]), + Dest + ("MPRV1",FTy 2,Var("mst",CTy"mstatus"))]), + Dest("MIE",bTy,Var("mst",CTy"mstatus"))]), + Dest("MPRV",FTy 2,Var("mst",CTy"mstatus"))]),LF]), + Call("privLevel",FTy 2,Var("p",CTy"Privilege"))])) +; +val scheduleCore_def = Def + ("scheduleCore",nVar"id", + Close + (qVar"state", + ITE(Bop(Lt,nVar"id",Dest("totalCore",nTy,qVar"state")), + Rupd("procID",TP[qVar"state",Mop(Cast F8,nVar"id")]),qVar"state"))) +; +val gpr_def = Def + ("gpr",Var("n",FTy 5), + Close + (qVar"state", + Apply + (Apply + (Dest("c_gpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5)))) +; +val write'gpr_def = Def + ("write'gpr",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + Rupd + ("c_gpr", + TP[qVar"state", + Fupd + (Dest("c_gpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state"), + Fupd + (Apply + (Dest("c_gpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5), + Var("value",F64)))]))) +; +val fcsr_def = Def + ("fcsr",qVar"state", + Dest + ("fpcsr",CTy"FPCSR", + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))) +; +val write'fcsr_def = Def + ("write'fcsr",Var("value",CTy"FPCSR"), + Close + (qVar"state", + Let(qVar"s", + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("fpcsr", + TP[Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Var("value",CTy"FPCSR")]))]), + Let(qVar"s", + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])]))])), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")),LT])]))])))))) +; +val fpr_def = Def + ("fpr",Var("n",FTy 5), + Close + (qVar"state", + Apply + (Apply + (Dest("c_fpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5)))) +; +val write'fpr_def = Def + ("write'fpr",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + Rupd + ("c_fpr", + TP[qVar"state", + Fupd + (Dest("c_fpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state"), + Fupd + (Apply + (Dest("c_fpr",ATy(F8,ATy(FTy 5,F64)),qVar"state"), + Dest("procID",F8,qVar"state")),Var("n",FTy 5), + Var("value",F64)))]))) +; +val PC_def = Def + ("PC",qVar"state", + Apply + (Dest("c_PC",ATy(F8,F64),qVar"state"),Dest("procID",F8,qVar"state"))) +; +val write'PC_def = Def + ("write'PC",Var("value",F64), + Close + (qVar"state", + Rupd + ("c_PC", + TP[qVar"state", + Fupd + (Dest("c_PC",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",F64))]))) +; +val Skip_def = Def + ("Skip",qVar"state", + Apply + (Dest("c_Skip",ATy(F8,F64),qVar"state"),Dest("procID",F8,qVar"state"))) +; +val write'Skip_def = Def + ("write'Skip",Var("value",F64), + Close + (qVar"state", + Rupd + ("c_Skip", + TP[qVar"state", + Fupd + (Dest("c_Skip",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",F64))]))) +; +val UCSR_def = Def + ("UCSR",qVar"state", + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'UCSR_def = Def + ("write'UCSR",Var("value",CTy"UserCSR"), + Close + (qVar"state", + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",CTy"UserCSR"))]))) +; +val SCSR_def = Def + ("SCSR",qVar"state", + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'SCSR_def = Def + ("write'SCSR",Var("value",CTy"SupervisorCSR"), + Close + (qVar"state", + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",CTy"SupervisorCSR"))]))) +; +val HCSR_def = Def + ("HCSR",qVar"state", + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'HCSR_def = Def + ("write'HCSR",Var("value",CTy"HypervisorCSR"), + Close + (qVar"state", + Rupd + ("c_HCSR", + TP[qVar"state", + Fupd + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",CTy"HypervisorCSR"))]))) +; +val MCSR_def = Def + ("MCSR",qVar"state", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'MCSR_def = Def + ("write'MCSR",Var("value",CTy"MachineCSR"), + Close + (qVar"state", + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",CTy"MachineCSR"))]))) +; +val NextFetch_def = Def + ("NextFetch",qVar"state", + Apply + (Dest("c_NextFetch",ATy(F8,OTy(CTy"TransferControl")),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'NextFetch_def = Def + ("write'NextFetch",Var("value",OTy(CTy"TransferControl")), + Close + (qVar"state", + Rupd + ("c_NextFetch", + TP[qVar"state", + Fupd + (Dest + ("c_NextFetch",ATy(F8,OTy(CTy"TransferControl")), + qVar"state"),Dest("procID",F8,qVar"state"), + Var("value",OTy(CTy"TransferControl")))]))) +; +val ReserveLoad_def = Def + ("ReserveLoad",qVar"state", + Apply + (Dest("c_ReserveLoad",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'ReserveLoad_def = Def + ("write'ReserveLoad",Var("value",OTy F64), + Close + (qVar"state", + Rupd + ("c_ReserveLoad", + TP[qVar"state", + Fupd + (Dest("c_ReserveLoad",ATy(F8,OTy F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",OTy F64))]))) +; +val ExitCode_def = Def + ("ExitCode",qVar"state", + Apply + (Dest("c_ExitCode",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'ExitCode_def = Def + ("write'ExitCode",Var("value",F64), + Close + (qVar"state", + Rupd + ("c_ExitCode", + TP[qVar"state", + Fupd + (Dest("c_ExitCode",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",F64))]))) +; +val curArch_def = Def + ("curArch",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("architecture",ATy(qTy,PTy(CTy"Architecture",qTy)), + Dest + ("ArchBase",FTy 2, + Dest + ("mcpuid",CTy"mcpuid", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state")))), + qVar"state"))) +; +val in32BitMode_def = Def + ("in32BitMode",AVar uTy, + Close + (qVar"state", + Let(TP[Var("v",CTy"Architecture"),qVar"s"], + Apply + (Call("curArch",ATy(qTy,PTy(CTy"Architecture",qTy)),LU), + qVar"state"), + TP[EQ(Var("v",CTy"Architecture"),LC("RV32I",CTy"Architecture")), + qVar"s"]))) +; +val curPrivilege_def = Def + ("curPrivilege",AVar uTy, + Close + (qVar"state", + Call + ("privilege",CTy"Privilege", + Dest + ("MPRV",FTy 2, + Dest + ("mstatus",CTy"mstatus", + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state")))))) +; +val curEPC_def = Def + ("curEPC",AVar uTy, + Close + (qVar"state", + CS(Apply + (Call("curPrivilege",ATy(qTy,CTy"Privilege"),LU),qVar"state"), + [(LC("User",CTy"Privilege"), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(F64,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception",LS"No EPC in U-mode")), + qVar"state")), + (LC("Supervisor",CTy"Privilege"), + TP[Dest + ("sepc",F64, + Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")),qVar"state")), + qVar"state"]), + (LC("Hypervisor",CTy"Privilege"), + TP[Dest + ("hepc",F64, + Apply + (Const("HCSR",ATy(qTy,CTy"HypervisorCSR")),qVar"state")), + qVar"state"]), + (LC("Machine",CTy"Privilege"), + TP[Dest + ("mepc",F64, + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state")), + qVar"state"])]))) +; +val sendIPI_def = Def + ("sendIPI",Var("core",F64), + Close + (qVar"state", + Let(Var("id",F8),Mop(Cast F8,Var("core",F64)), + ITE(Bop(Lt,Mop(Cast nTy,Var("id",F8)), + Dest("totalCore",nTy,qVar"state")), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Var("id",F8)), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Var("id",F8), + Rupd + ("mip", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSIP", + TP[Dest + ("mip",CTy"mip", + Var("v",CTy"MachineCSR")),LT])]))])), + qVar"state")))) +; +val rnd_mode_static_def = Def + ("rnd_mode_static",Var("rnd",FTy 3), + CS(Var("rnd",FTy 3), + [(LW(0,3),Mop(Some,LC("RNE",CTy"Rounding"))), + (LW(1,3),Mop(Some,LC("RTZ",CTy"Rounding"))), + (LW(2,3),Mop(Some,LC("RDN",CTy"Rounding"))), + (LW(3,3),Mop(Some,LC("RUP",CTy"Rounding"))), + (LW(4,3),Mop(Some,LC("RMM",CTy"Rounding"))), + (LW(7,3),Mop(Some,LC("RDYN",CTy"Rounding"))), + (AVar(FTy 3),LO(CTy"Rounding"))])) +; +val rnd_mode_dynamic_def = Def + ("rnd_mode_dynamic",Var("rnd",FTy 3), + CS(Var("rnd",FTy 3), + [(LW(0,3),Mop(Some,LC("RNE",CTy"Rounding"))), + (LW(1,3),Mop(Some,LC("RTZ",CTy"Rounding"))), + (LW(2,3),Mop(Some,LC("RDN",CTy"Rounding"))), + (LW(3,3),Mop(Some,LC("RUP",CTy"Rounding"))), + (LW(4,3),Mop(Some,LC("RMM",CTy"Rounding"))), + (AVar(FTy 3),LO(CTy"Rounding"))])) +; +val l3round_def = Def + ("l3round",Var("rnd",CTy"Rounding"), + CS(Var("rnd",CTy"Rounding"), + [(LC("RNE",CTy"Rounding"), + Mop(Some,binary_ieeeSyntax.roundTiesToEven_tm)), + (LC("RTZ",CTy"Rounding"), + Mop(Some,binary_ieeeSyntax.roundTowardZero_tm)), + (LC("RDN",CTy"Rounding"), + Mop(Some,binary_ieeeSyntax.roundTowardNegative_tm)), + (LC("RUP",CTy"Rounding"), + Mop(Some,binary_ieeeSyntax.roundTowardPositive_tm)), + (LC("RMM",CTy"Rounding"),LO rTy),(LC("RDYN",CTy"Rounding"),LO rTy)])) +; +val round_def = Def + ("round",Var("rnd",FTy 3), + Close + (qVar"state", + CS(Call("rnd_mode_static",OTy(CTy"Rounding"),Var("rnd",FTy 3)), + [(Mop(Some,LC("RDYN",CTy"Rounding")), + CS(Call + ("rnd_mode_dynamic",OTy(CTy"Rounding"), + Dest + ("FRM",FTy 3, + Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"))), + [(Mop(Some,Var("frm",CTy"Rounding")), + Call("l3round",OTy rTy,Var("frm",CTy"Rounding"))), + (LO(CTy"Rounding"),LO rTy)])), + (Mop(Some,Var("frm",CTy"Rounding")), + Call("l3round",OTy rTy,Var("frm",CTy"Rounding"))), + (LO(CTy"Rounding"),LO rTy)]))) +; +val RV32_CanonicalNan_def = Def0 ("RV32_CanonicalNan",LW(2143289344,32)) +; +val RV64_CanonicalNan_def = Def0 + ("RV64_CanonicalNan",LW(9221120237041090560,64)) +; +val FP32_IsSignalingNan_def = Def + ("FP32_IsSignalingNan",Var("x",F32), + Bop(And,EQ(EX(Var("x",F32),LN 30,LN 23,F8),LW(255,8)), + Bop(And,EQ(Bop(Bit,Var("x",F32),LN 22),LF), + Mop(Not,EQ(EX(Var("x",F32),LN 21,LN 0,FTy 22),LW(0,22)))))) +; +val FP64_IsSignalingNan_def = Def + ("FP64_IsSignalingNan",Var("x",F64), + Bop(And,EQ(EX(Var("x",F64),LN 62,LN 52,FTy 11),LW(2047,11)), + Bop(And,EQ(Bop(Bit,Var("x",F64),LN 51),LF), + Mop(Not,EQ(EX(Var("x",F64),LN 50,LN 0,FTy 51),LW(0,51)))))) +; +val FP32_Sign_def = Def + ("FP32_Sign",Var("x",F32),Bop(Bit,Var("x",F32),LN 31)) +; +val FP64_Sign_def = Def + ("FP64_Sign",Var("x",F64),Bop(Bit,Var("x",F64),LN 63)) +; +val setFP_Invalid_def = Def + ("setFP_Invalid",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("write'fcsr",ATy(qTy,qTy), + Rupd + ("NV", + TP[Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"),LT])), + qVar"state"))) +; +val setFP_DivZero_def = Def + ("setFP_DivZero",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("write'fcsr",ATy(qTy,qTy), + Rupd + ("DZ", + TP[Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"),LT])), + qVar"state"))) +; +val setFP_Overflow_def = Def + ("setFP_Overflow",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("write'fcsr",ATy(qTy,qTy), + Rupd + ("OF", + TP[Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"),LT])), + qVar"state"))) +; +val setFP_Underflow_def = Def + ("setFP_Underflow",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("write'fcsr",ATy(qTy,qTy), + Rupd + ("OF", + TP[Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"),LT])), + qVar"state"))) +; +val setFP_Inexact_def = Def + ("setFP_Inexact",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("write'fcsr",ATy(qTy,qTy), + Rupd + ("OF", + TP[Apply(Const("fcsr",ATy(qTy,CTy"FPCSR")),qVar"state"),LT])), + qVar"state"))) +; +val csrRW_def = Def + ("csrRW",Var("csr",FTy 12),EX(Var("csr",FTy 12),LN 11,LN 10,FTy 2)) +; +val csrPR_def = Def + ("csrPR",Var("csr",FTy 12),EX(Var("csr",FTy 12),LN 9,LN 8,FTy 2)) +; +val check_CSR_access_def = Def + ("check_CSR_access", + TP[Var("rw",FTy 2),Var("pr",FTy 2),Var("p",CTy"Privilege"), + Var("a",CTy"accessType")], + Bop(And, + Bop(Or,EQ(Var("a",CTy"accessType"),LC("Read",CTy"accessType")), + Mop(Not,EQ(Var("rw",FTy 2),LW(3,2)))), + Bop(Uge,Call("privLevel",FTy 2,Var("p",CTy"Privilege")), + Var("pr",FTy 2)))) +; +val is_CSR_defined_def = Def + ("is_CSR_defined",Var("csr",FTy 12), + Close + (qVar"state", + ITB([(Bop(And,Bop(Ge,Var("csr",FTy 12),LW(1,12)), + Bop(Le,Var("csr",FTy 12),LW(3,12))),TP[LT,qVar"state"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(3072,12)), + Bop(Le,Var("csr",FTy 12),LW(3074,12))),TP[LT,qVar"state"])], + Let(TP[bVar"v",qVar"s"], + ITE(Bop(Ge,Var("csr",FTy 12),LW(3200,12)), + ITE(Bop(Le,Var("csr",FTy 12),LW(3202,12)), + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU), + qVar"state"),TP[LF,qVar"state"]), + TP[LF,qVar"state"]), + ITB([(bVar"v",TP[LT,qVar"s"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(256,12)), + Bop(Le,Var("csr",FTy 12),LW(257,12))), + TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(260,12)),TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(289,12)),TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(3329,12)),TP[LT,qVar"s"])], + Let(TP[bVar"v",qVar"s"], + ITE(EQ(Var("csr",FTy 12),LW(3457,12)), + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s"),TP[LF,qVar"s"]), + ITB([(bVar"v",TP[LT,qVar"s"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(320,12)), + Bop(Le,Var("csr",FTy 12),LW(321,12))), + TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(324,12)), + TP[LT,qVar"s"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(3394,12)), + Bop(Le,Var("csr",FTy 12),LW(3395,12))), + TP[LT,qVar"s"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(384,12)), + Bop(Le,Var("csr",FTy 12),LW(385,12))), + TP[LT,qVar"s"]), + (Bop(And,Bop(Ge,Var("csr",FTy 12),LW(2304,12)), + Bop(Le,Var("csr",FTy 12),LW(2306,12))), + TP[LT,qVar"s"])], + Let(TP[bVar"v",qVar"s"], + ITE(Bop(Ge,Var("csr",FTy 12),LW(2432,12)), + ITE(Bop(Le,Var("csr",FTy 12),LW(2434,12)), + Apply + (Call + ("in32BitMode", + ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s"),TP[LF,qVar"s"]), + TP[LF,qVar"s"]), + ITB([(bVar"v",TP[LT,qVar"s"]), + (Bop(And, + Bop(Ge,Var("csr",FTy 12), + LW(3840,12)), + Bop(Le,Var("csr",FTy 12), + LW(3841,12))),TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(3856,12)), + TP[LT,qVar"s"]), + (Bop(And, + Bop(Ge,Var("csr",FTy 12), + LW(768,12)), + Bop(Le,Var("csr",FTy 12), + LW(770,12))),TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(772,12)), + TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(801,12)), + TP[LT,qVar"s"]), + (EQ(Var("csr",FTy 12),LW(1793,12)), + TP[LT,qVar"s"])], + Let(TP[bVar"v",qVar"s"], + ITE(EQ(Var("csr",FTy 12),LW(1857,12)), + Apply + (Call + ("in32BitMode", + ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s"),TP[LF,qVar"s"]), + ITB([(bVar"v",TP[LT,qVar"s"]), + (Bop(And, + Bop(Ge,Var("csr",FTy 12), + LW(832,12)), + Bop(Le,Var("csr",FTy 12), + LW(836,12))), + TP[LT,qVar"s"]), + (Bop(And, + Bop(Ge,Var("csr",FTy 12), + LW(896,12)), + Bop(Le,Var("csr",FTy 12), + LW(901,12))), + TP[LT,qVar"s"]), + (Bop(Ge,Var("csr",FTy 12), + LW(2817,12)), + TP[LT,qVar"s"])], + Let(TP[bVar"v",qVar"s"], + ITE(EQ(Var("csr",FTy 12), + LW(2945,12)), + Apply + (Call + ("in32BitMode", + ATy(qTy, + PTy(bTy,qTy)), + LU),qVar"s"), + TP[LF,qVar"s"]), + TP[Bop(Or,bVar"v", + Bop(And, + Bop(Ge, + Var("csr", + FTy 12), + LW(1920,12)), + Bop(And, + Bop(Le, + Var("csr", + FTy 12), + LW(1923, + 12)), + Mop(Not, + EQ(Var("csr", + FTy 12), + LW(1922, + 12)))))), + qVar"s"])))))))))))) +; +val CSRMap_def = Def + ("CSRMap",Var("csr",FTy 12), + Close + (qVar"state", + CS(Var("csr",FTy 12), + [(LW(1,12), + TP[Mop(Cast F64, + EX(Call + ("reg'FPCSR",F32, + Dest + ("fpcsr",CTy"FPCSR", + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),LN 4,LN 0, + FTy 5)),qVar"state"]), + (LW(2,12), + TP[Mop(Cast F64, + Dest + ("FRM",FTy 3, + Dest + ("fpcsr",CTy"FPCSR", + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))))),qVar"state"]), + (LW(3,12), + TP[Mop(Cast F64, + EX(Call + ("reg'FPCSR",F32, + Dest + ("fpcsr",CTy"FPCSR", + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),LN 7,LN 0, + F8)),qVar"state"]), + (LW(3072,12), + TP[Bop(Add, + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("cycle_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3073,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("time_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3074,12), + TP[Bop(Add, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("instret_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3200,12), + TP[Mop(SE F64, + EX(Bop(Add, + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("cycle_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(3201,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("time_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(3202,12), + TP[Mop(SE F64, + EX(Bop(Add, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("instret_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(256,12), + TP[Call + ("reg'sstatus",F64, + Call + ("lift_mstatus_sstatus",CTy"sstatus", + Dest + ("mstatus",CTy"mstatus", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))))),qVar"state"]), + (LW(257,12), + TP[Dest + ("stvec",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(260,12), + TP[Call + ("reg'sie",F64, + Call + ("lift_mie_sie",CTy"sie", + Dest + ("mie",CTy"mie", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))))),qVar"state"]), + (LW(289,12), + TP[Dest + ("stimecmp",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(3329,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("stime_delta",F64, + Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3457,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("stime_delta",F64, + Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(320,12), + TP[Dest + ("sscratch",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(321,12), + TP[Dest + ("sepc",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(3394,12), + TP[Call + ("reg'mcause",F64, + Dest + ("scause",CTy"mcause", + Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3395,12), + TP[Dest + ("sbadaddr",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(324,12), + TP[Call + ("reg'sip",F64, + Call + ("lift_mip_sip",CTy"sip", + Dest + ("mip",CTy"mip", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))))),qVar"state"]), + (LW(384,12), + TP[Dest + ("sptbr",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(385,12), + TP[Dest + ("sasid",F64, + Apply + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(2304,12), + TP[Bop(Add, + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("cycle_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(2305,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("time_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(2306,12), + TP[Bop(Add, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("instret_delta",F64, + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(2432,12), + TP[Mop(SE F64, + EX(Bop(Add, + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("cycle_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(2433,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("time_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(2434,12), + TP[Mop(SE F64, + EX(Bop(Add, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")), + Dest + ("instret_delta",F64, + Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(512,12), + TP[Call + ("reg'mstatus",F64, + Dest + ("hstatus",CTy"mstatus", + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(513,12), + TP[Dest + ("htvec",F64, + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(514,12), + TP[Call + ("reg'mtdeleg",F64, + Dest + ("htdeleg",CTy"mtdeleg", + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(545,12), + TP[Dest + ("htimecmp",F64, + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(3585,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("htime_delta",F64, + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3713,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("htime_delta",F64, + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(576,12), + TP[Dest + ("hscratch",F64, + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(577,12), + TP[Dest + ("hepc",F64, + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(578,12), + TP[Call + ("reg'mcause",F64, + Dest + ("hcause",CTy"mcause", + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(579,12), + TP[Dest + ("hbadaddr",F64, + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(2561,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("stime_delta",F64, + Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(2689,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("stime_delta",F64, + Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(3840,12), + TP[Call + ("reg'mcpuid",F64, + Dest + ("mcpuid",CTy"mcpuid", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3841,12), + TP[Call + ("reg'mimpid",F64, + Dest + ("mimpid",CTy"mimpid", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(3856,12), + TP[Dest + ("mhartid",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(768,12), + TP[Call + ("reg'mstatus",F64, + Dest + ("mstatus",CTy"mstatus", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(769,12), + TP[Dest + ("mtvec",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(770,12), + TP[Call + ("reg'mtdeleg",F64, + Dest + ("mtdeleg",CTy"mtdeleg", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(772,12), + TP[Call + ("reg'mie",F64, + Dest + ("mie",CTy"mie", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(801,12), + TP[Dest + ("mtimecmp",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(1793,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("mtime_delta",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(1857,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("mtime_delta",F64, + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(832,12), + TP[Dest + ("mscratch",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(833,12), + TP[Dest + ("mepc",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(834,12), + TP[Call + ("reg'mcause",F64, + Dest + ("mcause",CTy"mcause", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(835,12), + TP[Dest + ("mbadaddr",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(836,12), + TP[Call + ("reg'mip",F64, + Dest + ("mip",CTy"mip", + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(896,12), + TP[Dest + ("mbase",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(897,12), + TP[Dest + ("mbound",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(898,12), + TP[Dest + ("mibase",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(899,12), + TP[Dest + ("mibound",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(900,12), + TP[Dest + ("mdbase",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(901,12), + TP[Dest + ("mdbound",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(2817,12), + TP[Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("htime_delta",F64, + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")))),qVar"state"]), + (LW(2945,12), + TP[Mop(SE F64, + EX(Bop(Add,Dest("clock",F64,qVar"state"), + Dest + ("htime_delta",F64, + Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))),LN 63, + LN 32,F32)),qVar"state"]), + (LW(1920,12), + TP[Dest + ("mtohost",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(1921,12), + TP[Dest + ("mfromhost",F64, + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"))),qVar"state"]), + (LW(1923,12),TP[LW(0,64),qVar"state"]), + (AVar(FTy 12), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(F64,qTy)), + Call + ("UNDEFINED",CTy"exception", + CC[LS"unexpected CSR read at ", + Mop(Cast sTy,Var("csr",FTy 12))])),qVar"state"))]))) +; +val write'CSRMap_def = Def + ("write'CSRMap",TP[Var("value",F64),Var("csr",FTy 12)], + Close + (qVar"state", + CS(Var("csr",FTy 12), + [(LW(1,12), + Let(qVar"s", + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Let(Var("x1",CTy"FPCSR"), + Dest("fpcsr",CTy"FPCSR",Var("v",CTy"UserCSR")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"), + qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("fpcsr", + TP[Var("v",CTy"UserCSR"), + Call + ("write'reg'FPCSR",CTy"FPCSR", + TP[Var("x1",CTy"FPCSR"), + BFI(LN 4,LN 0, + EX(Var("value",F64),LN 4, + LN 0,FTy 5), + Call + ("reg'FPCSR",F32, + Var("x1",CTy"FPCSR")))])]))]))), + Let(qVar"s", + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])]))])), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + LT])]))]))))), + (LW(2,12), + Let(qVar"s", + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("fpcsr", + TP[Var("v",CTy"UserCSR"), + Rupd + ("FRM", + TP[Dest + ("fpcsr",CTy"FPCSR", + Var("v",CTy"UserCSR")), + EX(Var("value",F64),LN 2,LN 0, + FTy 3)])]))])), + Let(qVar"s", + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])]))])), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + LT])]))]))))), + (LW(3,12), + Let(qVar"s", + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("fpcsr", + TP[Var("v",CTy"UserCSR"), + Call + ("write'reg'FPCSR",CTy"FPCSR", + TP[Dest + ("fpcsr",CTy"FPCSR", + Var("v",CTy"UserCSR")), + EX(Var("value",F64),LN 31,LN 0,F32)])]))])), + Let(qVar"s", + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])]))])), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"s"),Dest("procID",F8,qVar"s"), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + LT])]))]))))), + (LW(256,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mstatus", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call + ("lower_sstatus_mstatus",CTy"mstatus", + TP[Call + ("rec'sstatus",CTy"sstatus", + Var("value",F64)), + Dest + ("mstatus",CTy"mstatus", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))])]))])), + (LW(257,12), + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("stvec", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(260,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mie", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call + ("lower_sie_mie",CTy"mie", + TP[Call("rec'sie",CTy"sie",Var("value",F64)), + Dest + ("mie",CTy"mie", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))])]))])), + (LW(289,12), + Let(qVar"s", + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("stimecmp", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")), + Var("value",F64)]))]), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s"), + Rupd + ("mip", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("STIP", + TP[Dest + ("mip",CTy"mip", + Var("v",CTy"MachineCSR")),LF])]))])))), + (LW(320,12), + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("sscratch", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(321,12), + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("sepc", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Bop(BAnd,Var("value",F64),Mop(SE F64,LW(4,3)))]))])), + (LW(324,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mip", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call + ("lower_sip_mip",CTy"mip", + TP[Call("rec'sip",CTy"sip",Var("value",F64)), + Dest + ("mip",CTy"mip", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")))])]))])), + (LW(384,12), + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("sptbr", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(385,12), + Rupd + ("c_SCSR", + TP[qVar"state", + Fupd + (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("sasid", + TP[Apply + (Dest + ("c_SCSR",ATy(F8,CTy"SupervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(2304,12), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("cycle_delta", + TP[Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Bop(Sub,Var("value",F64), + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")))]))])), + (LW(2305,12), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("time_delta", + TP[Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Bop(Sub,Var("value",F64), + Dest("clock",F64,qVar"state"))]))])), + (LW(2306,12), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("instret_delta", + TP[Apply + (Dest + ("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Bop(Sub,Var("value",F64), + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")))]))])), + (LW(2432,12), + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("cycle_delta", + TP[Var("v",CTy"UserCSR"), + BFI(LN 63,LN 32, + Bop(Lsl, + Bop(Sub, + EX(Var("value",F64),LN 31,LN 0, + F32), + EX(Apply + (Dest + ("c_cycles",ATy(F8,F64), + qVar"state"), + Dest + ("procID",F8,qVar"state")), + LN 63,LN 32,F32)),LN 32), + Dest + ("cycle_delta",F64, + Var("v",CTy"UserCSR")))]))]))), + (LW(2433,12), + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("time_delta", + TP[Var("v",CTy"UserCSR"), + BFI(LN 63,LN 32, + Bop(Lsl, + Bop(Sub, + EX(Var("value",F64),LN 31,LN 0, + F32), + EX(Dest("clock",F64,qVar"state"), + LN 63,LN 32,F32)),LN 32), + Dest + ("time_delta",F64, + Var("v",CTy"UserCSR")))]))]))), + (LW(2434,12), + Let(Var("v",CTy"UserCSR"), + Apply + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_UCSR", + TP[qVar"state", + Fupd + (Dest("c_UCSR",ATy(F8,CTy"UserCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("instret_delta", + TP[Var("v",CTy"UserCSR"), + BFI(LN 63,LN 32, + Bop(Lsl, + Bop(Sub, + EX(Var("value",F64),LN 31,LN 0, + F32), + EX(Apply + (Dest + ("c_instret", + ATy(F8,F64),qVar"state"), + Dest + ("procID",F8,qVar"state")), + LN 63,LN 32,F32)),LN 32), + Dest + ("instret_delta",F64, + Var("v",CTy"UserCSR")))]))]))), + (LW(768,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mstatus", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call + ("update_mstatus",CTy"mstatus", + TP[Dest + ("mstatus",CTy"mstatus", + Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state"))), + Call + ("rec'mstatus",CTy"mstatus", + Var("value",F64))])]))])), + (LW(769,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtvec", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(770,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtdeleg", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call + ("rec'mtdeleg",CTy"mtdeleg",Var("value",F64))]))])), + (LW(772,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mie", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call("rec'mie",CTy"mie",Var("value",F64))]))])), + (LW(801,12), + Let(qVar"s", + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtimecmp", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"), + Dest("procID",F8,qVar"state")), + Var("value",F64)]))]), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s")), + Rupd + ("c_MCSR", + TP[qVar"s", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"s"), + Dest("procID",F8,qVar"s"), + Rupd + ("mip", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MTIP", + TP[Dest + ("mip",CTy"mip", + Var("v",CTy"MachineCSR")),LF])]))])))), + (LW(1793,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtime_delta", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Bop(Sub,Var("value",F64), + Dest("clock",F64,qVar"state"))]))])), + (LW(1857,12), + Let(Var("v",CTy"MachineCSR"), + Apply + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtime_delta", + TP[Var("v",CTy"MachineCSR"), + BFI(LN 63,LN 32, + Bop(Lsl, + Bop(Sub, + EX(Var("value",F64),LN 31,LN 0, + F32), + EX(Dest("clock",F64,qVar"state"), + LN 63,LN 32,F32)),LN 32), + Dest + ("mtime_delta",F64, + Var("v",CTy"MachineCSR")))]))]))), + (LW(832,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mscratch", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(833,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mepc", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Bop(BAnd,Var("value",F64),Mop(SE F64,LW(4,3)))]))])), + (LW(834,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mcause", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call("rec'mcause",CTy"mcause",Var("value",F64))]))])), + (LW(835,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mbadaddr", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(836,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mip", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Call("rec'mip",CTy"mip",Var("value",F64))]))])), + (LW(896,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mbase", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(897,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mbound", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(898,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mibase", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(899,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mibound", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(900,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mdbase", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(901,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mdbound", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(2817,12), + Rupd + ("c_HCSR", + TP[qVar"state", + Fupd + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("htime_delta", + TP[Apply + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Bop(Sub,Var("value",F64), + Dest("clock",F64,qVar"state"))]))])), + (LW(2945,12), + Let(Var("v",CTy"HypervisorCSR"), + Apply + (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state")), + Rupd + ("c_HCSR", + TP[qVar"state", + Fupd + (Dest + ("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("htime_delta", + TP[Var("v",CTy"HypervisorCSR"), + BFI(LN 63,LN 32, + Bop(Lsl, + Bop(Sub, + EX(Var("value",F64),LN 31,LN 0, + F32), + EX(Dest("clock",F64,qVar"state"), + LN 63,LN 32,F32)),LN 32), + Dest + ("htime_delta",F64, + Var("v",CTy"HypervisorCSR")))]))]))), + (LW(1920,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mtohost", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(1921,12), + Rupd + ("c_MCSR", + TP[qVar"state", + Fupd + (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), + Dest("procID",F8,qVar"state"), + Rupd + ("mfromhost", + TP[Apply + (Dest + ("c_MCSR",ATy(F8,CTy"MachineCSR"), + qVar"state"),Dest("procID",F8,qVar"state")), + Var("value",F64)]))])), + (LW(1923,12), + Apply + (Call("sendIPI",ATy(qTy,qTy),Var("value",F64)),qVar"state")), + (AVar(FTy 12), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + CC[LS"unexpected CSR write to ", + Mop(Cast sTy,Var("csr",FTy 12))])),qVar"state")))]))) +; +val csrName_def = Def + ("csrName",Var("csr",FTy 12), + CS(Var("csr",FTy 12), + [(LW(1,12),LS"fflags"),(LW(2,12),LS"frm"),(LW(3,12),LS"fcsr"), + (LW(3072,12),LS"cycle"),(LW(3073,12),LS"time"), + (LW(3074,12),LS"instret"),(LW(3200,12),LS"cycleh"), + (LW(3201,12),LS"timeh"),(LW(3202,12),LS"instreth"), + (LW(256,12),LS"sstatus"),(LW(257,12),LS"stvec"), + (LW(260,12),LS"sie"),(LW(289,12),LS"stimecmp"), + (LW(3329,12),LS"stime"),(LW(3457,12),LS"stimeh"), + (LW(320,12),LS"sscratch"),(LW(321,12),LS"sepc"), + (LW(3394,12),LS"scause"),(LW(3395,12),LS"sbadaddr"), + (LW(324,12),LS"mip"),(LW(384,12),LS"sptbr"),(LW(385,12),LS"sasid"), + (LW(2304,12),LS"cycle"),(LW(2305,12),LS"time"), + (LW(2306,12),LS"instret"),(LW(2432,12),LS"cycleh"), + (LW(2433,12),LS"timeh"),(LW(2434,12),LS"instreth"), + (LW(512,12),LS"hstatus"),(LW(513,12),LS"htvec"), + (LW(514,12),LS"htdeleg"),(LW(545,12),LS"htimecmp"), + (LW(3585,12),LS"htime"),(LW(3713,12),LS"htimeh"), + (LW(576,12),LS"hscratch"),(LW(577,12),LS"hepc"), + (LW(578,12),LS"hcause"),(LW(579,12),LS"hbadaddr"), + (LW(2561,12),LS"stime"),(LW(2689,12),LS"stimeh"), + (LW(3840,12),LS"mcpuid"),(LW(3841,12),LS"mimpid"), + (LW(3856,12),LS"mhartid"),(LW(768,12),LS"mstatus"), + (LW(769,12),LS"mtvec"),(LW(770,12),LS"mtdeleg"), + (LW(772,12),LS"mie"),(LW(801,12),LS"mtimecmp"), + (LW(1793,12),LS"mtime"),(LW(1857,12),LS"mtimeh"), + (LW(832,12),LS"mscratch"),(LW(833,12),LS"mepc"), + (LW(834,12),LS"mcause"),(LW(835,12),LS"mbadaddr"), + (LW(836,12),LS"mip"),(LW(896,12),LS"mbase"), + (LW(897,12),LS"mbound"),(LW(898,12),LS"mibase"), + (LW(899,12),LS"mibound"),(LW(900,12),LS"mdbase"), + (LW(901,12),LS"mdbound"),(LW(2817,12),LS"htime"), + (LW(2945,12),LS"htimeh"),(LW(1920,12),LS"mtohost"), + (LW(1921,12),LS"mfromhost"),(LW(1923,12),LS"send_ipi"), + (AVar(FTy 12),LS"UNKNOWN")])) +; +val Delta_def = Def + ("Delta",qVar"state", + Apply + (Dest("c_update",ATy(F8,CTy"StateDelta"),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'Delta_def = Def + ("write'Delta",Var("value",CTy"StateDelta"), + Close + (qVar"state", + Rupd + ("c_update", + TP[qVar"state", + Fupd + (Dest("c_update",ATy(F8,CTy"StateDelta"),qVar"state"), + Dest("procID",F8,qVar"state"),Var("value",CTy"StateDelta"))]))) +; +val hex32_def = Def + ("hex32",Var("x",F32), + Mop(PadLeft,TP[LSC #"0",LN 8,Mop(Cast sTy,Var("x",F32))])) +; +val hex64_def = Def + ("hex64",Var("x",F64), + Mop(PadLeft,TP[LSC #"0",LN 16,Mop(Cast sTy,Var("x",F64))])) +; +val log_w_csr_def = Def + ("log_w_csr",TP[Var("csr",FTy 12),Var("data",F64)], + CC[LS"CSR (",Call("csrName",sTy,Var("csr",FTy 12)),LS") <- 0x", + Call("hex64",sTy,Var("data",F64))]) +; +val reg_def = Def + ("reg",Var("r",FTy 5), + ITB([(EQ(Var("r",FTy 5),LW(0,5)),LS"$0"), + (EQ(Var("r",FTy 5),LW(1,5)),LS"ra"), + (EQ(Var("r",FTy 5),LW(2,5)),LS"sp"), + (EQ(Var("r",FTy 5),LW(3,5)),LS"gp"), + (EQ(Var("r",FTy 5),LW(4,5)),LS"tp"), + (EQ(Var("r",FTy 5),LW(5,5)),LS"t0"), + (EQ(Var("r",FTy 5),LW(6,5)),LS"t1"), + (EQ(Var("r",FTy 5),LW(7,5)),LS"t2"), + (EQ(Var("r",FTy 5),LW(8,5)),LS"fp"), + (EQ(Var("r",FTy 5),LW(9,5)),LS"s1"), + (EQ(Var("r",FTy 5),LW(10,5)),LS"a0"), + (EQ(Var("r",FTy 5),LW(11,5)),LS"a1"), + (EQ(Var("r",FTy 5),LW(12,5)),LS"a2"), + (EQ(Var("r",FTy 5),LW(13,5)),LS"a3"), + (EQ(Var("r",FTy 5),LW(14,5)),LS"a4"), + (EQ(Var("r",FTy 5),LW(15,5)),LS"a5"), + (EQ(Var("r",FTy 5),LW(16,5)),LS"a6"), + (EQ(Var("r",FTy 5),LW(17,5)),LS"a7"), + (EQ(Var("r",FTy 5),LW(18,5)),LS"s2"), + (EQ(Var("r",FTy 5),LW(19,5)),LS"s3"), + (EQ(Var("r",FTy 5),LW(20,5)),LS"s4"), + (EQ(Var("r",FTy 5),LW(21,5)),LS"s5"), + (EQ(Var("r",FTy 5),LW(22,5)),LS"s6"), + (EQ(Var("r",FTy 5),LW(23,5)),LS"s7"), + (EQ(Var("r",FTy 5),LW(24,5)),LS"s8"), + (EQ(Var("r",FTy 5),LW(25,5)),LS"s9"), + (EQ(Var("r",FTy 5),LW(26,5)),LS"s10"), + (EQ(Var("r",FTy 5),LW(27,5)),LS"s11"), + (EQ(Var("r",FTy 5),LW(28,5)),LS"t3"), + (EQ(Var("r",FTy 5),LW(29,5)),LS"t4"), + (EQ(Var("r",FTy 5),LW(30,5)),LS"t5")],LS"t6")) +; +val fpreg_def = Def + ("fpreg",Var("r",FTy 5), + ITB([(EQ(Var("r",FTy 5),LW(0,5)),LS"fs0"), + (EQ(Var("r",FTy 5),LW(1,5)),LS"fs1"), + (EQ(Var("r",FTy 5),LW(2,5)),LS"fs2"), + (EQ(Var("r",FTy 5),LW(3,5)),LS"fs3"), + (EQ(Var("r",FTy 5),LW(4,5)),LS"fs4"), + (EQ(Var("r",FTy 5),LW(5,5)),LS"fs5"), + (EQ(Var("r",FTy 5),LW(6,5)),LS"fs6"), + (EQ(Var("r",FTy 5),LW(7,5)),LS"fs7"), + (EQ(Var("r",FTy 5),LW(8,5)),LS"fs8"), + (EQ(Var("r",FTy 5),LW(9,5)),LS"fs9"), + (EQ(Var("r",FTy 5),LW(10,5)),LS"fs10"), + (EQ(Var("r",FTy 5),LW(11,5)),LS"fs11"), + (EQ(Var("r",FTy 5),LW(12,5)),LS"fs12"), + (EQ(Var("r",FTy 5),LW(13,5)),LS"fs13"), + (EQ(Var("r",FTy 5),LW(14,5)),LS"fs14"), + (EQ(Var("r",FTy 5),LW(15,5)),LS"fs15"), + (EQ(Var("r",FTy 5),LW(16,5)),LS"fv0"), + (EQ(Var("r",FTy 5),LW(17,5)),LS"fv1"), + (EQ(Var("r",FTy 5),LW(18,5)),LS"fa0"), + (EQ(Var("r",FTy 5),LW(19,5)),LS"fa1"), + (EQ(Var("r",FTy 5),LW(20,5)),LS"fa2"), + (EQ(Var("r",FTy 5),LW(21,5)),LS"fa3"), + (EQ(Var("r",FTy 5),LW(22,5)),LS"fa4"), + (EQ(Var("r",FTy 5),LW(23,5)),LS"fa5"), + (EQ(Var("r",FTy 5),LW(24,5)),LS"fa6"), + (EQ(Var("r",FTy 5),LW(25,5)),LS"fa7"), + (EQ(Var("r",FTy 5),LW(26,5)),LS"ft0"), + (EQ(Var("r",FTy 5),LW(27,5)),LS"ft1"), + (EQ(Var("r",FTy 5),LW(28,5)),LS"ft2"), + (EQ(Var("r",FTy 5),LW(29,5)),LS"ft3"), + (EQ(Var("r",FTy 5),LW(30,5)),LS"ft4")],LS"ft5")) +; +val log_w_gpr_def = Def + ("log_w_gpr",TP[Var("r",FTy 5),Var("data",F64)], + CC[LS"Reg ",Call("reg",sTy,Var("r",FTy 5)),LS" (", + Mop(Cast sTy,Mop(Cast nTy,Var("r",FTy 5))),LS") <- 0x", + Call("hex64",sTy,Var("data",F64))]) +; +val log_w_fprs_def = Def + ("log_w_fprs",TP[Var("r",FTy 5),Var("data",F32)], + CC[LS"FPR ",Call("reg",sTy,Var("r",FTy 5)),LS" (", + Mop(Cast sTy,Mop(Cast nTy,Var("r",FTy 5))),LS") <- 0x", + Call("hex32",sTy,Var("data",F32))]) +; +val log_w_fprd_def = Def + ("log_w_fprd",TP[Var("r",FTy 5),Var("data",F64)], + CC[LS"FPR ",Call("reg",sTy,Var("r",FTy 5)),LS" (", + Mop(Cast sTy,Mop(Cast nTy,Var("r",FTy 5))),LS") <- 0x", + Call("hex64",sTy,Var("data",F64))]) +; +val log_w_mem_mask_def = Def + ("log_w_mem_mask", + TP[Var("pAddrIdx",FTy 61),Var("vAddr",F64),Var("mask",F64), + Var("data",F64),Var("old",F64),Var("new",F64)], + CC[LS"MEM[0x",Call("hex64",sTy,Mop(Cast F64,Var("pAddrIdx",FTy 61))), + LS"/",Call("hex64",sTy,Var("vAddr",F64)),LS"] <- (data: 0x", + Call("hex64",sTy,Var("data",F64)),LS", mask: 0x", + Call("hex64",sTy,Var("mask",F64)),LS", old: 0x", + Call("hex64",sTy,Var("old",F64)),LS", new: 0x", + Call("hex64",sTy,Var("new",F64)),LS")"]) +; +val log_w_mem_mask_misaligned_def = Def + ("log_w_mem_mask_misaligned", + TP[Var("pAddrIdx",FTy 61),Var("vAddr",F64),Var("mask",F64), + Var("data",F64),nVar"align",Var("old",F64),Var("new",F64)], + CC[LS"MEM[0x",Call("hex64",sTy,Mop(Cast F64,Var("pAddrIdx",FTy 61))), + LS"/",Call("hex64",sTy,Var("vAddr",F64)),LS"/ misaligned@", + Mop(Cast sTy,nVar"align"),LS"] <- (data: 0x", + Call("hex64",sTy,Var("data",F64)),LS", mask: 0x", + Call("hex64",sTy,Var("mask",F64)),LS", old: 0x", + Call("hex64",sTy,Var("old",F64)),LS", new: 0x", + Call("hex64",sTy,Var("new",F64)),LS")"]) +; +val log_w_mem_def = Def + ("log_w_mem", + TP[Var("pAddrIdx",FTy 61),Var("vAddr",F64),Var("data",F64)], + CC[LS"MEM[0x",Call("hex64",sTy,Mop(Cast F64,Var("pAddrIdx",FTy 61))), + LS"/",Call("hex64",sTy,Var("vAddr",F64)),LS"] <- (data: 0x", + Call("hex64",sTy,Var("data",F64)),LS")"]) +; +val log_r_mem_def = Def + ("log_r_mem", + TP[Var("pAddrIdx",FTy 61),Var("vAddr",F64),Var("data",F64)], + CC[LS"data <- MEM[0x", + Mop(PadLeft,TP[LSC #"0",LN 10,Mop(Cast sTy,Var("pAddrIdx",FTy 61))]), + LS"/",Call("hex64",sTy,Var("vAddr",F64)),LS"]: 0x", + Call("hex64",sTy,Var("data",F64))]) +; +val log_exc_def = Def + ("log_exc",Var("e",CTy"ExceptionType"), + CC[LS" Exception ",Call("excName",sTy,Var("e",CTy"ExceptionType")), + LS" raised!"]) +; +val log_tohost_def = Def + ("log_tohost",Var("tohost",F64), + CC[LS"-> host: ", + Mop(Cast sTy,Mop(Cast cTy,EX(Var("tohost",F64),LN 7,LN 0,F8)))]) +; +val clear_logs_def = Def + ("clear_logs",AVar uTy, + Close(qVar"state",Rupd("log",TP[qVar"state",LNL(PTy(nTy,sTy))]))) +; +val setTrap_def = Def + ("setTrap",TP[Var("e",CTy"ExceptionType"),Var("badaddr",OTy F64)], + Close + (qVar"state", + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + Mop(Some, + Call + ("Trap",CTy"TransferControl", + Rupd + ("badaddr", + TP[Rupd + ("trap", + TP[LX(CTy"SynchronousTrap"), + Var("e",CTy"ExceptionType")]), + Var("badaddr",OTy F64)])))),qVar"state"))) +; +val signalException_def = Def + ("signalException",Var("e",CTy"ExceptionType"), + Close + (qVar"state", + Apply + (Call + ("setTrap",ATy(qTy,qTy),TP[Var("e",CTy"ExceptionType"),LO F64]), + qVar"state"))) +; +val signalAddressException_def = Def + ("signalAddressException", + TP[Var("e",CTy"ExceptionType"),Var("vAddr",F64)], + Close + (qVar"state", + Apply + (Call + ("setTrap",ATy(qTy,qTy), + TP[Var("e",CTy"ExceptionType"),Mop(Some,Var("vAddr",F64))]), + qVar"state"))) +; +val signalEnvCall_def = Def + ("signalEnvCall",AVar uTy, + Close + (qVar"state", + Apply + (Call + ("signalException",ATy(qTy,qTy), + CS(Call + ("privilege",CTy"Privilege", + Dest + ("MPRV",FTy 2, + Dest + ("mstatus",CTy"mstatus", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state")))), + [(LC("User",CTy"Privilege"), + LC("UMode_Env_Call",CTy"ExceptionType")), + (LC("Supervisor",CTy"Privilege"), + LC("SMode_Env_Call",CTy"ExceptionType")), + (LC("Hypervisor",CTy"Privilege"), + LC("HMode_Env_Call",CTy"ExceptionType")), + (LC("Machine",CTy"Privilege"), + LC("MMode_Env_Call",CTy"ExceptionType"))])),qVar"state"))) +; +val checkDelegation_def = tDef + ("checkDelegation", + TP[Var("curPriv",CTy"Privilege"),bVar"intr",Var("ec",F4)], + Close + (qVar"state", + Let(nVar"e",Mop(Cast nTy,Var("ec",F4)), + CS(Var("curPriv",CTy"Privilege"), + [(LC("User",CTy"Privilege"), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(CTy"Privilege",qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"No user-level delegation!")),qVar"state")), + (LC("Supervisor",CTy"Privilege"), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(CTy"Privilege",qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"No supervisor-level delegation!")),qVar"state")), + (LC("Hypervisor",CTy"Privilege"), + TP[ITE(Bop(Or, + Bop(And,bVar"intr", + Bop(Bit, + Dest + ("Intr_deleg",FTy 48, + Dest + ("htdeleg",CTy"mtdeleg", + Apply + (Const + ("HCSR", + ATy(qTy,CTy"HypervisorCSR")), + qVar"state"))),nVar"e")), + Bop(And,Mop(Not,bVar"intr"), + Bop(Bit, + Dest + ("Exc_deleg",F16, + Dest + ("htdeleg",CTy"mtdeleg", + Apply + (Const + ("HCSR", + ATy(qTy,CTy"HypervisorCSR")), + qVar"state"))),nVar"e"))), + LC("Supervisor",CTy"Privilege"), + Var("curPriv",CTy"Privilege")),qVar"state"]), + (LC("Machine",CTy"Privilege"), + ITE(Bop(Or, + Bop(And,bVar"intr", + Bop(Bit, + Dest + ("Intr_deleg",FTy 48, + Dest + ("mtdeleg",CTy"mtdeleg", + Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))),nVar"e")), + Bop(And,Mop(Not,bVar"intr"), + Bop(Bit, + Dest + ("Exc_deleg",F16, + Dest + ("mtdeleg",CTy"mtdeleg", + Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))),nVar"e"))), + Apply + (Call + ("checkDelegation", + ATy(qTy,PTy(CTy"Privilege",qTy)), + TP[LC("Hypervisor",CTy"Privilege"),bVar"intr", + Var("ec",F4)]),qVar"state"), + TP[Var("curPriv",CTy"Privilege"),qVar"state"]))]))), + Close + (Var("x",PTy(PTy(CTy"Privilege",PTy(bTy,F4)),qTy)), + CS(Var("x",PTy(PTy(CTy"Privilege",PTy(bTy,F4)),qTy)), + [(TP[TP[Var("curPriv",CTy"Privilege"),bVar"intr",Var("ec",F4)], + AVar qTy],Mop(Cast nTy,Var("curPriv",CTy"Privilege")))])), + SIMP_TAC std_ss [DB.theorem "Privilege2num_thm"] +) +; +val checkPrivInterrupt_def = Def + ("checkPrivInterrupt",Var("curPriv",CTy"Privilege"), + Close + (qVar"state", + Let(Var("v",CTy"mip"), + Dest + ("mip",CTy"mip", + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state")), + Let(Var("v0",CTy"mie"), + Dest + ("mie",CTy"mie", + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state")), + CS(Var("curPriv",CTy"Privilege"), + [(LC("User",CTy"Privilege"), + Apply + (Call + ("raise'exception", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt",CTy"Privilege")), + qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"No user-level interrupts!")),qVar"state")), + (LC("Supervisor",CTy"Privilege"), + TP[ITB([(Bop(And,Dest("STIP",bTy,Var("v",CTy"mip")), + Dest("STIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Timer",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")])), + (Bop(And,Dest("SSIP",bTy,Var("v",CTy"mip")), + Dest("SSIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Software",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")]))], + LO(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"state"]), + (LC("Hypervisor",CTy"Privilege"), + TP[ITB([(Bop(And,Dest("HTIP",bTy,Var("v",CTy"mip")), + Dest("HTIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Timer",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")])), + (Bop(And,Dest("HSIP",bTy,Var("v",CTy"mip")), + Dest("HSIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Software",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")]))], + LO(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"state"]), + (LC("Machine",CTy"Privilege"), + TP[ITB([(Bop(And,Dest("MTIP",bTy,Var("v",CTy"mip")), + Dest("MTIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Timer",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")])), + (Bop(And,Dest("MSIP",bTy,Var("v",CTy"mip")), + Dest("MSIE",bTy,Var("v0",CTy"mie"))), + Mop(Some, + TP[LC("Software",CTy"Interrupt"), + Var("curPriv",CTy"Privilege")]))], + LO(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"state"])]))))) +; +val checkInterrupts_def = Def + ("checkInterrupts",AVar uTy, + Close + (qVar"state", + Let(bVar"v", + Dest + ("MIE",bTy, + Dest + ("mstatus",CTy"mstatus", + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state"))), + Let(Var("v0",CTy"Privilege"), + Apply + (Call("curPrivilege",ATy(qTy,CTy"Privilege"),LU), + qVar"state"), + CS(Var("v0",CTy"Privilege"), + [(LC("User",CTy"Privilege"), + Let(TP[Var("v1",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"], + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt",CTy"Privilege")), + qTy)),LC("Machine",CTy"Privilege")), + qVar"state"), + CS(Var("v1",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + [(LO(PTy(CTy"Interrupt",CTy"Privilege")), + Let(TP[Var("v1", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))),qVar"s"], + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")),qTy)), + LC("Hypervisor",CTy"Privilege")), + qVar"s"), + CS(Var("v1", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + [(LO(PTy(CTy"Interrupt",CTy"Privilege")), + ITE(Bop(Or, + EQ(Var("v0",CTy"Privilege"), + LC("User",CTy"Privilege")), + bVar"v"), + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")), + qTy)), + LC("Supervisor", + CTy"Privilege")),qVar"s"), + TP[LO(PTy(CTy"Interrupt", + CTy"Privilege")), + qVar"s"])), + (Var("i", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + TP[Var("i", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + qVar"s"])]))), + (Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + TP[Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"])]))), + (LC("Supervisor",CTy"Privilege"), + Let(TP[Var("v1",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"], + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt",CTy"Privilege")), + qTy)),LC("Machine",CTy"Privilege")), + qVar"state"), + CS(Var("v1",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + [(LO(PTy(CTy"Interrupt",CTy"Privilege")), + Let(TP[Var("v1", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))),qVar"s"], + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")),qTy)), + LC("Hypervisor",CTy"Privilege")), + qVar"s"), + CS(Var("v1", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + [(LO(PTy(CTy"Interrupt",CTy"Privilege")), + ITE(Bop(Or, + EQ(Var("v0",CTy"Privilege"), + LC("User",CTy"Privilege")), + bVar"v"), + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")), + qTy)), + LC("Supervisor", + CTy"Privilege")),qVar"s"), + TP[LO(PTy(CTy"Interrupt", + CTy"Privilege")), + qVar"s"])), + (Var("i", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + TP[Var("i", + OTy(PTy(CTy"Interrupt", + CTy"Privilege"))), + qVar"s"])]))), + (Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + TP[Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"])]))), + (LC("Hypervisor",CTy"Privilege"), + Let(TP[Var("v0",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"], + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt",CTy"Privilege")), + qTy)),LC("Machine",CTy"Privilege")), + qVar"state"), + CS(Var("v0",OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + [(LO(PTy(CTy"Interrupt",CTy"Privilege")), + ITE(bVar"v", + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")),qTy)), + LC("Hypervisor",CTy"Privilege")), + qVar"s"), + TP[LO(PTy(CTy"Interrupt",CTy"Privilege")), + qVar"s"])), + (Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + TP[Var("i", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"])]))), + (LC("Machine",CTy"Privilege"), + ITE(bVar"v", + Apply + (Call + ("checkPrivInterrupt", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt",CTy"Privilege")), + qTy)),LC("Machine",CTy"Privilege")), + qVar"state"), + TP[LO(PTy(CTy"Interrupt",CTy"Privilege")), + qVar"state"]))]))))) +; +val takeTrap_def = Def + ("takeTrap", + TP[bVar"intr",Var("ec",F4),Var("epc",F64),Var("badaddr",OTy F64), + Var("toPriv",CTy"Privilege")], + Close + (qVar"state", + Let(TP[Var("v0",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call("write'ReserveLoad",ATy(qTy,qTy),LO F64),qVar"state"), + TP[Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v0",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v0",CTy"MachineCSR"), + Rupd + ("MMPRV", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v0",CTy"MachineCSR")),LF])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(qVar"s", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v0",CTy"MachineCSR"), + Call + ("pushPrivilegeStack",CTy"mstatus", + TP[Dest + ("mstatus",CTy"mstatus", + Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s")), + Var("toPriv",CTy"Privilege")])])), + qVar"s"), + CS(Var("toPriv",CTy"Privilege"), + [(LC("User",CTy"Privilege"), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"Illegal trap to U-mode")),qVar"s"))), + (LC("Supervisor",CTy"Privilege"), + Let(Var("v",CTy"SupervisorCSR"), + Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")), + qVar"s"), + Let(TP[Var("v",CTy"SupervisorCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("scause", + TP[Var("v",CTy"SupervisorCSR"), + Rupd + ("Int", + TP[Dest + ("scause", + CTy"mcause", + Var("v", + CTy"SupervisorCSR")), + bVar"intr"])])), + qVar"s"), + TP[Apply + (Const + ("SCSR", + ATy(qTy,CTy"SupervisorCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"SupervisorCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("scause", + TP[Var("v", + CTy"SupervisorCSR"), + Rupd + ("EC", + TP[Dest + ("scause", + CTy"mcause", + Var("v", + CTy"SupervisorCSR")), + Var("ec",F4)])])), + qVar"s"), + TP[Apply + (Const + ("SCSR", + ATy(qTy,CTy"SupervisorCSR")), + qVar"s0"),qVar"s0"]), + Let(qVar"s", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("sepc", + TP[Var("v", + CTy"SupervisorCSR"), + Var("epc",F64)])), + qVar"s"), + Let(TP[Var("v",CTy"SupervisorCSR"), + qVar"s"], + Let(qVar"s0", + ITE(Mop(IsSome, + Var("badaddr", + OTy F64)), + Apply + (Call + ("write'SCSR", + ATy(qTy,qTy), + Rupd + ("sbadaddr", + TP[Apply + (Const + ("SCSR", + ATy(qTy, + CTy"SupervisorCSR")), + qVar"s"), + Mop(ValOf, + Var("badaddr", + OTy F64))])), + qVar"s"),qVar"s"), + TP[Apply + (Const + ("SCSR", + ATy(qTy, + CTy"SupervisorCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'PC",ATy(qTy,qTy), + Dest + ("stvec",F64, + Var("v", + CTy"SupervisorCSR"))), + qVar"s"))))))), + (LC("Hypervisor",CTy"Privilege"), + Mop(Snd, + Apply + (Call + ("raise'exception",ATy(qTy,PTy(uTy,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"Unsupported trap to H-mode")), + qVar"s"))), + (LC("Machine",CTy"Privilege"), + Let(Var("v0",CTy"MachineCSR"), + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s"), + Let(TP[Var("v0",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcause", + TP[Var("v0",CTy"MachineCSR"), + Rupd + ("Int", + TP[Dest + ("mcause", + CTy"mcause", + Var("v0", + CTy"MachineCSR")), + bVar"intr"])])), + qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v0",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcause", + TP[Var("v0", + CTy"MachineCSR"), + Rupd + ("EC", + TP[Dest + ("mcause", + CTy"mcause", + Var("v0", + CTy"MachineCSR")), + Var("ec",F4)])])), + qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(qVar"s", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mepc", + TP[Var("v0", + CTy"MachineCSR"), + Var("epc",F64)])), + qVar"s"), + Let(TP[Var("v0",CTy"MachineCSR"), + qVar"s"], + Let(qVar"s0", + ITE(Mop(IsSome, + Var("badaddr", + OTy F64)), + Apply + (Call + ("write'MCSR", + ATy(qTy,qTy), + Rupd + ("mbadaddr", + TP[Apply + (Const + ("MCSR", + ATy(qTy, + CTy"MachineCSR")), + qVar"s"), + Mop(ValOf, + Var("badaddr", + OTy F64))])), + qVar"s"),qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy, + CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'PC",ATy(qTy,qTy), + Bop(Add, + Dest + ("mtvec",F64, + Var("v0", + CTy"MachineCSR")), + Bop(Mul, + Mop(Cast F64, + Call + ("privLevel", + FTy 2, + Apply + (Call + ("curPrivilege", + ATy(qTy, + CTy"Privilege"), + LU), + qVar"state"))), + LW(64,64)))), + qVar"s")))))))])))))) +; +val CSR_def = Def + ("CSR",Var("n",FTy 12), + Close + (qVar"state", + Apply + (Call("CSRMap",ATy(qTy,PTy(F64,qTy)),Var("n",FTy 12)),qVar"state"))) +; +val write'CSR_def = Def + ("write'CSR",TP[Var("value",F64),Var("n",FTy 12)], + Close + (qVar"state", + Apply + (Call + ("write'CSRMap",ATy(qTy,qTy), + TP[Var("value",F64),Var("n",FTy 12)]),qVar"state"))) +; +val writeCSR_def = Def + ("writeCSR",TP[Var("csr",FTy 12),Var("val",F64)], + Close + (qVar"state", + Let(TP[Var("v",CTy"StateDelta"),qVar"s"], + Let(qVar"s", + Apply + (Call + ("write'CSR",ATy(qTy,qTy), + TP[Var("val",F64),Var("csr",FTy 12)]),qVar"state"), + TP[Apply(Const("Delta",ATy(qTy,CTy"StateDelta")),qVar"s"), + qVar"s"]), + Let(TP[Var("v",CTy"StateDelta"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta",ATy(qTy,qTy), + Rupd + ("addr", + TP[Var("v",CTy"StateDelta"), + Mop(Some,Mop(Cast F64,Var("csr",FTy 12)))])), + qVar"s"), + TP[Apply + (Const("Delta",ATy(qTy,CTy"StateDelta")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v0",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'Delta",ATy(qTy,qTy), + Rupd + ("data2", + TP[Var("v",CTy"StateDelta"), + Mop(Some,Var("v0",F64))])),qVar"s")))))) +; +val GPR_def = Def + ("GPR",Var("n",FTy 5), + Close + (qVar"state", + ITE(EQ(Var("n",FTy 5),LW(0,5)),LW(0,64), + Apply(Call("gpr",ATy(qTy,F64),Var("n",FTy 5)),qVar"state")))) +; +val write'GPR_def = Def + ("write'GPR",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + ITE(Mop(Not,EQ(Var("n",FTy 5),LW(0,5))), + Apply + (Call + ("write'gpr",ATy(qTy,qTy), + TP[Var("value",F64),Var("n",FTy 5)]),qVar"state"), + qVar"state"))) +; +val FPRS_def = Def + ("FPRS",Var("n",FTy 5), + Close + (qVar"state", + EX(Apply(Call("fpr",ATy(qTy,F64),Var("n",FTy 5)),qVar"state"),LN 31, + LN 0,F32))) +; +val write'FPRS_def = Def + ("write'FPRS",TP[Var("value",F32),Var("n",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'fpr",ATy(qTy,qTy), + TP[BFI(LN 31,LN 0,Var("value",F32), + Apply + (Call("fpr",ATy(qTy,F64),Var("n",FTy 5)),qVar"state")), + Var("n",FTy 5)]),qVar"state"))) +; +val FPRD_def = Def + ("FPRD",Var("n",FTy 5), + Close + (qVar"state", + Apply(Call("fpr",ATy(qTy,F64),Var("n",FTy 5)),qVar"state"))) +; +val write'FPRD_def = Def + ("write'FPRD",TP[Var("value",F64),Var("n",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'fpr",ATy(qTy,qTy),TP[Var("value",F64),Var("n",FTy 5)]), + qVar"state"))) +; +val writeFPRS_def = Def + ("writeFPRS",TP[Var("rd",FTy 5),Var("val",F32)], + Close + (qVar"state", + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s", + Apply + (Call + ("write'FPRS",ATy(qTy,qTy), + TP[Var("val",F32),Var("rd",FTy 5)]),qVar"state"), + TP[Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s"), + qVar"s"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"StateDelta"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")),LT])])), + qVar"s"), + TP[Apply + (Const("Delta",ATy(qTy,CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'Delta",ATy(qTy,qTy), + Rupd + ("data1", + TP[Var("v",CTy"StateDelta"), + Mop(Some,Mop(Cast F64,Var("val",F32)))])), + qVar"s")))))) +; +val writeFPRD_def = Def + ("writeFPRD",TP[Var("rd",FTy 5),Var("val",F64)], + Close + (qVar"state", + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s", + Apply + (Call + ("write'FPRD",ATy(qTy,qTy), + TP[Var("val",F64),Var("rd",FTy 5)]),qVar"state"), + TP[Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s"), + qVar"s"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Dirty",CTy"ExtStatus"))])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"StateDelta"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")),LT])])), + qVar"s"), + TP[Apply + (Const("Delta",ATy(qTy,CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'Delta",ATy(qTy,qTy), + Rupd + ("data1", + TP[Var("v",CTy"StateDelta"), + Mop(Some,Var("val",F64))])),qVar"s")))))) +; +val MEM_def = Def + ("MEM",Var("a",FTy 61), + Close + (qVar"state", + Let(Var("b",F64),Bop(Lsl,Mop(Cast F64,Var("a",FTy 61)),LN 3), + CC[Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(7,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(6,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(5,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(4,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(3,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(2,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(1,64))), + Apply(Dest("MEM8",ATy(F64,F8),qVar"state"),Var("b",F64))]))) +; +val write'MEM_def = Def + ("write'MEM",TP[Var("val",F64),Var("a",FTy 61)], + Close + (qVar"state", + Let(Var("b",F64),Bop(Lsl,Mop(Cast F64,Var("a",FTy 61)),LN 3), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"state", + Fupd + (Dest("MEM8",ATy(F64,F8),qVar"state"), + Bop(Add,Var("b",F64),LW(7,64)), + EX(Var("val",F64),LN 63,LN 56,F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("b",F64),LW(6,64)), + EX(Var("val",F64),LN 55,LN 48,F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("b",F64),LW(5,64)), + EX(Var("val",F64),LN 47,LN 40,F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("b",F64),LW(4,64)), + EX(Var("val",F64),LN 39,LN 32,F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("b",F64),LW(3,64)), + EX(Var("val",F64),LN 31,LN 24,F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest + ("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("b",F64),LW(2,64)), + EX(Var("val",F64),LN 23,LN 16, + F8))]), + Let(qVar"s", + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest + ("MEM8",ATy(F64,F8), + qVar"s"), + Bop(Add,Var("b",F64), + LW(1,64)), + EX(Var("val",F64),LN 15, + LN 8,F8))]), + Rupd + ("MEM8", + TP[qVar"s", + Fupd + (Dest + ("MEM8",ATy(F64,F8), + qVar"s"),Var("b",F64), + EX(Var("val",F64),LN 7, + LN 0,F8))]))))))))))) +; +val rawReadData_def = Def + ("rawReadData",Var("pAddr",F64), + Close + (qVar"state", + Let(Var("pAddrIdx",FTy 61),EX(Var("pAddr",F64),LN 63,LN 3,FTy 61), + Let(nVar"align", + Mop(Cast nTy,EX(Var("pAddr",F64),LN 2,LN 0,FTy 3)), + ITE(EQ(nVar"align",LN 0), + Apply + (Call("MEM",ATy(qTy,F64),Var("pAddrIdx",FTy 61)), + qVar"state"), + EX(Bop(Asr, + CC[Apply + (Call + ("MEM",ATy(qTy,F64), + Bop(Add,Var("pAddrIdx",FTy 61),LW(1,61))), + qVar"state"), + Apply + (Call + ("MEM",ATy(qTy,F64), + Var("pAddrIdx",FTy 61)),qVar"state")], + Bop(Mul,nVar"align",LN 8)),LN 63,LN 0,F64)))))) +; +val rawWriteData_def = Def + ("rawWriteData",TP[Var("pAddr",F64),Var("data",F64),nVar"nbytes"], + Close + (qVar"state", + Let(Var("mask",F64), + Bop(Sub, + Bop(Lsl,Mop(Cast F64,LW(1,1)),Bop(Mul,nVar"nbytes",LN 8)), + LW(1,64)), + Let(Var("pAddrIdx",FTy 61), + EX(Var("pAddr",F64),LN 63,LN 3,FTy 61), + Let(nVar"align", + Mop(Cast nTy,EX(Var("pAddr",F64),LN 2,LN 0,FTy 3)), + Let(Var("v",F64), + Apply + (Call("MEM",ATy(qTy,F64),Var("pAddrIdx",FTy 61)), + qVar"state"), + ITB([(EQ(nVar"align",LN 0), + Apply + (Call + ("write'MEM",ATy(qTy,qTy), + TP[Bop(BOr, + Bop(BAnd,Var("v",F64), + Mop(BNot,Var("mask",F64))), + Bop(BAnd,Var("data",F64), + Var("mask",F64))), + Var("pAddrIdx",FTy 61)]),qVar"state")), + (Bop(Le,Bop(Add,nVar"align",nVar"nbytes"), + Bop(Div,Mop(Size,Var("mask",F64)),LN 8)), + Apply + (Call + ("write'MEM",ATy(qTy,qTy), + TP[Bop(BOr, + Bop(BAnd,Var("v",F64), + Mop(BNot, + Bop(Lsl,Var("mask",F64), + Bop(Mul,nVar"align", + LN 8)))), + Bop(Lsl, + Bop(BAnd,Var("data",F64), + Var("mask",F64)), + Bop(Mul,nVar"align",LN 8))), + Var("pAddrIdx",FTy 61)]),qVar"state"))], + Let(Var("dw_mask",FTy 128), + Bop(Lsl,Mop(Cast(FTy 128),Var("mask",F64)), + Bop(Mul,nVar"align",LN 8)), + Let(Var("dw_new",FTy 128), + Bop(BOr, + Bop(BAnd, + CC[Apply + (Call + ("MEM",ATy(qTy,F64), + Bop(Add, + Var("pAddrIdx", + FTy 61), + LW(1,61))), + qVar"state"),Var("v",F64)], + Mop(BNot,Var("dw_mask",FTy 128))), + Bop(BAnd, + Bop(Lsl, + Mop(Cast(FTy 128), + Var("data",F64)), + Bop(Mul,nVar"align",LN 8)), + Var("dw_mask",FTy 128))), + Apply + (Call + ("write'MEM",ATy(qTy,qTy), + TP[EX(Var("dw_new",FTy 128), + Bop(Sub, + Mop(Size,Var("data",F64)), + LN 1),LN 0,F64), + Var("pAddrIdx",FTy 61)]), + Apply + (Call + ("write'MEM",ATy(qTy,qTy), + TP[EX(Var("dw_new",FTy 128), + Bop(Sub, + Bop(Mul,LN 2, + Mop(Size, + Var("data", + F64))), + LN 1), + Mop(Size,Var("data",F64)), + F64), + Bop(Add, + Var("pAddrIdx",FTy 61), + LW(1,61))]),qVar"state"))))))))))) +; +val rawReadHalf_def = Def + ("rawReadHalf",Var("pAddr",F64), + Close + (qVar"state", + Let(Var("v",F64), + Apply + (Call + ("MEM",ATy(qTy,F64),EX(Var("pAddr",F64),LN 63,LN 3,FTy 61)), + qVar"state"), + CS(EX(Var("pAddr",F64),LN 2,LN 1,FTy 2), + [(LW(0,2),EX(Var("v",F64),LN 63,LN 48,F16)), + (LW(1,2),EX(Var("v",F64),LN 47,LN 32,F16)), + (LW(2,2),EX(Var("v",F64),LN 31,LN 16,F16)), + (LW(3,2),EX(Var("v",F64),LN 15,LN 0,F16))])))) +; +val rawReadInst_def = Def + ("rawReadInst",Var("pAddr",F64), + Close + (qVar"state", + Let(TP[bVar"b'7",bVar"b'6",bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2", + bVar"b'1",bVar"b'0"], + BL(8, + Apply(Dest("MEM8",ATy(F64,F8),qVar"state"),Var("pAddr",F64))), + ITE(Bop(And,bVar"b'1",bVar"b'0"), + Let(qVar"s", + Apply + (Call("write'Skip",ATy(qTy,qTy),LW(4,64)),qVar"state"), + TP[Call + ("Word",CTy"rawInstType", + CC[Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("pAddr",F64),LW(3,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("pAddr",F64),LW(2,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("pAddr",F64),LW(1,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Var("pAddr",F64))]),qVar"s"]), + Let(qVar"s", + Apply + (Call("write'Skip",ATy(qTy,qTy),LW(2,64)),qVar"state"), + TP[Call + ("Half",CTy"rawInstType", + CC[Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Bop(Add,Var("pAddr",F64),LW(1,64))), + Apply + (Dest("MEM8",ATy(F64,F8),qVar"s"), + Var("pAddr",F64))]),qVar"s"]))))) +; +val rawWriteMem_def = Def + ("rawWriteMem",TP[Var("pAddr",F64),Var("data",F64)], + Close + (qVar"state", + Apply + (Call + ("write'MEM",ATy(qTy,qTy), + TP[Var("data",F64),EX(Var("pAddr",F64),LN 63,LN 3,FTy 61)]), + qVar"state"))) +; +val checkMemPermission_def = Def + ("checkMemPermission", + TP[Var("ft",CTy"fetchType"),Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"),Var("perm",F4)], + Close + (qVar"state", + CS(Var("perm",F4), + [(LW(0,4), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(bTy,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"Checking perm on Page-Table pointer!")),qVar"state")), + (LW(1,4), + Apply + (Call + ("raise'exception",ATy(qTy,PTy(bTy,qTy)), + Call + ("INTERNAL_ERROR",CTy"exception", + LS"Checking perm on Page-Table pointer!")),qVar"state")), + (LW(2,4), + TP[ITE(EQ(Var("priv",CTy"Privilege"),LC("User",CTy"Privilege")), + Mop(Not, + EQ(Var("ac",CTy"accessType"), + LC("Write",CTy"accessType"))), + Bop(And, + EQ(Var("ac",CTy"accessType"), + LC("Read",CTy"accessType")), + EQ(Var("ft",CTy"fetchType"), + LC("Data",CTy"fetchType")))),qVar"state"]), + (LW(3,4), + TP[Bop(Or, + EQ(Var("priv",CTy"Privilege"),LC("User",CTy"Privilege")), + Mop(Not, + EQ(Var("ft",CTy"fetchType"), + LC("Instruction",CTy"fetchType")))),qVar"state"]), + (LW(4,4), + TP[Bop(And, + EQ(Var("ac",CTy"accessType"),LC("Read",CTy"accessType")), + EQ(Var("ft",CTy"fetchType"),LC("Data",CTy"fetchType"))), + qVar"state"]), + (LW(5,4), + TP[Mop(Not, + EQ(Var("ft",CTy"fetchType"), + LC("Instruction",CTy"fetchType"))),qVar"state"]), + (LW(6,4), + TP[Mop(Not, + EQ(Var("ac",CTy"accessType"),LC("Write",CTy"accessType"))), + qVar"state"]),(LW(7,4),TP[LT,qVar"state"]), + (LW(8,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Bop(And, + EQ(Var("ac",CTy"accessType"), + LC("Read",CTy"accessType")), + EQ(Var("ft",CTy"fetchType"), + LC("Data",CTy"fetchType")))),qVar"state"]), + (LW(9,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Mop(Not, + EQ(Var("ft",CTy"fetchType"), + LC("Instruction",CTy"fetchType")))),qVar"state"]), + (LW(10,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Mop(Not, + EQ(Var("ac",CTy"accessType"), + LC("Write",CTy"accessType")))),qVar"state"]), + (LW(11,4), + TP[Mop(Not, + EQ(Var("priv",CTy"Privilege"),LC("User",CTy"Privilege"))), + qVar"state"]), + (LW(12,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Bop(And, + EQ(Var("ac",CTy"accessType"), + LC("Read",CTy"accessType")), + EQ(Var("ft",CTy"fetchType"), + LC("Data",CTy"fetchType")))),qVar"state"]), + (LW(13,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Mop(Not, + EQ(Var("ft",CTy"fetchType"), + LC("Instruction",CTy"fetchType")))),qVar"state"]), + (LW(14,4), + TP[Bop(And, + Mop(Not, + EQ(Var("priv",CTy"Privilege"), + LC("User",CTy"Privilege"))), + Mop(Not, + EQ(Var("ac",CTy"accessType"), + LC("Write",CTy"accessType")))),qVar"state"]), + (LW(15,4), + TP[Mop(Not, + EQ(Var("priv",CTy"Privilege"),LC("User",CTy"Privilege"))), + qVar"state"])]))) +; +val isGlobal_def = Def + ("isGlobal",Var("perm",F4), + EQ(EX(Var("perm",F4),LN 3,LN 2,FTy 2),LW(3,2))) +; +val rec'SV_PTE_def = Def + ("rec'SV_PTE",Var("x",F64), + Rec(CTy"SV_PTE", + [Bop(Bit,Var("x",F64),LN 6),EX(Var("x",F64),LN 47,LN 10,FTy 38), + Bop(Bit,Var("x",F64),LN 5),EX(Var("x",F64),LN 9,LN 7,FTy 3), + EX(Var("x",F64),LN 4,LN 1,F4),Bop(Bit,Var("x",F64),LN 0), + EX(Var("x",F64),LN 63,LN 48,F16)])) +; +val reg'SV_PTE_def = Def + ("reg'SV_PTE",Var("x",CTy"SV_PTE"), + CS(Var("x",CTy"SV_PTE"), + [(Rec(CTy"SV_PTE", + [bVar"PTE_D",Var("PTE_PPNi",FTy 38),bVar"PTE_R", + Var("PTE_SW",FTy 3),Var("PTE_T",F4),bVar"PTE_V", + Var("sv_pte'rst",F16)]), + CC[Var("sv_pte'rst",F16),Var("PTE_PPNi",FTy 38), + Var("PTE_SW",FTy 3),Mop(Cast F1,bVar"PTE_D"), + Mop(Cast F1,bVar"PTE_R"),Var("PTE_T",F4), + Mop(Cast F1,bVar"PTE_V")])])) +; +val write'rec'SV_PTE_def = Def + ("write'rec'SV_PTE",TP[AVar F64,Var("x",CTy"SV_PTE")], + Call("reg'SV_PTE",F64,Var("x",CTy"SV_PTE"))) +; +val write'reg'SV_PTE_def = Def + ("write'reg'SV_PTE",TP[AVar(CTy"SV_PTE"),Var("x",F64)], + Call("rec'SV_PTE",CTy"SV_PTE",Var("x",F64))) +; +val rec'SV_Vaddr_def = Def + ("rec'SV_Vaddr",Var("x",F64), + Rec(CTy"SV_Vaddr", + [EX(Var("x",F64),LN 11,LN 0,FTy 12), + EX(Var("x",F64),LN 47,LN 12,FTy 36), + EX(Var("x",F64),LN 63,LN 48,F16)])) +; +val reg'SV_Vaddr_def = Def + ("reg'SV_Vaddr",Var("x",CTy"SV_Vaddr"), + CS(Var("x",CTy"SV_Vaddr"), + [(Rec(CTy"SV_Vaddr", + [Var("Sv_PgOfs",FTy 12),Var("Sv_VPNi",FTy 36), + Var("sv_vaddr'rst",F16)]), + CC[Var("sv_vaddr'rst",F16),Var("Sv_VPNi",FTy 36), + Var("Sv_PgOfs",FTy 12)])])) +; +val write'rec'SV_Vaddr_def = Def + ("write'rec'SV_Vaddr",TP[AVar F64,Var("x",CTy"SV_Vaddr")], + Call("reg'SV_Vaddr",F64,Var("x",CTy"SV_Vaddr"))) +; +val write'reg'SV_Vaddr_def = Def + ("write'reg'SV_Vaddr",TP[AVar(CTy"SV_Vaddr"),Var("x",F64)], + Call("rec'SV_Vaddr",CTy"SV_Vaddr",Var("x",F64))) +; +val walk64_def = tDef + ("walk64", + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"),Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"),Var("ptb",F64),nVar"level"], + Close + (qVar"state", + Let(Var("va",CTy"SV_Vaddr"), + Call("rec'SV_Vaddr",CTy"SV_Vaddr",Var("vAddr",F64)), + Let(Var("pte_addr",F64), + Bop(Add,Var("ptb",F64), + Bop(Lsl, + Mop(Cast F64, + EX(Bop(Lsr, + Dest + ("Sv_VPNi",FTy 36, + Var("va",CTy"SV_Vaddr")), + Bop(Mul,nVar"level", + Const("LEVEL_BITS",nTy))), + Bop(Sub,Const("LEVEL_BITS",nTy),LN 1),LN 0, + FTy 9)),LN 3)), + Let(Var("v",CTy"SV_PTE"), + Call + ("rec'SV_PTE",CTy"SV_PTE", + Apply + (Call + ("rawReadData",ATy(qTy,F64),Var("pte_addr",F64)), + qVar"state")), + ITB([(Mop(Not,Dest("PTE_V",bTy,Var("v",CTy"SV_PTE"))), + TP[LO(PTy(F64, + PTy(CTy"SV_PTE",PTy(nTy,PTy(bTy,F64))))), + qVar"state"]), + (Bop(Or, + EQ(Dest("PTE_T",F4,Var("v",CTy"SV_PTE")), + LW(0,4)), + EQ(Dest("PTE_T",F4,Var("v",CTy"SV_PTE")), + LW(1,4))), + ITE(EQ(nVar"level",LN 0), + TP[LO(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64))))), + qVar"state"], + Apply + (Call + ("walk64", + ATy(qTy, + PTy(OTy(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64))))), + qTy)), + TP[Var("vAddr",F64), + Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"), + Mop(Cast F64, + Bop(Lsl, + Dest + ("PTE_PPNi",FTy 38, + Var("v",CTy"SV_PTE")), + Const("PAGESIZE_BITS",nTy))), + Bop(Sub,nVar"level",LN 1)]), + qVar"state")))], + Let(TP[bVar"v0",qVar"s"], + Apply + (Call + ("checkMemPermission", + ATy(qTy,PTy(bTy,qTy)), + TP[Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"), + Dest("PTE_T",F4,Var("v",CTy"SV_PTE"))]), + qVar"state"), + ITE(Mop(Not,bVar"v0"), + TP[LO(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64))))), + qVar"s"], + Let(TP[Var("r", + OTy(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64)))))), + Var("s1",PTy(CTy"SV_PTE",qTy))], + Let(Var("s0",CTy"SV_PTE"), + Rupd + ("PTE_R", + TP[Var("v",CTy"SV_PTE"),LT]), + Let(Var("s0",CTy"SV_PTE"), + ITE(EQ(Var("ac",CTy"accessType"), + LC("Write", + CTy"accessType")), + Rupd + ("PTE_D", + TP[Var("s0",CTy"SV_PTE"), + LT]), + Var("s0",CTy"SV_PTE")), + TP[Mop(Some, + TP[Mop(Cast F64, + CC[ITE(Bop(Gt, + nVar"level", + LN 0), + Bop(BOr, + Mop(Cast + (FTy 38), + Bop(Lsl, + Bop(Lsr, + Dest + ("PTE_PPNi", + FTy 38, + Var("v", + CTy"SV_PTE")), + Bop(Mul, + nVar"level", + Const + ("LEVEL_BITS", + nTy))), + Bop(Mul, + nVar"level", + Const + ("LEVEL_BITS", + nTy)))), + Mop(Cast + (FTy 38), + Bop(BAnd, + Dest + ("Sv_VPNi", + FTy 36, + Var("va", + CTy"SV_Vaddr")), + Bop(Sub, + Bop(Lsl, + LW(1, + 36), + Bop(Mul, + nVar"level", + Const + ("LEVEL_BITS", + nTy))), + LW(1, + 36))))), + Dest + ("PTE_PPNi", + FTy 38, + Var("v", + CTy"SV_PTE"))), + Dest + ("Sv_PgOfs", + FTy 12, + Var("va", + CTy"SV_Vaddr"))]), + Var("s0",CTy"SV_PTE"), + nVar"level", + Call + ("isGlobal",bTy, + Dest + ("PTE_T",F4, + Var("v", + CTy"SV_PTE"))), + Var("pte_addr",F64)]), + Var("s0",CTy"SV_PTE"), + ITE(Bop(Or, + Mop(Not, + EQ(Dest + ("PTE_R", + bTy, + Var("v", + CTy"SV_PTE")), + Dest + ("PTE_R", + bTy, + Var("s0", + CTy"SV_PTE")))), + Mop(Not, + EQ(Dest + ("PTE_D", + bTy, + Var("v", + CTy"SV_PTE")), + Dest + ("PTE_D", + bTy, + Var("s0", + CTy"SV_PTE"))))), + Apply + (Call + ("rawWriteData", + ATy(qTy,qTy), + TP[Var("pte_addr", + F64), + Call + ("reg'SV_PTE", + F64, + Var("s0", + CTy"SV_PTE")), + LN 8]),qVar"s"), + qVar"s")])), + TP[Var("r", + OTy(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64)))))), + Mop(Snd, + Var("s1",PTy(CTy"SV_PTE",qTy)))])))))))), + Close + (Var("x", + PTy(PTy(F64, + PTy(CTy"fetchType", + PTy(CTy"accessType",PTy(CTy"Privilege",PTy(F64,nTy))))), + qTy)), + CS(Var("x", + PTy(PTy(F64, + PTy(CTy"fetchType", + PTy(CTy"accessType", + PTy(CTy"Privilege",PTy(F64,nTy))))),qTy)), + [(TP[TP[Var("vAddr",F64),Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"),Var("priv",CTy"Privilege"), + Var("ptb",F64),nVar"level"],AVar qTy],nVar"level")])), + NO_TAC) +; +val curASID_def = Def + ("curASID",AVar uTy, + Close + (qVar"state", + EX(Dest + ("sasid",F64, + Apply(Const("SCSR",ATy(qTy,CTy"SupervisorCSR")),qVar"state")), + Bop(Sub,Const("ASID_SIZE",nTy),LN 1),LN 0,FTy 6))) +; +val mkTLBEntry_def = Def + ("mkTLBEntry", + TP[Var("asid",FTy 6),bVar"global",Var("vAddr",F64),Var("pAddr",F64), + Var("pte",CTy"SV_PTE"),nVar"i",Var("pteAddr",F64)], + Close + (qVar"state", + Let(Var("s0",CTy"TLBEntry"), + Rupd + ("vAddrMask", + TP[Rupd + ("pteAddr", + TP[Rupd + ("pte", + TP[Rupd + ("global", + TP[Rupd + ("asid", + TP[LX(CTy"TLBEntry"), + Var("asid",FTy 6)]),bVar"global"]), + Var("pte",CTy"SV_PTE")]),Var("pteAddr",F64)]), + Bop(Sub, + Bop(Lsl,LW(1,64), + Bop(Add,Bop(Mul,Const("LEVEL_BITS",nTy),nVar"i"), + Const("PAGESIZE_BITS",nTy))),LW(1,64))]), + Let(Var("s0",CTy"TLBEntry"), + Rupd + ("vMatchMask", + TP[Var("s0",CTy"TLBEntry"), + Bop(BXor,Mop(SE F64,LW(1,1)), + Dest("vAddrMask",F64,Var("s0",CTy"TLBEntry")))]), + Rupd + ("age", + TP[Rupd + ("pAddr", + TP[Rupd + ("vAddr", + TP[Var("s0",CTy"TLBEntry"), + Bop(BAnd,Var("vAddr",F64), + Dest + ("vMatchMask",F64, + Var("s0",CTy"TLBEntry")))]), + Bop(Lsl, + Bop(Asr,Var("pAddr",F64), + Bop(Add,Const("PAGESIZE_BITS",nTy), + Bop(Mul,Const("LEVEL_BITS",nTy), + nVar"i"))), + Bop(Add,Const("PAGESIZE_BITS",nTy), + Bop(Mul,Const("LEVEL_BITS",nTy),nVar"i")))]), + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"))]))))) +; +val TLBEntries_def = Def0 ("TLBEntries",LN 16) +; +val lookupTLB_def = Def + ("lookupTLB", + TP[Var("asid",FTy 6),Var("vAddr",F64), + Var("tlb",ATy(F4,OTy(CTy"TLBEntry")))], + Mop(Fst, + Mop(Snd, + Apply + (For(TP[LN 0,Bop(Sub,Const("TLBEntries",nTy),LN 1), + Close + (nVar"i", + Close + (Var("state",PTy(OTy(PTy(CTy"TLBEntry",F4)),uTy)), + CS(Apply + (Var("tlb",ATy(F4,OTy(CTy"TLBEntry"))), + Mop(Cast F4,nVar"i")), + [(Mop(Some,Var("e",CTy"TLBEntry")), + TP[LU, + ITE(Bop(And, + EQ(Mop(Fst, + Var("state", + PTy(OTy(PTy(CTy"TLBEntry", + F4)),uTy))), + LO(PTy(CTy"TLBEntry",F4))), + Bop(And, + Bop(Or, + Dest + ("global",bTy, + Var("e", + CTy"TLBEntry")), + EQ(Dest + ("asid",FTy 6, + Var("e", + CTy"TLBEntry")), + Var("asid",FTy 6))), + EQ(Dest + ("vAddr",F64, + Var("e",CTy"TLBEntry")), + Bop(BAnd, + Var("vAddr",F64), + Dest + ("vMatchMask",F64, + Var("e", + CTy"TLBEntry")))))), + TP[Mop(Some, + TP[Var("e",CTy"TLBEntry"), + Mop(Cast F4,nVar"i")]),LU], + Var("state", + PTy(OTy(PTy(CTy"TLBEntry",F4)), + uTy)))]), + (LO(CTy"TLBEntry"), + TP[LU, + Var("state", + PTy(OTy(PTy(CTy"TLBEntry",F4)),uTy))])])))]), + TP[LO(PTy(CTy"TLBEntry",F4)),LU])))) +; +val addToTLB_def = Def + ("addToTLB", + TP[Var("asid",FTy 6),Var("vAddr",F64),Var("pAddr",F64), + Var("pte",CTy"SV_PTE"),Var("pteAddr",F64),nVar"i",bVar"global", + Var("curTLB",ATy(F4,OTy(CTy"TLBEntry")))], + Close + (qVar"state", + Let(Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4,OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy)))))), + Mop(Snd, + Apply + (For(TP[LN 0,Bop(Sub,Const("TLBEntries",nTy),LN 1), + Close + (nVar"i", + Close + (Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy)))))), + CS(Apply + (Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))))), + Mop(Cast F4,nVar"i")), + [(Mop(Some,Var("e",CTy"TLBEntry")), + ITE(Bop(Ult, + Dest + ("age",F64, + Var("e",CTy"TLBEntry")), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))))), + Let(Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))), + TP[Mop(Fst, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))), + Let(Var("s", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))), + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))), + TP[Mop(Fst, + Var("s", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))), + Dest + ("age",F64, + Var("e", + CTy"TLBEntry")), + Mop(Snd, + Mop(Snd, + Var("s", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))])], + TP[LU, + Mop(Fst, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))), + nVar"i", + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))))]), + TP[LU, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))])), + (LO(CTy"TLBEntry"), + TP[LU, + ITE(Mop(Not, + Mop(Fst, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))), + TP[LT, + Let(Var("s0", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))), + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))), + TP[Mop(Fst, + Var("s0", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))), + Let(Var("s0", + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))), + Mop(Snd, + Var("s0", + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))), + TP[Mop(Fst, + Var("s0", + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))), + Fupd + (Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))))), + Mop(Cast F4, + nVar"i"), + Mop(Some, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))))))))), + Mop(Snd, + Mop(Snd, + Var("s0", + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))])])], + Var("state", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy)))))))])])))]), + TP[LF,LN 0,Mop(SE F64,LW(1,1)), + Var("curTLB",ATy(F4,OTy(CTy"TLBEntry"))), + Apply + (Call + ("mkTLBEntry",ATy(qTy,CTy"TLBEntry"), + TP[Var("asid",FTy 6),bVar"global", + Var("vAddr",F64),Var("pAddr",F64), + Var("pte",CTy"SV_PTE"),nVar"i", + Var("pteAddr",F64)]),qVar"state"),qVar"state"])), + ITE(Mop(Not, + Mop(Fst, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4,OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy)))))))), + Fupd + (Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy)))))))))), + Mop(Cast F4, + Mop(Fst, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4,OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy))))))))), + Mop(Some, + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry", + qTy))))))))))))), + Mop(Fst, + Mop(Snd, + Mop(Snd, + Mop(Snd, + Var("s", + PTy(bTy, + PTy(nTy, + PTy(F64, + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + PTy(CTy"TLBEntry",qTy)))))))))))))) +; +val flushTLB_def = Def + ("flushTLB", + TP[Var("asid",FTy 6),Var("addr",OTy F64), + Var("curTLB",ATy(F4,OTy(CTy"TLBEntry")))], + Mop(Fst, + Mop(Snd, + Apply + (For(TP[LN 0,Bop(Sub,Const("TLBEntries",nTy),LN 1), + Close + (nVar"i", + Close + (Var("state",PTy(ATy(F4,OTy(CTy"TLBEntry")),uTy)), + CS(TP[Apply + (Mop(Fst, + Var("state", + PTy(ATy(F4,OTy(CTy"TLBEntry")), + uTy))), + Mop(Cast F4,nVar"i")), + Var("addr",OTy F64)], + [(TP[Mop(Some,Var("e",CTy"TLBEntry")), + Mop(Some,Var("va",F64))], + TP[LU, + ITE(Bop(And, + Bop(Or, + EQ(Var("asid",FTy 6), + LW(0,6)), + Bop(And, + EQ(Var("asid",FTy 6), + Dest + ("asid",FTy 6, + Var("e", + CTy"TLBEntry"))), + Mop(Not, + Dest + ("global",bTy, + Var("e", + CTy"TLBEntry"))))), + EQ(Dest + ("vAddr",F64, + Var("e",CTy"TLBEntry")), + Bop(BAnd,Var("va",F64), + Dest + ("vMatchMask",F64, + Var("e",CTy"TLBEntry"))))), + TP[Fupd + (Mop(Fst, + Var("state", + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + uTy))), + Mop(Cast F4,nVar"i"), + LO(CTy"TLBEntry")),LU], + Var("state", + PTy(ATy(F4,OTy(CTy"TLBEntry")), + uTy)))]), + (TP[Mop(Some,Var("e",CTy"TLBEntry")),LO F64], + TP[LU, + ITE(Bop(Or, + EQ(Var("asid",FTy 6),LW(0,6)), + Bop(And, + EQ(Var("asid",FTy 6), + Dest + ("asid",FTy 6, + Var("e",CTy"TLBEntry"))), + Mop(Not, + Dest + ("global",bTy, + Var("e", + CTy"TLBEntry"))))), + TP[Fupd + (Mop(Fst, + Var("state", + PTy(ATy(F4, + OTy(CTy"TLBEntry")), + uTy))), + Mop(Cast F4,nVar"i"), + LO(CTy"TLBEntry")),LU], + Var("state", + PTy(ATy(F4,OTy(CTy"TLBEntry")), + uTy)))]), + (TP[LO(CTy"TLBEntry"),AVar(OTy F64)], + TP[LU, + Var("state", + PTy(ATy(F4,OTy(CTy"TLBEntry")),uTy))])])))]), + TP[Var("curTLB",ATy(F4,OTy(CTy"TLBEntry"))),LU])))) +; +val TLB_def = Def + ("TLB",qVar"state", + Apply + (Dest("c_tlb",ATy(F8,ATy(F4,OTy(CTy"TLBEntry"))),qVar"state"), + Dest("procID",F8,qVar"state"))) +; +val write'TLB_def = Def + ("write'TLB",Var("value",ATy(F4,OTy(CTy"TLBEntry"))), + Close + (qVar"state", + Rupd + ("c_tlb", + TP[qVar"state", + Fupd + (Dest + ("c_tlb",ATy(F8,ATy(F4,OTy(CTy"TLBEntry"))),qVar"state"), + Dest("procID",F8,qVar"state"), + Var("value",ATy(F4,OTy(CTy"TLBEntry"))))]))) +; +val translate64_def = Def + ("translate64", + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"),Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"),nVar"level"], + Close + (qVar"state", + Let(Var("v",FTy 6), + Apply(Call("curASID",ATy(qTy,FTy 6),LU),qVar"state"), + CS(Call + ("lookupTLB",OTy(PTy(CTy"TLBEntry",F4)), + TP[Var("v",FTy 6),Var("vAddr",F64), + Apply + (Const("TLB",ATy(qTy,ATy(F4,OTy(CTy"TLBEntry")))), + qVar"state")]), + [(Mop(Some,TP[Var("e",CTy"TLBEntry"),Var("idx",F4)]), + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkMemPermission",ATy(qTy,PTy(bTy,qTy)), + TP[Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"), + Dest + ("PTE_T",F4, + Dest + ("pte",CTy"SV_PTE",Var("e",CTy"TLBEntry")))]), + qVar"state"), + ITE(bVar"v", + TP[Mop(Some, + Bop(BOr, + Dest("pAddr",F64,Var("e",CTy"TLBEntry")), + Bop(BAnd,Var("vAddr",F64), + Dest + ("vAddrMask",F64, + Var("e",CTy"TLBEntry"))))), + ITE(Bop(And, + EQ(Var("ac",CTy"accessType"), + LC("Write",CTy"accessType")), + Mop(Not, + Dest + ("PTE_D",bTy, + Dest + ("pte",CTy"SV_PTE", + Var("e",CTy"TLBEntry"))))), + Let(Var("s0",CTy"TLBEntry"), + Rupd + ("pte", + TP[Var("e",CTy"TLBEntry"), + Rupd + ("PTE_D", + TP[Dest + ("pte",CTy"SV_PTE", + Var("e",CTy"TLBEntry")), + LT])]), + Let(qVar"s1", + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Dest + ("pteAddr",F64, + Var("s0",CTy"TLBEntry")), + Call + ("reg'SV_PTE",F64, + Dest + ("pte",CTy"SV_PTE", + Var("s0", + CTy"TLBEntry"))), + LN 8]),qVar"s"), + Apply + (Call + ("write'TLB",ATy(qTy,qTy), + Fupd + (Apply + (Const + ("TLB", + ATy(qTy, + ATy(F4, + OTy(CTy"TLBEntry")))), + qVar"s1"),Var("idx",F4), + Mop(Some, + Var("s0",CTy"TLBEntry")))), + qVar"s1"))),qVar"s")], + TP[LO F64,qVar"s"]))), + (LO(PTy(CTy"TLBEntry",F4)), + Let(TP[Var("v0", + OTy(PTy(F64, + PTy(CTy"SV_PTE",PTy(nTy,PTy(bTy,F64)))))), + qVar"s"], + Apply + (Call + ("walk64", + ATy(qTy, + PTy(OTy(PTy(F64, + PTy(CTy"SV_PTE", + PTy(nTy,PTy(bTy,F64))))),qTy)), + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("priv",CTy"Privilege"), + Dest + ("sptbr",F64, + Apply + (Const + ("SCSR",ATy(qTy,CTy"SupervisorCSR")), + qVar"state")),nVar"level"]),qVar"state"), + CS(Var("v0", + OTy(PTy(F64, + PTy(CTy"SV_PTE",PTy(nTy,PTy(bTy,F64)))))), + [(Mop(Some, + TP[Var("pAddr",F64),Var("pte",CTy"SV_PTE"), + nVar"i",bVar"global",Var("pteAddr",F64)]), + TP[Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'TLB",ATy(qTy,qTy), + Apply + (Call + ("addToTLB", + ATy(qTy,ATy(F4,OTy(CTy"TLBEntry"))), + TP[Var("v",FTy 6),Var("vAddr",F64), + Var("pAddr",F64), + Var("pte",CTy"SV_PTE"), + Var("pteAddr",F64),nVar"i", + bVar"global", + Apply + (Const + ("TLB", + ATy(qTy, + ATy(F4, + OTy(CTy"TLBEntry")))), + qVar"s")]),qVar"s")),qVar"s")]), + (LO(PTy(F64,PTy(CTy"SV_PTE",PTy(nTy,PTy(bTy,F64))))), + TP[LO F64,qVar"s"])])))])))) +; +val translateAddr_def = Def + ("translateAddr", + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"),Var("ac",CTy"accessType")], + Close + (qVar"state", + Let(Var("v",CTy"Privilege"), + Call + ("privilege",CTy"Privilege", + ITE(Bop(And, + Dest + ("MMPRV",bTy, + Dest + ("mstatus",CTy"mstatus", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))), + EQ(Var("ft",CTy"fetchType"),LC("Data",CTy"fetchType"))), + Dest + ("MPRV1",FTy 2, + Dest + ("mstatus",CTy"mstatus", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))), + Dest + ("MPRV",FTy 2, + Dest + ("mstatus",CTy"mstatus", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))))), + Let(TP[Var("v0",PTy(CTy"VM_Mode",CTy"Privilege")),qVar"s"], + Let(TP[Var("v0",CTy"VM_Mode"),qVar"s"], + Apply + (Call + ("vmType",ATy(qTy,PTy(CTy"VM_Mode",qTy)), + Dest + ("VM",FTy 5, + Dest + ("mstatus",CTy"mstatus", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state")))),qVar"state"), + TP[TP[Var("v0",CTy"VM_Mode"),Var("v",CTy"Privilege")], + qVar"s"]), + CS(Var("v0",PTy(CTy"VM_Mode",CTy"Privilege")), + [(TP[LC("Mbare",CTy"VM_Mode"),AVar(CTy"Privilege")], + TP[Mop(Some,Var("vAddr",F64)),qVar"s"]), + (TP[AVar(CTy"VM_Mode"),LC("Machine",CTy"Privilege")], + TP[Mop(Some,Var("vAddr",F64)),qVar"s"]), + (TP[LC("Sv39",CTy"VM_Mode"),AVar(CTy"Privilege")], + Apply + (Call + ("translate64",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("v",CTy"Privilege"),LN 2]),qVar"s")), + (TP[LC("Sv48",CTy"VM_Mode"),AVar(CTy"Privilege")], + Apply + (Call + ("translate64",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("vAddr",F64),Var("ft",CTy"fetchType"), + Var("ac",CTy"accessType"), + Var("v",CTy"Privilege"),LN 3]),qVar"s")), + (TP[AVar(CTy"VM_Mode"),AVar(CTy"Privilege")], + TP[LO F64,qVar"s"])]))))) +; +val matchLoadReservation_def = Def + ("matchLoadReservation",Var("vAddr",F64), + Close + (qVar"state", + Bop(And, + Mop(IsSome, + Apply(Const("ReserveLoad",ATy(qTy,OTy F64)),qVar"state")), + EQ(Mop(ValOf, + Apply(Const("ReserveLoad",ATy(qTy,OTy F64)),qVar"state")), + Var("vAddr",F64))))) +; +val branchTo_def = Def + ("branchTo",Var("newPC",F64), + Close + (qVar"state", + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + Mop(Some, + Call("BranchTo",CTy"TransferControl",Var("newPC",F64)))), + qVar"state"))) +; +val dfn'ADDI_def = Def + ("dfn'ADDI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Mop(SE F64,Var("imm",FTy 12))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'ADDIW_def = Def + ("dfn'ADDIW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Bop(Add, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + Mop(SE F64,Var("imm",FTy 12))),LN 31, + LN 0,F32)),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SLTI_def = Def + ("dfn'SLTI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + Bop(Lt, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")),Mop(SE F64,Var("imm",FTy 12)))), + Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'SLTIU_def = Def + ("dfn'SLTIU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + Bop(Ult, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")),Mop(SE F64,Var("imm",FTy 12)))), + Var("rd",FTy 5)]),qVar"s")))) +; +val dfn'ANDI_def = Def + ("dfn'ANDI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BAnd, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Mop(SE F64,Var("imm",FTy 12))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'ORI_def = Def + ("dfn'ORI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BOr, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Mop(SE F64,Var("imm",FTy 12))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'XORI_def = Def + ("dfn'XORI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BXor, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Mop(SE F64,Var("imm",FTy 12))), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SLLI_def = Def + ("dfn'SLLI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(Bop(And,bVar"v",Bop(Bit,Var("imm",FTy 6),LN 5)), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Lsl, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),Mop(Cast nTy,Var("imm",FTy 6))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SRLI_def = Def + ("dfn'SRLI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(Bop(And,bVar"v",Bop(Bit,Var("imm",FTy 6),LN 5)), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(TP[bVar"v",qVar"s"], + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Lsr, + ITE(bVar"v", + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")), + Mop(Cast nTy,Var("imm",FTy 6))), + Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'SRAI_def = Def + ("dfn'SRAI",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(Bop(And,bVar"v",Bop(Bit,Var("imm",FTy 6),LN 5)), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(TP[bVar"v",qVar"s"], + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Asr, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")), + Mop(Cast nTy,Var("imm",FTy 6))), + Var("rd",FTy 5)]),qVar"s")))))) +; +val dfn'SLLIW_def = Def + ("dfn'SLLIW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Lsl, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32),Mop(Cast nTy,Var("imm",FTy 5)))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SRLIW_def = Def + ("dfn'SRLIW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Lsr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32),Mop(Cast nTy,Var("imm",FTy 5)))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SRAIW_def = Def + ("dfn'SRAIW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Asr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32),Mop(Cast nTy,Var("imm",FTy 5)))), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'LUI_def = Def + ("dfn'LUI",TP[Var("rd",FTy 5),Var("imm",FTy 20)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,CC[Var("imm",FTy 20),LW(0,12)]),Var("rd",FTy 5)]), + qVar"state"))) +; +val dfn'AUIPC_def = Def + ("dfn'AUIPC",TP[Var("rd",FTy 5),Var("imm",FTy 20)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"state"), + Mop(SE F64,CC[Var("imm",FTy 20),LW(0,12)])), + Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'ADD_def = Def + ("dfn'ADD",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'ADDW_def = Def + ("dfn'ADDW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Add, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 31, + LN 0,F32))),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SUB_def = Def + ("dfn'SUB",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Sub, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SUBW_def = Def + ("dfn'SUBW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Sub, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 31, + LN 0,F32))),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SLT_def = Def + ("dfn'SLT",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + Bop(Lt, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0")))), + Var("rd",FTy 5)]),qVar"s0"))))) +; +val dfn'SLTU_def = Def + ("dfn'SLTU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + Bop(Ult, + ITE(bVar"v", + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")), + ITE(bVar"v0", + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0"), + LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0")))), + Var("rd",FTy 5)]),qVar"s0"))))) +; +val dfn'AND_def = Def + ("dfn'AND",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BAnd, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'OR_def = Def + ("dfn'OR",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BOr, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'XOR_def = Def + ("dfn'XOR",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(BXor, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'SLL_def = Def + ("dfn'SLL",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Lsl, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"), + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 4, + LN 0,FTy 5))),Var("rd",FTy 5)]),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Lsl, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"), + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SLLW_def = Def + ("dfn'SLLW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Lsl, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + Mop(Cast F32, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s"))))) +; +val dfn'SRL_def = Def + ("dfn'SRL",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + Bop(Lsr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + Mop(Cast F32, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Lsr, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"), + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SRLW_def = Def + ("dfn'SRLW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Lsr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + Mop(Cast F32, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s"))))) +; +val dfn'SRA_def = Def + ("dfn'SRA",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Asr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + Mop(Cast F32, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Asr, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"), + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 5, + LN 0,FTy 6))),Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'SRAW_def = Def + ("dfn'SRAW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Asr, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"),LN 31, + LN 0,F32), + Mop(Cast F32, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4,LN 0,FTy 5)))),Var("rd",FTy 5)]), + qVar"s"))))) +; +val dfn'MUL_def = Def + ("dfn'MUL",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Mul, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'MULH_def = Def + ("dfn'MULH",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Let(Var("prod",FTy 128), + Bop(Mul, + Mop(SE(FTy 128), + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"))), + Mop(SE(FTy 128), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0"), + LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0")))), + Let(TP[bVar"v",qVar"s"], + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s0"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITE(bVar"v", + Mop(SE F64, + EX(Var("prod",FTy 128),LN 63,LN 32, + F32)), + Mop(SE F64, + EX(Var("prod",FTy 128),LN 127, + LN 64,F64))),Var("rd",FTy 5)]), + qVar"s"))))))) +; +val dfn'MULHU_def = Def + ("dfn'MULHU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Let(Var("prod",FTy 128), + Bop(Mul, + ITE(bVar"v", + Mop(Cast(FTy 128), + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Mop(Cast(FTy 128), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"))), + ITE(bVar"v0", + Mop(Cast(FTy 128), + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Mop(Cast(FTy 128), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0")))), + Let(TP[bVar"v",qVar"s"], + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s0"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITE(bVar"v", + Mop(Cast F64, + EX(Var("prod",FTy 128),LN 63,LN 32, + F32)), + EX(Var("prod",FTy 128),LN 127,LN 64,F64)), + Var("rd",FTy 5)]),qVar"s"))))))) +; +val dfn'MULHSU_def = Def + ("dfn'MULHSU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Let(Var("prod",FTy 128), + Bop(Mul, + ITE(bVar"v", + Mop(SE(FTy 128), + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Mop(SE(FTy 128), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"))), + ITE(bVar"v0", + Mop(Cast(FTy 128), + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Mop(Cast(FTy 128), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0")))), + Let(TP[bVar"v",qVar"s"], + Apply + (Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU), + qVar"s0"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITE(bVar"v", + Mop(SE F64, + EX(Var("prod",FTy 128),LN 63,LN 32, + F32)), + EX(Var("prod",FTy 128),LN 127,LN 64,F64)), + Var("rd",FTy 5)]),qVar"s"))))))) +; +val dfn'MULW_def = Def + ("dfn'MULW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Mop(SE F64, + Bop(Mul, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32), + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 31,LN 0,F32))),LN 31,LN 0,F32)), + Var("rd",FTy 5)]),qVar"s"))))) +; +val dfn'DIV_def = Def + ("dfn'DIV",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + ITE(EQ(Apply(Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + LW(0,64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,LW(1,1)),Var("rd",FTy 5)]),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Quot, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'REM_def = Def + ("dfn'REM",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + ITE(EQ(Apply(Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + LW(0,64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Var("rd",FTy 5)]),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Rem, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'DIVU_def = Def + ("dfn'DIVU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + Let(Var("v0",F64), + ITE(bVar"v0", + Mop(Cast F64, + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0")), + ITE(EQ(Var("v0",F64),LW(0,64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,LW(1,1)),Var("rd",FTy 5)]), + qVar"s0"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Div, + ITE(bVar"v", + Mop(Cast F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")), + Var("v0",F64)),Var("rd",FTy 5)]), + qVar"s0"))))))) +; +val dfn'REMU_def = Def + ("dfn'REMU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + ITE(EQ(Apply(Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + LW(0,64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),Var("rd",FTy 5)]),qVar"state"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Mod, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state")))) +; +val dfn'DIVW_def = Def + ("dfn'DIVW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v0",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"s"), + LN 31,LN 0,F32), + ITE(EQ(Var("v0",F32),LW(0,32)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,LW(1,1)),Var("rd",FTy 5)]), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Quot, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32),Var("v0",F32))), + Var("rd",FTy 5)]),qVar"s"))))))) +; +val dfn'REMW_def = Def + ("dfn'REMW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32), + Let(Var("v0",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 31,LN 0,F32), + ITE(EQ(Var("v0",F32),LW(0,32)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,Var("v",F32)), + Var("rd",FTy 5)]),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Rem,Var("v",F32),Var("v0",F32))), + Var("rd",FTy 5)]),qVar"s")))))))) +; +val dfn'DIVUW_def = Def + ("dfn'DIVUW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v0",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"s"), + LN 31,LN 0,F32), + ITE(EQ(Var("v0",F32),LW(0,32)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,LW(1,1)),Var("rd",FTy 5)]), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Div, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32),Var("v0",F32))), + Var("rd",FTy 5)]),qVar"s"))))))) +; +val dfn'REMUW_def = Def + ("dfn'REMUW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32), + Let(Var("v0",F32), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 31,LN 0,F32), + ITE(EQ(Var("v0",F32),LW(0,32)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64,Var("v",F32)), + Var("rd",FTy 5)]),qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Bop(Mod,Var("v",F32),Var("v0",F32))), + Var("rd",FTy 5)]),qVar"s")))))))) +; +val dfn'JAL_def = Def + ("dfn'JAL",TP[Var("rd",FTy 5),Var("imm",FTy 20)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"state"), + Bop(Lsl,Mop(SE F64,Var("imm",FTy 20)),LN 1)), + ITE(Bop(Bit,Var("v",F64),LN 0), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Fetch_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Apply + (Call("branchTo",ATy(qTy,qTy),Var("v",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Add, + Apply(Const("PC",ATy(qTy,F64)),qVar"state"), + Apply + (Const("Skip",ATy(qTy,F64)),qVar"state")), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'JALR_def = Def + ("dfn'JALR",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(BAnd, + Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("imm",FTy 12))),Mop(SE F64,LW(2,2))), + ITE(Bop(Bit,Var("v",F64),LN 0), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Fetch_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Apply + (Call("branchTo",ATy(qTy,qTy),Var("v",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Bop(Add, + Apply(Const("PC",ATy(qTy,F64)),qVar"state"), + Apply + (Const("Skip",ATy(qTy,F64)),qVar"state")), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'BEQ_def = Def + ("dfn'BEQ",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(EQ(ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'BNE_def = Def + ("dfn'BNE",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(Mop(Not, + EQ(ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"), + LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s0"), + LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0")))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'BLT_def = Def + ("dfn'BLT",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(Bop(Lt, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'BLTU_def = Def + ("dfn'BLTU",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(Bop(Ult, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'BGE_def = Def + ("dfn'BGE",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(Bop(Ge, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'BGEU_def = Def + ("dfn'BGEU",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + Let(TP[bVar"v0",qVar"s0"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"s"), + ITE(Bop(Uge, + ITE(bVar"v", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")), + ITE(bVar"v0", + Mop(SE F64, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"),LN 31,LN 0,F32)), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s0"))), + Apply + (Call + ("branchTo",ATy(qTy,qTy), + Bop(Add,Apply(Const("PC",ATy(qTy,F64)),qVar"s0"), + Bop(Lsl,Mop(SE F64,Var("offs",FTy 12)),LN 1))), + qVar"s0"),qVar"s0"))))) +; +val dfn'LW_def = Def + ("dfn'LW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'LWU_def = Def + ("dfn'LWU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F64), + Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"s"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + EX(Apply + (Call + ("rawReadData", + ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + LN 31,LN 0,F32)), + Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))))) +; +val dfn'LH_def = Def + ("dfn'LH",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 15, + LN 0,F16)),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'LHU_def = Def + ("dfn'LHU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 15, + LN 0,F16)),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'LB_def = Def + ("dfn'LB",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 7, + LN 0,F8)),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'LBU_def = Def + ("dfn'LBU",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 7, + LN 0,F8)),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'LD_def = Def + ("dfn'LD",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F64), + Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"s"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))))) +; +val dfn'SW_def = Def + ("dfn'SW",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 4]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'SH_def = Def + ("dfn'SH",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 2]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'SB_def = Def + ("dfn'SB",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 1]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'SD_def = Def + ("dfn'SD",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F64), + Bop(Add, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"s"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"),LN 8]), + qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault", + CTy"ExceptionType"),Var("v",F64)]), + qVar"s"))]))))))) +; +val dfn'FENCE_def = Def + ("dfn'FENCE", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("pred",F4),Var("succ",F4)],LU) +; +val dfn'FENCE_I_def = Def + ("dfn'FENCE_I",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)],LU) +; +val dfn'LR_W_def = Def + ("dfn'LR_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'ReserveLoad",ATy(qTy,qTy), + Mop(Some,Var("v",F64))), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Apply + (Call + ("rawReadData", + ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + LN 31,LN 0,F32)),Var("rd",FTy 5)]), + qVar"s"))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'LR_D_def = Def + ("dfn'LR_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"s"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'ReserveLoad",ATy(qTy,qTy), + Mop(Some,Var("v",F64))), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Apply + (Call + ("rawReadData", + ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Var("rd",FTy 5)]),qVar"s"))), + (LO F64, + Apply + (Call + ("signalAddressException", + ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))))) +; +val dfn'SC_W_def = Def + ("dfn'SC_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITB([(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state")), + (Mop(Not, + Apply + (Call + ("matchLoadReservation",ATy(qTy,bTy),Var("v",F64)), + qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(1,64),Var("rd",FTy 5)]),qVar"state"))], + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call("write'ReserveLoad",ATy(qTy,qTy),LO F64), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + LN 4]),qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'SC_D_def = Def + ("dfn'SC_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply(Call("in32BitMode",ATy(qTy,PTy(bTy,qTy)),LU),qVar"state"), + ITE(bVar"v", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"), + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"s"), + ITB([(Mop(Not, + EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"s")), + (Mop(Not, + Apply + (Call + ("matchLoadReservation",ATy(qTy,bTy), + Var("v",F64)),qVar"s")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(1,64),Var("rd",FTy 5)]),qVar"s"))], + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"s"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'ReserveLoad",ATy(qTy,qTy), + LO F64), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)), + qVar"s"),LN 8]),qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException", + ATy(qTy,qTy), + TP[LC("Store_AMO_Fault", + CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))))) +; +val dfn'AMOSWAP_W_def = Def + ("dfn'AMOSWAP_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + EX(Apply + (Call + ("rawReadData", + ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + LN 31,LN 0,F32)),Var("rd",FTy 5)]), + qVar"s"))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOSWAP_D_def = Def + ("dfn'AMOSWAP_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Var("rd",FTy 5)]),qVar"s"))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOADD_W_def = Def + ("dfn'AMOADD_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(Add, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOADD_D_def = Def + ("dfn'AMOADD_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(Add, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOXOR_W_def = Def + ("dfn'AMOXOR_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BXor, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOXOR_D_def = Def + ("dfn'AMOXOR_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BXor, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOAND_W_def = Def + ("dfn'AMOAND_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BAnd, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOAND_D_def = Def + ("dfn'AMOAND_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BAnd, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOOR_W_def = Def + ("dfn'AMOOR_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BOr, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOOR_D_def = Def + ("dfn'AMOOR_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Bop(BOr, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMIN_W_def = Def + ("dfn'AMOMIN_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Smin, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMIN_D_def = Def + ("dfn'AMOMIN_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Smin, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMAX_W_def = Def + ("dfn'AMOMAX_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Smax, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMAX_D_def = Def + ("dfn'AMOMAX_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Smax, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMINU_W_def = Def + ("dfn'AMOMINU_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Min, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMINU_D_def = Def + ("dfn'AMOMINU_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Min, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMAXU_W_def = Def + ("dfn'AMOMAXU_W", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 1,LN 0,FTy 2),LW(0,2))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Mop(SE F64, + EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Max, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 4]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'AMOMAXU_D_def = Def + ("dfn'AMOMAXU_D", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + ITE(Mop(Not,EQ(EX(Var("v",F64),LN 2,LN 0,FTy 3),LW(0,3))), + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("AMO_Misaligned",CTy"ExceptionType"), + Var("v",F64)]),qVar"state"), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Let(Var("v",F64), + Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Max, + TP[Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"s"), + Var("v",F64)]),LN 8]), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + qVar"s")))), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))])))))) +; +val dfn'FLW_def = Def + ("dfn'FLW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'FPRS",ATy(qTy,qTy), + TP[EX(Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"),LN 31, + LN 0,F32),Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'FSW_def = Def + ("dfn'FSW",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Mop(Cast F64, + Apply + (Call + ("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"s")),LN 4]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'FADD_S_def = Def + ("dfn'FADD_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPAdd 32, + TP[Var("r",rTy), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSUB_S_def = Def + ("dfn'FSUB_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSub 32, + TP[Var("r",rTy), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMUL_S_def = Def + ("dfn'FMUL_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPMul 32, + TP[Var("r",rTy), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FDIV_S_def = Def + ("dfn'FDIV_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPDiv 32, + TP[Var("r",rTy), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSQRT_S_def = Def + ("dfn'FSQRT_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSqrt 32, + TP[Var("r",rTy), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMIN_S_def = Def + ("dfn'FMIN_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CS(Mop(FPCmp 32,TP[Var("v",F32),Var("v0",F32)]), + [(binary_ieeeSyntax.LT_tm,Var("v",F32)), + (binary_ieeeSyntax.EQ_tm,Var("v",F32)), + (binary_ieeeSyntax.GT_tm,Var("v0",F32)), + (binary_ieeeSyntax.UN_tm, + ITB([(Bop(Or, + Bop(Or, + Call + ("FP32_IsSignalingNan",bTy, + Var("v",F32)), + Call + ("FP32_IsSignalingNan",bTy, + Var("v0",F32))), + Bop(And, + EQ(Var("v",F32), + Const + ("RV32_CanonicalNan",F32)), + EQ(Var("v0",F32), + Const + ("RV32_CanonicalNan",F32)))), + Const("RV32_CanonicalNan",F32)), + (EQ(Var("v",F32), + Const("RV32_CanonicalNan",F32)), + Var("v0",F32))],Var("v",F32)))])]), + qVar"state"))))) +; +val dfn'FMAX_S_def = Def + ("dfn'FMAX_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CS(Mop(FPCmp 32,TP[Var("v",F32),Var("v0",F32)]), + [(binary_ieeeSyntax.LT_tm,Var("v0",F32)), + (binary_ieeeSyntax.EQ_tm,Var("v0",F32)), + (binary_ieeeSyntax.GT_tm,Var("v",F32)), + (binary_ieeeSyntax.UN_tm, + ITB([(Bop(Or, + Bop(Or, + Call + ("FP32_IsSignalingNan",bTy, + Var("v",F32)), + Call + ("FP32_IsSignalingNan",bTy, + Var("v0",F32))), + Bop(And, + EQ(Var("v",F32), + Const + ("RV32_CanonicalNan",F32)), + EQ(Var("v0",F32), + Const + ("RV32_CanonicalNan",F32)))), + Const("RV32_CanonicalNan",F32)), + (EQ(Var("v",F32), + Const("RV32_CanonicalNan",F32)), + Var("v0",F32))],Var("v",F32)))])]), + qVar"state"))))) +; +val dfn'FMADD_S_def = Def + ("dfn'FMADD_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPAdd 32, + TP[Var("r",rTy), + Mop(FPMul 32, + TP[Var("r",rTy), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs3",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMSUB_S_def = Def + ("dfn'FMSUB_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSub 32, + TP[Var("r",rTy), + Mop(FPMul 32, + TP[Var("r",rTy), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs3",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FNMADD_S_def = Def + ("dfn'FNMADD_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPNeg 32, + Mop(FPAdd 32, + TP[Var("r",rTy), + Mop(FPMul 32, + TP[Var("r",rTy), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call + ("FPRS",ATy(qTy,F32),Var("rs3",FTy 5)), + qVar"state")]))]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FNMSUB_S_def = Def + ("dfn'FNMSUB_S", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPNeg 32, + Mop(FPSub 32, + TP[Var("r",rTy), + Mop(FPMul 32, + TP[Var("r",rTy), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call + ("FPRS",ATy(qTy,F32),Var("rs3",FTy 5)), + qVar"state")]))]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_S_W_def = Def + ("dfn'FCVT_S_W",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 32, + TP[Var("r",rTy), + Mop(Cast iTy, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state"),LN 31,LN 0,F32))])]), + qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_S_WU_def = Def + ("dfn'FCVT_S_WU",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 32, + TP[Var("r",rTy), + Mop(Cast iTy, + CC[LW(0,1), + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs",FTy 5)),qVar"state"), + LN 31,LN 0,F32)])])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_W_S_def = Def + ("dfn'FCVT_W_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 32,TP[Var("r",rTy),Var("v",F32)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + EQ(Var("v",F32),POSINF32)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 31),LN 1))), + (EQ(Var("v",F32),NEGINF32), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 31)))), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 31),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 31),LN 1))), + (Bop(Lt,iVar"val", + Mop(Neg,Bop(Exp,LI 2,LN 31))), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 31))))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_WU_S_def = Def + ("dfn'FCVT_WU_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 32,TP[Var("r",rTy),Var("v",F32)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + EQ(Var("v",F32),POSINF32)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 32),LN 1))), + (EQ(Var("v",F32),NEGINF32),LW(0,64)), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 32),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 32),LN 1))), + (Bop(Lt,iVar"val",LI 0),LW(0,64))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_S_L_def = Def + ("dfn'FCVT_S_L",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 32, + TP[Var("r",rTy), + Mop(Cast iTy, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state"))])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_S_LU_def = Def + ("dfn'FCVT_S_LU",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 32, + TP[Var("r",rTy), + Mop(Cast iTy, + CC[LW(0,1), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state")])])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_L_S_def = Def + ("dfn'FCVT_L_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 32,TP[Var("r",rTy),Var("v",F32)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + EQ(Var("v",F32),POSINF32)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 63),LN 1))), + (EQ(Var("v",F32),NEGINF32), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 63)))), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 63),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 63),LN 1))), + (Bop(Lt,iVar"val", + Mop(Neg,Bop(Exp,LI 2,LN 63))), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 63))))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_LU_S_def = Def + ("dfn'FCVT_LU_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 32,TP[Var("r",rTy),Var("v",F32)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + EQ(Var("v",F32),POSINF32)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 64),LN 1))), + (EQ(Var("v",F32),NEGINF32),LW(0,64)), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 64),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 64),LN 1))), + (Bop(Lt,iVar"val",LI 0),LW(0,64))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSGNJ_S_def = Def + ("dfn'FSGNJ_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Mop(Cast F1, + Call + ("FP32_Sign",bTy, + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state"))), + EX(Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"),LN 30,LN 0,FTy 31)]]),qVar"state"))) +; +val dfn'FSGNJN_S_def = Def + ("dfn'FSGNJN_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Mop(Cast F1, + Mop(Not, + Call + ("FP32_Sign",bTy, + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)), + qVar"state")))), + EX(Apply + (Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)), + qVar"state"),LN 30,LN 0,FTy 31)]]),qVar"state"))) +; +val dfn'FSGNJX_S_def = Def + ("dfn'FSGNJX_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Bop(BXor, + Mop(Cast F1, + Call + ("FP32_Sign",bTy, + Apply + (Call + ("FPRS",ATy(qTy,F32), + Var("rs2",FTy 5)),qVar"state"))), + Mop(Cast F1,Call("FP32_Sign",bTy,Var("v",F32)))), + EX(Var("v",F32),LN 30,LN 0,FTy 31)]]),qVar"state")))) +; +val dfn'FMV_X_S_def = Def + ("dfn'FMV_X_S",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'FMV_S_X_def = Def + ("dfn'FMV_S_X",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + EX(Apply + (Call("GPR",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + LN 31,LN 0,F32)]),qVar"state"))) +; +val dfn'FEQ_S_def = Def + ("dfn'FEQ_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Call("FP32_IsSignalingNan",bTy,Var("v",F32)), + Call("FP32_IsSignalingNan",bTy,Var("v0",F32))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 32,TP[Var("v",F32),Var("v0",F32)]), + [(binary_ieeeSyntax.LT_tm,LW(0,64)), + (binary_ieeeSyntax.EQ_tm,LW(1,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FLT_S_def = Def + ("dfn'FLT_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + Mop(FPIsNan 32,Var("v0",F32))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 32,TP[Var("v",F32),Var("v0",F32)]), + [(binary_ieeeSyntax.LT_tm,LW(1,64)), + (binary_ieeeSyntax.EQ_tm,LW(0,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FLE_S_def = Def + ("dfn'FLE_S",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F32), + Apply(Call("FPRS",ATy(qTy,F32),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F32), + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Mop(FPIsNan 32,Var("v",F32)), + Mop(FPIsNan 32,Var("v0",F32))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 32,TP[Var("v",F32),Var("v0",F32)]), + [(binary_ieeeSyntax.LT_tm,LW(1,64)), + (binary_ieeeSyntax.EQ_tm,LW(1,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FCLASS_S_def = Def + ("dfn'FCLASS_S",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Let(TP[Var("v",F32),Var("s",PTy(FTy 10,qTy))], + TP[Apply(Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)),qVar"state"), + LW(0,10),qVar"state"], + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + BFI(LN 9,LN 9, + Mop(Cast F1, + EQ(Var("v",F32), + Const("RV32_CanonicalNan",F32))), + BFI(LN 8,LN 8, + Mop(Cast F1, + Call + ("FP32_IsSignalingNan",bTy, + Var("v",F32))), + BFI(LN 7,LN 7, + Mop(Cast F1,EQ(Var("v",F32),POSINF32)), + BFI(LN 6,LN 6, + Mop(Cast F1, + Bop(And, + Mop(Not, + Call + ("FP32_Sign",bTy, + Var("v",F32))), + Mop(FPIsNormal 32, + Var("v",F32)))), + BFI(LN 5,LN 5, + Mop(Cast F1, + Bop(And, + Mop(Not, + Call + ("FP32_Sign",bTy, + Var("v",F32))), + Mop(FPIsSubnormal 32, + Var("v",F32)))), + BFI(LN 4,LN 4, + Mop(Cast F1, + EQ(Var("v",F32), + POSZERO32)), + BFI(LN 3,LN 3, + Mop(Cast F1, + EQ(Var("v",F32), + NEGZERO32)), + BFI(LN 2,LN 2, + Mop(Cast F1, + Bop(And, + Call + ("FP32_Sign", + bTy, + Var("v", + F32)), + Mop(FPIsSubnormal 32, + Var("v", + F32)))), + BFI(LN 1,LN 1, + Mop(Cast F1, + Bop(And, + Call + ("FP32_Sign", + bTy, + Var("v", + F32)), + Mop(FPIsNormal 32, + Var("v", + F32)))), + BFI(LN 0,LN 0, + Mop(Cast F1, + EQ(Var("v", + F32), + NEGINF32)), + Mop(Fst, + Var("s", + PTy(FTy 10, + qTy)))))))))))))), + Var("rd",FTy 5)]),Mop(Snd,Var("s",PTy(FTy 10,qTy))))))) +; +val dfn'FLD_def = Def + ("dfn'FLD",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("write'FPRD",ATy(qTy,qTy), + TP[Apply + (Call + ("rawReadData",ATy(qTy,F64), + Var("pAddr",F64)),qVar"s"), + Var("rd",FTy 5)]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Load_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'FSD_def = Def + ("dfn'FSD",TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("offs",FTy 12)], + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply(Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Mop(SE F64,Var("offs",FTy 12))), + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Data",CTy"fetchType"), + LC("Write",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pAddr",F64)), + Apply + (Call + ("rawWriteData",ATy(qTy,qTy), + TP[Var("pAddr",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"s"),LN 8]),qVar"s")), + (LO F64, + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Store_AMO_Fault",CTy"ExceptionType"), + Var("v",F64)]),qVar"s"))]))))) +; +val dfn'FADD_D_def = Def + ("dfn'FADD_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPAdd 64, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSUB_D_def = Def + ("dfn'FSUB_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSub 64, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMUL_D_def = Def + ("dfn'FMUL_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPMul 64, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FDIV_D_def = Def + ("dfn'FDIV_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPDiv 64, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSQRT_D_def = Def + ("dfn'FSQRT_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSqrt 64, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMIN_D_def = Def + ("dfn'FMIN_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CS(Mop(FPCmp 64,TP[Var("v",F64),Var("v0",F64)]), + [(binary_ieeeSyntax.LT_tm,Var("v",F64)), + (binary_ieeeSyntax.EQ_tm,Var("v",F64)), + (binary_ieeeSyntax.GT_tm,Var("v0",F64)), + (binary_ieeeSyntax.UN_tm, + ITB([(Bop(Or, + Bop(Or, + Call + ("FP64_IsSignalingNan",bTy, + Var("v",F64)), + Call + ("FP64_IsSignalingNan",bTy, + Var("v0",F64))), + Bop(And, + EQ(Var("v",F64), + Const + ("RV64_CanonicalNan",F64)), + EQ(Var("v0",F64), + Const + ("RV64_CanonicalNan",F64)))), + Const("RV64_CanonicalNan",F64)), + (EQ(Var("v",F64), + Const("RV64_CanonicalNan",F64)), + Var("v0",F64))],Var("v",F64)))])]), + qVar"state"))))) +; +val dfn'FMAX_D_def = Def + ("dfn'FMAX_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CS(Mop(FPCmp 64,TP[Var("v",F64),Var("v0",F64)]), + [(binary_ieeeSyntax.LT_tm,Var("v0",F64)), + (binary_ieeeSyntax.EQ_tm,Var("v0",F64)), + (binary_ieeeSyntax.GT_tm,Var("v",F64)), + (binary_ieeeSyntax.UN_tm, + ITB([(Bop(Or, + Bop(Or, + Call + ("FP64_IsSignalingNan",bTy, + Var("v",F64)), + Call + ("FP64_IsSignalingNan",bTy, + Var("v0",F64))), + Bop(And, + EQ(Var("v",F64), + Const + ("RV64_CanonicalNan",F64)), + EQ(Var("v0",F64), + Const + ("RV64_CanonicalNan",F64)))), + Const("RV64_CanonicalNan",F64)), + (EQ(Var("v",F64), + Const("RV64_CanonicalNan",F64)), + Var("v0",F64))],Var("v",F64)))])]), + qVar"state"))))) +; +val dfn'FMADD_D_def = Def + ("dfn'FMADD_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPAdd 64, + TP[Var("r",rTy), + Mop(FPMul 64, + TP[Var("r",rTy), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs3",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FMSUB_D_def = Def + ("dfn'FMSUB_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPSub 64, + TP[Var("r",rTy), + Mop(FPMul 64, + TP[Var("r",rTy), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs3",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FNMADD_D_def = Def + ("dfn'FNMADD_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPNeg 64, + Mop(FPAdd 64, + TP[Var("r",rTy), + Mop(FPMul 64, + TP[Var("r",rTy), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call + ("FPRD",ATy(qTy,F64),Var("rs3",FTy 5)), + qVar"state")]))]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FNMSUB_D_def = Def + ("dfn'FNMSUB_D", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5), + Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPNeg 64, + Mop(FPSub 64, + TP[Var("r",rTy), + Mop(FPMul 64, + TP[Var("r",rTy), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"state")]), + Apply + (Call + ("FPRD",ATy(qTy,F64),Var("rs3",FTy 5)), + qVar"state")]))]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_D_W_def = Def + ("dfn'FCVT_D_W",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 64, + TP[Var("r",rTy), + Mop(Cast iTy, + EX(Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state"),LN 31,LN 0,F32))])]), + qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_D_WU_def = Def + ("dfn'FCVT_D_WU",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 64, + TP[Var("r",rTy), + Mop(Cast iTy, + CC[LW(0,1), + EX(Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs",FTy 5)),qVar"state"), + LN 31,LN 0,F32)])])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_W_D_def = Def + ("dfn'FCVT_W_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 64,TP[Var("r",rTy),Var("v",F64)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + EQ(Var("v",F64),POSINF64)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 31),LN 1))), + (EQ(Var("v",F64),NEGINF64), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 31)))), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 31),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 31),LN 1))), + (Bop(Lt,iVar"val", + Mop(Neg,Bop(Exp,LI 2,LN 31))), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 31))))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_WU_D_def = Def + ("dfn'FCVT_WU_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 64,TP[Var("r",rTy),Var("v",F64)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + EQ(Var("v",F64),POSINF64)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 32),LN 1))), + (EQ(Var("v",F64),NEGINF64),LW(0,64)), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 32),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 32),LN 1))), + (Bop(Lt,iVar"val",LI 0),LW(0,64))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_D_L_def = Def + ("dfn'FCVT_D_L",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 64, + TP[Var("r",rTy), + Mop(Cast iTy, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state"))])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_D_LU_def = Def + ("dfn'FCVT_D_LU",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FPFromInt 64, + TP[Var("r",rTy), + Mop(Cast iTy, + CC[LW(0,1), + Apply + (Call + ("GPR",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state")])])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_L_D_def = Def + ("dfn'FCVT_L_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 64,TP[Var("r",rTy),Var("v",F64)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + EQ(Var("v",F64),POSINF64)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 63),LN 1))), + (EQ(Var("v",F64),NEGINF64), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 63)))), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 63),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 63),LN 1))), + (Bop(Lt,iVar"val", + Mop(Neg,Bop(Exp,LI 2,LN 63))), + Mop(Neg, + Mop(Cast F64,Bop(Exp,LN 2,LN 63))))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_LU_D_def = Def + ("dfn'FCVT_LU_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Let(Var("v",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + Let(iVar"val", + Mop(ValOf,Mop(FPToInt 64,TP[Var("r",rTy),Var("v",F64)])), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[ITB([(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + EQ(Var("v",F64),POSINF64)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 64),LN 1))), + (EQ(Var("v",F64),NEGINF64),LW(0,64)), + (Bop(Gt,iVar"val", + Bop(Sub,Bop(Exp,LI 2,LN 64),LI 1)), + Mop(Cast F64, + Bop(Sub,Bop(Exp,LN 2,LN 64),LN 1))), + (Bop(Lt,iVar"val",LI 0),LW(0,64))], + Mop(Cast F64,iVar"val")),Var("rd",FTy 5)]), + qVar"state")))), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_S_D_def = Def + ("dfn'FCVT_S_D",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRS",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FP64To32, + TP[Var("r",rTy), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state")])]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FCVT_D_S_def = Def + ("dfn'FCVT_D_S",TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("fprnd",FTy 3)], + Close + (qVar"state", + CS(Apply + (Call("round",ATy(qTy,OTy rTy),Var("fprnd",FTy 3)),qVar"state"), + [(Mop(Some,Var("r",rTy)), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Mop(FP32To64, + Apply + (Call("FPRS",ATy(qTy,F32),Var("rs",FTy 5)), + qVar"state"))]),qVar"state")), + (LO rTy, + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state"))]))) +; +val dfn'FSGNJ_D_def = Def + ("dfn'FSGNJ_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Mop(Cast F1, + Call + ("FP64_Sign",bTy, + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state"))), + EX(Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),LN 62,LN 0,FTy 63)]]),qVar"state"))) +; +val dfn'FSGNJN_D_def = Def + ("dfn'FSGNJN_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Mop(Cast F1, + Mop(Not, + Call + ("FP64_Sign",bTy, + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)), + qVar"state")))), + EX(Apply + (Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"),LN 62,LN 0,FTy 63)]]),qVar"state"))) +; +val dfn'FSGNJX_D_def = Def + ("dfn'FSGNJX_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + CC[Bop(BXor, + Mop(Cast F1, + Call + ("FP64_Sign",bTy, + Apply + (Call + ("FPRD",ATy(qTy,F64), + Var("rs2",FTy 5)),qVar"state"))), + Mop(Cast F1,Call("FP64_Sign",bTy,Var("v",F64)))), + EX(Var("v",F64),LN 62,LN 0,FTy 63)]]),qVar"state")))) +; +val dfn'FMV_X_D_def = Def + ("dfn'FMV_X_D",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(SE F64, + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)), + qVar"state")),Var("rd",FTy 5)]),qVar"state"))) +; +val dfn'FMV_D_X_def = Def + ("dfn'FMV_D_X",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Apply + (Call + ("writeFPRD",ATy(qTy,qTy), + TP[Var("rd",FTy 5), + Apply(Call("GPR",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state")]), + qVar"state"))) +; +val dfn'FEQ_D_def = Def + ("dfn'FEQ_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Call("FP64_IsSignalingNan",bTy,Var("v",F64)), + Call("FP64_IsSignalingNan",bTy,Var("v0",F64))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 64,TP[Var("v",F64),Var("v0",F64)]), + [(binary_ieeeSyntax.LT_tm,LW(0,64)), + (binary_ieeeSyntax.EQ_tm,LW(1,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FLT_D_def = Def + ("dfn'FLT_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + Mop(FPIsNan 64,Var("v0",F64))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 64,TP[Var("v",F64),Var("v0",F64)]), + [(binary_ieeeSyntax.LT_tm,LW(1,64)), + (binary_ieeeSyntax.EQ_tm,LW(0,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FLE_D_def = Def + ("dfn'FLE_D",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + Close + (qVar"state", + Let(Var("v",F64), + Apply(Call("FPRD",ATy(qTy,F64),Var("rs1",FTy 5)),qVar"state"), + Let(Var("v0",F64), + Apply + (Call("FPRD",ATy(qTy,F64),Var("rs2",FTy 5)),qVar"state"), + ITE(Bop(Or,Mop(FPIsNan 64,Var("v",F64)), + Mop(FPIsNan 64,Var("v0",F64))), + Apply + (Call("setFP_Invalid",ATy(qTy,qTy),LU), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[LW(0,64),Var("rd",FTy 5)]),qVar"state")), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[CS(Mop(FPCmp 64,TP[Var("v",F64),Var("v0",F64)]), + [(binary_ieeeSyntax.LT_tm,LW(1,64)), + (binary_ieeeSyntax.EQ_tm,LW(1,64)), + (binary_ieeeSyntax.GT_tm,LW(0,64)), + (binary_ieeeSyntax.UN_tm,LW(0,64))]), + Var("rd",FTy 5)]),qVar"state")))))) +; +val dfn'FCLASS_D_def = Def + ("dfn'FCLASS_D",TP[Var("rd",FTy 5),Var("rs",FTy 5)], + Close + (qVar"state", + Let(TP[Var("v",F64),Var("s",PTy(FTy 10,qTy))], + TP[Apply(Call("FPRD",ATy(qTy,F64),Var("rs",FTy 5)),qVar"state"), + LW(0,10),qVar"state"], + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Mop(Cast F64, + BFI(LN 9,LN 9, + Mop(Cast F1, + EQ(Var("v",F64), + Const("RV64_CanonicalNan",F64))), + BFI(LN 8,LN 8, + Mop(Cast F1, + Call + ("FP64_IsSignalingNan",bTy, + Var("v",F64))), + BFI(LN 7,LN 7, + Mop(Cast F1,EQ(Var("v",F64),POSINF64)), + BFI(LN 6,LN 6, + Mop(Cast F1, + Bop(And, + Mop(Not, + Call + ("FP64_Sign",bTy, + Var("v",F64))), + Mop(FPIsNormal 64, + Var("v",F64)))), + BFI(LN 5,LN 5, + Mop(Cast F1, + Bop(And, + Mop(Not, + Call + ("FP64_Sign",bTy, + Var("v",F64))), + Mop(FPIsSubnormal 64, + Var("v",F64)))), + BFI(LN 4,LN 4, + Mop(Cast F1, + EQ(Var("v",F64), + POSZERO64)), + BFI(LN 3,LN 3, + Mop(Cast F1, + EQ(Var("v",F64), + NEGZERO64)), + BFI(LN 2,LN 2, + Mop(Cast F1, + Bop(And, + Call + ("FP64_Sign", + bTy, + Var("v", + F64)), + Mop(FPIsSubnormal 64, + Var("v", + F64)))), + BFI(LN 1,LN 1, + Mop(Cast F1, + Bop(And, + Call + ("FP64_Sign", + bTy, + Var("v", + F64)), + Mop(FPIsNormal 64, + Var("v", + F64)))), + BFI(LN 0,LN 0, + Mop(Cast F1, + EQ(Var("v", + F64), + NEGINF64)), + Mop(Fst, + Var("s", + PTy(FTy 10, + qTy)))))))))))))), + Var("rd",FTy 5)]),Mop(Snd,Var("s",PTy(FTy 10,qTy))))))) +; +val dfn'ECALL_def = Def + ("dfn'ECALL",qVar"state", + Apply(Call("signalEnvCall",ATy(qTy,qTy),LU),qVar"state")) +; +val dfn'EBREAK_def = Def + ("dfn'EBREAK",qVar"state", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Breakpoint",CTy"ExceptionType")),qVar"state")) +; +val dfn'ERET_def = Def + ("dfn'ERET",qVar"state", + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + Mop(Some,Const("Ereturn",CTy"TransferControl"))),qVar"state")) +; +val dfn'MRTS_def = Def + ("dfn'MRTS",qVar"state", + Let(TP[Var("v",CTy"SupervisorCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("scause", + TP[Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")), + qVar"state"), + Dest + ("mcause",CTy"mcause", + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state"))])),qVar"state"), + TP[Apply(Const("SCSR",ATy(qTy,CTy"SupervisorCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"SupervisorCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("sbadaddr", + TP[Var("v",CTy"SupervisorCSR"), + Dest + ("mbadaddr",F64, + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s"))])),qVar"s"), + TP[Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'SCSR",ATy(qTy,qTy), + Rupd + ("sepc", + TP[Var("v",CTy"SupervisorCSR"), + Dest + ("mepc",F64, + Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s"))])),qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + Mop(Some,Const("Mrts",CTy"TransferControl"))), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MPRV", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("privLevel",FTy 2, + LC("Supervisor",CTy"Privilege"))])])), + qVar"s")))))) +; +val dfn'WFI_def = Def0 ("dfn'WFI",LU) +; +val checkCSROp_def = Def + ("checkCSROp", + TP[Var("csr",FTy 12),Var("rs1",FTy 5),Var("a",CTy"accessType")], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("is_CSR_defined",ATy(qTy,PTy(bTy,qTy)),Var("csr",FTy 12)), + qVar"state"), + TP[Bop(And,bVar"v", + Call + ("check_CSR_access",bTy, + TP[Call("csrRW",FTy 2,Var("csr",FTy 12)), + Call("csrPR",FTy 2,Var("csr",FTy 12)), + Apply + (Call("curPrivilege",ATy(qTy,CTy"Privilege"),LU), + qVar"s"),Var("a",CTy"accessType")])),qVar"s"]))) +; +val dfn'CSRRW_def = Def + ("dfn'CSRRW",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("rs1",FTy 5), + LC("Write",CTy"accessType")]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"s")]),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'CSRRS_def = Def + ("dfn'CSRRS",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("rs1",FTy 5), + ITE(EQ(Var("rs1",FTy 5),LW(0,5)), + LC("Read",CTy"accessType"), + LC("Write",CTy"accessType"))]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + ITE(Mop(Not,EQ(Var("rs1",FTy 5),LW(0,5))), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Bop(BOr,Var("v",F64), + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s"))]), + qVar"s"),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'CSRRC_def = Def + ("dfn'CSRRC",TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("rs1",FTy 5), + ITE(EQ(Var("rs1",FTy 5),LW(0,5)), + LC("Read",CTy"accessType"), + LC("Write",CTy"accessType"))]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + ITE(Mop(Not,EQ(Var("rs1",FTy 5),LW(0,5))), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Bop(BAnd,Var("v",F64), + Mop(BNot, + Apply + (Call + ("GPR",ATy(qTy,F64), + Var("rs1",FTy 5)),qVar"s")))]), + qVar"s"),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'CSRRWI_def = Def + ("dfn'CSRRWI",TP[Var("rd",FTy 5),Var("zimm",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("zimm",FTy 5), + ITE(EQ(Var("zimm",FTy 5),LW(0,5)), + LC("Read",CTy"accessType"), + LC("Write",CTy"accessType"))]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + ITE(Mop(Not,EQ(Var("zimm",FTy 5),LW(0,5))), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Mop(Cast F64,Var("zimm",FTy 5))]), + qVar"s"),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'CSRRSI_def = Def + ("dfn'CSRRSI",TP[Var("rd",FTy 5),Var("zimm",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("zimm",FTy 5), + ITE(EQ(Var("zimm",FTy 5),LW(0,5)), + LC("Read",CTy"accessType"), + LC("Write",CTy"accessType"))]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + ITE(Mop(Not,EQ(Var("zimm",FTy 5),LW(0,5))), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Bop(BOr,Var("v",F64), + Mop(Cast F64,Var("zimm",FTy 5)))]), + qVar"s"),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'CSRRCI_def = Def + ("dfn'CSRRCI",TP[Var("rd",FTy 5),Var("zimm",FTy 5),Var("csr",FTy 12)], + Close + (qVar"state", + Let(TP[bVar"v",qVar"s"], + Apply + (Call + ("checkCSROp",ATy(qTy,PTy(bTy,qTy)), + TP[Var("csr",FTy 12),Var("zimm",FTy 5), + ITE(EQ(Var("zimm",FTy 5),LW(0,5)), + LC("Read",CTy"accessType"), + LC("Write",CTy"accessType"))]),qVar"state"), + ITE(bVar"v", + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("CSR",ATy(qTy,PTy(F64,qTy)),Var("csr",FTy 12)), + qVar"s"), + Apply + (Call + ("write'GPR",ATy(qTy,qTy), + TP[Var("v",F64),Var("rd",FTy 5)]), + ITE(Mop(Not,EQ(Var("zimm",FTy 5),LW(0,5))), + Apply + (Call + ("writeCSR",ATy(qTy,qTy), + TP[Var("csr",FTy 12), + Bop(BAnd,Var("v",F64), + Mop(BNot, + Mop(Cast F64,Var("zimm",FTy 5))))]), + qVar"s"),qVar"s"))), + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"s"))))) +; +val dfn'SFENCE_VM_def = Def + ("dfn'SFENCE_VM",Var("rs1",FTy 5), + Close + (qVar"state", + Apply + (Call + ("write'TLB",ATy(qTy,qTy), + Call + ("flushTLB",ATy(F4,OTy(CTy"TLBEntry")), + TP[Apply(Call("curASID",ATy(qTy,FTy 6),LU),qVar"state"), + ITE(EQ(Var("rs1",FTy 5),LW(0,5)),LO F64, + Mop(Some, + Apply + (Call("GPR",ATy(qTy,F64),Var("rs1",FTy 5)), + qVar"state"))), + Apply + (Const("TLB",ATy(qTy,ATy(F4,OTy(CTy"TLBEntry")))), + qVar"state")])),qVar"state"))) +; +val dfn'UnknownInstruction_def = Def + ("dfn'UnknownInstruction",qVar"state", + Apply + (Call + ("signalException",ATy(qTy,qTy), + LC("Illegal_Instr",CTy"ExceptionType")),qVar"state")) +; +val dfn'FETCH_MISALIGNED_def = Def + ("dfn'FETCH_MISALIGNED",Var("addr",F64), + Close + (qVar"state", + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Fetch_Misaligned",CTy"ExceptionType"),Var("addr",F64)]), + qVar"state"))) +; +val dfn'FETCH_FAULT_def = Def + ("dfn'FETCH_FAULT",Var("addr",F64), + Close + (qVar"state", + Apply + (Call + ("signalAddressException",ATy(qTy,qTy), + TP[LC("Fetch_Fault",CTy"ExceptionType"),Var("addr",F64)]), + qVar"state"))) +; +val Run_def = Def + ("Run",Var("v0",CTy"instruction"), + Close + (qVar"state", + CS(Var("v0",CTy"instruction"), + [(Const("UnknownInstruction",CTy"instruction"), + Apply(Const("dfn'UnknownInstruction",ATy(qTy,qTy)),qVar"state")), + (Call + ("FENCE",CTy"instruction", + Var("v170",PTy(FTy 5,PTy(FTy 5,PTy(F4,F4))))),qVar"state"), + (Call + ("FENCE_I",CTy"instruction", + Var("v171",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state"), + (Call("AMO",CTy"instruction",Var("v1",CTy"AMO")), + CS(Var("v1",CTy"AMO"), + [(Call + ("AMOADD_D",CTy"AMO", + Var("v2",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOADD_D",ATy(qTy,qTy), + Var("v2",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOADD_W",CTy"AMO", + Var("v3",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOADD_W",ATy(qTy,qTy), + Var("v3",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOAND_D",CTy"AMO", + Var("v4",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOAND_D",ATy(qTy,qTy), + Var("v4",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOAND_W",CTy"AMO", + Var("v5",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOAND_W",ATy(qTy,qTy), + Var("v5",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMAXU_D",CTy"AMO", + Var("v6",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMAXU_D",ATy(qTy,qTy), + Var("v6",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMAXU_W",CTy"AMO", + Var("v7",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMAXU_W",ATy(qTy,qTy), + Var("v7",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMAX_D",CTy"AMO", + Var("v8",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMAX_D",ATy(qTy,qTy), + Var("v8",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMAX_W",CTy"AMO", + Var("v9",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMAX_W",ATy(qTy,qTy), + Var("v9",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMINU_D",CTy"AMO", + Var("v10",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMINU_D",ATy(qTy,qTy), + Var("v10", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMINU_W",CTy"AMO", + Var("v11",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMINU_W",ATy(qTy,qTy), + Var("v11", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMIN_D",CTy"AMO", + Var("v12",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMIN_D",ATy(qTy,qTy), + Var("v12", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOMIN_W",CTy"AMO", + Var("v13",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOMIN_W",ATy(qTy,qTy), + Var("v13", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOOR_D",CTy"AMO", + Var("v14",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOOR_D",ATy(qTy,qTy), + Var("v14", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOOR_W",CTy"AMO", + Var("v15",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOOR_W",ATy(qTy,qTy), + Var("v15", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOSWAP_D",CTy"AMO", + Var("v16",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOSWAP_D",ATy(qTy,qTy), + Var("v16", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOSWAP_W",CTy"AMO", + Var("v17",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOSWAP_W",ATy(qTy,qTy), + Var("v17", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOXOR_D",CTy"AMO", + Var("v18",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOXOR_D",ATy(qTy,qTy), + Var("v18", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("AMOXOR_W",CTy"AMO", + Var("v19",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'AMOXOR_W",ATy(qTy,qTy), + Var("v19", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("LR_D",CTy"AMO", + Var("v20",PTy(F1,PTy(F1,PTy(FTy 5,FTy 5))))), + Apply + (Call + ("dfn'LR_D",ATy(qTy,qTy), + Var("v20",PTy(F1,PTy(F1,PTy(FTy 5,FTy 5))))), + qVar"state")), + (Call + ("LR_W",CTy"AMO", + Var("v21",PTy(F1,PTy(F1,PTy(FTy 5,FTy 5))))), + Apply + (Call + ("dfn'LR_W",ATy(qTy,qTy), + Var("v21",PTy(F1,PTy(F1,PTy(FTy 5,FTy 5))))), + qVar"state")), + (Call + ("SC_D",CTy"AMO", + Var("v22",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'SC_D",ATy(qTy,qTy), + Var("v22", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state")), + (Call + ("SC_W",CTy"AMO", + Var("v23",PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + Apply + (Call + ("dfn'SC_W",ATy(qTy,qTy), + Var("v23", + PTy(F1,PTy(F1,PTy(FTy 5,PTy(FTy 5,FTy 5)))))), + qVar"state"))])), + (Call("ArithI",CTy"instruction",Var("v24",CTy"ArithI")), + CS(Var("v24",CTy"ArithI"), + [(Call + ("ADDI",CTy"ArithI", + Var("v25",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'ADDI",ATy(qTy,qTy), + Var("v25",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("ADDIW",CTy"ArithI", + Var("v26",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'ADDIW",ATy(qTy,qTy), + Var("v26",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("ANDI",CTy"ArithI", + Var("v27",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'ANDI",ATy(qTy,qTy), + Var("v27",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call("AUIPC",CTy"ArithI",Var("v28",PTy(FTy 5,FTy 20))), + Apply + (Call + ("dfn'AUIPC",ATy(qTy,qTy), + Var("v28",PTy(FTy 5,FTy 20))),qVar"state")), + (Call("LUI",CTy"ArithI",Var("v29",PTy(FTy 5,FTy 20))), + Apply + (Call + ("dfn'LUI",ATy(qTy,qTy),Var("v29",PTy(FTy 5,FTy 20))), + qVar"state")), + (Call + ("ORI",CTy"ArithI", + Var("v30",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'ORI",ATy(qTy,qTy), + Var("v30",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("SLTI",CTy"ArithI", + Var("v31",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SLTI",ATy(qTy,qTy), + Var("v31",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("SLTIU",CTy"ArithI", + Var("v32",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SLTIU",ATy(qTy,qTy), + Var("v32",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("XORI",CTy"ArithI", + Var("v33",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'XORI",ATy(qTy,qTy), + Var("v33",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state"))])), + (Call("ArithR",CTy"instruction",Var("v34",CTy"ArithR")), + CS(Var("v34",CTy"ArithR"), + [(Call + ("ADD",CTy"ArithR", + Var("v35",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'ADD",ATy(qTy,qTy), + Var("v35",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("ADDW",CTy"ArithR", + Var("v36",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'ADDW",ATy(qTy,qTy), + Var("v36",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("AND",CTy"ArithR", + Var("v37",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'AND",ATy(qTy,qTy), + Var("v37",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("OR",CTy"ArithR",Var("v38",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'OR",ATy(qTy,qTy), + Var("v38",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLT",CTy"ArithR", + Var("v39",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLT",ATy(qTy,qTy), + Var("v39",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLTU",CTy"ArithR", + Var("v40",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLTU",ATy(qTy,qTy), + Var("v40",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SUB",CTy"ArithR", + Var("v41",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SUB",ATy(qTy,qTy), + Var("v41",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SUBW",CTy"ArithR", + Var("v42",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SUBW",ATy(qTy,qTy), + Var("v42",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("XOR",CTy"ArithR", + Var("v43",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'XOR",ATy(qTy,qTy), + Var("v43",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("Branch",CTy"instruction",Var("v44",CTy"Branch")), + CS(Var("v44",CTy"Branch"), + [(Call + ("BEQ",CTy"Branch", + Var("v45",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BEQ",ATy(qTy,qTy), + Var("v45",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("BGE",CTy"Branch", + Var("v46",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BGE",ATy(qTy,qTy), + Var("v46",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("BGEU",CTy"Branch", + Var("v47",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BGEU",ATy(qTy,qTy), + Var("v47",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("BLT",CTy"Branch", + Var("v48",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BLT",ATy(qTy,qTy), + Var("v48",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("BLTU",CTy"Branch", + Var("v49",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BLTU",ATy(qTy,qTy), + Var("v49",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call + ("BNE",CTy"Branch", + Var("v50",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'BNE",ATy(qTy,qTy), + Var("v50",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state")), + (Call("JAL",CTy"Branch",Var("v51",PTy(FTy 5,FTy 20))), + Apply + (Call + ("dfn'JAL",ATy(qTy,qTy),Var("v51",PTy(FTy 5,FTy 20))), + qVar"state")), + (Call + ("JALR",CTy"Branch", + Var("v52",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'JALR",ATy(qTy,qTy), + Var("v52",PTy(FTy 5,PTy(FTy 5,FTy 12)))),qVar"state"))])), + (Call("FArith",CTy"instruction",Var("v53",CTy"FArith")), + CS(Var("v53",CTy"FArith"), + [(Call + ("FADD_D",CTy"FArith", + Var("v54",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FADD_D",ATy(qTy,qTy), + Var("v54",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FADD_S",CTy"FArith", + Var("v55",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FADD_S",ATy(qTy,qTy), + Var("v55",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FDIV_D",CTy"FArith", + Var("v56",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FDIV_D",ATy(qTy,qTy), + Var("v56",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FDIV_S",CTy"FArith", + Var("v57",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FDIV_S",ATy(qTy,qTy), + Var("v57",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FEQ_D",CTy"FArith", + Var("v58",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FEQ_D",ATy(qTy,qTy), + Var("v58",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FEQ_S",CTy"FArith", + Var("v59",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FEQ_S",ATy(qTy,qTy), + Var("v59",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FLE_D",CTy"FArith", + Var("v60",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FLE_D",ATy(qTy,qTy), + Var("v60",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FLE_S",CTy"FArith", + Var("v61",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FLE_S",ATy(qTy,qTy), + Var("v61",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FLT_D",CTy"FArith", + Var("v62",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FLT_D",ATy(qTy,qTy), + Var("v62",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FLT_S",CTy"FArith", + Var("v63",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FLT_S",ATy(qTy,qTy), + Var("v63",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FMADD_D",CTy"FArith", + Var("v64", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FMADD_D",ATy(qTy,qTy), + Var("v64", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FMADD_S",CTy"FArith", + Var("v65", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FMADD_S",ATy(qTy,qTy), + Var("v65", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FMAX_D",CTy"FArith", + Var("v66",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FMAX_D",ATy(qTy,qTy), + Var("v66",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FMAX_S",CTy"FArith", + Var("v67",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FMAX_S",ATy(qTy,qTy), + Var("v67",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FMIN_D",CTy"FArith", + Var("v68",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FMIN_D",ATy(qTy,qTy), + Var("v68",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FMIN_S",CTy"FArith", + Var("v69",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FMIN_S",ATy(qTy,qTy), + Var("v69",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FMSUB_D",CTy"FArith", + Var("v70", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FMSUB_D",ATy(qTy,qTy), + Var("v70", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FMSUB_S",CTy"FArith", + Var("v71", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FMSUB_S",ATy(qTy,qTy), + Var("v71", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FMUL_D",CTy"FArith", + Var("v72",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FMUL_D",ATy(qTy,qTy), + Var("v72",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FMUL_S",CTy"FArith", + Var("v73",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FMUL_S",ATy(qTy,qTy), + Var("v73",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FNMADD_D",CTy"FArith", + Var("v74", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FNMADD_D",ATy(qTy,qTy), + Var("v74", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FNMADD_S",CTy"FArith", + Var("v75", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FNMADD_S",ATy(qTy,qTy), + Var("v75", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FNMSUB_D",CTy"FArith", + Var("v76", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FNMSUB_D",ATy(qTy,qTy), + Var("v76", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FNMSUB_S",CTy"FArith", + Var("v77", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + Apply + (Call + ("dfn'FNMSUB_S",ATy(qTy,qTy), + Var("v77", + PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3)))))), + qVar"state")), + (Call + ("FSQRT_D",CTy"FArith", + Var("v78",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FSQRT_D",ATy(qTy,qTy), + Var("v78",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FSQRT_S",CTy"FArith", + Var("v79",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FSQRT_S",ATy(qTy,qTy), + Var("v79",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FSUB_D",CTy"FArith", + Var("v80",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FSUB_D",ATy(qTy,qTy), + Var("v80",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state")), + (Call + ("FSUB_S",CTy"FArith", + Var("v81",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + Apply + (Call + ("dfn'FSUB_S",ATy(qTy,qTy), + Var("v81",PTy(FTy 5,PTy(FTy 5,PTy(FTy 5,FTy 3))))), + qVar"state"))])), + (Call("FConv",CTy"instruction",Var("v82",CTy"FConv")), + CS(Var("v82",CTy"FConv"), + [(Call("FCLASS_D",CTy"FConv",Var("v83",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FCLASS_D",ATy(qTy,qTy), + Var("v83",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("FCLASS_S",CTy"FConv",Var("v84",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FCLASS_S",ATy(qTy,qTy), + Var("v84",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("FCVT_D_L",CTy"FConv", + Var("v85",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_D_L",ATy(qTy,qTy), + Var("v85",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_D_LU",CTy"FConv", + Var("v86",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_D_LU",ATy(qTy,qTy), + Var("v86",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_D_S",CTy"FConv", + Var("v87",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_D_S",ATy(qTy,qTy), + Var("v87",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_D_W",CTy"FConv", + Var("v88",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_D_W",ATy(qTy,qTy), + Var("v88",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_D_WU",CTy"FConv", + Var("v89",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_D_WU",ATy(qTy,qTy), + Var("v89",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_LU_D",CTy"FConv", + Var("v90",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_LU_D",ATy(qTy,qTy), + Var("v90",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_LU_S",CTy"FConv", + Var("v91",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_LU_S",ATy(qTy,qTy), + Var("v91",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_L_D",CTy"FConv", + Var("v92",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_L_D",ATy(qTy,qTy), + Var("v92",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_L_S",CTy"FConv", + Var("v93",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_L_S",ATy(qTy,qTy), + Var("v93",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_S_D",CTy"FConv", + Var("v94",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_S_D",ATy(qTy,qTy), + Var("v94",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_S_L",CTy"FConv", + Var("v95",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_S_L",ATy(qTy,qTy), + Var("v95",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_S_LU",CTy"FConv", + Var("v96",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_S_LU",ATy(qTy,qTy), + Var("v96",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_S_W",CTy"FConv", + Var("v97",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_S_W",ATy(qTy,qTy), + Var("v97",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_S_WU",CTy"FConv", + Var("v98",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_S_WU",ATy(qTy,qTy), + Var("v98",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_WU_D",CTy"FConv", + Var("v99",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_WU_D",ATy(qTy,qTy), + Var("v99",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_WU_S",CTy"FConv", + Var("v100",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_WU_S",ATy(qTy,qTy), + Var("v100",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_W_D",CTy"FConv", + Var("v101",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_W_D",ATy(qTy,qTy), + Var("v101",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call + ("FCVT_W_S",CTy"FConv", + Var("v102",PTy(FTy 5,PTy(FTy 5,FTy 3)))), + Apply + (Call + ("dfn'FCVT_W_S",ATy(qTy,qTy), + Var("v102",PTy(FTy 5,PTy(FTy 5,FTy 3)))),qVar"state")), + (Call("FMV_D_X",CTy"FConv",Var("v103",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FMV_D_X",ATy(qTy,qTy), + Var("v103",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("FMV_S_X",CTy"FConv",Var("v104",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FMV_S_X",ATy(qTy,qTy), + Var("v104",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("FMV_X_D",CTy"FConv",Var("v105",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FMV_X_D",ATy(qTy,qTy), + Var("v105",PTy(FTy 5,FTy 5))),qVar"state")), + (Call("FMV_X_S",CTy"FConv",Var("v106",PTy(FTy 5,FTy 5))), + Apply + (Call + ("dfn'FMV_X_S",ATy(qTy,qTy), + Var("v106",PTy(FTy 5,FTy 5))),qVar"state")), + (Call + ("FSGNJN_D",CTy"FConv", + Var("v107",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJN_D",ATy(qTy,qTy), + Var("v107",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FSGNJN_S",CTy"FConv", + Var("v108",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJN_S",ATy(qTy,qTy), + Var("v108",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FSGNJX_D",CTy"FConv", + Var("v109",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJX_D",ATy(qTy,qTy), + Var("v109",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FSGNJX_S",CTy"FConv", + Var("v110",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJX_S",ATy(qTy,qTy), + Var("v110",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FSGNJ_D",CTy"FConv", + Var("v111",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJ_D",ATy(qTy,qTy), + Var("v111",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("FSGNJ_S",CTy"FConv", + Var("v112",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'FSGNJ_S",ATy(qTy,qTy), + Var("v112",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("FPLoad",CTy"instruction",Var("v113",CTy"FPLoad")), + CS(Var("v113",CTy"FPLoad"), + [(Call + ("FLD",CTy"FPLoad", + Var("v114",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'FLD",ATy(qTy,qTy), + Var("v114",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("FLW",CTy"FPLoad", + Var("v115",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'FLW",ATy(qTy,qTy), + Var("v115",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state"))])), + (Call("FPStore",CTy"instruction",Var("v116",CTy"FPStore")), + CS(Var("v116",CTy"FPStore"), + [(Call + ("FSD",CTy"FPStore", + Var("v117",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'FSD",ATy(qTy,qTy), + Var("v117",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("FSW",CTy"FPStore", + Var("v118",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'FSW",ATy(qTy,qTy), + Var("v118",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state"))])), + (Call("Internal",CTy"instruction",Var("v119",CTy"Internal")), + CS(Var("v119",CTy"Internal"), + [(Call("FETCH_FAULT",CTy"Internal",Var("v120",F64)), + Apply + (Call("dfn'FETCH_FAULT",ATy(qTy,qTy),Var("v120",F64)), + qVar"state")), + (Call("FETCH_MISALIGNED",CTy"Internal",Var("v121",F64)), + Apply + (Call + ("dfn'FETCH_MISALIGNED",ATy(qTy,qTy),Var("v121",F64)), + qVar"state"))])), + (Call("Load",CTy"instruction",Var("v122",CTy"Load")), + CS(Var("v122",CTy"Load"), + [(Call + ("LB",CTy"Load",Var("v123",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LB",ATy(qTy,qTy), + Var("v123",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LBU",CTy"Load", + Var("v124",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LBU",ATy(qTy,qTy), + Var("v124",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LD",CTy"Load",Var("v125",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LD",ATy(qTy,qTy), + Var("v125",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LH",CTy"Load",Var("v126",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LH",ATy(qTy,qTy), + Var("v126",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LHU",CTy"Load", + Var("v127",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LHU",ATy(qTy,qTy), + Var("v127",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LW",CTy"Load",Var("v128",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LW",ATy(qTy,qTy), + Var("v128",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("LWU",CTy"Load", + Var("v129",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'LWU",ATy(qTy,qTy), + Var("v129",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state"))])), + (Call("MulDiv",CTy"instruction",Var("v130",CTy"MulDiv")), + CS(Var("v130",CTy"MulDiv"), + [(Call + ("DIV",CTy"MulDiv", + Var("v131",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DIV",ATy(qTy,qTy), + Var("v131",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DIVU",CTy"MulDiv", + Var("v132",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DIVU",ATy(qTy,qTy), + Var("v132",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DIVUW",CTy"MulDiv", + Var("v133",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DIVUW",ATy(qTy,qTy), + Var("v133",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("DIVW",CTy"MulDiv", + Var("v134",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'DIVW",ATy(qTy,qTy), + Var("v134",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MUL",CTy"MulDiv", + Var("v135",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MUL",ATy(qTy,qTy), + Var("v135",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MULH",CTy"MulDiv", + Var("v136",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MULH",ATy(qTy,qTy), + Var("v136",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MULHSU",CTy"MulDiv", + Var("v137",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MULHSU",ATy(qTy,qTy), + Var("v137",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MULHU",CTy"MulDiv", + Var("v138",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MULHU",ATy(qTy,qTy), + Var("v138",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("MULW",CTy"MulDiv", + Var("v139",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'MULW",ATy(qTy,qTy), + Var("v139",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("REM",CTy"MulDiv", + Var("v140",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'REM",ATy(qTy,qTy), + Var("v140",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("REMU",CTy"MulDiv", + Var("v141",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'REMU",ATy(qTy,qTy), + Var("v141",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("REMUW",CTy"MulDiv", + Var("v142",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'REMUW",ATy(qTy,qTy), + Var("v142",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("REMW",CTy"MulDiv", + Var("v143",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'REMW",ATy(qTy,qTy), + Var("v143",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("Shift",CTy"instruction",Var("v144",CTy"Shift")), + CS(Var("v144",CTy"Shift"), + [(Call + ("SLL",CTy"Shift", + Var("v145",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLL",ATy(qTy,qTy), + Var("v145",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLLI",CTy"Shift", + Var("v146",PTy(FTy 5,PTy(FTy 5,FTy 6)))), + Apply + (Call + ("dfn'SLLI",ATy(qTy,qTy), + Var("v146",PTy(FTy 5,PTy(FTy 5,FTy 6)))),qVar"state")), + (Call + ("SLLIW",CTy"Shift", + Var("v147",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLLIW",ATy(qTy,qTy), + Var("v147",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SLLW",CTy"Shift", + Var("v148",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SLLW",ATy(qTy,qTy), + Var("v148",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRA",CTy"Shift", + Var("v149",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRA",ATy(qTy,qTy), + Var("v149",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRAI",CTy"Shift", + Var("v150",PTy(FTy 5,PTy(FTy 5,FTy 6)))), + Apply + (Call + ("dfn'SRAI",ATy(qTy,qTy), + Var("v150",PTy(FTy 5,PTy(FTy 5,FTy 6)))),qVar"state")), + (Call + ("SRAIW",CTy"Shift", + Var("v151",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRAIW",ATy(qTy,qTy), + Var("v151",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRAW",CTy"Shift", + Var("v152",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRAW",ATy(qTy,qTy), + Var("v152",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRL",CTy"Shift", + Var("v153",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRL",ATy(qTy,qTy), + Var("v153",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRLI",CTy"Shift", + Var("v154",PTy(FTy 5,PTy(FTy 5,FTy 6)))), + Apply + (Call + ("dfn'SRLI",ATy(qTy,qTy), + Var("v154",PTy(FTy 5,PTy(FTy 5,FTy 6)))),qVar"state")), + (Call + ("SRLIW",CTy"Shift", + Var("v155",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRLIW",ATy(qTy,qTy), + Var("v155",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state")), + (Call + ("SRLW",CTy"Shift", + Var("v156",PTy(FTy 5,PTy(FTy 5,FTy 5)))), + Apply + (Call + ("dfn'SRLW",ATy(qTy,qTy), + Var("v156",PTy(FTy 5,PTy(FTy 5,FTy 5)))),qVar"state"))])), + (Call("Store",CTy"instruction",Var("v157",CTy"Store")), + CS(Var("v157",CTy"Store"), + [(Call + ("SB",CTy"Store", + Var("v158",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SB",ATy(qTy,qTy), + Var("v158",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("SD",CTy"Store", + Var("v159",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SD",ATy(qTy,qTy), + Var("v159",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("SH",CTy"Store", + Var("v160",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SH",ATy(qTy,qTy), + Var("v160",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("SW",CTy"Store", + Var("v161",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'SW",ATy(qTy,qTy), + Var("v161",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state"))])), + (Call("System",CTy"instruction",Var("v162",CTy"System")), + CS(Var("v162",CTy"System"), + [(Const("EBREAK",CTy"System"), + Apply(Const("dfn'EBREAK",ATy(qTy,qTy)),qVar"state")), + (Const("ECALL",CTy"System"), + Apply(Const("dfn'ECALL",ATy(qTy,qTy)),qVar"state")), + (Const("ERET",CTy"System"), + Apply(Const("dfn'ERET",ATy(qTy,qTy)),qVar"state")), + (Const("MRTS",CTy"System"), + Apply(Const("dfn'MRTS",ATy(qTy,qTy)),qVar"state")), + (Const("WFI",CTy"System"),qVar"state"), + (Call + ("CSRRC",CTy"System", + Var("v163",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRC",ATy(qTy,qTy), + Var("v163",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("CSRRCI",CTy"System", + Var("v164",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRCI",ATy(qTy,qTy), + Var("v164",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("CSRRS",CTy"System", + Var("v165",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRS",ATy(qTy,qTy), + Var("v165",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("CSRRSI",CTy"System", + Var("v166",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRSI",ATy(qTy,qTy), + Var("v166",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("CSRRW",CTy"System", + Var("v167",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRW",ATy(qTy,qTy), + Var("v167",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call + ("CSRRWI",CTy"System", + Var("v168",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + Apply + (Call + ("dfn'CSRRWI",ATy(qTy,qTy), + Var("v168",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + qVar"state")), + (Call("SFENCE_VM",CTy"System",Var("v169",FTy 5)), + Apply + (Call("dfn'SFENCE_VM",ATy(qTy,qTy),Var("v169",FTy 5)), + qVar"state"))]))]))) +; +val Fetch_def = Def + ("Fetch",AVar uTy, + Close + (qVar"state", + Let(Var("v",F64),Apply(Const("PC",ATy(qTy,F64)),qVar"state"), + ITE(Bop(Bit,Var("v",F64),LN 0), + TP[Call + ("F_Error",CTy"FetchResult", + Call + ("Internal",CTy"instruction", + Call("FETCH_MISALIGNED",CTy"Internal",Var("v",F64)))), + qVar"state"], + Let(TP[Var("v0",OTy F64),qVar"s"], + Apply + (Call + ("translateAddr",ATy(qTy,PTy(OTy F64,qTy)), + TP[Var("v",F64),LC("Instruction",CTy"fetchType"), + LC("Read",CTy"accessType")]),qVar"state"), + CS(Var("v0",OTy F64), + [(Mop(Some,Var("pPC",F64)), + Let(TP[Var("v0",CTy"rawInstType"),qVar"s"], + Apply + (Call + ("rawReadInst", + ATy(qTy,PTy(CTy"rawInstType",qTy)), + Var("pPC",F64)),qVar"s"), + TP[Call + ("F_Result",CTy"FetchResult", + Var("v0",CTy"rawInstType")), + Let(TP[Var("v1",CTy"StateDelta"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta",ATy(qTy,qTy), + Rupd + ("exc_taken", + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s"),LF])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy,CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v1",CTy"StateDelta"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy,qTy), + Rupd + ("fetch_exc", + TP[Var("v1", + CTy"StateDelta"), + LF])),qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy,CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v1",CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy,qTy), + Rupd + ("pc", + TP[Var("v1", + CTy"StateDelta"), + Var("v",F64)])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy,qTy), + Rupd + ("rinstr", + TP[Var("v1", + CTy"StateDelta"), + Var("v0", + CTy"rawInstType")])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v", + CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy,qTy), + Rupd + ("addr", + TP[Var("v", + CTy"StateDelta"), + LO F64])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"), + qVar"s0"]), + Let(TP[Var("v", + CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy, + qTy), + Rupd + ("data1", + TP[Var("v", + CTy"StateDelta"), + LO F64])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"), + qVar"s0"]), + Let(TP[Var("v", + CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy, + qTy), + Rupd + ("data2", + TP[Var("v", + CTy"StateDelta"), + LO F64])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"), + qVar"s0"]), + Let(TP[Var("v", + CTy"StateDelta"), + qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'Delta", + ATy(qTy, + qTy), + Rupd + ("fp_data", + TP[Var("v", + CTy"StateDelta"), + LO F64])), + qVar"s"), + TP[Apply + (Const + ("Delta", + ATy(qTy, + CTy"StateDelta")), + qVar"s0"), + qVar"s0"]), + Apply + (Call + ("write'Delta", + ATy(qTy, + qTy), + Rupd + ("st_width", + TP[Var("v", + CTy"StateDelta"), + LO F32])), + qVar"s")))))))))])), + (LO F64, + TP[Call + ("F_Error",CTy"FetchResult", + Call + ("Internal",CTy"instruction", + Call + ("FETCH_FAULT",CTy"Internal", + Var("v",F64)))),qVar"s"])])))))) +; +val asImm12_def = Def + ("asImm12", + TP[Var("imm12",F1),Var("imm11",F1),Var("immhi",FTy 6),Var("immlo",F4)], + CC[Var("imm12",F1),Var("imm11",F1),Var("immhi",FTy 6),Var("immlo",F4)]) +; +val asImm20_def = Def + ("asImm20", + TP[Var("imm20",F1),Var("immhi",F8),Var("imm11",F1),Var("immlo",FTy 10)], + CC[Var("imm20",F1),Var("immhi",F8),Var("imm11",F1),Var("immlo",FTy 10)]) +; +val asSImm12_def = Def + ("asSImm12",TP[Var("immhi",FTy 7),Var("immlo",FTy 5)], + CC[Var("immhi",FTy 7),Var("immlo",FTy 5)]) +; +val Decode_def = Def + ("Decode",Var("w",F32), + Let(TP[bVar"b'31",bVar"b'30",bVar"b'29",bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25",bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20",bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12", + bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6", + bVar"b'5",bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"], + BL(32,Var("w",F32)), + ITB([(bVar"b'6", + ITE(Bop(And,bVar"b'1",bVar"b'0"), + ITB([(Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLT",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BGE",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BLTU",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Branch",CTy"instruction", + Call + ("BGEU",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asImm12",FTy 12, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast(FTy 6), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25"]), + Mop(Cast F4, + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2")))))), + Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3",bVar"b'2"))), + Call + ("Branch",CTy"instruction", + Call + ("JAL",CTy"Branch", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Call + ("asImm20",FTy 20, + TP[Mop(Cast F1,LL[bVar"b'31"]), + Mop(Cast F8, + LL[bVar"b'19",bVar"b'18", + bVar"b'17",bVar"b'16", + bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12"]), + Mop(Cast F1,LL[bVar"b'20"]), + Mop(Cast(FTy 10), + LL[bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27", + bVar"b'26",bVar"b'25", + bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21"])])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2")))))), + Call + ("FArith",CTy"instruction", + Call + ("FMADD_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2"))))), + Call + ("FArith",CTy"instruction", + Call + ("FMSUB_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Mop(Not,bVar"b'2")))))), + Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3",bVar"b'2"))))), + Call + ("FArith",CTy"instruction", + Call + ("FNMADD_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FADD_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FSUB_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMUL_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FDIV_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FSQRT_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMIN_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMAX_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FEQ_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FLT_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FLE_S",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FMV_X_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCLASS_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_W",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_WU",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FMV_S_X",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2")))))), + Call + ("FArith",CTy"instruction", + Call + ("FMADD_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2"))))), + Call + ("FArith",CTy"instruction", + Call + ("FMSUB_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3", + Mop(Not,bVar"b'2")))))), + Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3",bVar"b'2"))))), + Call + ("FArith",CTy"instruction", + Call + ("FNMADD_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 5), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FADD_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FSUB_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMUL_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FDIV_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FSQRT_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMIN_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FMAX_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FEQ_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FLT_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FArith",CTy"instruction", + Call + ("FLE_D",CTy"FArith", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCLASS_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_W",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_WU",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_L",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_LU",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_L",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_LU",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FMV_X_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FMV_D_X",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_D",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))), + Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_S",CTy"FConv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 3), + LL[bVar"b'14",bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRW",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRS",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRC",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRWI",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRSI",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("System",CTy"instruction", + Call + ("CSRRCI",CTy"System", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Const("ECALL",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Const("EBREAK",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Const("ERET",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + bVar"b'22", + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Const("MRTS",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + bVar"b'21", + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'19"), + Bop(And, + Mop(Not, + bVar"b'18"), + Bop(And, + Mop(Not, + bVar"b'17"), + Bop(And, + Mop(Not, + bVar"b'16"), + Bop(And, + Mop(Not, + bVar"b'15"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Const("WFI",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And, + Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'24"), + Bop(And, + Mop(Not, + bVar"b'23"), + Bop(And, + Mop(Not, + bVar"b'22"), + Bop(And, + Mop(Not, + bVar"b'21"), + Bop(And, + bVar"b'20", + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + Mop(Not, + bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + Mop(Not, + bVar"b'11"), + Bop(And, + Mop(Not, + bVar"b'10"), + Bop(And, + Mop(Not, + bVar"b'9"), + Bop(And, + Mop(Not, + bVar"b'8"), + Bop(And, + Mop(Not, + bVar"b'7"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))))))))))))), + Call + ("System",CTy"instruction", + Call + ("SFENCE_VM",CTy"System", + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]))))], + Const("UnknownInstruction",CTy"instruction")), + Const("UnknownInstruction",CTy"instruction"))), + (Bop(And,bVar"b'1",bVar"b'0"), + ITB([(Bop(And,bVar"b'5", + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"),bVar"b'2"))), + Call + ("ArithI",CTy"instruction", + Call + ("LUI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 20), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"),bVar"b'2"))), + Call + ("ArithI",CTy"instruction", + Call + ("AUIPC",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 20), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20", + bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15",bVar"b'14", + bVar"b'13",bVar"b'12"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLLI",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 6), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRLI",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 6), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2"))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRAI",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 6), + LL[bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,bVar"b'4", + Bop(And,bVar"b'3", + Mop(Not,bVar"b'2"))))))), + Call + ("ArithI",CTy"instruction", + Call + ("ADDIW",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLLIW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRLIW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRAIW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("ADDW",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("ArithR",CTy"instruction", + Call + ("SUBW",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SLLW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRLW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,Mop(Not,bVar"b'25"), + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("Shift",CTy"instruction", + Call + ("SRAW",CTy"Shift", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("MUL",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("MULH",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("MULHSU",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("MULHU",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("DIV",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("DIVU",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("REM",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("REMU",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And, + Mop(Not,bVar"b'14"), + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("MULW",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("DIVW",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And, + Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("DIVUW",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("REMW",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'26"), + Bop(And,bVar"b'25", + Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + bVar"b'4", + Bop(And, + bVar"b'3", + Mop(Not, + bVar"b'2")))))))))))))), + Call + ("MulDiv",CTy"instruction", + Call + ("REMUW",CTy"MulDiv", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'14", + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3",bVar"b'2")))))), + Call + ("FENCE",CTy"instruction", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast F4, + LL[bVar"b'27",bVar"b'26",bVar"b'25", + bVar"b'24"]), + Mop(Cast F4, + LL[bVar"b'23",bVar"b'22",bVar"b'21", + bVar"b'20"])])), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,bVar"b'3",bVar"b'2")))))), + Call + ("FENCE_I",CTy"instruction", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])])), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2")))))), + Call + ("FPLoad",CTy"instruction", + Call + ("FLW",CTy"FPLoad", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2")))))), + Call + ("FPLoad",CTy"instruction", + Call + ("FLD",CTy"FPLoad", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 12), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25",bVar"b'24",bVar"b'23", + bVar"b'22",bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2")))))), + Call + ("FPStore",CTy"instruction", + Call + ("FSW",CTy"FPStore", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + bVar"b'2")))))), + Call + ("FPStore",CTy"instruction", + Call + ("FSD",CTy"FPStore", + TP[Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"]), + Call + ("asSImm12",FTy 12, + TP[Mop(Cast(FTy 7), + LL[bVar"b'31",bVar"b'30",bVar"b'29", + bVar"b'28",bVar"b'27",bVar"b'26", + bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"])])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And, + Mop(Not,bVar"b'22"), + Bop(And, + Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + bVar"b'13", + Bop(And, + Mop(Not, + bVar"b'12"), + Bop(And, + bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2")))))))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("LR_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'24"), + Bop(And,Mop(Not,bVar"b'23"), + Bop(And, + Mop(Not,bVar"b'22"), + Bop(And, + Mop(Not,bVar"b'21"), + Bop(And, + Mop(Not, + bVar"b'20"), + Bop(And, + Mop(Not, + bVar"b'14"), + Bop(And, + bVar"b'13", + Bop(And, + bVar"b'12", + Bop(And, + bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2")))))))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("LR_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("SC_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,bVar"b'28", + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("SC_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOADD_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOAND_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOOR_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And, + Mop(Not,bVar"b'12"), + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_W",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,bVar"b'27", + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOADD_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOAND_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,Mop(Not,bVar"b'31"), + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOOR_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,Mop(Not,bVar"b'30"), + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,Mop(Not,bVar"b'29"), + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])]))), + (Bop(And,bVar"b'31", + Bop(And,bVar"b'30", + Bop(And,bVar"b'29", + Bop(And,Mop(Not,bVar"b'28"), + Bop(And,Mop(Not,bVar"b'27"), + Bop(And,Mop(Not,bVar"b'14"), + Bop(And,bVar"b'13", + Bop(And,bVar"b'12", + Bop(And,bVar"b'5", + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + bVar"b'3", + bVar"b'2"))))))))))), + Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_D",CTy"AMO", + TP[Mop(Cast F1,LL[bVar"b'26"]), + Mop(Cast F1,LL[bVar"b'25"]), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 5), + LL[bVar"b'19",bVar"b'18",bVar"b'17", + bVar"b'16",bVar"b'15"]), + Mop(Cast(FTy 5), + LL[bVar"b'24",bVar"b'23",bVar"b'22", + bVar"b'21",bVar"b'20"])])))], + Const("UnknownInstruction",CTy"instruction")))], + Const("UnknownInstruction",CTy"instruction")))) +; +val imm_def = Def + ("imm",Var("i",BTy"N"),CC[LS"0x",Mop(Cast sTy,Var("i",BTy"N"))]) +; +val instr_def = Def + ("instr",sVar"o",Mop(PadRight,TP[LSC #" ",LN 12,sVar"o"])) +; +val amotype_def = Def + ("amotype",TP[Var("aq",F1),Var("rl",F1)], + CS(TP[Var("aq",F1),Var("rl",F1)], + [(TP[LW(0,1),LW(0,1)],LS""),(TP[LW(1,1),LW(0,1)],LS".aq"), + (TP[LW(0,1),LW(1,1)],LS".rl"),(TP[LW(1,1),LW(1,1)],LS".sc")])) +; +val pRtype_def = Def + ("pRtype",TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("reg",sTy,Var("rs2",FTy 5))]) +; +val pARtype_def = Def + ("pARtype", + TP[sVar"o",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)], + Call + ("pRtype",sTy, + TP[CC[sVar"o",Call("amotype",sTy,TP[Var("aq",F1),Var("rl",F1)])], + Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])) +; +val pLRtype_def = Def + ("pLRtype", + TP[sVar"o",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5),Var("rs1",FTy 5)], + CC[Call + ("instr",sTy, + CC[sVar"o",Call("amotype",sTy,TP[Var("aq",F1),Var("rl",F1)])]), + LS" ",Call("reg",sTy,Var("rd",FTy 5)),LS", ", + Call("reg",sTy,Var("rs1",FTy 5))]) +; +val pItype_def = Def + ("pItype",TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("imm",sTy,Var("i",BTy"N"))]) +; +val pCSRtype_def = Def + ("pCSRtype", + TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("csrName",sTy,Var("csr",FTy 12))]) +; +val pCSRItype_def = Def + ("pCSRItype", + TP[sVar"o",Var("rd",FTy 5),Var("i",BTy"N"),Var("csr",FTy 12)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("imm",sTy,Var("i",BTy"N")),LS", ", + Call("csrName",sTy,Var("csr",FTy 12))]) +; +val pStype_def = Def + ("pStype",TP[sVar"o",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rs2",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("imm",sTy,Var("i",BTy"N"))]) +; +val pSBtype_def = Def + ("pSBtype", + TP[sVar"o",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rs1",FTy 5)), + LS", ",Call("reg",sTy,Var("rs2",FTy 5)),LS", ", + Call("imm",sTy,Bop(Lsl,Var("i",BTy"N"),LN 1))]) +; +val pUtype_def = Def + ("pUtype",TP[sVar"o",Var("rd",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("imm",sTy,Var("i",BTy"N"))]) +; +val pUJtype_def = Def + ("pUJtype",TP[sVar"o",Var("rd",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("imm",sTy,Bop(Lsl,Var("i",BTy"N"),LN 1))]) +; +val pN0type_def = Def ("pN0type",sVar"o",Call("instr",sTy,sVar"o")) +; +val pN1type_def = Def + ("pN1type",TP[sVar"o",Var("r",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("r",FTy 5))]) +; +val pFRtype_def = Def + ("pFRtype", + TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rd",FTy 5)), + LS", ",Call("fpreg",sTy,Var("rs1",FTy 5)),LS", ", + Call("fpreg",sTy,Var("rs2",FTy 5))]) +; +val pFR1type_def = Def + ("pFR1type",TP[sVar"o",Var("rd",FTy 5),Var("rs",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rd",FTy 5)), + LS", ",Call("fpreg",sTy,Var("rs",FTy 5))]) +; +val pFR3type_def = Def + ("pFR3type", + TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rd",FTy 5)), + LS", ",Call("fpreg",sTy,Var("rs1",FTy 5)),LS", ", + Call("fpreg",sTy,Var("rs2",FTy 5)),LS", ", + Call("fpreg",sTy,Var("rs3",FTy 5))]) +; +val pFItype_def = Def + ("pFItype",TP[sVar"o",Var("rd",FTy 5),Var("rs1",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rd",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("imm",sTy,Var("i",BTy"N"))]) +; +val pFStype_def = Def + ("pFStype", + TP[sVar"o",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("i",BTy"N")], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rs2",FTy 5)), + LS", ",Call("reg",sTy,Var("rs1",FTy 5)),LS", ", + Call("imm",sTy,Var("i",BTy"N"))]) +; +val pCFItype_def = Def + ("pCFItype",TP[sVar"o",Var("rd",FTy 5),Var("rs",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("fpreg",sTy,Var("rd",FTy 5)), + LS", ",Call("reg",sTy,Var("rs",FTy 5))]) +; +val pCIFtype_def = Def + ("pCIFtype",TP[sVar"o",Var("rd",FTy 5),Var("rs",FTy 5)], + CC[Call("instr",sTy,sVar"o"),LS" ",Call("reg",sTy,Var("rd",FTy 5)), + LS", ",Call("fpreg",sTy,Var("rs",FTy 5))]) +; +val instructionToString_def = Def + ("instructionToString",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BEQ",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BNE",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BLT",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BLT",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BGE",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BGE",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BLTU",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BLTU",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BGEU",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pSBtype",sTy, + TP[LS"BGEU",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"JALR",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call("JAL",CTy"Branch",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call("pUJtype",sTy,TP[LS"JAL",Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call("LUI",CTy"ArithI",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call("pUtype",sTy,TP[LS"LUI",Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call("AUIPC",CTy"ArithI",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call("pUtype",sTy,TP[LS"AUIPC",Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"ADDI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("pItype",sTy, + TP[LS"SLLI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"SLTI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"SLTIU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"XORI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("pItype",sTy, + TP[LS"SRLI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("pItype",sTy, + TP[LS"SRAI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"ORI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"ANDI",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"ADD",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SUB",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SLL",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SLT",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SLTU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"XOR",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SRL",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SRA",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"OR",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"AND",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDIW",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"ADDIW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("pItype",sTy, + TP[LS"SLLIW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("pItype",sTy, + TP[LS"SRLIW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("pItype",sTy, + TP[LS"SRAIW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADDW",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"ADDW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUBW",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SUBW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SLLW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SRLW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"SRAW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MUL",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"MUL",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULH",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"MULH",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULHSU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"MULHSU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULHU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"MULHU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIV",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"DIV",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"DIVU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REM",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"REM",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"REMU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"MULW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"DIVW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVUW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"DIVUW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"REMW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMUW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pRtype",sTy, + TP[LS"REMUW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LB",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LH",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LD",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LBU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LHU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pItype",sTy, + TP[LS"LWU",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pStype",sTy, + TP[LS"SB",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pStype",sTy, + TP[LS"SH",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pStype",sTy, + TP[LS"SW",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pStype",sTy, + TP[LS"SD",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("FENCE",CTy"instruction", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("pred",F4), + Var("succ",F4)]),Call("pN0type",sTy,LS"FENCE")), + (Call + ("FENCE_I",CTy"instruction", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)]), + Call("pN0type",sTy,LS"FENCE.I")), + (Call + ("FArith",CTy"instruction", + Call + ("FADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FADD.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FSUB.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMUL_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FMUL.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FDIV_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FDIV.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSQRT_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR1type",sTy,TP[LS"FSQRT.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMIN_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FMIN.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMAX_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FMAX.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FEQ_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FEQ.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLT_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FLT.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLE_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FLE.S",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FMADD.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FMSUB.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FNMADD.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FNMSUB.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FADD.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FSUB.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMUL_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FMUL.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FDIV_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("pFRtype",sTy, + TP[LS"FDIV.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSQRT_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR1type",sTy,TP[LS"FSQRT.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMIN_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FMIN.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMAX_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FMAX.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FEQ_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FEQ.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLT_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FLT.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLE_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FLE.D",Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FMADD.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FMSUB.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FNMADD.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("pFR3type",sTy, + TP[LS"FNMSUB.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJ.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJN.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJX.S",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy,TP[LS"FCVT.W.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy, + TP[LS"FCVT.WU.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_X_S",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCIFtype",sTy,TP[LS"FMV.X.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FCLASS_S",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCIFtype",sTy,TP[LS"FCLASS.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_W",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.S.W",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_WU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy, + TP[LS"FCVT.S.WU",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_S_X",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCFItype",sTy,TP[LS"FMV.S.X",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJ.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJN.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pFRtype",sTy, + TP[LS"FSGNJX.D",Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy,TP[LS"FCVT.W.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy, + TP[LS"FCVT.WU.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FCLASS_D",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCIFtype",sTy,TP[LS"FCLASS.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_W",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.D.W",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_WU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy, + TP[LS"FCVT.D.WU",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy,TP[LS"FCVT.L.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy, + TP[LS"FCVT.LU.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_L",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.S.L",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_LU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy, + TP[LS"FCVT.S.LU",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy,TP[LS"FCVT.L.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCIFtype",sTy, + TP[LS"FCVT.LU.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_X_D",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCIFtype",sTy,TP[LS"FMV.X.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_L",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.D.L",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_LU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy, + TP[LS"FCVT.D.LU",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_D_X",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("pCFItype",sTy,TP[LS"FMV.D.X",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.D.S",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("pCFItype",sTy,TP[LS"FCVT.S.D",Var("rd",FTy 5),Var("rs",FTy 5)])), + (Call + ("FPLoad",CTy"instruction", + Call + ("FLW",CTy"FPLoad", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pFItype",sTy, + TP[LS"FLW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPLoad",CTy"instruction", + Call + ("FLD",CTy"FPLoad", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("pFItype",sTy, + TP[LS"FLD",Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPStore",CTy"instruction", + Call + ("FSW",CTy"FPStore", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pFStype",sTy, + TP[LS"FSW",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPStore",CTy"instruction", + Call + ("FSD",CTy"FPStore", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("pFStype",sTy, + TP[LS"FSD",Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("AMO",CTy"instruction", + Call + ("LR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + Call + ("pLRtype",sTy, + TP[LS"LR.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("LR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + Call + ("pLRtype",sTy, + TP[LS"LR.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("SC_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"SC.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("SC_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"SC.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOSWAP.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOADD_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOADD.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOXOR.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOAND_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOAND.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOOR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOOR.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMIN.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMAX.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMINU.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMAXU.W",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOSWAP.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOADD_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOADD.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOXOR.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOAND_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOAND.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOOR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOOR.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMIN.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMAX.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMINU.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("pARtype",sTy, + TP[LS"AMOMAXU.D",Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + (Call("System",CTy"instruction",Const("ECALL",CTy"System")), + Call("pN0type",sTy,LS"ECALL")), + (Call("System",CTy"instruction",Const("EBREAK",CTy"System")), + Call("pN0type",sTy,LS"EBREAK")), + (Call("System",CTy"instruction",Const("ERET",CTy"System")), + Call("pN0type",sTy,LS"ERET")), + (Call("System",CTy"instruction",Const("MRTS",CTy"System")), + Call("pN0type",sTy,LS"MRTS")), + (Call("System",CTy"instruction",Const("WFI",CTy"System")), + Call("pN0type",sTy,LS"WFI")), + (Call + ("System",CTy"instruction", + Call + ("CSRRW",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRtype",sTy, + TP[LS"CSRRW",Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRS",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRtype",sTy, + TP[LS"CSRRS",Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRC",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRtype",sTy, + TP[LS"CSRRC",Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRWI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRItype",sTy, + TP[LS"CSRRWI",Var("rd",FTy 5),Var("imm",FTy 5), + Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRSI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRItype",sTy, + TP[LS"CSRRSI",Var("rd",FTy 5),Var("imm",FTy 5), + Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRCI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("pCSRItype",sTy, + TP[LS"CSRRCI",Var("rd",FTy 5),Var("imm",FTy 5), + Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call("SFENCE_VM",CTy"System",Var("rs1",FTy 5))), + Call("pN1type",sTy,TP[LS"SFENCE.VM",Var("rs1",FTy 5)])), + (Const("UnknownInstruction",CTy"instruction"), + Call("pN0type",sTy,LS"UNKNOWN")), + (Call + ("Internal",CTy"instruction", + Call("FETCH_MISALIGNED",CTy"Internal",AVar F64)), + Call("pN0type",sTy,LS"FETCH_MISALIGNED")), + (Call + ("Internal",CTy"instruction", + Call("FETCH_FAULT",CTy"Internal",AVar F64)), + Call("pN0type",sTy,LS"FETCH_FAULT"))])) +; +val Rtype_def = Def + ("Rtype", + TP[Var("o",FTy 7),Var("f3",FTy 3),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("f7",FTy 7)], + CC[Var("f7",FTy 7),Var("rs2",FTy 5),Var("rs1",FTy 5),Var("f3",FTy 3), + Var("rd",FTy 5),Var("o",FTy 7)]) +; +val R4type_def = Def + ("R4type", + TP[Var("o",FTy 7),Var("f3",FTy 3),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("rs3",FTy 5),Var("f2",FTy 2)], + CC[Var("rs3",FTy 5),Var("f2",FTy 2),Var("rs2",FTy 5),Var("rs1",FTy 5), + Var("f3",FTy 3),Var("rd",FTy 5),Var("o",FTy 7)]) +; +val Itype_def = Def + ("Itype", + TP[Var("o",FTy 7),Var("f3",FTy 3),Var("rd",FTy 5),Var("rs1",FTy 5), + Var("imm",FTy 12)], + CC[Var("imm",FTy 12),Var("rs1",FTy 5),Var("f3",FTy 3),Var("rd",FTy 5), + Var("o",FTy 7)]) +; +val Stype_def = Def + ("Stype", + TP[Var("o",FTy 7),Var("f3",FTy 3),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("imm",FTy 12)], + CC[EX(Var("imm",FTy 12),LN 11,LN 5,FTy 7),Var("rs2",FTy 5), + Var("rs1",FTy 5),Var("f3",FTy 3), + EX(Var("imm",FTy 12),LN 4,LN 0,FTy 5),Var("o",FTy 7)]) +; +val SBtype_def = Def + ("SBtype", + TP[Var("o",FTy 7),Var("f3",FTy 3),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("imm",FTy 12)], + CC[Mop(Cast F1,Bop(Bit,Var("imm",FTy 12),LN 11)), + EX(Var("imm",FTy 12),LN 9,LN 4,FTy 6),Var("rs2",FTy 5), + Var("rs1",FTy 5),Var("f3",FTy 3),EX(Var("imm",FTy 12),LN 3,LN 0,F4), + Mop(Cast F1,Bop(Bit,Var("imm",FTy 12),LN 10)),Var("o",FTy 7)]) +; +val Utype_def = Def + ("Utype",TP[Var("o",FTy 7),Var("rd",FTy 5),Var("imm",FTy 20)], + CC[Var("imm",FTy 20),Var("rd",FTy 5),Var("o",FTy 7)]) +; +val UJtype_def = Def + ("UJtype",TP[Var("o",FTy 7),Var("rd",FTy 5),Var("imm",FTy 20)], + CC[Mop(Cast F1,Bop(Bit,Var("imm",FTy 20),LN 19)), + EX(Var("imm",FTy 20),LN 9,LN 0,FTy 10), + Mop(Cast F1,Bop(Bit,Var("imm",FTy 20),LN 10)), + EX(Var("imm",FTy 20),LN 18,LN 11,F8),Var("rd",FTy 5),Var("o",FTy 7)]) +; +val opc_def = Def + ("opc",Var("code",F8),CC[EX(Var("code",F8),LN 4,LN 0,FTy 5),LW(3,2)]) +; +val amofunc_def = Def + ("amofunc",TP[Var("code",FTy 5),Var("aq",F1),Var("rl",F1)], + CC[Var("code",FTy 5),Var("aq",F1),Var("rl",F1)]) +; +val Encode_def = Def + ("Encode",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(0,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(1,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BLT",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(4,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BGE",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(5,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BLTU",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(6,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("BGEU",CTy"Branch", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("SBtype",F32, + TP[Call("opc",FTy 7,LW(24,8)),LW(7,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(25,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Branch",CTy"instruction", + Call("JAL",CTy"Branch",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call + ("UJtype",F32, + TP[Call("opc",FTy 7,LW(27,8)),Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call("LUI",CTy"ArithI",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call + ("Utype",F32, + TP[Call("opc",FTy 7,LW(13,8)),Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call("AUIPC",CTy"ArithI",TP[Var("rd",FTy 5),Var("imm",FTy 20)])), + Call + ("Utype",F32, + TP[Call("opc",FTy 7,LW(5,8)),Var("rd",FTy 5),Var("imm",FTy 20)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(0,6),Var("imm",FTy 6)]])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("SLTIU",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("XORI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(4,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(0,6),Var("imm",FTy 6)]])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAI",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 6)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(16,6),Var("imm",FTy 6)]])), + (Call + ("ArithI",CTy"instruction", + Call + ("ORI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(6,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(4,8)),LW(7,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(32,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLL",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLT",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SLTU",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(4,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRL",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRA",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(32,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(6,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(7,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithI",CTy"instruction", + Call + ("ADDIW",CTy"ArithI", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(6,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(6,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(0,7),Var("imm",FTy 5)]])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(6,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(0,7),Var("imm",FTy 5)]])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAIW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 5)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(6,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(32,7),Var("imm",FTy 5)]])), + (Call + ("ArithR",CTy"instruction", + Call + ("ADDW",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("ArithR",CTy"instruction", + Call + ("SUBW",CTy"ArithR", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(32,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SLLW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRLW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("Shift",CTy"instruction", + Call + ("SRAW",CTy"Shift", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(32,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MUL",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULH",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULHSU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULHU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIV",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(4,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REM",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(6,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMU",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(12,8)),LW(7,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("MULW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(4,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("DIVUW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(6,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("MulDiv",CTy"instruction", + Call + ("REMUW",CTy"MulDiv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(14,8)),LW(7,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("Load",CTy"instruction", + Call + ("LB",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LH",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LBU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(4,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LHU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(5,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Load",CTy"instruction", + Call + ("LWU",CTy"Load", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(0,8)),LW(6,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SB",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(8,8)),LW(0,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SH",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(8,8)),LW(1,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(8,8)),LW(2,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(8,8)),LW(3,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("FENCE",CTy"instruction", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("pred",F4), + Var("succ",F4)]), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(3,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),CC[LW(0,4),Var("pred",F4),Var("succ",F4)]])), + (Call + ("FENCE_I",CTy"instruction", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)]), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(3,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("FArith",CTy"instruction", + Call + ("FADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(0,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(4,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMUL_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(8,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FDIV_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(12,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSQRT_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(44,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMIN_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(20,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMAX_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(20,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FEQ_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(80,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLT_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(80,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLE_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(80,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(1,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(5,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMUL_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(9,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FDIV_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(13,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FSQRT_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(45,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMIN_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(21,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMAX_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(21,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FEQ_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(81,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLT_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(81,7)])), + (Call + ("FArith",CTy"instruction", + Call + ("FLE_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(81,7)])), + (Call + ("FPLoad",CTy"instruction", + Call + ("FLW",CTy"FPLoad", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(1,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPLoad",CTy"instruction", + Call + ("FLD",CTy"FPLoad", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("imm",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(1,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPStore",CTy"instruction", + Call + ("FSW",CTy"FPStore", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(9,8)),LW(2,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("FPStore",CTy"instruction", + Call + ("FSD",CTy"FPStore", + TP[Var("rs1",FTy 5),Var("rs2",FTy 5),Var("imm",FTy 12)])), + Call + ("Stype",F32, + TP[Call("opc",FTy 7,LW(9,8)),LW(3,3),Var("rs1",FTy 5), + Var("rs2",FTy 5),Var("imm",FTy 12)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(16,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(0,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(17,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(0,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(18,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(0,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMADD_S",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(19,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(0,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(16,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(1,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FMSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(17,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(1,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMSUB_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(18,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(1,2)])), + (Call + ("FArith",CTy"instruction", + Call + ("FNMADD_D",CTy"FArith", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5), + Var("rs3",FTy 5),Var("frm",FTy 3)])), + Call + ("R4type",F32, + TP[Call("opc",FTy 7,LW(19,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),Var("rs3",FTy 5),LW(1,2)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(16,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(16,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(16,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(96,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(1,5),LW(96,7)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_X_S",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(112,7)])), + (Call + ("FConv",CTy"instruction", + Call("FCLASS_S",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(112,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_W",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(104,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_WU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(1,5),LW(104,7)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_S_X",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(120,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJ_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(17,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJN_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(17,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FSGNJX_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5),LW(17,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_W_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(97,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_WU_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(1,5),LW(97,7)])), + (Call + ("FConv",CTy"instruction", + Call("FCLASS_D",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(1,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(113,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_W",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(105,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_WU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(1,5),LW(105,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(1,5),LW(32,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(33,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(2,5),LW(96,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_S",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(3,5),LW(96,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_L",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(2,5),LW(104,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_S_LU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(3,5),LW(104,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_L_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(2,5),LW(97,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_LU_D",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(3,5),LW(97,7)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_X_D",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(113,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_L",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(2,5),LW(105,7)])), + (Call + ("FConv",CTy"instruction", + Call + ("FCVT_D_LU",CTy"FConv", + TP[Var("rd",FTy 5),Var("rs",FTy 5),Var("frm",FTy 3)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),Var("frm",FTy 3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(3,5),LW(105,7)])), + (Call + ("FConv",CTy"instruction", + Call("FMV_D_X",CTy"FConv",TP[Var("rd",FTy 5),Var("rs",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(20,8)),LW(0,3),Var("rd",FTy 5), + Var("rs",FTy 5),LW(0,5),LW(121,7)])), + (Call + ("AMO",CTy"instruction", + Call + ("LR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),LW(0,5), + Call("amofunc",FTy 7,TP[LW(2,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("LR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),LW(0,5), + Call("amofunc",FTy 7,TP[LW(2,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("SC_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(3,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("SC_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(2,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(1,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOADD_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(0,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(4,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOAND_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(12,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOOR_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(8,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(16,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(20,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(24,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_W",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(28,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOSWAP_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(1,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOADD_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(0,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOXOR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(4,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOAND_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(12,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOOR_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(8,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMIN_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(16,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAX_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(20,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMINU_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(24,5),Var("aq",F1),Var("rl",F1)])])), + (Call + ("AMO",CTy"instruction", + Call + ("AMOMAXU_D",CTy"AMO", + TP[Var("aq",F1),Var("rl",F1),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5)])), + Call + ("Rtype",F32, + TP[Call("opc",FTy 7,LW(11,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("rs2",FTy 5), + Call("amofunc",FTy 7,TP[LW(28,5),Var("aq",F1),Var("rl",F1)])])), + (Call("System",CTy"instruction",Const("ECALL",CTy"System")), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),LW(0,5),LW(0,12)])), + (Call("System",CTy"instruction",Const("EBREAK",CTy"System")), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),LW(0,5),LW(1,12)])), + (Call("System",CTy"instruction",Const("ERET",CTy"System")), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),LW(0,5), + LW(256,12)])), + (Call("System",CTy"instruction",Const("MRTS",CTy"System")), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),LW(0,5), + LW(773,12)])), + (Call("System",CTy"instruction",Const("WFI",CTy"System")), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),LW(0,5), + LW(258,12)])), + (Call + ("System",CTy"instruction", + Call("SFENCE_VM",CTy"System",Var("rs1",FTy 5))), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(0,3),LW(0,5),Var("rs1",FTy 5), + LW(257,12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRW",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(1,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRS",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(2,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRC",CTy"System", + TP[Var("rd",FTy 5),Var("rs1",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(3,3),Var("rd",FTy 5), + Var("rs1",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRWI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(5,3),Var("rd",FTy 5), + Var("imm",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRSI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(6,3),Var("rd",FTy 5), + Var("imm",FTy 5),Var("csr",FTy 12)])), + (Call + ("System",CTy"instruction", + Call + ("CSRRCI",CTy"System", + TP[Var("rd",FTy 5),Var("imm",FTy 5),Var("csr",FTy 12)])), + Call + ("Itype",F32, + TP[Call("opc",FTy 7,LW(28,8)),LW(7,3),Var("rd",FTy 5), + Var("imm",FTy 5),Var("csr",FTy 12)])), + (Const("UnknownInstruction",CTy"instruction"),LW(0,32)), + (Call + ("Internal",CTy"instruction", + Call("FETCH_MISALIGNED",CTy"Internal",AVar F64)),LW(0,32)), + (Call + ("Internal",CTy"instruction", + Call("FETCH_FAULT",CTy"Internal",AVar F64)),LW(0,32))])) +; +val DecodeRVC_def = Def + ("DecodeRVC",Var("h",F16), + Let(TP[bVar"b'15",bVar"b'14",bVar"b'13",bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7",bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3",bVar"b'2",bVar"b'1",bVar"b'0"], + BL(16,Var("h",F16)), + ITB([(bVar"b'15", + ITB([(bVar"b'0", + ITE(Mop(Not,bVar"b'1"), + ITB([(Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'11"), + Mop(Not,bVar"b'10")))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("Shift",CTy"instruction", + Call + ("SRLI",CTy"Shift", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'11"), + bVar"b'10"))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("Shift",CTy"instruction", + Call + ("SRAI",CTy"Shift", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'11", + Mop(Not,bVar"b'10")))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithI",CTy"instruction", + Call + ("ANDI",CTy"ArithI", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[REP(Mop(Cast F1, + LL[bVar"b'12"]),LN 7, + FTy 7), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And, + Mop(Not,bVar"b'6"), + Mop(Not,bVar"b'5"))))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("SUB",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And, + Mop(Not,bVar"b'6"), + bVar"b'5")))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("XOR",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And,bVar"b'6", + Mop(Not,bVar"b'5"))))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("OR",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And,bVar"b'6", + bVar"b'5")))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("AND",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And, + Mop(Not,bVar"b'6"), + Mop(Not,bVar"b'5"))))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("SUBW",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"), + Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,bVar"b'11", + Bop(And,bVar"b'10", + Bop(And, + Mop(Not,bVar"b'6"), + bVar"b'5")))))), + Let(Var("r",FTy 3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("ADDW",CTy"ArithR", + TP[CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2),Var("r",FTy 3)], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,Mop(Not,bVar"b'14"),bVar"b'13"), + Call + ("Branch",CTy"instruction", + Call + ("JAL",CTy"Branch", + TP[LW(0,5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]), + LN 10,FTy 10), + Mop(Cast F1,LL[bVar"b'8"]), + Mop(Cast(FTy 2), + LL[bVar"b'10",bVar"b'9"]), + Mop(Cast F1,LL[bVar"b'6"]), + Mop(Cast F1,LL[bVar"b'7"]), + Mop(Cast F1,LL[bVar"b'2"]), + Mop(Cast F1,LL[bVar"b'11"]), + Mop(Cast(FTy 3), + LL[bVar"b'5",bVar"b'4", + bVar"b'3"])]]))), + (Bop(And,bVar"b'14",Mop(Not,bVar"b'13")), + Call + ("Branch",CTy"instruction", + Call + ("BEQ",CTy"Branch", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8", + bVar"b'7"])],LW(0,5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]), + LN 5,FTy 5), + Mop(Cast(FTy 2), + LL[bVar"b'6",bVar"b'5"]), + Mop(Cast F1,LL[bVar"b'2"]), + Mop(Cast(FTy 2), + LL[bVar"b'11",bVar"b'10"]), + Mop(Cast(FTy 2), + LL[bVar"b'4",bVar"b'3"])]]))), + (Bop(And,bVar"b'14",bVar"b'13"), + Call + ("Branch",CTy"instruction", + Call + ("BNE",CTy"Branch", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8", + bVar"b'7"])],LW(0,5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]), + LN 5,FTy 5), + Mop(Cast(FTy 2), + LL[bVar"b'6",bVar"b'5"]), + Mop(Cast F1,LL[bVar"b'2"]), + Mop(Cast(FTy 2), + LL[bVar"b'11",bVar"b'10"]), + Mop(Cast(FTy 2), + LL[bVar"b'4",bVar"b'3"])]])))], + Const("UnknownInstruction",CTy"instruction")), + Const("UnknownInstruction",CTy"instruction"))), + (bVar"b'14", + ITB([(Bop(And,Mop(Not,bVar"b'13"),Mop(Not,bVar"b'1")), + Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(0,5),Mop(Cast F1,LL[bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11", + bVar"b'10"]), + Mop(Cast F1,LL[bVar"b'6"]),LW(0,2)]]))), + (Bop(And,bVar"b'13",Mop(Not,bVar"b'1")), + Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(0,4), + Mop(Cast(FTy 2), + LL[bVar"b'6",bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11", + bVar"b'10"]),LW(0,3)]]))), + (Bop(And,Mop(Not,bVar"b'13"),bVar"b'1"), + Call + ("Store",CTy"instruction", + Call + ("SW",CTy"Store", + TP[LW(2,5), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"]), + CC[LW(0,4), + Mop(Cast(FTy 2), + LL[bVar"b'8",bVar"b'7"]), + Mop(Cast F4, + LL[bVar"b'12",bVar"b'11", + bVar"b'10",bVar"b'9"]),LW(0,2)]]))), + (Bop(And,bVar"b'13",bVar"b'1"), + Call + ("Store",CTy"instruction", + Call + ("SD",CTy"Store", + TP[LW(2,5), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"]), + CC[LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11", + bVar"b'10"]),LW(0,3)]])))], + Const("UnknownInstruction",CTy"instruction"))), + (Bop(And,bVar"b'13",Mop(Not,bVar"b'1")), + Call + ("FPStore",CTy"instruction", + Call + ("FSD",CTy"FPStore", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(0,4), + Mop(Cast(FTy 2),LL[bVar"b'6",bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11",bVar"b'10"]), + LW(0,3)]]))), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + bVar"b'1")))))))))))), + Const("UnknownInstruction",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + bVar"b'1"))))))), + Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[LW(0,5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(0,12)]))), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,Mop(Not,bVar"b'12"),bVar"b'1")), + Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(0,5), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"])]))), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And, + Mop(Not,bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Bop(And, + Mop(Not, + bVar"b'2"), + bVar"b'1")))))))))))), + Call + ("System",CTy"instruction", + Const("EBREAK",CTy"System"))), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12", + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And,Mop(Not,bVar"b'3"), + Bop(And,Mop(Not,bVar"b'2"), + bVar"b'1"))))))), + Call + ("Branch",CTy"instruction", + Call + ("JALR",CTy"Branch", + TP[LW(1,5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(0,12)]))), + (Bop(And,Mop(Not,bVar"b'13"), + Bop(And,bVar"b'12",bVar"b'1")), + Let(Var("r",FTy 5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7"]), + Call + ("ArithR",CTy"instruction", + Call + ("ADD",CTy"ArithR", + TP[Var("r",FTy 5),Var("r",FTy 5), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"])])))), + (Bop(And,bVar"b'13",bVar"b'1"), + Call + ("FPStore",CTy"instruction", + Call + ("FSD",CTy"FPStore", + TP[LW(2,5), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"]), + CC[LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11",bVar"b'10"]), + LW(0,3)]])))], + Const("UnknownInstruction",CTy"instruction"))), + (bVar"b'13", + ITB([(bVar"b'0", + ITE(Mop(Not,bVar"b'1"), + ITB([(Mop(Not,bVar"b'14"), + Let(Var("r",FTy 5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]), + Call + ("ArithI",CTy"instruction", + Call + ("ADDIW",CTy"ArithI", + TP[Var("r",FTy 5),Var("r",FTy 5), + CC[REP(Mop(Cast F1, + LL[bVar"b'12"]),LN 7, + FTy 7), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3", + bVar"b'2"])]])))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,bVar"b'8", + Bop(And, + Mop(Not,bVar"b'7"), + Bop(And, + Mop(Not, + bVar"b'6"), + Bop(And, + Mop(Not, + bVar"b'5"), + Bop(And, + Mop(Not, + bVar"b'4"), + Bop(And, + Mop(Not, + bVar"b'3"), + Mop(Not, + bVar"b'2")))))))))))), + Const("UnknownInstruction",CTy"instruction")), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,bVar"b'8", + Mop(Not,bVar"b'7")))))), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[LW(2,5),LW(2,5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]), + LN 3,FTy 3), + Mop(Cast(FTy 2), + LL[bVar"b'4",bVar"b'3"]), + Mop(Cast F1,LL[bVar"b'5"]), + Mop(Cast F1,LL[bVar"b'2"]), + Mop(Cast F1,LL[bVar"b'6"]), + LW(0,4)]]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Mop(Not,bVar"b'2"))))))), + Const("UnknownInstruction",CTy"instruction")), + (bVar"b'14", + Call + ("ArithI",CTy"instruction", + Call + ("LUI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10", + bVar"b'9",bVar"b'8",bVar"b'7"]), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]), + LN 15,FTy 15), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5", + bVar"b'4",bVar"b'3", + bVar"b'2"])]])))], + Const("UnknownInstruction",CTy"instruction")), + Const("UnknownInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'14"),Mop(Not,bVar"b'1")), + Call + ("FPLoad",CTy"instruction", + Call + ("FLD",CTy"FPLoad", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(0,4), + Mop(Cast(FTy 2),LL[bVar"b'6",bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11",bVar"b'10"]), + LW(0,3)]]))), + (Bop(And,bVar"b'14",Mop(Not,bVar"b'1")), + Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(0,4), + Mop(Cast(FTy 2),LL[bVar"b'6",bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11",bVar"b'10"]), + LW(0,3)]]))), + (Bop(And,Mop(Not,bVar"b'14"),bVar"b'1"), + Call + ("FPLoad",CTy"instruction", + Call + ("FLD",CTy"FPLoad", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(2,5), + CC[LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"]), + Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 2),LL[bVar"b'6",bVar"b'5"]), + LW(0,3)]]))), + (Bop(And,bVar"b'14", + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + bVar"b'1")))))), + Const("UnknownInstruction",CTy"instruction")), + (Bop(And,bVar"b'14",bVar"b'1"), + Call + ("Load",CTy"instruction", + Call + ("LD",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(2,5), + CC[LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"]), + Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 2),LL[bVar"b'6",bVar"b'5"]), + LW(0,3)]])))], + Const("UnknownInstruction",CTy"instruction"))), + (bVar"b'14", + ITB([(Bop(And,Mop(Not,bVar"b'1"),Mop(Not,bVar"b'0")), + Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + CC[LW(1,2), + Mop(Cast(FTy 3), + LL[bVar"b'9",bVar"b'8",bVar"b'7"])], + CC[LW(0,5),Mop(Cast F1,LL[bVar"b'5"]), + Mop(Cast(FTy 3), + LL[bVar"b'12",bVar"b'11",bVar"b'10"]), + Mop(Cast F1,LL[bVar"b'6"]),LW(0,2)]]))), + (Bop(And,Mop(Not,bVar"b'1"),bVar"b'0"), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(0,5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]),LN 7,FTy 7), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"])]]))), + (Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,bVar"b'1", + Mop(Not,bVar"b'0"))))))), + Const("UnknownInstruction",CTy"instruction")), + (Bop(And,bVar"b'1",Mop(Not,bVar"b'0")), + Call + ("Load",CTy"instruction", + Call + ("LW",CTy"Load", + TP[Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9", + bVar"b'8",bVar"b'7"]),LW(2,5), + CC[LW(0,4), + Mop(Cast(FTy 2),LL[bVar"b'3",bVar"b'2"]), + Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 3), + LL[bVar"b'6",bVar"b'5",bVar"b'4"]), + LW(0,2)]])))], + Const("UnknownInstruction",CTy"instruction"))), + (Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'1"), + Mop(Not,bVar"b'0")))))))))), + Const("UnknownInstruction",CTy"instruction")), + (Bop(And,Mop(Not,bVar"b'1"),Mop(Not,bVar"b'0")), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[CC[LW(1,2), + Mop(Cast(FTy 3),LL[bVar"b'4",bVar"b'3",bVar"b'2"])], + LW(2,5), + CC[LW(0,2), + Mop(Cast F4, + LL[bVar"b'10",bVar"b'9",bVar"b'8",bVar"b'7"]), + Mop(Cast(FTy 2),LL[bVar"b'12",bVar"b'11"]), + Mop(Cast F1,LL[bVar"b'5"]), + Mop(Cast F1,LL[bVar"b'6"]),LW(0,2)]]))), + (Bop(And,Mop(Not,bVar"b'12"), + Bop(And,Mop(Not,bVar"b'11"), + Bop(And,Mop(Not,bVar"b'10"), + Bop(And,Mop(Not,bVar"b'9"), + Bop(And,Mop(Not,bVar"b'8"), + Bop(And,Mop(Not,bVar"b'7"), + Bop(And,Mop(Not,bVar"b'6"), + Bop(And,Mop(Not,bVar"b'5"), + Bop(And,Mop(Not,bVar"b'4"), + Bop(And, + Mop(Not,bVar"b'3"), + Bop(And, + Mop(Not,bVar"b'2"), + Bop(And, + Mop(Not, + bVar"b'1"), + bVar"b'0")))))))))))), + Call + ("ArithI",CTy"instruction", + Call("ADDI",CTy"ArithI",TP[LW(0,5),LW(0,5),LW(0,12)]))), + (Bop(And,Mop(Not,bVar"b'1"),bVar"b'0"), + Let(Var("r",FTy 5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7"]), + Call + ("ArithI",CTy"instruction", + Call + ("ADDI",CTy"ArithI", + TP[Var("r",FTy 5),Var("r",FTy 5), + CC[REP(Mop(Cast F1,LL[bVar"b'12"]),LN 7,FTy 7), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"])]])))), + (Bop(And,bVar"b'1",Mop(Not,bVar"b'0")), + Let(Var("r",FTy 5), + Mop(Cast(FTy 5), + LL[bVar"b'11",bVar"b'10",bVar"b'9",bVar"b'8", + bVar"b'7"]), + Call + ("Shift",CTy"instruction", + Call + ("SLLI",CTy"Shift", + TP[Var("r",FTy 5),Var("r",FTy 5), + CC[Mop(Cast F1,LL[bVar"b'12"]), + Mop(Cast(FTy 5), + LL[bVar"b'6",bVar"b'5",bVar"b'4", + bVar"b'3",bVar"b'2"])]]))))], + Const("UnknownInstruction",CTy"instruction")))) +; +val CBtype_def = Def + ("CBtype", + TP[Var("o",FTy 2),Var("f3",FTy 3),Var("rs1",FTy 3),Var("imm",F8)], + CC[Var("f3",FTy 3),Mop(Cast F1,Bop(Bit,Var("imm",F8),LN 7)), + EX(Var("imm",F8),LN 3,LN 2,FTy 2),Var("rs1",FTy 3), + EX(Var("imm",F8),LN 6,LN 5,FTy 2),EX(Var("imm",F8),LN 1,LN 0,FTy 2), + Mop(Cast F1,Bop(Bit,Var("imm",F8),LN 5)),Var("o",FTy 2)]) +; +val EncodeRVC_def = Def + ("EncodeRVC",Var("i",CTy"instruction"), + CS(Var("i",CTy"instruction"), + [(Call("Branch",CTy"instruction",Var("v#0",CTy"Branch")), + CS(Var("v#0",CTy"Branch"), + [(Call + ("BEQ",CTy"Branch",Var("v#1",PTy(FTy 5,PTy(FTy 5,FTy 12)))), + CS(TP[BL(5,Mop(Fst,Var("v#1",PTy(FTy 5,PTy(FTy 5,FTy 12))))), + Mop(Fst, + Mop(Snd,Var("v#1",PTy(FTy 5,PTy(FTy 5,FTy 12))))), + BL(12, + Mop(Snd, + Mop(Snd,Var("v#1",PTy(FTy 5,PTy(FTy 5,FTy 12))))))], + [(TP[TP[LF,LT,bVar"rs1'2",bVar"rs1'1",bVar"rs1'0"], + LW(0,5),LF,LF,LF,LF,LF,bVar"imm'6",bVar"imm'5", + bVar"imm'4",bVar"imm'3",bVar"imm'2",bVar"imm'1", + bVar"imm'0"], + Call + ("Comp",CTy"rvc", + Call + ("CBtype",F16, + TP[LW(1,2),LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"rs1'2",bVar"rs1'1",bVar"rs1'0"]), + CC[LW(0,1), + Mop(Cast(FTy 7), + LL[bVar"imm'6",bVar"imm'5",bVar"imm'4", + bVar"imm'3",bVar"imm'2",bVar"imm'1", + bVar"imm'0"])]]))), + (TP[TP[LF,LT,bVar"rs1'2",bVar"rs1'1",bVar"rs1'0"], + LW(0,5),LT,LT,LT,LT,LT,bVar"imm'6",bVar"imm'5", + bVar"imm'4",bVar"imm'3",bVar"imm'2",bVar"imm'1", + bVar"imm'0"], + Call + ("Comp",CTy"rvc", + Call + ("CBtype",F16, + TP[LW(1,2),LW(0,3), + Mop(Cast(FTy 3), + LL[bVar"rs1'2",bVar"rs1'1",bVar"rs1'0"]), + CC[LW(1,1), + Mop(Cast(FTy 7), + LL[bVar"imm'6",bVar"imm'5",bVar"imm'4", + bVar"imm'3",bVar"imm'2",bVar"imm'1", + bVar"imm'0"])]]))), + (TP[TP[AVar bTy,AVar bTy,AVar bTy,AVar bTy,AVar bTy], + AVar(FTy 5),AVar bTy,AVar bTy,AVar bTy,AVar bTy, + AVar bTy,AVar bTy,AVar bTy,AVar bTy,AVar bTy, + AVar bTy,AVar bTy,AVar bTy], + Call + ("Full",CTy"rvc", + Call("Encode",F32,Var("i",CTy"instruction"))))])), + (AVar(CTy"Branch"), + Call + ("Full",CTy"rvc", + Call("Encode",F32,Var("i",CTy"instruction"))))])), + (AVar(CTy"instruction"), + Call("Full",CTy"rvc",Call("Encode",F32,Var("i",CTy"instruction"))))])) +; +val log_instruction_def = Def + ("log_instruction",TP[Var("w",F32),Var("inst",CTy"instruction")], + Close + (qVar"state", + CC[LS"instr ",Mop(Cast sTy,Dest("procID",F8,qVar"state")),LS" ", + Mop(Cast sTy, + Mop(Cast nTy, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")))),LS" 0x", + Call("hex64",sTy,Apply(Const("PC",ATy(qTy,F64)),qVar"state")), + LS" : ",Call("hex32",sTy,Var("w",F32)),LS" ", + Call("instructionToString",sTy,Var("inst",CTy"instruction"))])) +; +val exitCode_def = Def + ("exitCode",AVar uTy, + Close + (qVar"state", + Mop(Cast nTy,Apply(Const("ExitCode",ATy(qTy,F64)),qVar"state")))) +; +val CYCLES_PER_TIMER_TICK_def = Def0 ("CYCLES_PER_TIMER_TICK",LN 200) +; +val tickClock_def = Def + ("tickClock",AVar uTy, + Close + (qVar"state", + Let(Var("v",F64), + Bop(Add, + Apply + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")),LW(1,64)), + Rupd + ("clock", + TP[Rupd + ("c_cycles", + TP[qVar"state", + Fupd + (Dest("c_cycles",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"),Var("v",F64))]), + Bop(Div,Var("v",F64), + Mop(Cast F64,Const("CYCLES_PER_TIMER_TICK",nTy)))])))) +; +val incrInstret_def = Def + ("incrInstret",AVar uTy, + Close + (qVar"state", + Rupd + ("c_instret", + TP[qVar"state", + Fupd + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state"), + Bop(Add, + Apply + (Dest("c_instret",ATy(F8,F64),qVar"state"), + Dest("procID",F8,qVar"state")),LW(1,64)))]))) +; +val checkTimers_def = Def + ("checkTimers",AVar uTy, + Close + (qVar"state", + Let(qVar"s", + ITE(Bop(Ugt,Dest("clock",F64,qVar"state"), + Bop(Add, + Dest + ("mtimecmp",F64, + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state")), + Dest + ("mtime_delta",F64, + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"state")))), + Let(Var("v",CTy"MachineCSR"), + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state"), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mip", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MTIP", + TP[Dest + ("mip",CTy"mip", + Var("v",CTy"MachineCSR")),LT])])), + qVar"state")),qVar"state"), + ITE(Bop(Ugt,Dest("clock",F64,qVar"s"), + Bop(Add, + Dest + ("stimecmp",F64, + Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")), + qVar"s")), + Dest + ("stime_delta",F64, + Apply + (Const("SCSR",ATy(qTy,CTy"SupervisorCSR")), + qVar"s")))), + Let(Var("v",CTy"MachineCSR"), + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s"), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mip", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("STIP", + TP[Dest + ("mip",CTy"mip", + Var("v",CTy"MachineCSR")),LT])])), + qVar"s")),qVar"s")))) +; +val Next_def = Def + ("Next",qVar"state", + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s",Apply(Call("clear_logs",ATy(qTy,qTy),LU),qVar"state"), + TP[Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s"), + qVar"s"]), + Let(TP[Var("v",CTy"FetchResult"),qVar"s"], + Apply + (Call("Fetch",ATy(qTy,PTy(CTy"FetchResult",qTy)),LU), + ITE(Mop(Not, + EQ(Dest("mtohost",F64,Var("v",CTy"MachineCSR")), + LW(0,64))), + ITE(Bop(Bit, + Dest + ("mtohost",F64, + Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s")),LN 0), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0",Rupd("done",TP[qVar"s",LT]), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'ExitCode",ATy(qTy,qTy), + Bop(Asr, + Dest + ("mtohost",F64, + Var("v",CTy"MachineCSR")),LN 1)), + qVar"s")), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mtohost", + TP[Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s"),LW(0,64)])),qVar"s")), + qVar"s")), + Let(TP[Var("v",OTy(CTy"TransferControl")),qVar"s"], + Let(qVar"s0", + Apply + (Call("checkTimers",ATy(qTy,qTy),LU), + CS(Var("v",CTy"FetchResult"), + [(Call + ("F_Result",CTy"FetchResult", + Call("Half",CTy"rawInstType",Var("h",F16))), + Apply + (Call + ("Run",ATy(qTy,qTy), + Call + ("DecodeRVC",CTy"instruction", + Var("h",F16))),qVar"s")), + (Call + ("F_Result",CTy"FetchResult", + Call("Word",CTy"rawInstType",Var("w",F32))), + Apply + (Call + ("Run",ATy(qTy,qTy), + Call + ("Decode",CTy"instruction",Var("w",F32))), + qVar"s")), + (Call + ("F_Error",CTy"FetchResult", + Var("inst",CTy"instruction")), + Apply + (Call + ("Run",ATy(qTy,qTy), + Var("inst",CTy"instruction")),qVar"s"))])), + TP[Apply + (Const + ("NextFetch",ATy(qTy,OTy(CTy"TransferControl"))), + qVar"s0"),qVar"s0"]), + Apply + (Call("tickClock",ATy(qTy,qTy),LU), + Let(TP[Var("v", + PTy(OTy(CTy"TransferControl"), + OTy(PTy(CTy"Interrupt",CTy"Privilege")))), + qVar"s"], + Let(TP[Var("v0", + OTy(PTy(CTy"Interrupt",CTy"Privilege"))), + qVar"s"], + Apply + (Call + ("checkInterrupts", + ATy(qTy, + PTy(OTy(PTy(CTy"Interrupt", + CTy"Privilege")),qTy)),LU), + qVar"s"), + TP[TP[Var("v",OTy(CTy"TransferControl")), + Var("v0", + OTy(PTy(CTy"Interrupt",CTy"Privilege")))], + qVar"s"]), + CS(Var("v", + PTy(OTy(CTy"TransferControl"), + OTy(PTy(CTy"Interrupt",CTy"Privilege")))), + [(TP[LO(CTy"TransferControl"), + LO(PTy(CTy"Interrupt",CTy"Privilege"))], + Let(TP[Var("v",F64),qVar"s"], + Let(qVar"s0", + Apply + (Call("incrInstret",ATy(qTy,qTy),LU), + qVar"s"), + TP[Apply + (Const("PC",ATy(qTy,F64)),qVar"s0"), + qVar"s0"]), + Apply + (Call + ("write'PC",ATy(qTy,qTy), + Bop(Add,Var("v",F64), + Apply + (Const("Skip",ATy(qTy,F64)), + qVar"s"))),qVar"s"))), + (TP[LO(CTy"TransferControl"), + Mop(Some, + TP[Var("i",CTy"Interrupt"), + Var("p",CTy"Privilege")])], + Let(TP[Var("v",F64),qVar"s"], + Let(qVar"s0", + Apply + (Call("incrInstret",ATy(qTy,qTy),LU), + qVar"s"), + TP[Apply + (Const("PC",ATy(qTy,F64)),qVar"s0"), + qVar"s0"]), + Apply + (Call + ("takeTrap",ATy(qTy,qTy), + TP[LT, + Call + ("interruptIndex",F4, + Var("i",CTy"Interrupt")), + Bop(Add,Var("v",F64), + Apply + (Const("Skip",ATy(qTy,F64)), + qVar"s")),LO F64, + Var("p",CTy"Privilege")]),qVar"s"))), + (TP[Mop(Some, + Call + ("BranchTo",CTy"TransferControl", + Var("addr",F64))), + AVar + (OTy(PTy(CTy"Interrupt",CTy"Privilege")))], + Apply + (Call + ("write'PC",ATy(qTy,qTy),Var("addr",F64)), + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + LO(CTy"TransferControl")), + Apply + (Call("incrInstret",ATy(qTy,qTy),LU), + qVar"s")))), + (TP[Mop(Some, + Const("Ereturn",CTy"TransferControl")), + AVar + (OTy(PTy(CTy"Interrupt",CTy"Privilege")))], + Let(TP[Var("v",F64),qVar"s"], + Apply + (Call("curEPC",ATy(qTy,PTy(F64,qTy)),LU), + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + LO(CTy"TransferControl")), + Apply + (Call + ("incrInstret",ATy(qTy,qTy),LU), + qVar"s"))), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'PC",ATy(qTy,qTy), + Var("v",F64)),qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Call + ("popPrivilegeStack", + CTy"mstatus", + Dest + ("mstatus", + CTy"mstatus", + Apply + (Const + ("MCSR", + ATy(qTy, + CTy"MachineCSR")), + qVar"s")))])), + qVar"s")))), + (TP[Mop(Some, + Call + ("Trap",CTy"TransferControl", + Var("t",CTy"SynchronousTrap"))), + AVar + (OTy(PTy(CTy"Interrupt",CTy"Privilege")))], + Let(TP[Var("v",F64),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + LO(CTy"TransferControl")),qVar"s"), + TP[Apply + (Const("PC",ATy(qTy,F64)),qVar"s0"), + qVar"s0"]), + Apply + (Call + ("takeTrap",ATy(qTy,qTy), + TP[LF, + Call + ("excCode",F4, + Dest + ("trap",CTy"ExceptionType", + Var("t",CTy"SynchronousTrap"))), + Var("v",F64), + Dest + ("badaddr",OTy F64, + Var("t",CTy"SynchronousTrap")), + LC("Machine",CTy"Privilege")]), + qVar"s"))), + (TP[Mop(Some,Const("Mrts",CTy"TransferControl")), + AVar + (OTy(PTy(CTy"Interrupt",CTy"Privilege")))], + Let(TP[Var("v",CTy"SupervisorCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'NextFetch",ATy(qTy,qTy), + LO(CTy"TransferControl")), + Apply + (Call + ("incrInstret",ATy(qTy,qTy),LU), + qVar"s")), + TP[Apply + (Const + ("SCSR", + ATy(qTy,CTy"SupervisorCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'PC",ATy(qTy,qTy), + Dest + ("stvec",F64, + Var("v",CTy"SupervisorCSR"))), + qVar"s")))]))))))) +; +val initIdent_def = Def + ("initIdent",Var("arch",CTy"Architecture"), + Close + (qVar"state", + Let(Var("v",CTy"MachineCSR"), + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state"), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcpuid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("ArchBase", + TP[Dest + ("mcpuid",CTy"mcpuid", + Var("v",CTy"MachineCSR")), + Call + ("archBase",FTy 2, + Var("arch",CTy"Architecture"))])])), + qVar"state"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcpuid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("U", + TP[Dest + ("mcpuid",CTy"mcpuid", + Var("v",CTy"MachineCSR")),LT])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcpuid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("S", + TP[Dest + ("mcpuid",CTy"mcpuid", + Var("v",CTy"MachineCSR")), + LT])])),qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcpuid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("M", + TP[Dest + ("mcpuid",CTy"mcpuid", + Var("v",CTy"MachineCSR")), + LT])])),qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mcpuid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("I", + TP[Dest + ("mcpuid", + CTy"mcpuid", + Var("v", + CTy"MachineCSR")), + LT])])),qVar"s"), + TP[Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mimpid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("RVSource", + TP[Dest + ("mimpid", + CTy"mimpid", + Var("v", + CTy"MachineCSR")), + LW(32768,16)])])), + qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mimpid", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("RVImpl", + TP[Dest + ("mimpid", + CTy"mimpid", + Var("v", + CTy"MachineCSR")), + LW(0,48)])])),qVar"s")))))))))) +; +val initMachine_def = Def + ("initMachine",Var("hartid",F8), + Close + (qVar"state", + Let(Var("v",CTy"MachineCSR"), + Apply(Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"state"), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("VM", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("vmMode",FTy 5, + LC("Mbare",CTy"VM_Mode"))])])), + qVar"state"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")),qVar"s0"), + qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MPRV", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("privLevel",FTy 2, + LC("Machine",CTy"Privilege"))])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MIE", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + LF])])),qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MFS", + TP[Dest + ("mstatus",CTy"mstatus", + Var("v",CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Initial", + CTy"ExtStatus"))])])), + qVar"s"), + TP[Apply + (Const("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MXS", + TP[Dest + ("mstatus", + CTy"mstatus", + Var("v", + CTy"MachineCSR")), + Call + ("ext_status",FTy 2, + LC("Off", + CTy"ExtStatus"))])])), + qVar"s"), + TP[Apply + (Const + ("MCSR",ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mstatus", + TP[Var("v",CTy"MachineCSR"), + Rupd + ("MSD", + TP[Dest + ("mstatus", + CTy"mstatus", + Var("v", + CTy"MachineCSR")), + LF])])),qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Let(TP[Var("v",CTy"MachineCSR"),qVar"s"], + Let(qVar"s0", + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mhartid", + TP[Var("v", + CTy"MachineCSR"), + Mop(Cast F64, + Var("hartid",F8))])), + qVar"s"), + TP[Apply + (Const + ("MCSR", + ATy(qTy,CTy"MachineCSR")), + qVar"s0"),qVar"s0"]), + Apply + (Call + ("write'MCSR",ATy(qTy,qTy), + Rupd + ("mtvec", + TP[Var("v",CTy"MachineCSR"), + Mop(Cast F64,LW(256,16))])), + qVar"s"))))))))))) +; +val initRegs_def = Def + ("initRegs",nVar"pc", + Close + (qVar"state", + Rupd + ("done", + TP[Apply + (Call + ("write'NextFetch",ATy(qTy,qTy),LO(CTy"TransferControl")), + Apply + (Call("write'PC",ATy(qTy,qTy),Mop(Cast F64,nVar"pc")), + Mop(Snd, + Apply + (For(TP[LN 0,LN 31, + Close + (nVar"i", + Close + (qVar"state", + TP[LU, + Apply + (Call + ("write'fpr",ATy(qTy,qTy), + TP[LW(0,64), + Mop(Cast(FTy 5),nVar"i")]), + qVar"state")]))]), + Mop(Snd, + Apply + (For(TP[LN 0,LN 31, + Close + (nVar"i", + Close + (qVar"state", + TP[LU, + Apply + (Call + ("write'gpr", + ATy(qTy,qTy), + TP[LW(0,64), + Mop(Cast(FTy 5), + nVar"i")]), + qVar"state")]))]), + qVar"state")))))),LF]))) + +val () = Import.finish 1 diff --git a/src/shared/l3-machine-code/riscv/step/Holmakefile b/src/shared/l3-machine-code/riscv/step/Holmakefile new file mode 100644 index 000000000..c2ba1263d --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/Holmakefile @@ -0,0 +1,4 @@ +INCLUDES = $(HOLBADIR)/src/shared/l3-machine-code/riscv/model + +all: $(DEFAULT_TARGETS) +.PHONY: all diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sig b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sig new file mode 100644 index 000000000..9757fb28a --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sig @@ -0,0 +1,9 @@ +signature riscv_stepLib = +sig + val hex_to_padded_opcode: string -> Term.term + val riscv_decode: Term.term -> Thm.thm + val riscv_decode_hex: string -> Thm.thm + val riscv_step: Term.term -> Thm.thm + val riscv_step_hex: string -> Thm.thm + val riscv_dict: (string * Term.term) list +end diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml new file mode 100644 index 000000000..853bebe76 --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml @@ -0,0 +1,370 @@ +(* ------------------------------------------------------------------------ + RISCV step evaluator + ------------------------------------------------------------------------ *) + +structure riscv_stepLib :> riscv_stepLib = +struct + +open HolKernel boolLib bossLib +open blastLib riscvTheory riscv_stepTheory + +structure Parse = struct + open Parse + val (Type, Term) = parse_from_grammars riscv_stepTheory.riscv_step_grammars +end +open Parse + +val ERR = Feedback.mk_HOL_ERR "riscv_stepLib" + +val () = show_assums := true + +val s = ``s:riscv_state`` + +(* ------------------------------------------------------------------------- + Fetch + ------------------------------------------------------------------------- *) + +local + val i16 = fcpSyntax.mk_int_numeric_type 16 + val i32 = fcpSyntax.mk_int_numeric_type 32 + val x = Term.mk_var ("x", ``:rawInstType``) + fun padded_opcode v = + let + val (l, ty) = listSyntax.dest_list v + val () = ignore (ty = Type.bool andalso List.length l <= 32 orelse + raise ERR "mk_opcode" "bad opcode") + fun ends_in_TT [] = false + | ends_in_TT [x] = false + | ends_in_TT [x,y] = aconv x y andalso aconv x boolSyntax.T + | ends_in_TT (x::xs) = ends_in_TT xs + in + if ends_in_TT l then + listSyntax.mk_list (utilsLib.padLeft boolSyntax.F 32 l, ty) + else + listSyntax.mk_list (utilsLib.padLeft boolSyntax.F 16 l, ty) + end + fun pad_opcode v = + let + val xs = padded_opcode v + val (l,ty) = listSyntax.dest_list xs + in + if length l < 32 then mk_comb(``Half``,bitstringSyntax.mk_v2w (xs, i16)) + else mk_comb(``Word``,bitstringSyntax.mk_v2w (xs, i32)) + end +in + val padded_opcode = padded_opcode + fun fetch v = let + val vs = pad_opcode v + val lemma = if can (match_term ``Word _``) vs + then riscv_stepTheory.Fetch32 else riscv_stepTheory.Fetch16 + val bs = vs |> rand |> rand + in lemma |> SPEC bs |> SIMP_RULE std_ss [listTheory.CONS_11] + |> REWRITE_RULE [GSYM AND_IMP_INTRO] |> UNDISCH_ALL end + val fetch_hex = fetch o bitstringSyntax.bitstring_of_hexstring +end + +(* ------------------------------------------------------------------------- + Decode + ------------------------------------------------------------------------- *) + +local + val Decode = + riscvTheory.Decode_def + |> Thm.SPEC (bitstringSyntax.mk_vec 32 0) + |> Conv.RIGHT_CONV_RULE + (REWRITE_CONV + [riscvTheory.boolify32_v2w, asImm12_def, asImm20_def, + asSImm12_def] + THENC Conv.DEPTH_CONV PairedLambda.let_CONV + THENC EVAL + ) + val DecodeRVC = + riscvTheory.DecodeRVC_def + |> Thm.SPEC (bitstringSyntax.mk_vec 16 0) + |> Conv.RIGHT_CONV_RULE + (REWRITE_CONV [riscvTheory.boolify16_v2w] + THENC Conv.DEPTH_CONV PairedLambda.let_CONV + THENC EVAL + ) + val v32 = fst (bitstringSyntax.dest_v2w (bitstringSyntax.mk_vec 32 0)) + val v16 = fst (bitstringSyntax.dest_v2w (bitstringSyntax.mk_vec 16 0)) +in + val get_opc = boolSyntax.rand o boolSyntax.rand o utilsLib.lhsc + fun DecodeRISCV tm = + let + val (l,ty) = listSyntax.dest_list tm + in + if length l < 32 then + DecodeRVC |> Thm.INST (fst (Term.match_term v16 tm)) |> REWRITE_RULE [] + |> MATCH_MP DecodeRVC_IMP_DecodeAny + else + Decode |> Thm.INST (fst (Term.match_term v32 tm)) |> REWRITE_RULE [] + |> MATCH_MP Decode_IMP_DecodeAny + end +end + +fun make_nop (s, p) = + (s ^ "_NOP", + String.substring (p, 0, 20) ^ "FFFFF" ^ String.extract (p, 25, NONE)) + +fun find_all_rvc s = + let + val tm = utilsLib.pattern s + val th = DecodeRISCV tm + val tm = th |> concl |> rand + in + if not (is_cond tm) then [s] else let + val (b,_,_) = dest_cond tm + val v = hd (free_vars b |> rev) + val index = dest_var v |> fst |> explode |> tl |> implode |> string_to_int + fun flip_nth_underscore n [] = fail () + | flip_nth_underscore n (x::xs) = + if x <> #"_" then let + val (ys,zs) = flip_nth_underscore n xs + in (x::ys,x::zs) end + else if n = 0 then (#"F" :: xs, #"T" :: xs) else let + val (ys,zs) = flip_nth_underscore (n-1) xs + in (x::ys,x::zs) end + val (s1,s2) = flip_nth_underscore index (explode s) + in + find_all_rvc (implode s1) @ find_all_rvc (implode s2) + end + end; + +val rvc_pats = map (fn s => ("RVC_" ^ s, s)) + (find_all_rvc "______________TF" @ + find_all_rvc "______________FT" @ + find_all_rvc "______________FF") + +val riscv_decodes = + List.map (I ## (DecodeRISCV o utilsLib.pattern)) rvc_pats @ + List.map (I ## (DecodeRISCV o utilsLib.pattern)) + (let + val l = + [ + ("JALR", "_________________FFF_____TTFFTTT"), + ("JAL", "_________________________TTFTTTT"), + ("LUI", "_________________________FTTFTTT"), + ("AUIPC", "_________________________FFTFTTT"), + ("ADDI", "_________________FFF_____FFTFFTT"), + ("SLLI", "FFFFFF___________FFT_____FFTFFTT"), + ("SLTI", "_________________FTF_____FFTFFTT"), + ("SLTIU", "_________________FTT_____FFTFFTT"), + ("XORI", "_________________TFF_____FFTFFTT"), + ("SRLI", "FFFFFF___________TFT_____FFTFFTT"), + ("SRAI", "FTFFFF___________TFT_____FFTFFTT"), + ("ORI", "_________________TTF_____FFTFFTT"), + ("ANDI", "_________________TTT_____FFTFFTT"), + ("ADD", "FFFFFFF__________FFF_____FTTFFTT"), + ("SUB", "FTFFFFF__________FFF_____FTTFFTT"), + ("SLL", "FFFFFFF__________FFT_____FTTFFTT"), + ("SLT", "FFFFFFF__________FTF_____FTTFFTT"), + ("SLTU", "FFFFFFF__________FTT_____FTTFFTT"), + ("XOR", "FFFFFFF__________TFF_____FTTFFTT"), + ("SRL", "FFFFFFF__________TFT_____FTTFFTT"), + ("SRA", "FTFFFFF__________TFT_____FTTFFTT"), + ("OR", "FFFFFFF__________TTF_____FTTFFTT"), + ("AND", "FFFFFFF__________TTT_____FTTFFTT"), + ("ADDIW", "_________________FFF_____FFTTFTT"), + ("SLLIW", "FFFFFFF__________FFT_____FFTTFTT"), + ("SRLIW", "FFFFFFF__________TFT_____FFTTFTT"), + ("SRAIW", "FTFFFFF__________TFT_____FFTTFTT"), + ("ADDW", "FFFFFFF__________FFF_____FTTTFTT"), + ("SUBW", "FTFFFFF__________FFF_____FTTTFTT"), + ("SLLW", "FFFFFFF__________FFT_____FTTTFTT"), + ("SRLW", "FFFFFFF__________TFT_____FTTTFTT"), + ("SRAW", "FTFFFFF__________TFT_____FTTTFTT"), + ("MUL", "FFFFFFT__________FFF_____FTTFFTT"), + ("MULH", "FFFFFFT__________FFT_____FTTFFTT"), + ("MULHSU", "FFFFFFT__________FTF_____FTTFFTT"), + ("MULHU", "FFFFFFT__________FTT_____FTTFFTT"), + ("DIV", "FFFFFFT__________TFF_____FTTFFTT"), + ("DIVU", "FFFFFFT__________TFT_____FTTFFTT"), + ("REM", "FFFFFFT__________TTF_____FTTFFTT"), + ("REMU", "FFFFFFT__________TTT_____FTTFFTT"), + ("MULW", "FFFFFFT__________FFF_____FTTTFTT"), + ("DIVW", "FFFFFFT__________TFF_____FTTTFTT"), + ("DIVUW", "FFFFFFT__________TFT_____FTTTFTT"), + ("REMW", "FFFFFFT__________TTF_____FTTTFTT"), + ("REMUW", "FFFFFFT__________TTT_____FTTTFTT"), + ("LB", "_________________FFF_____FFFFFTT"), + ("LH", "_________________FFT_____FFFFFTT"), + ("LW", "_________________FTF_____FFFFFTT"), + ("LD", "_________________FTT_____FFFFFTT"), + ("LBU", "_________________TFF_____FFFFFTT"), + ("LHU", "_________________TFT_____FFFFFTT"), + ("LWU", "_________________TTF_____FFFFFTT") + ] + in + l @ List.map make_nop l @ + [ + ("SB", "_________________FFF_____FTFFFTT"), + ("SH", "_________________FFT_____FTFFFTT"), + ("SW", "_________________FTF_____FTFFFTT"), + ("SD", "_________________FTT_____FTFFFTT"), + ("BEQ", "_________________FFF_____TTFFFTT"), + ("BNE", "_________________FFT_____TTFFFTT"), + ("BLT", "_________________TFF_____TTFFFTT"), + ("BGE", "_________________TFT_____TTFFFTT"), + ("BLTU", "_________________TTF_____TTFFFTT"), + ("BGEU", "_________________TTT_____TTFFFTT") + ] + end) + +local + val net = + List.foldl (fn ((_, th), nt) => LVTermNet.insert (nt, ([], get_opc th), th)) + LVTermNet.empty riscv_decodes +in + fun riscv_decode v = + let + val tm = padded_opcode v + in + case LVTermNet.match (net, tm) of + [] => DecodeRISCV tm (* fallback *) + | [(([], opc), th)] => Thm.INST (fst (Term.match_term opc tm)) th + | [(([], opc), th), _] => Thm.INST (fst (Term.match_term opc tm)) th + | _ => raise ERR "decode" (utilsLib.long_term_to_string v) + end + val riscv_decode_hex = riscv_decode o bitstringSyntax.bitstring_of_hexstring + val riscv_dict = List.map (I ## (rand o get_opc)) riscv_decodes +end + +(* +val thms = List.map (riscv_decode o snd) riscv_dict +*) + +(* ------------------------------------------------------------------------- + Run + ------------------------------------------------------------------------- *) + +val STATE_CONV = + Conv.QCONV + (REWRITE_CONV + ([ASSUME ``^s.exception = riscv$NoException``, + ASSUME ``^s.c_NextFetch ^s.procID = NONE``, + riscv_stepTheory.update_pc, updateTheory.UPDATE_EQ] @ + utilsLib.datatype_rewrites true "riscv" ["riscv_state"])) + +val state_rule = Conv.RIGHT_CONV_RULE STATE_CONV +val full_state_rule = utilsLib.ALL_HYP_CONV_RULE STATE_CONV o state_rule + + + +val fetch_inst = + Thm.INST [] (* [s |-> snd (pairSyntax.dest_pair (utilsLib.rhsc (fetch ``[F]``)))] *) + +local + val rwts = List.map (full_state_rule o fetch_inst o DB.fetch "riscv_step") + riscv_stepTheory.rwts + val fnd = utilsLib.find_rw (utilsLib.mk_rw_net utilsLib.lhsc rwts) + val rule = Conv.DEPTH_CONV wordsLib.word_EQ_CONV + THENC REWRITE_CONV [riscv_stepTheory.v2w_0_rwts] + val eval_simp_rule = + utilsLib.ALL_HYP_CONV_RULE rule o Conv.CONV_RULE (Conv.RHS_CONV rule) + fun eval tm rwt = + let + val thm = eval_simp_rule (utilsLib.INST_REWRITE_CONV1 rwt tm) + in + if utilsLib.vacuous thm then NONE else SOME thm + end + val neg_count = List.length o List.filter boolSyntax.is_neg o Thm.hyp + fun err tm s = ( Parse.print_term tm; print "\n"; raise ERR "run" s ) +in + fun run tm = + (case List.mapPartial (eval tm) (fnd tm) of + [] => err tm "no valid step theorem" + | [x] => x + | l => List.last (mlibUseful.sort_map neg_count Int.compare l)) + handle HOL_ERR {message = "not found", origin_function = "find_rw", ...} => + err tm "instruction instance not supported" +end + +(* ------------------------------------------------------------------------- + Evaluator + ------------------------------------------------------------------------- *) + +local + fun mkselnm ty f = TypeBasePure.mk_recordtype_fieldsel{tyname=ty,fieldname=f} + fun mk_proj s = + Lib.curry Term.mk_comb + (Term.prim_mk_const {Thy = "riscv", Name = mkselnm "riscv_state" s}) + fun proj f = STATE_CONV o f o utilsLib.rhsc + val proj_exception = proj (mk_proj "exception") + val proj_NextFetch = mk_proj "c_NextFetch" + val proj_procID = mk_proj "procID" + val proj_NextFetch_procID = + proj (fn tm => Term.mk_comb (proj_NextFetch tm, proj_procID tm)) + val ap_snd = Thm.AP_TERM ``SND: unit # riscv_state -> riscv_state`` + val snd_conv = Conv.REWR_CONV pairTheory.SND + fun spec_run thm3 ethm = + Conv.RIGHT_CONV_RULE + (Conv.RAND_CONV (Conv.REWR_CONV ethm) THENC snd_conv) (ap_snd thm3) + fun next th = PURE_REWRITE_RULE [word_bit_0_lemmas] o state_rule o Drule.MATCH_MP th + val MP_Next_n = next riscv_stepTheory.NextRISCV + val MP_Next_c = next riscv_stepTheory.NextRISCV_cond_branch + val MP_Next_b = next riscv_stepTheory.NextRISCV_branch + val Run_CONV = utilsLib.Run_CONV ("riscv", s) o utilsLib.rhsc + fun tidy_up_signalAddressException th = + let + val rw = UNDISCH avoid_signalAddressException + fun FORCE_REWR_CONV rw tm = + let + val (p,_) = match_term (rw |> concl |> rator |> rand) tm + in INST p rw end handle HOL_ERR _ => NO_CONV tm; + in + CONV_RULE (DEPTH_CONV (FORCE_REWR_CONV rw)) th + |> DISCH_ALL |> SIMP_RULE std_ss [word_bit_add_lsl_simp] + |> SIMP_RULE (srw_ss ()) [] |> UNDISCH_ALL + end +in + fun riscv_step v = + let + val thm1 = fetch v + val thm2 = riscv_decode v |> SIMP_RULE std_ss [] + val new_s = thm1 |> concl |> rand |> rand + val thm3 = fetch_inst (Drule.SPEC_ALL (Run_CONV thm2)) |> INST [s |-> new_s] + val tm = utilsLib.rhsc thm3 + val ethm = run tm + val ethm = tidy_up_signalAddressException ethm + val thm4 = Conv.RIGHT_CONV_RULE (Conv.REWR_CONV ethm) thm3 + val thm5 = proj_exception thm4 + val thm6 = proj_NextFetch_procID thm4 + val thm = Drule.LIST_CONJ [thm1, thm2, thm4, thm5, thm6] + val tm = utilsLib.rhsc thm6 + in + if optionSyntax.is_none tm + then MP_Next_n thm + else if boolSyntax.is_cond tm + then MP_Next_c thm + else MP_Next_b thm + end +end + +val riscv_step_hex = riscv_step o bitstringSyntax.bitstring_of_hexstring + +val hex_to_padded_opcode = + padded_opcode o bitstringSyntax.bitstring_of_hexstring + +(* ========================================================================= *) + +(* Testing +fun find_opc n = Lib.assoc n riscv_dict +val v = find_opc "BEQ" +val v = find_opc "JAL" +val v = find_opc "ADDI" +val v = bitstringSyntax.bitstring_of_hexstring "B3" +val thms = List.map (Count.apply riscv_step o snd) riscv_dict + +val v = (v |> rand) +val th = riscv_step v + +val v = bitstringSyntax.bitstring_of_hexstring "56fd" +val th = riscv_step v + +filter (not o can (riscv_step o bitstringSyntax.bitstring_of_hexstring)) vs + +open riscv_stepLib +*) + +end diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml b/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml new file mode 100644 index 000000000..45c99d9cc --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml @@ -0,0 +1,899 @@ +(* ------------------------------------------------------------------------ + Definitions and theorems used by RISC-V step evaluator (riscv_stepLib) + ------------------------------------------------------------------------ *) + +open HolKernel boolLib bossLib + +open utilsLib +open wordsLib blastLib alignmentTheory +open riscvTheory + +val () = Theory.new_theory "riscv_step" +val _ = ParseExtras.temp_loose_equality() + +val ERR = mk_HOL_ERR "riscv_stepTheory"; + +val () = + ( List.app (fn f => f ()) + [numLib.prefer_num, wordsLib.prefer_word, wordsLib.guess_lengths] + ; show_assums := true + ; General.ignore (Parse.hide "imm") + ) + +fun uprove a b = utilsLib.STRIP_UNDISCH (Q.prove (a, b)) + +(* ------------------------------------------------------------------------ + Simplified Fetch and Next functions + ------------------------------------------------------------------------ *) + +val Fetch_def = Define` + Fetch s = + let (w, s) = translateAddr (PC s, Instruction, Read) s in + (rawReadInst (THE w) s)` + +val update_pc_def = Define `update_pc v s = SOME (write'PC v s)` + +val DecodeAny_def = Define ` + DecodeAny f = case f of Half h => DecodeRVC h | Word w => Decode w` + +val NextRISCV_def = Define` + NextRISCV s = + let (f, s) = Fetch s in + let s = Run (DecodeAny f) s in + if s.exception <> NoException then + NONE + else + let pc = PC s in + case NextFetch s of + NONE => update_pc (pc + Skip s) s + | SOME (BranchTo a) => update_pc a (write'NextFetch NONE s) + | _ => NONE` + +(* ------------------------------------------------------------------------ + Evaluation theorem + ------------------------------------------------------------------------ *) + +val NextRISCV = Q.store_thm("NextRISCV", + `(Fetch s = (w, s')) /\ + (DecodeAny w = i) /\ + (Run i s' = nxt) /\ + (nxt.exception = NoException) /\ + (nxt.c_NextFetch nxt.procID = NONE) ==> + (NextRISCV s = update_pc (nxt.c_PC nxt.procID + Skip nxt) nxt)`, + lrw [NextRISCV_def, PC_def, NextFetch_def, write'NextFetch_def] + ) + +val NextRISCV_branch = Q.store_thm("NextRISCV_branch", + `(Fetch s = (w, s')) /\ + (DecodeAny w = i) /\ + (Run i s' = nxt) /\ + (nxt.exception = NoException) /\ + (nxt.c_NextFetch nxt.procID = SOME (BranchTo a)) ==> + (NextRISCV s = + update_pc a + (nxt with c_NextFetch := (nxt.procID =+ NONE) nxt.c_NextFetch))`, + lrw [NextRISCV_def, PC_def, NextFetch_def, write'NextFetch_def] + \\ Cases_on `Run (Decode w) s'` + \\ fs [] + ) + +val NextRISCV_cond_branch = Q.store_thm("NextRISCV_cond_branch", + `(Fetch s = (w, s')) /\ + (DecodeAny w = i) /\ + (Run i s' = nxt) /\ + (nxt.exception = NoException) /\ + (nxt.c_NextFetch nxt.procID = if b then SOME (BranchTo a) else NONE) ==> + (NextRISCV s = + update_pc (if b then a else nxt.c_PC nxt.procID + Skip nxt) + (nxt with c_NextFetch := (nxt.procID =+ NONE) nxt.c_NextFetch))`, + lrw [NextRISCV_def, PC_def, NextFetch_def, write'NextFetch_def] + \\ Cases_on `Run (DecodeAny w) s'` + \\ fs [update_pc_def, write'PC_def, riscv_state_component_equality, + combinTheory.UPDATE_APPLY_IMP_ID] + ) + +(* ------------------------------------------------------------------------ + Sub-word select operation (temporary) + ------------------------------------------------------------------------ *) + +val select_def = zDefine` + select (p:'a word) (w: word64) = + let sz = 64 DIV (2 ** dimindex(:'a)) in + let l = w2n p * sz in + (l + sz - 1 >< l) w : 'b word` + +(* ------------------------------------------------------------------------ + Word extend abbreviations + ------------------------------------------------------------------------ *) + +val () = List.app Parse.temp_overload_on + [ + ("s_extend32", ``\w: word64. sw2sw ((31 >< 0) w : word32) : word64``), + ("z_extend32", ``\w: word64. w2w ((31 >< 0) w : word32) : word64``), + ("s_extend16", ``\w: word64. sw2sw ((15 >< 0) w : word16) : word64``), + ("z_extend16", ``\w: word64. w2w ((15 >< 0) w : word16) : word64``), + ("s_extend8", ``\w: word64. sw2sw ((7 >< 0) w : word8) : word64``), + ("z_extend8", ``\w: word64. w2w ((7 >< 0) w : word8) : word64``) + ] + +(* ------------------------------------------------------------------------ + Simplifying Rewrites + ------------------------------------------------------------------------ *) + +val word_bit_1_0 = store_thm("word_bit_1_0[simp]", + ``(word_bit 1 ((v2w [x0; x1; x2; x3; x4; x5; x6; x7]):word8) = x6) /\ + (word_bit 0 ((v2w [x0; x1; x2; x3; x4; x5; x6; x7]):word8) = x7)``, + blastLib.BBLAST_TAC); + +val cond_lem1 = Q.prove( + `(if b1 then (if b2 then x else y1) else (if b2 then x else y2)) = + (if b2 then x else if b1 then y1 else y2)`, + rw [] + ) + +val cond_rand_shift = Q.prove( + `((if b then x else y) << n = if b then x << n else y << n) /\ + ((if b then x else y) >>> n = if b then x >>> n else y >>> n)`, + rw [] + ) + +val word_bit_0_lemmas = Q.store_thm("word_bit_0_lemmas", + `!w. ¬word_bit 0 (0xFFFFFFFFFFFFFFFEw && w:word64) /\ + word_bit 0 ((0xFFFFFFFFFFFFFFFEw && w:word64) + v) = word_bit 0 v`, + blastLib.BBLAST_TAC) + +val cond_rand_thms = + utilsLib.mk_cond_rand_thms + [pairSyntax.fst_tm, + pairSyntax.snd_tm, + wordsSyntax.sw2sw_tm, + wordsSyntax.w2w_tm, + wordsSyntax.word_add_tm, + wordsSyntax.word_and_tm, + wordsSyntax.word_or_tm, + wordsSyntax.word_xor_tm, + ``(=):Architecture -> Architecture -> bool``, + ``(=):'a word -> 'a word -> bool``, + ``(h >< l) : 'a word -> 'b word`` + ] + +val ifTF = Q.prove(`(if b then T else F) = b`, rw []) + +val v2w_0_rwts = Q.store_thm("v2w_0_rwts", + `((v2w [F; F; F; F; T] = 1w: word5)) /\ + ((v2w [F; F; F; F; F] = 0w: word5)) /\ + ((v2w [T; b3; b2; b1; b0] = 0w: word5) = F) /\ + ((v2w [b3; T; b2; b1; b0] = 0w: word5) = F) /\ + ((v2w [b3; b2; T; b1; b0] = 0w: word5) = F) /\ + ((v2w [b3; b2; b1; T; b0] = 0w: word5) = F) /\ + ((v2w [b3; b2; b1; b0; T] = 0w: word5) = F)`, + blastLib.BBLAST_TAC + ) + +val aligned2 = Q.prove( + `(!w: word64. ((1 >< 0) w = 0w: word2) = aligned 2 w)`, + simp [alignmentTheory.aligned_extract] + \\ blastLib.BBLAST_TAC + ) + +val aligned3 = Q.prove( + `(!w: word64. (w2n ((2 >< 0) w: word3) = 0) = aligned 3 w)`, + simp [alignmentTheory.aligned_extract] + \\ blastLib.BBLAST_TAC + ) + +val address_align = blastLib.BBLAST_PROVE + ``w2w ((63 >< 3) a : 61 word) << 3 = (63 '' 3) (a: word64)`` + +val address_align2 = blastLib.BBLAST_PROVE + ``w2w ((63 >< 3) a + 1w: 61 word) << 3 = (63 '' 3) (a: word64) + 8w`` + +val address_aligned3 = uprove + `aligned 3 (a: word64) ==> ((63 '' 3) a = a)` + ( + simp [alignmentTheory.aligned_extract] + \\ blastLib.BBLAST_TAC + ) + +val words_of_dword = Q.prove( + `!b7:word8 b6:word8 b5:word8 b4:word8 b3:word8 b2:word8 b1:word8 b0:word8. + ((63 >< 32) ( b7 @@ b6 @@ b5 @@ b4 @@ b3 @@ b2 @@ b1 @@ b0 ) = + b7 @@ b6 @@ b5 @@ b4) /\ + ((31 >< 0 ) ( b7 @@ b6 @@ b5 @@ b4 @@ b3 @@ b2 @@ b1 @@ b0 ) = + b3 @@ b2 @@ b1 @@ b0)`, + simp_tac (srw_ss()++wordsLib.WORD_EXTRACT_ss) [] + ) + +val read_word = uprove + `aligned 2 (a: word64) ==> + ((if word_bit 2 a then + (63 >< 32) + (mem ((63 '' 3) a + 7w) @@ + mem ((63 '' 3) a + 6w) @@ + mem ((63 '' 3) a + 5w) @@ + mem ((63 '' 3) a + 4w) @@ + mem ((63 '' 3) a + 3w) @@ + mem ((63 '' 3) a + 2w) @@ + mem ((63 '' 3) a + 1w) @@ + mem ((63 '' 3) a)) : word32 + else + (31 >< 0) + (mem ((63 '' 3) a + 7w) @@ + mem ((63 '' 3) a + 6w) @@ + mem ((63 '' 3) a + 5w) @@ + mem ((63 '' 3) a + 4w) @@ + mem ((63 '' 3) a + 3w) @@ + mem ((63 '' 3) a + 2w) @@ + mem ((63 '' 3) a + 1w) @@ + mem ((63 '' 3) a))) = + mem (a + 3w) @@ mem (a + 2w) @@ mem (a + 1w) @@ (mem a : word8))` + ( + rewrite_tac [GSYM aligned2, words_of_dword] + \\ strip_tac + \\ CASE_TAC + >| [ + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC + ] + \\ simp [] + ) + +val tac = + lrw [select_def, alignmentTheory.aligned_extract] + >| [ + `(2 >< 2) x = 0w: word1` by blastLib.FULL_BBLAST_TAC, + `((2 >< 2) x = 1w: word1) /\ + ((2 >< 0) x = 4w: word3)` by blastLib.FULL_BBLAST_TAC, + `(2 >< 2) y = 0w: word1` by blastLib.FULL_BBLAST_TAC, + `((2 >< 2) y = 1w: word1) /\ + ((2 >< 0) y = 4w: word3)` by blastLib.FULL_BBLAST_TAC + ] + \\ simp [] + \\ blastLib.FULL_BBLAST_TAC + +val aligned_select_word_s = uprove + `aligned 2 (if b then (x: word64) else y) ==> + ((if aligned 3 (if b then x else y) then + s_extend32 w0 + else + s_extend32 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + s_extend32 (select (if b then (2 >< 2) x else (2 >< 2) y : word1) w0))` + tac + +val aligned_select_word_z = uprove + `aligned 2 (if b then (x: word64) else y) ==> + ((if aligned 3 (if b then x else y) then + z_extend32 w0 + else + z_extend32 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + z_extend32 (select (if b then (2 >< 2) x else (2 >< 2) y : word1) w0))` + tac + +val select_word = Q.prove( + `aligned 2 (a: word64) ==> + ((31 >< 0) + (select ((2 >< 2) a : word1) + (mem ((63 '' 3) a + 7w) @@ + mem ((63 '' 3) a + 6w) @@ + mem ((63 '' 3) a + 5w) @@ + mem ((63 '' 3) a + 4w) @@ + mem ((63 '' 3) a + 3w) @@ + mem ((63 '' 3) a + 2w) @@ + mem ((63 '' 3) a + 1w) @@ + mem ((63 '' 3) a )) : word64) = + mem (a + 3w) @@ mem (a + 2w) @@ mem (a + 1w) @@ (mem a : word8))`, + lrw [alignmentTheory.aligned_extract, select_def] + \\ wordsLib.Cases_on_word_value `(2 >< 2) a : word1` + >| [ + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC + ] + \\ simp [] + \\ simp_tac (srw_ss()++wordsLib.WORD_EXTRACT_ss) [] + ) + |> Q.INST [`a` |-> `if b then x else y`, `mem` |-> `s.MEM8`] + |> REWRITE_RULE [cond_rand_thms] + |> utilsLib.STRIP_UNDISCH + +val tac = + lrw [select_def, alignmentTheory.aligned_extract] + >| [ + `(2 >< 1) x = 0w: word2` by blastLib.FULL_BBLAST_TAC, + `(2 >< 1) x IN {1w; 2w; 3w: word2}` + by (wordsLib.Cases_on_word_value `(2 >< 1) x : word2` + \\ fs [] + \\ blastLib.FULL_BBLAST_TAC + ) + \\ fs [] + >| [ + `(2 >< 0) x = 2w: word3` by blastLib.FULL_BBLAST_TAC, + `(2 >< 0) x = 4w: word3` by blastLib.FULL_BBLAST_TAC, + `(2 >< 0) x = 6w: word3` by blastLib.FULL_BBLAST_TAC + ], + `(2 >< 1) y = 0w: word2` by blastLib.FULL_BBLAST_TAC, + `(2 >< 1) y IN {1w; 2w; 3w: word2}` + by (wordsLib.Cases_on_word_value `(2 >< 1) y : word2` + \\ fs [] + \\ blastLib.FULL_BBLAST_TAC + ) + \\ fs [] + >| [ + `(2 >< 0) y = 2w: word3` by blastLib.FULL_BBLAST_TAC, + `(2 >< 0) y = 4w: word3` by blastLib.FULL_BBLAST_TAC, + `(2 >< 0) y = 6w: word3` by blastLib.FULL_BBLAST_TAC + ] + ] + \\ simp [] + \\ blastLib.FULL_BBLAST_TAC + +val aligned_select_half_s = uprove + `aligned 1 (if b then (x: word64) else y) ==> + ((if aligned 3 (if b then x else y) then + s_extend16 w0 + else + s_extend16 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + s_extend16 (select (if b then (2 >< 1) x else (2 >< 1) y : word2) w0))` + tac + +val aligned_select_half_z = uprove + `aligned 1 (if b then (x: word64) else y) ==> + ((if aligned 3 (if b then x else y) then + z_extend16 w0 + else + z_extend16 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + z_extend16 (select (if b then (2 >< 1) x else (2 >< 1) y : word2) w0))` + tac + +val select_half = Q.prove( + `aligned 1 (a: word64) ==> + ((15 >< 0) + (select ((2 >< 1) a : word2) + (mem ((63 '' 3) a + 7w) @@ + mem ((63 '' 3) a + 6w) @@ + mem ((63 '' 3) a + 5w) @@ + mem ((63 '' 3) a + 4w) @@ + mem ((63 '' 3) a + 3w) @@ + mem ((63 '' 3) a + 2w) @@ + mem ((63 '' 3) a + 1w) @@ + mem ((63 '' 3) a )) : word64) = + mem (a + 1w) @@ (mem a : word8))`, + lrw [alignmentTheory.aligned_extract, select_def] + \\ wordsLib.Cases_on_word_value `(2 >< 1) a : word2` + >| [ + `(63 '' 3) a = a - 6w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 2w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC + ] + \\ simp [] + \\ simp_tac (srw_ss()++wordsLib.WORD_EXTRACT_ss) [] + ) + |> Q.INST [`a` |-> `if b then x else y`, `mem` |-> `s.MEM8`] + |> REWRITE_RULE [cond_rand_thms] + |> utilsLib.STRIP_UNDISCH + +val tac = + lrw [select_def, alignmentTheory.aligned_extract] + \\ fs [] + >| [ + `(2 >< 0) x : word3 = 0w` by blastLib.FULL_BBLAST_TAC, + `(2 >< 0) y : word3 = 0w` by blastLib.FULL_BBLAST_TAC, + wordsLib.Cases_on_word_value `(2 >< 0) x : word3`, + wordsLib.Cases_on_word_value `(2 >< 0) y : word3` + ] + \\ simp [] + \\ blastLib.BBLAST_TAC + +val aligned_select_byte_s = Q.prove( + `(if aligned 3 (if b then (x: word64) else y) then + s_extend8 w0 + else + s_extend8 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + s_extend8 (select (if b then (2 >< 0) x else (2 >< 0) y : word3) w0)`, + tac + ) + +val aligned_select_byte_z = Q.prove( + `(if aligned 3 (if b then (x: word64) else y) then + z_extend8 w0 + else + z_extend8 + ((63 >< 0) + (((w1: word64) @@ w0) >> + (w2n (if b then (2 >< 0) x else (2 >< 0) y : word3) * 8)))) = + z_extend8 (select (if b then (2 >< 0) x else (2 >< 0) y : word3) w0)`, + tac + ) + +val select_byte = Q.prove( + `((7 >< 0) + (select ((2 >< 0) a : word3) + (mem ((63 '' 3) a + 7w) @@ + mem ((63 '' 3) a + 6w) @@ + mem ((63 '' 3) a + 5w) @@ + mem ((63 '' 3) a + 4w) @@ + mem ((63 '' 3) a + 3w) @@ + mem ((63 '' 3) a + 2w) @@ + mem ((63 '' 3) a + 1w) @@ + mem ((63 '' 3) a )) : word64) = + ((mem: word64 -> word8) a))`, + lrw [alignmentTheory.aligned_extract, select_def] + \\ wordsLib.Cases_on_word_value `(2 >< 0) a : word3` + >| [ + `(63 '' 3) a = a - 7w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 6w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 5w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 3w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 2w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 1w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC + ] + \\ simp [] + \\ simp_tac (srw_ss()++wordsLib.WORD_EXTRACT_ss) [] + ) + |> Q.INST [`a` |-> `if b then x else y`, `mem` |-> `s.MEM8`] + |> REWRITE_RULE [cond_rand_thms] + +val byte_access = Q.prove( + `w2n ((2 >< 0) a : word3) + 1 <= 8`, + wordsLib.n2w_INTRO_TAC 4 + \\ blastLib.FULL_BBLAST_TAC + ) + +val aligned1_aligned3 = uprove + `aligned 1 (a: word64) ==> (aligned 3 a = ((2 >< 1) a = 0w: word2))` + (simp [alignmentTheory.aligned_extract] \\ blastLib.BBLAST_TAC) + +val aligned1_aligned3b = uprove + `aligned 1 (a: word64) ==> w2n ((2 >< 0) a : word3) + 2 <= 8` + ( + rw [alignmentTheory.aligned_extract] + \\ wordsLib.n2w_INTRO_TAC 4 + \\ blastLib.FULL_BBLAST_TAC + ) + +val aligned2_aligned3 = uprove + `aligned 2 (a: word64) ==> (aligned 3 a = ((2 >< 2) a = 0w: word1))` + (simp [alignmentTheory.aligned_extract] \\ blastLib.BBLAST_TAC) + +val aligned2_aligned3b = uprove + `aligned 2 (a: word64) ==> w2n ((2 >< 0) a : word3) + 4 <= 8` + ( + rw [alignmentTheory.aligned_extract] + \\ wordsLib.n2w_INTRO_TAC 4 + \\ blastLib.FULL_BBLAST_TAC + ) + +val w = + List.tabulate (8, fn i => Term.mk_var ("b" ^ Int.toString i, ``:word8``)) +val w = List.foldl wordsSyntax.mk_word_concat (hd w) (tl w) + +val extract_thms = Q.prove( + `((7 >< 0 ) ^w = b0) /\ ((15 >< 8 ) ^w = b1) /\ ((23 >< 16) ^w = b2) /\ + ((31 >< 24) ^w = b3) /\ ((39 >< 32) ^w = b4) /\ ((47 >< 40) ^w = b5) /\ + ((55 >< 48) ^w = b6) /\ ((63 >< 56) ^w = b7)`, + simp_tac (std_ss++wordsLib.SIZES_ss++wordsLib.WORD_EXTRACT_ss) + [wordsTheory.SHIFT_ZERO, wordsTheory.WORD_OR_CLAUSES] + ) + +val not1 = uprove + `a <> 1w: word2 ==> + ((if a = 0w then x1 + else if a = 2w then x2 + else if a = 3w then x3 + else x4) = + (if a = 0w then x1 + else if a = 2w then x2 + else x3))` + (rw [] \\ blastLib.FULL_BBLAST_TAC) + +val extract_over_add = + wordsTheory.WORD_EXTRACT_OVER_ADD + |> Q.ISPECL [`a: word64`, `b: word64`, `31n`] + |> INST_TYPE [Type.beta |-> ``:32``] + |> SIMP_RULE (srw_ss()) [] + |> GSYM + +val jal = uprove + `aligned 2 (pc: word64) /\ ~word_lsb (imm: word20) ==> + aligned 2 (pc + sw2sw imm << 1)` + ( + simp [alignmentTheory.aligned_extract] \\ blastLib.BBLAST_TAC + ) + +val jalr = uprove + `(b \/ aligned 2 x) /\ ~(imm: word12 ' 1) ==> + aligned 2 (if b then sw2sw imm && 0xFFFFFFFFFFFFFFFEw : word64 + else x + sw2sw imm && 0xFFFFFFFFFFFFFFFEw)` + ( + rw [alignmentTheory.aligned_extract] + \\ blastLib.FULL_BBLAST_TAC + ) + +val Decode_IMP_DecodeAny = store_thm("Decode_IMP_DecodeAny", + ``(Decode w = i) ==> (DecodeAny (Word w) = i)``, + fs [DecodeAny_def]); + +val DecodeRVC_IMP_DecodeAny = store_thm("DecodeRVC_IMP_DecodeAny", + ``(DecodeRVC h = i) ==> (DecodeAny (Half h) = i)``, + fs [DecodeAny_def]); + +val avoid_signalAddressException = store_thm("avoid_signalAddressException", + ``~b ==> ((if b then signalAddressException t u else s) = s)``, + fs []); + +val word_bit_add_lsl_simp = store_thm("word_bit_add_lsl_simp", + ``word_bit 0 (x + w << 1) = word_bit 0 (x:word64)``, + blastLib.BBLAST_TAC); + +(* ------------------------------------------------------------------------ + Evaluation setup + ------------------------------------------------------------------------ *) + +val s = ``s:riscv_state`` +val rd0 = ``rd = 0w: word5`` +val bare = ``(^s.c_MCSR ^s.procID).mstatus.VM = 0w`` +val archbase = ``(^s.c_MCSR ^s.procID).mcpuid.ArchBase`` +val shift = ``~((^archbase = 0w) /\ word_bit 5n (imm: word6))`` +val aligned = ``aligned 2 (^s.c_PC ^s.procID)`` +val aligned_d = + ``aligned 3 (if rs1 = 0w then sw2sw offs + else ^s.c_gpr ^s.procID rs1 + sw2sw (offs:word12))`` + +local + val cond_updates = utilsLib.mk_cond_update_thms [``:riscv_state``] + val datatype_rwts = + utilsLib.datatype_rewrites true "riscv" + ["riscv_state", "VM_Mode", "Architecture"] + fun riscv_thms thms = + thms @ cond_updates @ datatype_rwts @ + [wordsTheory.WORD_EXTRACT_ZERO2, wordsTheory.ZERO_SHIFT, + wordsTheory.WORD_ADD_0, wordsTheory.WORD_MULT_CLAUSES, + wordsTheory.WORD_AND_CLAUSES, wordsTheory.WORD_OR_CLAUSES, + wordsTheory.WORD_XOR_CLAUSES, wordsTheory.w2w_0, wordsTheory.sw2sw_0, + ifTF, cond_lem1, extract_over_add, cond_rand_shift, cond_rand_thms + ] +in + fun step_conv b = + utilsLib.setStepConv + (if b then + Conv.DEPTH_CONV wordsLib.SIZES_CONV + THENC utilsLib.WGROUND_CONV + else + ALL_CONV) + val ev = utilsLib.STEP (riscv_thms, s) + fun EV a b c d = hd (ev a b c d) +end + +local + val word_eq_ss = + simpLib.std_conv_ss + {name = "word_eq", conv = wordsLib.word_EQ_CONV, + pats = [``n2w a = n2w b: word64``]} +in + val store_tac = + asm_simp_tac (std_ss++wordsLib.WORD_ss) + [GSYM wordsTheory.WORD_EXTRACT_OVER_BITWISE, extract_thms] + \\ simp_tac (std_ss++wordsLib.SIZES_ss++wordsLib.WORD_EXTRACT_ss) + [wordsTheory.SHIFT_ZERO, wordsTheory.WORD_OR_CLAUSES] + \\ simp_tac + (std_ss++wordsLib.WORD_ARITH_ss++wordsLib.WORD_CANCEL_ss++word_eq_ss) + [updateTheory.UPDATE_APPLY_IMP_ID, combinTheory.UPDATE_APPLY] +end + +(* ------------------------------------------------------------------------ + Architecture Rewrites + ------------------------------------------------------------------------ *) + +val () = step_conv false + +val translateAddr = EV + [translateAddr_def, MCSR_def, vmType_def, pairTheory.pair_case_thm] + [[bare]] [] + ``translateAddr (vPC, ft, ac)`` + +val in32BitMode = EV + [in32BitMode_def, curArch_def, MCSR_def, architecture_def, not1] [] [] + ``in32BitMode()`` + +val PC = EV [PC_def] [] [] ``PC`` + +val Skip = save_thm("Skip",EV [Skip_def,boolify8_def] [] [] ``Skip``); + +val rawReadInst = EV + [rawReadInst_def, MEM_def, address_align, read_word] [] [] + ``rawReadInst a`` + +val rawReadData = EV + [rawReadData_def, aligned3, MEM_def, address_align, address_align2] + [] [] + ``rawReadData a`` + +val branchTo = EV + [branchTo_def, write'NextFetch_def] [] [] + ``branchTo newPC`` + +val GPR = EV [GPR_def, gpr_def] [] [] ``GPR n`` + +val write'GPR0 = + ev [write'GPR_def] [[``d = 0w:word5``]] [] + ``write'GPR (n, d)`` |> hd + +val write'GPR = + ev [write'GPR_def, write'gpr_def] [[``d <> 0w:word5``]] [] + ``write'GPR (n, d)`` |> hd + +val update_pc = Theory.save_thm("update_pc", + EV [update_pc_def, write'PC_def] [] [] ``update_pc v``) + +val Fetch = + EV [Fetch_def, PC, translateAddr, rawReadInst, boolify8_def, + write'Skip_def] [[aligned]] [] + ``Fetch`` + +val Fetch32 = store_thm("Fetch32", + ``!xs x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF + y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 yA yB yC yD yE yF. + (xs = [y0; y1; y2; y3; y4; y5; y6; y7; y8; y9; yA; yB; yC; yD; yE; yF; + x0; x1; x2; x3; x4; x5; x6; x7; x8; x9; xA; xB; xC; xD; xE; xF]) /\ + ((s.c_MCSR s.procID).mstatus.VM = 0w) ∧ + (s.MEM8 (s.c_PC s.procID + 3w) = v2w [y0; y1; y2; y3; y4; y5; y6; y7]) ∧ + (s.MEM8 (s.c_PC s.procID + 2w) = v2w [y8; y9; yA; yB; yC; yD; yE; yF]) ∧ + (s.MEM8 (s.c_PC s.procID + 1w) = v2w [x0; x1; x2; x3; x4; x5; x6; x7]) ∧ + (s.MEM8 (s.c_PC s.procID) = v2w [x8; x9; xA; xB; xC; xD; xE; xF]) ∧ + xE ∧ xF ⇒ + (Fetch s = + (Word (v2w xs), s with c_Skip := (s.procID =+ 4w) s.c_Skip))``, + simp [Fetch |> DISCH_ALL] \\ rw [] \\ blastLib.BBLAST_TAC); + +val Fetch16 = store_thm("Fetch16", + ``!xs x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF. + (xs = [x0; x1; x2; x3; x4; x5; x6; x7; x8; x9; xA; xB; xC; xD; xE; xF]) /\ + ((s.c_MCSR s.procID).mstatus.VM = 0w) ∧ + (s.MEM8 (s.c_PC s.procID + 1w) = v2w [x0; x1; x2; x3; x4; x5; x6; x7]) ∧ + (s.MEM8 (s.c_PC s.procID) = v2w [x8; x9; xA; xB; xC; xD; xE; xF]) ∧ + ~(xE ∧ xF) ⇒ + (Fetch s = + (Half (v2w xs), s with c_Skip := (s.procID =+ 2w) s.c_Skip))``, + simp [Fetch |> DISCH_ALL] \\ rw [] \\ blastLib.BBLAST_TAC); + +(* ------------------------------------------------------------------------ + Memory Store Rewrites + ------------------------------------------------------------------------ *) + +val () = step_conv true + +val write'MEM = EV [write'MEM_def] [] [] ``write'MEM (d, a)`` + +fun write_data_ev l1 l2 = + EV ([rawWriteData_def, aligned3, MEM_def, write'MEM, address_align] @ l1) l2 + [] + +val rawWriteData8 = + write_data_ev [address_aligned3] [[``aligned 3 (a: word64)``]] + ``rawWriteData (a, d, 8)`` + +fun get_mem8 thm = + thm |> utilsLib.rhsc + |> boolSyntax.rator + |> boolSyntax.rand + |> boolSyntax.rand + +val rawWriteData4 = write_data_ev [aligned2_aligned3, aligned2_aligned3b] [] + ``rawWriteData (a, d, 4)`` + +val tm = get_mem8 rawWriteData4 + +val thm = uprove + `aligned 2 a ==> + (^tm = (a =+ (7 >< 0) d) ((a + 1w =+ (15 >< 8) d) + ((a + 2w =+ (23 >< 16) d) ((a + 3w =+ (31 >< 24) d) s.MEM8))))` + ( + rw [alignmentTheory.aligned_extract] + \\ qabbrev_tac `mem = s.MEM8` + >- (`(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC \\ store_tac) + \\ `(2 >< 0) a : word3 = 4w: word3` by blastLib.FULL_BBLAST_TAC + \\ `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC + \\ store_tac + ) + +val rawWriteData4 = utilsLib.INST_REWRITE_RULE [thm] rawWriteData4 + +val rawWriteData2 = write_data_ev [aligned1_aligned3, aligned1_aligned3b] [] + ``rawWriteData (a, d, 2)`` + +val tm = get_mem8 rawWriteData2 + +val thm = uprove + `aligned 1 a ==> (^tm = (a =+ (7 >< 0) d) ((a + 1w =+ (15 >< 8) d) s.MEM8))` + ( + rw [alignmentTheory.aligned_extract] + \\ qabbrev_tac `mem = s.MEM8` + >- (`(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC \\ store_tac) + \\ `(2 >< 0) a : word3 IN {2w; 4w; 6w: word3}` + by (simp [] \\ blastLib.FULL_BBLAST_TAC) + \\ fs [] + >| [ + `(63 '' 3) a = a - 2w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 6w` by blastLib.FULL_BBLAST_TAC + ] + \\ store_tac + ) + +val rawWriteData2 = utilsLib.INST_REWRITE_RULE [thm] rawWriteData2 + +val rawWriteData1 = write_data_ev [byte_access] [] ``rawWriteData (a, d, 1)`` + +val tm = get_mem8 rawWriteData1 + +val thm = Q.prove( + `^tm = (a =+ (7 >< 0) d) s.MEM8`, + rw [alignmentTheory.aligned_extract] + \\ qabbrev_tac `mem = s.MEM8` + >- (`(63 '' 3) a = a` by blastLib.FULL_BBLAST_TAC \\ store_tac) + \\ wordsLib.Cases_on_word_value `(2 >< 0) a: word3` + \\ fs [] + >| [ + `(63 '' 3) a = a - 7w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 6w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 5w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 4w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 3w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 2w` by blastLib.FULL_BBLAST_TAC, + `(63 '' 3) a = a - 1w` by blastLib.FULL_BBLAST_TAC, + blastLib.FULL_BBLAST_TAC + ] + \\ store_tac + ) + +val rawWriteData1 = REWRITE_RULE [thm] rawWriteData1 + +(* ------------------------------------------------------------------------ + Instruction Rewrites + ------------------------------------------------------------------------ *) + +local + val l = + [GPR, in32BitMode, PC, wordsTheory.word_len_def, + branchTo, translateAddr, jal, jalr, aligned2, + aligned_select_word_s, aligned_select_word_z, select_word, + aligned_select_half_s, aligned_select_half_z, select_half, + aligned_select_byte_s, aligned_select_byte_z, select_byte, + rawReadData, rawWriteData8, rawWriteData4, rawWriteData2, rawWriteData1] + val hyp_eq_rule = + utilsLib.ALL_HYP_CONV_RULE (Conv.DEPTH_CONV wordsLib.word_EQ_CONV) +in + val () = utilsLib.reset_thms() + fun class args avoid n = + let + val name = "dfn'" ^ n + val read = if Lib.mem n ["LD"] then [address_aligned3] else [] + val (write, n) = + if List.exists (tmem rd0) avoid then + ([write'GPR0], n ^ "_NOP") + else + ([write'GPR], n) + val thms = DB.fetch "riscv" (name ^ "_def") :: write @ read + in + case ev (thms @ l) avoid [] (Parse.Term ([QUOTE name] @ args)) of + [th] => utilsLib.save_thms n [hyp_eq_rule th] + | _ => raise ERR "class" ("more than one theorem" ^ n) + end +end + +fun class_rd0 args avoid n = + let + val f = class args + in + (f avoid n, + f (case avoid of + [] => [[rd0]] + | [l] => [rd0 :: l] + | _ => raise ERR "" "") n) + end + +val arithi = class_rd0 `(rd, rs1, imm)` + +val ADDI = arithi [] "ADDI" +val ADDIW = arithi [[``^archbase <> 0w``]] "ADDIW" +val SLTI = arithi [] "SLTI" +val SLTIU = arithi [] "SLTIU" +val ANDI = arithi [] "ANDI" +val ORI = arithi [] "ORI" +val XORI = arithi [] "XORI" +val SLLI = arithi [[shift]] "SLLI" +val SRLI = arithi [[shift]] "SRLI" +val SRAI = arithi [[shift]] "SRAI" +val SLLIW = arithi [[``^archbase <> 0w``]] "SLLIW" +val SRLIW = arithi [[``^archbase <> 0w``]] "SRLIW" +val SRAIW = arithi [[``^archbase <> 0w``]] "SRAIW" + +val arithi = class_rd0 `(rd, imm)` [] + +val LUI = arithi "LUI" +val AUIPC = arithi "AUIPC" + +val arithr = class_rd0 `(rd, rs1, rs2)` + +val ADD = arithr [] "ADD" +val ADDW = arithr [[``^archbase <> 0w``]] "ADDW" +val SUB = arithr [] "SUB" +val SUBW = arithr [[``^archbase <> 0w``]] "SUBW" +val SLT = arithr [] "SLT" +val SLTU = arithr [] "SLTU" +val AND = arithr [] "AND" +val OR = arithr [] "OR" +val XOR = arithr [] "XOR" +val SLL = arithr [] "SLL" +val SRL = arithr [] "SRL" +val SRA = arithr [] "SRA" +val SLLW = arithr [[``^archbase <> 0w``]] "SLLW" +val SRLW = arithr [[``^archbase <> 0w``]] "SRLW" +val SRAW = arithr [[``^archbase <> 0w``]] "SRAW" + +val MUL = arithr [] "MUL" +val MULH = arithr [] "MULH" +val MULHU = arithr [] "MULHU" +val MULHSU = arithr [] "MULHSU" +val MULW = arithr [[``^archbase <> 0w``]] "MULW" +val DIV = arithr [] "DIV" +val REM = arithr [] "REM" +val DIVU = arithr [] "DIVU" +val REMU = arithr [] "REMU" +val DIVW = arithr [[``^archbase <> 0w``]] "DIVW" +val REMW = arithr [[``^archbase <> 0w``]] "REMW" +val DIVUW = arithr [[``^archbase <> 0w``]] "DIVUW" +val REMUW = arithr [[``^archbase <> 0w``]] "REMUW" + +val JAL = class_rd0 `(rd, imm)` [] "JAL" +val JALR = class_rd0 `(rd, rs1, imm)` [] "JALR" + +val cbranch = class `(rs1, rs2, offs)` [] + +val BEQ = cbranch "BEQ" +val BNE = cbranch "BNE" +val BLT = cbranch "BLT" +val BLTU = cbranch "BLTU" +val BGE = cbranch "BGE" +val BGEU = cbranch "BGEU" + +val load = class_rd0 `(rd, rs1, offs)` + +val LD = load [[``^archbase <> 0w``, aligned_d]] "LD" +val LW = load [] "LW" +val LH = load [] "LH" +val LB = load [] "LB" +val LWU = load [[``^archbase <> 0w``]] "LWU" +val LHU = load [[``^archbase <> 0w``]] "LHU" +val LBU = load [[``^archbase <> 0w``]] "LBU" + +val store = class `(rs1, rs2, offs)` + +val SD = store [[``^archbase <> 0w``, aligned_d]] "SD" +val SW = store [] "SW" +val SH = store [] "SH" +val SB = store [] "SB" + +(* ------------------------------------------------------------------------ *) + +val () = ( Theory.delete_const "select" + ; utilsLib.adjoin_thms () + ; export_theory () + ) diff --git a/src/theory/tools/lifter/Holmakefile b/src/theory/tools/lifter/Holmakefile index 0e856ccd6..18705a0f2 100644 --- a/src/theory/tools/lifter/Holmakefile +++ b/src/theory/tools/lifter/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/extra \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/src/tools/backlifter/Holmakefile b/src/tools/backlifter/Holmakefile index ff28fe5e6..1d0dd0027 100644 --- a/src/tools/backlifter/Holmakefile +++ b/src/tools/backlifter/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/src/tools/comp/Holmakefile b/src/tools/comp/Holmakefile index 7d1691881..6fbee76f1 100644 --- a/src/tools/comp/Holmakefile +++ b/src/tools/comp/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared \ $(HOLBADIR)/src/theory/program_logic \ $(HOLBADIR)/src/theory/bir \ diff --git a/src/tools/lifter/Holmakefile b/src/tools/lifter/Holmakefile index 244f7e89c..c4d981fab 100644 --- a/src/tools/lifter/Holmakefile +++ b/src/tools/lifter/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/extra \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/src/tools/scamv/symbexec/examples/minimal/Holmakefile b/src/tools/scamv/symbexec/examples/minimal/Holmakefile index 025cb0424..dcecc6070 100644 --- a/src/tools/scamv/symbexec/examples/minimal/Holmakefile +++ b/src/tools/scamv/symbexec/examples/minimal/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ $(HOLBADIR)/src/theory/tools/lifter \ diff --git a/src/tools/wp/Holmakefile b/src/tools/wp/Holmakefile index 8175f7e0a..2d4c6c1bc 100644 --- a/src/tools/wp/Holmakefile +++ b/src/tools/wp/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/shared/smt \ $(HOLBADIR)/src/theory/bir \ $(HOLBADIR)/src/theory/bir-support \ diff --git a/src/tools/wp/benchmark/binaries/Holmakefile b/src/tools/wp/benchmark/binaries/Holmakefile index c20b24f5b..30c5561aa 100644 --- a/src/tools/wp/benchmark/binaries/Holmakefile +++ b/src/tools/wp/benchmark/binaries/Holmakefile @@ -3,8 +3,8 @@ INCLUDES = $(HOLDIR)/examples/l3-machine-code/common \ $(HOLDIR)/examples/l3-machine-code/arm8/step \ $(HOLDIR)/examples/l3-machine-code/m0/model \ $(HOLDIR)/examples/l3-machine-code/m0/step \ - $(HOLDIR)/examples/l3-machine-code/riscv/model \ - $(HOLDIR)/examples/l3-machine-code/riscv/step \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/model \ + $(HOLBADIR)/src/shared/l3-machine-code/riscv/step \ $(HOLBADIR)/src/tools/lifter all: $(DEFAULT_TARGETS) From caf07c3fbd895b8a1aae0a807474926f983382eb Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Thu, 5 Dec 2024 19:13:04 +0100 Subject: [PATCH 11/14] Added the capability of executing CSR instructions to riscv_stepLib --- .../riscv/step/riscv_stepLib.sml | 41 ++++++- .../riscv/step/riscv_stepScript.sml | 74 ++++++++++++- .../riscv/step/riscv_stepSimps.sig | 12 ++ .../riscv/step/riscv_stepSimps.sml | 103 ++++++++++++++++++ 4 files changed, 224 insertions(+), 6 deletions(-) create mode 100644 src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sig create mode 100644 src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sml diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml index 853bebe76..72879d044 100644 --- a/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepLib.sml @@ -7,6 +7,7 @@ struct open HolKernel boolLib bossLib open blastLib riscvTheory riscv_stepTheory +open riscv_stepSimps structure Parse = struct open Parse @@ -193,7 +194,11 @@ val riscv_decodes = ("LD", "_________________FTT_____FFFFFTT"), ("LBU", "_________________TFF_____FFFFFTT"), ("LHU", "_________________TFT_____FFFFFTT"), - ("LWU", "_________________TTF_____FFFFFTT") + ("LWU", "_________________TTF_____FFFFFTT"), + (* CSR instructions *) + ("CSRRW", "_________________FFT_____TTTFFTT"), + ("CSRRS", "_________________FTF_____TTTFFTT"), + ("CSRRC", "_________________FTT_____TTTFFTT") ] in l @ List.map make_nop l @ @@ -305,6 +310,19 @@ local val MP_Next_c = next riscv_stepTheory.NextRISCV_cond_branch val MP_Next_b = next riscv_stepTheory.NextRISCV_branch val Run_CONV = utilsLib.Run_CONV ("riscv", s) o utilsLib.rhsc + fun tidy_up_system_inst thm = + let + (* Bit-blast effects of privilege checking *) + (* TODO: This could be used to clean up before BBLAST-ing *) + (* val thm = SIMP_RULE (std_ss++wordsLib.WORD_ss++bitstringLib.v2w_n2w_ss) [] thm *) + val thm2 = blastLib.BBLAST_RULE thm + (* Rewrite effects of CSRMap *) + val thm3 = CSRMap_match_rule thm2 + (* Rewrite effects of writeCSR *) + val thm4 = writeCSR_match_rule thm3 + in + thm4 + end fun tidy_up_signalAddressException th = let val rw = UNDISCH avoid_signalAddressException @@ -320,14 +338,29 @@ local in fun riscv_step v = let +(* + val v = bitstringSyntax.bitstring_of_hexstring "340110F3" (* CSRRW *) + val v = bitstringSyntax.bitstring_of_hexstring "340120F3" (* CSRRS *) + val v = bitstringSyntax.bitstring_of_hexstring "340130F3" (* CSRRC *) + + Example of instruction working: + val v = bitstringSyntax.bitstring_of_hexstring "00E10423" +*) val thm1 = fetch v val thm2 = riscv_decode v |> SIMP_RULE std_ss [] val new_s = thm1 |> concl |> rand |> rand val thm3 = fetch_inst (Drule.SPEC_ALL (Run_CONV thm2)) |> INST [s |-> new_s] val tm = utilsLib.rhsc thm3 - val ethm = run tm - val ethm = tidy_up_signalAddressException ethm - val thm4 = Conv.RIGHT_CONV_RULE (Conv.REWR_CONV ethm) thm3 + val ethm1 = + let + val ethm = run tm + in + if (is_System o rhs o concl) thm2 + then tidy_up_system_inst ethm + else ethm + end + val ethm2 = tidy_up_signalAddressException ethm1 + val thm4 = Conv.RIGHT_CONV_RULE (Conv.REWR_CONV ethm2) thm3 val thm5 = proj_exception thm4 val thm6 = proj_NextFetch_procID thm4 val thm = Drule.LIST_CONJ [thm1, thm2, thm4, thm5, thm6] diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml b/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml index 45c99d9cc..758626c60 100644 --- a/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepScript.sml @@ -7,6 +7,7 @@ open HolKernel boolLib bossLib open utilsLib open wordsLib blastLib alignmentTheory open riscvTheory +open riscv_stepSimps val () = Theory.new_theory "riscv_step" val _ = ParseExtras.temp_loose_equality() @@ -550,6 +551,7 @@ val s = ``s:riscv_state`` val rd0 = ``rd = 0w: word5`` val bare = ``(^s.c_MCSR ^s.procID).mstatus.VM = 0w`` val archbase = ``(^s.c_MCSR ^s.procID).mcpuid.ArchBase`` +val privilege_level = ``(^s.c_MCSR ^s.procID).mstatus.MPRV`` val shift = ``~((^archbase = 0w) /\ word_bit 5n (imm: word6))`` val aligned = ``aligned 2 (^s.c_PC ^s.procID)`` val aligned_d = @@ -560,7 +562,7 @@ local val cond_updates = utilsLib.mk_cond_update_thms [``:riscv_state``] val datatype_rwts = utilsLib.datatype_rewrites true "riscv" - ["riscv_state", "VM_Mode", "Architecture"] + ["riscv_state", "VM_Mode", "Architecture", "accessType", "Privilege"] fun riscv_thms thms = thms @ cond_updates @ datatype_rwts @ [wordsTheory.WORD_EXTRACT_ZERO2, wordsTheory.ZERO_SHIFT, @@ -765,6 +767,56 @@ val thm = Q.prove( val rawWriteData1 = REWRITE_RULE [thm] rawWriteData1 + +(* ------------------------------------------------------------------------ + CSR Rewrites + ------------------------------------------------------------------------ *) + + +val CSR = EV [CSR_def] [] [] ``CSR n`` + +val csrRW = EV [csrRW_def] [] [] ``csrRW w`` + +val csrPR = EV [csrPR_def] [] [] ``csrPR w`` + +val CSRMap = EV [CSRMap_def] [] [] ``CSRMap n s`` + +val checkCSROp = EV [checkCSROp_def, is_CSR_defined_def] [] [] ``checkCSROp (csr, rs1, a)`` + +val check_CSR_access = EV [check_CSR_access_def] [] [] ``check_CSR_access (rw,pr,p,a)`` + +val riscv_privilege_cases = store_thm("riscv_privilege_cases", +``!w1 w2 w3 w4 s. + (case + if (s.c_MCSR s.procID).mstatus.MPRV = 0w then User + else if (s.c_MCSR s.procID).mstatus.MPRV = 1w then Supervisor + else if (s.c_MCSR s.procID).mstatus.MPRV = 2w then Hypervisor + else if (s.c_MCSR s.procID).mstatus.MPRV = 3w then Machine + else ARB + of + User => w1 + | Supervisor => w2 + | Hypervisor => w3 + | Machine => w4) = + (if (s.c_MCSR s.procID).mstatus.MPRV = 0w then w1 + else if (s.c_MCSR s.procID).mstatus.MPRV = 1w then w2 + else if (s.c_MCSR s.procID).mstatus.MPRV = 2w then w3 + else w4 +) +``, + +REPEAT STRIP_TAC >> +wordsLib.Cases_on_word_value `(s.c_MCSR s.procID).mstatus.MPRV` >> ( + FULL_SIMP_TAC (riscv_ss++wordsLib.WORD_ss) [] +) +); + +(* privLevel and curPrivilege baked together *) +val privLevel = EV [privLevel_def, curPrivilege_def, privilege_def, MCSR_def, riscv_privilege_cases] [] [] ``privLevel (curPrivilege () s)`` + +val writeCSR = ev [writeCSR_def, write'CSR_def, write'Delta_def, Delta_def] [] [] ``writeCSR (csr, v)`` |> hd + + (* ------------------------------------------------------------------------ Instruction Rewrites ------------------------------------------------------------------------ *) @@ -790,7 +842,12 @@ in ([write'GPR0], n ^ "_NOP") else ([write'GPR], n) - val thms = DB.fetch "riscv" (name ^ "_def") :: write @ read + (* These rewrites should be done for all CSR instructions *) + val csr = + if Lib.mem n ["CSRRW", "CSRRS", "CSRRC", "CSRRWI", "CSRRSI", "CSRRCI"] + then [checkCSROp, check_CSR_access, CSR, privLevel, csrRW, csrPR] + else [] + val thms = DB.fetch "riscv" (name ^ "_def") :: write @ read @ csr in case ev (thms @ l) avoid [] (Parse.Term ([QUOTE name] @ args)) of [th] => utilsLib.save_thms n [hyp_eq_rule th] @@ -891,6 +948,19 @@ val SW = store [] "SW" val SH = store [] "SH" val SB = store [] "SB" +val csrinst = class `(rd, rs1, csr)` + +(* TODO: How to handle privilege level? Currently, machine mode is always assumed *) +val CSRRW_M = csrinst [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRW" +val CSRRS_M = csrinst [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRS" +val CSRRC_M = csrinst [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRC" + +val csrinsti = class `(rd, imm, csr)` + +val CSRRWI_M = csrinsti [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRWI" +val CSRRSI_M = csrinsti [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRSI" +val CSRRCI_M = csrinsti [[``^privilege_level = 3w``, ``^archbase <> 0w``]] "CSRRCI" + (* ------------------------------------------------------------------------ *) val () = ( Theory.delete_const "select" diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sig b/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sig new file mode 100644 index 000000000..4ce6b6826 --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sig @@ -0,0 +1,12 @@ +signature riscv_stepSimps = +sig + include Abbrev + + (* Simplifies some RISC-V datatype stuff *) + val riscv_ss : simpLib.simpset + + val is_System : term -> bool + + val writeCSR_match_rule : thm -> thm + val CSRMap_match_rule : thm -> thm +end diff --git a/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sml b/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sml new file mode 100644 index 000000000..263ebbf6e --- /dev/null +++ b/src/shared/l3-machine-code/riscv/step/riscv_stepSimps.sml @@ -0,0 +1,103 @@ +structure riscv_stepSimps :> riscv_stepSimps = +struct + +open HolKernel boolLib liteLib simpLib Parse bossLib; +open riscvTheory; + +val cond_updates = utilsLib.mk_cond_update_thms [``:riscv_state``] +val datatype_rwts = + utilsLib.datatype_rewrites true "riscv" + ["riscv_state", "VM_Mode", "Architecture", "accessType", "Privilege"] + +val riscv_ss = (std_ss++(rewrites (cond_updates@datatype_rwts))) + + + +(* Syntax functions for writeCSR *) +val (writeCSR_tm, mk_writeCSR, dest_writeCSR, is_writeCSR) = syntax_fns2 "riscv" "writeCSR" + +(* Syntax functions for CSRMap *) +val (CSRMap_tm, mk_CSRMap, dest_CSRMap, is_CSRMap) = syntax_fns2 "riscv" "CSRMap" + +(* Syntax functions for System *) +val (System_tm, mk_System, dest_System, is_System) = syntax_fns1 "riscv" "System" + +(* Filters out duplicate sub-terms. *) +local +fun filter_equal_terms' [] filtered_list = filtered_list + | filter_equal_terms' (h::t) [] = filter_equal_terms' t [h] + | filter_equal_terms' (h::t) filtered_list = + if isSome (List.find (term_eq h) filtered_list) + then filter_equal_terms' t filtered_list + else filter_equal_terms' t (h::filtered_list) +in +fun filter_equal_terms tm_list = filter_equal_terms' tm_list [] +end +; + +fun get_CSRMap_exps_from_tm tm = filter_equal_terms (find_terms (fn t => is_CSRMap t) tm) +fun get_CSRMap_exps thm = get_CSRMap_exps_from_tm (concl thm) + +fun get_writeCSR_exps thm = filter_equal_terms (find_terms (fn t => is_writeCSR t) (concl thm)) + +val CSRMap_conv = ( + (SIMP_CONV (bool_ss++bitstringLib.v2w_n2w_ss) + [CSRMap_def] + ) THENC + wordsLib.WORD_CONV THENC + SIMP_CONV riscv_ss [] + ) + +fun CSRMap_match_rule_conv tm = + let + val CSRMap_exps = get_CSRMap_exps_from_tm tm + val CSRMap_rewrs = map CSRMap_conv CSRMap_exps + in + SIMP_CONV riscv_ss CSRMap_rewrs tm + end +; + +val writeCSR_conv = ( + (SIMP_CONV (bool_ss++bitstringLib.v2w_n2w_ss) + [writeCSR_def, write'CSR_def, write'CSRMap_def] + ) THENC + (* TODO: Treat CSRMap using matching in a nested way here? + * Tests seem to imply not needed... *) +(* + wordsLib.WORD_CONV THENC ( + SIMP_CONV riscv_ss [LET_DEF, Delta_def, write'Delta_def, + CSR_def] + ) THENC + CSRMap_match_rule_conv THENC + wordsLib.WORD_CONV THENC ( + SIMP_CONV riscv_ss [] + ) +*) + wordsLib.WORD_CONV THENC ( + SIMP_CONV riscv_ss [LET_DEF, Delta_def, write'Delta_def, + CSR_def, CSRMap_def] + ) THENC + wordsLib.WORD_CONV THENC ( + SIMP_CONV riscv_ss [] + ) +) + +fun CSRMap_match_rule thm = + let + val CSRMap_exps = get_CSRMap_exps thm + val CSRMap_rewrs = map CSRMap_conv CSRMap_exps + in + SIMP_RULE riscv_ss CSRMap_rewrs thm + end +; + +fun writeCSR_match_rule thm = + let + val writeCSR_exps = get_writeCSR_exps thm + val writeCSR_rewrs = map writeCSR_conv writeCSR_exps + in + SIMP_RULE riscv_ss writeCSR_rewrs thm + end +; + +end From 9cc7ffb9994834a2b457dae84b603735cfda8a39 Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Thu, 5 Dec 2024 19:16:48 +0100 Subject: [PATCH 12/14] Changed CSR addresses and names in the RISC-V L3 model to agree with the latest version of the ISA manual --- .../l3-machine-code/riscv/model/riscvLib.sig | 2 +- .../l3-machine-code/riscv/model/riscvLib.sml | 2 +- .../riscv/model/riscvScript.sml | 43 ++++++++++--------- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/src/shared/l3-machine-code/riscv/model/riscvLib.sig b/src/shared/l3-machine-code/riscv/model/riscvLib.sig index 6e7269db2..c074c2bce 100644 --- a/src/shared/l3-machine-code/riscv/model/riscvLib.sig +++ b/src/shared/l3-machine-code/riscv/model/riscvLib.sig @@ -1,4 +1,4 @@ -(* riscvLib - generated by L3 - Mon Jun 01 11:52:39 2020 *) +(* riscvLib - generated by L3 - Thu Dec 05 14:01:53 2024 *) signature riscvLib = sig val riscv_compset: Thm.thm list -> computeLib.compset diff --git a/src/shared/l3-machine-code/riscv/model/riscvLib.sml b/src/shared/l3-machine-code/riscv/model/riscvLib.sml index 40e42f3f3..412d1971c 100644 --- a/src/shared/l3-machine-code/riscv/model/riscvLib.sml +++ b/src/shared/l3-machine-code/riscv/model/riscvLib.sml @@ -1,4 +1,4 @@ -(* riscvLib - generated by L3 - Mon Jun 01 11:52:39 2020 *) +(* riscvLib - generated by L3 - Thu Dec 05 14:01:53 2024 *) structure riscvLib :> riscvLib = struct open HolKernel boolLib bossLib diff --git a/src/shared/l3-machine-code/riscv/model/riscvScript.sml b/src/shared/l3-machine-code/riscv/model/riscvScript.sml index 6559814bd..2a04332cf 100644 --- a/src/shared/l3-machine-code/riscv/model/riscvScript.sml +++ b/src/shared/l3-machine-code/riscv/model/riscvScript.sml @@ -1,4 +1,4 @@ -(* riscvScript.sml - generated by L3 - Mon Jun 01 11:52:39 2020 *) +(* riscvScript.sml - generated by L3 - Thu Dec 05 14:01:53 2024 *) open HolKernel boolLib bossLib Import val () = Import.start "riscv" @@ -63,18 +63,19 @@ val _ = Record ("mcause",[("EC",F4),("Int",bTy),("mcause'rst",FTy 59)]) ; val _ = Record ("MachineCSR", - [("mbadaddr",F64),("mbase",F64),("mbound",F64),("mcause",CTy"mcause"), + [("mbase",F64),("mbound",F64),("mcause",CTy"mcause"), ("mcpuid",CTy"mcpuid"),("mdbase",F64),("mdbound",F64),("mepc",F64), ("mfromhost",F64),("mhartid",F64),("mibase",F64),("mibound",F64), ("mie",CTy"mie"),("mimpid",CTy"mimpid"),("mip",CTy"mip"), ("mscratch",F64),("mstatus",CTy"mstatus"),("mtdeleg",CTy"mtdeleg"), - ("mtime_delta",F64),("mtimecmp",F64),("mtohost",F64),("mtvec",F64)]) + ("mtime_delta",F64),("mtimecmp",F64),("mtohost",F64),("mtval",F64), + ("mtvec",F64)]) ; val _ = Record ("HypervisorCSR", - [("hbadaddr",F64),("hcause",CTy"mcause"),("hepc",F64),("hscratch",F64), + [("hcause",CTy"mcause"),("hepc",F64),("hscratch",F64), ("hstatus",CTy"mstatus"),("htdeleg",CTy"mtdeleg"),("htime_delta",F64), - ("htimecmp",F64),("htvec",F64)]) + ("htimecmp",F64),("htval",F64),("htvec",F64)]) ; val _ = Record ("sstatus", @@ -87,8 +88,8 @@ val _ = Record ("sie",[("SSIE",bTy),("STIE",bTy),("sie'rst",FTy 62)]) ; val _ = Record ("SupervisorCSR", - [("sasid",F64),("sbadaddr",F64),("scause",CTy"mcause"),("sepc",F64), - ("sptbr",F64),("sscratch",F64),("stime_delta",F64),("stimecmp",F64), + [("sasid",F64),("scause",CTy"mcause"),("sepc",F64),("sptbr",F64), + ("sscratch",F64),("stime_delta",F64),("stimecmp",F64),("stval",F64), ("stvec",F64)]) ; val _ = Record @@ -1717,7 +1718,7 @@ val is_CSR_defined_def = Def LW(3840,12)), Bop(Le,Var("csr",FTy 12), LW(3841,12))),TP[LT,qVar"s"]), - (EQ(Var("csr",FTy 12),LW(3856,12)), + (EQ(Var("csr",FTy 12),LW(3860,12)), TP[LT,qVar"s"]), (Bop(And, Bop(Ge,Var("csr",FTy 12), @@ -1960,7 +1961,7 @@ val CSRMap_def = Def Dest("procID",F8,qVar"state")))),qVar"state"]), (LW(3395,12), TP[Dest - ("sbadaddr",F64, + ("stval",F64, Apply (Dest("c_SCSR",ATy(F8,CTy"SupervisorCSR"),qVar"state"), Dest("procID",F8,qVar"state"))),qVar"state"]), @@ -2125,7 +2126,7 @@ val CSRMap_def = Def Dest("procID",F8,qVar"state")))),qVar"state"]), (LW(579,12), TP[Dest - ("hbadaddr",F64, + ("htval",F64, Apply (Dest("c_HCSR",ATy(F8,CTy"HypervisorCSR"),qVar"state"), Dest("procID",F8,qVar"state"))),qVar"state"]), @@ -2164,7 +2165,7 @@ val CSRMap_def = Def Apply (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), Dest("procID",F8,qVar"state")))),qVar"state"]), - (LW(3856,12), + (LW(3860,12), TP[Dest ("mhartid",F64, Apply @@ -2246,7 +2247,7 @@ val CSRMap_def = Def Dest("procID",F8,qVar"state")))),qVar"state"]), (LW(835,12), TP[Dest - ("mbadaddr",F64, + ("mtval",F64, Apply (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), Dest("procID",F8,qVar"state"))),qVar"state"]), @@ -3040,7 +3041,7 @@ val write'CSRMap_def = Def (Dest("c_MCSR",ATy(F8,CTy"MachineCSR"),qVar"state"), Dest("procID",F8,qVar"state"), Rupd - ("mbadaddr", + ("mtval", TP[Apply (Dest ("c_MCSR",ATy(F8,CTy"MachineCSR"), @@ -3236,7 +3237,7 @@ val csrName_def = Def (LW(260,12),LS"sie"),(LW(289,12),LS"stimecmp"), (LW(3329,12),LS"stime"),(LW(3457,12),LS"stimeh"), (LW(320,12),LS"sscratch"),(LW(321,12),LS"sepc"), - (LW(3394,12),LS"scause"),(LW(3395,12),LS"sbadaddr"), + (LW(3394,12),LS"scause"),(LW(3395,12),LS"stval"), (LW(324,12),LS"mip"),(LW(384,12),LS"sptbr"),(LW(385,12),LS"sasid"), (LW(2304,12),LS"cycle"),(LW(2305,12),LS"time"), (LW(2306,12),LS"instret"),(LW(2432,12),LS"cycleh"), @@ -3245,15 +3246,15 @@ val csrName_def = Def (LW(514,12),LS"htdeleg"),(LW(545,12),LS"htimecmp"), (LW(3585,12),LS"htime"),(LW(3713,12),LS"htimeh"), (LW(576,12),LS"hscratch"),(LW(577,12),LS"hepc"), - (LW(578,12),LS"hcause"),(LW(579,12),LS"hbadaddr"), + (LW(578,12),LS"hcause"),(LW(579,12),LS"htval"), (LW(2561,12),LS"stime"),(LW(2689,12),LS"stimeh"), (LW(3840,12),LS"mcpuid"),(LW(3841,12),LS"mimpid"), - (LW(3856,12),LS"mhartid"),(LW(768,12),LS"mstatus"), + (LW(3860,12),LS"mhartid"),(LW(768,12),LS"mstatus"), (LW(769,12),LS"mtvec"),(LW(770,12),LS"mtdeleg"), (LW(772,12),LS"mie"),(LW(801,12),LS"mtimecmp"), (LW(1793,12),LS"mtime"),(LW(1857,12),LS"mtimeh"), (LW(832,12),LS"mscratch"),(LW(833,12),LS"mepc"), - (LW(834,12),LS"mcause"),(LW(835,12),LS"mbadaddr"), + (LW(834,12),LS"mcause"),(LW(835,12),LS"mtval"), (LW(836,12),LS"mip"),(LW(896,12),LS"mbase"), (LW(897,12),LS"mbound"),(LW(898,12),LS"mibase"), (LW(899,12),LS"mibound"),(LW(900,12),LS"mdbase"), @@ -3932,7 +3933,7 @@ val takeTrap_def = Def ("write'SCSR", ATy(qTy,qTy), Rupd - ("sbadaddr", + ("stval", TP[Apply (Const ("SCSR", @@ -4037,7 +4038,7 @@ val takeTrap_def = Def ("write'MCSR", ATy(qTy,qTy), Rupd - ("mbadaddr", + ("mtval", TP[Apply (Const ("MCSR", @@ -10430,10 +10431,10 @@ val dfn'MRTS_def = Def (Call ("write'SCSR",ATy(qTy,qTy), Rupd - ("sbadaddr", + ("stval", TP[Var("v",CTy"SupervisorCSR"), Dest - ("mbadaddr",F64, + ("mtval",F64, Apply (Const("MCSR",ATy(qTy,CTy"MachineCSR")), qVar"s"))])),qVar"s"), From b99b4f4061aca928e4946cbf17807af9370c7b3f Mon Sep 17 00:00:00 2001 From: Karl Palmskog Date: Thu, 5 Dec 2024 20:09:52 +0100 Subject: [PATCH 13/14] use Holmakefile path relative to HOLBADIR --- src/tools/lifter/examples/Holmakefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/tools/lifter/examples/Holmakefile b/src/tools/lifter/examples/Holmakefile index c0386f478..56bdfa5cf 100644 --- a/src/tools/lifter/examples/Holmakefile +++ b/src/tools/lifter/examples/Holmakefile @@ -1,4 +1,4 @@ -INCLUDES = .. +INCLUDES = $(HOLBADIR)/src/tools/lifter all: $(DEFAULT_TARGETS) .PHONY: all From 60d1af3058be96a92bf4d4614fe83e7cea981ce1 Mon Sep 17 00:00:00 2001 From: Didrik Lundberg Date: Thu, 5 Dec 2024 21:52:30 +0100 Subject: [PATCH 14/14] Failing results in selftest logs now in order of occurrence --- src/tools/lifter/selftest_arm8.log | 4 ++-- src/tools/lifter/selftest_m0_be_main.log | 4 ++-- src/tools/lifter/selftest_m0_be_proc.log | 4 ++-- src/tools/lifter/selftest_m0_le_main.log | 4 ++-- src/tools/lifter/selftest_m0_le_proc.log | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/tools/lifter/selftest_arm8.log b/src/tools/lifter/selftest_arm8.log index b0ca7e4dd..615f22527 100644 --- a/src/tools/lifter/selftest_arm8.log +++ b/src/tools/lifter/selftest_arm8.log @@ -4123,8 +4123,8 @@ SUMMARY FAILING HEXCODES ARM 8 Instructions FAILED: 2/539 - "9BC37C41" (* umulh x1, x2, x3; lifting of ``Imm64 ((127 >< 64) (w2w (ms.REG 3w) * w2w (ms.REG 2w)))`` failed *), - "9B437C41" (* smulh x1, x2, x3; lifting of ``Imm64 ((127 >< 64) (sw2sw (ms.REG 3w) * sw2sw (ms.REG 2w)))`` failed *) + "9B437C41" (* smulh x1, x2, x3; lifting of ``Imm64 ((127 >< 64) (sw2sw (ms.REG 3w) * sw2sw (ms.REG 2w)))`` failed *), + "9BC37C41" (* umulh x1, x2, x3; lifting of ``Imm64 ((127 >< 64) (w2w (ms.REG 3w) * w2w (ms.REG 2w)))`` failed *) ] Instructions FIXED: 0 diff --git a/src/tools/lifter/selftest_m0_be_main.log b/src/tools/lifter/selftest_m0_be_main.log index 202c9d8a1..9e1ce9290 100644 --- a/src/tools/lifter/selftest_m0_be_main.log +++ b/src/tools/lifter/selftest_m0_be_main.log @@ -2679,8 +2679,8 @@ SUMMARY FAILING HEXCODES M0 BigEnd, Main SP Instructions FAILED: 2/111 - "A1BC" (* bmr_step_hex failed *), - "DFB8" (* bmr_step_hex failed *) + "DFB8" (* bmr_step_hex failed *), + "A1BC" (* bmr_step_hex failed *) ] Instructions FIXED: 0 diff --git a/src/tools/lifter/selftest_m0_be_proc.log b/src/tools/lifter/selftest_m0_be_proc.log index 4886eacdb..a8250d2ee 100644 --- a/src/tools/lifter/selftest_m0_be_proc.log +++ b/src/tools/lifter/selftest_m0_be_proc.log @@ -2682,8 +2682,8 @@ SUMMARY FAILING HEXCODES M0 BigEnd, Process SP Instructions FAILED: 2/111 - "A1BC" (* bmr_step_hex failed *), - "DFB8" (* bmr_step_hex failed *) + "DFB8" (* bmr_step_hex failed *), + "A1BC" (* bmr_step_hex failed *) ] Instructions FIXED: 0 diff --git a/src/tools/lifter/selftest_m0_le_main.log b/src/tools/lifter/selftest_m0_le_main.log index a3a78eb91..6355d9c9d 100644 --- a/src/tools/lifter/selftest_m0_le_main.log +++ b/src/tools/lifter/selftest_m0_le_main.log @@ -2684,8 +2684,8 @@ SUMMARY FAILING HEXCODES M0 LittleEnd, Main SP Instructions FAILED: 2/435 - "A1BC" (* bmr_step_hex failed *), - "DFB8" (* bmr_step_hex failed *) + "DFB8" (* bmr_step_hex failed *), + "A1BC" (* bmr_step_hex failed *) ] Instructions FIXED: 0 diff --git a/src/tools/lifter/selftest_m0_le_proc.log b/src/tools/lifter/selftest_m0_le_proc.log index 470a3e26f..946048101 100644 --- a/src/tools/lifter/selftest_m0_le_proc.log +++ b/src/tools/lifter/selftest_m0_le_proc.log @@ -2690,8 +2690,8 @@ SUMMARY FAILING HEXCODES M0 LittleEnd, Process SP Instructions FAILED: 2/111 - "A1BC" (* bmr_step_hex failed *), - "DFB8" (* bmr_step_hex failed *) + "DFB8" (* bmr_step_hex failed *), + "A1BC" (* bmr_step_hex failed *) ] Instructions FIXED: 0