README.md

Open Source Verilog Projects

This repository contains source code for labs and projects involving FPGA and Verilog based designs.

To Run & Test

There are two ways to run and simulate the projects in this repository. Either use Xilinx Vivado or an open source EDA tool such as EDA Playground.

Option 1. Xilinx Vivado

• Run the Xilinx Vivado Suite with the module and testbench files within each project. More instructions can be found here.

Option 2. EDA Playground

• Login with a Google or Facebook account to save and run modules and testbenches
• Testbench + Design: SystemVerilog/Verilog
• Tools & Simulators: Icarus Verilog 0.9.7