Drop unittest from TestCaseWithSimulator (#642)

Author: lekcyjna123

test/cache/test_icache.py

@@ -67,7 +67,7 @@ class TestSimpleCommonBusCacheRefiller(TestCaseWithSimulator):
     line_size: int
     fetch_block: int
 
-    def setUp(self) -> None:
+    def setup_method(self) -> None:
         self.gen_params = GenParams(
             test_core_config.replace(
                 xlen=self.isa_xlen, icache_line_bytes_log=self.line_size, fetch_block_bytes_log=self.fetch_block
@@ -130,22 +130,22 @@ def refiller_process(self):
 
                 cur_addr = req_addr + i * self.cp.fetch_block_bytes
 
-                self.assertEqual(ret["addr"], cur_addr)
+                assert ret["addr"] == cur_addr
 
                 if cur_addr in self.bad_fetch_blocks:
-                    self.assertEqual(ret["error"], 1)
-                    self.assertEqual(ret["last"], 1)
+                    assert ret["error"] == 1
+                    assert ret["last"] == 1
                     break
 
                 fetch_block = ret["fetch_block"]
                 for j in range(self.cp.words_in_fetch_block):
                     word = (fetch_block >> (j * self.cp.word_width)) & (2**self.cp.word_width - 1)
-                    self.assertEqual(word, self.mem[cur_addr + j * self.cp.word_width_bytes])
+                    assert word == self.mem[cur_addr + j * self.cp.word_width_bytes]
 
-                self.assertEqual(ret["error"], 0)
+                assert ret["error"] == 0
 
                 last = 1 if i == self.cp.fetch_blocks_in_line - 1 else 0
-                self.assertEqual(ret["last"], last)
+                assert ret["last"] == last
 
     def test(self):
         with self.run_simulation(self.test_module) as sim:
@@ -190,7 +190,7 @@ class TestICacheBypass(TestCaseWithSimulator):
     isa_xlen: str
     fetch_block: int
 
-    def setUp(self) -> None:
+    def setup_method(self) -> None:
         self.gen_params = GenParams(
             test_core_config.replace(xlen=self.isa_xlen, fetch_block_bytes_log=self.fetch_block, icache_enable=False)
         )
@@ -253,14 +253,14 @@ def user_process(self):
             ret = yield from self.m.accept_res.call()
 
             if (req_addr & ~(self.cp.word_width_bytes - 1)) in self.bad_addrs:
-                self.assertTrue(ret["error"])
+                assert ret["error"]
             else:
-                self.assertFalse(ret["error"])
+                assert not ret["error"]
 
                 data = self.mem[req_addr]
                 if self.gen_params.isa.xlen == 64:
                     data |= self.mem[req_addr + 4] << 32
-                self.assertEqual(ret["fetch_block"], data)
+                assert ret["fetch_block"] == data
 
             while random.random() < 0.5:
                 yield
@@ -321,7 +321,7 @@ class TestICache(TestCaseWithSimulator):
     line_size: int
     fetch_block: int
 
-    def setUp(self) -> None:
+    def setup_method(self) -> None:
         random.seed(42)
 
         self.mem = dict()
@@ -405,17 +405,17 @@ def assert_resp(self, resp: RecordIntDictRet):
         addr = self.issued_requests.popleft() & ~(self.cp.fetch_block_bytes - 1)
 
         if (addr & ~((1 << self.cp.offset_bits) - 1)) in self.bad_cache_lines:
-            self.assertTrue(resp["error"])
+            assert resp["error"]
         else:
-            self.assertFalse(resp["error"])
+            assert not resp["error"]
             fetch_block = 0
             for i in range(0, self.cp.fetch_block_bytes, 4):
                 fetch_block |= self.mem[addr + i] << (8 * i)
 
-            self.assertEqual(resp["fetch_block"], fetch_block)
+            assert resp["fetch_block"] == fetch_block
 
     def expect_refill(self, addr: int):
-        self.assertEqual(self.refill_requests.popleft(), addr)
+        assert self.refill_requests.popleft() == addr
 
     def call_cache(self, addr: int):
         yield from self.send_req(addr)
@@ -435,7 +435,7 @@ def cache_user_process():
             # Accesses to the same cache line shouldn't cause a cache miss
             for i in range(self.cp.fetch_blocks_in_line):
                 yield from self.call_cache(0x00010000 + i * self.cp.fetch_block_bytes)
-                self.assertEqual(len(self.refill_requests), 0)
+                assert len(self.refill_requests) == 0
 
             # Now go beyond the first cache line
             yield from self.call_cache(0x00010000 + self.cp.line_size_bytes)
@@ -456,7 +456,7 @@ def cache_user_process():
             # Now do some accesses within the cached memory
             for i in range(50):
                 yield from self.call_cache(random.randrange(0, self.cp.line_size_bytes * self.cp.num_of_sets, 4))
-            self.assertEqual(len(self.refill_requests), 0)
+            assert len(self.refill_requests) == 0
 
         with self.run_simulation(self.m) as sim:
             sim.add_sync_process(cache_user_process)
@@ -474,7 +474,7 @@ def cache_process():
             # And now both lines should be in the cache
             yield from self.call_cache(0x00010004)
             yield from self.call_cache(0x00020004)
-            self.assertEqual(len(self.refill_requests), 0)
+            assert len(self.refill_requests) == 0
 
         with self.run_simulation(self.m) as sim:
             sim.add_sync_process(cache_process)
@@ -501,7 +501,7 @@ def cache_process():
                 # Send the request
                 yield from self.m.issue_req.call_init(addr=addr)
                 yield Settle()
-                self.assertTrue((yield from self.m.issue_req.done()))
+                assert (yield from self.m.issue_req.done())
 
                 # After a cycle the response should be ready
                 yield
@@ -592,7 +592,7 @@ def cache_process():
                     addr = w * 0x00010000 + s * self.cp.line_size_bytes
                     yield from self.call_cache(addr)
 
-            self.assertEqual(len(self.refill_requests), 0)
+            assert len(self.refill_requests) == 0
 
             yield from self.m.flush_cache.call()
 
@@ -620,8 +620,8 @@ def cache_process():
             self.issued_requests.append(0x00010000)
             yield from self.m.flush_cache.call_init()
             yield Settle()
-            self.assertFalse((yield from self.m.issue_req.done()))
-            self.assertTrue((yield from self.m.flush_cache.done()))
+            assert not (yield from self.m.issue_req.done())
+            assert (yield from self.m.flush_cache.done())
             yield
             yield from self.m.flush_cache.call_do()
             yield from self.m.issue_req.call_do()
@@ -637,7 +637,7 @@ def cache_process():
             yield from self.m.flush_cache.call_init()
             yield
             # We cannot flush until there are two pending requests
-            self.assertFalse((yield from self.m.flush_cache.done()))
+            assert not (yield from self.m.flush_cache.done())
             yield
             yield from self.m.flush_cache.disable()
             yield

test/frontend/test_decode_stage.py

@@ -1,3 +1,4 @@
+import pytest
 from transactron.lib import AdapterTrans, FIFO
 
 from transactron.testing import TestCaseWithSimulator, TestbenchIO, SimpleTestCircuit, ModuleConnector
@@ -10,7 +11,8 @@
 
 
 class TestDecode(TestCaseWithSimulator):
-    def setUp(self) -> None:
+    @pytest.fixture(autouse=True)
+    def setup(self, configure_dependency_context):
         self.gen_params = GenParams(test_core_config.replace(start_pc=24))
 
         fifo_in = FIFO(self.gen_params.get(FetchLayouts).raw_instr, depth=2)
@@ -35,45 +37,45 @@ def decode_test_proc(self):
         yield from self.fifo_in_write.call(instr=0x02A28213)
         decoded = yield from self.fifo_out_read.call()
 
-        self.assertEqual(decoded["exec_fn"]["op_type"], OpType.ARITHMETIC)
-        self.assertEqual(decoded["exec_fn"]["funct3"], Funct3.ADD)
-        self.assertEqual(decoded["exec_fn"]["funct7"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_dst"], 4)
-        self.assertEqual(decoded["regs_l"]["rl_s1"], 5)
-        self.assertEqual(decoded["regs_l"]["rl_s2"], 0)
-        self.assertEqual(decoded["imm"], 42)
+        assert decoded["exec_fn"]["op_type"] == OpType.ARITHMETIC
+        assert decoded["exec_fn"]["funct3"] == Funct3.ADD
+        assert decoded["exec_fn"]["funct7"] == 0
+        assert decoded["regs_l"]["rl_dst"] == 4
+        assert decoded["regs_l"]["rl_s1"] == 5
+        assert decoded["regs_l"]["rl_s2"] == 0
+        assert decoded["imm"] == 42
 
         # testing an OP instruction (test copied from test_decoder.py)
         yield from self.fifo_in_write.call(instr=0x003100B3)
         decoded = yield from self.fifo_out_read.call()
 
-        self.assertEqual(decoded["exec_fn"]["op_type"], OpType.ARITHMETIC)
-        self.assertEqual(decoded["exec_fn"]["funct3"], Funct3.ADD)
-        self.assertEqual(decoded["exec_fn"]["funct7"], Funct7.ADD)
-        self.assertEqual(decoded["regs_l"]["rl_dst"], 1)
-        self.assertEqual(decoded["regs_l"]["rl_s1"], 2)
-        self.assertEqual(decoded["regs_l"]["rl_s2"], 3)
+        assert decoded["exec_fn"]["op_type"] == OpType.ARITHMETIC
+        assert decoded["exec_fn"]["funct3"] == Funct3.ADD
+        assert decoded["exec_fn"]["funct7"] == Funct7.ADD
+        assert decoded["regs_l"]["rl_dst"] == 1
+        assert decoded["regs_l"]["rl_s1"] == 2
+        assert decoded["regs_l"]["rl_s2"] == 3
 
         # testing an illegal
         yield from self.fifo_in_write.call(instr=0x0)
         decoded = yield from self.fifo_out_read.call()
 
-        self.assertEqual(decoded["exec_fn"]["op_type"], OpType.EXCEPTION)
-        self.assertEqual(decoded["exec_fn"]["funct3"], Funct3._EILLEGALINSTR)
-        self.assertEqual(decoded["exec_fn"]["funct7"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_dst"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_s1"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_s2"], 0)
+        assert decoded["exec_fn"]["op_type"] == OpType.EXCEPTION
+        assert decoded["exec_fn"]["funct3"] == Funct3._EILLEGALINSTR
+        assert decoded["exec_fn"]["funct7"] == 0
+        assert decoded["regs_l"]["rl_dst"] == 0
+        assert decoded["regs_l"]["rl_s1"] == 0
+        assert decoded["regs_l"]["rl_s2"] == 0
 
         yield from self.fifo_in_write.call(instr=0x0, access_fault=1)
         decoded = yield from self.fifo_out_read.call()
 
-        self.assertEqual(decoded["exec_fn"]["op_type"], OpType.EXCEPTION)
-        self.assertEqual(decoded["exec_fn"]["funct3"], Funct3._EINSTRACCESSFAULT)
-        self.assertEqual(decoded["exec_fn"]["funct7"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_dst"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_s1"], 0)
-        self.assertEqual(decoded["regs_l"]["rl_s2"], 0)
+        assert decoded["exec_fn"]["op_type"] == OpType.EXCEPTION
+        assert decoded["exec_fn"]["funct3"] == Funct3._EINSTRACCESSFAULT
+        assert decoded["exec_fn"]["funct7"] == 0
+        assert decoded["regs_l"]["rl_dst"] == 0
+        assert decoded["regs_l"]["rl_s1"] == 0
+        assert decoded["regs_l"]["rl_s2"] == 0
 
     def test(self):
         with self.run_simulation(self.m) as sim:

test/frontend/test_fetch.py

@@ -1,3 +1,4 @@
+import pytest
 from collections import deque
 
 import random
@@ -37,7 +38,7 @@ def elaborate(self, platform):
 
 
 class TestFetch(TestCaseWithSimulator):
-    def setUp(self) -> None:
+    def setup_method(self) -> None:
         self.gen_params = GenParams(test_core_config.replace(start_pc=0x18))
 
         self.icache = MockedICache(self.gen_params)
@@ -125,8 +126,8 @@ def fetch_out_check(self):
                 yield
 
             instr = self.instr_queue.popleft()
-            self.assertEqual(v["pc"], instr["pc"])
-            self.assertEqual(v["instr"], instr["instr"])
+            assert v["pc"] == instr["pc"]
+            assert v["instr"] == instr["instr"]
 
             if instr["is_branch"]:
                 # branches on mispredict will stall fetch because of exception and then resume with new pc
@@ -145,7 +146,8 @@ def test(self):
 
 
 class TestUnalignedFetch(TestCaseWithSimulator):
-    def setUp(self) -> None:
+    @pytest.fixture(autouse=True)
+    def setup(self, configure_dependency_context):
         self.gen_params = GenParams(test_core_config.replace(start_pc=0x18, compressed=True))
         self.instr_queue = deque()
         self.instructions = 500
@@ -256,8 +258,8 @@ def fetch_out_check(self):
                     v = yield from self.io_out.call()
                 discard_mispredict = False
 
-            self.assertEqual(v["pc"], instr["pc"])
-            self.assertEqual(v["access_fault"], instr_error)
+            assert v["pc"] == instr["pc"]
+            assert v["access_fault"] == instr_error
 
             if instr["is_branch"] or instr_error:
                 yield from self.random_wait(5)

test/frontend/test_instr_decoder.py

@@ -171,7 +171,7 @@ def __init__(
         ),
     ]
 
-    def setUp(self):
+    def setup_method(self):
         self.gen_params = GenParams(
             test_core_config.replace(
                 _implied_extensions=Extension.G | Extension.XINTMACHINEMODE | Extension.XINTSUPERVISOR | Extension.ZBB
@@ -186,52 +186,52 @@ def process():
                 yield self.decoder.instr.eq(test.encoding)
                 yield Settle()
 
-                self.assertEqual((yield self.decoder.illegal), test.illegal)
+                assert (yield self.decoder.illegal) == test.illegal
                 if test.illegal:
                     return
 
-                self.assertEqual((yield self.decoder.opcode), test.opcode)
+                assert (yield self.decoder.opcode) == test.opcode
 
                 if test.funct3 is not None:
-                    self.assertEqual((yield self.decoder.funct3), test.funct3)
-                self.assertEqual((yield self.decoder.funct3_v), test.funct3 is not None)
+                    assert (yield self.decoder.funct3) == test.funct3
+                assert (yield self.decoder.funct3_v) == (test.funct3 is not None)
 
                 if test.funct7 is not None:
-                    self.assertEqual((yield self.decoder.funct7), test.funct7)
-                self.assertEqual((yield self.decoder.funct7_v), test.funct7 is not None)
+                    assert (yield self.decoder.funct7) == test.funct7
+                assert (yield self.decoder.funct7_v) == (test.funct7 is not None)
 
                 if test.funct12 is not None:
-                    self.assertEqual((yield self.decoder.funct12), test.funct12)
-                self.assertEqual((yield self.decoder.funct12_v), test.funct12 is not None)
+                    assert (yield self.decoder.funct12) == test.funct12
+                assert (yield self.decoder.funct12_v) == (test.funct12 is not None)
 
                 if test.rd is not None:
-                    self.assertEqual((yield self.decoder.rd), test.rd)
-                self.assertEqual((yield self.decoder.rd_v), test.rd is not None)
+                    assert (yield self.decoder.rd) == test.rd
+                assert (yield self.decoder.rd_v) == (test.rd is not None)
 
                 if test.rs1 is not None:
-                    self.assertEqual((yield self.decoder.rs1), test.rs1)
-                self.assertEqual((yield self.decoder.rs1_v), test.rs1 is not None)
+                    assert (yield self.decoder.rs1) == test.rs1
+                assert (yield self.decoder.rs1_v) == (test.rs1 is not None)
 
                 if test.rs2 is not None:
-                    self.assertEqual((yield self.decoder.rs2), test.rs2)
-                self.assertEqual((yield self.decoder.rs2_v), test.rs2 is not None)
+                    assert (yield self.decoder.rs2) == test.rs2
+                assert (yield self.decoder.rs2_v) == (test.rs2 is not None)
 
                 if test.imm is not None:
-                    self.assertEqual((yield self.decoder.imm.as_signed()), test.imm)
+                    assert (yield self.decoder.imm.as_signed()) == test.imm
 
                 if test.succ is not None:
-                    self.assertEqual((yield self.decoder.succ), test.succ)
+                    assert (yield self.decoder.succ) == test.succ
 
                 if test.pred is not None:
-                    self.assertEqual((yield self.decoder.pred), test.pred)
+                    assert (yield self.decoder.pred) == test.pred
 
                 if test.fm is not None:
-                    self.assertEqual((yield self.decoder.fm), test.fm)
+                    assert (yield self.decoder.fm) == test.fm
 
                 if test.csr is not None:
-                    self.assertEqual((yield self.decoder.csr), test.csr)
+                    assert (yield self.decoder.csr) == test.csr
 
-                self.assertEqual((yield self.decoder.optype), test.op)
+                assert (yield self.decoder.optype) == test.op
 
         with self.run_simulation(self.decoder) as sim:
             sim.add_process(process)
@@ -280,7 +280,7 @@ def process():
             for encoding, illegal in self.E_TEST:
                 yield self.decoder.instr.eq(encoding)
                 yield Settle()
-                self.assertEqual((yield self.decoder.illegal), illegal)
+                assert (yield self.decoder.illegal) == illegal
 
         with self.run_simulation(self.decoder) as sim:
             sim.add_process(process)
@@ -329,7 +329,7 @@ def code_prefixes(code: code_type) -> list[code_type]:
                         encoding = known_codes[prefix]
 
                         # prefix of instruction can not be equal to code of any other isntruction
-                        self.assertIsNone(encoding, f"Instruction is not unique: I1 = {encoding} I2 = {instruction}")
+                        assert encoding is None, f"Instruction is not unique: I1 = {encoding} I2 = {instruction}"
 
                     known_codes[prefix] = None
 
@@ -398,4 +398,4 @@ def instruction_code(instr: Encoding) -> code_type:
 
             for instruction in ext_collisions:
                 code = instruction_code(instruction)
-                self.assertIn(code, known_codes, f"Instruction is not colliding: OpType={ext} I={instruction}")
+                assert code in known_codes, f"Instruction is not colliding: OpType={ext} I={instruction}"