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| 1 | +# Copyright (C) 2022 Intel Corporation |
| 2 | +# SPDX-License-Identifier: LGPL 2.1 or later |
| 3 | +# See: https://spdx.org/licenses/ |
| 4 | +import threading |
| 5 | +import unittest |
| 6 | +import typing as ty |
| 7 | + |
| 8 | +import numpy as np |
| 9 | + |
| 10 | +from lava.magma.core.decorator import implements, requires |
| 11 | +from lava.magma.core.model.py.model import PyLoihiProcessModel |
| 12 | +from lava.magma.core.model.py.ports import PyOutPort, PyInPort |
| 13 | +from lava.magma.core.model.py.type import LavaPyType |
| 14 | +from lava.magma.core.process.ports.ports import OutPort, InPort |
| 15 | +from lava.magma.core.process.process import AbstractProcess |
| 16 | +from lava.magma.core.resources import CPU |
| 17 | +from lava.magma.core.sync.protocols.loihi_protocol import LoihiProtocol |
| 18 | +from lava.magma.core.run_conditions import RunSteps |
| 19 | +from lava.magma.core.run_configs import Loihi2SimCfg |
| 20 | + |
| 21 | + |
| 22 | +class Process1(AbstractProcess): |
| 23 | + def __init__(self, shape_1: ty.Tuple, **kwargs): |
| 24 | + super().__init__(shape_1=shape_1, **kwargs) |
| 25 | + |
| 26 | + self.in_1 = InPort(shape=shape_1) |
| 27 | + self.out_1 = OutPort(shape=shape_1) |
| 28 | + |
| 29 | + |
| 30 | +@implements(proc=Process1, protocol=LoihiProtocol) |
| 31 | +@requires(CPU) |
| 32 | +class LoihiDenseSpkPyProcess1PM(PyLoihiProcessModel): |
| 33 | + in_1: PyInPort = LavaPyType(PyInPort.VEC_DENSE, float) |
| 34 | + out_1: PyOutPort = LavaPyType(PyOutPort.VEC_DENSE, float) |
| 35 | + |
| 36 | + def __init__(self, proc_params): |
| 37 | + super().__init__(proc_params) |
| 38 | + |
| 39 | + def run_spk(self): |
| 40 | + print(f"Receiving in Process...") |
| 41 | + data_1 = self.in_1.recv() |
| 42 | + print(f"Received {data_1} in Process...") |
| 43 | + |
| 44 | + print(f"Sending {data_1} from Process...") |
| 45 | + self.out_1.send(data_1) |
| 46 | + print(f"Sent {data_1} from Process!") |
| 47 | + |
| 48 | + |
| 49 | +class TestExternalPipeIO(unittest.TestCase): |
| 50 | + def test_run_steps_non_blocking(self): |
| 51 | + data = [[1], [2], [3], [4], [5]] |
| 52 | + |
| 53 | + relay = Process1(shape_1=(1,)) |
| 54 | + # Control buffer size with buffer_size arg, default is 64 |
| 55 | + relay.in_1.flag_external_pipe() |
| 56 | + # Control buffer size with buffer_size arg, default is 64 |
| 57 | + relay.out_1.flag_external_pipe() |
| 58 | + |
| 59 | + run_cfg = Loihi2SimCfg() |
| 60 | + run_condition = RunSteps(num_steps=5, blocking=False) |
| 61 | + |
| 62 | + def thread_inject_fn() -> None: |
| 63 | + for send_data_single_item in data: |
| 64 | + print(f"Sending {send_data_single_item} from thread_inject...") |
| 65 | + # Use probe() before send() to know whether or not send() will |
| 66 | + # block (i.e if the buffer of external_pipe_csp_send_port |
| 67 | + # is full). |
| 68 | + relay.in_1.external_pipe_csp_send_port.send( |
| 69 | + np.array(send_data_single_item)) |
| 70 | + print(f"Sent {send_data_single_item} from thread_inject!") |
| 71 | + |
| 72 | + def thread_extract_fn() -> None: |
| 73 | + for _ in range(len(data)): |
| 74 | + print(f"Receiving in thread_extract...") |
| 75 | + # Use probe() before recv() to know whether or not recv() will |
| 76 | + # block (i.e if the buffer of external_pipe_csp_recv_port |
| 77 | + # is empty). |
| 78 | + received_data = relay.out_1.external_pipe_csp_recv_port.recv() |
| 79 | + print(f"Received {received_data} in thread_extract!") |
| 80 | + |
| 81 | + thread_inject = threading.Thread(target=thread_inject_fn, |
| 82 | + daemon=True) |
| 83 | + thread_extract = threading.Thread(target=thread_extract_fn, |
| 84 | + daemon=True) |
| 85 | + |
| 86 | + relay.run(condition=run_condition, run_cfg=run_cfg) |
| 87 | + |
| 88 | + thread_inject.start() |
| 89 | + thread_extract.start() |
| 90 | + |
| 91 | + relay.wait() |
| 92 | + relay.stop() |
| 93 | + |
| 94 | + |
| 95 | +if __name__ == "__main__": |
| 96 | + unittest.main() |
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