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hargoniXbollu
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Co-authored-by: Siddharth <siddu.druid@gmail.com>
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src/Std/Sat/AIG/Basic.lean

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@@ -20,7 +20,7 @@ variable {α : Type} [Hashable α] [DecidableEq α]
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namespace AIG
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/--
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A circuit node declaration. These are not recursive but instead contain indices into an `AIG`.
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A circuit node declaration. These are not recursive but instead contain indices into an `AIG`, with inputs indexed by `α`.
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-/
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inductive Decl (α : Type) where
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/--
@@ -95,8 +95,7 @@ structure CacheHit (decls : Array (Decl α)) (decl : Decl α) where
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hvalid : decls[idx]'hbound = decl
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/--
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All indices, found in a `Cache` that is valid with respect to some `decls`, are within bounds of
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`decls`.
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For a `c : Cache α decls`, any index `idx` that is a cache hit for some `decl` is within bounds of `decls` (i.e. `idx < decls.size`).
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-/
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theorem Cache.get?_bounds {decls : Array (Decl α)} {idx : Nat} (c : Cache α decls) (decl : Decl α)
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(hfound : c.val[decl]? = some idx) :
@@ -186,7 +185,7 @@ opaque Cache.get? (cache : Cache α decls) (decl : Decl α) : Option (CacheHit d
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| none => none
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/--
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An `Array Decl` is a Direct Acyclic Graph (DAG) if this holds.
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An `Array Decl` is a Direct Acyclic Graph (DAG) if a gate at index `i` only points to nodes with index lower than `i`.
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-/
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def IsDag (α : Type) (decls : Array (Decl α)) : Prop :=
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∀ i lhs rhs linv rinv (h : i < decls.size),
@@ -366,7 +365,7 @@ scoped syntax "⟦" term ", " term "⟧" : term
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scoped syntax "⟦" term ", " term ", " term "⟧" : term
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macro_rules
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| `(⟦$entry, $assign⟧) => `(denote $assign $entry )
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| `(⟦$entry, $assign⟧) => `(denote $assign $entry)
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| `(⟦$aig, $ref, $assign⟧) => `(denote $assign (Entrypoint.mk $aig $ref))
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@[app_unexpander AIG.denote]
@@ -376,6 +375,9 @@ def unexpandDenote : Lean.PrettyPrinter.Unexpander
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| `($(_) $entry $assign) => `(⟦$entry, $assign⟧)
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| _ => throw ()
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/--
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The denotation of the sub-DAG in the `aig` at node `start` is false for all assignments.
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-/
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def UnsatAt (aig : AIG α) (start : Nat) (h : start < aig.decls.size) : Prop :=
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∀ assign, ⟦aig, ⟨start, h⟩, assign⟧ = false
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