MemoryUnitUtils.v

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--  Amirkabir University of Technology (Tehran Polytechnic)
--  Department of Computer Engineering (CE-AUT)
--  https://ce[dot]aut[dot]ac[dot]ir
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/*-----------------------------------------------------------
---  Module Name:  Memory Unit Utils
---  Description: Module5:
-----------------------------------------------------------*/
`timescale 1 ns/1 ns

module register(input D, input Clk,
input reset, input load, output reg Q);
		 always @(posedge Clk or negedge reset)
			 if (~reset)
				begin
				Q <= 1'b0;
				end else if (load)
				begin
				Q <= D;
				end
endmodule