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1 parent 1817f30 commit 356fd51

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+1468
-381
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‎verilog/.gitignore

+7-1
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a.exe
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.vscode
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.vscode
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verilog/Top/
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verilog/CNU.sv
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verilog/tb_top1.sv
6+
verilog/tb_bs.sv
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verilog/gentop.cpp
8+
verilog/permuter.sv

‎verilog/CNU.sv

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// CNU
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// Z : lifting size
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// dmax : maximum number of 1's in every row in PCM
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module CNU #(parameter BITS = 5 + 3, parameter Z = 32, parameter dmax = 10)(
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input [BITS-1:0] x [Z-1:0][dmax-1:0],
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output [BITS-1:0] out[Z-1]
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);
8+
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genvar i;
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generate;
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for(i = 0 ; i < Z ; i = i+1) begin
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FMIG_N #(.BITS(BITS), .N(dmax))(
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.x(x[i]),
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.out(),
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.idx(),
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);
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end
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endgenerate
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endmodule

‎verilog/CNU1.sv

+50
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`include "FMIG2.sv"
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// CNU
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// clk : clock
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// sel : select
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// Z : lifting size
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// dmax : maximum number of 1's in every row in PCM
7+
module CNU1 #(parameter BITS = 5 + 3, parameter dmax = 10, parameter MAX = 2**(BITS-1)-1, parameter INPUTS_BITS = $clog2(dmax))(
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input clk,
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input sel,
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input signed [BITS-1:0] x [dmax-1:0],
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output signed [BITS-1:0] min1,
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output signed [BITS-1:0] min2,
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output [INPUTS_BITS-1:0] idx_min
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);
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logic [INPUTS_BITS-1:0] idx, idx_min_w, idx_min_r;
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logic signed [BITS-1:0] min, min1_w, min2_w, min1_r, min2_r;
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logic signed [BITS-1:0] x_w [dmax-1:0];
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assign idx_min = sel ? idx_min_r : idx;
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assign min1 = sel ? min1_r : min;
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assign min2 = sel ? min : 0;
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24+
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FMIG_N #(.BITS(BITS), .N(dmax)) FMIG0 (
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.x(x_w),
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.out(min),
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.idx(idx)
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);
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always_comb begin
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min1_w = min1_r;
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min2_w = min2_r;
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idx_min_w = idx_min_r;
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x_w = x;
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if(sel) begin
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x_w[idx_min_r] = MAX;
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min2_w = min;
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end
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end
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always_ff @(posedge clk) begin
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min1_r <= min;
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min2_r <= min2_w;
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idx_min_r <= idx;
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end
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endmodule
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‎verilog/CNU1/255.txt

+100
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‎verilog/CNU1/7.txt

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60 102 69 -63 116 -101 85 -101 -63 1
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-59 13 32 24 -50 64 -36 -59 -50 6
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36 39 -5 -110 -126 -56 43 -126 -110 2
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20 15 39 55 -76 35 80 -76 15 2
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-52 -4 113 56 -32 -97 46 -97 -52 1
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78 -15 -82 118 84 -114 15 -114 -82 1
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-21 109 25 44 -97 119 -53 -97 -53 2
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-24 52 -102 -8 -41 65 33 -102 -41 4
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-107 -82 -8 -119 -9 -8 6 -119 -107 3
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-40 -35 11 -69 49 -79 59 -79 -69 1
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107 -92 11 77 20 74 119 -92 11 5
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47 64 -110 120 -26 45 -42 -110 -42 4
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-51 -57 44 50 -14 -22 71 -57 -51 5
14+
-107 -22 -36 38 24 60 -108 -108 -107 0
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52 -113 60 -88 -3 94 -117 -117 -113 0
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-63 -38 -113 -31 77 -47 33 -113 -63 4
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10 115 -73 -94 47 76 -105 -105 -94 0
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0 87 80 88 -100 45 14 -100 0 2
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-103 -96 4 33 -32 -109 24 -109 -103 1
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95 -12 42 23 83 -121 97 -121 -12 1
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-32 -18 24 -53 -118 121 24 -118 -53 2
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38 -88 -50 76 51 -53 -56 -88 -56 5
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114 -59 73 -8 39 23 61 -59 -8 5
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-103 8 98 -49 -58 24 -81 -103 -81 6
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-74 -21 98 -22 -5 122 -33 -74 -33 6
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57 -1 -33 -103 -116 -65 -75 -116 -103 2
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17 116 87 58 -34 56 -59 -59 -34 0
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0 -104 38 -16 -26 -12 39 -104 -26 5
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-23 71 48 -106 112 113 -78 -106 -78 3
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82 -70 89 -20 18 113 -115 -115 -70 0
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-126 -7 -3 105 -81 107 2 -126 -81 6
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-114 -27 30 41 -112 -77 116 -114 -112 6
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36 -17 -20 8 -20 73 6 -20 -20 4
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-122 77 -51 -64 -63 -91 -13 -122 -91 6
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7 -1 -23 106 27 -105 -24 -105 -24 1
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82 -18 -65 -44 -84 -51 -97 -97 -84 0
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-2 15 65 -86 -31 -100 56 -100 -86 1
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45 98 52 96 40 86 -24 -24 40 0
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-44 94 69 -80 -6 -88 109 -88 -80 1
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96 -85 -114 10 -39 -107 24 -114 -107 4
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-43 124 -34 -30 -53 -27 10 -53 -43 2
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111 47 -43 31 -65 -46 111 -65 -46 2
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7 36 -110 -88 53 81 33 -110 -88 4
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-7 -116 -76 8 86 124 6 -116 -76 5
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-21 100 110 32 14 -25 98 -25 -21 1
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16 24 121 -42 108 23 -126 -126 -42 0
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-22 -26 -59 100 -61 33 10 -61 -59 2
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-10 45 -61 -63 52 -124 -52 -124 -63 1
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-65 53 -44 38 17 93 63 -65 -44 6
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124 -122 -45 -97 80 110 53 -122 -97 5
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109 72 -96 -117 -30 -55 -62 -117 -96 3
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122 91 -57 -60 -69 2 -36 -69 -60 2
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-82 -53 -85 -105 -100 -29 -4 -105 -100 3
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22 6 42 -47 -41 69 42 -47 -41 3
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-34 -53 83 -128 -105 -84 -45 -128 -105 3
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-40 76 -111 81 25 -103 -64 -111 -103 4
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-54 -35 -3 -61 111 36 -55 -61 -55 3
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-66 -90 73 60 -1 82 53 -90 -66 5
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-20 -41 84 -46 103 -88 82 -88 -46 1
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-62 27 64 -74 82 115 101 -74 -62 3
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-6 -87 67 -79 36 70 102 -87 -79 5
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-95 -116 -87 -90 -24 -27 79 -116 -95 5
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-37 9 123 -28 87 36 -70 -70 -37 0
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-75 -126 16 -16 100 -62 -85 -126 -85 5
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84 -33 -98 110 70 -110 34 -110 -98 1
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69 -40 -36 -123 -99 -114 -64 -123 -114 3
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9 -66 98 -34 35 91 11 -66 -34 5
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-95 -36 103 127 -71 119 43 -95 -71 6
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-73 -52 84 -106 -78 104 20 -106 -78 3
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-44 -68 61 -2 34 -16 -119 -119 -68 0
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-95 -32 -4 -45 -69 -25 36 -95 -69 6
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-36 90 30 -118 -45 65 72 -118 -45 3
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-84 -56 -115 32 46 99 -103 -115 -103 4
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-88 -38 -42 30 -66 -27 16 -88 -66 6
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-97 -16 115 51 4 -111 94 -111 -97 1
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73 -123 12 51 51 -55 121 -123 -55 5
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126 -31 79 110 72 -55 14 -55 -31 1
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24 -35 -111 88 -118 -45 15 -118 -111 2
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4 84 71 116 -52 88 106 -52 4 2
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-60 -12 -39 61 -118 45 -43 -118 -60 2
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-104 -55 -72 -107 113 53 -50 -107 -104 3
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-126 91 -93 64 58 77 -65 -126 -93 6
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91 -29 -91 -3 14 -64 108 -91 -64 4
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-46 79 1 -36 35 -70 -32 -70 -46 1
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31 -2 123 -23 90 -120 111 -120 -23 1
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-103 -22 54 -122 43 -18 64 -122 -103 3
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108 -81 5 83 104 92 89 -81 5 5
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-121 -124 39 -36 -112 -18 -107 -124 -121 5
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-47 56 -98 -51 -113 13 57 -113 -98 2
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-15 -127 86 53 -82 114 76 -127 -82 5
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63 18 7 -121 -39 -98 -115 -121 -115 3
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-73 72 -99 -11 -108 -83 -76 -108 -99 2
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29 24 114 -71 82 -21 -25 -71 -25 3
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-56 18 31 45 -108 22 29 -108 -56 2
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84 -4 -112 -33 -64 -33 -79 -112 -79 4
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96 -47 48 110 81 -61 77 -61 -47 1
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-124 14 -46 -116 -71 -48 -94 -124 -116 6
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23 101 36 -33 -5 50 -100 -100 -33 0
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32 123 32 -60 18 -86 -52 -86 -60 1
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87 -46 57 -15 -77 -102 -115 -115 -102 0

‎verilog/FMIG2.sv

+58-6
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@@ -1,3 +1,5 @@
1+
///////////////////////////////////////////////////////////////////////////////
2+
// FMIG2
13
module FMIG2 #(parameter BITS = 5 + 3)(
24
input signed [BITS-1:0] x, y,
35
output signed [BITS-1:0] min,
@@ -11,7 +13,8 @@ assign cp_w = (y > x) ? 0 : 1;
1113
assign cp = cp_w;
1214

1315
endmodule
14-
16+
///////////////////////////////////////////////////////////////////////////////
17+
// FMIG2k
1518
module FMIG2k #(parameter BITS = 5 + 3, parameter K = 5)(
1619
input signed [BITS-1:0] x [2**K-1:0],
1720
output signed [BITS-1:0] out,
@@ -54,11 +57,60 @@ end
5457

5558
endmodule
5659

57-
module FMIG_N #(parameter BITS = 5 + 3, parameter N = 50);
60+
///////////////////////////////////////////////////////////////////////////////
61+
// FMIG_N
62+
// N : numbers of input
63+
// K : 2**K is the maximum 2's power numbers smallers than N
64+
// R : the remaining number of index to represent
65+
// if R != 0 : seperate the comparator to two
66+
// if R == 0 : just call FMIG2k
67+
// RB : number of bits to represent the index of R inputs
68+
module FMIG_N #(parameter BITS = 5 + 3, parameter N = 7, parameter K = $clog2(N + 1) - 1 , parameter R = N - 2**K,
69+
parameter RB = (R == 1) ? 1 : $clog2(R))(
70+
input signed [BITS-1:0] x [N-1:0],
71+
output signed [BITS-1:0] out,
72+
output [K:0] idx
73+
);
74+
75+
logic signed [BITS-1:0] min1_w, min2_w;
76+
logic [K-1:0] idx1_w, idx_min;
77+
logic [RB-1:0] idx2_w;
78+
logic cp_w;
79+
80+
if(N == 1) begin
81+
assign idx = 0;
82+
assign out = x[0];
83+
end
5884

59-
parameter K = $clog2(N + 1) - 1;
60-
parameter R = N - 2**K;
85+
else begin
86+
if(R != 0) begin
87+
FMIG2k #(.BITS(BITS), .K(K)) FMIG_1(
88+
.x(x[2**K-1:0]),
89+
.out(min1_w),
90+
.idx(idx1_w)
91+
);
92+
FMIG_N #(.BITS(BITS), .N(R)) FMIG_2(
93+
.x(x[N-1:2**K]),
94+
.out(min2_w),
95+
.idx(idx2_w)
96+
);
97+
FMIG2 #(.BITS(BITS)) FMIG2_3(
98+
.x(min1_w),
99+
.y(min2_w),
100+
.min(out),
101+
.cp(cp_w)
102+
);
103+
assign idx_min = cp_w ? idx2_w : idx1_w;
104+
assign idx = {cp_w, idx_min};
105+
end
61106

62-
integer TEST = K;
63-
integer TEST2 = R;
107+
else begin
108+
FMIG2k #(.BITS(BITS), .K(K)) FMIG_2(
109+
.x(x[2**K-1:0]),
110+
.out(out),
111+
.idx(idx)
112+
);
113+
end
114+
end
115+
///////////////////////////////////////////////////////////////////////////////
64116
endmodule

‎verilog/FMIG2k/FMIG16.txt

-100
This file was deleted.

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