diff --git a/src/PSUM_ADD.v b/src/PSUM_ADD.v
index b4f9e58..738e61a 100644
--- a/src/PSUM_ADD.v
+++ b/src/PSUM_ADD.v
@@ -7,12 +7,12 @@ module PSUM_ADD #(
 ) (
     input clk,
     input rst_n,
-    input signed [data_width-1:0] pe0_data,
-    input signed [data_width-1:0] pe1_data,
-    input signed [data_width-1:0] pe2_data,
-    input signed [data_width-1:0] pe3_data,
-    input signed [data_width-1:0] fifo_data,
-    output signed [data_width-1:0] out
+    input wire signed [data_width-1:0] pe0_data,
+    input wire signed [data_width-1:0] pe1_data,
+    input wire signed [data_width-1:0] pe2_data,
+    input wire signed [data_width-1:0] pe3_data,
+    input wire signed [data_width-1:0] fifo_data,
+    output wire signed [data_width-1:0] out
 );
 
     reg signed [data_width-1:0] psum0;
@@ -35,4 +35,4 @@ module PSUM_ADD #(
             out_r <= fifo_data + psum2;
         end
     end
-endmodule
\ No newline at end of file
+endmodule