From 5a4c97cd85f086ee9fb4dd47b58293b77f41597e Mon Sep 17 00:00:00 2001 From: Jiahan Xie Date: Tue, 5 Nov 2024 23:32:59 -0500 Subject: [PATCH] remove 'std_' before ieee754 operations --- .../circt/Dialect/Calyx/CalyxPrimitives.td | 20 +++++++++---------- .../Conversion/SCFToCalyx/convert_simple.mlir | 2 +- test/Dialect/Calyx/emit.mlir | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/circt/Dialect/Calyx/CalyxPrimitives.td b/include/circt/Dialect/Calyx/CalyxPrimitives.td index 4ad673638703..4970f25ba9e2 100644 --- a/include/circt/Dialect/Calyx/CalyxPrimitives.td +++ b/include/circt/Dialect/Calyx/CalyxPrimitives.td @@ -257,8 +257,8 @@ def SeqMemoryOp : CalyxPrimitive<"seq_mem", []> { }]; } -class CalyxLibraryOp traits = []> : - CalyxPrimitive<"std_" # mnemonic, traits> { +class CalyxLibraryOp traits = []> : + CalyxPrimitive { let summary = "Defines an operation which maps to a Calyx library primitive"; let description = [{ @@ -289,7 +289,7 @@ class CalyxLibraryOp traits = []> : ]; } -class BoolBinaryLibraryOp : CalyxLibraryOp : CalyxLibraryOp ]> { @@ -309,13 +309,13 @@ def SneqLibOp : BoolBinaryLibraryOp<"sneq"> {} def SgeLibOp : BoolBinaryLibraryOp<"sge"> {} def SleLibOp : BoolBinaryLibraryOp<"sle"> {} -class ArithBinaryLibraryOp traits = []> : - CalyxLibraryOp traits = []> : + CalyxLibraryOp ])> {} class CombinationalArithBinaryLibraryOp : - ArithBinaryLibraryOp ]> { @@ -332,7 +332,7 @@ def AndLibOp : CombinationalArithBinaryLibraryOp<"and"> {} def OrLibOp : CombinationalArithBinaryLibraryOp<"or"> {} def XorLibOp : CombinationalArithBinaryLibraryOp<"xor"> {} -class ArithBinaryFloatingPointLibraryOp : ArithBinaryLibraryOp : ArithBinaryLibraryOp]> {} def AddFNOp : ArithBinaryFloatingPointLibraryOp<"ieee754.add"> { @@ -410,7 +410,7 @@ def MulFNOp : ArithBinaryFloatingPointLibraryOp<"ieee754.mul"> { }]; } -def MuxLibOp : CalyxLibraryOp<"mux", [ +def MuxLibOp : CalyxLibraryOp<"mux", "std_", [ Combinational, SameTypeConstraint<"tru", "fal">, SameTypeConstraint<"tru", "out"> ]> { let results = (outs I1:$cond, AnyType:$tru, AnyType:$fal, AnyType:$out); @@ -432,7 +432,7 @@ def MuxLibOp : CalyxLibraryOp<"mux", [ }]; } -class ArithBinaryPipeLibraryOp : ArithBinaryLibraryOp : ArithBinaryLibraryOp ]> { let results = (outs I1:$clk, I1:$reset, I1:$go, AnyType:$left, AnyType:$right, AnyType:$out, I1:$done); @@ -445,7 +445,7 @@ def RemUPipeLibOp : ArithBinaryPipeLibraryOp<"remu"> {} def RemSPipeLibOp : ArithBinaryPipeLibraryOp<"rems"> {} class UnaryLibraryOp traits = []> : - CalyxLibraryOp { + CalyxLibraryOp { let results = (outs AnyInteger:$in, AnyInteger:$out); } diff --git a/test/Conversion/SCFToCalyx/convert_simple.mlir b/test/Conversion/SCFToCalyx/convert_simple.mlir index 09cdbef0acfd..e298591104d5 100644 --- a/test/Conversion/SCFToCalyx/convert_simple.mlir +++ b/test/Conversion/SCFToCalyx/convert_simple.mlir @@ -265,7 +265,7 @@ module { // CHECK: %cst = calyx.constant @cst_0 <4.200000e+00 : f32> : i32 // CHECK-DAG: %true = hw.constant true // CHECK-DAG: %mulf_0_reg.in, %mulf_0_reg.write_en, %mulf_0_reg.clk, %mulf_0_reg.reset, %mulf_0_reg.out, %mulf_0_reg.done = calyx.register @mulf_0_reg : i32, i1, i1, i1, i32, i1 -// CHECK-DAG: %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.std_ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 +// CHECK-DAG: %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 // CHECK-DAG: %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1 // CHECK: calyx.group @bb0_0 { // CHECK-DAG: calyx.assign %std_mulFN_0.left = %in0 : i32 diff --git a/test/Dialect/Calyx/emit.mlir b/test/Dialect/Calyx/emit.mlir index c9b4fbfd039b..96d751a2cf51 100644 --- a/test/Dialect/Calyx/emit.mlir +++ b/test/Dialect/Calyx/emit.mlir @@ -291,7 +291,7 @@ module attributes {calyx.entrypoint = "main"} { %true = hw.constant true %false = hw.constant false %addf_0_reg.in, %addf_0_reg.write_en, %addf_0_reg.clk, %addf_0_reg.reset, %addf_0_reg.out, %addf_0_reg.done = calyx.register @addf_0_reg : i32, i1, i1, i1, i32, i1 - %std_addFN_0.clk, %std_addFN_0.reset, %std_addFN_0.go, %std_addFN_0.control, %std_addFN_0.subOp, %std_addFN_0.left, %std_addFN_0.right, %std_addFN_0.roundingMode, %std_addFN_0.out, %std_addFN_0.exceptionalFlags, %std_addFN_0.done = calyx.std_ieee754.add @std_addFN_0 : i1, i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 + %std_addFN_0.clk, %std_addFN_0.reset, %std_addFN_0.go, %std_addFN_0.control, %std_addFN_0.subOp, %std_addFN_0.left, %std_addFN_0.right, %std_addFN_0.roundingMode, %std_addFN_0.out, %std_addFN_0.exceptionalFlags, %std_addFN_0.done = calyx.ieee754.add @std_addFN_0 : i1, i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1 calyx.wires { calyx.assign %out0 = %ret_arg0_reg.out : i32 @@ -342,7 +342,7 @@ module attributes {calyx.entrypoint = "main"} { %cst = calyx.constant @cst_0 <4.200000e+00 : f32> : i32 %true = hw.constant true %mulf_0_reg.in, %mulf_0_reg.write_en, %mulf_0_reg.clk, %mulf_0_reg.reset, %mulf_0_reg.out, %mulf_0_reg.done = calyx.register @mulf_0_reg : i32, i1, i1, i1, i32, i1 - %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.std_ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 + %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1 %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1 calyx.wires { calyx.assign %out0 = %ret_arg0_reg.out : i32