From f124fb041dd0acf544154657d6ff166385ab7b62 Mon Sep 17 00:00:00 2001
From: Nandor Licker <n@ndor.email>
Date: Wed, 15 Nov 2023 05:55:56 -0800
Subject: [PATCH] [NFC][Seq] Fix the parsing of seq.firreg presets

---
 lib/Dialect/Seq/SeqOps.cpp       | 23 ++++++++++++++---------
 test/Dialect/Seq/round-trip.mlir |  6 ++++--
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/lib/Dialect/Seq/SeqOps.cpp b/lib/Dialect/Seq/SeqOps.cpp
index b77a3da6667b..b224c2256505 100644
--- a/lib/Dialect/Seq/SeqOps.cpp
+++ b/lib/Dialect/Seq/SeqOps.cpp
@@ -434,20 +434,25 @@ ParseResult FirRegOp::parse(OpAsmParser &parser, OperationState &result) {
       return failure();
   }
 
-  Type ty;
+  std::optional<int64_t> presetValue;
   if (succeeded(parser.parseOptionalKeyword("preset"))) {
-    IntegerAttr preset;
-    if (parser.parseAttribute(preset, "preset", result.attributes) ||
-        parser.parseOptionalAttrDict(result.attributes))
-      return failure();
-    ty = preset.getType();
-  } else {
-    if (parser.parseOptionalAttrDict(result.attributes) ||
-        parser.parseColon() || parser.parseType(ty))
+    int64_t presetInt;
+    if (parser.parseInteger(presetInt))
       return failure();
+    presetValue = presetInt;
   }
+
+  Type ty;
+  if (parser.parseOptionalAttrDict(result.attributes) || parser.parseColon() ||
+      parser.parseType(ty))
+    return failure();
   result.addTypes({ty});
 
+  if (presetValue) {
+    result.addAttribute("preset",
+                        parser.getBuilder().getIntegerAttr(ty, *presetValue));
+  }
+
   setNameFromResult(parser, result);
 
   if (parser.resolveOperand(next, ty, result.operands))
diff --git a/test/Dialect/Seq/round-trip.mlir b/test/Dialect/Seq/round-trip.mlir
index abe8fcb578c2..639bb21db507 100644
--- a/test/Dialect/Seq/round-trip.mlir
+++ b/test/Dialect/Seq/round-trip.mlir
@@ -75,8 +75,10 @@ hw.module @fifo2(in %clk : !seq.clock, in %rst : i1, in %in : i32, in %rdEn : i1
 
 
 hw.module @preset(in %clock : !seq.clock, in %reset : i1, in %next : i32) {
-  // CHECK: %reg = seq.firreg %next clock %clock preset 0 : i32
-  %reg = seq.firreg %next clock %clock preset 0 : i32
+  // CHECK: %a = seq.firreg %next clock %clock preset 0 : i32
+  %a = seq.firreg %next clock %clock preset 0 : i32
+  // CHECK: %b = seq.firreg %next clock %clock preset 0 {sv.namehint = "x"} : i32
+  %b = seq.firreg %next clock %clock preset 0 {sv.namehint = "x"} : i32
 }
 
 hw.module @clock_dividers(in %clock: !seq.clock) {