Some strange logic errors related to the netlist generated by OpenFPGA

[Chris202305]

@tangxifan First of all, I would like to express my sincere thanks for your previous answer, which effectively resolved my doubts. I have a new question now. I have written a simple circuit, and the simulation results are correct. This circuit includes some basic logic operations, primarily adding three numbers after left-shifting them by three bits using multiplication. Theoretically, the lower three bits of the result should be 0. However, after processing it through OpenFPGA and simulating the generated netlist, the simulation shows that these three bits are all 1. What could be causing this issue?

[tangxifan]

@Chris202305 Can you try to add the --constant_net_method route when calling vpr?

OpenFPGA/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga

Line 3 in d645748

vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route

[Chris202305]

"Your suggestion is very effective. I have an additional question. I'm trying to find the detailed information about the delays of some components in the 'report_timing.setup.rpt' file provided by OpenFPGA. Where can I find this section of the file?