The issues encountered when synthesizing the Verilog generated by OpenFPGA in Quartus #1443
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@Chris202305 I am not sure what is your motivation to use Quartus here. If you want to emulate the FPGA fabric, please do not throw any testbench into the tools such as Quartus, they are not synthesizable. Also FPGA has a lot of combinational loops, emualtion may be very challenging since Quartus is not designed for this. |
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Actually, I have successfully performed UART functionality simulation on the netlist generated by OpenFPGA using VCS. Now, I want to program the netlist generated by OpenFPGA onto an FPGA development board using Quartus and configure the eFPGA using a microcontroller. However, during the analysis and synthesis process in Quartus, it gets stuck without any error messages. It has been running for over 8 hours. Since there are no error messages, I suspect that the netlist might be too large. Prior to this, I successfully tested the demo netlist provided by OpenFPGA, where the AND2 gate functionality could be programmed onto the board. I'm curious if there is any way to solve this problem |
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Additionally, I prefer not to utilize the 'pass_gate' circuit structure in my circuitry as it sometimes leads to issues during synthesis. However, upon reviewing the documentation, it seems that the 'mux' of this type must use the 'pass_gate' submodule. Is there any way to implement the multiplexer ('mux') without employing the 'pass_gate'? |
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@Chris202305 Please check the documentation about multiplexer modeling: https://openfpga.readthedocs.io/en/master/manual/arch_lang/circuit_model_examples/#multiplexers If you are using one-level or multi-level MUXes, you have to use pass-gate. If you are using tree-like MUXes, you can use standard cells. If you use the standard cell MUX, you may refer to the example: https://github.com/lnis-uofu/OpenFPGA/tree/master/openfpga_flow/tasks/fpga_verilog/mux_design |
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In the 'grid_clb' module, I noticed a distinct combinational logic loop. Could you please explain the intended design purpose of this loop? I am attempting to modify the netlist generated by the openfpga open-source tool to burn onto a development board. Currently, I am trying to understand the functionality of the combinational logic loops in the netlist. My aim is to interrupt or modify the circuit in some other way to eliminate these loops and address the synthesis challenges with the netlist. Do you think my approach is feasible?
雨书
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发送时间: 2023年11月15日(星期三) 凌晨2:35
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主题: Re: [lnis-uofu/OpenFPGA] The issues encountered when synthesizing the Verilog generated by OpenFPGA in Quartus (Discussion #1443)
@Chris202305 I am not sure what is your motivation to use Quartus here. If you want to emulate the FPGA fabric, please do not throw any testbench into the tools such as Quartus, they are not synthesizable. Also FPGA has a lot of combinational loops, emualtion may be very challenging since Quartus is not designed for this.
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@Chris202305 The combinational loop, which comes from the local routing of CLB, is essential to the FPGA architecture that you are looking into. To understand the local routing, I suggest you to read
Removing the comb. loop will cause fatal failures in your netlists. As a result, bitstream is wrong, and you cannot verify your FPGA fabric. |
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Thank you very much for your guidance. I have read your articles, and I finally have a better understanding of the structure of FPGAs.
In continuation of my previous question, I would like to inquire about how to control the layout and routing size of the generated eFPGA in an automated workflow. For instance, through calculations, I have determined that I only want to use 4 CLBs to construct an eFPGA. How can I use specific commands to constrain the tools and ensure that the number of CLBs is limited to 4? Modifying the CLB size or enhancing functional blocks might not necessarily shrink it to the desired size. What specific approach should I follow in this automated process?
雨书
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发送时间: 2023年12月6日(星期三) 凌晨3:18
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主题: Re: [lnis-uofu/OpenFPGA] The issues encountered when synthesizing the Verilog generated by OpenFPGA in Quartus (Discussion #1443)
@Chris202305 The combinational loop, which comes from the local routing of CLB, is essential to the FPGA architecture that you are looking into. To understand the local routing, I suggest you to read
My PhD thesis: https://infoscience.epfl.ch/record/232440 pp. 42-44
Prof. Vaughn Betz thesis: https://tspace.library.utoronto.ca/handle/1807/12758 Chapter 6
Removing the comb. loop will cause fatal failures in your netlists. As a result, bitstream is wrong, and you cannot verify your FPGA fabric.
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Thank you very much for your guidance. I have read your articles, and I finally have a better understanding of the structure of FPGAs.
In continuation of my previous question, I would like to inquire about how to control the layout and routing size of the generated eFPGA in an automated workflow. For instance, through calculations, I have determined that I only want to use 4 CLBs to construct an eFPGA. How can I use specific commands to constrain the tools and ensure that the number of CLBs is limited to 4? Modifying the CLB size or enhancing functional blocks might not necessarily shrink it to the desired size. What specific approach should I follow in this automated process?
In the VTR documentation, I found information about layout, that have solved some questions above， but I haven't found details on how to set the height and width of specific modules, such as the default 1x1 dimensions for CLBs. If I want to set it to 2x3 and then proceed with the layout, how should I handle this？
Oh，I have found my answers，Please forgive my impatience; I may have caused some confusion. I truly see you as a teacher, and I apologize for not thoroughly reading the documentation. Feel free to ask if there's anything I don't understand.
雨书
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…------------------ 原始邮件 ------------------
发件人: "lnis-uofu/OpenFPGA" ***@***.***>;
发送时间: 2023年12月6日(星期三) 凌晨3:18
***@***.***>;
***@***.******@***.***>;
主题: Re: [lnis-uofu/OpenFPGA] The issues encountered when synthesizing the Verilog generated by OpenFPGA in Quartus (Discussion #1443)
@Chris202305 The combinational loop, which comes from the local routing of CLB, is essential to the FPGA architecture that you are looking into. To understand the local routing, I suggest you to read
My PhD thesis: https://infoscience.epfl.ch/record/232440 pp. 42-44
Prof. Vaughn Betz thesis: https://tspace.library.utoronto.ca/handle/1807/12758 Chapter 6
Removing the comb. loop will cause fatal failures in your netlists. As a result, bitstream is wrong, and you cannot verify your FPGA fabric.
—
Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you were mentioned.Message ID: ***@***.***>
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Long time no see, Mr. Tang. I have another question for you. After testing some simple combinatorial logic circuits, I designed a basic UART circuit. After simulating it without any issues, I used a series of OpenFPGA tools to convert it into a set of Verilog files. When I tried to analyze and synthesize them using Quartus, the process got stuck，no progress, and no error reported. Is this related to the large resource consumption of the netlist generated by OpenFPGA? Are there any methods or techniques to reduce the netlist size or compress the resources occupied by the eFPGA?
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