Fpga fabric behavioral simulation

[YazanBaddour]

hello i created FPGA fabric that is very similar to the original k4n4 tileable fabric found in OpenFpga repository i just made the IO to be embedded and used a module from the gpio.v
I am seeing some delay in my behavioral simulation all soc outputs should rise and fall together but there is a delay. as shown i am using modelsim for simulation , i tried to remove the time enable but them the simulator never converges. any help would be appreciated to understand why i am seeing delay in behavioral simulation of the fabric , attached a pic of the waveforms and the files of the fabric
openfpgaarch.txt

xmlarch.txt
task.txt

and if someone coul provide me where to find good tutorial for floorplanning and pnr of hierarchical design using cadence innovus as i trying to follow the flow of this paper A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs
i did not understand how they cut the modules in rectilinear shape while maintaining utilization.
thank you so much