FPGA simulation question

[chaitalisathe]

Hello,

I am using full_testbench to generate and verify FPGA fabric.
When I ran the script "python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain", it generated bitstream (for eg.) of a size 2772 bits. Then simulation started, and it ran halfway through and then hanged up. When I checked simulation timing, it looked like that only half of the bitstream was loaded and then it just hanged.

When I checked vvp_sim_output.txt file, it was empty.

Is this known issue? Please let me know how to solve this one.

Thank you,
Chaitali

after this, there is no further activity on the terminal

[chaitalisathe]

Issue is found. There is a mismatch in input ports in netlist generated by yosys and original benchmark.

Not sure how to resolve it.

Thank you,

Chaitali