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[tangxifan]

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[ganeshgore]

This is great

[Gurusatwik]

How does OpenFPGA generate SDC files? Based on what technology are the clock frequency along with delays set? To which technology node is the Standard cell mapped to?

[tangxifan]

@Gurusatwik

• You may refer to the https://openfpga.readthedocs.io/en/master/manual/openfpga_shell/openfpga_commands/fpga_sdc_commands/ for SDC generation. Note that SDC files are highly related to your case. So, there are plenty of options for your actual needs.
• You can provide the clock frequency through the simulation setting file https://openfpga.readthedocs.io/en/master/manual/arch_lang/simulation_setting/ SDC generator will honor it.
• There is no restrictions on technology. You define what you want. We have silicon proofs on TSMC 22nm, Skywater 180nm etc. Researchers have tried a wide range of technologies, from 180nm down to 12nm. No issues shown.

[Gurusatwik]

• When the operating frequency is set to "auto", how will the VPR STA Engine analyze the maximum operating frequency of the fabric? It must need a standard cell library to analyze if I am not wrong.
• Isn't there any standard cell library in OpenFPGA to which the Fabric netlists are mapped to?
• What is the theory behind the frequency value set for clk[0] as shown in the below image?