How does the clock pin connect the routing channels?

[aaron941223]

I am a green hand to learn this project. This may be a simple problem but I haven't find the solution.

I used VTR to find the blocks and pins connection. I found that the clock signal for IOB or CLB has no local connection. The clock for all FFs should come from the global clock source.

But when I run Openfpga to generate a simple fabric RTL code, I found that the clock pin of CLB connected with the routing channels and followed the Fcin. I didn't find the corresponding settings in VPR arch xml. Where can I set this?

By the way, should I prepare an openfpga arch xml along with a vpr arch xml for the same fabric?

[Chris202305]

May I ask if the question has been resolved? As a newbie，I also want to know should I prepare an openfpga arch xml and a vpr arch xml. By the way, what's the difference between them？

[tangxifan]

@Chris202305
In short, the OpenFPGA architecture XML provides detailed information about circuit modeling for an FPGA fabric, while VPR's architecture description provides abstract-level information. Without OpenFPGA architecture, you can only model a hypothetical FPGA device at a high-level abstraction but cannot convert it into a phyiscal description, i.e., Verilog netlists. It means you want to prototype your FPGA architecture (convert the architecture description into physical layout, you need the OpenFPGA architecture XML).

You may find more details about the architecture XML.
https://openfpga.readthedocs.io/en/master/manual/arch_lang/generality/