From a8f322f588d70fff3329c9e5fcedee01d30bc797 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 13:21:52 -0700 Subject: [PATCH 1/9] [lib] update vtr to latest --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 9eef18c4f..83f8bfeb0 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 9eef18c4facb5dad0604682e6e5d3d904b97f6d8 +Subproject commit 83f8bfeb065b48b1f860faf88a65fef625f79d56 From 9423f6ba3d999a2f6adfbf850f3355c70471a4c3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 13:58:41 -0700 Subject: [PATCH 2/9] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 83f8bfeb0..9ddf4ca42 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 83f8bfeb065b48b1f860faf88a65fef625f79d56 +Subproject commit 9ddf4ca42db3a0f833a264a21eafcc0b93d1bf85 From 4f96680e1f9417c7ec0107ee1b674a570fb97f00 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 14:20:48 -0700 Subject: [PATCH 3/9] [core] adapt to side var changes --- .../src/openfpga_side_manager.cpp | 12 ++++---- libs/libpcf/src/base/io_pin_table.cpp | 2 +- libs/libpcf/src/io/write_csv_io_pin_table.cpp | 2 +- .../src/annotation/annotate_placement.cpp | 6 ++-- openfpga/src/annotation/annotate_rr_graph.cpp | 6 ++-- .../annotation/openfpga_annotate_routing.cpp | 2 +- .../annotation/write_xml_device_rr_gsb.cpp | 2 +- openfpga/src/base/openfpga_naming.cpp | 8 ++--- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 12 ++++---- .../src/fabric/build_grid_module_utils.cpp | 2 +- openfpga/src/fabric/build_grid_modules.cpp | 4 +-- .../src/fabric/build_routing_module_utils.cpp | 16 +++++----- ...top_module_child_fine_grained_instance.cpp | 4 +-- .../build_top_module_child_tile_instance.cpp | 2 +- .../fabric/build_top_module_connection.cpp | 2 +- .../src/fabric/build_top_module_memory.cpp | 2 +- .../src/fabric/build_top_module_utils.cpp | 4 +-- openfpga/src/fabric/module_manager.cpp | 2 +- .../fpga_bitstream/build_grid_bitstream.cpp | 2 +- .../fpga_bitstream/build_io_mapping_info.cpp | 6 ++-- .../extract_device_non_fabric_bitstream.cpp | 2 +- .../src/fpga_sdc/analysis_sdc_grid_writer.cpp | 2 +- openfpga/src/fpga_sdc/analysis_sdc_writer.cpp | 6 ++-- openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 2 +- .../src/fpga_sdc/sdc_hierarchy_writer.cpp | 4 +-- openfpga/src/fpga_spice/spice_grid.cpp | 6 ++-- openfpga/src/fpga_verilog/verilog_grid.cpp | 2 +- .../verilog_mock_fpga_wrapper.cpp | 6 ++-- .../verilog_simulation_info_writer.cpp | 6 ++-- .../fpga_verilog/verilog_testbench_utils.cpp | 6 ++-- .../src/tile_direct/build_tile_direct.cpp | 30 +++++++++---------- .../utils/openfpga_physical_tile_utils.cpp | 8 ++--- 32 files changed, 89 insertions(+), 89 deletions(-) diff --git a/libs/libopenfpgautil/src/openfpga_side_manager.cpp b/libs/libopenfpgautil/src/openfpga_side_manager.cpp index 4540984c8..0d9b04dd8 100644 --- a/libs/libopenfpgautil/src/openfpga_side_manager.cpp +++ b/libs/libopenfpgautil/src/openfpga_side_manager.cpp @@ -9,7 +9,7 @@ namespace openfpga { /* Constructors */ SideManager::SideManager(enum e_side side) { side_ = side; } -SideManager::SideManager() { side_ = NUM_SIDES; } +SideManager::SideManager() { side_ = NUM_2D_SIDES; } SideManager::SideManager(size_t side) { set_side(side); } @@ -27,7 +27,7 @@ enum e_side SideManager::get_opposite() const { case LEFT: return RIGHT; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -42,7 +42,7 @@ enum e_side SideManager::get_rotate_clockwise() const { case LEFT: return TOP; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } @@ -57,12 +57,12 @@ enum e_side SideManager::get_rotate_counterclockwise() const { case LEFT: return BOTTOM; default: - return NUM_SIDES; + return NUM_2D_SIDES; } } bool SideManager::validate() const { - if (NUM_SIDES == side_) { + if (NUM_2D_SIDES == side_) { return false; } return true; @@ -139,7 +139,7 @@ void SideManager::set_side(size_t side) { side_ = LEFT; return; default: - side_ = NUM_SIDES; + side_ = NUM_2D_SIDES; return; } } diff --git a/libs/libpcf/src/base/io_pin_table.cpp b/libs/libpcf/src/base/io_pin_table.cpp index 64f304acf..085ebd8c2 100644 --- a/libs/libpcf/src/base/io_pin_table.cpp +++ b/libs/libpcf/src/base/io_pin_table.cpp @@ -84,7 +84,7 @@ IoPinTableId IoPinTable::create_pin() { pin_ids_.push_back(pin_id); internal_pins_.emplace_back(); external_pins_.emplace_back(); - pin_sides_.emplace_back(NUM_SIDES); + pin_sides_.emplace_back(NUM_2D_SIDES); pin_directions_.emplace_back(NUM_IO_DIRECTIONS); return pin_id; diff --git a/libs/libpcf/src/io/write_csv_io_pin_table.cpp b/libs/libpcf/src/io/write_csv_io_pin_table.cpp index 48b74d324..3a6c832be 100644 --- a/libs/libpcf/src/io/write_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/write_csv_io_pin_table.cpp @@ -52,7 +52,7 @@ int write_csv_io_pin_table(const char* fname, const IoPinTable& io_pin_table) { /* Print data */ for (const IoPinTableId& pin_id : io_pin_table.pins()) { std::vector data_row_str; - data_row_str.push_back(SIDE_STRING[io_pin_table.pin_side(pin_id)]); + data_row_str.push_back(TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]); data_row_str.push_back( generate_xml_port_name(io_pin_table.internal_pin(pin_id))); data_row_str.push_back( diff --git a/openfpga/src/annotation/annotate_placement.cpp b/openfpga/src/annotation/annotate_placement.cpp index bf7d0b895..6e6450095 100644 --- a/openfpga/src/annotation/annotate_placement.cpp +++ b/openfpga/src/annotation/annotate_placement.cpp @@ -25,10 +25,10 @@ void annotate_mapped_blocks(const DeviceContext& device_ctx, place_annotation.init_mapped_blocks(device_ctx.grid); for (const ClusterBlockId& blk_id : cluster_ctx.clb_nlist.blocks()) { - vtr::Point grid_coord(place_ctx.block_locs[blk_id].loc.x, - place_ctx.block_locs[blk_id].loc.y); + vtr::Point grid_coord(place_ctx.block_locs()[blk_id].loc.x, + place_ctx.block_locs()[blk_id].loc.y); place_annotation.add_mapped_block( - grid_coord, place_ctx.block_locs[blk_id].loc.sub_tile, blk_id); + grid_coord, place_ctx.block_locs()[blk_id].loc.sub_tile, blk_id); } VTR_LOG("Done\n"); } diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 373607fb2..5f325d0a7 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -120,7 +120,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, rr_gsb.get_side_block_coordinate(side_manager.get_side()); RRChan rr_chan; std::vector> temp_opin_rr_nodes(2); - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; + enum e_side opin_grid_side[2] = {NUM_2D_SIDES, NUM_2D_SIDES}; enum PORTS chan_dir_to_port_dir_mapping[2] = { OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ @@ -301,8 +301,8 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Clear the temp data */ temp_opin_rr_nodes[0].clear(); temp_opin_rr_nodes[1].clear(); - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; + opin_grid_side[0] = NUM_2D_SIDES; + opin_grid_side[1] = NUM_2D_SIDES; } /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index afd0dc69f..384cf9041 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -42,7 +42,7 @@ vtr::vector annotate_rr_node_global_net( for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); t_block_loc blk_loc = get_block_loc(block_id, false); - int phy_pin = placement_ctx.physical_pins[pin_id]; + int phy_pin = placement_ctx.physical_pins()[pin_id]; t_physical_tile_type_ptr phy_tile = device_ctx.grid.get_physical_type( t_physical_tile_loc(blk_loc.loc.x, blk_loc.loc.y, 0)); int node_pin_num = phy_tile->num_pins; diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 1dd447d25..552ee361a 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -149,7 +149,7 @@ static void write_rr_gsb_chan_connection_to_xml( } else { for (const RREdgeId& driver_rr_edge : driver_rr_edges) { const RRNodeId& driver_rr_node = rr_graph.edge_src_node(driver_rr_edge); - e_side driver_node_side = NUM_SIDES; + e_side driver_node_side = NUM_2D_SIDES; int driver_node_index = -1; rr_gsb.get_node_side_and_index(rr_graph, driver_rr_node, IN_PORT, driver_node_side, driver_node_index); diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index c76273935..9fb186674 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -1091,7 +1091,7 @@ std::string generate_grid_block_prefix(const std::string& prefix, const e_side& io_side) { std::string block_prefix(prefix); - if (NUM_SIDES != io_side) { + if (NUM_2D_SIDES != io_side) { SideManager side_manager(io_side); block_prefix += std::string(side_manager.to_string()); block_prefix += std::string("_"); @@ -1110,7 +1110,7 @@ std::string generate_grid_block_netlist_name(const std::string& block_name, /* Add the name of physical block */ std::string module_name(block_name); - if ((true == is_block_io) && (NUM_SIDES != io_side)) { + if ((true == is_block_io) && (NUM_2D_SIDES != io_side)) { SideManager side_manager(io_side); module_name += std::string("_"); module_name += std::string(side_manager.to_string()); @@ -1385,7 +1385,7 @@ std::string generate_physical_block_instance_name(t_pb_type* pb_type, * This function try to infer if a grid locates at the border of a * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides * 1. if this grid is on the border, it will return the side it locates, - * 2. if this grid is in the center, it will return an valid value NUM_SIDES + * 2. if this grid is in the center, it will return an valid value NUM_2D_SIDES * * In this function, we assume that the corner grids are actually empty! * @@ -1412,7 +1412,7 @@ std::string generate_physical_block_instance_name(t_pb_type* pb_type, *******************************************************************/ e_side find_grid_border_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate) { - e_side grid_side = NUM_SIDES; + e_side grid_side = NUM_2D_SIDES; if (device_size.y() - 1 == grid_coordinate.y()) { return TOP; diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 79c73e327..53fb390cc 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -179,8 +179,8 @@ static int update_cluster_pin_with_post_routing_results( * but the expected side (only used side) will be opposite side of the * border side! */ - e_side pin_side = NUM_SIDES; - if (NUM_SIDES == border_side) { + e_side pin_side = NUM_2D_SIDES; + if (NUM_2D_SIDES == border_side) { if (1 != pin_sides.size()) { VTR_LOG_ERROR( "For tile '%s', found pin '%s' on %lu sides. Expect only 1. " @@ -377,7 +377,7 @@ int update_pb_pin_with_post_routing_results( /* Get the mapped blocks to this grid */ for (int isubtile = 0; isubtile < phy_tile->capacity; ++isubtile) { ClusterBlockId cluster_blk_id = - placement_ctx.grid_blocks.block_at_location( + placement_ctx.grid_blocks().block_at_location( {(int)x, (int)y, (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { @@ -389,7 +389,7 @@ int update_pb_pin_with_post_routing_results( status = update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, - NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, + NUM_2D_SIDES, placement_ctx.block_locs()[cluster_blk_id].loc.sub_tile, perimeter_cb, map_gnet2msb, num_fixup, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; @@ -414,7 +414,7 @@ int update_pb_pin_with_post_routing_results( /* Get the mapped blocks to this grid */ for (int isubtile = 0; isubtile < phy_tile_type->capacity; ++isubtile) { ClusterBlockId cluster_blk_id = - placement_ctx.grid_blocks.block_at_location( + placement_ctx.grid_blocks().block_at_location( {(int)io_coord.x(), (int)io_coord.y(), (int)isubtile, (int)layer}); /* Skip invalid ids */ if (ClusterBlockId::INVALID() == cluster_blk_id) { @@ -424,7 +424,7 @@ int update_pb_pin_with_post_routing_results( status = update_cluster_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side, - placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, perimeter_cb, + placement_ctx.block_locs()[cluster_blk_id].loc.sub_tile, perimeter_cb, map_gnet2msb, num_fixup, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 812038b10..f1b18bdba 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -30,7 +30,7 @@ std::vector find_grid_module_pin_sides( VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); - if (NUM_SIDES == border_side) { + if (NUM_2D_SIDES == border_side) { return {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 051a53f4f..30ad0995c 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -1430,7 +1430,7 @@ int build_grid_modules( * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as regular + * we will generate one module with NUM_2D_SIDES (same treatment as regular * grids) */ std::set io_type_sides = @@ -1449,7 +1449,7 @@ int build_grid_modules( /* For CLB and heterogenenous blocks */ status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, - sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, + sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_2D_SIDES, ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index b8f9b4c0d..f340d0f5b 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -143,7 +143,7 @@ ModulePinInfo find_switch_block_module_chan_port( int index = rr_gsb.get_node_index(rr_graph, cur_rr_node, chan_side, cur_rr_node_direction); /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index) && (NUM_SIDES != chan_side)); + VTR_ASSERT((-1 != index) && (NUM_2D_SIDES != chan_side)); std::string chan_port_name = generate_sb_module_track_port_name( rr_graph.node_type(rr_gsb.get_chan_node(chan_side, index)), chan_side, @@ -194,7 +194,7 @@ ModulePinInfo find_switch_block_module_input_port( /* Find the side where the grid pin locates in the grid */ enum e_side grid_pin_side = get_rr_graph_single_node_side(rr_graph, input_rr_node); - VTR_ASSERT(NUM_SIDES != grid_pin_side); + VTR_ASSERT(NUM_2D_SIDES != grid_pin_side); std::string input_port_name = generate_sb_module_grid_port_name( input_side, grid_pin_side, grids, vpr_device_annotation, rr_graph, @@ -235,12 +235,12 @@ std::vector find_switch_block_module_input_ports( for (const RRNodeId& input_rr_node : input_rr_nodes) { /* Find the side where the input locates in the Switch Block */ - enum e_side input_pin_side = NUM_SIDES; + enum e_side input_pin_side = NUM_2D_SIDES; /* The input could be at any side of the switch block, find it */ int index = -1; rr_gsb.get_node_side_and_index(rr_graph, input_rr_node, IN_PORT, input_pin_side, index); - VTR_ASSERT(NUM_SIDES != input_pin_side); + VTR_ASSERT(NUM_2D_SIDES != input_pin_side); VTR_ASSERT(-1 != index); input_ports.push_back(find_switch_block_module_input_port( @@ -302,12 +302,12 @@ ModulePortId find_connection_block_module_ipin_port( rr_graph.node_ylow(src_rr_node)); /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_ipin_side = NUM_SIDES; + enum e_side cb_ipin_side = NUM_2D_SIDES; int cb_ipin_index = -1; rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, OUT_PORT, cb_ipin_side, cb_ipin_index); /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_ipin_index) && (NUM_SIDES != cb_ipin_side)); + VTR_ASSERT((-1 != cb_ipin_index) && (NUM_2D_SIDES != cb_ipin_side)); std::string port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, vpr_device_annotation, rr_graph, rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)); @@ -332,12 +332,12 @@ ModulePortId find_connection_block_module_opin_port( VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node)); /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_opin_side = NUM_SIDES; + enum e_side cb_opin_side = NUM_2D_SIDES; int cb_opin_index = -1; rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side, cb_opin_index); /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); std::string port_name = generate_cb_module_grid_port_name( cb_opin_side, grids, vpr_device_annotation, rr_graph, rr_gsb.get_opin_node(cb_opin_side, cb_opin_index)); diff --git a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp index 914e384e1..990472856 100644 --- a/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp @@ -173,7 +173,7 @@ static vtr::Matrix add_top_module_grid_instances( /* Add a grid module to top_module*/ vtr::Point grid_coord(ix, iy); grid_instance_ids[ix][iy] = add_top_module_grid_instance( - module_manager, top_module, phy_tile_type, NUM_SIDES, grid_coord); + module_manager, top_module, phy_tile_type, NUM_2D_SIDES, grid_coord); } } @@ -427,7 +427,7 @@ static void add_top_module_io_children( std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_module_name = generate_grid_block_module_name( grid_module_name_prefix, std::string(grid_type->name), - is_io_type(grid_type), NUM_SIDES); + is_io_type(grid_type), NUM_2D_SIDES); ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); /* Add a I/O children to top_module*/ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 47f9e3051..3ff540266 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1539,7 +1539,7 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile, + vtr::Point(ix, iy), NUM_2D_SIDES, tile_instance_ids, fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 4de2ddf0d..91ae8f363 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1174,7 +1174,7 @@ static int build_top_module_global_net_from_grid_modules( status = build_top_module_global_net_for_given_grid_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_SIDES, grid_instance_ids, + vtr::Point(ix, iy), NUM_2D_SIDES, grid_instance_ids, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index d9d65fbc2..756985d29 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -529,7 +529,7 @@ void organize_top_module_memory_modules( module_manager, top_module, circuit_lib, config_protocol.type(), sram_model, grids, grid_instance_ids, device_rr_gsb, rr_graph, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, layer, - core_coord, NUM_SIDES); + core_coord, NUM_2D_SIDES); } /* Split memory modules into different regions */ diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index 8b7c8f2e6..586163bfa 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -79,7 +79,7 @@ std::string generate_grid_module_port_name_in_top_module( * RIGHT/LEFT side: CHANX *******************************************************************/ t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); + VTR_ASSERT(NUM_2D_SIDES != sb_side); if ((TOP == sb_side) || (BOTTOM == sb_side)) { return CHANY; @@ -96,7 +96,7 @@ t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { *******************************************************************/ vtr::Point find_top_module_gsb_coordinate_by_sb_side( const RRGSB& rr_gsb, const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); + VTR_ASSERT(NUM_2D_SIDES != sb_side); vtr::Point gsb_coordinate; diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 178a3b33f..82aa1732a 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -797,7 +797,7 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, ports_[module].push_back(port_info); port_types_[module].push_back(port_type); /* Deposit invalid value for each side */ - port_sides_[module].push_back(NUM_SIDES); + port_sides_[module].push_back(NUM_2D_SIDES); port_is_wire_[module].push_back(false); port_is_mappable_io_[module].push_back(false); port_is_register_[module].push_back(false); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index d8e4f17fb..cbc5e99b1 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -1007,7 +1007,7 @@ void build_grid_bitstream( bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, place_annotation, - bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose); + bitstream_annotation, grids, layer, grid_coord, NUM_2D_SIDES, verbose); } } VTR_LOGV(verbose, "Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp index 77c7b3e8a..9a26e8a1f 100644 --- a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp @@ -90,9 +90,9 @@ IoMap build_fpga_io_mapping_info( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ diff --git a/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp index 3793c1b3d..b4fcd7851 100644 --- a/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/extract_device_non_fabric_bitstream.cpp @@ -154,7 +154,7 @@ static void extract_device_non_fabric_pb_bitstream( // Get the mapped blocks to this grid for (int isubtile = 0; isubtile < grid_type->capacity; ++isubtile) { ClusterBlockId cluster_blk_id = - placement_ctx.grid_blocks.block_at_location( + placement_ctx.grid_blocks().block_at_location( {(int)ix, (int)iy, (int)isubtile, (int)layer}); if (grid_count) { fp << ","; diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp index 2de04a881..d2e673c2b 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp @@ -693,7 +693,7 @@ void print_analysis_sdc_disable_unused_grids( for (size_t iy = 1; iy < grids.height() - 1; ++iy) { print_analysis_sdc_disable_unused_grid( fp, vtr::Point(ix, iy), grids, device_annotation, - cluster_annotation, place_annotation, module_manager, NUM_SIDES); + cluster_annotation, place_annotation, module_manager, NUM_2D_SIDES); } } diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp index 65a0d3efa..11e5e5908 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp @@ -120,9 +120,9 @@ static void print_analysis_sdc_io_delays( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); if (size_t(-1) == io_index) { diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp index ae8b42781..56a63a595 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp @@ -593,7 +593,7 @@ void print_pnr_sdc_constrain_grid_timing( /* For CLB and heterogenenous blocks */ std::string grid_module_name = generate_grid_block_module_name( std::string(GRID_MODULE_NAME_PREFIX), std::string(physical_tile.name), - is_io_type(&physical_tile), NUM_SIDES); + is_io_type(&physical_tile), NUM_2D_SIDES); /* Find the module Id */ ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp index f2ae08864..42d434617 100644 --- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp +++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp @@ -323,7 +323,7 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir, * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as + * we will generate one module with NUM_2D_SIDES (same treatment as * regular grids) */ std::set io_type_sides = @@ -361,7 +361,7 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir, /* For CLB and heterogenenous blocks */ std::string grid_module_name = generate_grid_block_module_name( std::string(GRID_MODULE_NAME_PREFIX), std::string(physical_tile.name), - is_io_type(&physical_tile), NUM_SIDES); + is_io_type(&physical_tile), NUM_2D_SIDES); /* Find the module Id */ ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); diff --git a/openfpga/src/fpga_spice/spice_grid.cpp b/openfpga/src/fpga_spice/spice_grid.cpp index fee98b43f..6826cd4ba 100644 --- a/openfpga/src/fpga_spice/spice_grid.cpp +++ b/openfpga/src/fpga_spice/spice_grid.cpp @@ -274,7 +274,7 @@ static void print_spice_physical_tile_netlist( const e_side& border_side) { /* Check code: if this is an IO block, the border side MUST be valid */ if (true == is_io_type(phy_block_type)) { - VTR_ASSERT(NUM_SIDES != border_side); + VTR_ASSERT(NUM_2D_SIDES != border_side); } /* Give a name to the Verilog netlist */ @@ -393,7 +393,7 @@ void print_spice_grids(NetlistManager& netlist_manager, * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_SIDES (same treatment as regular + * we will generate one module with NUM_2D_SIDES (same treatment as regular * grids) */ std::set io_type_sides = @@ -407,7 +407,7 @@ void print_spice_grids(NetlistManager& netlist_manager, } else { /* For CLB and heterogenenous blocks */ print_spice_physical_tile_netlist(netlist_manager, module_manager, - subckt_dir, &physical_tile, NUM_SIDES); + subckt_dir, &physical_tile, NUM_2D_SIDES); } } VTR_LOG("Building physical tiles..."); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index f5cc2acf4..8d6fbf513 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -445,7 +445,7 @@ void print_verilog_grids( /* For CLB and heterogenenous blocks */ print_verilog_physical_tile_netlist( netlist_manager, module_manager, module_name_map, subckt_dir, - subckt_dir_name, &physical_tile, NUM_SIDES, options); + subckt_dir_name, &physical_tile, NUM_2D_SIDES, options); } } VTR_LOG("Building physical tiles..."); diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp index ad238dbf2..6f38c9cef 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp @@ -115,9 +115,9 @@ static void print_verilog_mock_fpga_wrapper_connect_ios( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index 3eb2a209e..b1c46742d 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -137,9 +137,9 @@ void print_verilog_simulation_info( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); if (size_t(-1) == io_index) { diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 02fc49737..1468a188a 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -383,9 +383,9 @@ void print_verilog_testbench_connect_fpga_ios( /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp index 357c0a25c..39cd6ce44 100644 --- a/openfpga/src/tile_direct/build_tile_direct.cpp +++ b/openfpga/src/tile_direct/build_tile_direct.cpp @@ -60,14 +60,14 @@ static std::string parse_direct_port(const std::string& direct_tile_inf) { /*************************************************************************************** * Check if a pin is located on a given side of physical tile - * If the given side is NUM_SIDES, we will search all the sides + * If the given side is NUM_2D_SIDES, we will search all the sides ***************************************************************************************/ static bool is_pin_locate_at_physical_tile_side( t_physical_tile_type_ptr physical_tile, const size_t& pin_width_offset, const size_t& pin_height_offset, const size_t& pin_id, const e_side& pin_side) { - if (NUM_SIDES == pin_side) { - for (size_t side = 0; side < NUM_SIDES; ++side) { + if (NUM_2D_SIDES == pin_side) { + for (size_t side = 0; side < NUM_2D_SIDES; ++side) { if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset] [side][pin_id]) { return true; @@ -418,7 +418,7 @@ static void build_inner_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -453,7 +453,7 @@ static void build_inner_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -482,10 +482,10 @@ static void build_inner_column_row_tile_direct( "%s[%lu][%lu].%s[%lu] at side '%s'\n", from_tile_name.c_str(), x, y, from_tile_port.get_name().c_str(), from_pins[ipin], - SIDE_STRING[from_side], to_tile_name.c_str(), + TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct( from_grid_coord, from_side, from_pins[ipin], to_grid_coord, to_side, to_pins[ipin]); @@ -593,7 +593,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -623,7 +623,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -655,10 +655,10 @@ static void build_inter_column_row_tile_direct( "%s[%lu][%lu].%s[%lu] at side '%s'\n", from_tile_name.c_str(), from_grid_coord.x(), from_grid_coord.y(), from_tile_port.get_name().c_str(), - from_pins[ipin], SIDE_STRING[from_side], + from_pins[ipin], TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct( from_grid_coord, from_side, from_pins[ipin], to_grid_coord, @@ -704,7 +704,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the from pin may locate any side! - * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.from_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -734,7 +734,7 @@ static void build_inter_column_row_tile_direct( } /* Search all the sides, the to pin may locate any side! - * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized + * Note: the vpr_direct.to_side is NUM_2D_SIDES, which is unintialized * This should be reported to VPR!!! */ for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) { @@ -766,10 +766,10 @@ static void build_inter_column_row_tile_direct( "at side '%s'\n", from_tile_name.c_str(), from_grid_coord.x(), from_grid_coord.y(), from_tile_port.get_name().c_str(), - from_pins[ipin], SIDE_STRING[from_side], + from_pins[ipin], TOTAL_2D_SIDE_STRINGS[from_side], to_tile_name.c_str(), to_grid_coord.x(), to_grid_coord.y(), to_tile_port.get_name().c_str(), to_pins[ipin], - SIDE_STRING[to_side]); + TOTAL_2D_SIDE_STRINGS[to_side]); TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, from_side, from_pins[ipin], diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp index 3a256639d..f8f16db64 100644 --- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp +++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp @@ -45,7 +45,7 @@ std::vector find_physical_tile_pin_side( * - When perimeter cb is on, the expected sides can be on any sides except * the border side. But we only expect 1 side */ - if (NUM_SIDES == border_side) { + if (NUM_2D_SIDES == border_side) { VTR_ASSERT(1 == pin_sides.size()); } else if (!perimeter_cb) { SideManager side_manager(border_side); @@ -92,10 +92,10 @@ std::set find_physical_io_tile_located_sides( /* Search the core part */ for (size_t ix = 1; ix < grids.width() - 1; ++ix) { for (size_t iy = 1; iy < grids.height() - 1; ++iy) { - /* If located in center, we add a NUM_SIDES and finish */ + /* If located in center, we add a NUM_2D_SIDES and finish */ if (physical_tile == grids.get_physical_type(t_physical_tile_loc(ix, iy, 0))) { - io_sides.insert(NUM_SIDES); + io_sides.insert(NUM_2D_SIDES); center_io = true; break; } @@ -112,7 +112,7 @@ std::set find_physical_io_tile_located_sides( for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) { for (const vtr::Point& io_coordinate : io_coordinates[fpga_side]) { - /* If located in center, we add a NUM_SIDES and finish */ + /* If located in center, we add a NUM_2D_SIDES and finish */ if (physical_tile == grids.get_physical_type(t_physical_tile_loc( io_coordinate.x(), io_coordinate.y(), 0))) { io_sides.insert(fpga_side); From b9a0b1cdf87486ea873acd05f2754754f4050586 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 14:21:19 -0700 Subject: [PATCH 4/9] [core] code format --- libs/libpcf/src/io/write_csv_io_pin_table.cpp | 3 ++- openfpga/src/fabric/build_grid_modules.cpp | 10 +++++----- .../fabric/build_top_module_child_tile_instance.cpp | 4 ++-- openfpga/src/fpga_spice/spice_grid.cpp | 7 ++++--- .../fpga_verilog/verilog_simulation_info_writer.cpp | 3 ++- 5 files changed, 15 insertions(+), 12 deletions(-) diff --git a/libs/libpcf/src/io/write_csv_io_pin_table.cpp b/libs/libpcf/src/io/write_csv_io_pin_table.cpp index 3a6c832be..218ff101a 100644 --- a/libs/libpcf/src/io/write_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/write_csv_io_pin_table.cpp @@ -52,7 +52,8 @@ int write_csv_io_pin_table(const char* fname, const IoPinTable& io_pin_table) { /* Print data */ for (const IoPinTableId& pin_id : io_pin_table.pins()) { std::vector data_row_str; - data_row_str.push_back(TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]); + data_row_str.push_back( + TOTAL_2D_SIDE_STRINGS[io_pin_table.pin_side(pin_id)]); data_row_str.push_back( generate_xml_port_name(io_pin_table.internal_pin(pin_id))); data_row_str.push_back( diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 30ad0995c..a2bb0abf4 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -1430,8 +1430,8 @@ int build_grid_modules( * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_2D_SIDES (same treatment as regular - * grids) + * we will generate one module with NUM_2D_SIDES (same treatment as + * regular grids) */ std::set io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile); @@ -1449,9 +1449,9 @@ int build_grid_modules( /* For CLB and heterogenenous blocks */ status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, - sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_2D_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, - device_ctx.arch->perimeter_cb, verbose); + sram_orgz_type, sram_model, &physical_tile, tile_annotation, + NUM_2D_SIDES, ql_memory_bank_config_setting, duplicate_grid_pin, + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 3ff540266..b3d3224d7 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1539,8 +1539,8 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, layer, - vtr::Point(ix, iy), NUM_2D_SIDES, tile_instance_ids, fabric_tile, - perimeter_cb); + vtr::Point(ix, iy), NUM_2D_SIDES, tile_instance_ids, + fabric_tile, perimeter_cb); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fpga_spice/spice_grid.cpp b/openfpga/src/fpga_spice/spice_grid.cpp index 6826cd4ba..ec8a58bc1 100644 --- a/openfpga/src/fpga_spice/spice_grid.cpp +++ b/openfpga/src/fpga_spice/spice_grid.cpp @@ -393,8 +393,8 @@ void print_spice_grids(NetlistManager& netlist_manager, * i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT}, * we will generate one module for each border side * - If a I/O block locates in the center of FPGA fabric: - * we will generate one module with NUM_2D_SIDES (same treatment as regular - * grids) + * we will generate one module with NUM_2D_SIDES (same treatment as + * regular grids) */ std::set io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile); @@ -407,7 +407,8 @@ void print_spice_grids(NetlistManager& netlist_manager, } else { /* For CLB and heterogenenous blocks */ print_spice_physical_tile_netlist(netlist_manager, module_manager, - subckt_dir, &physical_tile, NUM_2D_SIDES); + subckt_dir, &physical_tile, + NUM_2D_SIDES); } } VTR_LOG("Building physical tiles..."); diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index b1c46742d..b7ed5e628 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -139,7 +139,8 @@ void print_verilog_simulation_info( size_t io_index = io_location_map.io_index( place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + place_ctx.block_locs()[atom_ctx.lookup.atom_clb(atom_blk)] + .loc.sub_tile, module_io_port.get_name()); if (size_t(-1) == io_index) { From ce7f1b516208ef732238988212d958fe61f5a286 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 15:53:03 -0700 Subject: [PATCH 5/9] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 9ddf4ca42..585bd4fb2 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 9ddf4ca42db3a0f833a264a21eafcc0b93d1bf85 +Subproject commit 585bd4fb2bc334e1a3881642c2bdfbbdeb04c78a From 43128439feeaf8063cb22472fd304f60a7be76bc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 16:04:11 -0700 Subject: [PATCH 6/9] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 585bd4fb2..727ecf6a3 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 585bd4fb2bc334e1a3881642c2bdfbbdeb04c78a +Subproject commit 727ecf6a38f417d8cfd37f9b26b08666ec556b4c From efdb8bf441d4e7d6d4f8bf8e22aa0473340c3e87 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 17:14:11 -0700 Subject: [PATCH 7/9] [test] use fixed route chan width to avoid the bug on vpr which failed routing on min chan width condition --- .../mux_design/stdcell_mux2_last_stage/config/task.conf | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf index a70315f2d..d9b3a1757 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2_last_stage/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml From aa86381d651ddbac9e50755b0fe81f03ace63a40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 17:17:36 -0700 Subject: [PATCH 8/9] [test] adjust route chan width to avoid vpr bug on min route chan width (some case failed) --- .../config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf index 2549ab7dc..292458942 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=32 +openfpga_vpr_route_chan_width=40 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= From de4a65751925c0b3598417a94894d8dbafb4f9b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2024 18:02:10 -0700 Subject: [PATCH 9/9] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 727ecf6a3..2eb6eb694 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 727ecf6a38f417d8cfd37f9b26b08666ec556b4c +Subproject commit 2eb6eb6943ac59a3da19d36633814321b8df33e8