From d2c65624c773f471466d520ebe6c34c7f4dbf7d5 Mon Sep 17 00:00:00 2001 From: Lucas Russo Date: Fri, 10 Jul 2020 13:16:57 -0300 Subject: [PATCH 1/3] testbench/cic: update bpm_swap module to update only on next valid --- .../cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd | 11 ++++++++--- hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd | 7 +------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd b/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd index 2528730..dfcb67f 100755 --- a/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd +++ b/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd @@ -80,6 +80,7 @@ architecture rtl of swap_freqgen is signal cnst_swap_div_f : natural range 0 to 2**g_swap_div_freq_vec_width-1; signal clk_swap : std_logic; signal deswap : std_logic; + signal synch_pending : std_logic; begin ---------------------------------------------------------------- @@ -132,6 +133,7 @@ begin if rst_n_i = '0' then count <= 0; clk_swap <= '1'; + synch_pending <= '0'; else if en_i = '1' then -- Clear SW counter if we received a new SW divider period @@ -141,7 +143,11 @@ begin count <= 0; clk_swap <= '1'; elsif swap_div_f_cnt_en_i = '1' then - if count = cnst_swap_div_f then + if synch_pending = '1' then + count <= 0; + clk_swap <= '1'; + synch_pending <= '0'; + elsif count = cnst_swap_div_f then count <= 0; clk_swap <= not clk_swap; else @@ -154,8 +160,7 @@ begin if(sync_trig_i = '1' and -- sync trig arrived, (count /= cnst_swap_div_f -- but no sync necessary or clk_swap = '0')) then -- unless it's synchronized with a different phase, then reset it - count <= 0; - clk_swap <= '1'; + synch_pending <= '1'; end if; end if; diff --git a/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd b/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd index 9a5216e..a31f601 100755 --- a/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd +++ b/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swmode_sel.vhd @@ -81,12 +81,7 @@ begin deswap <= '0'; when others => - if clk_swap_i = '1' then - swap <= '1'; - else - swap <= '0'; - end if; - + swap <= '0'; deswap <= '0'; end case; end if; From 4a5896727776fc6d76bbd7130475112258338c68 Mon Sep 17 00:00:00 2001 From: Lucas Russo Date: Fri, 10 Jul 2020 13:18:02 -0300 Subject: [PATCH 2/3] testbench/cic: improve simulation to sync with similar real-life trigger --- hdl/testbench/cic/cic_bench.vhd | 19 +++++++++++++++++-- hdl/testbench/cic/wave.do | 10 ++++++---- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/hdl/testbench/cic/cic_bench.vhd b/hdl/testbench/cic/cic_bench.vhd index dcfa618..4a795d6 100644 --- a/hdl/testbench/cic/cic_bench.vhd +++ b/hdl/testbench/cic/cic_bench.vhd @@ -46,6 +46,7 @@ architecture str of cic_bench is ----------------------------------------------------------------------------- constant c_input_freq : real := 100.0e6; constant c_clock_period : time := 1.0 sec /(2.0*c_input_freq); + constant c_delay_period : time := c_clock_period; constant c_cycles_to_reset : natural := 4; signal clock : std_logic := '0'; @@ -77,6 +78,7 @@ architecture str of cic_bench is signal data_out : std_logic_vector(c_output_width-1 downto 0); signal cic_valid : std_logic; signal valid_tr : std_logic; + signal sync_trig : std_logic := '0'; signal endoffile : std_logic := '0'; component cic_dyn is @@ -141,7 +143,7 @@ begin -- architecture str begin if reset = '0' then valid_tr <= '0'; - wait for 7*c_clock_period; + wait for 11*c_clock_period; valid_tr <= '1'; wait for c_clock_period; else @@ -150,6 +152,19 @@ begin -- architecture str end if; end process; + sync_trig_gen : process + begin + if reset = '0' then + wait for (12*c_decimation_rate-1)*c_clock_period; + sync_trig <= '1'; + wait for c_clock_period; + sync_trig <= '0'; + else + sync_trig <= '0'; + wait for (4043+5)*c_delay_period; + end if; + end process; + cmp_tag : entity work.swap_freqgen generic map ( g_delay_vec_width => 10, @@ -160,7 +175,7 @@ begin -- architecture str rst_n_i => reset_n, en_i => ce, - sync_trig_i => '0', + sync_trig_i => sync_trig, -- Swap and de-swap signals swap_o => open, diff --git a/hdl/testbench/cic/wave.do b/hdl/testbench/cic/wave.do index d607685..0f7c57c 100644 --- a/hdl/testbench/cic/wave.do +++ b/hdl/testbench/cic/wave.do @@ -5,6 +5,7 @@ add wave -noupdate /cic_bench/clock add wave -noupdate /cic_bench/reset add wave -noupdate /cic_bench/ce add wave -noupdate /cic_bench/ce_out +add wave -noupdate /cic_bench/sync_trig add wave -noupdate /cic_bench/sw_out add wave -noupdate /cic_bench/data_tag add wave -noupdate /cic_bench/data_tag_en @@ -88,8 +89,8 @@ add wave -noupdate /cic_bench/uut/cmp_decimation_strober/strobe add wave -noupdate /cic_bench/uut/cmp_decimation_strober/strobe_o add wave -noupdate /cic_bench/uut/cmp_decimation_strober/valid_i add wave -noupdate -divider swap_freqgen -add wave -noupdate /cic_bench/cmp_tag/g_delay_vec_width -add wave -noupdate /cic_bench/cmp_tag/g_swap_div_freq_vec_width +add wave -noupdate -radix unsigned /cic_bench/cmp_tag/g_delay_vec_width +add wave -noupdate -radix unsigned /cic_bench/cmp_tag/g_swap_div_freq_vec_width add wave -noupdate /cic_bench/cmp_tag/clk_i add wave -noupdate /cic_bench/cmp_tag/rst_n_i add wave -noupdate /cic_bench/cmp_tag/en_i @@ -105,6 +106,7 @@ add wave -noupdate -radix unsigned /cic_bench/cmp_tag/cnst_swap_div_f_old add wave -noupdate -radix unsigned /cic_bench/cmp_tag/cnst_swap_div_f add wave -noupdate /cic_bench/cmp_tag/clk_swap add wave -noupdate /cic_bench/cmp_tag/deswap +add wave -noupdate /cic_bench/cmp_tag/synch_pending add wave -noupdate -divider cic add wave -noupdate /cic_bench/uut/cmp_cic_decim/BITGROWTH add wave -noupdate /cic_bench/uut/cmp_cic_decim/DATAIN_WIDTH @@ -152,7 +154,7 @@ add wave -noupdate /cic_bench/uut/gen_with_ce_sync/cmp_ce_synch/valid_o add wave -noupdate /cic_bench/uut/gen_with_ce_sync/cmp_ce_synch/data_int add wave -noupdate /cic_bench/uut/gen_with_ce_sync/cmp_ce_synch/valid_int TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {24345000 ps} 0} +WaveRestoreCursors {{Cursor 1} {22150000 ps} 0} quietly wave cursor active 1 configure wave -namecolwidth 208 configure wave -valuecolwidth 102 @@ -168,4 +170,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {23934843 ps} {24755157 ps} +WaveRestoreZoom {21739843 ps} {22560157 ps} From c6c5a5770feffd86be576f3925c7f0d8e2fd3715 Mon Sep 17 00:00:00 2001 From: Lucas Russo Date: Fri, 10 Jul 2020 13:18:38 -0300 Subject: [PATCH 3/3] testbench/cic: add fs timescale to simulation --- hdl/testbench/cic/run.do | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hdl/testbench/cic/run.do b/hdl/testbench/cic/run.do index 1fc82ab..44cc460 100644 --- a/hdl/testbench/cic/run.do +++ b/hdl/testbench/cic/run.do @@ -1,7 +1,8 @@ vcom cic_bench.vhd -- make -f Makefile -- output log file to file "output.log", set simulation resolution to "fs" -vsim -l output.log -t 1ps -L unisim work.cic_bench -voptargs="+acc" +vsim -l output.log -voptargs="+acc" -t fs +notimingchecks -L unisim work.cic_bench + set StdArithNoWarnings 1 set NumericStdNoWarnings 1 do wave.do