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Enhancements to balancing, LUT mapping, and rewriting (#616)
* Fix to AIG balancing * Adding substitute_node_no_restrash to data structures and fanout_view * Fixes in rewrite, sequential network support in depth_view * Increase support for sequential circuits in cut_enumeration * Enhanced LUT mapping * Adding new SOP and ESOP balancing algorithms * Adding tests for balancing * Fixing bad balancing in ESOPs * Updating changelog
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docs/algorithms/balancing.rst

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Algorithm
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~~~~~~~~~
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.. doxygenfunction:: mockturtle::sop_balancing
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.. doxygenfunction:: mockturtle::esop_balancing
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.. doxygenfunction:: mockturtle::balancing
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Rebalancing engines
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**Header:** ``mockturtle/algorithms/balancing/sop_balancing.hpp``
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.. doxygenstruct:: mockturtle::sop_rebalancing
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**Header:** ``mockturtle/algorithms/balancing/esop_balancing.hpp``
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.. doxygenstruct:: mockturtle::esop_rebalancing

docs/algorithms/lut_mapping.rst

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The following example shows how to perform a LUT mapping to an And-inverter
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graph using the default settings:
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.. code-block:: c++
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aig_network aig = ...;
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klut_network klut = lut_map( aig );
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Alternatively, the mapping information can be saved on the original network
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as follows:
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.. code-block:: c++
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aig_network aig = ...;
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mapping_view mapped_aig{aig};
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lut_map( mapped_aig );
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lut_map_inplace( mapped_aig );
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Note that the AIG is wrapped into a `mapping_view` in order to equip the
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network structure with the required mapping methods.
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ps.remove_dominated_cuts = false;
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ps.recompute_cuts = false;
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ps.cut_enumeration_ps.cut_size = 8;
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lut_map<mapped_view<mig_network, true>, true>( mapped_mig, ps );
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lut_map_inplace<mapped_view<mig_network, true>, true>( mapped_mig, ps );
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**Parameters and statistics**
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.. doxygenfunction:: mockturtle::lut_map
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.. doxygenfunction:: mockturtle::lut_map_inplace
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LUT mapping 2
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-------------

docs/changelog.rst

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- Add access methods to check if a node is present in the network given its immediate fanin (e.g., `has_and` in `aig_network`) `#580 <https://github.com/lsils/mockturtle/pull/580>`_
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- Crossed networks (`crossed_klut_network` and `buffered_crossed_klut_network`) `#589 <https://github.com/lsils/mockturtle/pull/589>`_
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- Generic network implementation with additional node types (`generic_network`) `#594 <https://github.com/lsils/mockturtle/pull/594>`_
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- Adding `substitute_node_no_restrash` to `aig_network`, `xag_network`, `mig_network`, `xmg_network`, and `fanout_view` to substitute nodes without structural hashing and simplifications `#616 <https://github.com/lsils/mockturtle/pull/616>`_
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- Adding `replace_in_node_no_restrash` to `aig_network`, `xag_network`, `mig_network`, and `xmg_network` to replace a fanin without structural hashing and simplifications `#616 <https://github.com/lsils/mockturtle/pull/616>`_
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* Algorithms:
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- AIG balancing (`aig_balance`) `#580 <https://github.com/lsils/mockturtle/pull/580>`_
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- Cost-generic resubstitution (`cost_generic_resub`) `#554 <https://github.com/lsils/mockturtle/pull/554>`_
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- DAG-aware in-place rewriting (`rewrite`) `#605 <https://github.com/lsils/mockturtle/pull/605>`_
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- Dynamic cut enumeration (`dynamic_cut_enumeration_impl`) `#605 <https://github.com/lsils/mockturtle/pull/605>`_
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- Extensions and fixes in refactoring (`refactoring`) `#607 <https://github.com/lsils/mockturtle/pull/607>`_
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- Improving LUT mapping, changing its interface, and integrating SOP/ESOP balancing (`lut_map`) `#616 <https://github.com/lsils/mockturtle/pull/616>`_
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- Adding LUT-based SOP and ESOP balancing (`sop_balancing`, `esop_balancing`) `#616 <https://github.com/lsils/mockturtle/pull/616>`_
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* I/O:
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- Write gates to GENLIB file (`write_genlib`) `#606 <https://github.com/lsils/mockturtle/pull/606>`_
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* Views:

docs/network.rst

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~~~~~~~~~~~~~
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.. doxygenclass:: mockturtle::network
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:members: substitute_node, substitute_nodes, replace_in_node, replace_in_outputs, take_out_node, is_dead
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:members: substitute_node, substitute_node_no_restrash, substitute_nodes, replace_in_node, replace_in_node_no_restrash, replace_in_outputs, take_out_node, is_dead
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:no-link:
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Structural properties

experiments/balancing.cpp

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/* mockturtle: C++ logic network library
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* Copyright (C) 2018-2023 EPFL
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <string>
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#include <vector>
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#include <fmt/format.h>
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#include <lorina/aiger.hpp>
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#include <mockturtle/algorithms/balancing.hpp>
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#include <mockturtle/algorithms/lut_mapper.hpp>
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#include <mockturtle/io/aiger_reader.hpp>
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#include <mockturtle/networks/xag.hpp>
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#include <mockturtle/networks/klut.hpp>
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#include <mockturtle/views/depth_view.hpp>
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#include <experiments.hpp>
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int main()
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{
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using namespace experiments;
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using namespace mockturtle;
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experiment<std::string, uint32_t, uint32_t, uint32_t, uint32_t, double, bool> exp( "sop_balancing", "benchmark", "size_before", "depth_before", "size_after", "depth_after", "runtime", "equivalent" );
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for ( auto const& benchmark : epfl_benchmarks() )
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{
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fmt::print( "[i] processing {}\n", benchmark );
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xag_network xag;
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if ( lorina::read_aiger( benchmark_path( benchmark ), aiger_reader( xag ) ) != lorina::return_code::success )
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{
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continue;
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}
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const uint32_t size_before = xag.num_gates();
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const uint32_t depth_before = depth_view{ xag }.depth();
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lut_map_params ps;
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ps.cut_enumeration_ps.cut_size = 4u;
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lut_map_stats st;
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const xag_network balanced_xag = esop_balancing( xag, ps, &st );
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const uint32_t size_after = balanced_xag.num_gates();
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const uint32_t depth_after = depth_view{ balanced_xag }.depth();
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auto const cec = benchmark == "hyp" ? true : abc_cec( balanced_xag, benchmark );
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exp( benchmark, size_before, depth_before, size_after, depth_after, to_seconds( st.time_total ), cec );
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}
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exp.save();
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exp.table();
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return 0;
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}

experiments/lut_mapper.cpp

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#include <fmt/format.h>
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#include <lorina/aiger.hpp>
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#include <mockturtle/algorithms/collapse_mapped.hpp>
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#include <mockturtle/algorithms/lut_mapper.hpp>
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#include <mockturtle/io/aiger_reader.hpp>
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#include <mockturtle/networks/aig.hpp>
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ps.area_oriented_mapping = false;
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ps.cut_expansion = true;
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lut_map_stats st;
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mapping_view<aig_network, false> mapped_aig{ aig };
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lut_map<decltype( mapped_aig ), false>( mapped_aig, ps, &st );
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const auto klut = *collapse_mapped_network<klut_network>( mapped_aig );
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const auto klut = lut_map( aig, ps, &st );
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depth_view<klut_network> klut_d{ klut };
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include/mockturtle/algorithms/aig_balancing.hpp

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public:
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aig_balance_impl( Ntk& ntk, aig_balancing_params const& ps )
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: ntk( ntk ), ps( ps ),storage( storage_init_size )
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: ntk( ntk ), ps( ps ), storage( storage_init_size )
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{
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}
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/* replace if new */
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if ( n != ntk.get_node( root ) )
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{
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ntk.substitute_node( n, root );
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ntk.substitute_node_no_restrash( n, root );
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}
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/* remember the substitution and the new node as already balanced */

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