From 6f24f6edb40c8d704c5df865122f89fd4301b037 Mon Sep 17 00:00:00 2001
From: aletempiac <alessandro.tempia@gmail.com>
Date: Thu, 22 Feb 2024 11:17:51 +0100
Subject: [PATCH] Adding docs on write verilog, updating the experiment on emap

---
 docs/io/writers.rst  |  6 ++++++
 experiments/emap.cpp | 11 +++++++++++
 2 files changed, 17 insertions(+)

diff --git a/docs/io/writers.rst b/docs/io/writers.rst
index b44f11769..427105ada 100644
--- a/docs/io/writers.rst
+++ b/docs/io/writers.rst
@@ -37,8 +37,14 @@ Write into structural Verilog files
 
 .. doxygenfunction:: mockturtle::write_verilog(Ntk const&, std::ostream&, write_verilog_params const&)
 
+.. doxygenfunction:: mockturtle::write_verilog_with_binding(Ntk const&, std::string const&, write_verilog_params const&)
+
 .. doxygenfunction:: mockturtle::write_verilog_with_binding(Ntk const&, std::ostream&, write_verilog_params const&)
 
+.. doxygenfunction:: mockturtle::write_verilog_with_cell(Ntk const&, std::string const&, write_verilog_params const&)
+
+.. doxygenfunction:: mockturtle::write_verilog_with_cell(Ntk const&, std::ostream&, write_verilog_params const&)
+
 Write into DIMACS files (CNF)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
diff --git a/experiments/emap.cpp b/experiments/emap.cpp
index aea95dab4..5b1bc2f10 100644
--- a/experiments/emap.cpp
+++ b/experiments/emap.cpp
@@ -30,9 +30,11 @@
 #include <fmt/format.h>
 #include <lorina/aiger.hpp>
 #include <lorina/genlib.hpp>
+#include <mockturtle/algorithms/aig_balancing.hpp>
 #include <mockturtle/algorithms/emap.hpp>
 #include <mockturtle/io/aiger_reader.hpp>
 #include <mockturtle/io/genlib_reader.hpp>
+#include <mockturtle/io/write_verilog.hpp>
 #include <mockturtle/networks/aig.hpp>
 #include <mockturtle/networks/block.hpp>
 #include <mockturtle/utils/name_utils.hpp>
@@ -76,6 +78,12 @@ int main()
       continue;
     }
 
+    /* remove structural redundancies */
+    aig_balancing_params bps;
+    bps.minimize_levels = false;
+    bps.fast_mode = false;
+    aig_balance( aig, bps );
+
     const uint32_t size_before = aig.num_gates();
     const uint32_t depth_before = depth_view( aig ).depth();
 
@@ -91,6 +99,9 @@ int main()
     restore_pio_names_by_order( aig, res_names );
     const auto cec = benchmark == "hyp" ? true : abc_cec_mapped_cell( res_names, benchmark, library );
 
+    /* write verilog netlist */
+    // write_verilog_with_cell( res_names, benchmark + "_mapped.v" );
+
     exp( benchmark, size_before, res.compute_area(), depth_before, res.compute_worst_delay(), st.multioutput_gates, to_seconds( st.time_total ), cec );
   }