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vivado.jou
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#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:37:14 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Fri Oct 11 12:50:32 2024
# Process ID: 36780
# Current directory: C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent37552 C:\Users\minde\Ambiente de Trabalho\Proj SD\LAB\2\lab_2\lab_2.xpr
# Log file: C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/vivado.log
# Journal file: C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2\vivado.jou
# Running On :Jaime
# Platform :Windows Server 2016 or Windows 10
# Operating System :22631
# Processor Detail :13th Gen Intel(R) Core(TM) i9-13900H
# CPU Frequency :2995 MHz
# CPU Physical cores:14
# CPU Logical cores :20
# Host memory :33954 MB
# Swap memory :2147 MB
# Total Virtual :36101 MB
# Available Virtual :21243 MB
#-----------------------------------------------------------
start_gui
open_project {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.xpr}
update_compile_order -fileset sources_1
export_ip_user_files -of_objects [get_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/circuito.vhd}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/control.vhd}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/datapath.vhd}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memOUT.vhd}}] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memIN/memIN1new.vhd}}] -no_script -reset -force -quiet
remove_files {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/circuito.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/control.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/datapath.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memOUT.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memIN/memIN1new.vhd}}
add_files -norecurse -scan_for_includes {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memOUT.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/datapath.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/control.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/circuito.vhd} {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/sources_1/new/memIN/memIN1new.vhd}}
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
launch_simulation
source circuito_tb.tcl
close_sim
launch_simulation
source circuito_tb.tcl
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_sim
launch_simulation
source circuito_tb.tcl
run 1000ns
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_design
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
set_property target_constrs_file {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.srcs/constrs_1/imports/Ambiente de Trabalho/Lab2_Constraints.xdc} [current_fileset -constrset]
save_constraints -force
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
refresh_design
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_design
launch_simulation -mode post-synthesis -type timing
source circuito_tb.tcl
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_sim
close_design
launch_simulation -mode post-synthesis -type timing
source circuito_tb.tcl
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
refresh_design
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3
current_sim simulation_3
close_sim
save_constraints -force
launch_simulation
reset_run synth_1
launch_simulation
launch_runs synth_1 -jobs 20
wait_on_run synth_1
launch_simulation
close_sim
close_design
launch_simulation
source circuito_tb.tcl
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
close_design
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
close_design
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_sim
launch_simulation
source circuito_tb.tcl
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
open_run synth_1 -name synth_1
close_sim
launch_simulation
source circuito_tb.tcl
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_sim
launch_simulation
source circuito_tb.tcl
run 1000ns
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
save_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
add_files -fileset sim_1 -norecurse {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}}
set_property xsim.view {{C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}} [get_filesets sim_1]
close_sim
launch_simulation
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
close_sim
launch_simulation
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
close_sim
launch_simulation
source circuito_tb.tcl
run 1000ns
close_design
launch_simulation -mode post-synthesis -type timing
source circuito_tb.tcl
close_sim
close_sim
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
close_design
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
launch_simulation
launch_simulation
source circuito_tb.tcl
run 10 us
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
close_sim
launch_simulation
launch_simulation
launch_simulation
close_project
open_project {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/lab_2.xpr}
update_compile_order -fileset sources_1
launch_simulation
launch_simulation
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
launch_simulation
launch_simulation
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
run 01000ns
launch_runs impl_1 -jobs 20
wait_on_run impl_1
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
refresh_design
reset_run synth_1
launch_runs synth_1 -jobs 20
wait_on_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
reset_run synth_1
launch_runs impl_1 -jobs 20
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 20
wait_on_run impl_1
close_sim
launch_simulation
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
run 1000ns
close_sim
launch_simulation
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
run 1000ns
launch_simulation -mode post-implementation -type timing
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
launch_simulation -mode post-implementation -type functional
open_wave_config {C:/Users/minde/Ambiente de Trabalho/Proj SD/LAB/2/lab_2/circuito_tb_behav.wcfg}
source circuito_tb.tcl
run 10 us
close_sim
current_sim simulation_18
close_sim
close_sim