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luyahanluyahan
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Disacard scratch reg in ULoadF/UStoref
- Becasue improve management of register t5 and t6, so we not need to use scratch paramter. - fix riscv-collab#177
1 parent 4e4cb7a commit 4efcf85

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5 files changed

+35
-43
lines changed

5 files changed

+35
-43
lines changed

‎src/codegen/riscv64/macro-assembler-riscv64.cc

Lines changed: 15 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,9 +1058,7 @@ void TurboAssembler::UnalignedLoadHelper(Register rd, const MemOperand& rs) {
10581058
}
10591059

10601060
template <int NBYTES>
1061-
void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs,
1062-
Register scratch) {
1063-
DCHECK(scratch != rs.rm());
1061+
void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs) {
10641062
DCHECK(NBYTES == 4 || NBYTES == 8);
10651063

10661064
BlockTrampolinePoolScope block_trampoline_pool(this);
@@ -1069,13 +1067,14 @@ void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs,
10691067
if (NeedAdjustBaseAndOffset(rs, OffsetAccessType::TWO_ACCESSES, NBYTES - 1)) {
10701068
// Adjust offset for two accesses and check if offset + 3 fits into int12.
10711069
Register scratch_base = temps.Acquire();
1072-
DCHECK(scratch_base != scratch && scratch_base != rs.rm());
1070+
DCHECK(scratch_base != rs.rm());
10731071
AdjustBaseAndOffset(&source, scratch_base, OffsetAccessType::TWO_ACCESSES,
10741072
NBYTES - 1);
10751073
}
10761074

10771075
Register scratch_other = temps.Acquire();
1078-
DCHECK(scratch_other != scratch && scratch_other != rs.rm());
1076+
Register scratch = temps.Acquire();
1077+
DCHECK(scratch != rs.rm() && scratch_other != scratch && scratch_other != rs.rm());
10791078
LoadNBytes<NBYTES, true>(scratch, source, scratch_other);
10801079
if (NBYTES == 4)
10811080
fmv_w_x(frd, scratch);
@@ -1115,11 +1114,10 @@ void TurboAssembler::UnalignedStoreHelper(Register rd, const MemOperand& rs,
11151114

11161115
template <int NBYTES>
11171116
void TurboAssembler::UnalignedFStoreHelper(FPURegister frd,
1118-
const MemOperand& rs,
1119-
Register scratch) {
1120-
DCHECK(scratch != rs.rm());
1117+
const MemOperand& rs) {
11211118
DCHECK(NBYTES == 8 || NBYTES == 4);
1122-
1119+
UseScratchRegisterScope temps(this);
1120+
Register scratch = temps.Acquire();
11231121
if (NBYTES == 4) {
11241122
fmv_x_w(scratch, frd);
11251123
} else {
@@ -1210,24 +1208,20 @@ void MacroAssembler::StoreWordPair(Register rd, const MemOperand& rs,
12101208
Sw(scratch, MemOperand(rs.rm(), rs.offset() + kPointerSize / 2));
12111209
}
12121210

1213-
void TurboAssembler::ULoadFloat(FPURegister fd, const MemOperand& rs,
1214-
Register scratch) {
1215-
UnalignedFLoadHelper<4>(fd, rs, scratch);
1211+
void TurboAssembler::ULoadFloat(FPURegister fd, const MemOperand& rs) {
1212+
UnalignedFLoadHelper<4>(fd, rs);
12161213
}
12171214

1218-
void TurboAssembler::UStoreFloat(FPURegister fd, const MemOperand& rs,
1219-
Register scratch) {
1220-
UnalignedFStoreHelper<4>(fd, rs, scratch);
1215+
void TurboAssembler::UStoreFloat(FPURegister fd, const MemOperand& rs) {
1216+
UnalignedFStoreHelper<4>(fd, rs);
12211217
}
12221218

1223-
void TurboAssembler::ULoadDouble(FPURegister fd, const MemOperand& rs,
1224-
Register scratch) {
1225-
UnalignedFLoadHelper<8>(fd, rs, scratch);
1219+
void TurboAssembler::ULoadDouble(FPURegister fd, const MemOperand& rs) {
1220+
UnalignedFLoadHelper<8>(fd, rs);
12261221
}
12271222

1228-
void TurboAssembler::UStoreDouble(FPURegister fd, const MemOperand& rs,
1229-
Register scratch) {
1230-
UnalignedFStoreHelper<8>(fd, rs, scratch);
1223+
void TurboAssembler::UStoreDouble(FPURegister fd, const MemOperand& rs) {
1224+
UnalignedFStoreHelper<8>(fd, rs);
12311225
}
12321226

12331227
void TurboAssembler::Lb(Register rd, const MemOperand& rs) {

‎src/codegen/riscv64/macro-assembler-riscv64.h

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -556,11 +556,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
556556
Register scratch_other = no_reg);
557557

558558
template <int NBYTES>
559-
void UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs,
560-
Register scratch);
559+
void UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs);
561560
template <int NBYTES>
562-
void UnalignedFStoreHelper(FPURegister frd, const MemOperand& rs,
563-
Register scratch);
561+
void UnalignedFStoreHelper(FPURegister frd, const MemOperand& rs);
564562

565563
template <typename Reg_T, typename Func>
566564
void AlignedLoadHelper(Reg_T target, const MemOperand& rs, Func generator);
@@ -584,11 +582,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
584582
void Uld(Register rd, const MemOperand& rs);
585583
void Usd(Register rd, const MemOperand& rs);
586584

587-
void ULoadFloat(FPURegister fd, const MemOperand& rs, Register scratch);
588-
void UStoreFloat(FPURegister fd, const MemOperand& rs, Register scratch);
585+
void ULoadFloat(FPURegister fd, const MemOperand& rs);
586+
void UStoreFloat(FPURegister fd, const MemOperand& rs);
589587

590-
void ULoadDouble(FPURegister fd, const MemOperand& rs, Register scratch);
591-
void UStoreDouble(FPURegister fd, const MemOperand& rs, Register scratch);
588+
void ULoadDouble(FPURegister fd, const MemOperand& rs);
589+
void UStoreDouble(FPURegister fd, const MemOperand& rs);
592590

593591
void Lb(Register rd, const MemOperand& rs);
594592
void Lbu(Register rd, const MemOperand& rs);

‎src/compiler/backend/riscv64/code-generator-riscv64.cc

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1605,7 +1605,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
16051605
break;
16061606
}
16071607
case kRiscvULoadFloat: {
1608-
__ ULoadFloat(i.OutputSingleRegister(), i.MemoryOperand(), kScratchReg);
1608+
__ ULoadFloat(i.OutputSingleRegister(), i.MemoryOperand());
16091609
break;
16101610
}
16111611
case kRiscvStoreFloat: {
@@ -1625,14 +1625,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
16251625
if (ft == kDoubleRegZero && !__ IsSingleZeroRegSet()) {
16261626
__ LoadFPRImmediate(kDoubleRegZero, 0.0f);
16271627
}
1628-
__ UStoreFloat(ft, operand, kScratchReg);
1628+
__ UStoreFloat(ft, operand);
16291629
break;
16301630
}
16311631
case kRiscvLoadDouble:
16321632
__ LoadDouble(i.OutputDoubleRegister(), i.MemoryOperand());
16331633
break;
16341634
case kRiscvULoadDouble:
1635-
__ ULoadDouble(i.OutputDoubleRegister(), i.MemoryOperand(), kScratchReg);
1635+
__ ULoadDouble(i.OutputDoubleRegister(), i.MemoryOperand());
16361636
break;
16371637
case kRiscvStoreDouble: {
16381638
FPURegister ft = i.InputOrZeroDoubleRegister(2);
@@ -1647,7 +1647,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
16471647
if (ft == kDoubleRegZero && !__ IsDoubleZeroRegSet()) {
16481648
__ LoadFPRImmediate(kDoubleRegZero, 0.0);
16491649
}
1650-
__ UStoreDouble(ft, i.MemoryOperand(), kScratchReg);
1650+
__ UStoreDouble(ft, i.MemoryOperand());
16511651
break;
16521652
}
16531653
case kRiscvSync: {

‎src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -102,10 +102,10 @@ inline void Store(LiftoffAssembler* assm, Register base, int32_t offset,
102102
assm->Usd(src.gp(), dst);
103103
break;
104104
case ValueType::kF32:
105-
assm->UStoreFloat(src.fp(), dst, t5);
105+
assm->UStoreFloat(src.fp(), dst);
106106
break;
107107
case ValueType::kF64:
108-
assm->UStoreDouble(src.fp(), dst, t5);
108+
assm->UStoreDouble(src.fp(), dst);
109109
break;
110110
default:
111111
UNREACHABLE();
@@ -419,10 +419,10 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
419419
TurboAssembler::Uld(dst.gp(), src_op);
420420
break;
421421
case LoadType::kF32Load:
422-
TurboAssembler::ULoadFloat(dst.fp(), src_op, t5);
422+
TurboAssembler::ULoadFloat(dst.fp(), src_op);
423423
break;
424424
case LoadType::kF64Load:
425-
TurboAssembler::ULoadDouble(dst.fp(), src_op, t5);
425+
TurboAssembler::ULoadDouble(dst.fp(), src_op);
426426
break;
427427
default:
428428
UNREACHABLE();
@@ -484,10 +484,10 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
484484
TurboAssembler::Usd(src.gp(), dst_op);
485485
break;
486486
case StoreType::kF32Store:
487-
TurboAssembler::UStoreFloat(src.fp(), dst_op, t5);
487+
TurboAssembler::UStoreFloat(src.fp(), dst_op);
488488
break;
489489
case StoreType::kF64Store:
490-
TurboAssembler::UStoreDouble(src.fp(), dst_op, t5);
490+
TurboAssembler::UStoreDouble(src.fp(), dst_op);
491491
break;
492492
default:
493493
UNREACHABLE();

‎test/cctest/test-macro-assembler-riscv64.cc

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -931,8 +931,8 @@ TEST(Uld) {
931931
}
932932

933933
auto fn = [](MacroAssembler& masm, int32_t in_offset, int32_t out_offset) {
934-
__ ULoadFloat(fa0, MemOperand(a0, in_offset), t0);
935-
__ UStoreFloat(fa0, MemOperand(a0, out_offset), t0);
934+
__ ULoadFloat(fa0, MemOperand(a0, in_offset));
935+
__ UStoreFloat(fa0, MemOperand(a0, out_offset));
936936
};
937937

938938
TEST(ULoadFloat) {
@@ -965,8 +965,8 @@ TEST(ULoadDouble) {
965965
char* buffer_middle = memory_buffer + (kBufferSize / 2);
966966

967967
auto fn = [](MacroAssembler& masm, int32_t in_offset, int32_t out_offset) {
968-
__ ULoadDouble(fa0, MemOperand(a0, in_offset), t0);
969-
__ UStoreDouble(fa0, MemOperand(a0, out_offset), t0);
968+
__ ULoadDouble(fa0, MemOperand(a0, in_offset));
969+
__ UStoreDouble(fa0, MemOperand(a0, out_offset));
970970
};
971971

972972
FOR_FLOAT64_INPUTS(i) {

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