From 788cd29ccedb1026db955b7e45ae24fe709329ab Mon Sep 17 00:00:00 2001 From: luyahan Date: Wed, 16 Sep 2020 17:23:22 +0900 Subject: [PATCH] Disacard scratch reg in ULoadF/UStoref - Becasue improve management of register t5 and t6, so we not need to use scratch paramter. - fix #177 --- .../riscv64/macro-assembler-riscv64.cc | 36 ++++++++----------- src/codegen/riscv64/macro-assembler-riscv64.h | 14 ++++---- .../backend/riscv64/code-generator-riscv64.cc | 8 ++--- .../riscv64/liftoff-assembler-riscv64.h | 12 +++---- test/cctest/test-macro-assembler-riscv64.cc | 8 ++--- 5 files changed, 35 insertions(+), 43 deletions(-) diff --git a/src/codegen/riscv64/macro-assembler-riscv64.cc b/src/codegen/riscv64/macro-assembler-riscv64.cc index d0aab6e272ed..84cd827516db 100644 --- a/src/codegen/riscv64/macro-assembler-riscv64.cc +++ b/src/codegen/riscv64/macro-assembler-riscv64.cc @@ -1058,9 +1058,7 @@ void TurboAssembler::UnalignedLoadHelper(Register rd, const MemOperand& rs) { } template -void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs, - Register scratch) { - DCHECK(scratch != rs.rm()); +void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs) { DCHECK(NBYTES == 4 || NBYTES == 8); BlockTrampolinePoolScope block_trampoline_pool(this); @@ -1069,13 +1067,14 @@ void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs, if (NeedAdjustBaseAndOffset(rs, OffsetAccessType::TWO_ACCESSES, NBYTES - 1)) { // Adjust offset for two accesses and check if offset + 3 fits into int12. Register scratch_base = temps.Acquire(); - DCHECK(scratch_base != scratch && scratch_base != rs.rm()); + DCHECK(scratch_base != rs.rm()); AdjustBaseAndOffset(&source, scratch_base, OffsetAccessType::TWO_ACCESSES, NBYTES - 1); } Register scratch_other = temps.Acquire(); - DCHECK(scratch_other != scratch && scratch_other != rs.rm()); + Register scratch = temps.Acquire(); + DCHECK(scratch != rs.rm() && scratch_other != scratch && scratch_other != rs.rm()); LoadNBytes(scratch, source, scratch_other); if (NBYTES == 4) fmv_w_x(frd, scratch); @@ -1115,11 +1114,10 @@ void TurboAssembler::UnalignedStoreHelper(Register rd, const MemOperand& rs, template void TurboAssembler::UnalignedFStoreHelper(FPURegister frd, - const MemOperand& rs, - Register scratch) { - DCHECK(scratch != rs.rm()); + const MemOperand& rs) { DCHECK(NBYTES == 8 || NBYTES == 4); - + UseScratchRegisterScope temps(this); + Register scratch = temps.Acquire(); if (NBYTES == 4) { fmv_x_w(scratch, frd); } else { @@ -1210,24 +1208,20 @@ void MacroAssembler::StoreWordPair(Register rd, const MemOperand& rs, Sw(scratch, MemOperand(rs.rm(), rs.offset() + kPointerSize / 2)); } -void TurboAssembler::ULoadFloat(FPURegister fd, const MemOperand& rs, - Register scratch) { - UnalignedFLoadHelper<4>(fd, rs, scratch); +void TurboAssembler::ULoadFloat(FPURegister fd, const MemOperand& rs) { + UnalignedFLoadHelper<4>(fd, rs); } -void TurboAssembler::UStoreFloat(FPURegister fd, const MemOperand& rs, - Register scratch) { - UnalignedFStoreHelper<4>(fd, rs, scratch); +void TurboAssembler::UStoreFloat(FPURegister fd, const MemOperand& rs) { + UnalignedFStoreHelper<4>(fd, rs); } -void TurboAssembler::ULoadDouble(FPURegister fd, const MemOperand& rs, - Register scratch) { - UnalignedFLoadHelper<8>(fd, rs, scratch); +void TurboAssembler::ULoadDouble(FPURegister fd, const MemOperand& rs) { + UnalignedFLoadHelper<8>(fd, rs); } -void TurboAssembler::UStoreDouble(FPURegister fd, const MemOperand& rs, - Register scratch) { - UnalignedFStoreHelper<8>(fd, rs, scratch); +void TurboAssembler::UStoreDouble(FPURegister fd, const MemOperand& rs) { + UnalignedFStoreHelper<8>(fd, rs); } void TurboAssembler::Lb(Register rd, const MemOperand& rs) { diff --git a/src/codegen/riscv64/macro-assembler-riscv64.h b/src/codegen/riscv64/macro-assembler-riscv64.h index a63269be70d8..d3bb35492572 100644 --- a/src/codegen/riscv64/macro-assembler-riscv64.h +++ b/src/codegen/riscv64/macro-assembler-riscv64.h @@ -556,11 +556,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { Register scratch_other = no_reg); template - void UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs, - Register scratch); + void UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs); template - void UnalignedFStoreHelper(FPURegister frd, const MemOperand& rs, - Register scratch); + void UnalignedFStoreHelper(FPURegister frd, const MemOperand& rs); template void AlignedLoadHelper(Reg_T target, const MemOperand& rs, Func generator); @@ -584,11 +582,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { void Uld(Register rd, const MemOperand& rs); void Usd(Register rd, const MemOperand& rs); - void ULoadFloat(FPURegister fd, const MemOperand& rs, Register scratch); - void UStoreFloat(FPURegister fd, const MemOperand& rs, Register scratch); + void ULoadFloat(FPURegister fd, const MemOperand& rs); + void UStoreFloat(FPURegister fd, const MemOperand& rs); - void ULoadDouble(FPURegister fd, const MemOperand& rs, Register scratch); - void UStoreDouble(FPURegister fd, const MemOperand& rs, Register scratch); + void ULoadDouble(FPURegister fd, const MemOperand& rs); + void UStoreDouble(FPURegister fd, const MemOperand& rs); void Lb(Register rd, const MemOperand& rs); void Lbu(Register rd, const MemOperand& rs); diff --git a/src/compiler/backend/riscv64/code-generator-riscv64.cc b/src/compiler/backend/riscv64/code-generator-riscv64.cc index c44104450ccd..c1ad42fef0ce 100644 --- a/src/compiler/backend/riscv64/code-generator-riscv64.cc +++ b/src/compiler/backend/riscv64/code-generator-riscv64.cc @@ -1605,7 +1605,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kRiscvULoadFloat: { - __ ULoadFloat(i.OutputSingleRegister(), i.MemoryOperand(), kScratchReg); + __ ULoadFloat(i.OutputSingleRegister(), i.MemoryOperand()); break; } case kRiscvStoreFloat: { @@ -1625,14 +1625,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( if (ft == kDoubleRegZero && !__ IsSingleZeroRegSet()) { __ LoadFPRImmediate(kDoubleRegZero, 0.0f); } - __ UStoreFloat(ft, operand, kScratchReg); + __ UStoreFloat(ft, operand); break; } case kRiscvLoadDouble: __ LoadDouble(i.OutputDoubleRegister(), i.MemoryOperand()); break; case kRiscvULoadDouble: - __ ULoadDouble(i.OutputDoubleRegister(), i.MemoryOperand(), kScratchReg); + __ ULoadDouble(i.OutputDoubleRegister(), i.MemoryOperand()); break; case kRiscvStoreDouble: { FPURegister ft = i.InputOrZeroDoubleRegister(2); @@ -1647,7 +1647,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( if (ft == kDoubleRegZero && !__ IsDoubleZeroRegSet()) { __ LoadFPRImmediate(kDoubleRegZero, 0.0); } - __ UStoreDouble(ft, i.MemoryOperand(), kScratchReg); + __ UStoreDouble(ft, i.MemoryOperand()); break; } case kRiscvSync: { diff --git a/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h b/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h index 929e3f75a1f6..8317f6f97e10 100644 --- a/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h +++ b/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h @@ -77,10 +77,10 @@ inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, assm->Usd(src.gp(), dst); break; case ValueType::kF32: - assm->UStoreFloat(src.fp(), dst, t5); + assm->UStoreFloat(src.fp(), dst); break; case ValueType::kF64: - assm->UStoreDouble(src.fp(), dst, t5); + assm->UStoreDouble(src.fp(), dst); break; default: UNREACHABLE(); @@ -394,10 +394,10 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, TurboAssembler::Uld(dst.gp(), src_op); break; case LoadType::kF32Load: - TurboAssembler::ULoadFloat(dst.fp(), src_op, t5); + TurboAssembler::ULoadFloat(dst.fp(), src_op); break; case LoadType::kF64Load: - TurboAssembler::ULoadDouble(dst.fp(), src_op, t5); + TurboAssembler::ULoadDouble(dst.fp(), src_op); break; default: UNREACHABLE(); @@ -459,10 +459,10 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, TurboAssembler::Usd(src.gp(), dst_op); break; case StoreType::kF32Store: - TurboAssembler::UStoreFloat(src.fp(), dst_op, t5); + TurboAssembler::UStoreFloat(src.fp(), dst_op); break; case StoreType::kF64Store: - TurboAssembler::UStoreDouble(src.fp(), dst_op, t5); + TurboAssembler::UStoreDouble(src.fp(), dst_op); break; default: UNREACHABLE(); diff --git a/test/cctest/test-macro-assembler-riscv64.cc b/test/cctest/test-macro-assembler-riscv64.cc index c96f0ea8dacb..add095662b07 100644 --- a/test/cctest/test-macro-assembler-riscv64.cc +++ b/test/cctest/test-macro-assembler-riscv64.cc @@ -931,8 +931,8 @@ TEST(Uld) { } auto fn = [](MacroAssembler& masm, int32_t in_offset, int32_t out_offset) { - __ ULoadFloat(fa0, MemOperand(a0, in_offset), t0); - __ UStoreFloat(fa0, MemOperand(a0, out_offset), t0); + __ ULoadFloat(fa0, MemOperand(a0, in_offset)); + __ UStoreFloat(fa0, MemOperand(a0, out_offset)); }; TEST(ULoadFloat) { @@ -965,8 +965,8 @@ TEST(ULoadDouble) { char* buffer_middle = memory_buffer + (kBufferSize / 2); auto fn = [](MacroAssembler& masm, int32_t in_offset, int32_t out_offset) { - __ ULoadDouble(fa0, MemOperand(a0, in_offset), t0); - __ UStoreDouble(fa0, MemOperand(a0, out_offset), t0); + __ ULoadDouble(fa0, MemOperand(a0, in_offset)); + __ UStoreDouble(fa0, MemOperand(a0, out_offset)); }; FOR_FLOAT64_INPUTS(i) {