diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index 93d5d160..6096045e 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -9,7 +9,10 @@
 
 
 class Memory:
-    def __init__(self, *, width, depth, init=None, name=None, simulate=True):
+    # Configuration options to configure default behaviour for all generated memories
+    # These options should only be set in top level of code and not in modules
+    simulate   = True
+    def __init__(self, *, width, depth, init=None, name=None, simulate=None):
         if not isinstance(width, int) or width < 0:
             raise TypeError("Memory width must be a non-negative integer, not {!r}"
                             .format(width))
@@ -25,6 +28,8 @@ def __init__(self, *, width, depth, init=None, name=None, simulate=True):
 
         # Array of signals for simulation.
         self._array = Array()
+        if simulate is None:
+            simulate = Memory.simulate
         if simulate:
             for addr in range(self.depth):
                 self._array.append(Signal(self.width, name="{}({})"