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Design Rule Check - version 1.drc
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Design Rule Check - version 1.drc
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Protel Design System Design Rule Check
PCB File : D:\Work\_Fiverr\marcvanh\Connector board\res\FMC ZMOD ADAPTER\Imported version 1.PrjPcb\version 1.PcbDoc
Date : 7/14/2021
Time : 3:33:11 PM
Processing Rule : Clearance Constraint (Gap=0.127mm) ((InDifferentialPairClass('All Differential Pairs'))),((InDifferentialPairClass('All Differential Pairs')))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.127mm) (Max=1mm) (Preferred=0.3mm) (All)
Rule Violations :0
Processing Rule : Routing Via (MinHoleWidth=0.3mm) (MaxHoleWidth=0.8mm) (PreferredHoleWidth=0.3mm) (MinWidth=0.6mm) (MaxWidth=0.8mm) (PreferedWidth=0.6mm) (All)
Rule Violations :0
Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.13mm) (Max=0.254mm) (Prefered=0.254mm) and Width Constraints (Min=0.135mm) (Max=0.381mm) (Prefered=0.381mm) (InDifferentialPairClass('All Differential Pairs'))
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.3mm) (Conductor Width=0.3mm) (Air Gap=0.2mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (InPadClass('PowerPads'))
Rule Violations :0
Processing Rule : Minimum Annular Ring (Minimum=0.076mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.3mm) (Max=6.3mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0mm) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=500mm) (All)
Rule Violations :0
Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=1816.048mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:05