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ulala.map.rpt
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ulala.map.rpt
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Analysis & Synthesis report for ulala
Sun Sep 30 00:28:14 2018
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Sep 30 00:28:14 2018 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; ulala ;
; Top-level Entity Name ; ula ;
; Family ; Cyclone IV E ;
; Total logic elements ; 195 ;
; Total combinational functions ; 195 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 62 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE115F29C7 ; ;
; Top-level entity name ; ula ; ulala ;
; Family name ; Cyclone IV E ; Cyclone IV GX ;
; Synchronization Register Chain Length ; 2 ; 3 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-4 processors ; 0.0% ;
+----------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------+
; decot.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/decot.bdf ;
; A_ou_Ac2.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/A_ou_Ac2.bdf ;
; Comp2.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/Comp2.bdf ;
; complemento2parasoma.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/complemento2parasoma.bdf ;
; FA.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/FA.bdf ;
; funcao_and.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/funcao_and.bdf ;
; funcao_igual.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/funcao_igual.bdf ;
; funcao_xor.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/funcao_xor.bdf ;
; halfadd.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/halfadd.bdf ;
; maiorque.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/maiorque.bdf ;
; mux2.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/mux2.bdf ;
; somador_bit_a_bit.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/somador_bit_a_bit.bdf ;
; soma.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/soma.bdf ;
; ula.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/ula.bdf ;
; comparador_modular.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/comparador_modular.bdf ;
; retorna1_sesomaigual0.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; C:/Users/frpmn/Desktop/SD/ULA2.0/retorna1_sesomaigual0.bdf ;
+----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------+
+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------+
; Resource ; Usage ;
+---------------------------------------------+-----------+
; Estimated Total logic elements ; 195 ;
; ; ;
; Total combinational functions ; 195 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 129 ;
; -- 3 input functions ; 53 ;
; -- <=2 input functions ; 13 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 187 ;
; -- arithmetic mode ; 8 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 62 ;
; Maximum fan-out node ; b_0~input ;
; Maximum fan-out ; 35 ;
; Total fan-out ; 801 ;
; Average fan-out ; 2.51 ;
+---------------------------------------------+-----------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+
; |ula ; 195 (135) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 62 ; 0 ; |ula ; work ;
; |Comp2:inst2| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|Comp2:inst2 ; work ;
; |halfadd:inst8| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|Comp2:inst2|halfadd:inst8 ; work ;
; |funcao_igual:inst5| ; 5 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|funcao_igual:inst5 ; ;
; |funcao_xor:inst| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|funcao_igual:inst5|funcao_xor:inst ; ;
; |maiorque:inst166| ; 5 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|maiorque:inst166 ; ;
; |comparador_modular:inst| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|maiorque:inst166|comparador_modular:inst ; ;
; |maiorque:inst3| ; 6 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|maiorque:inst3 ; ;
; |comparador_modular:inst| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|maiorque:inst3|comparador_modular:inst ; ;
; |mux2:inst13| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|mux2:inst13 ; ;
; |soma:inst163| ; 16 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163 ; ;
; |A_ou_Ac2:inst24| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|A_ou_Ac2:inst24 ; work ;
; |A_ou_Ac2:inst31| ; 6 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|A_ou_Ac2:inst31 ; ;
; |complemento2parasoma:inst4| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|A_ou_Ac2:inst31|complemento2parasoma:inst4 ; ;
; |FA:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|A_ou_Ac2:inst31|complemento2parasoma:inst4|FA:inst10 ; ;
; |FA:inst9| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|A_ou_Ac2:inst31|complemento2parasoma:inst4|FA:inst9 ; ;
; |somador_bit_a_bit:inst25| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|somador_bit_a_bit:inst25 ; ;
; |FA:inst5| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst163|somador_bit_a_bit:inst25|FA:inst5 ; ;
; |soma:inst164| ; 21 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164 ; ;
; |A_ou_Ac2:inst23| ; 5 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst23 ; ;
; |complemento2parasoma:inst4| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst23|complemento2parasoma:inst4 ; ;
; |FA:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst23|complemento2parasoma:inst4|FA:inst10 ; ;
; |A_ou_Ac2:inst24| ; 5 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst24 ; ;
; |complemento2parasoma:inst4| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst24|complemento2parasoma:inst4 ; ;
; |FA:inst11| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst24|complemento2parasoma:inst4|FA:inst11 ; ;
; |A_ou_Ac2:inst31| ; 5 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst31 ; ;
; |complemento2parasoma:inst4| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst31|complemento2parasoma:inst4 ; ;
; |FA:inst10| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|A_ou_Ac2:inst31|complemento2parasoma:inst4|FA:inst10 ; ;
; |somador_bit_a_bit:inst25| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|somador_bit_a_bit:inst25 ; ;
; |FA:inst5| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ula|soma:inst164|somador_bit_a_bit:inst25|FA:inst5 ; ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
Info: Processing started: Sun Sep 30 00:28:10 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ulala -c ulala
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Found 1 design units, including 1 entities, in source file decot.bdf
Info: Found entity 1: decot
Info: Found 1 design units, including 1 entities, in source file a_ou_ac2.bdf
Info: Found entity 1: A_ou_Ac2
Info: Found 1 design units, including 1 entities, in source file aornota.bdf
Info: Found entity 1: AornotA
Warning: Can't analyze file -- file and_bit_vetor.bdf is missing
Info: Found 1 design units, including 1 entities, in source file comp2.bdf
Info: Found entity 1: Comp2
Info: Found 1 design units, including 1 entities, in source file comparador modular.bdf
Info: Found entity 1: comparador modular
Info: Found 1 design units, including 1 entities, in source file complemento2parasoma.bdf
Info: Found entity 1: complemento2parasoma
Info: Found 1 design units, including 1 entities, in source file complementoa2.bdf
Info: Found entity 1: complementoa2
Info: Found 1 design units, including 1 entities, in source file complmentoa2tipo2.bdf
Info: Found entity 1: complmentoa2tipo2
Info: Found 1 design units, including 1 entities, in source file decod.bdf
Info: Found entity 1: decod
Info: Found 1 design units, including 1 entities, in source file decodnovo.bdf
Info: Found entity 1: decodnovo
Info: Found 1 design units, including 1 entities, in source file fa.bdf
Info: Found entity 1: FA
Info: Found 1 design units, including 1 entities, in source file funcao_and.bdf
Info: Found entity 1: funcao_and
Info: Found 1 design units, including 1 entities, in source file funcao_igual.bdf
Info: Found entity 1: funcao_igual
Info: Found 1 design units, including 1 entities, in source file funcao_maiorque.bdf
Info: Found entity 1: funcao_maiorque
Info: Found 1 design units, including 1 entities, in source file funcao_xor.bdf
Info: Found entity 1: funcao_xor
Info: Found 1 design units, including 1 entities, in source file halfadd.bdf
Info: Found entity 1: halfadd
Info: Found 1 design units, including 1 entities, in source file maiorque.bdf
Info: Found entity 1: maiorque
Warning: Entity "mux" obtained from "C:/Users/frpmn/Desktop/SD/ULA2.0/mux.bdf" instead of from Quartus II megafunction library
Info: Found 1 design units, including 1 entities, in source file mux.bdf
Info: Found entity 1: mux
Info: Found 1 design units, including 1 entities, in source file mux2.bdf
Info: Found entity 1: mux2
Warning: Can't analyze file -- file or_vetor_vetor.bdf is missing
Info: Found 1 design units, including 1 entities, in source file somador_bit_a_bit.bdf
Info: Found entity 1: somador_bit_a_bit
Info: Found 1 design units, including 1 entities, in source file soma.bdf
Info: Found entity 1: soma
Info: Found 1 design units, including 1 entities, in source file ula.bdf
Info: Found entity 1: ula
Info: Found 1 design units, including 1 entities, in source file comparador_modular.bdf
Info: Found entity 1: comparador_modular
Info: Found 1 design units, including 1 entities, in source file lcd.bdf
Info: Found entity 1: LCD
Info: Elaborating entity "ula" for the top level hierarchy
Warning: Block or symbol "AND2" of instance "inst44" overlaps another block or symbol
Warning: Block or symbol "mux2" of instance "inst13" overlaps another block or symbol
Info: Elaborating entity "mux2" for hierarchy "mux2:inst13"
Info: Elaborating entity "funcao_igual" for hierarchy "funcao_igual:inst5"
Info: Elaborating entity "funcao_xor" for hierarchy "funcao_igual:inst5|funcao_xor:inst"
Info: Elaborating entity "maiorque" for hierarchy "maiorque:inst166"
Info: Elaborating entity "comparador_modular" for hierarchy "maiorque:inst166|comparador_modular:inst"
Info: Elaborating entity "soma" for hierarchy "soma:inst164"
Info: Elaborating entity "A_ou_Ac2" for hierarchy "soma:inst164|A_ou_Ac2:inst31"
Info: Elaborating entity "complemento2parasoma" for hierarchy "soma:inst164|A_ou_Ac2:inst31|complemento2parasoma:inst4"
Info: Elaborating entity "FA" for hierarchy "soma:inst164|A_ou_Ac2:inst31|complemento2parasoma:inst4|FA:inst6"
Info: Elaborating entity "somador_bit_a_bit" for hierarchy "soma:inst164|somador_bit_a_bit:inst25"
Warning: Using design file retorna1_sesomaigual0.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: retorna1_sesomaigual0
Info: Elaborating entity "retorna1_sesomaigual0" for hierarchy "soma:inst164|retorna1_sesomaigual0:inst4"
Info: Elaborating entity "funcao_and" for hierarchy "funcao_and:inst14"
Info: Elaborating entity "Comp2" for hierarchy "Comp2:inst2"
Info: Elaborating entity "halfadd" for hierarchy "Comp2:inst2|halfadd:inst9"
Info: Elaborating entity "decot" for hierarchy "decot:inst9"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "ff" is stuck at VCC
Warning (13410): Pin "aadea" is stuck at VCC
Warning (13410): Pin "dddea" is stuck at VCC
Warning (13410): Pin "eedea" is stuck at VCC
Warning (13410): Pin "ffdea" is stuck at VCC
Warning (13410): Pin "ggdea" is stuck at VCC
Warning (13410): Pin "aadeb" is stuck at VCC
Warning (13410): Pin "dddeb" is stuck at VCC
Warning (13410): Pin "eedeb" is stuck at VCC
Warning (13410): Pin "ffdeb" is stuck at VCC
Warning (13410): Pin "ggdeb" is stuck at VCC
Info: Timing-Driven Synthesis is running
Warning: Ignored assignments for entity "ulala" -- entity does not exist in design
Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity ulala -section_id "Root Region" was ignored
Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity ulala -section_id "Root Region" was ignored
Info: Implemented 257 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 49 output pins
Info: Implemented 195 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
Info: Peak virtual memory: 225 megabytes
Info: Processing ended: Sun Sep 30 00:28:14 2018
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03