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s6-2024-10-23_071246.zip new file mode 100644 index 0000000..c66be29 Binary files /dev/null and b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-23_071246.zip differ diff --git a/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_121730.zip b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_121730.zip new file mode 100644 index 0000000..c66be29 Binary files /dev/null and b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_121730.zip differ diff --git a/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_133025.zip b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_133025.zip new file mode 100644 index 0000000..c66be29 Binary files /dev/null and b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-25_133025.zip differ diff --git a/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-26_113808.zip b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-26_113808.zip new file mode 100644 index 0000000..c66be29 Binary files /dev/null and b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-26_113808.zip differ diff --git a/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-27_203154.zip b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-27_203154.zip new file mode 100644 index 0000000..c66be29 Binary files /dev/null and b/Hardware/Hardawre v3/projet s6/projet s6-backups/projet s6-2024-10-27_203154.zip differ diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6-job.gbrjob b/Hardware/Hardawre v3/projet s6/projet s6-job.gbrjob similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6-job.gbrjob rename to Hardware/Hardawre v3/projet s6/projet s6-job.gbrjob diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_pcb b/Hardware/Hardawre v3/projet s6/projet s6.kicad_pcb similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_pcb rename to Hardware/Hardawre v3/projet s6/projet s6.kicad_pcb diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_prl b/Hardware/Hardawre v3/projet s6/projet s6.kicad_prl similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_prl rename to Hardware/Hardawre v3/projet s6/projet s6.kicad_prl diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_pro b/Hardware/Hardawre v3/projet s6/projet s6.kicad_pro similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_pro rename to Hardware/Hardawre v3/projet s6/projet s6.kicad_pro diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_sch b/Hardware/Hardawre v3/projet s6/projet s6.kicad_sch similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/projet s6.kicad_sch rename to Hardware/Hardawre v3/projet s6/projet s6.kicad_sch diff --git a/Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/untitled.kicad_sch b/Hardware/Hardawre v3/projet s6/untitled.kicad_sch similarity index 100% rename from Hardware/Hardawre v2(everything as been patched and work fine)/projet s6/untitled.kicad_sch rename to Hardware/Hardawre v3/projet s6/untitled.kicad_sch diff --git a/Software/Flapy Bird/.cproject b/Software/Flapy Bird/.cproject deleted file mode 100644 index 7a319f3..0000000 --- a/Software/Flapy Bird/.cproject +++ /dev/null @@ -1,174 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Software/Flapy Bird/.mxproject b/Software/Flapy Bird/.mxproject deleted file mode 100644 index 5bad693..0000000 --- a/Software/Flapy Bird/.mxproject +++ /dev/null @@ -1,25 +0,0 @@ -[PreviousLibFiles] -LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; - -[PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;;; -HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc; -CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; - -[PreviousGenFiles] -AdvancedFolderStructure=true -HeaderFileListSize=3 -HeaderFiles#0=..\Core\Inc\stm32f4xx_it.h -HeaderFiles#1=..\Core\Inc\stm32f4xx_hal_conf.h -HeaderFiles#2=..\Core\Inc\main.h -HeaderFolderListSize=1 -HeaderPath#0=..\Core\Inc -HeaderFiles=; -SourceFileListSize=3 -SourceFiles#0=..\Core\Src\stm32f4xx_it.c -SourceFiles#1=..\Core\Src\stm32f4xx_hal_msp.c -SourceFiles#2=..\Core\Src\main.c -SourceFolderListSize=1 -SourcePath#0=..\Core\Src -SourceFiles=; - diff --git a/Software/Flapy Bird/.project b/Software/Flapy Bird/.project deleted file mode 100644 index 36f46d9..0000000 --- a/Software/Flapy Bird/.project +++ /dev/null @@ -1,32 +0,0 @@ - - - Flapy Bird - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - com.st.stm32cube.ide.mcu.MCUProjectNature - com.st.stm32cube.ide.mcu.MCUCubeProjectNature - org.eclipse.cdt.core.cnature - com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature - com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature - com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature - com.st.stm32cube.ide.mcu.MCURootProjectNature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/Software/Flapy Bird/.settings/language.settings.xml b/Software/Flapy Bird/.settings/language.settings.xml deleted file mode 100644 index 6da1079..0000000 --- a/Software/Flapy Bird/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Software/Flapy Bird/.settings/stm32cubeide.project.prefs b/Software/Flapy Bird/.settings/stm32cubeide.project.prefs deleted file mode 100644 index 01d932f..0000000 --- a/Software/Flapy Bird/.settings/stm32cubeide.project.prefs +++ /dev/null @@ -1,5 +0,0 @@ -635E684B79701B039C64EA45C3F84D30=8367202309E85B9B3FAD95580DEE0559 -66BE74F758C12D739921AEA421D593D3=1 -8DF89ED150041C4CBC7CB9A9CAA90856=4BB9820116899354E6956783ED36B62A -DC22A860405A8BF2F2C095E5B6529F12=4BB9820116899354E6956783ED36B62A -eclipse.preferences.version=1 diff --git a/Software/Flapy Bird/Core/Inc/button.h b/Software/Flapy Bird/Core/Inc/button.h deleted file mode 100644 index 98f3580..0000000 --- a/Software/Flapy Bird/Core/Inc/button.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * button.h - * - * Created on: Jan 7, 2019 - * Author: Cuong - */ - -#ifndef BUTTON_H_ -#define BUTTON_H_ - -#define BUT_WIDTH 49 -#define BUT_HEIGH 48 - -unsigned short button[0x930] ={ -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, // 0x0010 (16) -0xB7FF, 0xBFFF, 0xCEB9, 0xE591, 0xEC8A, 0xFC06, 0xFB61, 0xFB20, 0xFB00, 0xFB20, 0xFB82, 0xFC27, 0xECEC, 0xDDF3, 0xCF3B, 0xB7FF, // 0x0020 (32) -0xB7FF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0030 (48) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, // 0x0040 (64) -0xDE56, 0xFC27, 0xFA60, 0xFA80, 0xFAA0, 0xFA80, 0xFB00, 0xE385, 0xDBC7, 0xDBC8, 0xDBC7, 0xE385, 0xFB00, 0xFA80, 0xFAA0, 0xFA80, // 0x0050 (80) -0xFAA0, 0xEC8A, 0xD6F9, 0xB7FF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0060 (96) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, 0xDD91, // 0x0070 (112) -0xFAC0, 0xFAA0, 0xFAA0, 0xEB63, 0xBC70, 0x8D39, 0x6DDF, 0x6DDF, 0x6DDF, 0x75BF, 0x75BF, 0x75BF, 0x75DF, 0x6DFF, 0x6DFF, 0x9539, // 0x0080 (128) -0xBC70, 0xEB63, 0xFA80, 0xFA80, 0xFB21, 0xE635, 0xB7FF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0090 (144) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xDE77, 0xFAC0, // 0x00A0 (160) -0xFAA0, 0xFAC0, 0xC44D, 0x7D9E, 0x6DDF, 0x7DDF, 0x965F, 0xA6BF, 0xAEFF, 0xB73F, 0xB73F, 0xB75F, 0xB73F, 0xAEFF, 0xA6BF, 0x965F, // 0x00B0 (176) -0x85FF, 0x759F, 0x6DFF, 0x7DBE, 0xC44D, 0xFAC0, 0xFA80, 0xFB20, 0xD6F9, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x00C0 (192) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, 0xFC27, 0xFA80, // 0x00D0 (208) -0xFAC0, 0xBC4E, 0x6DFF, 0x75BF, 0x965F, 0xAF1F, 0xBF7F, 0xB75F, 0xB75F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB75F, // 0x00E0 (224) -0xB75F, 0xBF7F, 0xB75F, 0x9E9F, 0x85DF, 0x75BF, 0x75FF, 0xC44E, 0xFAA0, 0xFA60, 0xF48A, 0xBFFF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x00F0 (240) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xC77D, 0xFAE0, 0xFAA0, // 0x0100 (256) -0xEB64, 0x7DBF, 0x75BF, 0x965F, 0xB75F, 0xB75F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, // 0x0110 (272) -0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xBF7F, 0xAEFF, 0x85DF, 0x75DF, 0x7DBE, 0xEB64, 0xFAA0, 0xFB00, 0xC79E, 0xB7FF, 0xBFDF, // 0x0120 (288) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xC6FA, 0xFA80, 0xFAA0, // 0x0130 (304) -0xBC6F, 0x6DFF, 0x85DF, 0xB73F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, // 0x0140 (320) -0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xBF7F, 0xA69F, 0x7D9F, 0x6E1F, 0xBC6F, 0xFAA0, 0xFA80, 0xC6FA, // 0x0150 (336) -0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xCEFA, 0xFA80, 0xFAC0, // 0x0160 (352) -0x9D18, 0x6DDF, 0x965F, 0xBF7F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB75F, 0xB75F, 0xB75F, 0xB75F, 0xB75F, 0xB75F, // 0x0170 (368) -0xB75F, 0xB75F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB73F, 0x85BE, 0x75FF, 0x9D17, 0xFAC0, // 0x0180 (384) -0xFA80, 0xCED9, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xCF9E, 0xFA80, 0xFAC0, // 0x0190 (400) -0x9559, 0x75BF, 0x9E9F, 0xBF7F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB75F, 0xB75F, 0xAEFF, 0xA69F, 0x9E5E, 0x9E3E, 0x9E1E, 0x9E1E, // 0x01A0 (416) -0x9E3E, 0x9E5E, 0xA69F, 0xAEDF, 0xB75F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB75F, 0x85BE, 0x75DF, // 0x01B0 (432) -0x9559, 0xFAC0, 0xFA80, 0xCF3C, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFFF, 0xFAE0, 0xFAA0, // 0x01C0 (448) -0x9538, 0x75BF, 0x9E9F, 0xBF7F, 0xB73F, 0xB73F, 0xB75F, 0xB77F, 0xAEFF, 0x9E5F, 0x95FE, 0x95FE, 0x961E, 0x9E1E, 0x9E1E, 0x9E3E, // 0x01D0 (464) -0x9E1E, 0x9E3E, 0x9E1E, 0x9E1E, 0x9E1E, 0x95FE, 0xA67F, 0xB75F, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xB75F, // 0x01E0 (480) -0x85BE, 0x7DDF, 0x9D18, 0xFAC0, 0xFAC0, 0xBFFF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xF427, 0xFAA0, // 0x01F0 (496) -0xB491, 0x75DF, 0x965E, 0xBF7F, 0xB73F, 0xB73F, 0xB75F, 0xAF1F, 0x961E, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3F, 0xA65F, 0xA67F, // 0x0200 (512) -0xA65F, 0x9E3E, 0xA63E, 0x9E3E, 0x9E3E, 0x9E3E, 0x9E3E, 0x9E1E, 0x95FE, 0xAEDF, 0xB75F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, 0xB73F, // 0x0210 (528) -0xB75F, 0xAF1F, 0x859E, 0x75FF, 0xB490, 0xFAA0, 0xFBC5, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xDE76, 0xFA80, // 0x0220 (544) -0xE3A6, 0x6DFF, 0x8DDE, 0xBF7F, 0xB73F, 0xB73F, 0xB75F, 0x9E5F, 0x8DDE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65F, 0x95FE, 0x6438, // 0x0230 (560) -0x5C17, 0x857C, 0xAE9F, 0xA65E, 0xA65E, 0xA65E, 0xA65E, 0xA63E, 0xA63E, 0x9E3E, 0x9E1E, 0xA67E, 0xB75F, 0xB75F, 0xB73F, 0xB73F, // 0x0240 (576) -0xB73F, 0xB73F, 0xBF7F, 0x963E, 0x85BE, 0x6E1F, 0xE385, 0xFA80, 0xDDF3, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFFF, 0xFAE0, // 0x0250 (592) -0xFAC0, 0x7DDF, 0x7D9F, 0xB73F, 0xB75F, 0xB75F, 0xB73F, 0x95FE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65F, 0x95DD, 0x84B7, // 0x0260 (608) -0xFFFF, 0xF7BF, 0xA579, 0x5BD7, 0xB6BF, 0xAE7F, 0xA65E, 0xA65E, 0xA65E, 0xA65E, 0xA65E, 0xA63E, 0x9E1E, 0x9E1E, 0xB73F, 0xB75F, // 0x0270 (624) -0xB73F, 0xB73F, 0xB73F, 0xB75F, 0xA6BF, 0x85BE, 0x85DF, 0x7DDF, 0xFAE0, 0xFAA0, 0xBFFF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xE5B1, // 0x0280 (640) -0xFA80, 0xB490, 0x75DF, 0x965F, 0xB75F, 0xB75F, 0xB73F, 0x8DDE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA63E, 0xAE7F, 0x6C79, // 0x0290 (656) -0xEF7E, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73D, 0x4B75, 0xAE5E, 0xAE9F, 0xAE7E, 0xAE5E, 0xA65E, 0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9DFE, // 0x02A0 (672) -0xA67F, 0xB73F, 0xB77F, 0xB77F, 0xB73F, 0x8DFE, 0x85DE, 0x85DE, 0x7DFF, 0xBC70, 0xFAA0, 0xE50E, 0xB7FF, 0xBFDF, 0xBFDF, 0xB7FF, // 0x02B0 (688) -0xFAC0, 0xFAE0, 0x75FF, 0x7D9E, 0xB75F, 0xB75F, 0xB75F, 0x8DDE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xAE7F, // 0x02C0 (704) -0x6C99, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x63D6, 0x8D9C, 0xB6DF, 0xAE7E, 0xAE7E, 0xAE5E, 0xA65E, 0xA65E, 0xA65E, // 0x02D0 (720) -0x9E3E, 0x9E1E, 0x95FE, 0x961E, 0x961E, 0x8DDE, 0x8DFE, 0x8DDE, 0x85DE, 0x85BF, 0x75FF, 0xFAE0, 0xFAA0, 0xBFFF, 0xBFDF, 0xB7FF, // 0x02E0 (736) -0xD635, 0xFA80, 0xBC70, 0x7DDF, 0x963F, 0xB75F, 0xB77F, 0x961E, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xA65E, // 0x02F0 (752) -0xAE9F, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8CF8, 0x6C58, 0xBEFF, 0xAE7E, 0xAE7E, 0xAE7E, 0xA65E, // 0x0300 (768) -0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x8DFE, 0x8DFE, 0x8DDE, 0x85DE, 0x7DDF, 0xBC70, 0xFAA0, 0xE5D3, 0xB7FF, // 0x0310 (784) -0xB7FF, 0xFC06, 0xFAA0, 0x7DDF, 0x7D9F, 0xAEFF, 0xB77F, 0x9E7F, 0x8DDE, 0x961E, 0x961E, 0x9E3E, 0x9E3E, 0xA63E, 0xA65E, 0xA65E, // 0x0320 (800) -0xAE7E, 0xB69F, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE9C, 0x4B76, 0xB6BF, 0xB69F, 0xAE7E, // 0x0330 (816) -0xAE7E, 0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9E3E, 0x961E, 0x961E, 0x95FE, 0x8DFE, 0x8DDE, 0x85DE, 0x85DF, 0x759F, 0xFAA0, 0xFBA3, // 0x0340 (832) -0xB7FF, 0xBFFF, 0xFA60, 0xE3A6, 0x75FF, 0x859E, 0xB75F, 0xB71F, 0x8DBE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0xA63E, 0xA65E, 0xA65E, // 0x0350 (848) -0xAE7E, 0xAE7E, 0xB6BF, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x5375, 0xA61D, // 0x0360 (864) -0xB6BF, 0xAE7E, 0xAE7E, 0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x961E, 0x8DFE, 0x8DFE, 0x8DDE, 0x85DE, 0x657F, 0xE3A6, // 0x0370 (880) -0xFA60, 0xBFFF, 0xD6B8, 0xFA80, 0xB492, 0x7DDF, 0x8DFE, 0xBF9F, 0x963E, 0x8DFE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, // 0x0380 (896) -0xAE5E, 0xAE7E, 0xAE7E, 0xB6BF, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x0390 (912) -0x7457, 0x7CFA, 0xBEFF, 0xAE7E, 0xAE5E, 0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x8DFE, 0x8DDE, 0x8DDE, 0x655F, // 0x03A0 (928) -0xB471, 0xFAA0, 0xD676, 0xE570, 0xFAA0, 0x8D7B, 0x7DBF, 0x963F, 0xB73F, 0x8DBE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, // 0x03B0 (944) -0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xBEDF, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x03C0 (960) -0xFFFF, 0xFFFF, 0xB5DA, 0x53D7, 0xBEDF, 0xAE7F, 0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x8DFE, 0x8DDE, 0x8DDE, // 0x03D0 (976) -0x6D5F, 0x851A, 0xFAA0, 0xE54F, 0xEC89, 0xFAA0, 0x6DFF, 0x85BE, 0x9E9F, 0x9E7F, 0x8DDE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0xA65E, // 0x03E0 (992) -0xA65E, 0xAE7E, 0xAE7E, 0xB67E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x03F0 (1008) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5E, 0x4B55, 0xAE5E, 0xAE9F, 0xA65E, 0xA63E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x8DFE, 0x8DDE, // 0x0400 (1024) -0x8DDE, 0x6D3E, 0x5D7F, 0xFAC0, 0xF468, 0xFBE5, 0xF321, 0x75FF, 0x85BE, 0xA6BF, 0x8DDE, 0x8DFE, 0x961E, 0x961E, 0x9E3E, 0x9E3E, // 0x0410 (1040) -0xA63E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x0420 (1056) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5BD6, 0x8D7C, 0xAE9F, 0xA63E, 0x9E3E, 0x9E3E, 0x961E, 0x961E, 0x95FE, // 0x0430 (1072) -0x8DFE, 0x8DFE, 0x6D1E, 0x5D7F, 0xFB20, 0xFBC4, 0xFB61, 0xE384, 0x75FF, 0x85BE, 0x9E5F, 0x8DDE, 0x95FE, 0x961E, 0x9E1E, 0x9E1E, // 0x0440 (1088) -0x9E3E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x0450 (1104) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x9D59, 0x6458, 0xAE9F, 0x9E3E, 0x9E1E, 0x9E1E, 0x961E, // 0x0460 (1120) -0x95FE, 0x8DFE, 0x8DFE, 0x64FE, 0x5D5F, 0xEB84, 0xFB40, 0xFB20, 0xE3A6, 0x75FF, 0x85BE, 0x8E1E, 0x8DDE, 0x95FE, 0x95FE, 0x9E1E, // 0x0470 (1136) -0x9E3E, 0xA63E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x0480 (1152) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xADDA, 0x6C79, 0xA67F, 0x9E3E, 0x9E1E, // 0x0490 (1168) -0x95FE, 0x95FE, 0x8DFE, 0x8DDE, 0x64DE, 0x5D5F, 0xE3C5, 0xFB00, 0xFB00, 0xE3A6, 0x75FF, 0x85BE, 0x8DDE, 0x8DDE, 0x95FE, 0x95FE, // 0x04A0 (1184) -0x9E1E, 0x9E3E, 0xA63E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, // 0x04B0 (1200) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x4B55, 0xAE9F, 0x9E3E, // 0x04C0 (1216) -0x9E1E, 0x95FE, 0x95FE, 0x8DFE, 0x7D9E, 0x64FE, 0x5D5F, 0xE3A5, 0xFB00, 0xFB40, 0xE384, 0x75FF, 0x85DE, 0x8DDE, 0x8DFE, 0x95FE, // 0x04D0 (1232) -0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, // 0x04E0 (1248) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD6DC, 0x6C99, 0xA65F, // 0x04F0 (1264) -0x9E1E, 0x9E1E, 0x961E, 0x8DFE, 0x95FE, 0x753E, 0x64FE, 0x5D5F, 0xEB84, 0xFB41, 0xFBC4, 0xF321, 0x75FF, 0x85DE, 0x8DDE, 0x8DFE, // 0x0500 (1280) -0x95FE, 0x961E, 0x961E, 0x9E3E, 0x9E3E, 0xA63E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, 0xFFFF, // 0x0510 (1296) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBE1B, 0x53D7, 0xAE9F, // 0x0520 (1312) -0x9E3E, 0x9E3E, 0x961E, 0x961E, 0x95FE, 0x8DFE, 0x64FE, 0x64FE, 0x657F, 0xFB20, 0xFBE5, 0xF448, 0xFAA0, 0x75FF, 0x85BE, 0x8DDE, // 0x0530 (1328) -0x8DDE, 0x8DFE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0xA65E, 0xA65E, 0xAE5E, 0xAE7E, 0xB67E, 0xB69E, 0xBEDF, 0x7CD9, 0xE73E, 0xFFFF, // 0x0540 (1344) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7C77, 0x74B9, 0xAEBF, // 0x0550 (1360) -0xA63E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x95FE, 0x7D9E, 0x64FE, 0x64FE, 0x659F, 0xFAA0, 0xF469, 0xE54F, 0xFAA0, 0x853B, 0x85DF, // 0x0560 (1376) -0x85DE, 0x8DDE, 0x8DFE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB69E, 0xBEDF, 0x74B9, 0xE73E, // 0x0570 (1392) -0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5375, 0x9DFD, 0xAE9F, // 0x0580 (1408) -0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x961E, 0x6CFE, 0x64FE, 0x651F, 0x851A, 0xFAA0, 0xE570, 0xDE76, 0xFAA0, 0xAC71, // 0x0590 (1424) -0x759F, 0x85DE, 0x8DDE, 0x8DFE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xAE5E, 0xAE7E, 0xAE7E, 0xB6BF, 0x74B9, // 0x05A0 (1440) -0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD6BC, 0x4B75, 0xB69F, 0xAE7F, // 0x05B0 (1456) -0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x961E, 0x859E, 0x64FE, 0x6D1E, 0x5D1F, 0xB491, 0xFAA0, 0xD697, 0xBFDF, 0xFA60, // 0x05C0 (1472) -0xE3A6, 0x5D3F, 0x8DDE, 0x85DE, 0x8DFE, 0x8DFE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, 0xAE7E, 0xAE7E, 0xB6BF, // 0x05D0 (1488) -0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x9518, 0x6458, 0xBEFF, 0xAE7E, // 0x05E0 (1504) -0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9E1E, 0x961E, 0x95FE, 0x961E, 0x64FE, 0x64FE, 0x64FE, 0x5D5F, 0xEBA5, 0xFA60, 0xBFFF, 0xB7FF, // 0x05F0 (1520) -0xFBA3, 0xFAC0, 0x6D5F, 0x6D5E, 0x8DFE, 0x8DDE, 0x8DFE, 0x95FE, 0x961E, 0x961E, 0x9E3E, 0x9E3E, 0xA63E, 0xA65E, 0xA65E, 0xAE7E, // 0x0600 (1536) -0xB69F, 0x74B9, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5BB6, 0x8D9C, 0xB6DF, 0xAE7E, // 0x0610 (1552) -0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9E3E, 0x961E, 0x961E, 0x961E, 0x753E, 0x64FE, 0x6D1E, 0x64FE, 0x757F, 0xFAA0, 0xFBE5, 0xB7FF, // 0x0620 (1568) -0xB7FF, 0xE5F3, 0xFAA0, 0xBC70, 0x5CFF, 0x7D9E, 0x8DDE, 0x8DFE, 0x8DFE, 0x95FE, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA65E, 0xA65E, // 0x0630 (1584) -0xA65E, 0xAE9F, 0x7499, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73E, 0x4B55, 0xAE7E, 0xB69F, 0xAE7E, // 0x0640 (1600) -0xA65E, 0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x961E, 0x859E, 0x64FE, 0x6D1E, 0x64FE, 0x5D1F, 0xBC70, 0xFAA0, 0xDE35, // 0x0650 (1616) -0xB7FF, 0xBFDF, 0xBFFF, 0xFAA0, 0xFB00, 0x5D7F, 0x64FE, 0x85BE, 0x8DFE, 0x8DFE, 0x95FE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0x9E3E, // 0x0660 (1632) -0xA65E, 0xA65E, 0xAE9F, 0x6C99, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xADBA, 0x5BD7, 0xB6DF, 0xAE7F, 0xAE5E, // 0x0670 (1648) -0xA65E, 0xA65E, 0xA65E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x961E, 0x8DDE, 0x64DE, 0x64FE, 0x6D1E, 0x64FE, 0x659F, 0xFB00, 0xFAC0, // 0x0680 (1664) -0xBFFF, 0xBFDF, 0xBFDF, 0xB7FF, 0xE52E, 0xFAA0, 0xB470, 0x5D1F, 0x64FE, 0x85BE, 0x8DFE, 0x8DFE, 0x95FE, 0x961E, 0x961E, 0x9E1E, // 0x0690 (1680) -0x9E3E, 0x9E3E, 0xA63E, 0xAE7F, 0x6C99, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7436, 0x7CFA, 0xB6DF, 0xAE5E, 0xA65E, // 0x06A0 (1696) -0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x961E, 0x8DDE, 0x64FE, 0x64FE, 0x6D1E, 0x64FE, 0x5D3F, 0xBC8F, 0xFAA0, // 0x06B0 (1712) -0xE591, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFFF, 0xFAC0, 0xFAE0, 0x6D7F, 0x64FE, 0x64FE, 0x85BE, 0x95FE, 0x8DFE, 0x95FE, 0x961E, // 0x06C0 (1728) -0x961E, 0x9E1E, 0x9E3E, 0x9E3E, 0xA67F, 0x6C99, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BF, 0x5375, 0x9DFD, 0xAE9F, 0xA65E, 0xA65E, // 0x06D0 (1744) -0xA65E, 0xA65E, 0xA63E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x9E1E, 0x8DDE, 0x64DE, 0x64FE, 0x6D1E, 0x6D1E, 0x64FE, 0x757F, 0xFAE0, // 0x06E0 (1760) -0xFAE0, 0xBFFF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xD614, 0xFA80, 0xEBA6, 0x555F, 0x64FE, 0x64FE, 0x755E, 0x961E, 0x95FE, // 0x06F0 (1776) -0x95FE, 0x961E, 0x961E, 0x9E1E, 0x9E3E, 0x9E3F, 0x8D9C, 0x63D6, 0xFFFF, 0xFFFF, 0xC65B, 0x4B96, 0xAE9F, 0xA67F, 0xA65E, 0xA63E, // 0x0700 (1792) -0xA63E, 0xA63E, 0x9E3E, 0x9E3E, 0x9E3E, 0x9E1E, 0x961E, 0x9E3E, 0x7D7E, 0x64DE, 0x64FE, 0x6D1E, 0x6D1E, 0x64FE, 0x5D7F, 0xEBA5, // 0x0710 (1808) -0xFA80, 0xDE77, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xF3E6, 0xFAA0, 0xB490, 0x5D3F, 0x64FE, 0x64FE, 0x6D1E, // 0x0720 (1824) -0x8DDE, 0x961E, 0x95FE, 0x961E, 0x961E, 0x9E1E, 0x9E1E, 0xA65F, 0x857C, 0x5BD7, 0x6437, 0x74DA, 0xAE9F, 0xA65E, 0x9E3E, 0x9E3E, // 0x0730 (1840) -0x9E3E, 0x9E3E, 0x9E3E, 0x9E3E, 0x9E1E, 0x9E1E, 0x9E3E, 0x961E, 0x6D1E, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x5D3F, 0xBC90, // 0x0740 (1856) -0xFAA0, 0xF428, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFFF, 0xFAE0, 0xFAC0, 0x9517, 0x5D1F, 0x64FE, // 0x0750 (1872) -0x64FE, 0x64DE, 0x753E, 0x8DFE, 0x961E, 0x961E, 0x961E, 0x961E, 0x961E, 0x9E3F, 0x9E5F, 0xA65F, 0x9E5F, 0x9E3E, 0x9E3E, 0x9E3E, // 0x0760 (1888) -0x9E3E, 0x9E1E, 0x9E1E, 0x9E1E, 0x9E1E, 0x9E3E, 0x961E, 0x755E, 0x64DE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x5D1F, 0x9CF7, // 0x0770 (1904) -0xFAC0, 0xFB00, 0xBFFF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xCF7E, 0xFA80, 0xFAC0, 0x9539, // 0x0780 (1920) -0x5D1F, 0x64FE, 0x6D1E, 0x64FE, 0x64DE, 0x6D3E, 0x85BE, 0x961E, 0x961E, 0x961E, 0x961E, 0x961E, 0x9E1E, 0x961E, 0x9E1E, 0x9E1E, // 0x0790 (1936) -0x9E1E, 0x9E1E, 0x9E3E, 0x9E3E, 0x9E3E, 0x8DDE, 0x755E, 0x64DE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x5D1F, 0x9519, // 0x07A0 (1952) -0xFAC0, 0xFAA0, 0xC7BF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xCEFA, 0xFA80, // 0x07B0 (1968) -0xFAC0, 0x9CF7, 0x553F, 0x64FE, 0x6D1E, 0x6D1E, 0x64FE, 0x64FE, 0x64DE, 0x6D3E, 0x7D7E, 0x85BE, 0x8DDE, 0x961E, 0x9E1E, 0x9E3E, // 0x07C0 (1984) -0x961E, 0x95FE, 0x8DDE, 0x7D9E, 0x755E, 0x64FE, 0x64FE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x553F, 0x9CF6, // 0x07D0 (2000) -0xFAC0, 0xFA80, 0xCF3B, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, // 0x07E0 (2016) -0xC71B, 0xFAA0, 0xFAA0, 0xC46F, 0x5D7F, 0x64FE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64DE, 0x64DE, // 0x07F0 (2032) -0x64DE, 0x64DE, 0x64DE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6CFE, 0x64FE, 0x557F, 0xC44E, // 0x0800 (2048) -0xFAA0, 0xFAA0, 0xC73B, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0810 (2064) -0xBFDF, 0xB7FF, 0xC7BF, 0xFB20, 0xFAA0, 0xF384, 0x757E, 0x5D3F, 0x64FE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, // 0x0820 (2080) -0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x5D1F, 0x755E, 0xF383, // 0x0830 (2096) -0xFAA0, 0xFB00, 0xC7BF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0840 (2112) -0xBFDF, 0xBFDF, 0xBFDF, 0xB7DF, 0xBFFF, 0xF4AB, 0xFA60, 0xFAC0, 0xC44E, 0x659F, 0x5D1F, 0x64FE, 0x64FE, 0x6D1E, 0x6D1E, 0x6D1E, // 0x0850 (2128) -0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x6D1E, 0x64FE, 0x651E, 0x5D1F, 0x657F, 0xC44D, 0xFAC0, // 0x0860 (2144) -0xFA60, 0xF48A, 0xBFFF, 0xB7DF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0870 (2160) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xD6FA, 0xFB21, 0xFA80, 0xFAC0, 0xCC4D, 0x755D, 0x5D7F, 0x5D1F, 0x651F, // 0x0880 (2176) -0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x64FE, 0x651F, 0x5D1F, 0x555F, 0x755D, 0xC44D, 0xFAE0, 0xFAA0, // 0x0890 (2192) -0xFB00, 0xD6D9, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x08A0 (2208) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, 0xE635, 0xFB21, 0xFA80, 0xFAA0, 0xF363, 0xBC6F, // 0x08B0 (2224) -0x8D19, 0x659F, 0x5D9F, 0x5D5F, 0x5D3F, 0x5D3F, 0x5D3F, 0x5D5F, 0x5D7F, 0x659F, 0x8CF9, 0xBC6F, 0xF363, 0xFAA0, 0xFA80, 0xFB00, // 0x08C0 (2240) -0xDDF3, 0xB7FF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x08D0 (2256) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, 0xD6D9, 0xEC8A, 0xFAA0, // 0x08E0 (2272) -0xFA80, 0xFAA0, 0xFAA0, 0xFB00, 0xEB85, 0xE3C6, 0xE3E7, 0xE3C6, 0xEB85, 0xFB00, 0xFAA0, 0xFAA0, 0xFA80, 0xFA80, 0xFC69, 0xD697, // 0x08F0 (2288) -0xB7FF, 0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0900 (2304) -0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xB7FF, 0xB7FF, // 0x0910 (2320) -0xB7FF, 0xCF1B, 0xDDD2, 0xECCB, 0xFC27, 0xFB82, 0xFB20, 0xFB00, 0xFB20, 0xFB82, 0xFC06, 0xECAA, 0xE5B1, 0xCEDA, 0xBFFF, 0xB7FF, // 0x0920 (2336) -0xB7FF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, 0xBFDF, // 0x0930 (2352) -}; - -#endif /* BUTTON_H_ */ diff --git a/Software/Flapy Bird/Core/Inc/font.h b/Software/Flapy Bird/Core/Inc/font.h deleted file mode 100644 index a0b4d9b..0000000 --- a/Software/Flapy Bird/Core/Inc/font.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * font.h - * - * Created on: Jan 5, 2019 - * Author: Cuong - */ - -#ifndef FONT_H_ -#define FONT_H_ - -#ifndef __FONT_H_ -#define __FONT_H_ - -#include "stm32f4xx_hal.h" -uint16_t font[96][5] = -{ - {0x00, 0x00, 0x00, 0x00, 0x00} // 20 - ,{0x00, 0x00, 0x5F, 0x00, 0x00} // 21 ! - ,{0x00, 0x07, 0x00, 0x07, 0x00} // 22 " - ,{0x14, 0x7F, 0x14, 0x7f, 0x14} // 23 # - ,{0x24, 0x2A, 0x7F, 0x2A, 0x12} // 24 $ - ,{0x23, 0x13, 0x08, 0x64, 0x62} // 25 % - ,{0x36, 0x49, 0x55, 0x22, 0x50} // 26 & - ,{0x00, 0x05, 0x03, 0x00, 0x00} // 27 ' - ,{0x00, 0x1C, 0x22, 0x41, 0x00} // 28 ( - ,{0x00, 0x41, 0x22, 0x1C, 0x00} // 29 ) - ,{0x14, 0x08, 0x3E, 0x08, 0x14} // 2a * - ,{0x08, 0x08, 0x3E, 0x08, 0x08} // 2b + - ,{0x00, 0x50, 0x30, 0x00, 0x00} // 2c , - ,{0x08, 0x08, 0x08, 0x08, 0x08} // 2d - - ,{0x00, 0x60, 0x60, 0x00, 0x00} // 2e . - ,{0x20, 0x10, 0x08, 0x04, 0x02} // 2f / - ,{0x3E, 0x51, 0x49, 0x45, 0x3E} // 30 0 - ,{0x00, 0x42, 0x7F, 0x40, 0x00} // 31 1 - ,{0x42, 0x61, 0x51, 0x49, 0x46} // 32 2 - ,{0x21, 0x41, 0x45, 0x4B, 0x31} // 33 3 - ,{0x18, 0x14, 0x12, 0x7F, 0x10} // 34 4 - ,{0x27, 0x45, 0x45, 0x45, 0x39} // 35 5 - ,{0x3C, 0x4a, 0x49, 0x49, 0x30} // 36 6 - ,{0x01, 0x71, 0x09, 0x05, 0x03} // 37 7 - ,{0x36, 0x49, 0x49, 0x49, 0x36} // 38 8 - ,{0x06, 0x49, 0x49, 0x29, 0x1E} // 39 9 - ,{0x00, 0x36, 0x36, 0x00, 0x00} // 3a : - ,{0x00, 0x56, 0x36, 0x00, 0x00} // 3b ; - ,{0x08, 0x14, 0x22, 0x41, 0x00} // 3c < - ,{0x14, 0x14, 0x14, 0x14, 0x14} // 3d = - ,{0x00, 0x41, 0x22, 0x14, 0x08} // 3e > - ,{0x02, 0x01, 0x51, 0x09, 0x06} // 3f ? - ,{0x32, 0x49, 0x79, 0x41, 0x3E} // 40 @ - ,{0x7E, 0x11, 0x11, 0x11, 0x7E} // 41 A - ,{0x7F, 0x49, 0x49, 0x49, 0x36} // 42 B - ,{0x3E, 0x41, 0x41, 0x41, 0x22} // 43 C - ,{0x7F, 0x41, 0x41, 0x22, 0x1C} // 44 D - ,{0x7F, 0x49, 0x49, 0x49, 0x41} // 45 E - ,{0x7F, 0x09, 0x09, 0x09, 0x01} // 46 F - ,{0x3E, 0x41, 0x49, 0x49, 0x7A} // 47 G - ,{0x7F, 0x08, 0x08, 0x08, 0x7F} // 48 H - ,{0x00, 0x41, 0x7F, 0x41, 0x00} // 49 I - ,{0x20, 0x40, 0x41, 0x3F, 0x01} // 4a J - ,{0x7F, 0x08, 0x14, 0x22, 0x41} // 4b K - ,{0x7F, 0x40, 0x40, 0x40, 0x40} // 4c L - ,{0x7F, 0x02, 0x0C, 0x02, 0x7F} // 4d M - ,{0x7F, 0x04, 0x08, 0x10, 0x7F} // 4e N - ,{0x3E, 0x41, 0x41, 0x41, 0x3E} // 4f O - ,{0x7F, 0x09, 0x09, 0x09, 0x06} // 50 P - ,{0x3E, 0x41, 0x51, 0x21, 0x5E} // 51 Q - ,{0x7F, 0x09, 0x19, 0x29, 0x46} // 52 R - ,{0x46, 0x49, 0x49, 0x49, 0x31} // 53 S - ,{0x01, 0x01, 0x7F, 0x01, 0x01} // 54 T - ,{0x3F, 0x40, 0x40, 0x40, 0x3F} // 55 U - ,{0x1F, 0x20, 0x40, 0x20, 0x1F} // 56 V - ,{0x3F, 0x40, 0x38, 0x40, 0x3F} // 57 W - ,{0x63, 0x14, 0x08, 0x14, 0x63} // 58 X - ,{0x07, 0x08, 0x70, 0x08, 0x07} // 59 Y - ,{0x61, 0x51, 0x49, 0x45, 0x43} // 5a Z - ,{0x00, 0x7F, 0x41, 0x41, 0x00} // 5b [ - ,{0x02, 0x04, 0x08, 0x10, 0x20} // 5c ? - ,{0x00, 0x41, 0x41, 0x7F, 0x00} // 5d ] - ,{0x04, 0x02, 0x01, 0x02, 0x04} // 5e ^ - ,{0x40, 0x40, 0x40, 0x40, 0x40} // 5f _ - ,{0x00, 0x01, 0x02, 0x04, 0x00} // 60 ` - ,{0x20, 0x54, 0x54, 0x54, 0x78} // 61 a - ,{0x7F, 0x48, 0x44, 0x44, 0x38} // 62 b - ,{0x38, 0x44, 0x44, 0x44, 0x20} // 63 c - ,{0x38, 0x44, 0x44, 0x48, 0x7F} // 64 d - ,{0x38, 0x54, 0x54, 0x54, 0x18} // 65 e - ,{0x08, 0x7E, 0x09, 0x01, 0x02} // 66 f - ,{0x0C, 0x52, 0x52, 0x52, 0x3E} // 67 g - ,{0x7F, 0x08, 0x04, 0x04, 0x78} // 68 h - ,{0x00, 0x44, 0x7D, 0x40, 0x00} // 69 i - ,{0x20, 0x40, 0x44, 0x3D, 0x00} // 6a j - ,{0x7F, 0x10, 0x28, 0x44, 0x00} // 6b k - ,{0x00, 0x41, 0x7F, 0x40, 0x00} // 6c l - ,{0x7C, 0x04, 0x18, 0x04, 0x78} // 6d m - ,{0x7C, 0x08, 0x04, 0x04, 0x78} // 6e n - ,{0x38, 0x44, 0x44, 0x44, 0x38} // 6f o - ,{0x7C, 0x14, 0x14, 0x14, 0x08} // 70 p - ,{0x08, 0x14, 0x14, 0x18, 0x7C} // 71 q - ,{0x7C, 0x08, 0x04, 0x04, 0x08} // 72 r - ,{0x48, 0x54, 0x54, 0x54, 0x20} // 73 s - ,{0x04, 0x3F, 0x44, 0x40, 0x20} // 74 t - ,{0x3C, 0x40, 0x40, 0x20, 0x7C} // 75 u - ,{0x1C, 0x20, 0x40, 0x20, 0x1C} // 76 v - ,{0x3C, 0x40, 0x30, 0x40, 0x3C} // 77 w - ,{0x44, 0x28, 0x10, 0x28, 0x44} // 78 x - ,{0x0C, 0x50, 0x50, 0x50, 0x3C} // 79 y - ,{0x44, 0x64, 0x54, 0x4C, 0x44} // 7a z - ,{0x00, 0x08, 0x36, 0x41, 0x00} // 7b { - ,{0x00, 0x00, 0x7F, 0x00, 0x00} // 7c | - ,{0x00, 0x41, 0x36, 0x08, 0x00} // 7d } - ,{0x10, 0x08, 0x08, 0x10, 0x08} // 7e ? - ,{0x78, 0x46, 0x41, 0x46, 0x78} // 7f ? -}; - -#endif - -#endif /* FONT_H_ */ diff --git a/Software/Flapy Bird/Core/Inc/image.h b/Software/Flapy Bird/Core/Inc/image.h deleted file mode 100644 index f87fd65..0000000 --- a/Software/Flapy Bird/Core/Inc/image.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * bird_image.h - * - * Created on: Jan 6, 2019 - * Author: Cuong - */ - -#ifndef IMAGE_H_ -#define IMAGE_H_ - -unsigned short bird_image[0x1EE] ={ -0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, 0xCFFF, 0xD7FF, 0x6410, 0x3A6A, 0x3A8A, 0x3A8A, 0x3A8A, 0x3A8A, 0x42AA, // 0x0010 (16) -0x42AA, 0x3208, 0xA679, 0xD7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, // 0x0020 (32) -0xBF7D, 0xB75D, 0xC7DF, 0x3A27, 0x0000, 0x0820, 0x0820, 0x0820, 0x0840, 0x0000, 0x0000, 0x0000, 0x8534, 0xBF9E, 0xCFFF, 0xC7FF, // 0x0030 (48) -0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, 0xE7FF, 0x1966, 0x0000, 0x0000, 0xBC60, 0xFF00, 0xFEC0, // 0x0040 (64) -0xFEC0, 0xFEE0, 0xFFC0, 0x4180, 0x0001, 0xFFFF, 0x3165, 0x0000, 0xEFFF, 0xCFFF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, // 0x0050 (80) -0xCFFF, 0xCFFF, 0xBF7D, 0x2A09, 0x8BA2, 0xAC20, 0xA3E0, 0xE580, 0xFE20, 0xFE20, 0xFE20, 0xEDC0, 0x4160, 0x8C4E, 0xB596, 0xFFFF, // 0x0060 (96) -0xC638, 0x9CF3, 0x29E7, 0x9E59, 0xCFFF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, 0xC7FF, 0xCFFF, 0xAEFB, 0x0000, 0xBC80, 0xFEA0, // 0x0070 (112) -0xFE80, 0xFE20, 0xFE20, 0xFE20, 0xFE40, 0xE580, 0x0000, 0xBDD7, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x0000, 0x8555, 0xCFFF, 0xCFFF, // 0x0080 (128) -0xC7FF, 0xC7FF, 0xD7FF, 0xB73C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xFF20, 0xFE40, 0xFE20, 0xFE20, 0xFE40, 0xE580, // 0x0090 (144) -0x0000, 0xB5B6, 0xFFFF, 0xFFFF, 0x3186, 0x0000, 0xFFFF, 0x41E7, 0x0000, 0xDFFF, 0xC7FF, 0xC7FF, 0x7CD3, 0x534D, 0x9CB2, 0x94B2, // 0x00A0 (160) -0x94B2, 0x94B2, 0x94B2, 0x8C70, 0x5A00, 0xD520, 0xFE40, 0xFE20, 0xFE40, 0xE580, 0x0000, 0xB5B6, 0xFFFF, 0xFFFF, 0x4228, 0x0020, // 0x00B0 (176) -0xFFFF, 0x4A28, 0x0020, 0xDFFF, 0xC7FF, 0xC7FF, 0x3228, 0x1061, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x0000, 0xBC60, // 0x00C0 (192) -0xFEC0, 0xFE20, 0xFE40, 0xE560, 0x0000, 0xBDF8, 0xFFFF, 0xFFFF, 0x31A6, 0x0000, 0xFFFF, 0x4A28, 0x0020, 0xDFFF, 0xC7FF, 0xC7FF, // 0x00D0 (208) -0x3A69, 0x10A3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x31CA, 0x0000, 0xFEC0, 0xFE20, 0xFE40, 0xFF60, 0x28E0, // 0x00E0 (224) -0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x4A69, 0x0041, 0xEFFF, 0xCFFF, 0xC7FF, 0x3A6A, 0x1080, 0xFFB0, 0xFFBB, 0xFFFF, 0xFFFF, // 0x00F0 (240) -0xFFFF, 0xFFDE, 0xFF8F, 0x39C4, 0x0840, 0xFEC0, 0xFE20, 0xFE20, 0xFE60, 0xA3E0, 0x7B01, 0x7C11, 0x7BEF, 0x7BEF, 0x8C51, 0x2104, // 0x0100 (256) -0x0000, 0x6410, 0xAEBA, 0xCFFF, 0x29C7, 0x0800, 0xFF20, 0xFFD9, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFF20, 0x3140, 0x0000, 0xFEC0, // 0x0110 (272) -0xFE20, 0xFE20, 0xFE20, 0xFF00, 0xFE60, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8DD7, 0xE7FF, 0xD7FF, 0xB75D, // 0x0120 (288) -0x0000, 0xBC60, 0xFE80, 0xFE40, 0xFE60, 0xED80, 0x0000, 0xBC80, 0xFEC0, 0xFE20, 0xFE20, 0xFE20, 0xFEE0, 0x3140, 0x0000, 0xFBC2, // 0x0130 (304) -0xFB81, 0xFB81, 0xFB81, 0xFB81, 0xFB81, 0xFBA2, 0x3820, 0x0041, 0xCFFF, 0xBF7D, 0x42CC, 0x8363, 0x9380, 0x9380, 0x9380, 0x8B60, // 0x0140 (320) -0x49C0, 0xCCE0, 0xFE00, 0xF5C0, 0xF5E0, 0xEDA0, 0x8B80, 0x69E0, 0x6120, 0x81C1, 0x81C1, 0x81C1, 0x81C1, 0x81C1, 0x81C1, 0x89A0, // 0x0150 (336) -0x62C9, 0x6430, 0xC7FF, 0xCFFF, 0xE7FF, 0x1946, 0x0000, 0x0000, 0x0000, 0x0840, 0xFE60, 0xE580, 0xE560, 0xE560, 0xE580, 0xC4C0, // 0x0160 (352) -0x0000, 0xB241, 0xF341, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8DD7, 0xDFFF, 0xC7FF, 0xC7FF, 0xCFFF, 0xC7FF, // 0x0170 (368) -0xC7FF, 0xD7FF, 0x29C7, 0x0800, 0xFE40, 0xEDA0, 0xEDA0, 0xE560, 0xE560, 0xE580, 0xF5C0, 0x3960, 0x0000, 0xFB81, 0xEB41, 0xEB41, // 0x0180 (384) -0xEB41, 0xF341, 0xDB01, 0x0000, 0x8D75, 0xCFFF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, 0xCFFF, 0xD7FF, 0x6410, 0x4A88, 0x9BA0, 0x9380, // 0x0190 (400) -0x9BC0, 0xEDA0, 0xE560, 0xE560, 0xF5C0, 0x72E0, 0x49A0, 0x9A01, 0x9A01, 0x9A01, 0x9A01, 0x9A01, 0x89E1, 0x0000, 0x8D75, 0xCFFF, // 0x01A0 (416) -0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xD7FF, 0xB75D, 0x0000, 0x0000, 0x0000, 0xFE80, 0xFE00, 0xFE00, 0xFE00, 0xFE60, // 0x01B0 (432) -0xEDA0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8534, 0xCFFF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, // 0x01C0 (448) -0xC7FF, 0xC7FF, 0xB73C, 0xBF7D, 0xA679, 0x0000, 0x0800, 0x0800, 0x0800, 0x0000, 0x18C1, 0xC7FF, 0xB75D, 0xB75D, 0xB75D, 0xB75D, // 0x01D0 (464) -0xB75D, 0xB73C, 0xC7DF, 0xCFFF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xC7FF, 0xCFFF, 0xCFFF, 0xBF9E, 0x3208, // 0x01E0 (480) -0x42AA, 0x42AA, 0x42AA, 0x3A8A, 0x4B0C, 0xDFFF, 0xCFFF, 0xCFFF, 0xCFFF, 0xCFFF, 0xCFFF, 0xCFFF, 0xCFFF, 0xC7FF, }; - - -#endif /* IMAGE_H_ */ diff --git a/Software/Flapy Bird/Core/Inc/line.h b/Software/Flapy Bird/Core/Inc/line.h deleted file mode 100644 index 856c259..0000000 --- a/Software/Flapy Bird/Core/Inc/line.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * line.h - * - * Created on: Jan 6, 2019 - * Author: Cuong - */ - -#ifndef LINE_H_ -#define LINE_H_ - -unsigned short line[0x640] ={ -0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xA6CA, 0xBF8E, 0xBF6D, 0xBF6D, 0xBF8E, 0xA6CB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAEEB, 0xBF8E, // 0x0010 (16) -0xBF6D, 0xBF8D, 0xBF8E, 0xA6AB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAF0C, 0xBF8D, 0xBF6D, 0xBF6D, 0xBF6D, 0xA6AA, 0x9EAA, 0x9EAA, // 0x0020 (32) -0x9EAA, 0x9E8A, 0xAF2C, 0xBF8D, 0xBF6D, 0xBF8D, 0xBF8E, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB72C, 0xBF6D, 0xBF6D, 0xBF8D, // 0x0030 (48) -0xB74D, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB76D, 0xBF6D, 0xB76D, 0xBF8E, 0xB74C, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, // 0x0040 (64) -0xB76D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAF2C, 0x9E8A, 0x9EAA, 0x9EAA, 0x9E8A, 0x9EAA, 0xBF8D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAEEB, 0x9EAA, // 0x0050 (80) -0x9EAA, 0x9EAA, 0x9E8A, 0xA6CB, 0xBF8E, 0xBF6D, 0xBF6D, 0xBF8E, 0xA6EB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xA6CB, 0xBF8E, 0xBF6D, // 0x0060 (96) -0xBF6D, 0xBF8D, 0xA6CB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAEEB, 0xBF8D, 0xBF6D, 0xBF8D, 0xBF8E, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, // 0x0070 (112) -0x9E8A, 0xAF0C, 0xBF8D, 0xBF6D, 0xBF8D, 0xBF6D, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB72C, 0xBF6D, 0xBF6D, 0xBF8E, 0xB76D, // 0x0080 (128) -0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB74D, 0xBF6D, 0xBF6D, 0xBF8E, 0xB74D, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB76D, // 0x0090 (144) -0xBF6D, 0xBF6D, 0xBF8E, 0xAF2C, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, 0xBF8E, 0xBF6D, 0xBF6D, 0xBF8E, 0xAF0C, 0x9EAA, 0x9EAA, // 0x00A0 (160) -0x9EAA, 0x9E8A, 0xA6CB, 0xBF6D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAEEB, 0x9E8A, 0x9EAA, 0x9EAA, 0x9E8A, 0xA6CB, 0xBF8D, 0xBF6D, 0xBF6D, // 0x00B0 (176) -0xBF8E, 0xA6CB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xA6EB, 0xBF8E, 0xBF6D, 0xBF6D, 0xBF8E, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, // 0x00C0 (192) -0xAF0C, 0xBF8D, 0xBF6D, 0xBF8D, 0xB76D, 0xA6AA, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAF2C, 0xBF8D, 0xBF6D, 0xBF8D, 0xBF8D, 0x9E8A, // 0x00D0 (208) -0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB72C, 0xBF6D, 0xBF6D, 0xBF8E, 0xB74D, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB76D, 0xBF6D, // 0x00E0 (224) -0xBF6D, 0xBF8E, 0xB72C, 0x9E8A, 0x9EAA, 0x9EAA, 0x9E8A, 0x9EAA, 0xB76D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAF2C, 0x9E8A, 0x9EAA, 0x9EAA, // 0x00F0 (240) -0x9E8A, 0xA6AA, 0xBF8D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAF0B, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xA6CA, 0xBF8E, 0xBF6D, 0xBF6D, 0xBF8E, // 0x0100 (256) -0xA6CB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAEEB, 0xBF8D, 0xBF6D, 0xBF6D, 0xBF8E, 0xA6CB, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAF0C, // 0x0110 (272) -0xBF8D, 0xBF6D, 0xBF8D, 0xBF8D, 0xA6AA, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xAF2C, 0xBF8D, 0xBF6D, 0xBF8D, 0xBF6D, 0x9E8A, 0x9EAA, // 0x0120 (288) -0x9EAA, 0x9EAA, 0x9E8A, 0xB74D, 0xBF6D, 0xBF6D, 0xBF8D, 0xB74D, 0x9EAA, 0x9EAA, 0x9EAA, 0x9EAA, 0x9E8A, 0xB76D, 0xBF6D, 0xBF6D, // 0x0130 (304) -0xBF8E, 0xB74D, 0x9E8A, 0x9EAA, 0x9EAA, 0x9E8A, 0x9EAA, 0xB76D, 0xBF6D, 0xBF6D, 0xBF8E, 0xAF2C, 0x9E8A, 0x9EAA, 0x9EAA, 0x9EAA, // 0x0140 (320) -0x6DE5, 0x6DE5, 0x6DC5, 0x7626, 0x9F2A, 0x9F2A, 0x9F4A, 0x9F4B, 0x7E67, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E47, 0x972A, 0x9F2A, // 0x0150 (336) -0x9F4B, 0x972A, 0x7E47, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x8667, 0x9F2A, 0x9F2A, 0x9F4B, 0x972A, 0x7626, 0x6DE5, 0x6DE5, 0x6DC5, // 0x0160 (352) -0x6DE5, 0x8688, 0x9F4A, 0x9F4A, 0x9F4B, 0x970A, 0x7605, 0x6DC5, 0x6DE5, 0x6DC5, 0x6DE5, 0x8EA8, 0x9F2A, 0x9F2A, 0x9F4B, 0x96E9, // 0x0170 (368) -0x75E5, 0x6DE5, 0x6DE5, 0x6DC5, 0x6DE5, 0x8EC9, 0x9F4A, 0x9F2A, 0x9F4B, 0x8EE9, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7606, 0x96E9, // 0x0180 (384) -0x9F2A, 0x9F4A, 0x9F4B, 0x8EA8, 0x6DE5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7606, 0x972A, 0x9F2A, 0x9F2A, 0x9F4B, 0x8688, 0x6DC5, 0x6DE5, // 0x0190 (400) -0x6DE5, 0x6DC5, 0x7E26, 0x970A, 0x9F4A, 0x9F4A, 0x9F2A, 0x8667, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E47, 0x9F2A, 0x9F2A, 0x9F4B, // 0x01A0 (416) -0x9F2A, 0x7E47, 0x6DC5, 0x6DE5, 0x6DC5, 0x6DC5, 0x7E47, 0x9F2A, 0x9F2A, 0x9F4B, 0x972A, 0x7626, 0x6DC5, 0x6DE5, 0x6DC5, 0x6DC5, // 0x01B0 (432) -0x8688, 0x9F2A, 0x9F2A, 0x9F4B, 0x970A, 0x7606, 0x6DC5, 0x6DE5, 0x6DC5, 0x6DC5, 0x86A8, 0x9F4A, 0x9F2A, 0x9F4B, 0x970A, 0x75E5, // 0x01C0 (448) -0x6DE5, 0x6DE5, 0x6DC5, 0x75E5, 0x8EC9, 0x9F2A, 0x9F4A, 0x9F4B, 0x8EE9, 0x6DE5, 0x6DE5, 0x6DE5, 0x6DC5, 0x75E5, 0x96E9, 0x9F2A, // 0x01D0 (464) -0x9F4A, 0x9F4B, 0x8EC8, 0x6DE5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7606, 0x970A, 0x9F4A, 0x9F2A, 0x9F4B, 0x86A8, 0x6DC5, 0x6DE5, 0x6DE5, // 0x01E0 (480) -0x6DC5, 0x7626, 0x970A, 0x9F2A, 0x9F4B, 0x9F2A, 0x8687, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E26, 0x9F2A, 0x9F2A, 0x9F4A, 0x9F2A, // 0x01F0 (496) -0x7E47, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E67, 0x9F2A, 0x9F2A, 0x9F4B, 0x9F2A, 0x7E26, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x8687, // 0x0200 (512) -0x9F2A, 0x9F4A, 0x9F4B, 0x970A, 0x7626, 0x6DE5, 0x6DE5, 0x6DC5, 0x6DE5, 0x8688, 0x9F4A, 0x9F4A, 0x9F4B, 0x970A, 0x75E5, 0x6DC5, // 0x0210 (528) -0x6DE5, 0x6DC5, 0x6DE5, 0x8EC9, 0x9F2A, 0x9F4A, 0x9F4B, 0x8EE9, 0x75E5, 0x6DC5, 0x6DE5, 0x6DC5, 0x75E5, 0x8EE9, 0x9F2A, 0x9F2A, // 0x0220 (544) -0x9F4B, 0x8EC9, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7606, 0x96E9, 0x9F2A, 0x9F2A, 0x9F4B, 0x8EA8, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, // 0x0230 (560) -0x7606, 0x972A, 0x9F2A, 0x9F4A, 0x9F4B, 0x8667, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E26, 0x972A, 0x9F2A, 0x9F4B, 0x9F4A, 0x7E67, // 0x0240 (576) -0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7E47, 0x9F2A, 0x9F2A, 0x9F4B, 0x972A, 0x7E47, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x8667, 0x9F2A, // 0x0250 (592) -0x9F2A, 0x9F4B, 0x972A, 0x7606, 0x6DE5, 0x6DE5, 0x6DC5, 0x6DC5, 0x86A8, 0x9F2A, 0x9F4A, 0x9F4B, 0x970A, 0x7606, 0x6DC5, 0x6DE5, // 0x0260 (608) -0x6DC5, 0x6DE5, 0x8EA8, 0x9F2A, 0x9F4A, 0x9F4B, 0x96E9, 0x75E5, 0x6DE5, 0x6DE5, 0x6DC5, 0x75E5, 0x8EC9, 0x9F2A, 0x9F4A, 0x9F4B, // 0x0270 (624) -0x8EE9, 0x6DC5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7605, 0x96E9, 0x9F2A, 0x9F4A, 0x9F4B, 0x8EA8, 0x6DE5, 0x6DE5, 0x6DE5, 0x6DC5, 0x7606, // 0x0280 (640) -0x75E6, 0x75E5, 0x8667, 0x9F4B, 0x9F4B, 0x9F4B, 0x9F2B, 0x7E47, 0x75C5, 0x75E6, 0x75E5, 0x75C5, 0x8E88, 0x9F4B, 0x9F4B, 0x9F4B, // 0x0290 (656) -0x9F0A, 0x7E27, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x8EA8, 0xA76B, 0x9F4B, 0xA74B, 0x970A, 0x7E06, 0x75E5, 0x75E6, 0x75E5, 0x75E6, // 0x02A0 (672) -0x8EC9, 0xA74B, 0x9F4B, 0xA74B, 0x96EA, 0x75E6, 0x75E5, 0x75E6, 0x75E5, 0x75E5, 0x96EA, 0xA74B, 0x9F4B, 0xA74B, 0x96C9, 0x75E6, // 0x02B0 (688) -0x75E5, 0x75E6, 0x75E5, 0x7E06, 0x96EA, 0xA74B, 0x9F4B, 0xA74B, 0x8EA9, 0x6DC5, 0x75E6, 0x75E6, 0x75C5, 0x7E26, 0x9F0A, 0xA74B, // 0x02C0 (704) -0x9F4B, 0xA74B, 0x8E88, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x7E27, 0x9F2B, 0x9F4B, 0x9F4B, 0xA74B, 0x8667, 0x75C5, 0x75E6, 0x75E6, // 0x02D0 (720) -0x75C5, 0x8668, 0x9F2B, 0x9F4B, 0x9F4B, 0x9F2B, 0x8647, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x8668, 0xA74B, 0x9F4B, 0x9F4B, 0x9F2B, // 0x02E0 (736) -0x7E27, 0x75C5, 0x75E6, 0x75E6, 0x75E5, 0x8E88, 0xA74B, 0x9F4B, 0x9F4B, 0x9F0A, 0x7E06, 0x75C5, 0x75E6, 0x75E5, 0x75C5, 0x8EC9, // 0x02F0 (752) -0xA74B, 0x9F4B, 0xA74B, 0x96EA, 0x7606, 0x75E5, 0x75E6, 0x75E5, 0x75E6, 0x96C9, 0xA74B, 0x9F4B, 0xA74B, 0x96C9, 0x75E5, 0x75E5, // 0x0300 (768) -0x75E6, 0x75E5, 0x7606, 0x970A, 0xA74B, 0x9F2B, 0xA74B, 0x8EA9, 0x75E5, 0x75E6, 0x75E6, 0x75E5, 0x7E06, 0x9F0A, 0x9F4B, 0x9F4B, // 0x0310 (784) -0xA74B, 0x8E88, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x7E27, 0x9F2A, 0xA74B, 0x9F4B, 0xA74B, 0x8688, 0x6DC5, 0x75E6, 0x75E6, 0x75C5, // 0x0320 (800) -0x8647, 0x9F2B, 0x9F4B, 0x9F4B, 0x9F4B, 0x8647, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x8668, 0xA74B, 0x9F4B, 0x9F4B, 0x9F2B, 0x7E27, // 0x0330 (816) -0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x8E88, 0x9F4B, 0x9F4B, 0x9F4B, 0x9F0A, 0x7E27, 0x75E5, 0x75E6, 0x75E6, 0x75C5, 0x8EA9, 0xA76B, // 0x0340 (832) -0x9F4B, 0xA74B, 0x970A, 0x7606, 0x75E5, 0x75E6, 0x75E5, 0x75E6, 0x96C9, 0xA74B, 0x9F4B, 0xA74B, 0x96E9, 0x75E6, 0x75E5, 0x75E6, // 0x0350 (848) -0x75E5, 0x75E6, 0x96EA, 0xA74B, 0x9F4B, 0xA74B, 0x8EA9, 0x75E6, 0x75E5, 0x75E6, 0x75E5, 0x7E06, 0x970A, 0xA74B, 0x9F4B, 0xA74B, // 0x0360 (864) -0x8EA9, 0x6DC5, 0x75E6, 0x75E6, 0x75C5, 0x7E27, 0x9F2A, 0xA74B, 0x9F4B, 0x9F4B, 0x8688, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x7E47, // 0x0370 (880) -0x9F4B, 0x9F4B, 0x9F4B, 0xA76B, 0x8647, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x8667, 0x9F2B, 0x9F4B, 0x9F4B, 0x9F2B, 0x8647, 0x75C5, // 0x0380 (896) -0x75E6, 0x75E5, 0x75C5, 0x8688, 0xA74B, 0x9F4B, 0x9F4B, 0x9F2A, 0x7E26, 0x75C5, 0x75E6, 0x75E6, 0x75E5, 0x8EA9, 0xA76B, 0x9F2B, // 0x0390 (912) -0x9F4B, 0x9F0A, 0x7E06, 0x75E5, 0x75E6, 0x75E6, 0x75E5, 0x8EC9, 0xA74B, 0x9F4B, 0xA74B, 0x96E9, 0x7606, 0x75E5, 0x75E6, 0x75E5, // 0x03A0 (928) -0x75E6, 0x96EA, 0xA74B, 0x9F4B, 0xA74B, 0x96C9, 0x75E6, 0x75E5, 0x75E6, 0x75E5, 0x7E06, 0x96EA, 0xA74B, 0x9F4B, 0xA74B, 0x8EA9, // 0x03B0 (944) -0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x7E26, 0x9F0A, 0xA74B, 0x9F4B, 0xA74B, 0x8688, 0x75C5, 0x75E6, 0x75E6, 0x75C5, 0x7E27, 0x9F2B, // 0x03C0 (960) -0x7606, 0x8EC9, 0xA76B, 0xA76B, 0xA76B, 0x9F2A, 0x7E26, 0x75E5, 0x7606, 0x7606, 0x7606, 0x96E9, 0xA78B, 0xA76B, 0xA76B, 0x972A, // 0x03D0 (976) -0x7606, 0x7605, 0x7606, 0x7606, 0x7626, 0x970A, 0xA78B, 0xA76B, 0x9F6B, 0x970A, 0x7606, 0x7605, 0x7606, 0x7606, 0x7626, 0x9F2A, // 0x03E0 (992) -0xA76B, 0xA76B, 0xA76B, 0x8EC9, 0x7606, 0x7606, 0x7606, 0x7606, 0x7E46, 0x9F4B, 0xA78B, 0xA76B, 0x9F6B, 0x8EA8, 0x7605, 0x7606, // 0x03F0 (1008) -0x7606, 0x7606, 0x7E67, 0x9F4B, 0xA76B, 0xA76B, 0x9F6B, 0x86A8, 0x75E5, 0x7606, 0x7606, 0x7606, 0x8667, 0xA76B, 0xA76B, 0xA76B, // 0x0400 (1024) -0x9F4B, 0x7E67, 0x7605, 0x7606, 0x7606, 0x7606, 0x86A8, 0xA76B, 0xA76B, 0xA76B, 0x9F4B, 0x7E47, 0x75E5, 0x7606, 0x7606, 0x7606, // 0x0410 (1040) -0x8EC9, 0xA76B, 0xA76B, 0xA76B, 0x9F2A, 0x7E26, 0x75E5, 0x7606, 0x7606, 0x7606, 0x8EE9, 0xA78B, 0xA76B, 0xA76B, 0x9F4A, 0x7606, // 0x0420 (1056) -0x7605, 0x7606, 0x7606, 0x7626, 0x9709, 0xA76B, 0xA76B, 0xA76B, 0x9709, 0x7606, 0x7605, 0x7606, 0x7606, 0x7626, 0x9F2A, 0xA78B, // 0x0430 (1072) -0xA76B, 0xA76B, 0x8EE9, 0x7606, 0x7606, 0x7606, 0x7606, 0x7E47, 0x9F2A, 0xA78B, 0xA76B, 0x9F6B, 0x8EC9, 0x7605, 0x7606, 0x7606, // 0x0440 (1088) -0x7606, 0x7E47, 0x9F6B, 0xA76B, 0xA76B, 0x9F6B, 0x8688, 0x7605, 0x7606, 0x7606, 0x7606, 0x8667, 0xA76B, 0xA76B, 0x9F6B, 0x9F6B, // 0x0450 (1104) -0x8667, 0x75E5, 0x7606, 0x7606, 0x7606, 0x8688, 0xA76B, 0xA76B, 0x9F6B, 0x9F4B, 0x7E67, 0x75E5, 0x7606, 0x7606, 0x7606, 0x8EA8, // 0x0460 (1120) -0xA76B, 0xA76B, 0xA76B, 0x9F4B, 0x7E26, 0x7605, 0x7606, 0x7606, 0x7606, 0x8EC9, 0xA78B, 0xA76B, 0xA76B, 0x9F2A, 0x7626, 0x7605, // 0x0470 (1136) -0x7606, 0x7606, 0x7606, 0x970A, 0xA76B, 0xA76B, 0xA76B, 0x970A, 0x7606, 0x7605, 0x7606, 0x7606, 0x7626, 0x972A, 0xA78C, 0xA76B, // 0x0480 (1152) -0xA76B, 0x96E9, 0x7606, 0x7606, 0x7606, 0x7606, 0x7E46, 0x9F2A, 0xA76B, 0xA76B, 0x9F6B, 0x8EC9, 0x7606, 0x7606, 0x7606, 0x7606, // 0x0490 (1168) -0x7E46, 0xA76B, 0xA76B, 0x9F6B, 0x9F6B, 0x86A8, 0x7605, 0x7606, 0x7606, 0x7606, 0x8667, 0x9F4B, 0xA76B, 0xA76B, 0x9F6B, 0x8688, // 0x04A0 (1184) -0x75E5, 0x7606, 0x7606, 0x7605, 0x8688, 0xA76B, 0xA76B, 0xA76B, 0x9F4B, 0x8667, 0x75E5, 0x7606, 0x7606, 0x7606, 0x86A8, 0xA76B, // 0x04B0 (1200) -0xA76B, 0xA76B, 0x9F4B, 0x7E26, 0x75E5, 0x7606, 0x7606, 0x7606, 0x8EC9, 0xA76B, 0xA76B, 0xA76B, 0x972A, 0x7E26, 0x75E5, 0x7606, // 0x04C0 (1216) -0x7606, 0x7606, 0x96E9, 0xA78B, 0xA76B, 0xA76B, 0x972A, 0x7606, 0x7605, 0x7606, 0x7606, 0x7E26, 0x970A, 0xA76B, 0xA76B, 0x9F6B, // 0x04D0 (1232) -0x96E9, 0x7606, 0x7605, 0x7606, 0x7606, 0x7626, 0x9F4A, 0xA76B, 0xA76B, 0xA76B, 0x8EC9, 0x7606, 0x7606, 0x7606, 0x7606, 0x7E47, // 0x04E0 (1248) -0x9F4B, 0xA78B, 0xA76B, 0x9F6B, 0x8EA8, 0x75E5, 0x7606, 0x7606, 0x7606, 0x7E67, 0x9F6B, 0xA76B, 0xA76B, 0x9F6B, 0x86A8, 0x75E5, // 0x04F0 (1264) -0x7606, 0x7606, 0x7606, 0x7E67, 0xA76B, 0xA76B, 0xA76B, 0x9F4B, 0x7E67, 0x7605, 0x7606, 0x7606, 0x7606, 0x8EA8, 0xA76B, 0xA76B, // 0x0500 (1280) -0x6D25, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6505, 0x64E4, 0x64E4, 0x64E5, 0x64E4, 0x6D46, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DC8, 0x64E4, // 0x0510 (1296) -0x64E4, 0x6504, 0x6505, 0x64E4, 0x7566, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x64E4, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x7D87, 0x7DC8, // 0x0520 (1312) -0x7DA7, 0x7DA7, 0x7587, 0x64E4, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x7DA7, 0x7DC7, 0x7DA7, 0x7DA7, 0x7587, 0x64E4, 0x6504, 0x6504, // 0x0530 (1328) -0x6505, 0x64E4, 0x7DA7, 0x7DA7, 0x7DA7, 0x7DA7, 0x7566, 0x64E4, 0x64E4, 0x6504, 0x6505, 0x6505, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, // 0x0540 (1344) -0x6D46, 0x64E4, 0x64E4, 0x6505, 0x6504, 0x6D25, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6D25, 0x64E4, 0x64E4, 0x6505, 0x64E5, 0x6D25, // 0x0550 (1360) -0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6505, 0x64E4, 0x6504, 0x6505, 0x64E4, 0x6D46, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DC8, 0x64E4, 0x64E4, // 0x0560 (1376) -0x64E4, 0x6505, 0x64E4, 0x7566, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x64E4, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x7587, 0x7DC7, 0x7DA7, // 0x0570 (1392) -0x7DA7, 0x7DA7, 0x64C4, 0x64E4, 0x6504, 0x6505, 0x64E4, 0x7587, 0x7DC7, 0x7DA7, 0x7DA7, 0x7587, 0x64E4, 0x6504, 0x64E4, 0x6505, // 0x0580 (1408) -0x64E4, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x7566, 0x64E4, 0x6505, 0x6504, 0x6505, 0x6505, 0x7DA7, 0x7DA7, 0x7DA7, 0x7DA7, 0x6D46, // 0x0590 (1424) -0x64E4, 0x6504, 0x64E4, 0x6505, 0x6505, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6D45, 0x64E4, 0x6504, 0x6504, 0x6505, 0x6D25, 0x7DC8, // 0x05A0 (1440) -0x7DA7, 0x7DA7, 0x7DC8, 0x6505, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x6D46, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6505, 0x64E4, 0x64E4, // 0x05B0 (1456) -0x6505, 0x64E4, 0x7566, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x64E4, 0x64E4, 0x6504, 0x6505, 0x64E4, 0x7566, 0x7DC8, 0x7DA7, 0x7DA7, // 0x05C0 (1472) -0x7DA7, 0x64C4, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x7DA7, 0x7DC7, 0x7DA7, 0x7DA7, 0x7587, 0x64E4, 0x64E4, 0x64E4, 0x6505, 0x64E4, // 0x05D0 (1488) -0x7DA7, 0x7DA7, 0x7DA7, 0x7DA7, 0x7566, 0x64E4, 0x6504, 0x64E4, 0x6505, 0x6505, 0x7DA7, 0x7DA7, 0x7DA7, 0x7DA7, 0x7566, 0x64E4, // 0x05E0 (1504) -0x6504, 0x6504, 0x6505, 0x64E4, 0x85C8, 0x7DA7, 0x7DA7, 0x7DC7, 0x6D25, 0x64E4, 0x64E4, 0x6504, 0x6504, 0x6D25, 0x7DC8, 0x7DA7, // 0x05F0 (1520) -0x7DA7, 0x7DA8, 0x6D25, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x6D25, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6505, 0x64E4, 0x6504, 0x6505, // 0x0600 (1536) -0x64E4, 0x6D46, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DC8, 0x64E4, 0x64E4, 0x6504, 0x6505, 0x64E4, 0x7566, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, // 0x0610 (1552) -0x64E4, 0x64E4, 0x64E4, 0x6505, 0x64E4, 0x7587, 0x7DC7, 0x7DA7, 0x7DA7, 0x7DA7, 0x64E4, 0x6504, 0x64E4, 0x6505, 0x64E4, 0x7DA7, // 0x0620 (1568) -0x7DA7, 0x7DA7, 0x7DA7, 0x7587, 0x64E4, 0x6504, 0x6504, 0x6505, 0x64E4, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x7566, 0x64E4, 0x64E4, // 0x0630 (1584) -0x6504, 0x6505, 0x6505, 0x7DC8, 0x7DA7, 0x7DA7, 0x7DA7, 0x6D46, 0x64E4, 0x64E4, 0x6504, 0x6505, 0x6D25, 0x7DC8, 0x7DA7, 0x7DA7, // 0x0640 (1600) -}; - -#endif /* LINE_H_ */ diff --git a/Software/Flapy Bird/Core/Inc/main.h b/Software/Flapy Bird/Core/Inc/main.h deleted file mode 100644 index 051b78f..0000000 --- a/Software/Flapy Bird/Core/Inc/main.h +++ /dev/null @@ -1,114 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); - -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -/* Private defines -----------------------------------------------------------*/ -#define D2_Pin GPIO_PIN_2 -#define D2_GPIO_Port GPIOE -#define D3_Pin GPIO_PIN_3 -#define D3_GPIO_Port GPIOE -#define D4_Pin GPIO_PIN_4 -#define D4_GPIO_Port GPIOE -#define D5_Pin GPIO_PIN_5 -#define D5_GPIO_Port GPIOE -#define D6_Pin GPIO_PIN_6 -#define D6_GPIO_Port GPIOE -#define D7_Pin GPIO_PIN_7 -#define D7_GPIO_Port GPIOE -#define D8_Pin GPIO_PIN_8 -#define D8_GPIO_Port GPIOE -#define D9_Pin GPIO_PIN_9 -#define D9_GPIO_Port GPIOE -#define D10_Pin GPIO_PIN_10 -#define D10_GPIO_Port GPIOE -#define D11_Pin GPIO_PIN_11 -#define D11_GPIO_Port GPIOE -#define D12_Pin GPIO_PIN_12 -#define D12_GPIO_Port GPIOE -#define D13_Pin GPIO_PIN_13 -#define D13_GPIO_Port GPIOE -#define D14_Pin GPIO_PIN_14 -#define D14_GPIO_Port GPIOE -#define D15_Pin GPIO_PIN_15 -#define D15_GPIO_Port GPIOE -#define CS_Pin GPIO_PIN_10 -#define CS_GPIO_Port GPIOB -#define T_IRQ_Pin GPIO_PIN_1 -#define T_IRQ_GPIO_Port GPIOD -#define RESET_Pin GPIO_PIN_3 -#define RESET_GPIO_Port GPIOD -#define RD_Pin GPIO_PIN_4 -#define RD_GPIO_Port GPIOD -#define WR_Pin GPIO_PIN_5 -#define WR_GPIO_Port GPIOD -#define RS_Pin GPIO_PIN_6 -#define RS_GPIO_Port GPIOD -#define T_CS_Pin GPIO_PIN_7 -#define T_CS_GPIO_Port GPIOD -#define D0_Pin GPIO_PIN_0 -#define D0_GPIO_Port GPIOE -#define D1_Pin GPIO_PIN_1 -#define D1_GPIO_Port GPIOE -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H */ diff --git a/Software/Flapy Bird/Core/Inc/ssd1289.h b/Software/Flapy Bird/Core/Inc/ssd1289.h deleted file mode 100644 index b2b4d26..0000000 --- a/Software/Flapy Bird/Core/Inc/ssd1289.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * ssd1289.h - * - * Created on: Jan 5, 2019 - * Author: Cuong - */ - -#ifndef SSD1289_H_ -#define SSD1289_H_ - -#include "stm32f4xx_hal.h" - -#define MAX_X 319 -#define MAX_Y 239 - -#define YES 1 -#define NO 0 - -#define Blue 0x001F -#define Red 0xF800 -#define Yellow 0xFFE0 -#define Green 0x07E0 -#define White 0xFFFF -#define Black 0x0000 -#define Pill_Color 0x1E04 -#define Background 0xC7FF -#define Hscolor 0xF01F - -#define RS HAL_GPIO_WritePin(GPIOD, GPIO_PIN_6, GPIO_PIN_SET) /*RS = 1 ghi data*/ -#define RSN HAL_GPIO_WritePin(GPIOD, GPIO_PIN_6, GPIO_PIN_RESET) /*RS = 0 ghi lenh*/ - -#define WR HAL_GPIO_WritePin(GPIOD, GPIO_PIN_5, GPIO_PIN_SET) /*Ghi du lieu, suon len cua xung tren chan WR se ghi data len LCD*/ -#define WRN HAL_GPIO_WritePin(GPIOD, GPIO_PIN_5, GPIO_PIN_RESET) - -#define RD HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4, GPIO_PIN_SET) /*Doc du lieu, suon len cua xung tren chan RD doc trang thai LCD*/ -#define RDN HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4, GPIO_PIN_RESET) - - -#define CS HAL_GPIO_WritePin(GPIOB, GPIO_PIN_10, GPIO_PIN_SET) /*Chipselect - tich cuc muc thap*/ -#define CSN HAL_GPIO_WritePin(GPIOB, GPIO_PIN_10, GPIO_PIN_RESET) - -#define RST HAL_GPIO_WritePin(GPIOD, GPIO_PIN_3, GPIO_PIN_SET) /*Chan RESET LCD tich cuc muc thap*/ -#define RSTN HAL_GPIO_WritePin(GPIOD, GPIO_PIN_3, GPIO_PIN_RESET) - - - -/*For SSD1289*/ -void SSD1289_Init(); /*Khoi tao man hinh cam ung*/ -void SSD1289_Reset(); - -void swap(uint16_t *a, uint16_t *b); - -void SSD1289_Write_Com(uint16_t DH); /*Gui dia chi thanh ghi*/ -void SSD1289_Write_Data(uint16_t DH); /*Gan du lieu vao thanh ghi vua gui*/ -void SSD1289_Write_Com_Data(uint16_t com1,uint16_t dat1); /*Ghi du lieu vao thanh ghi co dia chi cho truoc*/ - -void SSD1289_Fill_Color(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color); /*To mau mot vung hinh chu nhat*/ -void SSD1289_Address_Set(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); -void SSD1289_Set_Cursor(uint16_t x_pos, uint16_t y_pos); - -void SSD1289_Write_Pixel(uint16_t x, uint16_t y, uint16_t color); /*Ghi mau vao pixel co toa do nhat dinh*/ -void SSD1289_Write_Pic(const uint16_t *pic); /*Hien thi anh*/ -//void SSD1289_Write_Pic_Coor(const uint16_t *pic, uint16_t x, uint16_t y, uint16_t length, uint16_t width); /*Hien thi anh theo toa do*/ -void SSD1289_Clear_Screen(); /*Xoa man hinh*/ -void SSD1289_Write_Back_Ground(uint16_t color); - -void SSD1289_Print_Char(uint16_t x_pos, uint16_t y_pos, uint16_t font_size, uint16_t color, uint16_t back_color, char ch); -void SSD1289_Print_String(uint16_t x_pos, uint16_t y_pos, uint16_t dis_char, uint16_t dis_line, uint16_t font_size, uint16_t color, uint16_t back_color, char* string); - -void SSD1289_Draw_H_Line(uint16_t x1, uint16_t x2, uint16_t y1, uint16_t color); -void SSD1289_Draw_V_Line(uint16_t x1, uint16_t y1, uint16_t y2, uint16_t color); -void SSD1289_Draw_Rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t fill, uint16_t color); - -void SSD1289_Write_Pic_Coor(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t *pic); -void SSD1289_Print(uint16_t x, uint16_t y, char *string); -#endif /* SSD1289_H_ */ diff --git a/Software/Flapy Bird/Core/Inc/stm32f4xx_hal_conf.h b/Software/Flapy Bird/Core/Inc/stm32f4xx_hal_conf.h deleted file mode 100644 index 1c99541..0000000 --- a/Software/Flapy Bird/Core/Inc/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32f4xx_hal_conf.h. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - - /* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -#define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_FMPSMBUS_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_FMPSMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_fmpsmbus.h" -#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/Software/Flapy Bird/Core/Inc/stm32f4xx_it.h b/Software/Flapy Bird/Core/Inc/stm32f4xx_it.h deleted file mode 100644 index 14e5c37..0000000 --- a/Software/Flapy Bird/Core/Inc/stm32f4xx_it.h +++ /dev/null @@ -1,66 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f4xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IT_H -#define __STM32F4xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IT_H */ diff --git a/Software/Flapy Bird/Core/Inc/xpt2046.h b/Software/Flapy Bird/Core/Inc/xpt2046.h deleted file mode 100644 index b43d241..0000000 --- a/Software/Flapy Bird/Core/Inc/xpt2046.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __XPT2046_H -#define __XPT2046_H - -#include "stm32f4xx_hal.h" -#include "stm32f4xx_hal_spi.h" - -/*Chieu dai truc x*/ -/*Chieu dai truc y*/ - -#define cmd_X 0x90 -#define cmd_Y 0xD0 - -#define T_WIDTH 3230 -#define X_T_MIN 470 - -#define T_HEIGH 3050 -#define Y_T_MIN 470 - -#define LCD_WID 319.0 -#define LCD_HEI 239.0 - -#define READX 1 -#define READY 0 - -#define T_CSN HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET) -#define T_CS HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET) - - -uint8_t Read_IRQ(); -uint16_t XPT2046_Read(uint8_t cmd); -uint16_t XPT2046_Calibrate(uint16_t coor, uint16_t r); - - -#endif diff --git a/Software/Flapy Bird/Core/Src/main.c b/Software/Flapy Bird/Core/Src/main.c deleted file mode 100644 index 9df0b38..0000000 --- a/Software/Flapy Bird/Core/Src/main.c +++ /dev/null @@ -1,542 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -#include "image.h" -#include "line.h" -#include "button.h" -#include "stm32f4xx_hal.h" -#include "xpt2046.h" -#include "ssd1289.h" -#include "stdlib.h" - -#define WIDTH_PILL 40 /*Chieu rong ong khoi*/ - -#define HIDDENT 50 /*Phan ong khoi bi an ben trai*/ - -#define HEIGH_SCREEN 215 /*Chieu cao man hinh hien thi chim*/ - -#define DISTANCE 60 /*Khoang cach giua hai ong khoi*/ - -#define YES 1 -#define NO 0 - -#define WIDTH_BIRD 26 /*Chieu rong cua hinh chim*/ -#define HEIGH_BIRD 19 /*Chieu cao cua hinh chim*/ - -#define WIDTH_LINE 320 -#define HEIGH_LINE 5 - -#define BIRD_X 110 /*toa do X cua chim*/ -#define BIRD_Y 100 - -#define X_COM 136 - -#define FALLING 0 /* Bay xuong */ -#define RISING 1 /* Bay len */ - -#define X_SCORE 75 -#define Y_SCORE 223 -#define X_H_SCORE 180 - -#define X_GAME_OVER 90 -#define Y_GAME_OVER 40 - -#define X_GAME_SCORE 95 -#define Y_GAME_SCORE 70 - -#define X_SOCRE_END 165 -#define SCORED 69 - -#define X_BUT 140 -#define Y_BUT 100 - -SPI_HandleTypeDef hspi3; - -uint16_t list_heigh[15]; -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -SPI_HandleTypeDef hspi3; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_SPI3_Init(void); -/* USER CODE BEGIN PFP */ -void Init_Game(); -void Draw_Pillar(int16_t x, uint16_t heigh); -void Init_Heigh_Pill(); -void Bird_Fly(uint16_t y); -void Convert_To_String(uint16_t val); -void Print_Score(uint16_t, uint16_t x_score, uint16_t color); -void Game_Over(); -int Button_Press(uint16_t x, uint16_t y, uint16_t width, uint16_t heigh); -void Welcome(); -void Click_Here(); -uint16_t score = 0; /*Diem so*/ -uint16_t high_score = 0; - - -int16_t x1 = 0, x2 = 0; /*Toa do x cua 2 ong khoi xuat hien tren man hinh*/ - -uint16_t heigh_pill1 = 0; /*Chieu cao ong khoi khi bat day game*/ -uint16_t heigh_pill2 = 0; - -int16_t y_bird = 0; - -uint16_t x_com = 0; -uint16_t h_com = 0; -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_SPI3_Init(); - /* USER CODE BEGIN 2 */ - SSD1289_Init(); - SSD1289_Clear_Screen(); - -// Init_Game(); /*Khoi tao game*/ - - Welcome(); - - int c = 0; - int score_old = 0; - int game_over=NO; - - while (1) - { - if(!Read_IRQ()){ - if((game_over==NO)||Button_Press(X_BUT, Y_BUT, BUT_WIDTH, BUT_HEIGH)){ - score_old = score; - c = 0; - Init_Game(); - - if(score_old > high_score){ - high_score = score_old; - Print_Score(high_score, 300, Hscolor); - } - while(1){ - if(x1 == 70){ /*Neu ong khoi 1 di qua toa to 110 thi tao ong khoi 2*/ - x2 = 320; - heigh_pill2 = list_heigh[rand()%15]; - } - if(x2 == 70){ /*Neu ong khoi di qua toa do 110 thi tao them ong khoi*/ - x1 = 320; - heigh_pill1 = list_heigh[rand()%15]; - } - - /*Ve ong khoi*/ - Draw_Pillar(x1, heigh_pill1); - Draw_Pillar(x2, heigh_pill2); - - - if(!Read_IRQ()){ /*Neu co tin hieu cam ung*/ - y_bird -= 5; - c = 1; - } - else if(c){ // Neu chua cham lan nao thi chim van dung yen - y_bird += 2; - } - - if(x1 > 70){ - x_com = x1; - h_com = heigh_pill1-1; - } - else{ - x_com = x2; - h_com = heigh_pill2-1; - } - if(((x_com==X_COM)&&((y_bird<=h_com)||(y_bird+HEIGH_BIRD>=(h_com+DISTANCE))))|| - ((y_bird<=h_com+1)&&( ((X_COM>=x_com)&& - (X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&&(BIRD_X<=(x_com+WIDTH_PILL)))))|| - (((y_bird+HEIGH_BIRD)>=(h_com+DISTANCE))&& - (((X_COM>=x_com)&&(X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&& - (BIRD_X<=(x_com+WIDTH_PILL)))))|| - ((y_bird+HEIGH_BIRD)>=HEIGH_SCREEN)){ - - game_over = YES; - Game_Over(); - break; - } - - if(x1 == SCORED || x2 == SCORED){ - score += 1; - Print_Score(score, X_SCORE, Blue); - } - - if(c){ - Bird_Fly(y_bird); - x1--; - x2--; - } - HAL_Delay(10); - } - } - } - } - -} - -void Init_Heigh_Pill(){ - int i =0; - int value = 0; - for(i=0; i<15; i++){ - list_heigh[i] = 150-value; - value += 10; - } - -} - -void Welcome(){ - SSD1289_Write_Back_Ground(Black); - SSD1289_Print_String(50, 40, 2, 1, 4, White, Black, "Flapy Bird"); - SSD1289_Print_String(40, 185, 1, 1, 2, White, Black, "Click to enter the game!"); -} -void Draw_Pillar(int16_t x, uint16_t heigh){ - if(x < 321){ - /*Xoa ong khoi cu*/ - int16_t x1 = x+WIDTH_PILL+1; - - SSD1289_Draw_V_Line(x1, 1, heigh, Background); /*Xoa ong khoi top*/ - SSD1289_Draw_V_Line(x1, 1+heigh+DISTANCE, HEIGH_SCREEN, Background); /*Xoa ong khoi bot*/ - - /*Ve ong khoi moi*/ - SSD1289_Draw_V_Line(x, 1, heigh, Green); - SSD1289_Draw_V_Line(x, 1+heigh+DISTANCE, HEIGH_SCREEN, Green); - } -} - - -void Bird_Fly(uint16_t y){ - SSD1289_Fill_Color(BIRD_X, y-3, (BIRD_X+WIDTH_BIRD+5), (y+HEIGH_BIRD+5), Background); - HAL_Delay(5); - SSD1289_Write_Pic_Coor(BIRD_X, y, WIDTH_BIRD, HEIGH_BIRD, bird_image); -} - -void Print_Score(uint16_t val, uint16_t x_score, uint16_t color){ - uint16_t a = 0, b = 0; - char string[3] = {0, 0, '\0'}; - /*Xoa diem cu*/ - SSD1289_Fill_Color(x_score, Y_SCORE, x_score+20, 239, Yellow); - if(val < 10){ - SSD1289_Print_Char(x_score, Y_SCORE, 2, color, Yellow, (val+48)); - } - else{ - a = val%10 + 48; /*Hang don vi*/ - b = val/10 + 48; /*Hang chuc*/ - string[0] = b; - string[1] = a; - SSD1289_Print_String(x_score, Y_SCORE, 1, 1, 2, color, Yellow, string); - } - -} - -void Game_Over(){ - - SSD1289_Fill_Color(X_GAME_OVER-40, Y_GAME_OVER-10, X_GAME_OVER+120, Y_GAME_OVER+70, Background); - SSD1289_Print_String(X_GAME_OVER, Y_GAME_OVER, 2, 2, 3, Red, Background, "Game Over"); - SSD1289_Print_String(X_GAME_SCORE, Y_GAME_SCORE, 2, 2, 2, Red, Background, "Score: "); - uint16_t a = 0, b = 0; - char string[3] = {0, 0, '\0'}; - if(score < 10){ - SSD1289_Print_Char(X_SOCRE_END, Y_GAME_SCORE, 2, Red, Background, (score+48)); - } - else{ - a = score%10 + 48; /*Hang don vi*/ - b = score/10 + 48; /*Hang chuc*/ - string[0] = b; - string[1] = a; - SSD1289_Print_String(X_SOCRE_END, Y_GAME_SCORE, 2, 2, 2, Red, Background, string); - } - - HAL_Delay(1500); - SSD1289_Write_Pic_Coor(X_BUT, Y_BUT, BUT_WIDTH, BUT_HEIGH, button); -} - -int Button_Press(uint16_t x, uint16_t y, uint16_t width, uint16_t heigh){ - uint16_t lcd_x = 0, lcd_y = 0; - if(!Read_IRQ()){ - lcd_x = XPT2046_Calibrate(XPT2046_Read(cmd_X), 1); - lcd_y = XPT2046_Calibrate(XPT2046_Read(cmd_Y), 0); - - if(((lcd_x>x)&&(lcd_x<(x+width)))&&((lcd_y>y)&&(lcd_y<(y+heigh)))) - return YES; - else - return NO; - } - return NO; -} - -void Init_Game(){ - Init_Heigh_Pill(); - score = 0; - x1 = 320; - x2 = 600; /*Toa do x cua 2 ong khoi xuat hien tren man hinh*/ - heigh_pill1 = list_heigh[rand()%15]; /*Chieu cao ong khoi khi bat day game*/ - heigh_pill2 = 100; - y_bird = BIRD_Y; - x_com = 320; - h_com = heigh_pill1; - SSD1289_Write_Back_Ground(Background); - SSD1289_Write_Pic_Coor(BIRD_X, BIRD_Y, WIDTH_BIRD, HEIGH_BIRD, bird_image); - SSD1289_Write_Pic_Coor(0, HEIGH_SCREEN, WIDTH_LINE, HEIGH_LINE, line); - SSD1289_Fill_Color(0, HEIGH_SCREEN+5, 319, 239, Yellow); - SSD1289_Print_String(10, HEIGH_SCREEN+8, 1, 1, 2, Blue, Yellow, "Score: "); - Print_Score(score, X_SCORE, Blue); - SSD1289_Print_String(X_H_SCORE, HEIGH_SCREEN+8, 1, 1, 2, Hscolor, Yellow, "High Score: "); - Print_Score(high_score, 300, Hscolor); -} - - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 8; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief SPI3 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI3_Init(void) -{ - - /* USER CODE BEGIN SPI3_Init 0 */ - - /* USER CODE END SPI3_Init 0 */ - - /* USER CODE BEGIN SPI3_Init 1 */ - - /* USER CODE END SPI3_Init 1 */ - /* SPI3 parameter configuration*/ - hspi3.Instance = SPI3; - hspi3.Init.Mode = SPI_MODE_MASTER; - hspi3.Init.Direction = SPI_DIRECTION_2LINES; - hspi3.Init.DataSize = SPI_DATASIZE_8BIT; - hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi3.Init.NSS = SPI_NSS_SOFT; - hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; - hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi3.Init.TIMode = SPI_TIMODE_DISABLE; - hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - hspi3.Init.CRCPolynomial = 10; - if (HAL_SPI_Init(&hspi3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI3_Init 2 */ - - /* USER CODE END SPI3_Init 2 */ - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOE, D2_Pin|D3_Pin|D4_Pin|D5_Pin - |D6_Pin|D7_Pin|D8_Pin|D9_Pin - |D10_Pin|D11_Pin|D12_Pin|D13_Pin - |D14_Pin|D15_Pin|D0_Pin|D1_Pin, GPIO_PIN_SET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(CS_GPIO_Port, CS_Pin, GPIO_PIN_SET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOD, RESET_Pin|RD_Pin|WR_Pin|RS_Pin - |T_CS_Pin, GPIO_PIN_SET); - - /*Configure GPIO pins : D2_Pin D3_Pin D4_Pin D5_Pin - D6_Pin D7_Pin D8_Pin D9_Pin - D10_Pin D11_Pin D12_Pin D13_Pin - D14_Pin D15_Pin D0_Pin D1_Pin */ - GPIO_InitStruct.Pin = D2_Pin|D3_Pin|D4_Pin|D5_Pin - |D6_Pin|D7_Pin|D8_Pin|D9_Pin - |D10_Pin|D11_Pin|D12_Pin|D13_Pin - |D14_Pin|D15_Pin|D0_Pin|D1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - /*Configure GPIO pin : CS_Pin */ - GPIO_InitStruct.Pin = CS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - HAL_GPIO_Init(CS_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : T_IRQ_Pin */ - GPIO_InitStruct.Pin = T_IRQ_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(T_IRQ_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : RESET_Pin RD_Pin WR_Pin RS_Pin - T_CS_Pin */ - GPIO_InitStruct.Pin = RESET_Pin|RD_Pin|WR_Pin|RS_Pin - |T_CS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ diff --git a/Software/Flapy Bird/Core/Src/ssd1289.c b/Software/Flapy Bird/Core/Src/ssd1289.c deleted file mode 100644 index 1588572..0000000 --- a/Software/Flapy Bird/Core/Src/ssd1289.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * ssd1289.c - * - * Created on: Jan 5, 2019 - * Author: Cuong - */ - -#include "ssd1289.h" -#include "font.h" - - -void swap(uint16_t *a, uint16_t *b) -{ - uint16_t temp = 0x0000; - - temp = *b; - *b = *a; - *a = temp; -} - -/*Ghui dia chi thanh ghi*/ -void SSD1289_Write_Com(uint16_t DH) -{ - RSN; - CSN; - GPIOE -> ODR = DH; - WRN; - WR; - CS; -} - -/*Gui du lieu ghi vao thanh ghi*/ -void SSD1289_Write_Data(uint16_t DH) -{ - RS; - CSN; - GPIOE -> ODR = DH; - WRN; - WR; - CS; -} - -/*Gui dong thoi dia chi thanh ghi va du lieu thanh ghi*/ -void SSD1289_Write_Com_Data(uint16_t com1,uint16_t dat1) -{ - SSD1289_Write_Com(com1); - SSD1289_Write_Data(dat1); -} - -/*Reset man hinh*/ -void SSD1289_Reset(){ - RSTN; - HAL_Delay(10); - RST; -} - -/*Set dia chi cua so*/ -void SSD1289_Address_Set(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) /*Thiet lap vung lam viec cua man hinh*/ -{ - /*Doi toa do ve toa do mong muon*/ - swap(&x1, &y1); - swap(&x2, &y2); - - SSD1289_Write_Com_Data(0x0044,(x2<<8)+x1); - SSD1289_Write_Com_Data(0x0045, y1); - SSD1289_Write_Com_Data(0x0046, y2); - SSD1289_Write_Com_Data(0x004E, x1); - SSD1289_Write_Com_Data(0x004F, y1); - SSD1289_Write_Com(0x0022); -} - -/*Ghi pixel*/ -void SSD1289_Write_Pixel(uint16_t x, uint16_t y, uint16_t color) -{ - CSN; - - swap(&x, &y); - SSD1289_Write_Com_Data(0x004E, x); - SSD1289_Write_Com_Data(0x004F, y); - SSD1289_Write_Com_Data(0x0022, color); - - CS; -} - -/*Ve duong thang*/ -void SSD1289_Draw_Line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color) -{ - uint16_t dx = 0x0000; - uint16_t dy = 0x0000; - uint16_t stepx = 0x0000; - uint16_t stepy = 0x0000; - uint16_t fraction = 0x0000; - - dy = (y2 - y1); - dx = (x2 - x1); - - if(dy < 0) - { - dy = -dy; - stepy = -1; - } - else - { - stepy = 1; - } - - if(dx < 0) - { - dx = -dx; - stepx = -1; - } - else - { - stepx = 1; - } - - dx <<= 0x01; - dy <<= 0x01; - - SSD1289_Write_Pixel(x1, y1, color); - - if(dx > dy) - { - fraction = (dy - (dx >> 1)); - while(x1 != x2) - { - if(fraction >= 0) - { - y1 += stepy; - fraction -= dx; - } - x1 += stepx; - fraction += dy; - - SSD1289_Write_Pixel(x1, y1, color); - } - } - else - { - fraction = (dx - (dy >> 1)); - - while(y1 != y2) - { - if (fraction >= 0) - { - x1 += stepx; - fraction -= dy; - } - y1 += stepy; - fraction += dx; - SSD1289_Write_Pixel(x1, y1, color); - } - } -} - -/*Set vi tri con tro*/ -void SSD1289_Set_Cursor(uint16_t x_pos, uint16_t y_pos) /*Thiet lap vi tri con tro ban dau khi ve*/ -{ - swap(&x_pos, &y_pos); - - SSD1289_Write_Com_Data(0x004E, x_pos); - SSD1289_Write_Com_Data(0x004F, y_pos); - SSD1289_Write_Com(0x0022); -} - -/*Ve mau*/ -void SSD1289_Fill_Color(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color){ /*To mau trong khoang da duoc quy dinh*/ - uint16_t max_index = (x2 - x1 + 1)*(y2 - y1 + 1); - SSD1289_Address_Set(x1, y1, x2, y2); - - while(max_index){ - SSD1289_Write_Data(color); - max_index--; - } -} - - -void SSD1289_Write_Pic_Coor(uint16_t x, uint16_t y, uint16_t length, uint16_t width, uint16_t *pic){ - uint16_t index_x = 0, index_y = 0, i = 0; - for(index_y = 0; index_y < width; index_y++){ - for(index_x = 0; index_x < length; index_x++){ - SSD1289_Write_Pixel(x + index_x, y + index_y, pic[i]); - i++; - } - } -} -void SSD1289_Print_Char(uint16_t x_pos, uint16_t y_pos, uint16_t font_size, uint16_t color, uint16_t back_color, char ch){ - int i = 0; - int j = 0; - uint16_t y = y_pos; - uint16_t column = 0; - if(font_size == 0) - font_size = 1; - uint16_t *value = font[(uint16_t)ch-32]; - for(i = 0; i < 5; i++){ - column = value[i]; - y_pos = y; - for(j = 0; j < 7; j++){ - if((column >> j) & 0x0001) - SSD1289_Fill_Color(x_pos, y_pos, (x_pos + font_size - 1), (y_pos +font_size - 1), color); - else{ - SSD1289_Fill_Color(x_pos, y_pos, (x_pos + font_size - 1), (y_pos +font_size - 1), back_color); - } - y_pos += font_size; - } - x_pos+= font_size; - } -} - -void SSD1289_Print_String(uint16_t x_pos, uint16_t y_pos, uint16_t dis_char, uint16_t dis_line, uint16_t font_size, uint16_t color, uint16_t back_color, char *str){ - uint16_t x = x_pos; - if(str == NULL) - return; - do{ - if(*str == '\n'){ - str++; - y_pos = y_pos + font_size * 7 + dis_line; - x_pos = x; - } - SSD1289_Print_Char(x_pos, y_pos, font_size, color, back_color, *str++); - x_pos += (font_size *5 + dis_char); - } - while(*str != '\0'); -} -void SSD1289_Print(uint16_t x, uint16_t y, char *string){ - SSD1289_Write_Back_Ground(Black); - SSD1289_Print_String(x, y, 1, 1, 1, White, Black, string); -} -void SSD1289_Draw_V_Line(uint16_t x1, uint16_t y1, uint16_t y2, uint16_t color) -{ - - if(y1 > y2) - { - swap(&y1, &y2); - } - - while(y2 > (y1-1)) - { - SSD1289_Write_Pixel(x1, y2, color); - y2--; - } -} - - -void SSD1289_Draw_H_Line(uint16_t x1, uint16_t x2, uint16_t y1, uint16_t color) -{ - - if(x1 > x2) - { - swap(&x1, &x2); - } - - while(x2 > (x1 - 1)) - { - SSD1289_Write_Pixel(x2, y1, color); - x2--; - } -} -void SSD1289_Draw_Rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t fill, uint16_t color) -{ - uint16_t i = 0x0000; - uint16_t xmin = 0x0000; - uint16_t xmax = 0x0000; - uint16_t ymin = 0x0000; - uint16_t ymax = 0x0000; - - switch(fill) - { - case YES: - { - if(x1 < x2) - { - xmin = x1; - xmax = x2; - } - else - { - xmin = x2; - xmax = x1; - } - - if(y1 < y2) - { - ymin = y1; - ymax = y2; - } - else - { - ymin = y2; - ymax = y1; - } - - for(; xmin <= xmax; ++xmin) - { - for(i = ymin; i <= ymax; ++i) - { - SSD1289_Write_Pixel(xmin, i, color); - } - } - - break; - } - default: - { - SSD1289_Draw_V_Line(x1, y1, y2, color); - SSD1289_Draw_V_Line(x2, y1, y2, color); - SSD1289_Draw_H_Line(x1, x2, y1, color); - SSD1289_Draw_H_Line(x1, x2, y2, color); - break; - } - } -} - -void SSD1289_Write_Pic(const uint16_t *pic) -{ - uint16_t i_x = 0; - uint16_t i_y = 0; - uint32_t i = 0; - - for(i_y = 0; i_y < 240; i_y++) - { - for(i_x = 0; i_x < 320; i_x++) - { - SSD1289_Write_Pixel(i_x, i_y, pic[i]); - i++; - } - } -} - -void SSD1289_Write_Back_Ground(uint16_t color) -{ - uint16_t x = 0, y = 0; - for(y = 0; y < 240; y++){ - for(x = 0; x < 320; x++){ - SSD1289_Write_Pixel(x, y, color); - } - } -} -void SSD1289_Clear_Screen(){ - SSD1289_Write_Back_Ground(White); -} -void SSD1289_Init(void) -{ - - RST; - HAL_Delay(100); - RSTN;; - HAL_Delay(100); - RST; - CS; - RD; - WR; - HAL_Delay(100); - - SSD1289_Write_Com_Data(0x0000,0x0001); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0003,0xA8A4); HAL_Delay(1); - SSD1289_Write_Com_Data(0x000C,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x000D,0x080C); HAL_Delay(1); - SSD1289_Write_Com_Data(0x000E,0x2B00); HAL_Delay(1); - SSD1289_Write_Com_Data(0x001E,0x00B0); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0001,0x293F); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0002,0x0600); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0010,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0011,0x6070); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0005,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0006,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0016,0xEF1C); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0017,0x0003); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0007,0x0233); HAL_Delay(1); - SSD1289_Write_Com_Data(0x000B,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x000F,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0041,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0042,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0048,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0049,0x013F); HAL_Delay(1); - SSD1289_Write_Com_Data(0x004A,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x004B,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0044,0xEF00); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0045,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0046,0x013F); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0030,0x0707); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0031,0x0204); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0032,0x0204); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0033,0x0502); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0034,0x0507); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0035,0x0204); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0036,0x0204); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0037,0x0502); HAL_Delay(1); - SSD1289_Write_Com_Data(0x003A,0x0302); HAL_Delay(1); - SSD1289_Write_Com_Data(0x003B,0x0302); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0023,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0024,0x0000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x0025,0x8000); HAL_Delay(1); - SSD1289_Write_Com_Data(0x004f,0); - SSD1289_Write_Com_Data(0x004e,0); - SSD1289_Write_Com(0x0022); -} - - - - diff --git a/Software/Flapy Bird/Core/Src/stm32f4xx_hal_msp.c b/Software/Flapy Bird/Core/Src/stm32f4xx_hal_msp.c deleted file mode 100644 index 37e9e66..0000000 --- a/Software/Flapy Bird/Core/Src/stm32f4xx_hal_msp.c +++ /dev/null @@ -1,150 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f4xx_hal_msp.c - * @brief This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); - - /* System interrupt init*/ - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/** -* @brief SPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hspi->Instance==SPI3) - { - /* USER CODE BEGIN SPI3_MspInit 0 */ - - /* USER CODE END SPI3_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_SPI3_CLK_ENABLE(); - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI3 GPIO Configuration - PB3 ------> SPI3_SCK - PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI - */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN SPI3_MspInit 1 */ - - /* USER CODE END SPI3_MspInit 1 */ - } - -} - -/** -* @brief SPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) -{ - if(hspi->Instance==SPI3) - { - /* USER CODE BEGIN SPI3_MspDeInit 0 */ - - /* USER CODE END SPI3_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_SPI3_CLK_DISABLE(); - - /**SPI3 GPIO Configuration - PB3 ------> SPI3_SCK - PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); - - /* USER CODE BEGIN SPI3_MspDeInit 1 */ - - /* USER CODE END SPI3_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ diff --git a/Software/Flapy Bird/Core/Src/stm32f4xx_it.c b/Software/Flapy Bird/Core/Src/stm32f4xx_it.c deleted file mode 100644 index 5d15005..0000000 --- a/Software/Flapy Bird/Core/Src/stm32f4xx_it.c +++ /dev/null @@ -1,203 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f4xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32f4xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - { - } - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Pre-fetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVCall_IRQn 0 */ - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F4xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f4xx.s). */ -/******************************************************************************/ - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ diff --git a/Software/Flapy Bird/Core/Src/syscalls.c b/Software/Flapy Bird/Core/Src/syscalls.c deleted file mode 100644 index fadb992..0000000 --- a/Software/Flapy Bird/Core/Src/syscalls.c +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @file syscalls.c - * @author Auto-generated by STM32CubeIDE - * @brief STM32CubeIDE Minimal System calls file - * - * For more information about which c-functions - * need which of these lowlevel functions - * please consult the Newlib libc-manual - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes */ -#include -#include -#include -#include -#include -#include -#include -#include - - -/* Variables */ -extern int __io_putchar(int ch) __attribute__((weak)); -extern int __io_getchar(void) __attribute__((weak)); - - -char *__env[1] = { 0 }; -char **environ = __env; - - -/* Functions */ -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - return 1; -} - -int _kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -void _exit (int status) -{ - _kill(status, -1); - while (1) {} /* Make sure we hang here */ -} - -__attribute__((weak)) int _read(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } - -return len; -} - -__attribute__((weak)) int _write(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar(*ptr++); - } - return len; -} - -int _close(int file) -{ - return -1; -} - - -int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _isatty(int file) -{ - return 1; -} - -int _lseek(int file, int ptr, int dir) -{ - return 0; -} - -int _open(char *path, int flags, ...) -{ - /* Pretend like we always fail */ - return -1; -} - -int _wait(int *status) -{ - errno = ECHILD; - return -1; -} - -int _unlink(char *name) -{ - errno = ENOENT; - return -1; -} - -int _times(struct tms *buf) -{ - return -1; -} - -int _stat(char *file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _link(char *old, char *new) -{ - errno = EMLINK; - return -1; -} - -int _fork(void) -{ - errno = EAGAIN; - return -1; -} - -int _execve(char *name, char **argv, char **env) -{ - errno = ENOMEM; - return -1; -} diff --git a/Software/Flapy Bird/Core/Src/sysmem.c b/Software/Flapy Bird/Core/Src/sysmem.c deleted file mode 100644 index 54081ac..0000000 --- a/Software/Flapy Bird/Core/Src/sysmem.c +++ /dev/null @@ -1,79 +0,0 @@ -/** - ****************************************************************************** - * @file sysmem.c - * @author Generated by STM32CubeIDE - * @brief STM32CubeIDE System Memory calls file - * - * For more information about which C functions - * need which of these lowlevel functions - * please consult the newlib libc manual - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes */ -#include -#include - -/** - * Pointer to the current high watermark of the heap usage - */ -static uint8_t *__sbrk_heap_end = NULL; - -/** - * @brief _sbrk() allocates memory to the newlib heap and is used by malloc - * and others from the C library - * - * @verbatim - * ############################################################################ - * # .data # .bss # newlib heap # MSP stack # - * # # # # Reserved by _Min_Stack_Size # - * ############################################################################ - * ^-- RAM start ^-- _end _estack, RAM end --^ - * @endverbatim - * - * This implementation starts allocating at the '_end' linker symbol - * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack - * The implementation considers '_estack' linker symbol to be RAM end - * NOTE: If the MSP stack, at any point during execution, grows larger than the - * reserved size, please increase the '_Min_Stack_Size'. - * - * @param incr Memory size - * @return Pointer to allocated memory - */ -void *_sbrk(ptrdiff_t incr) -{ - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - const uint8_t *max_heap = (uint8_t *)stack_limit; - uint8_t *prev_heap_end; - - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - { - __sbrk_heap_end = &_end; - } - - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - { - errno = ENOMEM; - return (void *)-1; - } - - prev_heap_end = __sbrk_heap_end; - __sbrk_heap_end += incr; - - return (void *)prev_heap_end; -} diff --git a/Software/Flapy Bird/Core/Src/system_stm32f4xx.c b/Software/Flapy Bird/Core/Src/system_stm32f4xx.c deleted file mode 100644 index 3bd40f7..0000000 --- a/Software/Flapy Bird/Core/Src/system_stm32f4xx.c +++ /dev/null @@ -1,747 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - - -#include "stm32f4xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) -/* #define DATA_IN_ExtSRAM */ -#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ - STM32F412Zx || STM32F412Vx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx */ - -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -uint32_t SystemCoreClock = 16000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value - * depends on the application requirements), user has to ensure that HSE_VALUE - * is same as the real frequency of the crystal used. Otherwise, this function - * may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; - - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ - RCC->AHB1ENR |= 0x000001F8; - - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; - -/*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ - FMC_Bank5_6->SDCMR = 0x00000073; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ - FMC_Bank5_6->SDCMR = 0x00046014; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ - - (void)(tmp); -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - -#if defined(STM32F446xx) - /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface - clock */ - RCC->AHB1ENR |= 0x0000007D; -#else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - -#if defined(STM32F446xx) - /* Connect PAx pins to FMC Alternate function */ - GPIOA->AFR[0] |= 0xC0000000; - GPIOA->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOA->MODER |= 0x00008000; - /* Configure PDx pins speed to 50 MHz */ - GPIOA->OSPEEDR |= 0x00008000; - /* Configure PDx pins Output type to push-pull */ - GPIOA->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOA->PUPDR |= 0x00000000; - - /* Connect PCx pins to FMC Alternate function */ - GPIOC->AFR[0] |= 0x00CC0000; - GPIOC->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOC->MODER |= 0x00000A00; - /* Configure PDx pins speed to 50 MHz */ - GPIOC->OSPEEDR |= 0x00000A00; - /* Configure PDx pins Output type to push-pull */ - GPIOC->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOC->PUPDR |= 0x00000000; -#endif /* STM32F446xx */ - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -/*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - /* Configure and enable SDRAM bank1 */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCR[0] = 0x00001954; -#else - FMC_Bank5_6->SDCR[0] = 0x000019E4; -#endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x000000F3; -#else - FMC_Bank5_6->SDCMR = 0x00000073; -#endif /* STM32F446xx */ - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x00044014; -#else - FMC_Bank5_6->SDCMR = 0x00046014; -#endif /* STM32F446xx */ - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; -#if defined(STM32F446xx) - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); -#endif /* STM32F446xx */ - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); -#endif /* DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) - -#if defined(DATA_IN_ExtSRAM) -/*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FMC/FSMC Configuration --------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ - || defined(STM32F412Zx) || defined(STM32F412Vx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ - -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); -} -#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/Software/Flapy Bird/Core/Src/xpt2046.c b/Software/Flapy Bird/Core/Src/xpt2046.c deleted file mode 100644 index cd10d20..0000000 --- a/Software/Flapy Bird/Core/Src/xpt2046.c +++ /dev/null @@ -1,45 +0,0 @@ -#include "xpt2046.h" - - -extern SPI_HandleTypeDef hspi3; -volatile uint8_t receive_data = 0; -volatile uint8_t send_cmd; - -uint8_t Read_IRQ(){ - return HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_1); -} - -uint16_t XPT2046_Read(uint8_t cmd){ - uint16_t coor; - - T_CSN; - send_cmd = cmd; - HAL_SPI_Transmit(&hspi3, (uint8_t*) &send_cmd, 1, 1000); - send_cmd = 0x00; - HAL_SPI_TransmitReceive(&hspi3, (uint8_t*) &send_cmd, (uint8_t*) &receive_data, 1, 1000); - coor = (uint16_t) receive_data; - coor = coor << 8; - send_cmd = 0x00; - HAL_SPI_TransmitReceive(&hspi3, (uint8_t*) &send_cmd, (uint8_t*) &receive_data, 1, 1000); - coor = coor | (uint16_t) receive_data; - coor = coor >> 3; - T_CS; - - return coor; -} - -/*sel = 0: Tinh toa do x - sel != 0: Tinh toa do y - coor: toa do nhan duoc*/ -uint16_t XPT2046_Calibrate(uint16_t coor, uint16_t r){ - uint16_t temp = 0; - - if(r == 1){ - temp = (uint16_t) (LCD_WID * ((float)(coor - X_T_MIN)/T_WIDTH)); - } - else{ - temp = (uint16_t) (LCD_HEI * ((float)(coor - Y_T_MIN)/T_HEIGH)); - } - - return temp; -} diff --git a/Software/Flapy Bird/Core/Startup/startup_stm32f407vgtx.s b/Software/Flapy Bird/Core/Startup/startup_stm32f407vgtx.s deleted file mode 100644 index 3b99b6b..0000000 --- a/Software/Flapy Bird/Core/Startup/startup_stm32f407vgtx.s +++ /dev/null @@ -1,505 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f407xx.s - * @author MCD Application Team - * @brief STM32F407xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler diff --git a/Software/Flapy Bird/Debug/Core/Src/main.d b/Software/Flapy Bird/Debug/Core/Src/main.d deleted file mode 100644 index 77e5503..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/main.d +++ /dev/null @@ -1,61 +0,0 @@ -Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h \ - ../Core/Inc/image.h ../Core/Inc/line.h ../Core/Inc/button.h \ - ../Core/Inc/xpt2046.h ../Core/Inc/ssd1289.h -../Core/Inc/main.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: -../Core/Inc/image.h: -../Core/Inc/line.h: -../Core/Inc/button.h: -../Core/Inc/xpt2046.h: -../Core/Inc/ssd1289.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/main.o b/Software/Flapy Bird/Debug/Core/Src/main.o deleted file mode 100644 index 271e4c4..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/main.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/main.su b/Software/Flapy Bird/Debug/Core/Src/main.su deleted file mode 100644 index 2d32529..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/main.su +++ /dev/null @@ -1,13 +0,0 @@ -../Core/Src/main.c:138:5:main 24 static -../Core/Src/main.c:249:6:Init_Heigh_Pill 16 static -../Core/Src/main.c:259:6:Welcome 24 static -../Core/Src/main.c:264:6:Draw_Pillar 24 static -../Core/Src/main.c:279:6:Bird_Fly 24 static -../Core/Src/main.c:285:6:Print_Score 40 static -../Core/Src/main.c:303:6:Game_Over 32 static -../Core/Src/main.c:325:5:Button_Press 32 static -../Core/Src/main.c:339:6:Init_Game 24 static -../Core/Src/main.c:364:6:SystemClock_Config 88 static -../Core/Src/main.c:410:13:MX_SPI3_Init 8 static -../Core/Src/main.c:448:13:MX_GPIO_Init 48 static -../Core/Src/main.c:516:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Software/Flapy Bird/Debug/Core/Src/ssd1289.d b/Software/Flapy Bird/Debug/Core/Src/ssd1289.d deleted file mode 100644 index e53d9fe..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/ssd1289.d +++ /dev/null @@ -1,56 +0,0 @@ -Core/Src/ssd1289.o: ../Core/Src/ssd1289.c ../Core/Inc/ssd1289.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h \ - ../Core/Inc/font.h -../Core/Inc/ssd1289.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: -../Core/Inc/font.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/ssd1289.o b/Software/Flapy Bird/Debug/Core/Src/ssd1289.o deleted file mode 100644 index 9e77c3e..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/ssd1289.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/ssd1289.su b/Software/Flapy Bird/Debug/Core/Src/ssd1289.su deleted file mode 100644 index 9f181b1..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/ssd1289.su +++ /dev/null @@ -1,21 +0,0 @@ -../Core/Src/ssd1289.c:12:6:swap 24 static -../Core/Src/ssd1289.c:22:6:SSD1289_Write_Com 16 static -../Core/Src/ssd1289.c:33:6:SSD1289_Write_Data 16 static -../Core/Src/ssd1289.c:44:6:SSD1289_Write_Com_Data 16 static -../Core/Src/ssd1289.c:51:6:SSD1289_Reset 8 static -../Core/Src/ssd1289.c:58:6:SSD1289_Address_Set 24 static -../Core/Src/ssd1289.c:73:6:SSD1289_Write_Pixel 16 static -../Core/Src/ssd1289.c:86:6:SSD1289_Draw_Line 40 static -../Core/Src/ssd1289.c:157:6:SSD1289_Set_Cursor 16 static -../Core/Src/ssd1289.c:167:6:SSD1289_Fill_Color 32 static -../Core/Src/ssd1289.c:178:6:SSD1289_Write_Pic_Coor 32 static -../Core/Src/ssd1289.c:187:6:SSD1289_Print_Char 48 static -../Core/Src/ssd1289.c:210:6:SSD1289_Print_String 40 static -../Core/Src/ssd1289.c:225:6:SSD1289_Print 32 static -../Core/Src/ssd1289.c:229:6:SSD1289_Draw_V_Line 24 static -../Core/Src/ssd1289.c:245:6:SSD1289_Draw_H_Line 24 static -../Core/Src/ssd1289.c:259:6:SSD1289_Draw_Rectangle 40 static -../Core/Src/ssd1289.c:314:6:SSD1289_Write_Pic 24 static -../Core/Src/ssd1289.c:330:6:SSD1289_Write_Back_Ground 24 static -../Core/Src/ssd1289.c:339:6:SSD1289_Clear_Screen 8 static -../Core/Src/ssd1289.c:342:6:SSD1289_Init 8 static diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.d b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.d deleted file mode 100644 index 0bed562..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.d +++ /dev/null @@ -1,54 +0,0 @@ -Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ - ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Core/Inc/main.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.o b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.o deleted file mode 100644 index c051edf..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.su b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.su deleted file mode 100644 index b51b230..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_hal_msp.su +++ /dev/null @@ -1,3 +0,0 @@ -../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit 16 static -../Core/Src/stm32f4xx_hal_msp.c:87:6:HAL_SPI_MspInit 48 static -../Core/Src/stm32f4xx_hal_msp.c:124:6:HAL_SPI_MspDeInit 16 static diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.d b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.d deleted file mode 100644 index 2f932df..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.d +++ /dev/null @@ -1,56 +0,0 @@ -Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h \ - ../Core/Inc/stm32f4xx_it.h -../Core/Inc/main.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: -../Core/Inc/stm32f4xx_it.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.o b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.o deleted file mode 100644 index 8392e08..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.su b/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.su deleted file mode 100644 index 088e092..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/stm32f4xx_it.su +++ /dev/null @@ -1,9 +0,0 @@ -../Core/Src/stm32f4xx_it.c:69:6:NMI_Handler 4 static -../Core/Src/stm32f4xx_it.c:84:6:HardFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:99:6:MemManage_Handler 4 static -../Core/Src/stm32f4xx_it.c:114:6:BusFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:129:6:UsageFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:144:6:SVC_Handler 4 static -../Core/Src/stm32f4xx_it.c:157:6:DebugMon_Handler 4 static -../Core/Src/stm32f4xx_it.c:170:6:PendSV_Handler 4 static -../Core/Src/stm32f4xx_it.c:183:6:SysTick_Handler 8 static diff --git a/Software/Flapy Bird/Debug/Core/Src/subdir.mk b/Software/Flapy Bird/Debug/Core/Src/subdir.mk deleted file mode 100644 index 7a85364..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/subdir.mk +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../Core/Src/main.c \ -../Core/Src/ssd1289.c \ -../Core/Src/stm32f4xx_hal_msp.c \ -../Core/Src/stm32f4xx_it.c \ -../Core/Src/syscalls.c \ -../Core/Src/sysmem.c \ -../Core/Src/system_stm32f4xx.c \ -../Core/Src/xpt2046.c - -OBJS += \ -./Core/Src/main.o \ -./Core/Src/ssd1289.o \ -./Core/Src/stm32f4xx_hal_msp.o \ -./Core/Src/stm32f4xx_it.o \ -./Core/Src/syscalls.o \ -./Core/Src/sysmem.o \ -./Core/Src/system_stm32f4xx.o \ -./Core/Src/xpt2046.o - -C_DEPS += \ -./Core/Src/main.d \ -./Core/Src/ssd1289.d \ -./Core/Src/stm32f4xx_hal_msp.d \ -./Core/Src/stm32f4xx_it.d \ -./Core/Src/syscalls.d \ -./Core/Src/sysmem.d \ -./Core/Src/system_stm32f4xx.d \ -./Core/Src/xpt2046.d - - -# Each subdirectory must supply rules for building sources it contributes -Core/Src/%.o Core/Src/%.su: ../Core/Src/%.c Core/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" - -clean: clean-Core-2f-Src - -clean-Core-2f-Src: - -$(RM) ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/ssd1289.d ./Core/Src/ssd1289.o ./Core/Src/ssd1289.su ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su ./Core/Src/xpt2046.d ./Core/Src/xpt2046.o ./Core/Src/xpt2046.su - -.PHONY: clean-Core-2f-Src - diff --git a/Software/Flapy Bird/Debug/Core/Src/syscalls.d b/Software/Flapy Bird/Debug/Core/Src/syscalls.d deleted file mode 100644 index 8667c70..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/syscalls.d +++ /dev/null @@ -1 +0,0 @@ -Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/Software/Flapy Bird/Debug/Core/Src/syscalls.o b/Software/Flapy Bird/Debug/Core/Src/syscalls.o deleted file mode 100644 index 02a8c4b..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/syscalls.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/syscalls.su b/Software/Flapy Bird/Debug/Core/Src/syscalls.su deleted file mode 100644 index a7d10e5..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/syscalls.su +++ /dev/null @@ -1,18 +0,0 @@ -../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static -../Core/Src/syscalls.c:48:5:_getpid 4 static -../Core/Src/syscalls.c:53:5:_kill 16 static -../Core/Src/syscalls.c:59:6:_exit 16 static -../Core/Src/syscalls.c:65:27:_read 32 static -../Core/Src/syscalls.c:77:27:_write 32 static -../Core/Src/syscalls.c:88:5:_close 16 static -../Core/Src/syscalls.c:94:5:_fstat 16 static -../Core/Src/syscalls.c:100:5:_isatty 16 static -../Core/Src/syscalls.c:105:5:_lseek 24 static -../Core/Src/syscalls.c:110:5:_open 12 static -../Core/Src/syscalls.c:116:5:_wait 16 static -../Core/Src/syscalls.c:122:5:_unlink 16 static -../Core/Src/syscalls.c:128:5:_times 16 static -../Core/Src/syscalls.c:133:5:_stat 16 static -../Core/Src/syscalls.c:139:5:_link 16 static -../Core/Src/syscalls.c:145:5:_fork 8 static -../Core/Src/syscalls.c:151:5:_execve 24 static diff --git a/Software/Flapy Bird/Debug/Core/Src/sysmem.d b/Software/Flapy Bird/Debug/Core/Src/sysmem.d deleted file mode 100644 index 74fecf9..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/sysmem.d +++ /dev/null @@ -1 +0,0 @@ -Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/Software/Flapy Bird/Debug/Core/Src/sysmem.o b/Software/Flapy Bird/Debug/Core/Src/sysmem.o deleted file mode 100644 index e950be7..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/sysmem.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/sysmem.su b/Software/Flapy Bird/Debug/Core/Src/sysmem.su deleted file mode 100644 index 12d5f17..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/sysmem.su +++ /dev/null @@ -1 +0,0 @@ -../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.d b/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.d deleted file mode 100644 index c064ee8..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.d +++ /dev/null @@ -1,53 +0,0 @@ -Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.o b/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.o deleted file mode 100644 index b586081..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.su b/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.su deleted file mode 100644 index 96f1cd4..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/system_stm32f4xx.su +++ /dev/null @@ -1,2 +0,0 @@ -../Core/Src/system_stm32f4xx.c:167:6:SystemInit 4 static -../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 32 static diff --git a/Software/Flapy Bird/Debug/Core/Src/xpt2046.d b/Software/Flapy Bird/Debug/Core/Src/xpt2046.d deleted file mode 100644 index 8ad55a1..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/xpt2046.d +++ /dev/null @@ -1,54 +0,0 @@ -Core/Src/xpt2046.o: ../Core/Src/xpt2046.c ../Core/Inc/xpt2046.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Core/Inc/xpt2046.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Core/Src/xpt2046.o b/Software/Flapy Bird/Debug/Core/Src/xpt2046.o deleted file mode 100644 index 9bcd422..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Src/xpt2046.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Src/xpt2046.su b/Software/Flapy Bird/Debug/Core/Src/xpt2046.su deleted file mode 100644 index e8326e4..0000000 --- a/Software/Flapy Bird/Debug/Core/Src/xpt2046.su +++ /dev/null @@ -1,3 +0,0 @@ -../Core/Src/xpt2046.c:8:9:Read_IRQ 8 static -../Core/Src/xpt2046.c:12:10:XPT2046_Read 32 static -../Core/Src/xpt2046.c:34:11:XPT2046_Calibrate 24 static diff --git a/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.d b/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.d deleted file mode 100644 index 87d7abd..0000000 --- a/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.d +++ /dev/null @@ -1,2 +0,0 @@ -Core/Startup/startup_stm32f407vgtx.o: \ - ../Core/Startup/startup_stm32f407vgtx.s diff --git a/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.o b/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.o deleted file mode 100644 index 0ab9eb6..0000000 Binary files a/Software/Flapy Bird/Debug/Core/Startup/startup_stm32f407vgtx.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Core/Startup/subdir.mk b/Software/Flapy Bird/Debug/Core/Startup/subdir.mk deleted file mode 100644 index 357853c..0000000 --- a/Software/Flapy Bird/Debug/Core/Startup/subdir.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -S_SRCS += \ -../Core/Startup/startup_stm32f407vgtx.s - -OBJS += \ -./Core/Startup/startup_stm32f407vgtx.o - -S_DEPS += \ -./Core/Startup/startup_stm32f407vgtx.d - - -# Each subdirectory must supply rules for building sources it contributes -Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk - arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" - -clean: clean-Core-2f-Startup - -clean-Core-2f-Startup: - -$(RM) ./Core/Startup/startup_stm32f407vgtx.d ./Core/Startup/startup_stm32f407vgtx.o - -.PHONY: clean-Core-2f-Startup - diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d deleted file mode 100644 index 8281670..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o deleted file mode 100644 index 56e7cbf..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su deleted file mode 100644 index 424e879..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su +++ /dev/null @@ -1,27 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:373:21:HAL_GetTickFreq 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:389:13:HAL_Delay 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:415:13:HAL_SuspendTick 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:431:13:HAL_ResumeTick 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:441:10:HAL_GetHalVersion 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:450:10:HAL_GetREVID 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:459:10:HAL_GetDEVID 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:468:6:HAL_DBGMCU_EnableDBGSleepMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:477:6:HAL_DBGMCU_DisableDBGSleepMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:486:6:HAL_DBGMCU_EnableDBGStopMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:495:6:HAL_DBGMCU_DisableDBGStopMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:504:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:513:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:524:6:HAL_EnableCompensationCell 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:535:6:HAL_DisableCompensationCell 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:544:10:HAL_GetUIDw0 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:553:10:HAL_GetUIDw1 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:562:10:HAL_GetUIDw2 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d deleted file mode 100644 index 89f1512..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o deleted file mode 100644 index ee662fd..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su deleted file mode 100644 index 6ed4c17..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su +++ /dev/null @@ -1,32 +0,0 @@ -../Drivers/CMSIS/Include/core_cm4.h:1657:22:__NVIC_SetPriorityGrouping 24 static -../Drivers/CMSIS/Include/core_cm4.h:1676:26:__NVIC_GetPriorityGrouping 4 static -../Drivers/CMSIS/Include/core_cm4.h:1688:22:__NVIC_EnableIRQ 16 static -../Drivers/CMSIS/Include/core_cm4.h:1724:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm -../Drivers/CMSIS/Include/core_cm4.h:1743:26:__NVIC_GetPendingIRQ 16 static -../Drivers/CMSIS/Include/core_cm4.h:1762:22:__NVIC_SetPendingIRQ 16 static -../Drivers/CMSIS/Include/core_cm4.h:1777:22:__NVIC_ClearPendingIRQ 16 static -../Drivers/CMSIS/Include/core_cm4.h:1794:26:__NVIC_GetActive 16 static -../Drivers/CMSIS/Include/core_cm4.h:1816:22:__NVIC_SetPriority 16 static -../Drivers/CMSIS/Include/core_cm4.h:1838:26:__NVIC_GetPriority 16 static -../Drivers/CMSIS/Include/core_cm4.h:1863:26:NVIC_EncodePriority 40 static -../Drivers/CMSIS/Include/core_cm4.h:1890:22:NVIC_DecodePriority 40 static -../Drivers/CMSIS/Include/core_cm4.h:1939:34:__NVIC_SystemReset 4 static,ignoring_inline_asm -../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 4 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 16 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:298:6:HAL_MPU_ConfigRegion 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:342:10:HAL_NVIC_GetPriorityGrouping 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:369:6:HAL_NVIC_GetPriority 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:384:6:HAL_NVIC_SetPendingIRQ 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:402:10:HAL_NVIC_GetPendingIRQ 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:418:6:HAL_NVIC_ClearPendingIRQ 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:435:10:HAL_NVIC_GetActive 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:452:6:HAL_SYSTICK_CLKSourceConfig 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:470:6:HAL_SYSTICK_IRQHandler 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:479:13:HAL_SYSTICK_Callback 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d deleted file mode 100644 index c0ca4f1..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o deleted file mode 100644 index a9141ba..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su deleted file mode 100644 index 6c24b90..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su +++ /dev/null @@ -1,15 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 48 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 24 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d deleted file mode 100644 index b7551ee..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o deleted file mode 100644 index 771996d..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su deleted file mode 100644 index 9b2268b..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su +++ /dev/null @@ -1,4 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 24 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d deleted file mode 100644 index 2e10de4..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o deleted file mode 100644 index e8d4464..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su deleted file mode 100644 index be56024..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su +++ /dev/null @@ -1,9 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:495:6:HAL_EXTI_ClearPending 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:516:6:HAL_EXTI_GenerateSWI 24 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d deleted file mode 100644 index a122fa2..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o deleted file mode 100644 index 73dcb55..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su deleted file mode 100644 index a5b3ff7..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su +++ /dev/null @@ -1,17 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:154:19:HAL_FLASH_Program 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:212:19:HAL_FLASH_Program_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:259:6:HAL_FLASH_IRQHandler 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:382:13:HAL_FLASH_EndOfOperationCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:399:13:HAL_FLASH_OperationErrorCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:431:19:HAL_FLASH_Unlock 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:455:19:HAL_FLASH_Lock 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:467:19:HAL_FLASH_OB_Unlock 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:487:19:HAL_FLASH_OB_Lock 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:499:19:HAL_FLASH_OB_Launch 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:536:10:HAL_FLASH_GetError 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:550:19:FLASH_WaitForLastOperation 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:610:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:644:13:FLASH_Program_Word 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:669:13:FLASH_Program_HalfWord 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:694:13:FLASH_Program_Byte 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:711:13:FLASH_SetErrorCode 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d deleted file mode 100644 index 359ec5c..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o deleted file mode 100644 index 8d53f71..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su deleted file mode 100644 index e114bef..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su +++ /dev/null @@ -1,16 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:284:19:HAL_FLASHEx_OBProgram 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:343:6:HAL_FLASHEx_OBGetConfig 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:951:13:FLASH_MassErase 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:980:6:FLASH_Erase_Sector 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1030:26:FLASH_OB_EnableWRP 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1066:26:FLASH_OB_DisableWRP 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1160:26:FLASH_OB_RDP_LevelConfig 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1194:26:FLASH_OB_UserConfig 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1229:26:FLASH_OB_BOR_LevelConfig 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1247:16:FLASH_OB_GetUser 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1257:17:FLASH_OB_GetWRP 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1271:16:FLASH_OB_GetRDP 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1299:16:FLASH_OB_GetBOR 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1309:6:FLASH_FlushCaches 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d deleted file mode 100644 index 2108c0e..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o deleted file mode 100644 index 37f54db..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su deleted file mode 100644 index e69de29..0000000 diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d deleted file mode 100644 index f26b2a4..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o deleted file mode 100644 index cb391f8..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su deleted file mode 100644 index 2ae1321..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su +++ /dev/null @@ -1,8 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d deleted file mode 100644 index baeb205..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o deleted file mode 100644 index be33af6..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su deleted file mode 100644 index e0a0182..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su +++ /dev/null @@ -1,17 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:266:6:HAL_PWR_ConfigPVD 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:309:6:HAL_PWR_EnablePVD 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_DisablePVD 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:332:6:HAL_PWR_EnableWakeUpPin 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:350:6:HAL_PWR_DisableWakeUpPin 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:379:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:422:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:461:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:482:6:HAL_PWR_PVD_IRQHandler 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:499:13:HAL_PWR_PVDCallback 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:514:6:HAL_PWR_EnableSleepOnExit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:6:HAL_PWR_DisableSleepOnExit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:538:6:HAL_PWR_EnableSEVOnPend 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:550:6:HAL_PWR_DisableSEVOnPend 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d deleted file mode 100644 index 22bb879..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o deleted file mode 100644 index f1faa51..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su deleted file mode 100644 index cd686a1..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su +++ /dev/null @@ -1,6 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:232:19:HAL_PWREx_ControlVoltageScaling 32 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d deleted file mode 100644 index b37eed3..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o deleted file mode 100644 index a8ae14c..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su deleted file mode 100644 index 9dfcbbe..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su +++ /dev/null @@ -1,14 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 56 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 112 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:941:10:HAL_RCC_GetHCLKFreq 4 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:952:10:HAL_RCC_GetPCLK1Freq 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:964:10:HAL_RCC_GetPCLK2Freq 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:977:13:HAL_RCC_GetOscConfig 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1056:6:HAL_RCC_GetClockConfig 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1082:6:HAL_RCC_NMI_IRQHandler 8 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1099:13:HAL_RCC_CSSCallback 4 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d deleted file mode 100644 index 36d0bf5..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o deleted file mode 100644 index 2777547..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su deleted file mode 100644 index f23cf1b..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su +++ /dev/null @@ -1,6 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2513:19:HAL_RCCEx_PeriphCLKConfig 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2641:6:HAL_RCCEx_GetPeriphCLKConfig 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2679:10:HAL_RCCEx_GetPeriphCLKFreq 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2803:19:HAL_RCCEx_EnablePLLI2S 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2886:19:HAL_RCCEx_DisablePLLI2S 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3143:19:HAL_RCC_DeInit 16 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d deleted file mode 100644 index c8025c9..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o deleted file mode 100644 index f19e947..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.su deleted file mode 100644 index d5bbaf4..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.su +++ /dev/null @@ -1,55 +0,0 @@ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:311:19:HAL_SPI_Init 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:437:19:HAL_SPI_DeInit 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:481:13:HAL_SPI_MspInit 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:497:13:HAL_SPI_MspDeInit 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:769:19:HAL_SPI_Transmit 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:934:19:HAL_SPI_Receive 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1132:19:HAL_SPI_TransmitReceive 56 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1356:19:HAL_SPI_Transmit_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1441:19:HAL_SPI_Receive_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1535:19:HAL_SPI_TransmitReceive_IT 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1623:19:HAL_SPI_Transmit_DMA 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1731:19:HAL_SPI_Receive_DMA 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1846:19:HAL_SPI_TransmitReceive_DMA 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:1992:19:HAL_SPI_Abort 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2137:19:HAL_SPI_Abort_IT 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2298:19:HAL_SPI_DMAPause 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2318:19:HAL_SPI_DMAResume 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2338:19:HAL_SPI_DMAStop 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2378:6:HAL_SPI_IRQHandler 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2485:13:HAL_SPI_TxCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2501:13:HAL_SPI_RxCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2517:13:HAL_SPI_TxRxCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2533:13:HAL_SPI_TxHalfCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2549:13:HAL_SPI_RxHalfCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2565:13:HAL_SPI_TxRxHalfCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2581:13:HAL_SPI_ErrorCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2599:13:HAL_SPI_AbortCpltCallback 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2634:22:HAL_SPI_GetState 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2646:10:HAL_SPI_GetError 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2671:13:SPI_DMATransmitCplt 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2728:13:SPI_DMAReceiveCplt 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2817:13:SPI_DMATransmitReceiveCplt 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2897:13:SPI_DMAHalfTransmitCplt 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2915:13:SPI_DMAHalfReceiveCplt 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2933:13:SPI_DMAHalfTransmitReceiveCplt 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2951:13:SPI_DMAError 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2974:13:SPI_DMAAbortOnError 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:2996:13:SPI_DMATxAbortCallback 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3061:13:SPI_DMARxAbortCallback 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3120:13:SPI_2linesRxISR_8BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3183:13:SPI_2linesTxISR_8BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3219:13:SPI_2linesRxISR_16BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3275:13:SPI_2linesTxISR_16BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3335:13:SPI_RxISR_8BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3391:13:SPI_RxISR_16BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3424:13:SPI_TxISR_8BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3449:13:SPI_TxISR_16BIT 16 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3479:26:SPI_WaitFlagStateUntilTimeout 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3546:26:SPI_EndRxTransaction 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3596:26:SPI_EndRxTxTransaction 40 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3636:13:SPI_CloseRxTx_ISR 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3731:13:SPI_CloseRx_ISR 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3794:13:SPI_CloseTx_ISR 32 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3855:13:SPI_AbortRx_ISR 24 static -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c:3891:13:SPI_AbortTx_ISR 16 static diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d deleted file mode 100644 index 5033293..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o deleted file mode 100644 index 12b03c7..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su deleted file mode 100644 index e69de29..0000000 diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d deleted file mode 100644 index b6c2c81..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d +++ /dev/null @@ -1,54 +0,0 @@ -Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ - ../Core/Inc/stm32f4xx_hal_conf.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - ../Drivers/CMSIS/Include/core_cm4.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h: -../Drivers/CMSIS/Include/core_cm4.h: -../Drivers/CMSIS/Include/cmsis_version.h: -../Drivers/CMSIS/Include/cmsis_compiler.h: -../Drivers/CMSIS/Include/cmsis_gcc.h: -../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h: diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o deleted file mode 100644 index a6d5ff8..0000000 Binary files a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su deleted file mode 100644 index e69de29..0000000 diff --git a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk deleted file mode 100644 index adf5ba4..0000000 --- a/Software/Flapy Bird/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +++ /dev/null @@ -1,72 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c - -OBJS += \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - -C_DEPS += \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d - - -# Each subdirectory must supply rules for building sources it contributes -Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" - -clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src - -clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: - -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su - -.PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src - diff --git a/Software/Flapy Bird/Debug/Flapy Bird.elf b/Software/Flapy Bird/Debug/Flapy Bird.elf deleted file mode 100644 index 861c4ca..0000000 Binary files a/Software/Flapy Bird/Debug/Flapy Bird.elf and /dev/null differ diff --git a/Software/Flapy Bird/Debug/Flapy Bird.list b/Software/Flapy Bird/Debug/Flapy Bird.list deleted file mode 100644 index d4744a6..0000000 --- a/Software/Flapy Bird/Debug/Flapy Bird.list +++ /dev/null @@ -1,10492 +0,0 @@ - -Flapy Bird.elf: file format elf32-littlearm - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00004990 08000190 08000190 00010190 2**4 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000001a8 08004b20 08004b20 00014b20 2**2 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08004cc8 08004cc8 000226ec 2**0 - CONTENTS - 4 .ARM 00000008 08004cc8 08004cc8 00014cc8 2**2 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08004cd0 08004cd0 000226ec 2**0 - CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08004cd0 08004cd0 00014cd0 2**2 - CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08004cd4 08004cd4 00014cd4 2**2 - CONTENTS, ALLOC, LOAD, DATA - 8 .data 000026ec 20000000 08004cd8 00020000 2**2 - CONTENTS, ALLOC, LOAD, DATA - 9 .ccmram 00000000 10000000 10000000 000226ec 2**0 - CONTENTS - 10 .bss 000000c0 200026ec 200026ec 000226ec 2**2 - ALLOC - 11 ._user_heap_stack 00000604 200027ac 200027ac 000226ec 2**0 - ALLOC - 12 .ARM.attributes 00000030 00000000 00000000 000226ec 2**0 - CONTENTS, READONLY - 13 .debug_info 00007ab2 00000000 00000000 0002271c 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_abbrev 00001902 00000000 00000000 0002a1ce 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_aranges 000007d0 00000000 00000000 0002bad0 2**3 - CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_ranges 000006f8 00000000 00000000 0002c2a0 2**3 - CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_macro 000211e7 00000000 00000000 0002c998 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_line 00008acc 00000000 00000000 0004db7f 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .debug_str 000c3d9f 00000000 00000000 0005664b 2**0 - CONTENTS, READONLY, DEBUGGING, OCTETS - 20 .comment 00000050 00000000 00000000 0011a3ea 2**0 - CONTENTS, READONLY - 21 .debug_frame 000028ec 00000000 00000000 0011a43c 2**2 - CONTENTS, READONLY, DEBUGGING, OCTETS - -Disassembly of section .text: - -08000190 <__do_global_dtors_aux>: - 8000190: b510 push {r4, lr} - 8000192: 4c05 ldr r4, [pc, #20] ; (80001a8 <__do_global_dtors_aux+0x18>) - 8000194: 7823 ldrb r3, [r4, #0] - 8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16> - 8000198: 4b04 ldr r3, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x1c>) - 800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12> - 800019c: 4804 ldr r0, [pc, #16] ; (80001b0 <__do_global_dtors_aux+0x20>) - 800019e: f3af 8000 nop.w - 80001a2: 2301 movs r3, #1 - 80001a4: 7023 strb r3, [r4, #0] - 80001a6: bd10 pop {r4, pc} - 80001a8: 200026ec .word 0x200026ec - 80001ac: 00000000 .word 0x00000000 - 80001b0: 08004b08 .word 0x08004b08 - -080001b4 : - 80001b4: b508 push {r3, lr} - 80001b6: 4b03 ldr r3, [pc, #12] ; (80001c4 ) - 80001b8: b11b cbz r3, 80001c2 - 80001ba: 4903 ldr r1, [pc, #12] ; (80001c8 ) - 80001bc: 4803 ldr r0, [pc, #12] ; (80001cc ) - 80001be: f3af 8000 nop.w - 80001c2: bd08 pop {r3, pc} - 80001c4: 00000000 .word 0x00000000 - 80001c8: 200026f0 .word 0x200026f0 - 80001cc: 08004b08 .word 0x08004b08 - -080001d0 : - 80001d0: f001 01ff and.w r1, r1, #255 ; 0xff - 80001d4: 2a10 cmp r2, #16 - 80001d6: db2b blt.n 8000230 - 80001d8: f010 0f07 tst.w r0, #7 - 80001dc: d008 beq.n 80001f0 - 80001de: f810 3b01 ldrb.w r3, [r0], #1 - 80001e2: 3a01 subs r2, #1 - 80001e4: 428b cmp r3, r1 - 80001e6: d02d beq.n 8000244 - 80001e8: f010 0f07 tst.w r0, #7 - 80001ec: b342 cbz r2, 8000240 - 80001ee: d1f6 bne.n 80001de - 80001f0: b4f0 push {r4, r5, r6, r7} - 80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8 - 80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16 - 80001fa: f022 0407 bic.w r4, r2, #7 - 80001fe: f07f 0700 mvns.w r7, #0 - 8000202: 2300 movs r3, #0 - 8000204: e8f0 5602 ldrd r5, r6, [r0], #8 - 8000208: 3c08 subs r4, #8 - 800020a: ea85 0501 eor.w r5, r5, r1 - 800020e: ea86 0601 eor.w r6, r6, r1 - 8000212: fa85 f547 uadd8 r5, r5, r7 - 8000216: faa3 f587 sel r5, r3, r7 - 800021a: fa86 f647 uadd8 r6, r6, r7 - 800021e: faa5 f687 sel r6, r5, r7 - 8000222: b98e cbnz r6, 8000248 - 8000224: d1ee bne.n 8000204 - 8000226: bcf0 pop {r4, r5, r6, r7} - 8000228: f001 01ff and.w r1, r1, #255 ; 0xff - 800022c: f002 0207 and.w r2, r2, #7 - 8000230: b132 cbz r2, 8000240 - 8000232: f810 3b01 ldrb.w r3, [r0], #1 - 8000236: 3a01 subs r2, #1 - 8000238: ea83 0301 eor.w r3, r3, r1 - 800023c: b113 cbz r3, 8000244 - 800023e: d1f8 bne.n 8000232 - 8000240: 2000 movs r0, #0 - 8000242: 4770 bx lr - 8000244: 3801 subs r0, #1 - 8000246: 4770 bx lr - 8000248: 2d00 cmp r5, #0 - 800024a: bf06 itte eq - 800024c: 4635 moveq r5, r6 - 800024e: 3803 subeq r0, #3 - 8000250: 3807 subne r0, #7 - 8000252: f015 0f01 tst.w r5, #1 - 8000256: d107 bne.n 8000268 - 8000258: 3001 adds r0, #1 - 800025a: f415 7f80 tst.w r5, #256 ; 0x100 - 800025e: bf02 ittt eq - 8000260: 3001 addeq r0, #1 - 8000262: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 - 8000266: 3001 addeq r0, #1 - 8000268: bcf0 pop {r4, r5, r6, r7} - 800026a: 3801 subs r0, #1 - 800026c: 4770 bx lr - 800026e: bf00 nop - -08000270 <__aeabi_dmul>: - 8000270: b570 push {r4, r5, r6, lr} - 8000272: f04f 0cff mov.w ip, #255 ; 0xff - 8000276: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 - 800027a: ea1c 5411 ands.w r4, ip, r1, lsr #20 - 800027e: bf1d ittte ne - 8000280: ea1c 5513 andsne.w r5, ip, r3, lsr #20 - 8000284: ea94 0f0c teqne r4, ip - 8000288: ea95 0f0c teqne r5, ip - 800028c: f000 f8de bleq 800044c <__aeabi_dmul+0x1dc> - 8000290: 442c add r4, r5 - 8000292: ea81 0603 eor.w r6, r1, r3 - 8000296: ea21 514c bic.w r1, r1, ip, lsl #21 - 800029a: ea23 534c bic.w r3, r3, ip, lsl #21 - 800029e: ea50 3501 orrs.w r5, r0, r1, lsl #12 - 80002a2: bf18 it ne - 80002a4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 - 80002a8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 - 80002ac: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 - 80002b0: d038 beq.n 8000324 <__aeabi_dmul+0xb4> - 80002b2: fba0 ce02 umull ip, lr, r0, r2 - 80002b6: f04f 0500 mov.w r5, #0 - 80002ba: fbe1 e502 umlal lr, r5, r1, r2 - 80002be: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 - 80002c2: fbe0 e503 umlal lr, r5, r0, r3 - 80002c6: f04f 0600 mov.w r6, #0 - 80002ca: fbe1 5603 umlal r5, r6, r1, r3 - 80002ce: f09c 0f00 teq ip, #0 - 80002d2: bf18 it ne - 80002d4: f04e 0e01 orrne.w lr, lr, #1 - 80002d8: f1a4 04ff sub.w r4, r4, #255 ; 0xff - 80002dc: f5b6 7f00 cmp.w r6, #512 ; 0x200 - 80002e0: f564 7440 sbc.w r4, r4, #768 ; 0x300 - 80002e4: d204 bcs.n 80002f0 <__aeabi_dmul+0x80> - 80002e6: ea5f 0e4e movs.w lr, lr, lsl #1 - 80002ea: 416d adcs r5, r5 - 80002ec: eb46 0606 adc.w r6, r6, r6 - 80002f0: ea42 21c6 orr.w r1, r2, r6, lsl #11 - 80002f4: ea41 5155 orr.w r1, r1, r5, lsr #21 - 80002f8: ea4f 20c5 mov.w r0, r5, lsl #11 - 80002fc: ea40 505e orr.w r0, r0, lr, lsr #21 - 8000300: ea4f 2ece mov.w lr, lr, lsl #11 - 8000304: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd - 8000308: bf88 it hi - 800030a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 - 800030e: d81e bhi.n 800034e <__aeabi_dmul+0xde> - 8000310: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 - 8000314: bf08 it eq - 8000316: ea5f 0e50 movseq.w lr, r0, lsr #1 - 800031a: f150 0000 adcs.w r0, r0, #0 - 800031e: eb41 5104 adc.w r1, r1, r4, lsl #20 - 8000322: bd70 pop {r4, r5, r6, pc} - 8000324: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 - 8000328: ea46 0101 orr.w r1, r6, r1 - 800032c: ea40 0002 orr.w r0, r0, r2 - 8000330: ea81 0103 eor.w r1, r1, r3 - 8000334: ebb4 045c subs.w r4, r4, ip, lsr #1 - 8000338: bfc2 ittt gt - 800033a: ebd4 050c rsbsgt r5, r4, ip - 800033e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 - 8000342: bd70 popgt {r4, r5, r6, pc} - 8000344: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 - 8000348: f04f 0e00 mov.w lr, #0 - 800034c: 3c01 subs r4, #1 - 800034e: f300 80ab bgt.w 80004a8 <__aeabi_dmul+0x238> - 8000352: f114 0f36 cmn.w r4, #54 ; 0x36 - 8000356: bfde ittt le - 8000358: 2000 movle r0, #0 - 800035a: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 - 800035e: bd70 pople {r4, r5, r6, pc} - 8000360: f1c4 0400 rsb r4, r4, #0 - 8000364: 3c20 subs r4, #32 - 8000366: da35 bge.n 80003d4 <__aeabi_dmul+0x164> - 8000368: 340c adds r4, #12 - 800036a: dc1b bgt.n 80003a4 <__aeabi_dmul+0x134> - 800036c: f104 0414 add.w r4, r4, #20 - 8000370: f1c4 0520 rsb r5, r4, #32 - 8000374: fa00 f305 lsl.w r3, r0, r5 - 8000378: fa20 f004 lsr.w r0, r0, r4 - 800037c: fa01 f205 lsl.w r2, r1, r5 - 8000380: ea40 0002 orr.w r0, r0, r2 - 8000384: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 - 8000388: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 - 800038c: eb10 70d3 adds.w r0, r0, r3, lsr #31 - 8000390: fa21 f604 lsr.w r6, r1, r4 - 8000394: eb42 0106 adc.w r1, r2, r6 - 8000398: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 800039c: bf08 it eq - 800039e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 80003a2: bd70 pop {r4, r5, r6, pc} - 80003a4: f1c4 040c rsb r4, r4, #12 - 80003a8: f1c4 0520 rsb r5, r4, #32 - 80003ac: fa00 f304 lsl.w r3, r0, r4 - 80003b0: fa20 f005 lsr.w r0, r0, r5 - 80003b4: fa01 f204 lsl.w r2, r1, r4 - 80003b8: ea40 0002 orr.w r0, r0, r2 - 80003bc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 - 80003c0: eb10 70d3 adds.w r0, r0, r3, lsr #31 - 80003c4: f141 0100 adc.w r1, r1, #0 - 80003c8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 80003cc: bf08 it eq - 80003ce: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 80003d2: bd70 pop {r4, r5, r6, pc} - 80003d4: f1c4 0520 rsb r5, r4, #32 - 80003d8: fa00 f205 lsl.w r2, r0, r5 - 80003dc: ea4e 0e02 orr.w lr, lr, r2 - 80003e0: fa20 f304 lsr.w r3, r0, r4 - 80003e4: fa01 f205 lsl.w r2, r1, r5 - 80003e8: ea43 0302 orr.w r3, r3, r2 - 80003ec: fa21 f004 lsr.w r0, r1, r4 - 80003f0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 - 80003f4: fa21 f204 lsr.w r2, r1, r4 - 80003f8: ea20 0002 bic.w r0, r0, r2 - 80003fc: eb00 70d3 add.w r0, r0, r3, lsr #31 - 8000400: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 - 8000404: bf08 it eq - 8000406: ea20 70d3 biceq.w r0, r0, r3, lsr #31 - 800040a: bd70 pop {r4, r5, r6, pc} - 800040c: f094 0f00 teq r4, #0 - 8000410: d10f bne.n 8000432 <__aeabi_dmul+0x1c2> - 8000412: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 - 8000416: 0040 lsls r0, r0, #1 - 8000418: eb41 0101 adc.w r1, r1, r1 - 800041c: f411 1f80 tst.w r1, #1048576 ; 0x100000 - 8000420: bf08 it eq - 8000422: 3c01 subeq r4, #1 - 8000424: d0f7 beq.n 8000416 <__aeabi_dmul+0x1a6> - 8000426: ea41 0106 orr.w r1, r1, r6 - 800042a: f095 0f00 teq r5, #0 - 800042e: bf18 it ne - 8000430: 4770 bxne lr - 8000432: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 - 8000436: 0052 lsls r2, r2, #1 - 8000438: eb43 0303 adc.w r3, r3, r3 - 800043c: f413 1f80 tst.w r3, #1048576 ; 0x100000 - 8000440: bf08 it eq - 8000442: 3d01 subeq r5, #1 - 8000444: d0f7 beq.n 8000436 <__aeabi_dmul+0x1c6> - 8000446: ea43 0306 orr.w r3, r3, r6 - 800044a: 4770 bx lr - 800044c: ea94 0f0c teq r4, ip - 8000450: ea0c 5513 and.w r5, ip, r3, lsr #20 - 8000454: bf18 it ne - 8000456: ea95 0f0c teqne r5, ip - 800045a: d00c beq.n 8000476 <__aeabi_dmul+0x206> - 800045c: ea50 0641 orrs.w r6, r0, r1, lsl #1 - 8000460: bf18 it ne - 8000462: ea52 0643 orrsne.w r6, r2, r3, lsl #1 - 8000466: d1d1 bne.n 800040c <__aeabi_dmul+0x19c> - 8000468: ea81 0103 eor.w r1, r1, r3 - 800046c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 - 8000470: f04f 0000 mov.w r0, #0 - 8000474: bd70 pop {r4, r5, r6, pc} - 8000476: ea50 0641 orrs.w r6, r0, r1, lsl #1 - 800047a: bf06 itte eq - 800047c: 4610 moveq r0, r2 - 800047e: 4619 moveq r1, r3 - 8000480: ea52 0643 orrsne.w r6, r2, r3, lsl #1 - 8000484: d019 beq.n 80004ba <__aeabi_dmul+0x24a> - 8000486: ea94 0f0c teq r4, ip - 800048a: d102 bne.n 8000492 <__aeabi_dmul+0x222> - 800048c: ea50 3601 orrs.w r6, r0, r1, lsl #12 - 8000490: d113 bne.n 80004ba <__aeabi_dmul+0x24a> - 8000492: ea95 0f0c teq r5, ip - 8000496: d105 bne.n 80004a4 <__aeabi_dmul+0x234> - 8000498: ea52 3603 orrs.w r6, r2, r3, lsl #12 - 800049c: bf1c itt ne - 800049e: 4610 movne r0, r2 - 80004a0: 4619 movne r1, r3 - 80004a2: d10a bne.n 80004ba <__aeabi_dmul+0x24a> - 80004a4: ea81 0103 eor.w r1, r1, r3 - 80004a8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 - 80004ac: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 - 80004b0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 - 80004b4: f04f 0000 mov.w r0, #0 - 80004b8: bd70 pop {r4, r5, r6, pc} - 80004ba: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 - 80004be: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 - 80004c2: bd70 pop {r4, r5, r6, pc} - -080004c4 <__aeabi_drsub>: - 80004c4: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 - 80004c8: e002 b.n 80004d0 <__adddf3> - 80004ca: bf00 nop - -080004cc <__aeabi_dsub>: - 80004cc: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 - -080004d0 <__adddf3>: - 80004d0: b530 push {r4, r5, lr} - 80004d2: ea4f 0441 mov.w r4, r1, lsl #1 - 80004d6: ea4f 0543 mov.w r5, r3, lsl #1 - 80004da: ea94 0f05 teq r4, r5 - 80004de: bf08 it eq - 80004e0: ea90 0f02 teqeq r0, r2 - 80004e4: bf1f itttt ne - 80004e6: ea54 0c00 orrsne.w ip, r4, r0 - 80004ea: ea55 0c02 orrsne.w ip, r5, r2 - 80004ee: ea7f 5c64 mvnsne.w ip, r4, asr #21 - 80004f2: ea7f 5c65 mvnsne.w ip, r5, asr #21 - 80004f6: f000 80e2 beq.w 80006be <__adddf3+0x1ee> - 80004fa: ea4f 5454 mov.w r4, r4, lsr #21 - 80004fe: ebd4 5555 rsbs r5, r4, r5, lsr #21 - 8000502: bfb8 it lt - 8000504: 426d neglt r5, r5 - 8000506: dd0c ble.n 8000522 <__adddf3+0x52> - 8000508: 442c add r4, r5 - 800050a: ea80 0202 eor.w r2, r0, r2 - 800050e: ea81 0303 eor.w r3, r1, r3 - 8000512: ea82 0000 eor.w r0, r2, r0 - 8000516: ea83 0101 eor.w r1, r3, r1 - 800051a: ea80 0202 eor.w r2, r0, r2 - 800051e: ea81 0303 eor.w r3, r1, r3 - 8000522: 2d36 cmp r5, #54 ; 0x36 - 8000524: bf88 it hi - 8000526: bd30 pophi {r4, r5, pc} - 8000528: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 - 800052c: ea4f 3101 mov.w r1, r1, lsl #12 - 8000530: f44f 1c80 mov.w ip, #1048576 ; 0x100000 - 8000534: ea4c 3111 orr.w r1, ip, r1, lsr #12 - 8000538: d002 beq.n 8000540 <__adddf3+0x70> - 800053a: 4240 negs r0, r0 - 800053c: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 8000540: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 - 8000544: ea4f 3303 mov.w r3, r3, lsl #12 - 8000548: ea4c 3313 orr.w r3, ip, r3, lsr #12 - 800054c: d002 beq.n 8000554 <__adddf3+0x84> - 800054e: 4252 negs r2, r2 - 8000550: eb63 0343 sbc.w r3, r3, r3, lsl #1 - 8000554: ea94 0f05 teq r4, r5 - 8000558: f000 80a7 beq.w 80006aa <__adddf3+0x1da> - 800055c: f1a4 0401 sub.w r4, r4, #1 - 8000560: f1d5 0e20 rsbs lr, r5, #32 - 8000564: db0d blt.n 8000582 <__adddf3+0xb2> - 8000566: fa02 fc0e lsl.w ip, r2, lr - 800056a: fa22 f205 lsr.w r2, r2, r5 - 800056e: 1880 adds r0, r0, r2 - 8000570: f141 0100 adc.w r1, r1, #0 - 8000574: fa03 f20e lsl.w r2, r3, lr - 8000578: 1880 adds r0, r0, r2 - 800057a: fa43 f305 asr.w r3, r3, r5 - 800057e: 4159 adcs r1, r3 - 8000580: e00e b.n 80005a0 <__adddf3+0xd0> - 8000582: f1a5 0520 sub.w r5, r5, #32 - 8000586: f10e 0e20 add.w lr, lr, #32 - 800058a: 2a01 cmp r2, #1 - 800058c: fa03 fc0e lsl.w ip, r3, lr - 8000590: bf28 it cs - 8000592: f04c 0c02 orrcs.w ip, ip, #2 - 8000596: fa43 f305 asr.w r3, r3, r5 - 800059a: 18c0 adds r0, r0, r3 - 800059c: eb51 71e3 adcs.w r1, r1, r3, asr #31 - 80005a0: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 - 80005a4: d507 bpl.n 80005b6 <__adddf3+0xe6> - 80005a6: f04f 0e00 mov.w lr, #0 - 80005aa: f1dc 0c00 rsbs ip, ip, #0 - 80005ae: eb7e 0000 sbcs.w r0, lr, r0 - 80005b2: eb6e 0101 sbc.w r1, lr, r1 - 80005b6: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 - 80005ba: d31b bcc.n 80005f4 <__adddf3+0x124> - 80005bc: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 - 80005c0: d30c bcc.n 80005dc <__adddf3+0x10c> - 80005c2: 0849 lsrs r1, r1, #1 - 80005c4: ea5f 0030 movs.w r0, r0, rrx - 80005c8: ea4f 0c3c mov.w ip, ip, rrx - 80005cc: f104 0401 add.w r4, r4, #1 - 80005d0: ea4f 5244 mov.w r2, r4, lsl #21 - 80005d4: f512 0f80 cmn.w r2, #4194304 ; 0x400000 - 80005d8: f080 809a bcs.w 8000710 <__adddf3+0x240> - 80005dc: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 - 80005e0: bf08 it eq - 80005e2: ea5f 0c50 movseq.w ip, r0, lsr #1 - 80005e6: f150 0000 adcs.w r0, r0, #0 - 80005ea: eb41 5104 adc.w r1, r1, r4, lsl #20 - 80005ee: ea41 0105 orr.w r1, r1, r5 - 80005f2: bd30 pop {r4, r5, pc} - 80005f4: ea5f 0c4c movs.w ip, ip, lsl #1 - 80005f8: 4140 adcs r0, r0 - 80005fa: eb41 0101 adc.w r1, r1, r1 - 80005fe: 3c01 subs r4, #1 - 8000600: bf28 it cs - 8000602: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 - 8000606: d2e9 bcs.n 80005dc <__adddf3+0x10c> - 8000608: f091 0f00 teq r1, #0 - 800060c: bf04 itt eq - 800060e: 4601 moveq r1, r0 - 8000610: 2000 moveq r0, #0 - 8000612: fab1 f381 clz r3, r1 - 8000616: bf08 it eq - 8000618: 3320 addeq r3, #32 - 800061a: f1a3 030b sub.w r3, r3, #11 - 800061e: f1b3 0220 subs.w r2, r3, #32 - 8000622: da0c bge.n 800063e <__adddf3+0x16e> - 8000624: 320c adds r2, #12 - 8000626: dd08 ble.n 800063a <__adddf3+0x16a> - 8000628: f102 0c14 add.w ip, r2, #20 - 800062c: f1c2 020c rsb r2, r2, #12 - 8000630: fa01 f00c lsl.w r0, r1, ip - 8000634: fa21 f102 lsr.w r1, r1, r2 - 8000638: e00c b.n 8000654 <__adddf3+0x184> - 800063a: f102 0214 add.w r2, r2, #20 - 800063e: bfd8 it le - 8000640: f1c2 0c20 rsble ip, r2, #32 - 8000644: fa01 f102 lsl.w r1, r1, r2 - 8000648: fa20 fc0c lsr.w ip, r0, ip - 800064c: bfdc itt le - 800064e: ea41 010c orrle.w r1, r1, ip - 8000652: 4090 lslle r0, r2 - 8000654: 1ae4 subs r4, r4, r3 - 8000656: bfa2 ittt ge - 8000658: eb01 5104 addge.w r1, r1, r4, lsl #20 - 800065c: 4329 orrge r1, r5 - 800065e: bd30 popge {r4, r5, pc} - 8000660: ea6f 0404 mvn.w r4, r4 - 8000664: 3c1f subs r4, #31 - 8000666: da1c bge.n 80006a2 <__adddf3+0x1d2> - 8000668: 340c adds r4, #12 - 800066a: dc0e bgt.n 800068a <__adddf3+0x1ba> - 800066c: f104 0414 add.w r4, r4, #20 - 8000670: f1c4 0220 rsb r2, r4, #32 - 8000674: fa20 f004 lsr.w r0, r0, r4 - 8000678: fa01 f302 lsl.w r3, r1, r2 - 800067c: ea40 0003 orr.w r0, r0, r3 - 8000680: fa21 f304 lsr.w r3, r1, r4 - 8000684: ea45 0103 orr.w r1, r5, r3 - 8000688: bd30 pop {r4, r5, pc} - 800068a: f1c4 040c rsb r4, r4, #12 - 800068e: f1c4 0220 rsb r2, r4, #32 - 8000692: fa20 f002 lsr.w r0, r0, r2 - 8000696: fa01 f304 lsl.w r3, r1, r4 - 800069a: ea40 0003 orr.w r0, r0, r3 - 800069e: 4629 mov r1, r5 - 80006a0: bd30 pop {r4, r5, pc} - 80006a2: fa21 f004 lsr.w r0, r1, r4 - 80006a6: 4629 mov r1, r5 - 80006a8: bd30 pop {r4, r5, pc} - 80006aa: f094 0f00 teq r4, #0 - 80006ae: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 - 80006b2: bf06 itte eq - 80006b4: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 - 80006b8: 3401 addeq r4, #1 - 80006ba: 3d01 subne r5, #1 - 80006bc: e74e b.n 800055c <__adddf3+0x8c> - 80006be: ea7f 5c64 mvns.w ip, r4, asr #21 - 80006c2: bf18 it ne - 80006c4: ea7f 5c65 mvnsne.w ip, r5, asr #21 - 80006c8: d029 beq.n 800071e <__adddf3+0x24e> - 80006ca: ea94 0f05 teq r4, r5 - 80006ce: bf08 it eq - 80006d0: ea90 0f02 teqeq r0, r2 - 80006d4: d005 beq.n 80006e2 <__adddf3+0x212> - 80006d6: ea54 0c00 orrs.w ip, r4, r0 - 80006da: bf04 itt eq - 80006dc: 4619 moveq r1, r3 - 80006de: 4610 moveq r0, r2 - 80006e0: bd30 pop {r4, r5, pc} - 80006e2: ea91 0f03 teq r1, r3 - 80006e6: bf1e ittt ne - 80006e8: 2100 movne r1, #0 - 80006ea: 2000 movne r0, #0 - 80006ec: bd30 popne {r4, r5, pc} - 80006ee: ea5f 5c54 movs.w ip, r4, lsr #21 - 80006f2: d105 bne.n 8000700 <__adddf3+0x230> - 80006f4: 0040 lsls r0, r0, #1 - 80006f6: 4149 adcs r1, r1 - 80006f8: bf28 it cs - 80006fa: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 - 80006fe: bd30 pop {r4, r5, pc} - 8000700: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 - 8000704: bf3c itt cc - 8000706: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 - 800070a: bd30 popcc {r4, r5, pc} - 800070c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 - 8000710: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 - 8000714: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 - 8000718: f04f 0000 mov.w r0, #0 - 800071c: bd30 pop {r4, r5, pc} - 800071e: ea7f 5c64 mvns.w ip, r4, asr #21 - 8000722: bf1a itte ne - 8000724: 4619 movne r1, r3 - 8000726: 4610 movne r0, r2 - 8000728: ea7f 5c65 mvnseq.w ip, r5, asr #21 - 800072c: bf1c itt ne - 800072e: 460b movne r3, r1 - 8000730: 4602 movne r2, r0 - 8000732: ea50 3401 orrs.w r4, r0, r1, lsl #12 - 8000736: bf06 itte eq - 8000738: ea52 3503 orrseq.w r5, r2, r3, lsl #12 - 800073c: ea91 0f03 teqeq r1, r3 - 8000740: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 - 8000744: bd30 pop {r4, r5, pc} - 8000746: bf00 nop - -08000748 <__aeabi_ui2d>: - 8000748: f090 0f00 teq r0, #0 - 800074c: bf04 itt eq - 800074e: 2100 moveq r1, #0 - 8000750: 4770 bxeq lr - 8000752: b530 push {r4, r5, lr} - 8000754: f44f 6480 mov.w r4, #1024 ; 0x400 - 8000758: f104 0432 add.w r4, r4, #50 ; 0x32 - 800075c: f04f 0500 mov.w r5, #0 - 8000760: f04f 0100 mov.w r1, #0 - 8000764: e750 b.n 8000608 <__adddf3+0x138> - 8000766: bf00 nop - -08000768 <__aeabi_i2d>: - 8000768: f090 0f00 teq r0, #0 - 800076c: bf04 itt eq - 800076e: 2100 moveq r1, #0 - 8000770: 4770 bxeq lr - 8000772: b530 push {r4, r5, lr} - 8000774: f44f 6480 mov.w r4, #1024 ; 0x400 - 8000778: f104 0432 add.w r4, r4, #50 ; 0x32 - 800077c: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 - 8000780: bf48 it mi - 8000782: 4240 negmi r0, r0 - 8000784: f04f 0100 mov.w r1, #0 - 8000788: e73e b.n 8000608 <__adddf3+0x138> - 800078a: bf00 nop - -0800078c <__aeabi_f2d>: - 800078c: 0042 lsls r2, r0, #1 - 800078e: ea4f 01e2 mov.w r1, r2, asr #3 - 8000792: ea4f 0131 mov.w r1, r1, rrx - 8000796: ea4f 7002 mov.w r0, r2, lsl #28 - 800079a: bf1f itttt ne - 800079c: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 - 80007a0: f093 4f7f teqne r3, #4278190080 ; 0xff000000 - 80007a4: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 - 80007a8: 4770 bxne lr - 80007aa: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 - 80007ae: bf08 it eq - 80007b0: 4770 bxeq lr - 80007b2: f093 4f7f teq r3, #4278190080 ; 0xff000000 - 80007b6: bf04 itt eq - 80007b8: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 - 80007bc: 4770 bxeq lr - 80007be: b530 push {r4, r5, lr} - 80007c0: f44f 7460 mov.w r4, #896 ; 0x380 - 80007c4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 - 80007c8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 - 80007cc: e71c b.n 8000608 <__adddf3+0x138> - 80007ce: bf00 nop - -080007d0 <__aeabi_ul2d>: - 80007d0: ea50 0201 orrs.w r2, r0, r1 - 80007d4: bf08 it eq - 80007d6: 4770 bxeq lr - 80007d8: b530 push {r4, r5, lr} - 80007da: f04f 0500 mov.w r5, #0 - 80007de: e00a b.n 80007f6 <__aeabi_l2d+0x16> - -080007e0 <__aeabi_l2d>: - 80007e0: ea50 0201 orrs.w r2, r0, r1 - 80007e4: bf08 it eq - 80007e6: 4770 bxeq lr - 80007e8: b530 push {r4, r5, lr} - 80007ea: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 - 80007ee: d502 bpl.n 80007f6 <__aeabi_l2d+0x16> - 80007f0: 4240 negs r0, r0 - 80007f2: eb61 0141 sbc.w r1, r1, r1, lsl #1 - 80007f6: f44f 6480 mov.w r4, #1024 ; 0x400 - 80007fa: f104 0432 add.w r4, r4, #50 ; 0x32 - 80007fe: ea5f 5c91 movs.w ip, r1, lsr #22 - 8000802: f43f aed8 beq.w 80005b6 <__adddf3+0xe6> - 8000806: f04f 0203 mov.w r2, #3 - 800080a: ea5f 0cdc movs.w ip, ip, lsr #3 - 800080e: bf18 it ne - 8000810: 3203 addne r2, #3 - 8000812: ea5f 0cdc movs.w ip, ip, lsr #3 - 8000816: bf18 it ne - 8000818: 3203 addne r2, #3 - 800081a: eb02 02dc add.w r2, r2, ip, lsr #3 - 800081e: f1c2 0320 rsb r3, r2, #32 - 8000822: fa00 fc03 lsl.w ip, r0, r3 - 8000826: fa20 f002 lsr.w r0, r0, r2 - 800082a: fa01 fe03 lsl.w lr, r1, r3 - 800082e: ea40 000e orr.w r0, r0, lr - 8000832: fa21 f102 lsr.w r1, r1, r2 - 8000836: 4414 add r4, r2 - 8000838: e6bd b.n 80005b6 <__adddf3+0xe6> - 800083a: bf00 nop - -0800083c <__aeabi_d2uiz>: - 800083c: 004a lsls r2, r1, #1 - 800083e: d211 bcs.n 8000864 <__aeabi_d2uiz+0x28> - 8000840: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 - 8000844: d211 bcs.n 800086a <__aeabi_d2uiz+0x2e> - 8000846: d50d bpl.n 8000864 <__aeabi_d2uiz+0x28> - 8000848: f46f 7378 mvn.w r3, #992 ; 0x3e0 - 800084c: ebb3 5262 subs.w r2, r3, r2, asr #21 - 8000850: d40e bmi.n 8000870 <__aeabi_d2uiz+0x34> - 8000852: ea4f 23c1 mov.w r3, r1, lsl #11 - 8000856: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 - 800085a: ea43 5350 orr.w r3, r3, r0, lsr #21 - 800085e: fa23 f002 lsr.w r0, r3, r2 - 8000862: 4770 bx lr - 8000864: f04f 0000 mov.w r0, #0 - 8000868: 4770 bx lr - 800086a: ea50 3001 orrs.w r0, r0, r1, lsl #12 - 800086e: d102 bne.n 8000876 <__aeabi_d2uiz+0x3a> - 8000870: f04f 30ff mov.w r0, #4294967295 - 8000874: 4770 bx lr - 8000876: f04f 0000 mov.w r0, #0 - 800087a: 4770 bx lr - -0800087c <__aeabi_uldivmod>: - 800087c: b953 cbnz r3, 8000894 <__aeabi_uldivmod+0x18> - 800087e: b94a cbnz r2, 8000894 <__aeabi_uldivmod+0x18> - 8000880: 2900 cmp r1, #0 - 8000882: bf08 it eq - 8000884: 2800 cmpeq r0, #0 - 8000886: bf1c itt ne - 8000888: f04f 31ff movne.w r1, #4294967295 - 800088c: f04f 30ff movne.w r0, #4294967295 - 8000890: f000 b974 b.w 8000b7c <__aeabi_idiv0> - 8000894: f1ad 0c08 sub.w ip, sp, #8 - 8000898: e96d ce04 strd ip, lr, [sp, #-16]! - 800089c: f000 f806 bl 80008ac <__udivmoddi4> - 80008a0: f8dd e004 ldr.w lr, [sp, #4] - 80008a4: e9dd 2302 ldrd r2, r3, [sp, #8] - 80008a8: b004 add sp, #16 - 80008aa: 4770 bx lr - -080008ac <__udivmoddi4>: - 80008ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 80008b0: 9d08 ldr r5, [sp, #32] - 80008b2: 4604 mov r4, r0 - 80008b4: 468e mov lr, r1 - 80008b6: 2b00 cmp r3, #0 - 80008b8: d14d bne.n 8000956 <__udivmoddi4+0xaa> - 80008ba: 428a cmp r2, r1 - 80008bc: 4694 mov ip, r2 - 80008be: d969 bls.n 8000994 <__udivmoddi4+0xe8> - 80008c0: fab2 f282 clz r2, r2 - 80008c4: b152 cbz r2, 80008dc <__udivmoddi4+0x30> - 80008c6: fa01 f302 lsl.w r3, r1, r2 - 80008ca: f1c2 0120 rsb r1, r2, #32 - 80008ce: fa20 f101 lsr.w r1, r0, r1 - 80008d2: fa0c fc02 lsl.w ip, ip, r2 - 80008d6: ea41 0e03 orr.w lr, r1, r3 - 80008da: 4094 lsls r4, r2 - 80008dc: ea4f 481c mov.w r8, ip, lsr #16 - 80008e0: 0c21 lsrs r1, r4, #16 - 80008e2: fbbe f6f8 udiv r6, lr, r8 - 80008e6: fa1f f78c uxth.w r7, ip - 80008ea: fb08 e316 mls r3, r8, r6, lr - 80008ee: ea41 4303 orr.w r3, r1, r3, lsl #16 - 80008f2: fb06 f107 mul.w r1, r6, r7 - 80008f6: 4299 cmp r1, r3 - 80008f8: d90a bls.n 8000910 <__udivmoddi4+0x64> - 80008fa: eb1c 0303 adds.w r3, ip, r3 - 80008fe: f106 30ff add.w r0, r6, #4294967295 - 8000902: f080 811f bcs.w 8000b44 <__udivmoddi4+0x298> - 8000906: 4299 cmp r1, r3 - 8000908: f240 811c bls.w 8000b44 <__udivmoddi4+0x298> - 800090c: 3e02 subs r6, #2 - 800090e: 4463 add r3, ip - 8000910: 1a5b subs r3, r3, r1 - 8000912: b2a4 uxth r4, r4 - 8000914: fbb3 f0f8 udiv r0, r3, r8 - 8000918: fb08 3310 mls r3, r8, r0, r3 - 800091c: ea44 4403 orr.w r4, r4, r3, lsl #16 - 8000920: fb00 f707 mul.w r7, r0, r7 - 8000924: 42a7 cmp r7, r4 - 8000926: d90a bls.n 800093e <__udivmoddi4+0x92> - 8000928: eb1c 0404 adds.w r4, ip, r4 - 800092c: f100 33ff add.w r3, r0, #4294967295 - 8000930: f080 810a bcs.w 8000b48 <__udivmoddi4+0x29c> - 8000934: 42a7 cmp r7, r4 - 8000936: f240 8107 bls.w 8000b48 <__udivmoddi4+0x29c> - 800093a: 4464 add r4, ip - 800093c: 3802 subs r0, #2 - 800093e: ea40 4006 orr.w r0, r0, r6, lsl #16 - 8000942: 1be4 subs r4, r4, r7 - 8000944: 2600 movs r6, #0 - 8000946: b11d cbz r5, 8000950 <__udivmoddi4+0xa4> - 8000948: 40d4 lsrs r4, r2 - 800094a: 2300 movs r3, #0 - 800094c: e9c5 4300 strd r4, r3, [r5] - 8000950: 4631 mov r1, r6 - 8000952: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8000956: 428b cmp r3, r1 - 8000958: d909 bls.n 800096e <__udivmoddi4+0xc2> - 800095a: 2d00 cmp r5, #0 - 800095c: f000 80ef beq.w 8000b3e <__udivmoddi4+0x292> - 8000960: 2600 movs r6, #0 - 8000962: e9c5 0100 strd r0, r1, [r5] - 8000966: 4630 mov r0, r6 - 8000968: 4631 mov r1, r6 - 800096a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800096e: fab3 f683 clz r6, r3 - 8000972: 2e00 cmp r6, #0 - 8000974: d14a bne.n 8000a0c <__udivmoddi4+0x160> - 8000976: 428b cmp r3, r1 - 8000978: d302 bcc.n 8000980 <__udivmoddi4+0xd4> - 800097a: 4282 cmp r2, r0 - 800097c: f200 80f9 bhi.w 8000b72 <__udivmoddi4+0x2c6> - 8000980: 1a84 subs r4, r0, r2 - 8000982: eb61 0303 sbc.w r3, r1, r3 - 8000986: 2001 movs r0, #1 - 8000988: 469e mov lr, r3 - 800098a: 2d00 cmp r5, #0 - 800098c: d0e0 beq.n 8000950 <__udivmoddi4+0xa4> - 800098e: e9c5 4e00 strd r4, lr, [r5] - 8000992: e7dd b.n 8000950 <__udivmoddi4+0xa4> - 8000994: b902 cbnz r2, 8000998 <__udivmoddi4+0xec> - 8000996: deff udf #255 ; 0xff - 8000998: fab2 f282 clz r2, r2 - 800099c: 2a00 cmp r2, #0 - 800099e: f040 8092 bne.w 8000ac6 <__udivmoddi4+0x21a> - 80009a2: eba1 010c sub.w r1, r1, ip - 80009a6: ea4f 471c mov.w r7, ip, lsr #16 - 80009aa: fa1f fe8c uxth.w lr, ip - 80009ae: 2601 movs r6, #1 - 80009b0: 0c20 lsrs r0, r4, #16 - 80009b2: fbb1 f3f7 udiv r3, r1, r7 - 80009b6: fb07 1113 mls r1, r7, r3, r1 - 80009ba: ea40 4101 orr.w r1, r0, r1, lsl #16 - 80009be: fb0e f003 mul.w r0, lr, r3 - 80009c2: 4288 cmp r0, r1 - 80009c4: d908 bls.n 80009d8 <__udivmoddi4+0x12c> - 80009c6: eb1c 0101 adds.w r1, ip, r1 - 80009ca: f103 38ff add.w r8, r3, #4294967295 - 80009ce: d202 bcs.n 80009d6 <__udivmoddi4+0x12a> - 80009d0: 4288 cmp r0, r1 - 80009d2: f200 80cb bhi.w 8000b6c <__udivmoddi4+0x2c0> - 80009d6: 4643 mov r3, r8 - 80009d8: 1a09 subs r1, r1, r0 - 80009da: b2a4 uxth r4, r4 - 80009dc: fbb1 f0f7 udiv r0, r1, r7 - 80009e0: fb07 1110 mls r1, r7, r0, r1 - 80009e4: ea44 4401 orr.w r4, r4, r1, lsl #16 - 80009e8: fb0e fe00 mul.w lr, lr, r0 - 80009ec: 45a6 cmp lr, r4 - 80009ee: d908 bls.n 8000a02 <__udivmoddi4+0x156> - 80009f0: eb1c 0404 adds.w r4, ip, r4 - 80009f4: f100 31ff add.w r1, r0, #4294967295 - 80009f8: d202 bcs.n 8000a00 <__udivmoddi4+0x154> - 80009fa: 45a6 cmp lr, r4 - 80009fc: f200 80bb bhi.w 8000b76 <__udivmoddi4+0x2ca> - 8000a00: 4608 mov r0, r1 - 8000a02: eba4 040e sub.w r4, r4, lr - 8000a06: ea40 4003 orr.w r0, r0, r3, lsl #16 - 8000a0a: e79c b.n 8000946 <__udivmoddi4+0x9a> - 8000a0c: f1c6 0720 rsb r7, r6, #32 - 8000a10: 40b3 lsls r3, r6 - 8000a12: fa22 fc07 lsr.w ip, r2, r7 - 8000a16: ea4c 0c03 orr.w ip, ip, r3 - 8000a1a: fa20 f407 lsr.w r4, r0, r7 - 8000a1e: fa01 f306 lsl.w r3, r1, r6 - 8000a22: 431c orrs r4, r3 - 8000a24: 40f9 lsrs r1, r7 - 8000a26: ea4f 491c mov.w r9, ip, lsr #16 - 8000a2a: fa00 f306 lsl.w r3, r0, r6 - 8000a2e: fbb1 f8f9 udiv r8, r1, r9 - 8000a32: 0c20 lsrs r0, r4, #16 - 8000a34: fa1f fe8c uxth.w lr, ip - 8000a38: fb09 1118 mls r1, r9, r8, r1 - 8000a3c: ea40 4101 orr.w r1, r0, r1, lsl #16 - 8000a40: fb08 f00e mul.w r0, r8, lr - 8000a44: 4288 cmp r0, r1 - 8000a46: fa02 f206 lsl.w r2, r2, r6 - 8000a4a: d90b bls.n 8000a64 <__udivmoddi4+0x1b8> - 8000a4c: eb1c 0101 adds.w r1, ip, r1 - 8000a50: f108 3aff add.w sl, r8, #4294967295 - 8000a54: f080 8088 bcs.w 8000b68 <__udivmoddi4+0x2bc> - 8000a58: 4288 cmp r0, r1 - 8000a5a: f240 8085 bls.w 8000b68 <__udivmoddi4+0x2bc> - 8000a5e: f1a8 0802 sub.w r8, r8, #2 - 8000a62: 4461 add r1, ip - 8000a64: 1a09 subs r1, r1, r0 - 8000a66: b2a4 uxth r4, r4 - 8000a68: fbb1 f0f9 udiv r0, r1, r9 - 8000a6c: fb09 1110 mls r1, r9, r0, r1 - 8000a70: ea44 4101 orr.w r1, r4, r1, lsl #16 - 8000a74: fb00 fe0e mul.w lr, r0, lr - 8000a78: 458e cmp lr, r1 - 8000a7a: d908 bls.n 8000a8e <__udivmoddi4+0x1e2> - 8000a7c: eb1c 0101 adds.w r1, ip, r1 - 8000a80: f100 34ff add.w r4, r0, #4294967295 - 8000a84: d26c bcs.n 8000b60 <__udivmoddi4+0x2b4> - 8000a86: 458e cmp lr, r1 - 8000a88: d96a bls.n 8000b60 <__udivmoddi4+0x2b4> - 8000a8a: 3802 subs r0, #2 - 8000a8c: 4461 add r1, ip - 8000a8e: ea40 4008 orr.w r0, r0, r8, lsl #16 - 8000a92: fba0 9402 umull r9, r4, r0, r2 - 8000a96: eba1 010e sub.w r1, r1, lr - 8000a9a: 42a1 cmp r1, r4 - 8000a9c: 46c8 mov r8, r9 - 8000a9e: 46a6 mov lr, r4 - 8000aa0: d356 bcc.n 8000b50 <__udivmoddi4+0x2a4> - 8000aa2: d053 beq.n 8000b4c <__udivmoddi4+0x2a0> - 8000aa4: b15d cbz r5, 8000abe <__udivmoddi4+0x212> - 8000aa6: ebb3 0208 subs.w r2, r3, r8 - 8000aaa: eb61 010e sbc.w r1, r1, lr - 8000aae: fa01 f707 lsl.w r7, r1, r7 - 8000ab2: fa22 f306 lsr.w r3, r2, r6 - 8000ab6: 40f1 lsrs r1, r6 - 8000ab8: 431f orrs r7, r3 - 8000aba: e9c5 7100 strd r7, r1, [r5] - 8000abe: 2600 movs r6, #0 - 8000ac0: 4631 mov r1, r6 - 8000ac2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8000ac6: f1c2 0320 rsb r3, r2, #32 - 8000aca: 40d8 lsrs r0, r3 - 8000acc: fa0c fc02 lsl.w ip, ip, r2 - 8000ad0: fa21 f303 lsr.w r3, r1, r3 - 8000ad4: 4091 lsls r1, r2 - 8000ad6: 4301 orrs r1, r0 - 8000ad8: ea4f 471c mov.w r7, ip, lsr #16 - 8000adc: fa1f fe8c uxth.w lr, ip - 8000ae0: fbb3 f0f7 udiv r0, r3, r7 - 8000ae4: fb07 3610 mls r6, r7, r0, r3 - 8000ae8: 0c0b lsrs r3, r1, #16 - 8000aea: ea43 4306 orr.w r3, r3, r6, lsl #16 - 8000aee: fb00 f60e mul.w r6, r0, lr - 8000af2: 429e cmp r6, r3 - 8000af4: fa04 f402 lsl.w r4, r4, r2 - 8000af8: d908 bls.n 8000b0c <__udivmoddi4+0x260> - 8000afa: eb1c 0303 adds.w r3, ip, r3 - 8000afe: f100 38ff add.w r8, r0, #4294967295 - 8000b02: d22f bcs.n 8000b64 <__udivmoddi4+0x2b8> - 8000b04: 429e cmp r6, r3 - 8000b06: d92d bls.n 8000b64 <__udivmoddi4+0x2b8> - 8000b08: 3802 subs r0, #2 - 8000b0a: 4463 add r3, ip - 8000b0c: 1b9b subs r3, r3, r6 - 8000b0e: b289 uxth r1, r1 - 8000b10: fbb3 f6f7 udiv r6, r3, r7 - 8000b14: fb07 3316 mls r3, r7, r6, r3 - 8000b18: ea41 4103 orr.w r1, r1, r3, lsl #16 - 8000b1c: fb06 f30e mul.w r3, r6, lr - 8000b20: 428b cmp r3, r1 - 8000b22: d908 bls.n 8000b36 <__udivmoddi4+0x28a> - 8000b24: eb1c 0101 adds.w r1, ip, r1 - 8000b28: f106 38ff add.w r8, r6, #4294967295 - 8000b2c: d216 bcs.n 8000b5c <__udivmoddi4+0x2b0> - 8000b2e: 428b cmp r3, r1 - 8000b30: d914 bls.n 8000b5c <__udivmoddi4+0x2b0> - 8000b32: 3e02 subs r6, #2 - 8000b34: 4461 add r1, ip - 8000b36: 1ac9 subs r1, r1, r3 - 8000b38: ea46 4600 orr.w r6, r6, r0, lsl #16 - 8000b3c: e738 b.n 80009b0 <__udivmoddi4+0x104> - 8000b3e: 462e mov r6, r5 - 8000b40: 4628 mov r0, r5 - 8000b42: e705 b.n 8000950 <__udivmoddi4+0xa4> - 8000b44: 4606 mov r6, r0 - 8000b46: e6e3 b.n 8000910 <__udivmoddi4+0x64> - 8000b48: 4618 mov r0, r3 - 8000b4a: e6f8 b.n 800093e <__udivmoddi4+0x92> - 8000b4c: 454b cmp r3, r9 - 8000b4e: d2a9 bcs.n 8000aa4 <__udivmoddi4+0x1f8> - 8000b50: ebb9 0802 subs.w r8, r9, r2 - 8000b54: eb64 0e0c sbc.w lr, r4, ip - 8000b58: 3801 subs r0, #1 - 8000b5a: e7a3 b.n 8000aa4 <__udivmoddi4+0x1f8> - 8000b5c: 4646 mov r6, r8 - 8000b5e: e7ea b.n 8000b36 <__udivmoddi4+0x28a> - 8000b60: 4620 mov r0, r4 - 8000b62: e794 b.n 8000a8e <__udivmoddi4+0x1e2> - 8000b64: 4640 mov r0, r8 - 8000b66: e7d1 b.n 8000b0c <__udivmoddi4+0x260> - 8000b68: 46d0 mov r8, sl - 8000b6a: e77b b.n 8000a64 <__udivmoddi4+0x1b8> - 8000b6c: 3b02 subs r3, #2 - 8000b6e: 4461 add r1, ip - 8000b70: e732 b.n 80009d8 <__udivmoddi4+0x12c> - 8000b72: 4630 mov r0, r6 - 8000b74: e709 b.n 800098a <__udivmoddi4+0xde> - 8000b76: 4464 add r4, ip - 8000b78: 3802 subs r0, #2 - 8000b7a: e742 b.n 8000a02 <__udivmoddi4+0x156> - -08000b7c <__aeabi_idiv0>: - 8000b7c: 4770 bx lr - 8000b7e: bf00 nop - -08000b80
: -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - 8000b80: b580 push {r7, lr} - 8000b82: b084 sub sp, #16 - 8000b84: af00 add r7, sp, #0 - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - 8000b86: f001 fb75 bl 8002274 - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - 8000b8a: f000 fbf1 bl 8001370 - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - 8000b8e: f000 fc8f bl 80014b0 - MX_SPI3_Init(); - 8000b92: f000 fc57 bl 8001444 - /* USER CODE BEGIN 2 */ - SSD1289_Init(); - 8000b96: f000 ffbb bl 8001b10 - SSD1289_Clear_Screen(); - 8000b9a: f000 ffb1 bl 8001b00 - -// Init_Game(); /*Khoi tao game*/ - - Welcome(); - 8000b9e: f000 f979 bl 8000e94 - - int c = 0; - 8000ba2: 2300 movs r3, #0 - 8000ba4: 60fb str r3, [r7, #12] - int score_old = 0; - 8000ba6: 2300 movs r3, #0 - 8000ba8: 607b str r3, [r7, #4] - int game_over=NO; - 8000baa: 2300 movs r3, #0 - 8000bac: 60bb str r3, [r7, #8] - - while (1) - { - if(!Read_IRQ()){ - 8000bae: f001 fa83 bl 80020b8 - 8000bb2: 4603 mov r3, r0 - 8000bb4: 2b00 cmp r3, #0 - 8000bb6: d1fa bne.n 8000bae - if((game_over==NO)||Button_Press(X_BUT, Y_BUT, BUT_WIDTH, BUT_HEIGH)){ - 8000bb8: 68bb ldr r3, [r7, #8] - 8000bba: 2b00 cmp r3, #0 - 8000bbc: d008 beq.n 8000bd0 - 8000bbe: 2330 movs r3, #48 ; 0x30 - 8000bc0: 2231 movs r2, #49 ; 0x31 - 8000bc2: 2164 movs r1, #100 ; 0x64 - 8000bc4: 208c movs r0, #140 ; 0x8c - 8000bc6: f000 fae9 bl 800119c - 8000bca: 4603 mov r3, r0 - 8000bcc: 2b00 cmp r3, #0 - 8000bce: d0ee beq.n 8000bae - score_old = score; - 8000bd0: 4b92 ldr r3, [pc, #584] ; (8000e1c ) - 8000bd2: 881b ldrh r3, [r3, #0] - 8000bd4: 607b str r3, [r7, #4] - c = 0; - 8000bd6: 2300 movs r3, #0 - 8000bd8: 60fb str r3, [r7, #12] - Init_Game(); - 8000bda: f000 fb29 bl 8001230 - - if(score_old > high_score){ - 8000bde: 4b90 ldr r3, [pc, #576] ; (8000e20 ) - 8000be0: 881b ldrh r3, [r3, #0] - 8000be2: 461a mov r2, r3 - 8000be4: 687b ldr r3, [r7, #4] - 8000be6: 4293 cmp r3, r2 - 8000be8: dd0c ble.n 8000c04 - high_score = score_old; - 8000bea: 687b ldr r3, [r7, #4] - 8000bec: b29a uxth r2, r3 - 8000bee: 4b8c ldr r3, [pc, #560] ; (8000e20 ) - 8000bf0: 801a strh r2, [r3, #0] - Print_Score(high_score, 300, Hscolor); - 8000bf2: 4b8b ldr r3, [pc, #556] ; (8000e20 ) - 8000bf4: 881b ldrh r3, [r3, #0] - 8000bf6: f24f 021f movw r2, #61471 ; 0xf01f - 8000bfa: f44f 7196 mov.w r1, #300 ; 0x12c - 8000bfe: 4618 mov r0, r3 - 8000c00: f000 f9ce bl 8000fa0 - } - while(1){ - if(x1 == 70){ /*Neu ong khoi 1 di qua toa to 110 thi tao ong khoi 2*/ - 8000c04: 4b87 ldr r3, [pc, #540] ; (8000e24 ) - 8000c06: f9b3 3000 ldrsh.w r3, [r3] - 8000c0a: 2b46 cmp r3, #70 ; 0x46 - 8000c0c: d116 bne.n 8000c3c - x2 = 320; - 8000c0e: 4b86 ldr r3, [pc, #536] ; (8000e28 ) - 8000c10: f44f 72a0 mov.w r2, #320 ; 0x140 - 8000c14: 801a strh r2, [r3, #0] - heigh_pill2 = list_heigh[rand()%15]; - 8000c16: f002 ff3f bl 8003a98 - 8000c1a: 4602 mov r2, r0 - 8000c1c: 4b83 ldr r3, [pc, #524] ; (8000e2c ) - 8000c1e: fb83 1302 smull r1, r3, r3, r2 - 8000c22: 4413 add r3, r2 - 8000c24: 10d9 asrs r1, r3, #3 - 8000c26: 17d3 asrs r3, r2, #31 - 8000c28: 1ac9 subs r1, r1, r3 - 8000c2a: 460b mov r3, r1 - 8000c2c: 011b lsls r3, r3, #4 - 8000c2e: 1a5b subs r3, r3, r1 - 8000c30: 1ad1 subs r1, r2, r3 - 8000c32: 4b7f ldr r3, [pc, #508] ; (8000e30 ) - 8000c34: f833 2011 ldrh.w r2, [r3, r1, lsl #1] - 8000c38: 4b7e ldr r3, [pc, #504] ; (8000e34 ) - 8000c3a: 801a strh r2, [r3, #0] - } - if(x2 == 70){ /*Neu ong khoi di qua toa do 110 thi tao them ong khoi*/ - 8000c3c: 4b7a ldr r3, [pc, #488] ; (8000e28 ) - 8000c3e: f9b3 3000 ldrsh.w r3, [r3] - 8000c42: 2b46 cmp r3, #70 ; 0x46 - 8000c44: d116 bne.n 8000c74 - x1 = 320; - 8000c46: 4b77 ldr r3, [pc, #476] ; (8000e24 ) - 8000c48: f44f 72a0 mov.w r2, #320 ; 0x140 - 8000c4c: 801a strh r2, [r3, #0] - heigh_pill1 = list_heigh[rand()%15]; - 8000c4e: f002 ff23 bl 8003a98 - 8000c52: 4602 mov r2, r0 - 8000c54: 4b75 ldr r3, [pc, #468] ; (8000e2c ) - 8000c56: fb83 1302 smull r1, r3, r3, r2 - 8000c5a: 4413 add r3, r2 - 8000c5c: 10d9 asrs r1, r3, #3 - 8000c5e: 17d3 asrs r3, r2, #31 - 8000c60: 1ac9 subs r1, r1, r3 - 8000c62: 460b mov r3, r1 - 8000c64: 011b lsls r3, r3, #4 - 8000c66: 1a5b subs r3, r3, r1 - 8000c68: 1ad1 subs r1, r2, r3 - 8000c6a: 4b71 ldr r3, [pc, #452] ; (8000e30 ) - 8000c6c: f833 2011 ldrh.w r2, [r3, r1, lsl #1] - 8000c70: 4b71 ldr r3, [pc, #452] ; (8000e38 ) - 8000c72: 801a strh r2, [r3, #0] - } - - /*Ve ong khoi*/ - Draw_Pillar(x1, heigh_pill1); - 8000c74: 4b6b ldr r3, [pc, #428] ; (8000e24 ) - 8000c76: f9b3 3000 ldrsh.w r3, [r3] - 8000c7a: 4a6f ldr r2, [pc, #444] ; (8000e38 ) - 8000c7c: 8812 ldrh r2, [r2, #0] - 8000c7e: 4611 mov r1, r2 - 8000c80: 4618 mov r0, r3 - 8000c82: f000 f933 bl 8000eec - Draw_Pillar(x2, heigh_pill2); - 8000c86: 4b68 ldr r3, [pc, #416] ; (8000e28 ) - 8000c88: f9b3 3000 ldrsh.w r3, [r3] - 8000c8c: 4a69 ldr r2, [pc, #420] ; (8000e34 ) - 8000c8e: 8812 ldrh r2, [r2, #0] - 8000c90: 4611 mov r1, r2 - 8000c92: 4618 mov r0, r3 - 8000c94: f000 f92a bl 8000eec - - - if(!Read_IRQ()){ /*Neu co tin hieu cam ung*/ - 8000c98: f001 fa0e bl 80020b8 - 8000c9c: 4603 mov r3, r0 - 8000c9e: 2b00 cmp r3, #0 - 8000ca0: d10b bne.n 8000cba - y_bird -= 5; - 8000ca2: 4b66 ldr r3, [pc, #408] ; (8000e3c ) - 8000ca4: f9b3 3000 ldrsh.w r3, [r3] - 8000ca8: b29b uxth r3, r3 - 8000caa: 3b05 subs r3, #5 - 8000cac: b29b uxth r3, r3 - 8000cae: b21a sxth r2, r3 - 8000cb0: 4b62 ldr r3, [pc, #392] ; (8000e3c ) - 8000cb2: 801a strh r2, [r3, #0] - c = 1; - 8000cb4: 2301 movs r3, #1 - 8000cb6: 60fb str r3, [r7, #12] - 8000cb8: e00b b.n 8000cd2 - } - else if(c){ // Neu chua cham lan nao thi chim van dung yen - 8000cba: 68fb ldr r3, [r7, #12] - 8000cbc: 2b00 cmp r3, #0 - 8000cbe: d008 beq.n 8000cd2 - y_bird += 2; - 8000cc0: 4b5e ldr r3, [pc, #376] ; (8000e3c ) - 8000cc2: f9b3 3000 ldrsh.w r3, [r3] - 8000cc6: b29b uxth r3, r3 - 8000cc8: 3302 adds r3, #2 - 8000cca: b29b uxth r3, r3 - 8000ccc: b21a sxth r2, r3 - 8000cce: 4b5b ldr r3, [pc, #364] ; (8000e3c ) - 8000cd0: 801a strh r2, [r3, #0] - } - - if(x1 > 70){ - 8000cd2: 4b54 ldr r3, [pc, #336] ; (8000e24 ) - 8000cd4: f9b3 3000 ldrsh.w r3, [r3] - 8000cd8: 2b46 cmp r3, #70 ; 0x46 - 8000cda: dd0c ble.n 8000cf6 - x_com = x1; - 8000cdc: 4b51 ldr r3, [pc, #324] ; (8000e24 ) - 8000cde: f9b3 3000 ldrsh.w r3, [r3] - 8000ce2: b29a uxth r2, r3 - 8000ce4: 4b56 ldr r3, [pc, #344] ; (8000e40 ) - 8000ce6: 801a strh r2, [r3, #0] - h_com = heigh_pill1-1; - 8000ce8: 4b53 ldr r3, [pc, #332] ; (8000e38 ) - 8000cea: 881b ldrh r3, [r3, #0] - 8000cec: 3b01 subs r3, #1 - 8000cee: b29a uxth r2, r3 - 8000cf0: 4b54 ldr r3, [pc, #336] ; (8000e44 ) - 8000cf2: 801a strh r2, [r3, #0] - 8000cf4: e00b b.n 8000d0e - } - else{ - x_com = x2; - 8000cf6: 4b4c ldr r3, [pc, #304] ; (8000e28 ) - 8000cf8: f9b3 3000 ldrsh.w r3, [r3] - 8000cfc: b29a uxth r2, r3 - 8000cfe: 4b50 ldr r3, [pc, #320] ; (8000e40 ) - 8000d00: 801a strh r2, [r3, #0] - h_com = heigh_pill2-1; - 8000d02: 4b4c ldr r3, [pc, #304] ; (8000e34 ) - 8000d04: 881b ldrh r3, [r3, #0] - 8000d06: 3b01 subs r3, #1 - 8000d08: b29a uxth r2, r3 - 8000d0a: 4b4e ldr r3, [pc, #312] ; (8000e44 ) - 8000d0c: 801a strh r2, [r3, #0] - } - if(((x_com==X_COM)&&((y_bird<=h_com)||(y_bird+HEIGH_BIRD>=(h_com+DISTANCE))))|| - 8000d0e: 4b4c ldr r3, [pc, #304] ; (8000e40 ) - 8000d10: 881b ldrh r3, [r3, #0] - 8000d12: 2b88 cmp r3, #136 ; 0x88 - 8000d14: d10f bne.n 8000d36 - 8000d16: 4b49 ldr r3, [pc, #292] ; (8000e3c ) - 8000d18: f9b3 3000 ldrsh.w r3, [r3] - 8000d1c: 461a mov r2, r3 - 8000d1e: 4b49 ldr r3, [pc, #292] ; (8000e44 ) - 8000d20: 881b ldrh r3, [r3, #0] - 8000d22: 429a cmp r2, r3 - 8000d24: dd3d ble.n 8000da2 - 8000d26: 4b47 ldr r3, [pc, #284] ; (8000e44 ) - 8000d28: 881b ldrh r3, [r3, #0] - 8000d2a: 3328 adds r3, #40 ; 0x28 - 8000d2c: 4a43 ldr r2, [pc, #268] ; (8000e3c ) - 8000d2e: f9b2 2000 ldrsh.w r2, [r2] - 8000d32: 4293 cmp r3, r2 - 8000d34: db35 blt.n 8000da2 - ((y_bird<=h_com+1)&&( ((X_COM>=x_com)&& - 8000d36: 4b41 ldr r3, [pc, #260] ; (8000e3c ) - 8000d38: f9b3 3000 ldrsh.w r3, [r3] - 8000d3c: 461a mov r2, r3 - 8000d3e: 4b41 ldr r3, [pc, #260] ; (8000e44 ) - 8000d40: 881b ldrh r3, [r3, #0] - 8000d42: 3301 adds r3, #1 - if(((x_com==X_COM)&&((y_bird<=h_com)||(y_bird+HEIGH_BIRD>=(h_com+DISTANCE))))|| - 8000d44: 429a cmp r2, r3 - 8000d46: dc0f bgt.n 8000d68 - ((y_bird<=h_com+1)&&( ((X_COM>=x_com)&& - 8000d48: 4b3d ldr r3, [pc, #244] ; (8000e40 ) - 8000d4a: 881b ldrh r3, [r3, #0] - 8000d4c: 2b88 cmp r3, #136 ; 0x88 - 8000d4e: d803 bhi.n 8000d58 - (X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&&(BIRD_X<=(x_com+WIDTH_PILL)))))|| - 8000d50: 4b3b ldr r3, [pc, #236] ; (8000e40 ) - 8000d52: 881b ldrh r3, [r3, #0] - ((y_bird<=h_com+1)&&( ((X_COM>=x_com)&& - 8000d54: 2b5f cmp r3, #95 ; 0x5f - 8000d56: d824 bhi.n 8000da2 - (X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&&(BIRD_X<=(x_com+WIDTH_PILL)))))|| - 8000d58: 4b39 ldr r3, [pc, #228] ; (8000e40 ) - 8000d5a: 881b ldrh r3, [r3, #0] - 8000d5c: 2b6e cmp r3, #110 ; 0x6e - 8000d5e: d803 bhi.n 8000d68 - 8000d60: 4b37 ldr r3, [pc, #220] ; (8000e40 ) - 8000d62: 881b ldrh r3, [r3, #0] - 8000d64: 2b45 cmp r3, #69 ; 0x45 - 8000d66: d81c bhi.n 8000da2 - (((y_bird+HEIGH_BIRD)>=(h_com+DISTANCE))&& - 8000d68: 4b36 ldr r3, [pc, #216] ; (8000e44 ) - 8000d6a: 881b ldrh r3, [r3, #0] - 8000d6c: 3328 adds r3, #40 ; 0x28 - 8000d6e: 4a33 ldr r2, [pc, #204] ; (8000e3c ) - 8000d70: f9b2 2000 ldrsh.w r2, [r2] - (X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&&(BIRD_X<=(x_com+WIDTH_PILL)))))|| - 8000d74: 4293 cmp r3, r2 - 8000d76: da0f bge.n 8000d98 - (((X_COM>=x_com)&&(X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&& - 8000d78: 4b31 ldr r3, [pc, #196] ; (8000e40 ) - 8000d7a: 881b ldrh r3, [r3, #0] - (((y_bird+HEIGH_BIRD)>=(h_com+DISTANCE))&& - 8000d7c: 2b88 cmp r3, #136 ; 0x88 - 8000d7e: d803 bhi.n 8000d88 - (((X_COM>=x_com)&&(X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&& - 8000d80: 4b2f ldr r3, [pc, #188] ; (8000e40 ) - 8000d82: 881b ldrh r3, [r3, #0] - 8000d84: 2b5f cmp r3, #95 ; 0x5f - 8000d86: d80c bhi.n 8000da2 - 8000d88: 4b2d ldr r3, [pc, #180] ; (8000e40 ) - 8000d8a: 881b ldrh r3, [r3, #0] - 8000d8c: 2b6e cmp r3, #110 ; 0x6e - 8000d8e: d803 bhi.n 8000d98 - (BIRD_X<=(x_com+WIDTH_PILL)))))|| - 8000d90: 4b2b ldr r3, [pc, #172] ; (8000e40 ) - 8000d92: 881b ldrh r3, [r3, #0] - (((X_COM>=x_com)&&(X_COM <= (x_com+WIDTH_PILL)))||((BIRD_X>=x_com)&& - 8000d94: 2b45 cmp r3, #69 ; 0x45 - 8000d96: d804 bhi.n 8000da2 - ((y_bird+HEIGH_BIRD)>=HEIGH_SCREEN)){ - 8000d98: 4b28 ldr r3, [pc, #160] ; (8000e3c ) - 8000d9a: f9b3 3000 ldrsh.w r3, [r3] - (BIRD_X<=(x_com+WIDTH_PILL)))))|| - 8000d9e: 2bc3 cmp r3, #195 ; 0xc3 - 8000da0: dd04 ble.n 8000dac - - game_over = YES; - 8000da2: 2301 movs r3, #1 - 8000da4: 60bb str r3, [r7, #8] - Game_Over(); - 8000da6: f000 f963 bl 8001070 - break; - 8000daa: e036 b.n 8000e1a - } - - if(x1 == SCORED || x2 == SCORED){ - 8000dac: 4b1d ldr r3, [pc, #116] ; (8000e24 ) - 8000dae: f9b3 3000 ldrsh.w r3, [r3] - 8000db2: 2b45 cmp r3, #69 ; 0x45 - 8000db4: d004 beq.n 8000dc0 - 8000db6: 4b1c ldr r3, [pc, #112] ; (8000e28 ) - 8000db8: f9b3 3000 ldrsh.w r3, [r3] - 8000dbc: 2b45 cmp r3, #69 ; 0x45 - 8000dbe: d10c bne.n 8000dda - score += 1; - 8000dc0: 4b16 ldr r3, [pc, #88] ; (8000e1c ) - 8000dc2: 881b ldrh r3, [r3, #0] - 8000dc4: 3301 adds r3, #1 - 8000dc6: b29a uxth r2, r3 - 8000dc8: 4b14 ldr r3, [pc, #80] ; (8000e1c ) - 8000dca: 801a strh r2, [r3, #0] - Print_Score(score, X_SCORE, Blue); - 8000dcc: 4b13 ldr r3, [pc, #76] ; (8000e1c ) - 8000dce: 881b ldrh r3, [r3, #0] - 8000dd0: 221f movs r2, #31 - 8000dd2: 214b movs r1, #75 ; 0x4b - 8000dd4: 4618 mov r0, r3 - 8000dd6: f000 f8e3 bl 8000fa0 - } - - if(c){ - 8000dda: 68fb ldr r3, [r7, #12] - 8000ddc: 2b00 cmp r3, #0 - 8000dde: d018 beq.n 8000e12 - Bird_Fly(y_bird); - 8000de0: 4b16 ldr r3, [pc, #88] ; (8000e3c ) - 8000de2: f9b3 3000 ldrsh.w r3, [r3] - 8000de6: b29b uxth r3, r3 - 8000de8: 4618 mov r0, r3 - 8000dea: f000 f8b5 bl 8000f58 - x1--; - 8000dee: 4b0d ldr r3, [pc, #52] ; (8000e24 ) - 8000df0: f9b3 3000 ldrsh.w r3, [r3] - 8000df4: b29b uxth r3, r3 - 8000df6: 3b01 subs r3, #1 - 8000df8: b29b uxth r3, r3 - 8000dfa: b21a sxth r2, r3 - 8000dfc: 4b09 ldr r3, [pc, #36] ; (8000e24 ) - 8000dfe: 801a strh r2, [r3, #0] - x2--; - 8000e00: 4b09 ldr r3, [pc, #36] ; (8000e28 ) - 8000e02: f9b3 3000 ldrsh.w r3, [r3] - 8000e06: b29b uxth r3, r3 - 8000e08: 3b01 subs r3, #1 - 8000e0a: b29b uxth r3, r3 - 8000e0c: b21a sxth r2, r3 - 8000e0e: 4b06 ldr r3, [pc, #24] ; (8000e28 ) - 8000e10: 801a strh r2, [r3, #0] - } - HAL_Delay(10); - 8000e12: 200a movs r0, #10 - 8000e14: f001 faa0 bl 8002358 - if(x1 == 70){ /*Neu ong khoi 1 di qua toa to 110 thi tao ong khoi 2*/ - 8000e18: e6f4 b.n 8000c04 - if(!Read_IRQ()){ - 8000e1a: e6c8 b.n 8000bae - 8000e1c: 2000277e .word 0x2000277e - 8000e20: 20002780 .word 0x20002780 - 8000e24: 20002782 .word 0x20002782 - 8000e28: 20002784 .word 0x20002784 - 8000e2c: 88888889 .word 0x88888889 - 8000e30: 20002760 .word 0x20002760 - 8000e34: 20002788 .word 0x20002788 - 8000e38: 20002786 .word 0x20002786 - 8000e3c: 2000278a .word 0x2000278a - 8000e40: 2000278c .word 0x2000278c - 8000e44: 2000278e .word 0x2000278e - -08000e48 : - } - } - -} - -void Init_Heigh_Pill(){ - 8000e48: b480 push {r7} - 8000e4a: b083 sub sp, #12 - 8000e4c: af00 add r7, sp, #0 - int i =0; - 8000e4e: 2300 movs r3, #0 - 8000e50: 607b str r3, [r7, #4] - int value = 0; - 8000e52: 2300 movs r3, #0 - 8000e54: 603b str r3, [r7, #0] - for(i=0; i<15; i++){ - 8000e56: 2300 movs r3, #0 - 8000e58: 607b str r3, [r7, #4] - 8000e5a: e00e b.n 8000e7a - list_heigh[i] = 150-value; - 8000e5c: 683b ldr r3, [r7, #0] - 8000e5e: b29b uxth r3, r3 - 8000e60: f1c3 0396 rsb r3, r3, #150 ; 0x96 - 8000e64: b299 uxth r1, r3 - 8000e66: 4a0a ldr r2, [pc, #40] ; (8000e90 ) - 8000e68: 687b ldr r3, [r7, #4] - 8000e6a: f822 1013 strh.w r1, [r2, r3, lsl #1] - value += 10; - 8000e6e: 683b ldr r3, [r7, #0] - 8000e70: 330a adds r3, #10 - 8000e72: 603b str r3, [r7, #0] - for(i=0; i<15; i++){ - 8000e74: 687b ldr r3, [r7, #4] - 8000e76: 3301 adds r3, #1 - 8000e78: 607b str r3, [r7, #4] - 8000e7a: 687b ldr r3, [r7, #4] - 8000e7c: 2b0e cmp r3, #14 - 8000e7e: dded ble.n 8000e5c - } - -} - 8000e80: bf00 nop - 8000e82: bf00 nop - 8000e84: 370c adds r7, #12 - 8000e86: 46bd mov sp, r7 - 8000e88: f85d 7b04 ldr.w r7, [sp], #4 - 8000e8c: 4770 bx lr - 8000e8e: bf00 nop - 8000e90: 20002760 .word 0x20002760 - -08000e94 : - -void Welcome(){ - 8000e94: b580 push {r7, lr} - 8000e96: b084 sub sp, #16 - 8000e98: af04 add r7, sp, #16 - SSD1289_Write_Back_Ground(Black); - 8000e9a: 2000 movs r0, #0 - 8000e9c: f000 fe09 bl 8001ab2 - SSD1289_Print_String(50, 40, 2, 1, 4, White, Black, "Flapy Bird"); - 8000ea0: 4b10 ldr r3, [pc, #64] ; (8000ee4 ) - 8000ea2: 9303 str r3, [sp, #12] - 8000ea4: 2300 movs r3, #0 - 8000ea6: 9302 str r3, [sp, #8] - 8000ea8: f64f 73ff movw r3, #65535 ; 0xffff - 8000eac: 9301 str r3, [sp, #4] - 8000eae: 2304 movs r3, #4 - 8000eb0: 9300 str r3, [sp, #0] - 8000eb2: 2301 movs r3, #1 - 8000eb4: 2202 movs r2, #2 - 8000eb6: 2128 movs r1, #40 ; 0x28 - 8000eb8: 2032 movs r0, #50 ; 0x32 - 8000eba: f000 fd83 bl 80019c4 - SSD1289_Print_String(40, 185, 1, 1, 2, White, Black, "Click to enter the game!"); - 8000ebe: 4b0a ldr r3, [pc, #40] ; (8000ee8 ) - 8000ec0: 9303 str r3, [sp, #12] - 8000ec2: 2300 movs r3, #0 - 8000ec4: 9302 str r3, [sp, #8] - 8000ec6: f64f 73ff movw r3, #65535 ; 0xffff - 8000eca: 9301 str r3, [sp, #4] - 8000ecc: 2302 movs r3, #2 - 8000ece: 9300 str r3, [sp, #0] - 8000ed0: 2301 movs r3, #1 - 8000ed2: 2201 movs r2, #1 - 8000ed4: 21b9 movs r1, #185 ; 0xb9 - 8000ed6: 2028 movs r0, #40 ; 0x28 - 8000ed8: f000 fd74 bl 80019c4 -} - 8000edc: bf00 nop - 8000ede: 46bd mov sp, r7 - 8000ee0: bd80 pop {r7, pc} - 8000ee2: bf00 nop - 8000ee4: 08004b20 .word 0x08004b20 - 8000ee8: 08004b2c .word 0x08004b2c - -08000eec : -void Draw_Pillar(int16_t x, uint16_t heigh){ - 8000eec: b580 push {r7, lr} - 8000eee: b084 sub sp, #16 - 8000ef0: af00 add r7, sp, #0 - 8000ef2: 4603 mov r3, r0 - 8000ef4: 460a mov r2, r1 - 8000ef6: 80fb strh r3, [r7, #6] - 8000ef8: 4613 mov r3, r2 - 8000efa: 80bb strh r3, [r7, #4] - if(x < 321){ - 8000efc: f9b7 3006 ldrsh.w r3, [r7, #6] - 8000f00: f5b3 7fa0 cmp.w r3, #320 ; 0x140 - 8000f04: dc23 bgt.n 8000f4e - /*Xoa ong khoi cu*/ - int16_t x1 = x+WIDTH_PILL+1; - 8000f06: 88fb ldrh r3, [r7, #6] - 8000f08: 3329 adds r3, #41 ; 0x29 - 8000f0a: b29b uxth r3, r3 - 8000f0c: 81fb strh r3, [r7, #14] - - SSD1289_Draw_V_Line(x1, 1, heigh, Background); /*Xoa ong khoi top*/ - 8000f0e: 89f8 ldrh r0, [r7, #14] - 8000f10: 88ba ldrh r2, [r7, #4] - 8000f12: f24c 73ff movw r3, #51199 ; 0xc7ff - 8000f16: 2101 movs r1, #1 - 8000f18: f000 fd9e bl 8001a58 - SSD1289_Draw_V_Line(x1, 1+heigh+DISTANCE, HEIGH_SCREEN, Background); /*Xoa ong khoi bot*/ - 8000f1c: 89f8 ldrh r0, [r7, #14] - 8000f1e: 88bb ldrh r3, [r7, #4] - 8000f20: 333d adds r3, #61 ; 0x3d - 8000f22: b299 uxth r1, r3 - 8000f24: f24c 73ff movw r3, #51199 ; 0xc7ff - 8000f28: 22d7 movs r2, #215 ; 0xd7 - 8000f2a: f000 fd95 bl 8001a58 - - /*Ve ong khoi moi*/ - SSD1289_Draw_V_Line(x, 1, heigh, Green); - 8000f2e: 88f8 ldrh r0, [r7, #6] - 8000f30: 88ba ldrh r2, [r7, #4] - 8000f32: f44f 63fc mov.w r3, #2016 ; 0x7e0 - 8000f36: 2101 movs r1, #1 - 8000f38: f000 fd8e bl 8001a58 - SSD1289_Draw_V_Line(x, 1+heigh+DISTANCE, HEIGH_SCREEN, Green); - 8000f3c: 88f8 ldrh r0, [r7, #6] - 8000f3e: 88bb ldrh r3, [r7, #4] - 8000f40: 333d adds r3, #61 ; 0x3d - 8000f42: b299 uxth r1, r3 - 8000f44: f44f 63fc mov.w r3, #2016 ; 0x7e0 - 8000f48: 22d7 movs r2, #215 ; 0xd7 - 8000f4a: f000 fd85 bl 8001a58 - } -} - 8000f4e: bf00 nop - 8000f50: 3710 adds r7, #16 - 8000f52: 46bd mov sp, r7 - 8000f54: bd80 pop {r7, pc} - ... - -08000f58 : - - -void Bird_Fly(uint16_t y){ - 8000f58: b580 push {r7, lr} - 8000f5a: b084 sub sp, #16 - 8000f5c: af02 add r7, sp, #8 - 8000f5e: 4603 mov r3, r0 - 8000f60: 80fb strh r3, [r7, #6] - SSD1289_Fill_Color(BIRD_X, y-3, (BIRD_X+WIDTH_BIRD+5), (y+HEIGH_BIRD+5), Background); - 8000f62: 88fb ldrh r3, [r7, #6] - 8000f64: 3b03 subs r3, #3 - 8000f66: b299 uxth r1, r3 - 8000f68: 88fb ldrh r3, [r7, #6] - 8000f6a: 3318 adds r3, #24 - 8000f6c: b29b uxth r3, r3 - 8000f6e: f24c 72ff movw r2, #51199 ; 0xc7ff - 8000f72: 9200 str r2, [sp, #0] - 8000f74: 228d movs r2, #141 ; 0x8d - 8000f76: 206e movs r0, #110 ; 0x6e - 8000f78: f000 fc2e bl 80017d8 - HAL_Delay(5); - 8000f7c: 2005 movs r0, #5 - 8000f7e: f001 f9eb bl 8002358 - SSD1289_Write_Pic_Coor(BIRD_X, y, WIDTH_BIRD, HEIGH_BIRD, bird_image); - 8000f82: 88f9 ldrh r1, [r7, #6] - 8000f84: 4b05 ldr r3, [pc, #20] ; (8000f9c ) - 8000f86: 9300 str r3, [sp, #0] - 8000f88: 2313 movs r3, #19 - 8000f8a: 221a movs r2, #26 - 8000f8c: 206e movs r0, #110 ; 0x6e - 8000f8e: f000 fc55 bl 800183c -} - 8000f92: bf00 nop - 8000f94: 3708 adds r7, #8 - 8000f96: 46bd mov sp, r7 - 8000f98: bd80 pop {r7, pc} - 8000f9a: bf00 nop - 8000f9c: 20000000 .word 0x20000000 - -08000fa0 : - -void Print_Score(uint16_t val, uint16_t x_score, uint16_t color){ - 8000fa0: b580 push {r7, lr} - 8000fa2: b088 sub sp, #32 - 8000fa4: af04 add r7, sp, #16 - 8000fa6: 4603 mov r3, r0 - 8000fa8: 80fb strh r3, [r7, #6] - 8000faa: 460b mov r3, r1 - 8000fac: 80bb strh r3, [r7, #4] - 8000fae: 4613 mov r3, r2 - 8000fb0: 807b strh r3, [r7, #2] - uint16_t a = 0, b = 0; - 8000fb2: 2300 movs r3, #0 - 8000fb4: 81fb strh r3, [r7, #14] - 8000fb6: 2300 movs r3, #0 - 8000fb8: 81bb strh r3, [r7, #12] - char string[3] = {0, 0, '\0'}; - 8000fba: 4a2b ldr r2, [pc, #172] ; (8001068 ) - 8000fbc: f107 0308 add.w r3, r7, #8 - 8000fc0: 6812 ldr r2, [r2, #0] - 8000fc2: 4611 mov r1, r2 - 8000fc4: 8019 strh r1, [r3, #0] - 8000fc6: 3302 adds r3, #2 - 8000fc8: 0c12 lsrs r2, r2, #16 - 8000fca: 701a strb r2, [r3, #0] - /*Xoa diem cu*/ - SSD1289_Fill_Color(x_score, Y_SCORE, x_score+20, 239, Yellow); - 8000fcc: 88bb ldrh r3, [r7, #4] - 8000fce: 3314 adds r3, #20 - 8000fd0: b29a uxth r2, r3 - 8000fd2: 88b8 ldrh r0, [r7, #4] - 8000fd4: f64f 73e0 movw r3, #65504 ; 0xffe0 - 8000fd8: 9300 str r3, [sp, #0] - 8000fda: 23ef movs r3, #239 ; 0xef - 8000fdc: 21df movs r1, #223 ; 0xdf - 8000fde: f000 fbfb bl 80017d8 - if(val < 10){ - 8000fe2: 88fb ldrh r3, [r7, #6] - 8000fe4: 2b09 cmp r3, #9 - 8000fe6: d80f bhi.n 8001008 - SSD1289_Print_Char(x_score, Y_SCORE, 2, color, Yellow, (val+48)); - 8000fe8: 88fb ldrh r3, [r7, #6] - 8000fea: b2db uxtb r3, r3 - 8000fec: 3330 adds r3, #48 ; 0x30 - 8000fee: b2db uxtb r3, r3 - 8000ff0: 887a ldrh r2, [r7, #2] - 8000ff2: 88b8 ldrh r0, [r7, #4] - 8000ff4: 9301 str r3, [sp, #4] - 8000ff6: f64f 73e0 movw r3, #65504 ; 0xffe0 - 8000ffa: 9300 str r3, [sp, #0] - 8000ffc: 4613 mov r3, r2 - 8000ffe: 2202 movs r2, #2 - 8001000: 21df movs r1, #223 ; 0xdf - 8001002: f000 fc5d bl 80018c0 - string[0] = b; - string[1] = a; - SSD1289_Print_String(x_score, Y_SCORE, 1, 1, 2, color, Yellow, string); - } - -} - 8001006: e02a b.n 800105e - a = val%10 + 48; /*Hang don vi*/ - 8001008: 88fa ldrh r2, [r7, #6] - 800100a: 4b18 ldr r3, [pc, #96] ; (800106c ) - 800100c: fba3 1302 umull r1, r3, r3, r2 - 8001010: 08d9 lsrs r1, r3, #3 - 8001012: 460b mov r3, r1 - 8001014: 009b lsls r3, r3, #2 - 8001016: 440b add r3, r1 - 8001018: 005b lsls r3, r3, #1 - 800101a: 1ad3 subs r3, r2, r3 - 800101c: b29b uxth r3, r3 - 800101e: 3330 adds r3, #48 ; 0x30 - 8001020: 81fb strh r3, [r7, #14] - b = val/10 + 48; /*Hang chuc*/ - 8001022: 88fb ldrh r3, [r7, #6] - 8001024: 4a11 ldr r2, [pc, #68] ; (800106c ) - 8001026: fba2 2303 umull r2, r3, r2, r3 - 800102a: 08db lsrs r3, r3, #3 - 800102c: b29b uxth r3, r3 - 800102e: 3330 adds r3, #48 ; 0x30 - 8001030: 81bb strh r3, [r7, #12] - string[0] = b; - 8001032: 89bb ldrh r3, [r7, #12] - 8001034: b2db uxtb r3, r3 - 8001036: 723b strb r3, [r7, #8] - string[1] = a; - 8001038: 89fb ldrh r3, [r7, #14] - 800103a: b2db uxtb r3, r3 - 800103c: 727b strb r3, [r7, #9] - SSD1289_Print_String(x_score, Y_SCORE, 1, 1, 2, color, Yellow, string); - 800103e: 88b8 ldrh r0, [r7, #4] - 8001040: f107 0308 add.w r3, r7, #8 - 8001044: 9303 str r3, [sp, #12] - 8001046: f64f 73e0 movw r3, #65504 ; 0xffe0 - 800104a: 9302 str r3, [sp, #8] - 800104c: 887b ldrh r3, [r7, #2] - 800104e: 9301 str r3, [sp, #4] - 8001050: 2302 movs r3, #2 - 8001052: 9300 str r3, [sp, #0] - 8001054: 2301 movs r3, #1 - 8001056: 2201 movs r2, #1 - 8001058: 21df movs r1, #223 ; 0xdf - 800105a: f000 fcb3 bl 80019c4 -} - 800105e: bf00 nop - 8001060: 3710 adds r7, #16 - 8001062: 46bd mov sp, r7 - 8001064: bd80 pop {r7, pc} - 8001066: bf00 nop - 8001068: 08004b48 .word 0x08004b48 - 800106c: cccccccd .word 0xcccccccd - -08001070 : - -void Game_Over(){ - 8001070: b580 push {r7, lr} - 8001072: b086 sub sp, #24 - 8001074: af04 add r7, sp, #16 - - SSD1289_Fill_Color(X_GAME_OVER-40, Y_GAME_OVER-10, X_GAME_OVER+120, Y_GAME_OVER+70, Background); - 8001076: f24c 73ff movw r3, #51199 ; 0xc7ff - 800107a: 9300 str r3, [sp, #0] - 800107c: 236e movs r3, #110 ; 0x6e - 800107e: 22d2 movs r2, #210 ; 0xd2 - 8001080: 211e movs r1, #30 - 8001082: 2032 movs r0, #50 ; 0x32 - 8001084: f000 fba8 bl 80017d8 - SSD1289_Print_String(X_GAME_OVER, Y_GAME_OVER, 2, 2, 3, Red, Background, "Game Over"); - 8001088: 4b3e ldr r3, [pc, #248] ; (8001184 ) - 800108a: 9303 str r3, [sp, #12] - 800108c: f24c 73ff movw r3, #51199 ; 0xc7ff - 8001090: 9302 str r3, [sp, #8] - 8001092: f44f 4378 mov.w r3, #63488 ; 0xf800 - 8001096: 9301 str r3, [sp, #4] - 8001098: 2303 movs r3, #3 - 800109a: 9300 str r3, [sp, #0] - 800109c: 2302 movs r3, #2 - 800109e: 2202 movs r2, #2 - 80010a0: 2128 movs r1, #40 ; 0x28 - 80010a2: 205a movs r0, #90 ; 0x5a - 80010a4: f000 fc8e bl 80019c4 - SSD1289_Print_String(X_GAME_SCORE, Y_GAME_SCORE, 2, 2, 2, Red, Background, "Score: "); - 80010a8: 4b37 ldr r3, [pc, #220] ; (8001188 ) - 80010aa: 9303 str r3, [sp, #12] - 80010ac: f24c 73ff movw r3, #51199 ; 0xc7ff - 80010b0: 9302 str r3, [sp, #8] - 80010b2: f44f 4378 mov.w r3, #63488 ; 0xf800 - 80010b6: 9301 str r3, [sp, #4] - 80010b8: 2302 movs r3, #2 - 80010ba: 9300 str r3, [sp, #0] - 80010bc: 2302 movs r3, #2 - 80010be: 2202 movs r2, #2 - 80010c0: 2146 movs r1, #70 ; 0x46 - 80010c2: 205f movs r0, #95 ; 0x5f - 80010c4: f000 fc7e bl 80019c4 - uint16_t a = 0, b = 0; - 80010c8: 2300 movs r3, #0 - 80010ca: 80fb strh r3, [r7, #6] - 80010cc: 2300 movs r3, #0 - 80010ce: 80bb strh r3, [r7, #4] - char string[3] = {0, 0, '\0'}; - 80010d0: 4a2e ldr r2, [pc, #184] ; (800118c ) - 80010d2: 463b mov r3, r7 - 80010d4: 6812 ldr r2, [r2, #0] - 80010d6: 4611 mov r1, r2 - 80010d8: 8019 strh r1, [r3, #0] - 80010da: 3302 adds r3, #2 - 80010dc: 0c12 lsrs r2, r2, #16 - 80010de: 701a strb r2, [r3, #0] - if(score < 10){ - 80010e0: 4b2b ldr r3, [pc, #172] ; (8001190 ) - 80010e2: 881b ldrh r3, [r3, #0] - 80010e4: 2b09 cmp r3, #9 - 80010e6: d810 bhi.n 800110a - SSD1289_Print_Char(X_SOCRE_END, Y_GAME_SCORE, 2, Red, Background, (score+48)); - 80010e8: 4b29 ldr r3, [pc, #164] ; (8001190 ) - 80010ea: 881b ldrh r3, [r3, #0] - 80010ec: b2db uxtb r3, r3 - 80010ee: 3330 adds r3, #48 ; 0x30 - 80010f0: b2db uxtb r3, r3 - 80010f2: 9301 str r3, [sp, #4] - 80010f4: f24c 73ff movw r3, #51199 ; 0xc7ff - 80010f8: 9300 str r3, [sp, #0] - 80010fa: f44f 4378 mov.w r3, #63488 ; 0xf800 - 80010fe: 2202 movs r2, #2 - 8001100: 2146 movs r1, #70 ; 0x46 - 8001102: 20a5 movs r0, #165 ; 0xa5 - 8001104: f000 fbdc bl 80018c0 - 8001108: e02c b.n 8001164 - } - else{ - a = score%10 + 48; /*Hang don vi*/ - 800110a: 4b21 ldr r3, [pc, #132] ; (8001190 ) - 800110c: 881a ldrh r2, [r3, #0] - 800110e: 4b21 ldr r3, [pc, #132] ; (8001194 ) - 8001110: fba3 1302 umull r1, r3, r3, r2 - 8001114: 08d9 lsrs r1, r3, #3 - 8001116: 460b mov r3, r1 - 8001118: 009b lsls r3, r3, #2 - 800111a: 440b add r3, r1 - 800111c: 005b lsls r3, r3, #1 - 800111e: 1ad3 subs r3, r2, r3 - 8001120: b29b uxth r3, r3 - 8001122: 3330 adds r3, #48 ; 0x30 - 8001124: 80fb strh r3, [r7, #6] - b = score/10 + 48; /*Hang chuc*/ - 8001126: 4b1a ldr r3, [pc, #104] ; (8001190 ) - 8001128: 881b ldrh r3, [r3, #0] - 800112a: 4a1a ldr r2, [pc, #104] ; (8001194 ) - 800112c: fba2 2303 umull r2, r3, r2, r3 - 8001130: 08db lsrs r3, r3, #3 - 8001132: b29b uxth r3, r3 - 8001134: 3330 adds r3, #48 ; 0x30 - 8001136: 80bb strh r3, [r7, #4] - string[0] = b; - 8001138: 88bb ldrh r3, [r7, #4] - 800113a: b2db uxtb r3, r3 - 800113c: 703b strb r3, [r7, #0] - string[1] = a; - 800113e: 88fb ldrh r3, [r7, #6] - 8001140: b2db uxtb r3, r3 - 8001142: 707b strb r3, [r7, #1] - SSD1289_Print_String(X_SOCRE_END, Y_GAME_SCORE, 2, 2, 2, Red, Background, string); - 8001144: 463b mov r3, r7 - 8001146: 9303 str r3, [sp, #12] - 8001148: f24c 73ff movw r3, #51199 ; 0xc7ff - 800114c: 9302 str r3, [sp, #8] - 800114e: f44f 4378 mov.w r3, #63488 ; 0xf800 - 8001152: 9301 str r3, [sp, #4] - 8001154: 2302 movs r3, #2 - 8001156: 9300 str r3, [sp, #0] - 8001158: 2302 movs r3, #2 - 800115a: 2202 movs r2, #2 - 800115c: 2146 movs r1, #70 ; 0x46 - 800115e: 20a5 movs r0, #165 ; 0xa5 - 8001160: f000 fc30 bl 80019c4 - } - - HAL_Delay(1500); - 8001164: f240 50dc movw r0, #1500 ; 0x5dc - 8001168: f001 f8f6 bl 8002358 - SSD1289_Write_Pic_Coor(X_BUT, Y_BUT, BUT_WIDTH, BUT_HEIGH, button); - 800116c: 4b0a ldr r3, [pc, #40] ; (8001198 ) - 800116e: 9300 str r3, [sp, #0] - 8001170: 2330 movs r3, #48 ; 0x30 - 8001172: 2231 movs r2, #49 ; 0x31 - 8001174: 2164 movs r1, #100 ; 0x64 - 8001176: 208c movs r0, #140 ; 0x8c - 8001178: f000 fb60 bl 800183c -} - 800117c: bf00 nop - 800117e: 3708 adds r7, #8 - 8001180: 46bd mov sp, r7 - 8001182: bd80 pop {r7, pc} - 8001184: 08004b4c .word 0x08004b4c - 8001188: 08004b58 .word 0x08004b58 - 800118c: 08004b48 .word 0x08004b48 - 8001190: 2000277e .word 0x2000277e - 8001194: cccccccd .word 0xcccccccd - 8001198: 2000105c .word 0x2000105c - -0800119c : - -int Button_Press(uint16_t x, uint16_t y, uint16_t width, uint16_t heigh){ - 800119c: b590 push {r4, r7, lr} - 800119e: b085 sub sp, #20 - 80011a0: af00 add r7, sp, #0 - 80011a2: 4604 mov r4, r0 - 80011a4: 4608 mov r0, r1 - 80011a6: 4611 mov r1, r2 - 80011a8: 461a mov r2, r3 - 80011aa: 4623 mov r3, r4 - 80011ac: 80fb strh r3, [r7, #6] - 80011ae: 4603 mov r3, r0 - 80011b0: 80bb strh r3, [r7, #4] - 80011b2: 460b mov r3, r1 - 80011b4: 807b strh r3, [r7, #2] - 80011b6: 4613 mov r3, r2 - 80011b8: 803b strh r3, [r7, #0] - uint16_t lcd_x = 0, lcd_y = 0; - 80011ba: 2300 movs r3, #0 - 80011bc: 81fb strh r3, [r7, #14] - 80011be: 2300 movs r3, #0 - 80011c0: 81bb strh r3, [r7, #12] - if(!Read_IRQ()){ - 80011c2: f000 ff79 bl 80020b8 - 80011c6: 4603 mov r3, r0 - 80011c8: 2b00 cmp r3, #0 - 80011ca: d12b bne.n 8001224 - lcd_x = XPT2046_Calibrate(XPT2046_Read(cmd_X), 1); - 80011cc: 2090 movs r0, #144 ; 0x90 - 80011ce: f000 ff7f bl 80020d0 - 80011d2: 4603 mov r3, r0 - 80011d4: 2101 movs r1, #1 - 80011d6: 4618 mov r0, r3 - 80011d8: f000 ffca bl 8002170 - 80011dc: 4603 mov r3, r0 - 80011de: 81fb strh r3, [r7, #14] - lcd_y = XPT2046_Calibrate(XPT2046_Read(cmd_Y), 0); - 80011e0: 20d0 movs r0, #208 ; 0xd0 - 80011e2: f000 ff75 bl 80020d0 - 80011e6: 4603 mov r3, r0 - 80011e8: 2100 movs r1, #0 - 80011ea: 4618 mov r0, r3 - 80011ec: f000 ffc0 bl 8002170 - 80011f0: 4603 mov r3, r0 - 80011f2: 81bb strh r3, [r7, #12] - - if(((lcd_x>x)&&(lcd_x<(x+width)))&&((lcd_y>y)&&(lcd_y<(y+heigh)))) - 80011f4: 89fa ldrh r2, [r7, #14] - 80011f6: 88fb ldrh r3, [r7, #6] - 80011f8: 429a cmp r2, r3 - 80011fa: d911 bls.n 8001220 - 80011fc: 89fa ldrh r2, [r7, #14] - 80011fe: 88f9 ldrh r1, [r7, #6] - 8001200: 887b ldrh r3, [r7, #2] - 8001202: 440b add r3, r1 - 8001204: 429a cmp r2, r3 - 8001206: da0b bge.n 8001220 - 8001208: 89ba ldrh r2, [r7, #12] - 800120a: 88bb ldrh r3, [r7, #4] - 800120c: 429a cmp r2, r3 - 800120e: d907 bls.n 8001220 - 8001210: 89ba ldrh r2, [r7, #12] - 8001212: 88b9 ldrh r1, [r7, #4] - 8001214: 883b ldrh r3, [r7, #0] - 8001216: 440b add r3, r1 - 8001218: 429a cmp r2, r3 - 800121a: da01 bge.n 8001220 - return YES; - 800121c: 2301 movs r3, #1 - 800121e: e002 b.n 8001226 - else - return NO; - 8001220: 2300 movs r3, #0 - 8001222: e000 b.n 8001226 - } - return NO; - 8001224: 2300 movs r3, #0 -} - 8001226: 4618 mov r0, r3 - 8001228: 3714 adds r7, #20 - 800122a: 46bd mov sp, r7 - 800122c: bd90 pop {r4, r7, pc} - ... - -08001230 : - -void Init_Game(){ - 8001230: b580 push {r7, lr} - 8001232: b084 sub sp, #16 - 8001234: af04 add r7, sp, #16 - Init_Heigh_Pill(); - 8001236: f7ff fe07 bl 8000e48 - score = 0; - 800123a: 4b3e ldr r3, [pc, #248] ; (8001334 ) - 800123c: 2200 movs r2, #0 - 800123e: 801a strh r2, [r3, #0] - x1 = 320; - 8001240: 4b3d ldr r3, [pc, #244] ; (8001338 ) - 8001242: f44f 72a0 mov.w r2, #320 ; 0x140 - 8001246: 801a strh r2, [r3, #0] - x2 = 600; /*Toa do x cua 2 ong khoi xuat hien tren man hinh*/ - 8001248: 4b3c ldr r3, [pc, #240] ; (800133c ) - 800124a: f44f 7216 mov.w r2, #600 ; 0x258 - 800124e: 801a strh r2, [r3, #0] - heigh_pill1 = list_heigh[rand()%15]; /*Chieu cao ong khoi khi bat day game*/ - 8001250: f002 fc22 bl 8003a98 - 8001254: 4602 mov r2, r0 - 8001256: 4b3a ldr r3, [pc, #232] ; (8001340 ) - 8001258: fb83 1302 smull r1, r3, r3, r2 - 800125c: 4413 add r3, r2 - 800125e: 10d9 asrs r1, r3, #3 - 8001260: 17d3 asrs r3, r2, #31 - 8001262: 1ac9 subs r1, r1, r3 - 8001264: 460b mov r3, r1 - 8001266: 011b lsls r3, r3, #4 - 8001268: 1a5b subs r3, r3, r1 - 800126a: 1ad1 subs r1, r2, r3 - 800126c: 4b35 ldr r3, [pc, #212] ; (8001344 ) - 800126e: f833 2011 ldrh.w r2, [r3, r1, lsl #1] - 8001272: 4b35 ldr r3, [pc, #212] ; (8001348 ) - 8001274: 801a strh r2, [r3, #0] - heigh_pill2 = 100; - 8001276: 4b35 ldr r3, [pc, #212] ; (800134c ) - 8001278: 2264 movs r2, #100 ; 0x64 - 800127a: 801a strh r2, [r3, #0] - y_bird = BIRD_Y; - 800127c: 4b34 ldr r3, [pc, #208] ; (8001350 ) - 800127e: 2264 movs r2, #100 ; 0x64 - 8001280: 801a strh r2, [r3, #0] - x_com = 320; - 8001282: 4b34 ldr r3, [pc, #208] ; (8001354 ) - 8001284: f44f 72a0 mov.w r2, #320 ; 0x140 - 8001288: 801a strh r2, [r3, #0] - h_com = heigh_pill1; - 800128a: 4b2f ldr r3, [pc, #188] ; (8001348 ) - 800128c: 881a ldrh r2, [r3, #0] - 800128e: 4b32 ldr r3, [pc, #200] ; (8001358 ) - 8001290: 801a strh r2, [r3, #0] - SSD1289_Write_Back_Ground(Background); - 8001292: f24c 70ff movw r0, #51199 ; 0xc7ff - 8001296: f000 fc0c bl 8001ab2 - SSD1289_Write_Pic_Coor(BIRD_X, BIRD_Y, WIDTH_BIRD, HEIGH_BIRD, bird_image); - 800129a: 4b30 ldr r3, [pc, #192] ; (800135c ) - 800129c: 9300 str r3, [sp, #0] - 800129e: 2313 movs r3, #19 - 80012a0: 221a movs r2, #26 - 80012a2: 2164 movs r1, #100 ; 0x64 - 80012a4: 206e movs r0, #110 ; 0x6e - 80012a6: f000 fac9 bl 800183c - SSD1289_Write_Pic_Coor(0, HEIGH_SCREEN, WIDTH_LINE, HEIGH_LINE, line); - 80012aa: 4b2d ldr r3, [pc, #180] ; (8001360 ) - 80012ac: 9300 str r3, [sp, #0] - 80012ae: 2305 movs r3, #5 - 80012b0: f44f 72a0 mov.w r2, #320 ; 0x140 - 80012b4: 21d7 movs r1, #215 ; 0xd7 - 80012b6: 2000 movs r0, #0 - 80012b8: f000 fac0 bl 800183c - SSD1289_Fill_Color(0, HEIGH_SCREEN+5, 319, 239, Yellow); - 80012bc: f64f 73e0 movw r3, #65504 ; 0xffe0 - 80012c0: 9300 str r3, [sp, #0] - 80012c2: 23ef movs r3, #239 ; 0xef - 80012c4: f240 123f movw r2, #319 ; 0x13f - 80012c8: 21dc movs r1, #220 ; 0xdc - 80012ca: 2000 movs r0, #0 - 80012cc: f000 fa84 bl 80017d8 - SSD1289_Print_String(10, HEIGH_SCREEN+8, 1, 1, 2, Blue, Yellow, "Score: "); - 80012d0: 4b24 ldr r3, [pc, #144] ; (8001364 ) - 80012d2: 9303 str r3, [sp, #12] - 80012d4: f64f 73e0 movw r3, #65504 ; 0xffe0 - 80012d8: 9302 str r3, [sp, #8] - 80012da: 231f movs r3, #31 - 80012dc: 9301 str r3, [sp, #4] - 80012de: 2302 movs r3, #2 - 80012e0: 9300 str r3, [sp, #0] - 80012e2: 2301 movs r3, #1 - 80012e4: 2201 movs r2, #1 - 80012e6: 21df movs r1, #223 ; 0xdf - 80012e8: 200a movs r0, #10 - 80012ea: f000 fb6b bl 80019c4 - Print_Score(score, X_SCORE, Blue); - 80012ee: 4b11 ldr r3, [pc, #68] ; (8001334 ) - 80012f0: 881b ldrh r3, [r3, #0] - 80012f2: 221f movs r2, #31 - 80012f4: 214b movs r1, #75 ; 0x4b - 80012f6: 4618 mov r0, r3 - 80012f8: f7ff fe52 bl 8000fa0 - SSD1289_Print_String(X_H_SCORE, HEIGH_SCREEN+8, 1, 1, 2, Hscolor, Yellow, "High Score: "); - 80012fc: 4b1a ldr r3, [pc, #104] ; (8001368 ) - 80012fe: 9303 str r3, [sp, #12] - 8001300: f64f 73e0 movw r3, #65504 ; 0xffe0 - 8001304: 9302 str r3, [sp, #8] - 8001306: f24f 031f movw r3, #61471 ; 0xf01f - 800130a: 9301 str r3, [sp, #4] - 800130c: 2302 movs r3, #2 - 800130e: 9300 str r3, [sp, #0] - 8001310: 2301 movs r3, #1 - 8001312: 2201 movs r2, #1 - 8001314: 21df movs r1, #223 ; 0xdf - 8001316: 20b4 movs r0, #180 ; 0xb4 - 8001318: f000 fb54 bl 80019c4 - Print_Score(high_score, 300, Hscolor); - 800131c: 4b13 ldr r3, [pc, #76] ; (800136c ) - 800131e: 881b ldrh r3, [r3, #0] - 8001320: f24f 021f movw r2, #61471 ; 0xf01f - 8001324: f44f 7196 mov.w r1, #300 ; 0x12c - 8001328: 4618 mov r0, r3 - 800132a: f7ff fe39 bl 8000fa0 -} - 800132e: bf00 nop - 8001330: 46bd mov sp, r7 - 8001332: bd80 pop {r7, pc} - 8001334: 2000277e .word 0x2000277e - 8001338: 20002782 .word 0x20002782 - 800133c: 20002784 .word 0x20002784 - 8001340: 88888889 .word 0x88888889 - 8001344: 20002760 .word 0x20002760 - 8001348: 20002786 .word 0x20002786 - 800134c: 20002788 .word 0x20002788 - 8001350: 2000278a .word 0x2000278a - 8001354: 2000278c .word 0x2000278c - 8001358: 2000278e .word 0x2000278e - 800135c: 20000000 .word 0x20000000 - 8001360: 200003dc .word 0x200003dc - 8001364: 08004b58 .word 0x08004b58 - 8001368: 08004b60 .word 0x08004b60 - 800136c: 20002780 .word 0x20002780 - -08001370 : -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - 8001370: b580 push {r7, lr} - 8001372: b094 sub sp, #80 ; 0x50 - 8001374: af00 add r7, sp, #0 - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 8001376: f107 0320 add.w r3, r7, #32 - 800137a: 2230 movs r2, #48 ; 0x30 - 800137c: 2100 movs r1, #0 - 800137e: 4618 mov r0, r3 - 8001380: f002 fb82 bl 8003a88 - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8001384: f107 030c add.w r3, r7, #12 - 8001388: 2200 movs r2, #0 - 800138a: 601a str r2, [r3, #0] - 800138c: 605a str r2, [r3, #4] - 800138e: 609a str r2, [r3, #8] - 8001390: 60da str r2, [r3, #12] - 8001392: 611a str r2, [r3, #16] - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - 8001394: 2300 movs r3, #0 - 8001396: 60bb str r3, [r7, #8] - 8001398: 4b28 ldr r3, [pc, #160] ; (800143c ) - 800139a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800139c: 4a27 ldr r2, [pc, #156] ; (800143c ) - 800139e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 80013a2: 6413 str r3, [r2, #64] ; 0x40 - 80013a4: 4b25 ldr r3, [pc, #148] ; (800143c ) - 80013a6: 6c1b ldr r3, [r3, #64] ; 0x40 - 80013a8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80013ac: 60bb str r3, [r7, #8] - 80013ae: 68bb ldr r3, [r7, #8] - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 80013b0: 2300 movs r3, #0 - 80013b2: 607b str r3, [r7, #4] - 80013b4: 4b22 ldr r3, [pc, #136] ; (8001440 ) - 80013b6: 681b ldr r3, [r3, #0] - 80013b8: 4a21 ldr r2, [pc, #132] ; (8001440 ) - 80013ba: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 80013be: 6013 str r3, [r2, #0] - 80013c0: 4b1f ldr r3, [pc, #124] ; (8001440 ) - 80013c2: 681b ldr r3, [r3, #0] - 80013c4: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 80013c8: 607b str r3, [r7, #4] - 80013ca: 687b ldr r3, [r7, #4] - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - 80013cc: 2301 movs r3, #1 - 80013ce: 623b str r3, [r7, #32] - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 80013d0: f44f 3380 mov.w r3, #65536 ; 0x10000 - 80013d4: 627b str r3, [r7, #36] ; 0x24 - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 80013d6: 2302 movs r3, #2 - 80013d8: 63bb str r3, [r7, #56] ; 0x38 - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - 80013da: f44f 0380 mov.w r3, #4194304 ; 0x400000 - 80013de: 63fb str r3, [r7, #60] ; 0x3c - RCC_OscInitStruct.PLL.PLLM = 8; - 80013e0: 2308 movs r3, #8 - 80013e2: 643b str r3, [r7, #64] ; 0x40 - RCC_OscInitStruct.PLL.PLLN = 336; - 80013e4: f44f 73a8 mov.w r3, #336 ; 0x150 - 80013e8: 647b str r3, [r7, #68] ; 0x44 - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - 80013ea: 2302 movs r3, #2 - 80013ec: 64bb str r3, [r7, #72] ; 0x48 - RCC_OscInitStruct.PLL.PLLQ = 7; - 80013ee: 2307 movs r3, #7 - 80013f0: 64fb str r3, [r7, #76] ; 0x4c - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 80013f2: f107 0320 add.w r3, r7, #32 - 80013f6: 4618 mov r0, r3 - 80013f8: f001 fa86 bl 8002908 - 80013fc: 4603 mov r3, r0 - 80013fe: 2b00 cmp r3, #0 - 8001400: d001 beq.n 8001406 - { - Error_Handler(); - 8001402: f000 f8ed bl 80015e0 - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8001406: 230f movs r3, #15 - 8001408: 60fb str r3, [r7, #12] - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 800140a: 2302 movs r3, #2 - 800140c: 613b str r3, [r7, #16] - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 800140e: 2300 movs r3, #0 - 8001410: 617b str r3, [r7, #20] - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - 8001412: f44f 53a0 mov.w r3, #5120 ; 0x1400 - 8001416: 61bb str r3, [r7, #24] - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - 8001418: f44f 5380 mov.w r3, #4096 ; 0x1000 - 800141c: 61fb str r3, [r7, #28] - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - 800141e: f107 030c add.w r3, r7, #12 - 8001422: 2105 movs r1, #5 - 8001424: 4618 mov r0, r3 - 8001426: f001 fce7 bl 8002df8 - 800142a: 4603 mov r3, r0 - 800142c: 2b00 cmp r3, #0 - 800142e: d001 beq.n 8001434 - { - Error_Handler(); - 8001430: f000 f8d6 bl 80015e0 - } -} - 8001434: bf00 nop - 8001436: 3750 adds r7, #80 ; 0x50 - 8001438: 46bd mov sp, r7 - 800143a: bd80 pop {r7, pc} - 800143c: 40023800 .word 0x40023800 - 8001440: 40007000 .word 0x40007000 - -08001444 : - * @brief SPI3 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI3_Init(void) -{ - 8001444: b580 push {r7, lr} - 8001446: af00 add r7, sp, #0 - - /* USER CODE BEGIN SPI3_Init 1 */ - - /* USER CODE END SPI3_Init 1 */ - /* SPI3 parameter configuration*/ - hspi3.Instance = SPI3; - 8001448: 4b17 ldr r3, [pc, #92] ; (80014a8 ) - 800144a: 4a18 ldr r2, [pc, #96] ; (80014ac ) - 800144c: 601a str r2, [r3, #0] - hspi3.Init.Mode = SPI_MODE_MASTER; - 800144e: 4b16 ldr r3, [pc, #88] ; (80014a8 ) - 8001450: f44f 7282 mov.w r2, #260 ; 0x104 - 8001454: 605a str r2, [r3, #4] - hspi3.Init.Direction = SPI_DIRECTION_2LINES; - 8001456: 4b14 ldr r3, [pc, #80] ; (80014a8 ) - 8001458: 2200 movs r2, #0 - 800145a: 609a str r2, [r3, #8] - hspi3.Init.DataSize = SPI_DATASIZE_8BIT; - 800145c: 4b12 ldr r3, [pc, #72] ; (80014a8 ) - 800145e: 2200 movs r2, #0 - 8001460: 60da str r2, [r3, #12] - hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; - 8001462: 4b11 ldr r3, [pc, #68] ; (80014a8 ) - 8001464: 2200 movs r2, #0 - 8001466: 611a str r2, [r3, #16] - hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; - 8001468: 4b0f ldr r3, [pc, #60] ; (80014a8 ) - 800146a: 2200 movs r2, #0 - 800146c: 615a str r2, [r3, #20] - hspi3.Init.NSS = SPI_NSS_SOFT; - 800146e: 4b0e ldr r3, [pc, #56] ; (80014a8 ) - 8001470: f44f 7200 mov.w r2, #512 ; 0x200 - 8001474: 619a str r2, [r3, #24] - hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; - 8001476: 4b0c ldr r3, [pc, #48] ; (80014a8 ) - 8001478: 2218 movs r2, #24 - 800147a: 61da str r2, [r3, #28] - hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; - 800147c: 4b0a ldr r3, [pc, #40] ; (80014a8 ) - 800147e: 2200 movs r2, #0 - 8001480: 621a str r2, [r3, #32] - hspi3.Init.TIMode = SPI_TIMODE_DISABLE; - 8001482: 4b09 ldr r3, [pc, #36] ; (80014a8 ) - 8001484: 2200 movs r2, #0 - 8001486: 625a str r2, [r3, #36] ; 0x24 - hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - 8001488: 4b07 ldr r3, [pc, #28] ; (80014a8 ) - 800148a: 2200 movs r2, #0 - 800148c: 629a str r2, [r3, #40] ; 0x28 - hspi3.Init.CRCPolynomial = 10; - 800148e: 4b06 ldr r3, [pc, #24] ; (80014a8 ) - 8001490: 220a movs r2, #10 - 8001492: 62da str r2, [r3, #44] ; 0x2c - if (HAL_SPI_Init(&hspi3) != HAL_OK) - 8001494: 4804 ldr r0, [pc, #16] ; (80014a8 ) - 8001496: f001 fe9b bl 80031d0 - 800149a: 4603 mov r3, r0 - 800149c: 2b00 cmp r3, #0 - 800149e: d001 beq.n 80014a4 - { - Error_Handler(); - 80014a0: f000 f89e bl 80015e0 - } - /* USER CODE BEGIN SPI3_Init 2 */ - - /* USER CODE END SPI3_Init 2 */ - -} - 80014a4: bf00 nop - 80014a6: bd80 pop {r7, pc} - 80014a8: 20002708 .word 0x20002708 - 80014ac: 40003c00 .word 0x40003c00 - -080014b0 : - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - 80014b0: b580 push {r7, lr} - 80014b2: b08a sub sp, #40 ; 0x28 - 80014b4: af00 add r7, sp, #0 - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80014b6: f107 0314 add.w r3, r7, #20 - 80014ba: 2200 movs r2, #0 - 80014bc: 601a str r2, [r3, #0] - 80014be: 605a str r2, [r3, #4] - 80014c0: 609a str r2, [r3, #8] - 80014c2: 60da str r2, [r3, #12] - 80014c4: 611a str r2, [r3, #16] - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOE_CLK_ENABLE(); - 80014c6: 2300 movs r3, #0 - 80014c8: 613b str r3, [r7, #16] - 80014ca: 4b41 ldr r3, [pc, #260] ; (80015d0 ) - 80014cc: 6b1b ldr r3, [r3, #48] ; 0x30 - 80014ce: 4a40 ldr r2, [pc, #256] ; (80015d0 ) - 80014d0: f043 0310 orr.w r3, r3, #16 - 80014d4: 6313 str r3, [r2, #48] ; 0x30 - 80014d6: 4b3e ldr r3, [pc, #248] ; (80015d0 ) - 80014d8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80014da: f003 0310 and.w r3, r3, #16 - 80014de: 613b str r3, [r7, #16] - 80014e0: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOH_CLK_ENABLE(); - 80014e2: 2300 movs r3, #0 - 80014e4: 60fb str r3, [r7, #12] - 80014e6: 4b3a ldr r3, [pc, #232] ; (80015d0 ) - 80014e8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80014ea: 4a39 ldr r2, [pc, #228] ; (80015d0 ) - 80014ec: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80014f0: 6313 str r3, [r2, #48] ; 0x30 - 80014f2: 4b37 ldr r3, [pc, #220] ; (80015d0 ) - 80014f4: 6b1b ldr r3, [r3, #48] ; 0x30 - 80014f6: f003 0380 and.w r3, r3, #128 ; 0x80 - 80014fa: 60fb str r3, [r7, #12] - 80014fc: 68fb ldr r3, [r7, #12] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 80014fe: 2300 movs r3, #0 - 8001500: 60bb str r3, [r7, #8] - 8001502: 4b33 ldr r3, [pc, #204] ; (80015d0 ) - 8001504: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001506: 4a32 ldr r2, [pc, #200] ; (80015d0 ) - 8001508: f043 0302 orr.w r3, r3, #2 - 800150c: 6313 str r3, [r2, #48] ; 0x30 - 800150e: 4b30 ldr r3, [pc, #192] ; (80015d0 ) - 8001510: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001512: f003 0302 and.w r3, r3, #2 - 8001516: 60bb str r3, [r7, #8] - 8001518: 68bb ldr r3, [r7, #8] - __HAL_RCC_GPIOD_CLK_ENABLE(); - 800151a: 2300 movs r3, #0 - 800151c: 607b str r3, [r7, #4] - 800151e: 4b2c ldr r3, [pc, #176] ; (80015d0 ) - 8001520: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001522: 4a2b ldr r2, [pc, #172] ; (80015d0 ) - 8001524: f043 0308 orr.w r3, r3, #8 - 8001528: 6313 str r3, [r2, #48] ; 0x30 - 800152a: 4b29 ldr r3, [pc, #164] ; (80015d0 ) - 800152c: 6b1b ldr r3, [r3, #48] ; 0x30 - 800152e: f003 0308 and.w r3, r3, #8 - 8001532: 607b str r3, [r7, #4] - 8001534: 687b ldr r3, [r7, #4] - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOE, D2_Pin|D3_Pin|D4_Pin|D5_Pin - 8001536: 2201 movs r2, #1 - 8001538: f64f 71ff movw r1, #65535 ; 0xffff - 800153c: 4825 ldr r0, [pc, #148] ; (80015d4 ) - 800153e: f001 f9c9 bl 80028d4 - |D6_Pin|D7_Pin|D8_Pin|D9_Pin - |D10_Pin|D11_Pin|D12_Pin|D13_Pin - |D14_Pin|D15_Pin|D0_Pin|D1_Pin, GPIO_PIN_SET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(CS_GPIO_Port, CS_Pin, GPIO_PIN_SET); - 8001542: 2201 movs r2, #1 - 8001544: f44f 6180 mov.w r1, #1024 ; 0x400 - 8001548: 4823 ldr r0, [pc, #140] ; (80015d8 ) - 800154a: f001 f9c3 bl 80028d4 - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOD, RESET_Pin|RD_Pin|WR_Pin|RS_Pin - 800154e: 2201 movs r2, #1 - 8001550: 21f8 movs r1, #248 ; 0xf8 - 8001552: 4822 ldr r0, [pc, #136] ; (80015dc ) - 8001554: f001 f9be bl 80028d4 - - /*Configure GPIO pins : D2_Pin D3_Pin D4_Pin D5_Pin - D6_Pin D7_Pin D8_Pin D9_Pin - D10_Pin D11_Pin D12_Pin D13_Pin - D14_Pin D15_Pin D0_Pin D1_Pin */ - GPIO_InitStruct.Pin = D2_Pin|D3_Pin|D4_Pin|D5_Pin - 8001558: f64f 73ff movw r3, #65535 ; 0xffff - 800155c: 617b str r3, [r7, #20] - |D6_Pin|D7_Pin|D8_Pin|D9_Pin - |D10_Pin|D11_Pin|D12_Pin|D13_Pin - |D14_Pin|D15_Pin|D0_Pin|D1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 800155e: 2301 movs r3, #1 - 8001560: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001562: 2300 movs r3, #0 - 8001564: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8001566: 2303 movs r3, #3 - 8001568: 623b str r3, [r7, #32] - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - 800156a: f107 0314 add.w r3, r7, #20 - 800156e: 4619 mov r1, r3 - 8001570: 4818 ldr r0, [pc, #96] ; (80015d4 ) - 8001572: f000 fffb bl 800256c - - /*Configure GPIO pin : CS_Pin */ - GPIO_InitStruct.Pin = CS_Pin; - 8001576: f44f 6380 mov.w r3, #1024 ; 0x400 - 800157a: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 800157c: 2301 movs r3, #1 - 800157e: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001580: 2300 movs r3, #0 - 8001582: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8001584: 2303 movs r3, #3 - 8001586: 623b str r3, [r7, #32] - HAL_GPIO_Init(CS_GPIO_Port, &GPIO_InitStruct); - 8001588: f107 0314 add.w r3, r7, #20 - 800158c: 4619 mov r1, r3 - 800158e: 4812 ldr r0, [pc, #72] ; (80015d8 ) - 8001590: f000 ffec bl 800256c - - /*Configure GPIO pin : T_IRQ_Pin */ - GPIO_InitStruct.Pin = T_IRQ_Pin; - 8001594: 2302 movs r3, #2 - 8001596: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8001598: 2300 movs r3, #0 - 800159a: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 800159c: 2300 movs r3, #0 - 800159e: 61fb str r3, [r7, #28] - HAL_GPIO_Init(T_IRQ_GPIO_Port, &GPIO_InitStruct); - 80015a0: f107 0314 add.w r3, r7, #20 - 80015a4: 4619 mov r1, r3 - 80015a6: 480d ldr r0, [pc, #52] ; (80015dc ) - 80015a8: f000 ffe0 bl 800256c - - /*Configure GPIO pins : RESET_Pin RD_Pin WR_Pin RS_Pin - T_CS_Pin */ - GPIO_InitStruct.Pin = RESET_Pin|RD_Pin|WR_Pin|RS_Pin - 80015ac: 23f8 movs r3, #248 ; 0xf8 - 80015ae: 617b str r3, [r7, #20] - |T_CS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80015b0: 2301 movs r3, #1 - 80015b2: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 80015b4: 2300 movs r3, #0 - 80015b6: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 80015b8: 2303 movs r3, #3 - 80015ba: 623b str r3, [r7, #32] - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 80015bc: f107 0314 add.w r3, r7, #20 - 80015c0: 4619 mov r1, r3 - 80015c2: 4806 ldr r0, [pc, #24] ; (80015dc ) - 80015c4: f000 ffd2 bl 800256c - -} - 80015c8: bf00 nop - 80015ca: 3728 adds r7, #40 ; 0x28 - 80015cc: 46bd mov sp, r7 - 80015ce: bd80 pop {r7, pc} - 80015d0: 40023800 .word 0x40023800 - 80015d4: 40021000 .word 0x40021000 - 80015d8: 40020400 .word 0x40020400 - 80015dc: 40020c00 .word 0x40020c00 - -080015e0 : -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - 80015e0: b480 push {r7} - 80015e2: af00 add r7, sp, #0 - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); - 80015e4: b672 cpsid i -} - 80015e6: bf00 nop - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - 80015e8: e7fe b.n 80015e8 - -080015ea : -#include "ssd1289.h" -#include "font.h" - - -void swap(uint16_t *a, uint16_t *b) -{ - 80015ea: b480 push {r7} - 80015ec: b085 sub sp, #20 - 80015ee: af00 add r7, sp, #0 - 80015f0: 6078 str r0, [r7, #4] - 80015f2: 6039 str r1, [r7, #0] - uint16_t temp = 0x0000; - 80015f4: 2300 movs r3, #0 - 80015f6: 81fb strh r3, [r7, #14] - - temp = *b; - 80015f8: 683b ldr r3, [r7, #0] - 80015fa: 881b ldrh r3, [r3, #0] - 80015fc: 81fb strh r3, [r7, #14] - *b = *a; - 80015fe: 687b ldr r3, [r7, #4] - 8001600: 881a ldrh r2, [r3, #0] - 8001602: 683b ldr r3, [r7, #0] - 8001604: 801a strh r2, [r3, #0] - *a = temp; - 8001606: 687b ldr r3, [r7, #4] - 8001608: 89fa ldrh r2, [r7, #14] - 800160a: 801a strh r2, [r3, #0] -} - 800160c: bf00 nop - 800160e: 3714 adds r7, #20 - 8001610: 46bd mov sp, r7 - 8001612: f85d 7b04 ldr.w r7, [sp], #4 - 8001616: 4770 bx lr - -08001618 : - -/*Ghui dia chi thanh ghi*/ -void SSD1289_Write_Com(uint16_t DH) -{ - 8001618: b580 push {r7, lr} - 800161a: b082 sub sp, #8 - 800161c: af00 add r7, sp, #0 - 800161e: 4603 mov r3, r0 - 8001620: 80fb strh r3, [r7, #6] - RSN; - 8001622: 2200 movs r2, #0 - 8001624: 2140 movs r1, #64 ; 0x40 - 8001626: 4810 ldr r0, [pc, #64] ; (8001668 ) - 8001628: f001 f954 bl 80028d4 - CSN; - 800162c: 2200 movs r2, #0 - 800162e: f44f 6180 mov.w r1, #1024 ; 0x400 - 8001632: 480e ldr r0, [pc, #56] ; (800166c ) - 8001634: f001 f94e bl 80028d4 - GPIOE -> ODR = DH; - 8001638: 4a0d ldr r2, [pc, #52] ; (8001670 ) - 800163a: 88fb ldrh r3, [r7, #6] - 800163c: 6153 str r3, [r2, #20] - WRN; - 800163e: 2200 movs r2, #0 - 8001640: 2120 movs r1, #32 - 8001642: 4809 ldr r0, [pc, #36] ; (8001668 ) - 8001644: f001 f946 bl 80028d4 - WR; - 8001648: 2201 movs r2, #1 - 800164a: 2120 movs r1, #32 - 800164c: 4806 ldr r0, [pc, #24] ; (8001668 ) - 800164e: f001 f941 bl 80028d4 - CS; - 8001652: 2201 movs r2, #1 - 8001654: f44f 6180 mov.w r1, #1024 ; 0x400 - 8001658: 4804 ldr r0, [pc, #16] ; (800166c ) - 800165a: f001 f93b bl 80028d4 -} - 800165e: bf00 nop - 8001660: 3708 adds r7, #8 - 8001662: 46bd mov sp, r7 - 8001664: bd80 pop {r7, pc} - 8001666: bf00 nop - 8001668: 40020c00 .word 0x40020c00 - 800166c: 40020400 .word 0x40020400 - 8001670: 40021000 .word 0x40021000 - -08001674 : - -/*Gui du lieu ghi vao thanh ghi*/ -void SSD1289_Write_Data(uint16_t DH) -{ - 8001674: b580 push {r7, lr} - 8001676: b082 sub sp, #8 - 8001678: af00 add r7, sp, #0 - 800167a: 4603 mov r3, r0 - 800167c: 80fb strh r3, [r7, #6] - RS; - 800167e: 2201 movs r2, #1 - 8001680: 2140 movs r1, #64 ; 0x40 - 8001682: 4810 ldr r0, [pc, #64] ; (80016c4 ) - 8001684: f001 f926 bl 80028d4 - CSN; - 8001688: 2200 movs r2, #0 - 800168a: f44f 6180 mov.w r1, #1024 ; 0x400 - 800168e: 480e ldr r0, [pc, #56] ; (80016c8 ) - 8001690: f001 f920 bl 80028d4 - GPIOE -> ODR = DH; - 8001694: 4a0d ldr r2, [pc, #52] ; (80016cc ) - 8001696: 88fb ldrh r3, [r7, #6] - 8001698: 6153 str r3, [r2, #20] - WRN; - 800169a: 2200 movs r2, #0 - 800169c: 2120 movs r1, #32 - 800169e: 4809 ldr r0, [pc, #36] ; (80016c4 ) - 80016a0: f001 f918 bl 80028d4 - WR; - 80016a4: 2201 movs r2, #1 - 80016a6: 2120 movs r1, #32 - 80016a8: 4806 ldr r0, [pc, #24] ; (80016c4 ) - 80016aa: f001 f913 bl 80028d4 - CS; - 80016ae: 2201 movs r2, #1 - 80016b0: f44f 6180 mov.w r1, #1024 ; 0x400 - 80016b4: 4804 ldr r0, [pc, #16] ; (80016c8 ) - 80016b6: f001 f90d bl 80028d4 -} - 80016ba: bf00 nop - 80016bc: 3708 adds r7, #8 - 80016be: 46bd mov sp, r7 - 80016c0: bd80 pop {r7, pc} - 80016c2: bf00 nop - 80016c4: 40020c00 .word 0x40020c00 - 80016c8: 40020400 .word 0x40020400 - 80016cc: 40021000 .word 0x40021000 - -080016d0 : - -/*Gui dong thoi dia chi thanh ghi va du lieu thanh ghi*/ -void SSD1289_Write_Com_Data(uint16_t com1,uint16_t dat1) -{ - 80016d0: b580 push {r7, lr} - 80016d2: b082 sub sp, #8 - 80016d4: af00 add r7, sp, #0 - 80016d6: 4603 mov r3, r0 - 80016d8: 460a mov r2, r1 - 80016da: 80fb strh r3, [r7, #6] - 80016dc: 4613 mov r3, r2 - 80016de: 80bb strh r3, [r7, #4] - SSD1289_Write_Com(com1); - 80016e0: 88fb ldrh r3, [r7, #6] - 80016e2: 4618 mov r0, r3 - 80016e4: f7ff ff98 bl 8001618 - SSD1289_Write_Data(dat1); - 80016e8: 88bb ldrh r3, [r7, #4] - 80016ea: 4618 mov r0, r3 - 80016ec: f7ff ffc2 bl 8001674 -} - 80016f0: bf00 nop - 80016f2: 3708 adds r7, #8 - 80016f4: 46bd mov sp, r7 - 80016f6: bd80 pop {r7, pc} - -080016f8 : - RST; -} - -/*Set dia chi cua so*/ -void SSD1289_Address_Set(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) /*Thiet lap vung lam viec cua man hinh*/ -{ - 80016f8: b590 push {r4, r7, lr} - 80016fa: b083 sub sp, #12 - 80016fc: af00 add r7, sp, #0 - 80016fe: 4604 mov r4, r0 - 8001700: 4608 mov r0, r1 - 8001702: 4611 mov r1, r2 - 8001704: 461a mov r2, r3 - 8001706: 4623 mov r3, r4 - 8001708: 80fb strh r3, [r7, #6] - 800170a: 4603 mov r3, r0 - 800170c: 80bb strh r3, [r7, #4] - 800170e: 460b mov r3, r1 - 8001710: 807b strh r3, [r7, #2] - 8001712: 4613 mov r3, r2 - 8001714: 803b strh r3, [r7, #0] - /*Doi toa do ve toa do mong muon*/ - swap(&x1, &y1); - 8001716: 1d3a adds r2, r7, #4 - 8001718: 1dbb adds r3, r7, #6 - 800171a: 4611 mov r1, r2 - 800171c: 4618 mov r0, r3 - 800171e: f7ff ff64 bl 80015ea - swap(&x2, &y2); - 8001722: 463a mov r2, r7 - 8001724: 1cbb adds r3, r7, #2 - 8001726: 4611 mov r1, r2 - 8001728: 4618 mov r0, r3 - 800172a: f7ff ff5e bl 80015ea - - SSD1289_Write_Com_Data(0x0044,(x2<<8)+x1); - 800172e: 887b ldrh r3, [r7, #2] - 8001730: 021b lsls r3, r3, #8 - 8001732: b29a uxth r2, r3 - 8001734: 88fb ldrh r3, [r7, #6] - 8001736: 4413 add r3, r2 - 8001738: b29b uxth r3, r3 - 800173a: 4619 mov r1, r3 - 800173c: 2044 movs r0, #68 ; 0x44 - 800173e: f7ff ffc7 bl 80016d0 - SSD1289_Write_Com_Data(0x0045, y1); - 8001742: 88bb ldrh r3, [r7, #4] - 8001744: 4619 mov r1, r3 - 8001746: 2045 movs r0, #69 ; 0x45 - 8001748: f7ff ffc2 bl 80016d0 - SSD1289_Write_Com_Data(0x0046, y2); - 800174c: 883b ldrh r3, [r7, #0] - 800174e: 4619 mov r1, r3 - 8001750: 2046 movs r0, #70 ; 0x46 - 8001752: f7ff ffbd bl 80016d0 - SSD1289_Write_Com_Data(0x004E, x1); - 8001756: 88fb ldrh r3, [r7, #6] - 8001758: 4619 mov r1, r3 - 800175a: 204e movs r0, #78 ; 0x4e - 800175c: f7ff ffb8 bl 80016d0 - SSD1289_Write_Com_Data(0x004F, y1); - 8001760: 88bb ldrh r3, [r7, #4] - 8001762: 4619 mov r1, r3 - 8001764: 204f movs r0, #79 ; 0x4f - 8001766: f7ff ffb3 bl 80016d0 - SSD1289_Write_Com(0x0022); - 800176a: 2022 movs r0, #34 ; 0x22 - 800176c: f7ff ff54 bl 8001618 -} - 8001770: bf00 nop - 8001772: 370c adds r7, #12 - 8001774: 46bd mov sp, r7 - 8001776: bd90 pop {r4, r7, pc} - -08001778 : - -/*Ghi pixel*/ -void SSD1289_Write_Pixel(uint16_t x, uint16_t y, uint16_t color) -{ - 8001778: b580 push {r7, lr} - 800177a: b082 sub sp, #8 - 800177c: af00 add r7, sp, #0 - 800177e: 4603 mov r3, r0 - 8001780: 80fb strh r3, [r7, #6] - 8001782: 460b mov r3, r1 - 8001784: 80bb strh r3, [r7, #4] - 8001786: 4613 mov r3, r2 - 8001788: 807b strh r3, [r7, #2] - CSN; - 800178a: 2200 movs r2, #0 - 800178c: f44f 6180 mov.w r1, #1024 ; 0x400 - 8001790: 4810 ldr r0, [pc, #64] ; (80017d4 ) - 8001792: f001 f89f bl 80028d4 - - swap(&x, &y); - 8001796: 1d3a adds r2, r7, #4 - 8001798: 1dbb adds r3, r7, #6 - 800179a: 4611 mov r1, r2 - 800179c: 4618 mov r0, r3 - 800179e: f7ff ff24 bl 80015ea - SSD1289_Write_Com_Data(0x004E, x); - 80017a2: 88fb ldrh r3, [r7, #6] - 80017a4: 4619 mov r1, r3 - 80017a6: 204e movs r0, #78 ; 0x4e - 80017a8: f7ff ff92 bl 80016d0 - SSD1289_Write_Com_Data(0x004F, y); - 80017ac: 88bb ldrh r3, [r7, #4] - 80017ae: 4619 mov r1, r3 - 80017b0: 204f movs r0, #79 ; 0x4f - 80017b2: f7ff ff8d bl 80016d0 - SSD1289_Write_Com_Data(0x0022, color); - 80017b6: 887b ldrh r3, [r7, #2] - 80017b8: 4619 mov r1, r3 - 80017ba: 2022 movs r0, #34 ; 0x22 - 80017bc: f7ff ff88 bl 80016d0 - - CS; - 80017c0: 2201 movs r2, #1 - 80017c2: f44f 6180 mov.w r1, #1024 ; 0x400 - 80017c6: 4803 ldr r0, [pc, #12] ; (80017d4 ) - 80017c8: f001 f884 bl 80028d4 -} - 80017cc: bf00 nop - 80017ce: 3708 adds r7, #8 - 80017d0: 46bd mov sp, r7 - 80017d2: bd80 pop {r7, pc} - 80017d4: 40020400 .word 0x40020400 - -080017d8 : - SSD1289_Write_Com_Data(0x004F, y_pos); - SSD1289_Write_Com(0x0022); -} - -/*Ve mau*/ -void SSD1289_Fill_Color(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color){ /*To mau trong khoang da duoc quy dinh*/ - 80017d8: b590 push {r4, r7, lr} - 80017da: b085 sub sp, #20 - 80017dc: af00 add r7, sp, #0 - 80017de: 4604 mov r4, r0 - 80017e0: 4608 mov r0, r1 - 80017e2: 4611 mov r1, r2 - 80017e4: 461a mov r2, r3 - 80017e6: 4623 mov r3, r4 - 80017e8: 80fb strh r3, [r7, #6] - 80017ea: 4603 mov r3, r0 - 80017ec: 80bb strh r3, [r7, #4] - 80017ee: 460b mov r3, r1 - 80017f0: 807b strh r3, [r7, #2] - 80017f2: 4613 mov r3, r2 - 80017f4: 803b strh r3, [r7, #0] - uint16_t max_index = (x2 - x1 + 1)*(y2 - y1 + 1); - 80017f6: 887a ldrh r2, [r7, #2] - 80017f8: 88fb ldrh r3, [r7, #6] - 80017fa: 1ad3 subs r3, r2, r3 - 80017fc: 3301 adds r3, #1 - 80017fe: b29a uxth r2, r3 - 8001800: 8839 ldrh r1, [r7, #0] - 8001802: 88bb ldrh r3, [r7, #4] - 8001804: 1acb subs r3, r1, r3 - 8001806: 3301 adds r3, #1 - 8001808: b29b uxth r3, r3 - 800180a: fb12 f303 smulbb r3, r2, r3 - 800180e: 81fb strh r3, [r7, #14] - SSD1289_Address_Set(x1, y1, x2, y2); - 8001810: 883b ldrh r3, [r7, #0] - 8001812: 887a ldrh r2, [r7, #2] - 8001814: 88b9 ldrh r1, [r7, #4] - 8001816: 88f8 ldrh r0, [r7, #6] - 8001818: f7ff ff6e bl 80016f8 - - while(max_index){ - 800181c: e006 b.n 800182c - SSD1289_Write_Data(color); - 800181e: 8c3b ldrh r3, [r7, #32] - 8001820: 4618 mov r0, r3 - 8001822: f7ff ff27 bl 8001674 - max_index--; - 8001826: 89fb ldrh r3, [r7, #14] - 8001828: 3b01 subs r3, #1 - 800182a: 81fb strh r3, [r7, #14] - while(max_index){ - 800182c: 89fb ldrh r3, [r7, #14] - 800182e: 2b00 cmp r3, #0 - 8001830: d1f5 bne.n 800181e - } -} - 8001832: bf00 nop - 8001834: bf00 nop - 8001836: 3714 adds r7, #20 - 8001838: 46bd mov sp, r7 - 800183a: bd90 pop {r4, r7, pc} - -0800183c : - - -void SSD1289_Write_Pic_Coor(uint16_t x, uint16_t y, uint16_t length, uint16_t width, uint16_t *pic){ - 800183c: b590 push {r4, r7, lr} - 800183e: b085 sub sp, #20 - 8001840: af00 add r7, sp, #0 - 8001842: 4604 mov r4, r0 - 8001844: 4608 mov r0, r1 - 8001846: 4611 mov r1, r2 - 8001848: 461a mov r2, r3 - 800184a: 4623 mov r3, r4 - 800184c: 80fb strh r3, [r7, #6] - 800184e: 4603 mov r3, r0 - 8001850: 80bb strh r3, [r7, #4] - 8001852: 460b mov r3, r1 - 8001854: 807b strh r3, [r7, #2] - 8001856: 4613 mov r3, r2 - 8001858: 803b strh r3, [r7, #0] - uint16_t index_x = 0, index_y = 0, i = 0; - 800185a: 2300 movs r3, #0 - 800185c: 81fb strh r3, [r7, #14] - 800185e: 2300 movs r3, #0 - 8001860: 81bb strh r3, [r7, #12] - 8001862: 2300 movs r3, #0 - 8001864: 817b strh r3, [r7, #10] - for(index_y = 0; index_y < width; index_y++){ - 8001866: 2300 movs r3, #0 - 8001868: 81bb strh r3, [r7, #12] - 800186a: e01f b.n 80018ac - for(index_x = 0; index_x < length; index_x++){ - 800186c: 2300 movs r3, #0 - 800186e: 81fb strh r3, [r7, #14] - 8001870: e015 b.n 800189e - SSD1289_Write_Pixel(x + index_x, y + index_y, pic[i]); - 8001872: 88fa ldrh r2, [r7, #6] - 8001874: 89fb ldrh r3, [r7, #14] - 8001876: 4413 add r3, r2 - 8001878: b298 uxth r0, r3 - 800187a: 88ba ldrh r2, [r7, #4] - 800187c: 89bb ldrh r3, [r7, #12] - 800187e: 4413 add r3, r2 - 8001880: b299 uxth r1, r3 - 8001882: 897b ldrh r3, [r7, #10] - 8001884: 005b lsls r3, r3, #1 - 8001886: 6a3a ldr r2, [r7, #32] - 8001888: 4413 add r3, r2 - 800188a: 881b ldrh r3, [r3, #0] - 800188c: 461a mov r2, r3 - 800188e: f7ff ff73 bl 8001778 - i++; - 8001892: 897b ldrh r3, [r7, #10] - 8001894: 3301 adds r3, #1 - 8001896: 817b strh r3, [r7, #10] - for(index_x = 0; index_x < length; index_x++){ - 8001898: 89fb ldrh r3, [r7, #14] - 800189a: 3301 adds r3, #1 - 800189c: 81fb strh r3, [r7, #14] - 800189e: 89fa ldrh r2, [r7, #14] - 80018a0: 887b ldrh r3, [r7, #2] - 80018a2: 429a cmp r2, r3 - 80018a4: d3e5 bcc.n 8001872 - for(index_y = 0; index_y < width; index_y++){ - 80018a6: 89bb ldrh r3, [r7, #12] - 80018a8: 3301 adds r3, #1 - 80018aa: 81bb strh r3, [r7, #12] - 80018ac: 89ba ldrh r2, [r7, #12] - 80018ae: 883b ldrh r3, [r7, #0] - 80018b0: 429a cmp r2, r3 - 80018b2: d3db bcc.n 800186c - } - } -} - 80018b4: bf00 nop - 80018b6: bf00 nop - 80018b8: 3714 adds r7, #20 - 80018ba: 46bd mov sp, r7 - 80018bc: bd90 pop {r4, r7, pc} - ... - -080018c0 : -void SSD1289_Print_Char(uint16_t x_pos, uint16_t y_pos, uint16_t font_size, uint16_t color, uint16_t back_color, char ch){ - 80018c0: b590 push {r4, r7, lr} - 80018c2: b089 sub sp, #36 ; 0x24 - 80018c4: af02 add r7, sp, #8 - 80018c6: 4604 mov r4, r0 - 80018c8: 4608 mov r0, r1 - 80018ca: 4611 mov r1, r2 - 80018cc: 461a mov r2, r3 - 80018ce: 4623 mov r3, r4 - 80018d0: 80fb strh r3, [r7, #6] - 80018d2: 4603 mov r3, r0 - 80018d4: 80bb strh r3, [r7, #4] - 80018d6: 460b mov r3, r1 - 80018d8: 807b strh r3, [r7, #2] - 80018da: 4613 mov r3, r2 - 80018dc: 803b strh r3, [r7, #0] - int i = 0; - 80018de: 2300 movs r3, #0 - 80018e0: 617b str r3, [r7, #20] - int j = 0; - 80018e2: 2300 movs r3, #0 - 80018e4: 613b str r3, [r7, #16] - uint16_t y = y_pos; - 80018e6: 88bb ldrh r3, [r7, #4] - 80018e8: 81fb strh r3, [r7, #14] - uint16_t column = 0; - 80018ea: 2300 movs r3, #0 - 80018ec: 81bb strh r3, [r7, #12] - if(font_size == 0) - 80018ee: 887b ldrh r3, [r7, #2] - 80018f0: 2b00 cmp r3, #0 - 80018f2: d101 bne.n 80018f8 - font_size = 1; - 80018f4: 2301 movs r3, #1 - 80018f6: 807b strh r3, [r7, #2] - uint16_t *value = font[(uint16_t)ch-32]; - 80018f8: f897 302c ldrb.w r3, [r7, #44] ; 0x2c - 80018fc: f1a3 0220 sub.w r2, r3, #32 - 8001900: 4613 mov r3, r2 - 8001902: 009b lsls r3, r3, #2 - 8001904: 4413 add r3, r2 - 8001906: 005b lsls r3, r3, #1 - 8001908: 4a2d ldr r2, [pc, #180] ; (80019c0 ) - 800190a: 4413 add r3, r2 - 800190c: 60bb str r3, [r7, #8] - for(i = 0; i < 5; i++){ - 800190e: 2300 movs r3, #0 - 8001910: 617b str r3, [r7, #20] - 8001912: e04c b.n 80019ae - column = value[i]; - 8001914: 697b ldr r3, [r7, #20] - 8001916: 005b lsls r3, r3, #1 - 8001918: 68ba ldr r2, [r7, #8] - 800191a: 4413 add r3, r2 - 800191c: 881b ldrh r3, [r3, #0] - 800191e: 81bb strh r3, [r7, #12] - y_pos = y; - 8001920: 89fb ldrh r3, [r7, #14] - 8001922: 80bb strh r3, [r7, #4] - for(j = 0; j < 7; j++){ - 8001924: 2300 movs r3, #0 - 8001926: 613b str r3, [r7, #16] - 8001928: e037 b.n 800199a - if((column >> j) & 0x0001) - 800192a: 89ba ldrh r2, [r7, #12] - 800192c: 693b ldr r3, [r7, #16] - 800192e: fa42 f303 asr.w r3, r2, r3 - 8001932: f003 0301 and.w r3, r3, #1 - 8001936: 2b00 cmp r3, #0 - 8001938: d014 beq.n 8001964 - SSD1289_Fill_Color(x_pos, y_pos, (x_pos + font_size - 1), (y_pos +font_size - 1), color); - 800193a: 88fa ldrh r2, [r7, #6] - 800193c: 887b ldrh r3, [r7, #2] - 800193e: 4413 add r3, r2 - 8001940: b29b uxth r3, r3 - 8001942: 3b01 subs r3, #1 - 8001944: b29c uxth r4, r3 - 8001946: 88ba ldrh r2, [r7, #4] - 8001948: 887b ldrh r3, [r7, #2] - 800194a: 4413 add r3, r2 - 800194c: b29b uxth r3, r3 - 800194e: 3b01 subs r3, #1 - 8001950: b29a uxth r2, r3 - 8001952: 88b9 ldrh r1, [r7, #4] - 8001954: 88f8 ldrh r0, [r7, #6] - 8001956: 883b ldrh r3, [r7, #0] - 8001958: 9300 str r3, [sp, #0] - 800195a: 4613 mov r3, r2 - 800195c: 4622 mov r2, r4 - 800195e: f7ff ff3b bl 80017d8 - 8001962: e013 b.n 800198c - else{ - SSD1289_Fill_Color(x_pos, y_pos, (x_pos + font_size - 1), (y_pos +font_size - 1), back_color); - 8001964: 88fa ldrh r2, [r7, #6] - 8001966: 887b ldrh r3, [r7, #2] - 8001968: 4413 add r3, r2 - 800196a: b29b uxth r3, r3 - 800196c: 3b01 subs r3, #1 - 800196e: b29c uxth r4, r3 - 8001970: 88ba ldrh r2, [r7, #4] - 8001972: 887b ldrh r3, [r7, #2] - 8001974: 4413 add r3, r2 - 8001976: b29b uxth r3, r3 - 8001978: 3b01 subs r3, #1 - 800197a: b29a uxth r2, r3 - 800197c: 88b9 ldrh r1, [r7, #4] - 800197e: 88f8 ldrh r0, [r7, #6] - 8001980: 8d3b ldrh r3, [r7, #40] ; 0x28 - 8001982: 9300 str r3, [sp, #0] - 8001984: 4613 mov r3, r2 - 8001986: 4622 mov r2, r4 - 8001988: f7ff ff26 bl 80017d8 - } - y_pos += font_size; - 800198c: 88ba ldrh r2, [r7, #4] - 800198e: 887b ldrh r3, [r7, #2] - 8001990: 4413 add r3, r2 - 8001992: 80bb strh r3, [r7, #4] - for(j = 0; j < 7; j++){ - 8001994: 693b ldr r3, [r7, #16] - 8001996: 3301 adds r3, #1 - 8001998: 613b str r3, [r7, #16] - 800199a: 693b ldr r3, [r7, #16] - 800199c: 2b06 cmp r3, #6 - 800199e: ddc4 ble.n 800192a - } - x_pos+= font_size; - 80019a0: 88fa ldrh r2, [r7, #6] - 80019a2: 887b ldrh r3, [r7, #2] - 80019a4: 4413 add r3, r2 - 80019a6: 80fb strh r3, [r7, #6] - for(i = 0; i < 5; i++){ - 80019a8: 697b ldr r3, [r7, #20] - 80019aa: 3301 adds r3, #1 - 80019ac: 617b str r3, [r7, #20] - 80019ae: 697b ldr r3, [r7, #20] - 80019b0: 2b04 cmp r3, #4 - 80019b2: ddaf ble.n 8001914 - } -} - 80019b4: bf00 nop - 80019b6: bf00 nop - 80019b8: 371c adds r7, #28 - 80019ba: 46bd mov sp, r7 - 80019bc: bd90 pop {r4, r7, pc} - 80019be: bf00 nop - 80019c0: 200022bc .word 0x200022bc - -080019c4 : - -void SSD1289_Print_String(uint16_t x_pos, uint16_t y_pos, uint16_t dis_char, uint16_t dis_line, uint16_t font_size, uint16_t color, uint16_t back_color, char *str){ - 80019c4: b590 push {r4, r7, lr} - 80019c6: b087 sub sp, #28 - 80019c8: af02 add r7, sp, #8 - 80019ca: 4604 mov r4, r0 - 80019cc: 4608 mov r0, r1 - 80019ce: 4611 mov r1, r2 - 80019d0: 461a mov r2, r3 - 80019d2: 4623 mov r3, r4 - 80019d4: 80fb strh r3, [r7, #6] - 80019d6: 4603 mov r3, r0 - 80019d8: 80bb strh r3, [r7, #4] - 80019da: 460b mov r3, r1 - 80019dc: 807b strh r3, [r7, #2] - 80019de: 4613 mov r3, r2 - 80019e0: 803b strh r3, [r7, #0] - uint16_t x = x_pos; - 80019e2: 88fb ldrh r3, [r7, #6] - 80019e4: 81fb strh r3, [r7, #14] - if(str == NULL) - 80019e6: 6afb ldr r3, [r7, #44] ; 0x2c - 80019e8: 2b00 cmp r3, #0 - 80019ea: d031 beq.n 8001a50 - return; - do{ - if(*str == '\n'){ - 80019ec: 6afb ldr r3, [r7, #44] ; 0x2c - 80019ee: 781b ldrb r3, [r3, #0] - 80019f0: 2b0a cmp r3, #10 - 80019f2: d10f bne.n 8001a14 - str++; - 80019f4: 6afb ldr r3, [r7, #44] ; 0x2c - 80019f6: 3301 adds r3, #1 - 80019f8: 62fb str r3, [r7, #44] ; 0x2c - y_pos = y_pos + font_size * 7 + dis_line; - 80019fa: 8c3b ldrh r3, [r7, #32] - 80019fc: 461a mov r2, r3 - 80019fe: 00d2 lsls r2, r2, #3 - 8001a00: 1ad3 subs r3, r2, r3 - 8001a02: b29a uxth r2, r3 - 8001a04: 88bb ldrh r3, [r7, #4] - 8001a06: 4413 add r3, r2 - 8001a08: b29a uxth r2, r3 - 8001a0a: 883b ldrh r3, [r7, #0] - 8001a0c: 4413 add r3, r2 - 8001a0e: 80bb strh r3, [r7, #4] - x_pos = x; - 8001a10: 89fb ldrh r3, [r7, #14] - 8001a12: 80fb strh r3, [r7, #6] - } - SSD1289_Print_Char(x_pos, y_pos, font_size, color, back_color, *str++); - 8001a14: 6afb ldr r3, [r7, #44] ; 0x2c - 8001a16: 1c5a adds r2, r3, #1 - 8001a18: 62fa str r2, [r7, #44] ; 0x2c - 8001a1a: 781b ldrb r3, [r3, #0] - 8001a1c: 8cbc ldrh r4, [r7, #36] ; 0x24 - 8001a1e: 8c3a ldrh r2, [r7, #32] - 8001a20: 88b9 ldrh r1, [r7, #4] - 8001a22: 88f8 ldrh r0, [r7, #6] - 8001a24: 9301 str r3, [sp, #4] - 8001a26: 8d3b ldrh r3, [r7, #40] ; 0x28 - 8001a28: 9300 str r3, [sp, #0] - 8001a2a: 4623 mov r3, r4 - 8001a2c: f7ff ff48 bl 80018c0 - x_pos += (font_size *5 + dis_char); - 8001a30: 8c3b ldrh r3, [r7, #32] - 8001a32: 461a mov r2, r3 - 8001a34: 0092 lsls r2, r2, #2 - 8001a36: 4413 add r3, r2 - 8001a38: b29a uxth r2, r3 - 8001a3a: 887b ldrh r3, [r7, #2] - 8001a3c: 4413 add r3, r2 - 8001a3e: b29a uxth r2, r3 - 8001a40: 88fb ldrh r3, [r7, #6] - 8001a42: 4413 add r3, r2 - 8001a44: 80fb strh r3, [r7, #6] - } - while(*str != '\0'); - 8001a46: 6afb ldr r3, [r7, #44] ; 0x2c - 8001a48: 781b ldrb r3, [r3, #0] - 8001a4a: 2b00 cmp r3, #0 - 8001a4c: d1ce bne.n 80019ec - 8001a4e: e000 b.n 8001a52 - return; - 8001a50: bf00 nop -} - 8001a52: 3714 adds r7, #20 - 8001a54: 46bd mov sp, r7 - 8001a56: bd90 pop {r4, r7, pc} - -08001a58 : -void SSD1289_Print(uint16_t x, uint16_t y, char *string){ - SSD1289_Write_Back_Ground(Black); - SSD1289_Print_String(x, y, 1, 1, 1, White, Black, string); -} -void SSD1289_Draw_V_Line(uint16_t x1, uint16_t y1, uint16_t y2, uint16_t color) -{ - 8001a58: b590 push {r4, r7, lr} - 8001a5a: b083 sub sp, #12 - 8001a5c: af00 add r7, sp, #0 - 8001a5e: 4604 mov r4, r0 - 8001a60: 4608 mov r0, r1 - 8001a62: 4611 mov r1, r2 - 8001a64: 461a mov r2, r3 - 8001a66: 4623 mov r3, r4 - 8001a68: 80fb strh r3, [r7, #6] - 8001a6a: 4603 mov r3, r0 - 8001a6c: 80bb strh r3, [r7, #4] - 8001a6e: 460b mov r3, r1 - 8001a70: 807b strh r3, [r7, #2] - 8001a72: 4613 mov r3, r2 - 8001a74: 803b strh r3, [r7, #0] - - if(y1 > y2) - 8001a76: 88ba ldrh r2, [r7, #4] - 8001a78: 887b ldrh r3, [r7, #2] - 8001a7a: 429a cmp r2, r3 - 8001a7c: d910 bls.n 8001aa0 - { - swap(&y1, &y2); - 8001a7e: 1cba adds r2, r7, #2 - 8001a80: 1d3b adds r3, r7, #4 - 8001a82: 4611 mov r1, r2 - 8001a84: 4618 mov r0, r3 - 8001a86: f7ff fdb0 bl 80015ea - } - - while(y2 > (y1-1)) - 8001a8a: e009 b.n 8001aa0 - { - SSD1289_Write_Pixel(x1, y2, color); - 8001a8c: 8879 ldrh r1, [r7, #2] - 8001a8e: 883a ldrh r2, [r7, #0] - 8001a90: 88fb ldrh r3, [r7, #6] - 8001a92: 4618 mov r0, r3 - 8001a94: f7ff fe70 bl 8001778 - y2--; - 8001a98: 887b ldrh r3, [r7, #2] - 8001a9a: 3b01 subs r3, #1 - 8001a9c: b29b uxth r3, r3 - 8001a9e: 807b strh r3, [r7, #2] - while(y2 > (y1-1)) - 8001aa0: 88ba ldrh r2, [r7, #4] - 8001aa2: 887b ldrh r3, [r7, #2] - 8001aa4: 429a cmp r2, r3 - 8001aa6: d9f1 bls.n 8001a8c - } -} - 8001aa8: bf00 nop - 8001aaa: bf00 nop - 8001aac: 370c adds r7, #12 - 8001aae: 46bd mov sp, r7 - 8001ab0: bd90 pop {r4, r7, pc} - -08001ab2 : - } - } -} - -void SSD1289_Write_Back_Ground(uint16_t color) -{ - 8001ab2: b580 push {r7, lr} - 8001ab4: b084 sub sp, #16 - 8001ab6: af00 add r7, sp, #0 - 8001ab8: 4603 mov r3, r0 - 8001aba: 80fb strh r3, [r7, #6] - uint16_t x = 0, y = 0; - 8001abc: 2300 movs r3, #0 - 8001abe: 81fb strh r3, [r7, #14] - 8001ac0: 2300 movs r3, #0 - 8001ac2: 81bb strh r3, [r7, #12] - for(y = 0; y < 240; y++){ - 8001ac4: 2300 movs r3, #0 - 8001ac6: 81bb strh r3, [r7, #12] - 8001ac8: e012 b.n 8001af0 - for(x = 0; x < 320; x++){ - 8001aca: 2300 movs r3, #0 - 8001acc: 81fb strh r3, [r7, #14] - 8001ace: e008 b.n 8001ae2 - SSD1289_Write_Pixel(x, y, color); - 8001ad0: 88fa ldrh r2, [r7, #6] - 8001ad2: 89b9 ldrh r1, [r7, #12] - 8001ad4: 89fb ldrh r3, [r7, #14] - 8001ad6: 4618 mov r0, r3 - 8001ad8: f7ff fe4e bl 8001778 - for(x = 0; x < 320; x++){ - 8001adc: 89fb ldrh r3, [r7, #14] - 8001ade: 3301 adds r3, #1 - 8001ae0: 81fb strh r3, [r7, #14] - 8001ae2: 89fb ldrh r3, [r7, #14] - 8001ae4: f5b3 7fa0 cmp.w r3, #320 ; 0x140 - 8001ae8: d3f2 bcc.n 8001ad0 - for(y = 0; y < 240; y++){ - 8001aea: 89bb ldrh r3, [r7, #12] - 8001aec: 3301 adds r3, #1 - 8001aee: 81bb strh r3, [r7, #12] - 8001af0: 89bb ldrh r3, [r7, #12] - 8001af2: 2bef cmp r3, #239 ; 0xef - 8001af4: d9e9 bls.n 8001aca - } - } -} - 8001af6: bf00 nop - 8001af8: bf00 nop - 8001afa: 3710 adds r7, #16 - 8001afc: 46bd mov sp, r7 - 8001afe: bd80 pop {r7, pc} - -08001b00 : -void SSD1289_Clear_Screen(){ - 8001b00: b580 push {r7, lr} - 8001b02: af00 add r7, sp, #0 - SSD1289_Write_Back_Ground(White); - 8001b04: f64f 70ff movw r0, #65535 ; 0xffff - 8001b08: f7ff ffd3 bl 8001ab2 -} - 8001b0c: bf00 nop - 8001b0e: bd80 pop {r7, pc} - -08001b10 : -void SSD1289_Init(void) -{ - 8001b10: b580 push {r7, lr} - 8001b12: af00 add r7, sp, #0 - - RST; - 8001b14: 2201 movs r2, #1 - 8001b16: 2108 movs r1, #8 - 8001b18: 48ac ldr r0, [pc, #688] ; (8001dcc ) - 8001b1a: f000 fedb bl 80028d4 - HAL_Delay(100); - 8001b1e: 2064 movs r0, #100 ; 0x64 - 8001b20: f000 fc1a bl 8002358 - RSTN;; - 8001b24: 2200 movs r2, #0 - 8001b26: 2108 movs r1, #8 - 8001b28: 48a8 ldr r0, [pc, #672] ; (8001dcc ) - 8001b2a: f000 fed3 bl 80028d4 - HAL_Delay(100); - 8001b2e: 2064 movs r0, #100 ; 0x64 - 8001b30: f000 fc12 bl 8002358 - RST; - 8001b34: 2201 movs r2, #1 - 8001b36: 2108 movs r1, #8 - 8001b38: 48a4 ldr r0, [pc, #656] ; (8001dcc ) - 8001b3a: f000 fecb bl 80028d4 - CS; - 8001b3e: 2201 movs r2, #1 - 8001b40: f44f 6180 mov.w r1, #1024 ; 0x400 - 8001b44: 48a2 ldr r0, [pc, #648] ; (8001dd0 ) - 8001b46: f000 fec5 bl 80028d4 - RD; - 8001b4a: 2201 movs r2, #1 - 8001b4c: 2110 movs r1, #16 - 8001b4e: 489f ldr r0, [pc, #636] ; (8001dcc ) - 8001b50: f000 fec0 bl 80028d4 - WR; - 8001b54: 2201 movs r2, #1 - 8001b56: 2120 movs r1, #32 - 8001b58: 489c ldr r0, [pc, #624] ; (8001dcc ) - 8001b5a: f000 febb bl 80028d4 - HAL_Delay(100); - 8001b5e: 2064 movs r0, #100 ; 0x64 - 8001b60: f000 fbfa bl 8002358 - - SSD1289_Write_Com_Data(0x0000,0x0001); HAL_Delay(1); - 8001b64: 2101 movs r1, #1 - 8001b66: 2000 movs r0, #0 - 8001b68: f7ff fdb2 bl 80016d0 - 8001b6c: 2001 movs r0, #1 - 8001b6e: f000 fbf3 bl 8002358 - SSD1289_Write_Com_Data(0x0003,0xA8A4); HAL_Delay(1); - 8001b72: f64a 01a4 movw r1, #43172 ; 0xa8a4 - 8001b76: 2003 movs r0, #3 - 8001b78: f7ff fdaa bl 80016d0 - 8001b7c: 2001 movs r0, #1 - 8001b7e: f000 fbeb bl 8002358 - SSD1289_Write_Com_Data(0x000C,0x0000); HAL_Delay(1); - 8001b82: 2100 movs r1, #0 - 8001b84: 200c movs r0, #12 - 8001b86: f7ff fda3 bl 80016d0 - 8001b8a: 2001 movs r0, #1 - 8001b8c: f000 fbe4 bl 8002358 - SSD1289_Write_Com_Data(0x000D,0x080C); HAL_Delay(1); - 8001b90: f640 010c movw r1, #2060 ; 0x80c - 8001b94: 200d movs r0, #13 - 8001b96: f7ff fd9b bl 80016d0 - 8001b9a: 2001 movs r0, #1 - 8001b9c: f000 fbdc bl 8002358 - SSD1289_Write_Com_Data(0x000E,0x2B00); HAL_Delay(1); - 8001ba0: f44f 512c mov.w r1, #11008 ; 0x2b00 - 8001ba4: 200e movs r0, #14 - 8001ba6: f7ff fd93 bl 80016d0 - 8001baa: 2001 movs r0, #1 - 8001bac: f000 fbd4 bl 8002358 - SSD1289_Write_Com_Data(0x001E,0x00B0); HAL_Delay(1); - 8001bb0: 21b0 movs r1, #176 ; 0xb0 - 8001bb2: 201e movs r0, #30 - 8001bb4: f7ff fd8c bl 80016d0 - 8001bb8: 2001 movs r0, #1 - 8001bba: f000 fbcd bl 8002358 - SSD1289_Write_Com_Data(0x0001,0x293F); HAL_Delay(1); - 8001bbe: f642 113f movw r1, #10559 ; 0x293f - 8001bc2: 2001 movs r0, #1 - 8001bc4: f7ff fd84 bl 80016d0 - 8001bc8: 2001 movs r0, #1 - 8001bca: f000 fbc5 bl 8002358 - SSD1289_Write_Com_Data(0x0002,0x0600); HAL_Delay(1); - 8001bce: f44f 61c0 mov.w r1, #1536 ; 0x600 - 8001bd2: 2002 movs r0, #2 - 8001bd4: f7ff fd7c bl 80016d0 - 8001bd8: 2001 movs r0, #1 - 8001bda: f000 fbbd bl 8002358 - SSD1289_Write_Com_Data(0x0010,0x0000); HAL_Delay(1); - 8001bde: 2100 movs r1, #0 - 8001be0: 2010 movs r0, #16 - 8001be2: f7ff fd75 bl 80016d0 - 8001be6: 2001 movs r0, #1 - 8001be8: f000 fbb6 bl 8002358 - SSD1289_Write_Com_Data(0x0011,0x6070); HAL_Delay(1); - 8001bec: f246 0170 movw r1, #24688 ; 0x6070 - 8001bf0: 2011 movs r0, #17 - 8001bf2: f7ff fd6d bl 80016d0 - 8001bf6: 2001 movs r0, #1 - 8001bf8: f000 fbae bl 8002358 - SSD1289_Write_Com_Data(0x0005,0x0000); HAL_Delay(1); - 8001bfc: 2100 movs r1, #0 - 8001bfe: 2005 movs r0, #5 - 8001c00: f7ff fd66 bl 80016d0 - 8001c04: 2001 movs r0, #1 - 8001c06: f000 fba7 bl 8002358 - SSD1289_Write_Com_Data(0x0006,0x0000); HAL_Delay(1); - 8001c0a: 2100 movs r1, #0 - 8001c0c: 2006 movs r0, #6 - 8001c0e: f7ff fd5f bl 80016d0 - 8001c12: 2001 movs r0, #1 - 8001c14: f000 fba0 bl 8002358 - SSD1289_Write_Com_Data(0x0016,0xEF1C); HAL_Delay(1); - 8001c18: f64e 711c movw r1, #61212 ; 0xef1c - 8001c1c: 2016 movs r0, #22 - 8001c1e: f7ff fd57 bl 80016d0 - 8001c22: 2001 movs r0, #1 - 8001c24: f000 fb98 bl 8002358 - SSD1289_Write_Com_Data(0x0017,0x0003); HAL_Delay(1); - 8001c28: 2103 movs r1, #3 - 8001c2a: 2017 movs r0, #23 - 8001c2c: f7ff fd50 bl 80016d0 - 8001c30: 2001 movs r0, #1 - 8001c32: f000 fb91 bl 8002358 - SSD1289_Write_Com_Data(0x0007,0x0233); HAL_Delay(1); - 8001c36: f240 2133 movw r1, #563 ; 0x233 - 8001c3a: 2007 movs r0, #7 - 8001c3c: f7ff fd48 bl 80016d0 - 8001c40: 2001 movs r0, #1 - 8001c42: f000 fb89 bl 8002358 - SSD1289_Write_Com_Data(0x000B,0x0000); HAL_Delay(1); - 8001c46: 2100 movs r1, #0 - 8001c48: 200b movs r0, #11 - 8001c4a: f7ff fd41 bl 80016d0 - 8001c4e: 2001 movs r0, #1 - 8001c50: f000 fb82 bl 8002358 - SSD1289_Write_Com_Data(0x000F,0x0000); HAL_Delay(1); - 8001c54: 2100 movs r1, #0 - 8001c56: 200f movs r0, #15 - 8001c58: f7ff fd3a bl 80016d0 - 8001c5c: 2001 movs r0, #1 - 8001c5e: f000 fb7b bl 8002358 - SSD1289_Write_Com_Data(0x0041,0x0000); HAL_Delay(1); - 8001c62: 2100 movs r1, #0 - 8001c64: 2041 movs r0, #65 ; 0x41 - 8001c66: f7ff fd33 bl 80016d0 - 8001c6a: 2001 movs r0, #1 - 8001c6c: f000 fb74 bl 8002358 - SSD1289_Write_Com_Data(0x0042,0x0000); HAL_Delay(1); - 8001c70: 2100 movs r1, #0 - 8001c72: 2042 movs r0, #66 ; 0x42 - 8001c74: f7ff fd2c bl 80016d0 - 8001c78: 2001 movs r0, #1 - 8001c7a: f000 fb6d bl 8002358 - SSD1289_Write_Com_Data(0x0048,0x0000); HAL_Delay(1); - 8001c7e: 2100 movs r1, #0 - 8001c80: 2048 movs r0, #72 ; 0x48 - 8001c82: f7ff fd25 bl 80016d0 - 8001c86: 2001 movs r0, #1 - 8001c88: f000 fb66 bl 8002358 - SSD1289_Write_Com_Data(0x0049,0x013F); HAL_Delay(1); - 8001c8c: f240 113f movw r1, #319 ; 0x13f - 8001c90: 2049 movs r0, #73 ; 0x49 - 8001c92: f7ff fd1d bl 80016d0 - 8001c96: 2001 movs r0, #1 - 8001c98: f000 fb5e bl 8002358 - SSD1289_Write_Com_Data(0x004A,0x0000); HAL_Delay(1); - 8001c9c: 2100 movs r1, #0 - 8001c9e: 204a movs r0, #74 ; 0x4a - 8001ca0: f7ff fd16 bl 80016d0 - 8001ca4: 2001 movs r0, #1 - 8001ca6: f000 fb57 bl 8002358 - SSD1289_Write_Com_Data(0x004B,0x0000); HAL_Delay(1); - 8001caa: 2100 movs r1, #0 - 8001cac: 204b movs r0, #75 ; 0x4b - 8001cae: f7ff fd0f bl 80016d0 - 8001cb2: 2001 movs r0, #1 - 8001cb4: f000 fb50 bl 8002358 - SSD1289_Write_Com_Data(0x0044,0xEF00); HAL_Delay(1); - 8001cb8: f44f 416f mov.w r1, #61184 ; 0xef00 - 8001cbc: 2044 movs r0, #68 ; 0x44 - 8001cbe: f7ff fd07 bl 80016d0 - 8001cc2: 2001 movs r0, #1 - 8001cc4: f000 fb48 bl 8002358 - SSD1289_Write_Com_Data(0x0045,0x0000); HAL_Delay(1); - 8001cc8: 2100 movs r1, #0 - 8001cca: 2045 movs r0, #69 ; 0x45 - 8001ccc: f7ff fd00 bl 80016d0 - 8001cd0: 2001 movs r0, #1 - 8001cd2: f000 fb41 bl 8002358 - SSD1289_Write_Com_Data(0x0046,0x013F); HAL_Delay(1); - 8001cd6: f240 113f movw r1, #319 ; 0x13f - 8001cda: 2046 movs r0, #70 ; 0x46 - 8001cdc: f7ff fcf8 bl 80016d0 - 8001ce0: 2001 movs r0, #1 - 8001ce2: f000 fb39 bl 8002358 - SSD1289_Write_Com_Data(0x0030,0x0707); HAL_Delay(1); - 8001ce6: f240 7107 movw r1, #1799 ; 0x707 - 8001cea: 2030 movs r0, #48 ; 0x30 - 8001cec: f7ff fcf0 bl 80016d0 - 8001cf0: 2001 movs r0, #1 - 8001cf2: f000 fb31 bl 8002358 - SSD1289_Write_Com_Data(0x0031,0x0204); HAL_Delay(1); - 8001cf6: f44f 7101 mov.w r1, #516 ; 0x204 - 8001cfa: 2031 movs r0, #49 ; 0x31 - 8001cfc: f7ff fce8 bl 80016d0 - 8001d00: 2001 movs r0, #1 - 8001d02: f000 fb29 bl 8002358 - SSD1289_Write_Com_Data(0x0032,0x0204); HAL_Delay(1); - 8001d06: f44f 7101 mov.w r1, #516 ; 0x204 - 8001d0a: 2032 movs r0, #50 ; 0x32 - 8001d0c: f7ff fce0 bl 80016d0 - 8001d10: 2001 movs r0, #1 - 8001d12: f000 fb21 bl 8002358 - SSD1289_Write_Com_Data(0x0033,0x0502); HAL_Delay(1); - 8001d16: f240 5102 movw r1, #1282 ; 0x502 - 8001d1a: 2033 movs r0, #51 ; 0x33 - 8001d1c: f7ff fcd8 bl 80016d0 - 8001d20: 2001 movs r0, #1 - 8001d22: f000 fb19 bl 8002358 - SSD1289_Write_Com_Data(0x0034,0x0507); HAL_Delay(1); - 8001d26: f240 5107 movw r1, #1287 ; 0x507 - 8001d2a: 2034 movs r0, #52 ; 0x34 - 8001d2c: f7ff fcd0 bl 80016d0 - 8001d30: 2001 movs r0, #1 - 8001d32: f000 fb11 bl 8002358 - SSD1289_Write_Com_Data(0x0035,0x0204); HAL_Delay(1); - 8001d36: f44f 7101 mov.w r1, #516 ; 0x204 - 8001d3a: 2035 movs r0, #53 ; 0x35 - 8001d3c: f7ff fcc8 bl 80016d0 - 8001d40: 2001 movs r0, #1 - 8001d42: f000 fb09 bl 8002358 - SSD1289_Write_Com_Data(0x0036,0x0204); HAL_Delay(1); - 8001d46: f44f 7101 mov.w r1, #516 ; 0x204 - 8001d4a: 2036 movs r0, #54 ; 0x36 - 8001d4c: f7ff fcc0 bl 80016d0 - 8001d50: 2001 movs r0, #1 - 8001d52: f000 fb01 bl 8002358 - SSD1289_Write_Com_Data(0x0037,0x0502); HAL_Delay(1); - 8001d56: f240 5102 movw r1, #1282 ; 0x502 - 8001d5a: 2037 movs r0, #55 ; 0x37 - 8001d5c: f7ff fcb8 bl 80016d0 - 8001d60: 2001 movs r0, #1 - 8001d62: f000 faf9 bl 8002358 - SSD1289_Write_Com_Data(0x003A,0x0302); HAL_Delay(1); - 8001d66: f240 3102 movw r1, #770 ; 0x302 - 8001d6a: 203a movs r0, #58 ; 0x3a - 8001d6c: f7ff fcb0 bl 80016d0 - 8001d70: 2001 movs r0, #1 - 8001d72: f000 faf1 bl 8002358 - SSD1289_Write_Com_Data(0x003B,0x0302); HAL_Delay(1); - 8001d76: f240 3102 movw r1, #770 ; 0x302 - 8001d7a: 203b movs r0, #59 ; 0x3b - 8001d7c: f7ff fca8 bl 80016d0 - 8001d80: 2001 movs r0, #1 - 8001d82: f000 fae9 bl 8002358 - SSD1289_Write_Com_Data(0x0023,0x0000); HAL_Delay(1); - 8001d86: 2100 movs r1, #0 - 8001d88: 2023 movs r0, #35 ; 0x23 - 8001d8a: f7ff fca1 bl 80016d0 - 8001d8e: 2001 movs r0, #1 - 8001d90: f000 fae2 bl 8002358 - SSD1289_Write_Com_Data(0x0024,0x0000); HAL_Delay(1); - 8001d94: 2100 movs r1, #0 - 8001d96: 2024 movs r0, #36 ; 0x24 - 8001d98: f7ff fc9a bl 80016d0 - 8001d9c: 2001 movs r0, #1 - 8001d9e: f000 fadb bl 8002358 - SSD1289_Write_Com_Data(0x0025,0x8000); HAL_Delay(1); - 8001da2: f44f 4100 mov.w r1, #32768 ; 0x8000 - 8001da6: 2025 movs r0, #37 ; 0x25 - 8001da8: f7ff fc92 bl 80016d0 - 8001dac: 2001 movs r0, #1 - 8001dae: f000 fad3 bl 8002358 - SSD1289_Write_Com_Data(0x004f,0); - 8001db2: 2100 movs r1, #0 - 8001db4: 204f movs r0, #79 ; 0x4f - 8001db6: f7ff fc8b bl 80016d0 - SSD1289_Write_Com_Data(0x004e,0); - 8001dba: 2100 movs r1, #0 - 8001dbc: 204e movs r0, #78 ; 0x4e - 8001dbe: f7ff fc87 bl 80016d0 - SSD1289_Write_Com(0x0022); - 8001dc2: 2022 movs r0, #34 ; 0x22 - 8001dc4: f7ff fc28 bl 8001618 -} - 8001dc8: bf00 nop - 8001dca: bd80 pop {r7, pc} - 8001dcc: 40020c00 .word 0x40020c00 - 8001dd0: 40020400 .word 0x40020400 - -08001dd4 : -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - 8001dd4: b580 push {r7, lr} - 8001dd6: b082 sub sp, #8 - 8001dd8: af00 add r7, sp, #0 - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8001dda: 2300 movs r3, #0 - 8001ddc: 607b str r3, [r7, #4] - 8001dde: 4b10 ldr r3, [pc, #64] ; (8001e20 ) - 8001de0: 6c5b ldr r3, [r3, #68] ; 0x44 - 8001de2: 4a0f ldr r2, [pc, #60] ; (8001e20 ) - 8001de4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8001de8: 6453 str r3, [r2, #68] ; 0x44 - 8001dea: 4b0d ldr r3, [pc, #52] ; (8001e20 ) - 8001dec: 6c5b ldr r3, [r3, #68] ; 0x44 - 8001dee: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8001df2: 607b str r3, [r7, #4] - 8001df4: 687b ldr r3, [r7, #4] - __HAL_RCC_PWR_CLK_ENABLE(); - 8001df6: 2300 movs r3, #0 - 8001df8: 603b str r3, [r7, #0] - 8001dfa: 4b09 ldr r3, [pc, #36] ; (8001e20 ) - 8001dfc: 6c1b ldr r3, [r3, #64] ; 0x40 - 8001dfe: 4a08 ldr r2, [pc, #32] ; (8001e20 ) - 8001e00: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8001e04: 6413 str r3, [r2, #64] ; 0x40 - 8001e06: 4b06 ldr r3, [pc, #24] ; (8001e20 ) - 8001e08: 6c1b ldr r3, [r3, #64] ; 0x40 - 8001e0a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001e0e: 603b str r3, [r7, #0] - 8001e10: 683b ldr r3, [r7, #0] - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); - 8001e12: 2007 movs r0, #7 - 8001e14: f000 fb76 bl 8002504 - /* System interrupt init*/ - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - 8001e18: bf00 nop - 8001e1a: 3708 adds r7, #8 - 8001e1c: 46bd mov sp, r7 - 8001e1e: bd80 pop {r7, pc} - 8001e20: 40023800 .word 0x40023800 - -08001e24 : -* This function configures the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) -{ - 8001e24: b580 push {r7, lr} - 8001e26: b08a sub sp, #40 ; 0x28 - 8001e28: af00 add r7, sp, #0 - 8001e2a: 6078 str r0, [r7, #4] - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001e2c: f107 0314 add.w r3, r7, #20 - 8001e30: 2200 movs r2, #0 - 8001e32: 601a str r2, [r3, #0] - 8001e34: 605a str r2, [r3, #4] - 8001e36: 609a str r2, [r3, #8] - 8001e38: 60da str r2, [r3, #12] - 8001e3a: 611a str r2, [r3, #16] - if(hspi->Instance==SPI3) - 8001e3c: 687b ldr r3, [r7, #4] - 8001e3e: 681b ldr r3, [r3, #0] - 8001e40: 4a19 ldr r2, [pc, #100] ; (8001ea8 ) - 8001e42: 4293 cmp r3, r2 - 8001e44: d12b bne.n 8001e9e - { - /* USER CODE BEGIN SPI3_MspInit 0 */ - - /* USER CODE END SPI3_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_SPI3_CLK_ENABLE(); - 8001e46: 2300 movs r3, #0 - 8001e48: 613b str r3, [r7, #16] - 8001e4a: 4b18 ldr r3, [pc, #96] ; (8001eac ) - 8001e4c: 6c1b ldr r3, [r3, #64] ; 0x40 - 8001e4e: 4a17 ldr r2, [pc, #92] ; (8001eac ) - 8001e50: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8001e54: 6413 str r3, [r2, #64] ; 0x40 - 8001e56: 4b15 ldr r3, [pc, #84] ; (8001eac ) - 8001e58: 6c1b ldr r3, [r3, #64] ; 0x40 - 8001e5a: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8001e5e: 613b str r3, [r7, #16] - 8001e60: 693b ldr r3, [r7, #16] - - __HAL_RCC_GPIOB_CLK_ENABLE(); - 8001e62: 2300 movs r3, #0 - 8001e64: 60fb str r3, [r7, #12] - 8001e66: 4b11 ldr r3, [pc, #68] ; (8001eac ) - 8001e68: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001e6a: 4a10 ldr r2, [pc, #64] ; (8001eac ) - 8001e6c: f043 0302 orr.w r3, r3, #2 - 8001e70: 6313 str r3, [r2, #48] ; 0x30 - 8001e72: 4b0e ldr r3, [pc, #56] ; (8001eac ) - 8001e74: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001e76: f003 0302 and.w r3, r3, #2 - 8001e7a: 60fb str r3, [r7, #12] - 8001e7c: 68fb ldr r3, [r7, #12] - /**SPI3 GPIO Configuration - PB3 ------> SPI3_SCK - PB4 ------> SPI3_MISO - PB5 ------> SPI3_MOSI - */ - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5; - 8001e7e: 2338 movs r3, #56 ; 0x38 - 8001e80: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8001e82: 2302 movs r3, #2 - 8001e84: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8001e86: 2300 movs r3, #0 - 8001e88: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8001e8a: 2303 movs r3, #3 - 8001e8c: 623b str r3, [r7, #32] - GPIO_InitStruct.Alternate = GPIO_AF6_SPI3; - 8001e8e: 2306 movs r3, #6 - 8001e90: 627b str r3, [r7, #36] ; 0x24 - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8001e92: f107 0314 add.w r3, r7, #20 - 8001e96: 4619 mov r1, r3 - 8001e98: 4805 ldr r0, [pc, #20] ; (8001eb0 ) - 8001e9a: f000 fb67 bl 800256c - /* USER CODE BEGIN SPI3_MspInit 1 */ - - /* USER CODE END SPI3_MspInit 1 */ - } - -} - 8001e9e: bf00 nop - 8001ea0: 3728 adds r7, #40 ; 0x28 - 8001ea2: 46bd mov sp, r7 - 8001ea4: bd80 pop {r7, pc} - 8001ea6: bf00 nop - 8001ea8: 40003c00 .word 0x40003c00 - 8001eac: 40023800 .word 0x40023800 - 8001eb0: 40020400 .word 0x40020400 - -08001eb4 : -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - 8001eb4: b480 push {r7} - 8001eb6: af00 add r7, sp, #0 - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - 8001eb8: e7fe b.n 8001eb8 - -08001eba : - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - 8001eba: b480 push {r7} - 8001ebc: af00 add r7, sp, #0 - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - 8001ebe: e7fe b.n 8001ebe - -08001ec0 : - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - 8001ec0: b480 push {r7} - 8001ec2: af00 add r7, sp, #0 - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - 8001ec4: e7fe b.n 8001ec4 - -08001ec6 : - -/** - * @brief This function handles Pre-fetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - 8001ec6: b480 push {r7} - 8001ec8: af00 add r7, sp, #0 - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - 8001eca: e7fe b.n 8001eca - -08001ecc : - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - 8001ecc: b480 push {r7} - 8001ece: af00 add r7, sp, #0 - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - 8001ed0: e7fe b.n 8001ed0 - -08001ed2 : - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - 8001ed2: b480 push {r7} - 8001ed4: af00 add r7, sp, #0 - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - 8001ed6: bf00 nop - 8001ed8: 46bd mov sp, r7 - 8001eda: f85d 7b04 ldr.w r7, [sp], #4 - 8001ede: 4770 bx lr - -08001ee0 : - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - 8001ee0: b480 push {r7} - 8001ee2: af00 add r7, sp, #0 - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - 8001ee4: bf00 nop - 8001ee6: 46bd mov sp, r7 - 8001ee8: f85d 7b04 ldr.w r7, [sp], #4 - 8001eec: 4770 bx lr - -08001eee : - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - 8001eee: b480 push {r7} - 8001ef0: af00 add r7, sp, #0 - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - 8001ef2: bf00 nop - 8001ef4: 46bd mov sp, r7 - 8001ef6: f85d 7b04 ldr.w r7, [sp], #4 - 8001efa: 4770 bx lr - -08001efc : - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - 8001efc: b580 push {r7, lr} - 8001efe: af00 add r7, sp, #0 - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - 8001f00: f000 fa0a bl 8002318 - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - 8001f04: bf00 nop - 8001f06: bd80 pop {r7, pc} - -08001f08 <_getpid>: -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - 8001f08: b480 push {r7} - 8001f0a: af00 add r7, sp, #0 - return 1; - 8001f0c: 2301 movs r3, #1 -} - 8001f0e: 4618 mov r0, r3 - 8001f10: 46bd mov sp, r7 - 8001f12: f85d 7b04 ldr.w r7, [sp], #4 - 8001f16: 4770 bx lr - -08001f18 <_kill>: - -int _kill(int pid, int sig) -{ - 8001f18: b580 push {r7, lr} - 8001f1a: b082 sub sp, #8 - 8001f1c: af00 add r7, sp, #0 - 8001f1e: 6078 str r0, [r7, #4] - 8001f20: 6039 str r1, [r7, #0] - errno = EINVAL; - 8001f22: f001 fd87 bl 8003a34 <__errno> - 8001f26: 4603 mov r3, r0 - 8001f28: 2216 movs r2, #22 - 8001f2a: 601a str r2, [r3, #0] - return -1; - 8001f2c: f04f 33ff mov.w r3, #4294967295 -} - 8001f30: 4618 mov r0, r3 - 8001f32: 3708 adds r7, #8 - 8001f34: 46bd mov sp, r7 - 8001f36: bd80 pop {r7, pc} - -08001f38 <_exit>: - -void _exit (int status) -{ - 8001f38: b580 push {r7, lr} - 8001f3a: b082 sub sp, #8 - 8001f3c: af00 add r7, sp, #0 - 8001f3e: 6078 str r0, [r7, #4] - _kill(status, -1); - 8001f40: f04f 31ff mov.w r1, #4294967295 - 8001f44: 6878 ldr r0, [r7, #4] - 8001f46: f7ff ffe7 bl 8001f18 <_kill> - while (1) {} /* Make sure we hang here */ - 8001f4a: e7fe b.n 8001f4a <_exit+0x12> - -08001f4c <_read>: -} - -__attribute__((weak)) int _read(int file, char *ptr, int len) -{ - 8001f4c: b580 push {r7, lr} - 8001f4e: b086 sub sp, #24 - 8001f50: af00 add r7, sp, #0 - 8001f52: 60f8 str r0, [r7, #12] - 8001f54: 60b9 str r1, [r7, #8] - 8001f56: 607a str r2, [r7, #4] - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001f58: 2300 movs r3, #0 - 8001f5a: 617b str r3, [r7, #20] - 8001f5c: e00a b.n 8001f74 <_read+0x28> - { - *ptr++ = __io_getchar(); - 8001f5e: f3af 8000 nop.w - 8001f62: 4601 mov r1, r0 - 8001f64: 68bb ldr r3, [r7, #8] - 8001f66: 1c5a adds r2, r3, #1 - 8001f68: 60ba str r2, [r7, #8] - 8001f6a: b2ca uxtb r2, r1 - 8001f6c: 701a strb r2, [r3, #0] - for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001f6e: 697b ldr r3, [r7, #20] - 8001f70: 3301 adds r3, #1 - 8001f72: 617b str r3, [r7, #20] - 8001f74: 697a ldr r2, [r7, #20] - 8001f76: 687b ldr r3, [r7, #4] - 8001f78: 429a cmp r2, r3 - 8001f7a: dbf0 blt.n 8001f5e <_read+0x12> - } - -return len; - 8001f7c: 687b ldr r3, [r7, #4] -} - 8001f7e: 4618 mov r0, r3 - 8001f80: 3718 adds r7, #24 - 8001f82: 46bd mov sp, r7 - 8001f84: bd80 pop {r7, pc} - -08001f86 <_write>: - -__attribute__((weak)) int _write(int file, char *ptr, int len) -{ - 8001f86: b580 push {r7, lr} - 8001f88: b086 sub sp, #24 - 8001f8a: af00 add r7, sp, #0 - 8001f8c: 60f8 str r0, [r7, #12] - 8001f8e: 60b9 str r1, [r7, #8] - 8001f90: 607a str r2, [r7, #4] - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001f92: 2300 movs r3, #0 - 8001f94: 617b str r3, [r7, #20] - 8001f96: e009 b.n 8001fac <_write+0x26> - { - __io_putchar(*ptr++); - 8001f98: 68bb ldr r3, [r7, #8] - 8001f9a: 1c5a adds r2, r3, #1 - 8001f9c: 60ba str r2, [r7, #8] - 8001f9e: 781b ldrb r3, [r3, #0] - 8001fa0: 4618 mov r0, r3 - 8001fa2: f3af 8000 nop.w - for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001fa6: 697b ldr r3, [r7, #20] - 8001fa8: 3301 adds r3, #1 - 8001faa: 617b str r3, [r7, #20] - 8001fac: 697a ldr r2, [r7, #20] - 8001fae: 687b ldr r3, [r7, #4] - 8001fb0: 429a cmp r2, r3 - 8001fb2: dbf1 blt.n 8001f98 <_write+0x12> - } - return len; - 8001fb4: 687b ldr r3, [r7, #4] -} - 8001fb6: 4618 mov r0, r3 - 8001fb8: 3718 adds r7, #24 - 8001fba: 46bd mov sp, r7 - 8001fbc: bd80 pop {r7, pc} - -08001fbe <_close>: - -int _close(int file) -{ - 8001fbe: b480 push {r7} - 8001fc0: b083 sub sp, #12 - 8001fc2: af00 add r7, sp, #0 - 8001fc4: 6078 str r0, [r7, #4] - return -1; - 8001fc6: f04f 33ff mov.w r3, #4294967295 -} - 8001fca: 4618 mov r0, r3 - 8001fcc: 370c adds r7, #12 - 8001fce: 46bd mov sp, r7 - 8001fd0: f85d 7b04 ldr.w r7, [sp], #4 - 8001fd4: 4770 bx lr - -08001fd6 <_fstat>: - - -int _fstat(int file, struct stat *st) -{ - 8001fd6: b480 push {r7} - 8001fd8: b083 sub sp, #12 - 8001fda: af00 add r7, sp, #0 - 8001fdc: 6078 str r0, [r7, #4] - 8001fde: 6039 str r1, [r7, #0] - st->st_mode = S_IFCHR; - 8001fe0: 683b ldr r3, [r7, #0] - 8001fe2: f44f 5200 mov.w r2, #8192 ; 0x2000 - 8001fe6: 605a str r2, [r3, #4] - return 0; - 8001fe8: 2300 movs r3, #0 -} - 8001fea: 4618 mov r0, r3 - 8001fec: 370c adds r7, #12 - 8001fee: 46bd mov sp, r7 - 8001ff0: f85d 7b04 ldr.w r7, [sp], #4 - 8001ff4: 4770 bx lr - -08001ff6 <_isatty>: - -int _isatty(int file) -{ - 8001ff6: b480 push {r7} - 8001ff8: b083 sub sp, #12 - 8001ffa: af00 add r7, sp, #0 - 8001ffc: 6078 str r0, [r7, #4] - return 1; - 8001ffe: 2301 movs r3, #1 -} - 8002000: 4618 mov r0, r3 - 8002002: 370c adds r7, #12 - 8002004: 46bd mov sp, r7 - 8002006: f85d 7b04 ldr.w r7, [sp], #4 - 800200a: 4770 bx lr - -0800200c <_lseek>: - -int _lseek(int file, int ptr, int dir) -{ - 800200c: b480 push {r7} - 800200e: b085 sub sp, #20 - 8002010: af00 add r7, sp, #0 - 8002012: 60f8 str r0, [r7, #12] - 8002014: 60b9 str r1, [r7, #8] - 8002016: 607a str r2, [r7, #4] - return 0; - 8002018: 2300 movs r3, #0 -} - 800201a: 4618 mov r0, r3 - 800201c: 3714 adds r7, #20 - 800201e: 46bd mov sp, r7 - 8002020: f85d 7b04 ldr.w r7, [sp], #4 - 8002024: 4770 bx lr - ... - -08002028 <_sbrk>: - * - * @param incr Memory size - * @return Pointer to allocated memory - */ -void *_sbrk(ptrdiff_t incr) -{ - 8002028: b580 push {r7, lr} - 800202a: b086 sub sp, #24 - 800202c: af00 add r7, sp, #0 - 800202e: 6078 str r0, [r7, #4] - extern uint8_t _end; /* Symbol defined in the linker script */ - extern uint8_t _estack; /* Symbol defined in the linker script */ - extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ - const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - 8002030: 4a14 ldr r2, [pc, #80] ; (8002084 <_sbrk+0x5c>) - 8002032: 4b15 ldr r3, [pc, #84] ; (8002088 <_sbrk+0x60>) - 8002034: 1ad3 subs r3, r2, r3 - 8002036: 617b str r3, [r7, #20] - const uint8_t *max_heap = (uint8_t *)stack_limit; - 8002038: 697b ldr r3, [r7, #20] - 800203a: 613b str r3, [r7, #16] - uint8_t *prev_heap_end; - - /* Initialize heap end at first call */ - if (NULL == __sbrk_heap_end) - 800203c: 4b13 ldr r3, [pc, #76] ; (800208c <_sbrk+0x64>) - 800203e: 681b ldr r3, [r3, #0] - 8002040: 2b00 cmp r3, #0 - 8002042: d102 bne.n 800204a <_sbrk+0x22> - { - __sbrk_heap_end = &_end; - 8002044: 4b11 ldr r3, [pc, #68] ; (800208c <_sbrk+0x64>) - 8002046: 4a12 ldr r2, [pc, #72] ; (8002090 <_sbrk+0x68>) - 8002048: 601a str r2, [r3, #0] - } - - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - 800204a: 4b10 ldr r3, [pc, #64] ; (800208c <_sbrk+0x64>) - 800204c: 681a ldr r2, [r3, #0] - 800204e: 687b ldr r3, [r7, #4] - 8002050: 4413 add r3, r2 - 8002052: 693a ldr r2, [r7, #16] - 8002054: 429a cmp r2, r3 - 8002056: d207 bcs.n 8002068 <_sbrk+0x40> - { - errno = ENOMEM; - 8002058: f001 fcec bl 8003a34 <__errno> - 800205c: 4603 mov r3, r0 - 800205e: 220c movs r2, #12 - 8002060: 601a str r2, [r3, #0] - return (void *)-1; - 8002062: f04f 33ff mov.w r3, #4294967295 - 8002066: e009 b.n 800207c <_sbrk+0x54> - } - - prev_heap_end = __sbrk_heap_end; - 8002068: 4b08 ldr r3, [pc, #32] ; (800208c <_sbrk+0x64>) - 800206a: 681b ldr r3, [r3, #0] - 800206c: 60fb str r3, [r7, #12] - __sbrk_heap_end += incr; - 800206e: 4b07 ldr r3, [pc, #28] ; (800208c <_sbrk+0x64>) - 8002070: 681a ldr r2, [r3, #0] - 8002072: 687b ldr r3, [r7, #4] - 8002074: 4413 add r3, r2 - 8002076: 4a05 ldr r2, [pc, #20] ; (800208c <_sbrk+0x64>) - 8002078: 6013 str r3, [r2, #0] - - return (void *)prev_heap_end; - 800207a: 68fb ldr r3, [r7, #12] -} - 800207c: 4618 mov r0, r3 - 800207e: 3718 adds r7, #24 - 8002080: 46bd mov sp, r7 - 8002082: bd80 pop {r7, pc} - 8002084: 20020000 .word 0x20020000 - 8002088: 00000400 .word 0x00000400 - 800208c: 20002790 .word 0x20002790 - 8002090: 200027b0 .word 0x200027b0 - -08002094 : - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - 8002094: b480 push {r7} - 8002096: af00 add r7, sp, #0 - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 8002098: 4b06 ldr r3, [pc, #24] ; (80020b4 ) - 800209a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800209e: 4a05 ldr r2, [pc, #20] ; (80020b4 ) - 80020a0: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 80020a4: f8c2 3088 str.w r3, [r2, #136] ; 0x88 - - /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ -} - 80020a8: bf00 nop - 80020aa: 46bd mov sp, r7 - 80020ac: f85d 7b04 ldr.w r7, [sp], #4 - 80020b0: 4770 bx lr - 80020b2: bf00 nop - 80020b4: e000ed00 .word 0xe000ed00 - -080020b8 : - -extern SPI_HandleTypeDef hspi3; -volatile uint8_t receive_data = 0; -volatile uint8_t send_cmd; - -uint8_t Read_IRQ(){ - 80020b8: b580 push {r7, lr} - 80020ba: af00 add r7, sp, #0 - return HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_1); - 80020bc: 2102 movs r1, #2 - 80020be: 4803 ldr r0, [pc, #12] ; (80020cc ) - 80020c0: f000 fbf0 bl 80028a4 - 80020c4: 4603 mov r3, r0 -} - 80020c6: 4618 mov r0, r3 - 80020c8: bd80 pop {r7, pc} - 80020ca: bf00 nop - 80020cc: 40020c00 .word 0x40020c00 - -080020d0 : - -uint16_t XPT2046_Read(uint8_t cmd){ - 80020d0: b580 push {r7, lr} - 80020d2: b086 sub sp, #24 - 80020d4: af02 add r7, sp, #8 - 80020d6: 4603 mov r3, r0 - 80020d8: 71fb strb r3, [r7, #7] - uint16_t coor; - - T_CSN; - 80020da: 2200 movs r2, #0 - 80020dc: 2180 movs r1, #128 ; 0x80 - 80020de: 4820 ldr r0, [pc, #128] ; (8002160 ) - 80020e0: f000 fbf8 bl 80028d4 - send_cmd = cmd; - 80020e4: 4a1f ldr r2, [pc, #124] ; (8002164 ) - 80020e6: 79fb ldrb r3, [r7, #7] - 80020e8: 7013 strb r3, [r2, #0] - HAL_SPI_Transmit(&hspi3, (uint8_t*) &send_cmd, 1, 1000); - 80020ea: f44f 737a mov.w r3, #1000 ; 0x3e8 - 80020ee: 2201 movs r2, #1 - 80020f0: 491c ldr r1, [pc, #112] ; (8002164 ) - 80020f2: 481d ldr r0, [pc, #116] ; (8002168 ) - 80020f4: f001 f8f5 bl 80032e2 - send_cmd = 0x00; - 80020f8: 4b1a ldr r3, [pc, #104] ; (8002164 ) - 80020fa: 2200 movs r2, #0 - 80020fc: 701a strb r2, [r3, #0] - HAL_SPI_TransmitReceive(&hspi3, (uint8_t*) &send_cmd, (uint8_t*) &receive_data, 1, 1000); - 80020fe: f44f 737a mov.w r3, #1000 ; 0x3e8 - 8002102: 9300 str r3, [sp, #0] - 8002104: 2301 movs r3, #1 - 8002106: 4a19 ldr r2, [pc, #100] ; (800216c ) - 8002108: 4916 ldr r1, [pc, #88] ; (8002164 ) - 800210a: 4817 ldr r0, [pc, #92] ; (8002168 ) - 800210c: f001 fa25 bl 800355a - coor = (uint16_t) receive_data; - 8002110: 4b16 ldr r3, [pc, #88] ; (800216c ) - 8002112: 781b ldrb r3, [r3, #0] - 8002114: b2db uxtb r3, r3 - 8002116: 81fb strh r3, [r7, #14] - coor = coor << 8; - 8002118: 89fb ldrh r3, [r7, #14] - 800211a: 021b lsls r3, r3, #8 - 800211c: 81fb strh r3, [r7, #14] - send_cmd = 0x00; - 800211e: 4b11 ldr r3, [pc, #68] ; (8002164 ) - 8002120: 2200 movs r2, #0 - 8002122: 701a strb r2, [r3, #0] - HAL_SPI_TransmitReceive(&hspi3, (uint8_t*) &send_cmd, (uint8_t*) &receive_data, 1, 1000); - 8002124: f44f 737a mov.w r3, #1000 ; 0x3e8 - 8002128: 9300 str r3, [sp, #0] - 800212a: 2301 movs r3, #1 - 800212c: 4a0f ldr r2, [pc, #60] ; (800216c ) - 800212e: 490d ldr r1, [pc, #52] ; (8002164 ) - 8002130: 480d ldr r0, [pc, #52] ; (8002168 ) - 8002132: f001 fa12 bl 800355a - coor = coor | (uint16_t) receive_data; - 8002136: 4b0d ldr r3, [pc, #52] ; (800216c ) - 8002138: 781b ldrb r3, [r3, #0] - 800213a: b2db uxtb r3, r3 - 800213c: b29a uxth r2, r3 - 800213e: 89fb ldrh r3, [r7, #14] - 8002140: 4313 orrs r3, r2 - 8002142: 81fb strh r3, [r7, #14] - coor = coor >> 3; - 8002144: 89fb ldrh r3, [r7, #14] - 8002146: 08db lsrs r3, r3, #3 - 8002148: 81fb strh r3, [r7, #14] - T_CS; - 800214a: 2201 movs r2, #1 - 800214c: 2180 movs r1, #128 ; 0x80 - 800214e: 4804 ldr r0, [pc, #16] ; (8002160 ) - 8002150: f000 fbc0 bl 80028d4 - - return coor; - 8002154: 89fb ldrh r3, [r7, #14] -} - 8002156: 4618 mov r0, r3 - 8002158: 3710 adds r7, #16 - 800215a: 46bd mov sp, r7 - 800215c: bd80 pop {r7, pc} - 800215e: bf00 nop - 8002160: 40020c00 .word 0x40020c00 - 8002164: 20002795 .word 0x20002795 - 8002168: 20002708 .word 0x20002708 - 800216c: 20002794 .word 0x20002794 - -08002170 : - -/*sel = 0: Tinh toa do x - sel != 0: Tinh toa do y - coor: toa do nhan duoc*/ -uint16_t XPT2046_Calibrate(uint16_t coor, uint16_t r){ - 8002170: b580 push {r7, lr} - 8002172: b084 sub sp, #16 - 8002174: af00 add r7, sp, #0 - 8002176: 4603 mov r3, r0 - 8002178: 460a mov r2, r1 - 800217a: 80fb strh r3, [r7, #6] - 800217c: 4613 mov r3, r2 - 800217e: 80bb strh r3, [r7, #4] - uint16_t temp = 0; - 8002180: 2300 movs r3, #0 - 8002182: 81fb strh r3, [r7, #14] - - if(r == 1){ - 8002184: 88bb ldrh r3, [r7, #4] - 8002186: 2b01 cmp r3, #1 - 8002188: d11c bne.n 80021c4 - temp = (uint16_t) (LCD_WID * ((float)(coor - X_T_MIN)/T_WIDTH)); - 800218a: 88fb ldrh r3, [r7, #6] - 800218c: f5a3 73eb sub.w r3, r3, #470 ; 0x1d6 - 8002190: ee07 3a90 vmov s15, r3 - 8002194: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8002198: ed9f 7a1f vldr s14, [pc, #124] ; 8002218 - 800219c: eec7 6a87 vdiv.f32 s13, s15, s14 - 80021a0: ee16 0a90 vmov r0, s13 - 80021a4: f7fe faf2 bl 800078c <__aeabi_f2d> - 80021a8: a317 add r3, pc, #92 ; (adr r3, 8002208 ) - 80021aa: e9d3 2300 ldrd r2, r3, [r3] - 80021ae: f7fe f85f bl 8000270 <__aeabi_dmul> - 80021b2: 4602 mov r2, r0 - 80021b4: 460b mov r3, r1 - 80021b6: 4610 mov r0, r2 - 80021b8: 4619 mov r1, r3 - 80021ba: f7fe fb3f bl 800083c <__aeabi_d2uiz> - 80021be: 4603 mov r3, r0 - 80021c0: 81fb strh r3, [r7, #14] - 80021c2: e01b b.n 80021fc - } - else{ - temp = (uint16_t) (LCD_HEI * ((float)(coor - Y_T_MIN)/T_HEIGH)); - 80021c4: 88fb ldrh r3, [r7, #6] - 80021c6: f5a3 73eb sub.w r3, r3, #470 ; 0x1d6 - 80021ca: ee07 3a90 vmov s15, r3 - 80021ce: eef8 7ae7 vcvt.f32.s32 s15, s15 - 80021d2: ed9f 7a12 vldr s14, [pc, #72] ; 800221c - 80021d6: eec7 6a87 vdiv.f32 s13, s15, s14 - 80021da: ee16 0a90 vmov r0, s13 - 80021de: f7fe fad5 bl 800078c <__aeabi_f2d> - 80021e2: a30b add r3, pc, #44 ; (adr r3, 8002210 ) - 80021e4: e9d3 2300 ldrd r2, r3, [r3] - 80021e8: f7fe f842 bl 8000270 <__aeabi_dmul> - 80021ec: 4602 mov r2, r0 - 80021ee: 460b mov r3, r1 - 80021f0: 4610 mov r0, r2 - 80021f2: 4619 mov r1, r3 - 80021f4: f7fe fb22 bl 800083c <__aeabi_d2uiz> - 80021f8: 4603 mov r3, r0 - 80021fa: 81fb strh r3, [r7, #14] - } - - return temp; - 80021fc: 89fb ldrh r3, [r7, #14] -} - 80021fe: 4618 mov r0, r3 - 8002200: 3710 adds r7, #16 - 8002202: 46bd mov sp, r7 - 8002204: bd80 pop {r7, pc} - 8002206: bf00 nop - 8002208: 00000000 .word 0x00000000 - 800220c: 4073f000 .word 0x4073f000 - 8002210: 00000000 .word 0x00000000 - 8002214: 406de000 .word 0x406de000 - 8002218: 4549e000 .word 0x4549e000 - 800221c: 453ea000 .word 0x453ea000 - -08002220 : - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - 8002220: f8df d034 ldr.w sp, [pc, #52] ; 8002258 - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - 8002224: 480d ldr r0, [pc, #52] ; (800225c ) - ldr r1, =_edata - 8002226: 490e ldr r1, [pc, #56] ; (8002260 ) - ldr r2, =_sidata - 8002228: 4a0e ldr r2, [pc, #56] ; (8002264 ) - movs r3, #0 - 800222a: 2300 movs r3, #0 - b LoopCopyDataInit - 800222c: e002 b.n 8002234 - -0800222e : - -CopyDataInit: - ldr r4, [r2, r3] - 800222e: 58d4 ldr r4, [r2, r3] - str r4, [r0, r3] - 8002230: 50c4 str r4, [r0, r3] - adds r3, r3, #4 - 8002232: 3304 adds r3, #4 - -08002234 : - -LoopCopyDataInit: - adds r4, r0, r3 - 8002234: 18c4 adds r4, r0, r3 - cmp r4, r1 - 8002236: 428c cmp r4, r1 - bcc CopyDataInit - 8002238: d3f9 bcc.n 800222e - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - 800223a: 4a0b ldr r2, [pc, #44] ; (8002268 ) - ldr r4, =_ebss - 800223c: 4c0b ldr r4, [pc, #44] ; (800226c ) - movs r3, #0 - 800223e: 2300 movs r3, #0 - b LoopFillZerobss - 8002240: e001 b.n 8002246 - -08002242 : - -FillZerobss: - str r3, [r2] - 8002242: 6013 str r3, [r2, #0] - adds r2, r2, #4 - 8002244: 3204 adds r2, #4 - -08002246 : - -LoopFillZerobss: - cmp r2, r4 - 8002246: 42a2 cmp r2, r4 - bcc FillZerobss - 8002248: d3fb bcc.n 8002242 - -/* Call the clock system initialization function.*/ - bl SystemInit - 800224a: f7ff ff23 bl 8002094 -/* Call static constructors */ - bl __libc_init_array - 800224e: f001 fbf7 bl 8003a40 <__libc_init_array> -/* Call the application's entry point.*/ - bl main - 8002252: f7fe fc95 bl 8000b80
- bx lr - 8002256: 4770 bx lr - ldr sp, =_estack /* set stack pointer */ - 8002258: 20020000 .word 0x20020000 - ldr r0, =_sdata - 800225c: 20000000 .word 0x20000000 - ldr r1, =_edata - 8002260: 200026ec .word 0x200026ec - ldr r2, =_sidata - 8002264: 08004cd8 .word 0x08004cd8 - ldr r2, =_sbss - 8002268: 200026ec .word 0x200026ec - ldr r4, =_ebss - 800226c: 200027ac .word 0x200027ac - -08002270 : - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - 8002270: e7fe b.n 8002270 - ... - -08002274 : - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - 8002274: b580 push {r7, lr} - 8002276: af00 add r7, sp, #0 - /* Configure Flash prefetch, Instruction cache, Data cache */ -#if (INSTRUCTION_CACHE_ENABLE != 0U) - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - 8002278: 4b0e ldr r3, [pc, #56] ; (80022b4 ) - 800227a: 681b ldr r3, [r3, #0] - 800227c: 4a0d ldr r2, [pc, #52] ; (80022b4 ) - 800227e: f443 7300 orr.w r3, r3, #512 ; 0x200 - 8002282: 6013 str r3, [r2, #0] -#endif /* INSTRUCTION_CACHE_ENABLE */ - -#if (DATA_CACHE_ENABLE != 0U) - __HAL_FLASH_DATA_CACHE_ENABLE(); - 8002284: 4b0b ldr r3, [pc, #44] ; (80022b4 ) - 8002286: 681b ldr r3, [r3, #0] - 8002288: 4a0a ldr r2, [pc, #40] ; (80022b4 ) - 800228a: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 800228e: 6013 str r3, [r2, #0] -#endif /* DATA_CACHE_ENABLE */ - -#if (PREFETCH_ENABLE != 0U) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 8002290: 4b08 ldr r3, [pc, #32] ; (80022b4 ) - 8002292: 681b ldr r3, [r3, #0] - 8002294: 4a07 ldr r2, [pc, #28] ; (80022b4 ) - 8002296: f443 7380 orr.w r3, r3, #256 ; 0x100 - 800229a: 6013 str r3, [r2, #0] -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 800229c: 2003 movs r0, #3 - 800229e: f000 f931 bl 8002504 - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - 80022a2: 2000 movs r0, #0 - 80022a4: f000 f808 bl 80022b8 - - /* Init the low level hardware */ - HAL_MspInit(); - 80022a8: f7ff fd94 bl 8001dd4 - - /* Return function status */ - return HAL_OK; - 80022ac: 2300 movs r3, #0 -} - 80022ae: 4618 mov r0, r3 - 80022b0: bd80 pop {r7, pc} - 80022b2: bf00 nop - 80022b4: 40023c00 .word 0x40023c00 - -080022b8 : - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - 80022b8: b580 push {r7, lr} - 80022ba: b082 sub sp, #8 - 80022bc: af00 add r7, sp, #0 - 80022be: 6078 str r0, [r7, #4] - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 80022c0: 4b12 ldr r3, [pc, #72] ; (800230c ) - 80022c2: 681a ldr r2, [r3, #0] - 80022c4: 4b12 ldr r3, [pc, #72] ; (8002310 ) - 80022c6: 781b ldrb r3, [r3, #0] - 80022c8: 4619 mov r1, r3 - 80022ca: f44f 737a mov.w r3, #1000 ; 0x3e8 - 80022ce: fbb3 f3f1 udiv r3, r3, r1 - 80022d2: fbb2 f3f3 udiv r3, r2, r3 - 80022d6: 4618 mov r0, r3 - 80022d8: f000 f93b bl 8002552 - 80022dc: 4603 mov r3, r0 - 80022de: 2b00 cmp r3, #0 - 80022e0: d001 beq.n 80022e6 - { - return HAL_ERROR; - 80022e2: 2301 movs r3, #1 - 80022e4: e00e b.n 8002304 - } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 80022e6: 687b ldr r3, [r7, #4] - 80022e8: 2b0f cmp r3, #15 - 80022ea: d80a bhi.n 8002302 - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80022ec: 2200 movs r2, #0 - 80022ee: 6879 ldr r1, [r7, #4] - 80022f0: f04f 30ff mov.w r0, #4294967295 - 80022f4: f000 f911 bl 800251a - uwTickPrio = TickPriority; - 80022f8: 4a06 ldr r2, [pc, #24] ; (8002314 ) - 80022fa: 687b ldr r3, [r7, #4] - 80022fc: 6013 str r3, [r2, #0] - { - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; - 80022fe: 2300 movs r3, #0 - 8002300: e000 b.n 8002304 - return HAL_ERROR; - 8002302: 2301 movs r3, #1 -} - 8002304: 4618 mov r0, r3 - 8002306: 3708 adds r7, #8 - 8002308: 46bd mov sp, r7 - 800230a: bd80 pop {r7, pc} - 800230c: 2000267c .word 0x2000267c - 8002310: 20002684 .word 0x20002684 - 8002314: 20002680 .word 0x20002680 - -08002318 : - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - 8002318: b480 push {r7} - 800231a: af00 add r7, sp, #0 - uwTick += uwTickFreq; - 800231c: 4b06 ldr r3, [pc, #24] ; (8002338 ) - 800231e: 781b ldrb r3, [r3, #0] - 8002320: 461a mov r2, r3 - 8002322: 4b06 ldr r3, [pc, #24] ; (800233c ) - 8002324: 681b ldr r3, [r3, #0] - 8002326: 4413 add r3, r2 - 8002328: 4a04 ldr r2, [pc, #16] ; (800233c ) - 800232a: 6013 str r3, [r2, #0] -} - 800232c: bf00 nop - 800232e: 46bd mov sp, r7 - 8002330: f85d 7b04 ldr.w r7, [sp], #4 - 8002334: 4770 bx lr - 8002336: bf00 nop - 8002338: 20002684 .word 0x20002684 - 800233c: 20002798 .word 0x20002798 - -08002340 : - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - 8002340: b480 push {r7} - 8002342: af00 add r7, sp, #0 - return uwTick; - 8002344: 4b03 ldr r3, [pc, #12] ; (8002354 ) - 8002346: 681b ldr r3, [r3, #0] -} - 8002348: 4618 mov r0, r3 - 800234a: 46bd mov sp, r7 - 800234c: f85d 7b04 ldr.w r7, [sp], #4 - 8002350: 4770 bx lr - 8002352: bf00 nop - 8002354: 20002798 .word 0x20002798 - -08002358 : - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - 8002358: b580 push {r7, lr} - 800235a: b084 sub sp, #16 - 800235c: af00 add r7, sp, #0 - 800235e: 6078 str r0, [r7, #4] - uint32_t tickstart = HAL_GetTick(); - 8002360: f7ff ffee bl 8002340 - 8002364: 60b8 str r0, [r7, #8] - uint32_t wait = Delay; - 8002366: 687b ldr r3, [r7, #4] - 8002368: 60fb str r3, [r7, #12] - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - 800236a: 68fb ldr r3, [r7, #12] - 800236c: f1b3 3fff cmp.w r3, #4294967295 - 8002370: d005 beq.n 800237e - { - wait += (uint32_t)(uwTickFreq); - 8002372: 4b0a ldr r3, [pc, #40] ; (800239c ) - 8002374: 781b ldrb r3, [r3, #0] - 8002376: 461a mov r2, r3 - 8002378: 68fb ldr r3, [r7, #12] - 800237a: 4413 add r3, r2 - 800237c: 60fb str r3, [r7, #12] - } - - while((HAL_GetTick() - tickstart) < wait) - 800237e: bf00 nop - 8002380: f7ff ffde bl 8002340 - 8002384: 4602 mov r2, r0 - 8002386: 68bb ldr r3, [r7, #8] - 8002388: 1ad3 subs r3, r2, r3 - 800238a: 68fa ldr r2, [r7, #12] - 800238c: 429a cmp r2, r3 - 800238e: d8f7 bhi.n 8002380 - { - } -} - 8002390: bf00 nop - 8002392: bf00 nop - 8002394: 3710 adds r7, #16 - 8002396: 46bd mov sp, r7 - 8002398: bd80 pop {r7, pc} - 800239a: bf00 nop - 800239c: 20002684 .word 0x20002684 - -080023a0 <__NVIC_SetPriorityGrouping>: - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - 80023a0: b480 push {r7} - 80023a2: b085 sub sp, #20 - 80023a4: af00 add r7, sp, #0 - 80023a6: 6078 str r0, [r7, #4] - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 80023a8: 687b ldr r3, [r7, #4] - 80023aa: f003 0307 and.w r3, r3, #7 - 80023ae: 60fb str r3, [r7, #12] - - reg_value = SCB->AIRCR; /* read old register configuration */ - 80023b0: 4b0c ldr r3, [pc, #48] ; (80023e4 <__NVIC_SetPriorityGrouping+0x44>) - 80023b2: 68db ldr r3, [r3, #12] - 80023b4: 60bb str r3, [r7, #8] - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 80023b6: 68ba ldr r2, [r7, #8] - 80023b8: f64f 03ff movw r3, #63743 ; 0xf8ff - 80023bc: 4013 ands r3, r2 - 80023be: 60bb str r3, [r7, #8] - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 80023c0: 68fb ldr r3, [r7, #12] - 80023c2: 021a lsls r2, r3, #8 - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 80023c4: 68bb ldr r3, [r7, #8] - 80023c6: 4313 orrs r3, r2 - reg_value = (reg_value | - 80023c8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 - 80023cc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 80023d0: 60bb str r3, [r7, #8] - SCB->AIRCR = reg_value; - 80023d2: 4a04 ldr r2, [pc, #16] ; (80023e4 <__NVIC_SetPriorityGrouping+0x44>) - 80023d4: 68bb ldr r3, [r7, #8] - 80023d6: 60d3 str r3, [r2, #12] -} - 80023d8: bf00 nop - 80023da: 3714 adds r7, #20 - 80023dc: 46bd mov sp, r7 - 80023de: f85d 7b04 ldr.w r7, [sp], #4 - 80023e2: 4770 bx lr - 80023e4: e000ed00 .word 0xe000ed00 - -080023e8 <__NVIC_GetPriorityGrouping>: - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - 80023e8: b480 push {r7} - 80023ea: af00 add r7, sp, #0 - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 80023ec: 4b04 ldr r3, [pc, #16] ; (8002400 <__NVIC_GetPriorityGrouping+0x18>) - 80023ee: 68db ldr r3, [r3, #12] - 80023f0: 0a1b lsrs r3, r3, #8 - 80023f2: f003 0307 and.w r3, r3, #7 -} - 80023f6: 4618 mov r0, r3 - 80023f8: 46bd mov sp, r7 - 80023fa: f85d 7b04 ldr.w r7, [sp], #4 - 80023fe: 4770 bx lr - 8002400: e000ed00 .word 0xe000ed00 - -08002404 <__NVIC_SetPriority>: - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - 8002404: b480 push {r7} - 8002406: b083 sub sp, #12 - 8002408: af00 add r7, sp, #0 - 800240a: 4603 mov r3, r0 - 800240c: 6039 str r1, [r7, #0] - 800240e: 71fb strb r3, [r7, #7] - if ((int32_t)(IRQn) >= 0) - 8002410: f997 3007 ldrsb.w r3, [r7, #7] - 8002414: 2b00 cmp r3, #0 - 8002416: db0a blt.n 800242e <__NVIC_SetPriority+0x2a> - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8002418: 683b ldr r3, [r7, #0] - 800241a: b2da uxtb r2, r3 - 800241c: 490c ldr r1, [pc, #48] ; (8002450 <__NVIC_SetPriority+0x4c>) - 800241e: f997 3007 ldrsb.w r3, [r7, #7] - 8002422: 0112 lsls r2, r2, #4 - 8002424: b2d2 uxtb r2, r2 - 8002426: 440b add r3, r1 - 8002428: f883 2300 strb.w r2, [r3, #768] ; 0x300 - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - 800242c: e00a b.n 8002444 <__NVIC_SetPriority+0x40> - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 800242e: 683b ldr r3, [r7, #0] - 8002430: b2da uxtb r2, r3 - 8002432: 4908 ldr r1, [pc, #32] ; (8002454 <__NVIC_SetPriority+0x50>) - 8002434: 79fb ldrb r3, [r7, #7] - 8002436: f003 030f and.w r3, r3, #15 - 800243a: 3b04 subs r3, #4 - 800243c: 0112 lsls r2, r2, #4 - 800243e: b2d2 uxtb r2, r2 - 8002440: 440b add r3, r1 - 8002442: 761a strb r2, [r3, #24] -} - 8002444: bf00 nop - 8002446: 370c adds r7, #12 - 8002448: 46bd mov sp, r7 - 800244a: f85d 7b04 ldr.w r7, [sp], #4 - 800244e: 4770 bx lr - 8002450: e000e100 .word 0xe000e100 - 8002454: e000ed00 .word 0xe000ed00 - -08002458 : - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - 8002458: b480 push {r7} - 800245a: b089 sub sp, #36 ; 0x24 - 800245c: af00 add r7, sp, #0 - 800245e: 60f8 str r0, [r7, #12] - 8002460: 60b9 str r1, [r7, #8] - 8002462: 607a str r2, [r7, #4] - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8002464: 68fb ldr r3, [r7, #12] - 8002466: f003 0307 and.w r3, r3, #7 - 800246a: 61fb str r3, [r7, #28] - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 800246c: 69fb ldr r3, [r7, #28] - 800246e: f1c3 0307 rsb r3, r3, #7 - 8002472: 2b04 cmp r3, #4 - 8002474: bf28 it cs - 8002476: 2304 movcs r3, #4 - 8002478: 61bb str r3, [r7, #24] - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 800247a: 69fb ldr r3, [r7, #28] - 800247c: 3304 adds r3, #4 - 800247e: 2b06 cmp r3, #6 - 8002480: d902 bls.n 8002488 - 8002482: 69fb ldr r3, [r7, #28] - 8002484: 3b03 subs r3, #3 - 8002486: e000 b.n 800248a - 8002488: 2300 movs r3, #0 - 800248a: 617b str r3, [r7, #20] - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 800248c: f04f 32ff mov.w r2, #4294967295 - 8002490: 69bb ldr r3, [r7, #24] - 8002492: fa02 f303 lsl.w r3, r2, r3 - 8002496: 43da mvns r2, r3 - 8002498: 68bb ldr r3, [r7, #8] - 800249a: 401a ands r2, r3 - 800249c: 697b ldr r3, [r7, #20] - 800249e: 409a lsls r2, r3 - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 80024a0: f04f 31ff mov.w r1, #4294967295 - 80024a4: 697b ldr r3, [r7, #20] - 80024a6: fa01 f303 lsl.w r3, r1, r3 - 80024aa: 43d9 mvns r1, r3 - 80024ac: 687b ldr r3, [r7, #4] - 80024ae: 400b ands r3, r1 - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 80024b0: 4313 orrs r3, r2 - ); -} - 80024b2: 4618 mov r0, r3 - 80024b4: 3724 adds r7, #36 ; 0x24 - 80024b6: 46bd mov sp, r7 - 80024b8: f85d 7b04 ldr.w r7, [sp], #4 - 80024bc: 4770 bx lr - ... - -080024c0 : - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - 80024c0: b580 push {r7, lr} - 80024c2: b082 sub sp, #8 - 80024c4: af00 add r7, sp, #0 - 80024c6: 6078 str r0, [r7, #4] - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80024c8: 687b ldr r3, [r7, #4] - 80024ca: 3b01 subs r3, #1 - 80024cc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 80024d0: d301 bcc.n 80024d6 - { - return (1UL); /* Reload value impossible */ - 80024d2: 2301 movs r3, #1 - 80024d4: e00f b.n 80024f6 - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80024d6: 4a0a ldr r2, [pc, #40] ; (8002500 ) - 80024d8: 687b ldr r3, [r7, #4] - 80024da: 3b01 subs r3, #1 - 80024dc: 6053 str r3, [r2, #4] - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80024de: 210f movs r1, #15 - 80024e0: f04f 30ff mov.w r0, #4294967295 - 80024e4: f7ff ff8e bl 8002404 <__NVIC_SetPriority> - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80024e8: 4b05 ldr r3, [pc, #20] ; (8002500 ) - 80024ea: 2200 movs r2, #0 - 80024ec: 609a str r2, [r3, #8] - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80024ee: 4b04 ldr r3, [pc, #16] ; (8002500 ) - 80024f0: 2207 movs r2, #7 - 80024f2: 601a str r2, [r3, #0] - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ - 80024f4: 2300 movs r3, #0 -} - 80024f6: 4618 mov r0, r3 - 80024f8: 3708 adds r7, #8 - 80024fa: 46bd mov sp, r7 - 80024fc: bd80 pop {r7, pc} - 80024fe: bf00 nop - 8002500: e000e010 .word 0xe000e010 - -08002504 : - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - 8002504: b580 push {r7, lr} - 8002506: b082 sub sp, #8 - 8002508: af00 add r7, sp, #0 - 800250a: 6078 str r0, [r7, #4] - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); - 800250c: 6878 ldr r0, [r7, #4] - 800250e: f7ff ff47 bl 80023a0 <__NVIC_SetPriorityGrouping> -} - 8002512: bf00 nop - 8002514: 3708 adds r7, #8 - 8002516: 46bd mov sp, r7 - 8002518: bd80 pop {r7, pc} - -0800251a : - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - 800251a: b580 push {r7, lr} - 800251c: b086 sub sp, #24 - 800251e: af00 add r7, sp, #0 - 8002520: 4603 mov r3, r0 - 8002522: 60b9 str r1, [r7, #8] - 8002524: 607a str r2, [r7, #4] - 8002526: 73fb strb r3, [r7, #15] - uint32_t prioritygroup = 0x00U; - 8002528: 2300 movs r3, #0 - 800252a: 617b str r3, [r7, #20] - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - 800252c: f7ff ff5c bl 80023e8 <__NVIC_GetPriorityGrouping> - 8002530: 6178 str r0, [r7, #20] - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8002532: 687a ldr r2, [r7, #4] - 8002534: 68b9 ldr r1, [r7, #8] - 8002536: 6978 ldr r0, [r7, #20] - 8002538: f7ff ff8e bl 8002458 - 800253c: 4602 mov r2, r0 - 800253e: f997 300f ldrsb.w r3, [r7, #15] - 8002542: 4611 mov r1, r2 - 8002544: 4618 mov r0, r3 - 8002546: f7ff ff5d bl 8002404 <__NVIC_SetPriority> -} - 800254a: bf00 nop - 800254c: 3718 adds r7, #24 - 800254e: 46bd mov sp, r7 - 8002550: bd80 pop {r7, pc} - -08002552 : - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - 8002552: b580 push {r7, lr} - 8002554: b082 sub sp, #8 - 8002556: af00 add r7, sp, #0 - 8002558: 6078 str r0, [r7, #4] - return SysTick_Config(TicksNumb); - 800255a: 6878 ldr r0, [r7, #4] - 800255c: f7ff ffb0 bl 80024c0 - 8002560: 4603 mov r3, r0 -} - 8002562: 4618 mov r0, r3 - 8002564: 3708 adds r7, #8 - 8002566: 46bd mov sp, r7 - 8002568: bd80 pop {r7, pc} - ... - -0800256c : - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - 800256c: b480 push {r7} - 800256e: b089 sub sp, #36 ; 0x24 - 8002570: af00 add r7, sp, #0 - 8002572: 6078 str r0, [r7, #4] - 8002574: 6039 str r1, [r7, #0] - uint32_t position; - uint32_t ioposition = 0x00U; - 8002576: 2300 movs r3, #0 - 8002578: 617b str r3, [r7, #20] - uint32_t iocurrent = 0x00U; - 800257a: 2300 movs r3, #0 - 800257c: 613b str r3, [r7, #16] - uint32_t temp = 0x00U; - 800257e: 2300 movs r3, #0 - 8002580: 61bb str r3, [r7, #24] - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - - /* Configure the port pins */ - for(position = 0U; position < GPIO_NUMBER; position++) - 8002582: 2300 movs r3, #0 - 8002584: 61fb str r3, [r7, #28] - 8002586: e16b b.n 8002860 - { - /* Get the IO position */ - ioposition = 0x01U << position; - 8002588: 2201 movs r2, #1 - 800258a: 69fb ldr r3, [r7, #28] - 800258c: fa02 f303 lsl.w r3, r2, r3 - 8002590: 617b str r3, [r7, #20] - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 8002592: 683b ldr r3, [r7, #0] - 8002594: 681b ldr r3, [r3, #0] - 8002596: 697a ldr r2, [r7, #20] - 8002598: 4013 ands r3, r2 - 800259a: 613b str r3, [r7, #16] - - if(iocurrent == ioposition) - 800259c: 693a ldr r2, [r7, #16] - 800259e: 697b ldr r3, [r7, #20] - 80025a0: 429a cmp r2, r3 - 80025a2: f040 815a bne.w 800285a - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Output or Alternate function mode selection */ - if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 80025a6: 683b ldr r3, [r7, #0] - 80025a8: 685b ldr r3, [r3, #4] - 80025aa: f003 0303 and.w r3, r3, #3 - 80025ae: 2b01 cmp r3, #1 - 80025b0: d005 beq.n 80025be - (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 80025b2: 683b ldr r3, [r7, #0] - 80025b4: 685b ldr r3, [r3, #4] - 80025b6: f003 0303 and.w r3, r3, #3 - if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 80025ba: 2b02 cmp r3, #2 - 80025bc: d130 bne.n 8002620 - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - 80025be: 687b ldr r3, [r7, #4] - 80025c0: 689b ldr r3, [r3, #8] - 80025c2: 61bb str r3, [r7, #24] - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - 80025c4: 69fb ldr r3, [r7, #28] - 80025c6: 005b lsls r3, r3, #1 - 80025c8: 2203 movs r2, #3 - 80025ca: fa02 f303 lsl.w r3, r2, r3 - 80025ce: 43db mvns r3, r3 - 80025d0: 69ba ldr r2, [r7, #24] - 80025d2: 4013 ands r3, r2 - 80025d4: 61bb str r3, [r7, #24] - temp |= (GPIO_Init->Speed << (position * 2U)); - 80025d6: 683b ldr r3, [r7, #0] - 80025d8: 68da ldr r2, [r3, #12] - 80025da: 69fb ldr r3, [r7, #28] - 80025dc: 005b lsls r3, r3, #1 - 80025de: fa02 f303 lsl.w r3, r2, r3 - 80025e2: 69ba ldr r2, [r7, #24] - 80025e4: 4313 orrs r3, r2 - 80025e6: 61bb str r3, [r7, #24] - GPIOx->OSPEEDR = temp; - 80025e8: 687b ldr r3, [r7, #4] - 80025ea: 69ba ldr r2, [r7, #24] - 80025ec: 609a str r2, [r3, #8] - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - 80025ee: 687b ldr r3, [r7, #4] - 80025f0: 685b ldr r3, [r3, #4] - 80025f2: 61bb str r3, [r7, #24] - temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 80025f4: 2201 movs r2, #1 - 80025f6: 69fb ldr r3, [r7, #28] - 80025f8: fa02 f303 lsl.w r3, r2, r3 - 80025fc: 43db mvns r3, r3 - 80025fe: 69ba ldr r2, [r7, #24] - 8002600: 4013 ands r3, r2 - 8002602: 61bb str r3, [r7, #24] - temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8002604: 683b ldr r3, [r7, #0] - 8002606: 685b ldr r3, [r3, #4] - 8002608: 091b lsrs r3, r3, #4 - 800260a: f003 0201 and.w r2, r3, #1 - 800260e: 69fb ldr r3, [r7, #28] - 8002610: fa02 f303 lsl.w r3, r2, r3 - 8002614: 69ba ldr r2, [r7, #24] - 8002616: 4313 orrs r3, r2 - 8002618: 61bb str r3, [r7, #24] - GPIOx->OTYPER = temp; - 800261a: 687b ldr r3, [r7, #4] - 800261c: 69ba ldr r2, [r7, #24] - 800261e: 605a str r2, [r3, #4] - } - - if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8002620: 683b ldr r3, [r7, #0] - 8002622: 685b ldr r3, [r3, #4] - 8002624: f003 0303 and.w r3, r3, #3 - 8002628: 2b03 cmp r3, #3 - 800262a: d017 beq.n 800265c - { - /* Check the parameters */ - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - 800262c: 687b ldr r3, [r7, #4] - 800262e: 68db ldr r3, [r3, #12] - 8002630: 61bb str r3, [r7, #24] - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); - 8002632: 69fb ldr r3, [r7, #28] - 8002634: 005b lsls r3, r3, #1 - 8002636: 2203 movs r2, #3 - 8002638: fa02 f303 lsl.w r3, r2, r3 - 800263c: 43db mvns r3, r3 - 800263e: 69ba ldr r2, [r7, #24] - 8002640: 4013 ands r3, r2 - 8002642: 61bb str r3, [r7, #24] - temp |= ((GPIO_Init->Pull) << (position * 2U)); - 8002644: 683b ldr r3, [r7, #0] - 8002646: 689a ldr r2, [r3, #8] - 8002648: 69fb ldr r3, [r7, #28] - 800264a: 005b lsls r3, r3, #1 - 800264c: fa02 f303 lsl.w r3, r2, r3 - 8002650: 69ba ldr r2, [r7, #24] - 8002652: 4313 orrs r3, r2 - 8002654: 61bb str r3, [r7, #24] - GPIOx->PUPDR = temp; - 8002656: 687b ldr r3, [r7, #4] - 8002658: 69ba ldr r2, [r7, #24] - 800265a: 60da str r2, [r3, #12] - } - - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 800265c: 683b ldr r3, [r7, #0] - 800265e: 685b ldr r3, [r3, #4] - 8002660: f003 0303 and.w r3, r3, #3 - 8002664: 2b02 cmp r3, #2 - 8002666: d123 bne.n 80026b0 - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3U]; - 8002668: 69fb ldr r3, [r7, #28] - 800266a: 08da lsrs r2, r3, #3 - 800266c: 687b ldr r3, [r7, #4] - 800266e: 3208 adds r2, #8 - 8002670: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8002674: 61bb str r3, [r7, #24] - temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - 8002676: 69fb ldr r3, [r7, #28] - 8002678: f003 0307 and.w r3, r3, #7 - 800267c: 009b lsls r3, r3, #2 - 800267e: 220f movs r2, #15 - 8002680: fa02 f303 lsl.w r3, r2, r3 - 8002684: 43db mvns r3, r3 - 8002686: 69ba ldr r2, [r7, #24] - 8002688: 4013 ands r3, r2 - 800268a: 61bb str r3, [r7, #24] - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - 800268c: 683b ldr r3, [r7, #0] - 800268e: 691a ldr r2, [r3, #16] - 8002690: 69fb ldr r3, [r7, #28] - 8002692: f003 0307 and.w r3, r3, #7 - 8002696: 009b lsls r3, r3, #2 - 8002698: fa02 f303 lsl.w r3, r2, r3 - 800269c: 69ba ldr r2, [r7, #24] - 800269e: 4313 orrs r3, r2 - 80026a0: 61bb str r3, [r7, #24] - GPIOx->AFR[position >> 3U] = temp; - 80026a2: 69fb ldr r3, [r7, #28] - 80026a4: 08da lsrs r2, r3, #3 - 80026a6: 687b ldr r3, [r7, #4] - 80026a8: 3208 adds r2, #8 - 80026aa: 69b9 ldr r1, [r7, #24] - 80026ac: f843 1022 str.w r1, [r3, r2, lsl #2] - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - 80026b0: 687b ldr r3, [r7, #4] - 80026b2: 681b ldr r3, [r3, #0] - 80026b4: 61bb str r3, [r7, #24] - temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); - 80026b6: 69fb ldr r3, [r7, #28] - 80026b8: 005b lsls r3, r3, #1 - 80026ba: 2203 movs r2, #3 - 80026bc: fa02 f303 lsl.w r3, r2, r3 - 80026c0: 43db mvns r3, r3 - 80026c2: 69ba ldr r2, [r7, #24] - 80026c4: 4013 ands r3, r2 - 80026c6: 61bb str r3, [r7, #24] - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - 80026c8: 683b ldr r3, [r7, #0] - 80026ca: 685b ldr r3, [r3, #4] - 80026cc: f003 0203 and.w r2, r3, #3 - 80026d0: 69fb ldr r3, [r7, #28] - 80026d2: 005b lsls r3, r3, #1 - 80026d4: fa02 f303 lsl.w r3, r2, r3 - 80026d8: 69ba ldr r2, [r7, #24] - 80026da: 4313 orrs r3, r2 - 80026dc: 61bb str r3, [r7, #24] - GPIOx->MODER = temp; - 80026de: 687b ldr r3, [r7, #4] - 80026e0: 69ba ldr r2, [r7, #24] - 80026e2: 601a str r2, [r3, #0] - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) - 80026e4: 683b ldr r3, [r7, #0] - 80026e6: 685b ldr r3, [r3, #4] - 80026e8: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 80026ec: 2b00 cmp r3, #0 - 80026ee: f000 80b4 beq.w 800285a - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - 80026f2: 2300 movs r3, #0 - 80026f4: 60fb str r3, [r7, #12] - 80026f6: 4b60 ldr r3, [pc, #384] ; (8002878 ) - 80026f8: 6c5b ldr r3, [r3, #68] ; 0x44 - 80026fa: 4a5f ldr r2, [pc, #380] ; (8002878 ) - 80026fc: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8002700: 6453 str r3, [r2, #68] ; 0x44 - 8002702: 4b5d ldr r3, [pc, #372] ; (8002878 ) - 8002704: 6c5b ldr r3, [r3, #68] ; 0x44 - 8002706: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800270a: 60fb str r3, [r7, #12] - 800270c: 68fb ldr r3, [r7, #12] - - temp = SYSCFG->EXTICR[position >> 2U]; - 800270e: 4a5b ldr r2, [pc, #364] ; (800287c ) - 8002710: 69fb ldr r3, [r7, #28] - 8002712: 089b lsrs r3, r3, #2 - 8002714: 3302 adds r3, #2 - 8002716: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 800271a: 61bb str r3, [r7, #24] - temp &= ~(0x0FU << (4U * (position & 0x03U))); - 800271c: 69fb ldr r3, [r7, #28] - 800271e: f003 0303 and.w r3, r3, #3 - 8002722: 009b lsls r3, r3, #2 - 8002724: 220f movs r2, #15 - 8002726: fa02 f303 lsl.w r3, r2, r3 - 800272a: 43db mvns r3, r3 - 800272c: 69ba ldr r2, [r7, #24] - 800272e: 4013 ands r3, r2 - 8002730: 61bb str r3, [r7, #24] - temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - 8002732: 687b ldr r3, [r7, #4] - 8002734: 4a52 ldr r2, [pc, #328] ; (8002880 ) - 8002736: 4293 cmp r3, r2 - 8002738: d02b beq.n 8002792 - 800273a: 687b ldr r3, [r7, #4] - 800273c: 4a51 ldr r2, [pc, #324] ; (8002884 ) - 800273e: 4293 cmp r3, r2 - 8002740: d025 beq.n 800278e - 8002742: 687b ldr r3, [r7, #4] - 8002744: 4a50 ldr r2, [pc, #320] ; (8002888 ) - 8002746: 4293 cmp r3, r2 - 8002748: d01f beq.n 800278a - 800274a: 687b ldr r3, [r7, #4] - 800274c: 4a4f ldr r2, [pc, #316] ; (800288c ) - 800274e: 4293 cmp r3, r2 - 8002750: d019 beq.n 8002786 - 8002752: 687b ldr r3, [r7, #4] - 8002754: 4a4e ldr r2, [pc, #312] ; (8002890 ) - 8002756: 4293 cmp r3, r2 - 8002758: d013 beq.n 8002782 - 800275a: 687b ldr r3, [r7, #4] - 800275c: 4a4d ldr r2, [pc, #308] ; (8002894 ) - 800275e: 4293 cmp r3, r2 - 8002760: d00d beq.n 800277e - 8002762: 687b ldr r3, [r7, #4] - 8002764: 4a4c ldr r2, [pc, #304] ; (8002898 ) - 8002766: 4293 cmp r3, r2 - 8002768: d007 beq.n 800277a - 800276a: 687b ldr r3, [r7, #4] - 800276c: 4a4b ldr r2, [pc, #300] ; (800289c ) - 800276e: 4293 cmp r3, r2 - 8002770: d101 bne.n 8002776 - 8002772: 2307 movs r3, #7 - 8002774: e00e b.n 8002794 - 8002776: 2308 movs r3, #8 - 8002778: e00c b.n 8002794 - 800277a: 2306 movs r3, #6 - 800277c: e00a b.n 8002794 - 800277e: 2305 movs r3, #5 - 8002780: e008 b.n 8002794 - 8002782: 2304 movs r3, #4 - 8002784: e006 b.n 8002794 - 8002786: 2303 movs r3, #3 - 8002788: e004 b.n 8002794 - 800278a: 2302 movs r3, #2 - 800278c: e002 b.n 8002794 - 800278e: 2301 movs r3, #1 - 8002790: e000 b.n 8002794 - 8002792: 2300 movs r3, #0 - 8002794: 69fa ldr r2, [r7, #28] - 8002796: f002 0203 and.w r2, r2, #3 - 800279a: 0092 lsls r2, r2, #2 - 800279c: 4093 lsls r3, r2 - 800279e: 69ba ldr r2, [r7, #24] - 80027a0: 4313 orrs r3, r2 - 80027a2: 61bb str r3, [r7, #24] - SYSCFG->EXTICR[position >> 2U] = temp; - 80027a4: 4935 ldr r1, [pc, #212] ; (800287c ) - 80027a6: 69fb ldr r3, [r7, #28] - 80027a8: 089b lsrs r3, r3, #2 - 80027aa: 3302 adds r3, #2 - 80027ac: 69ba ldr r2, [r7, #24] - 80027ae: f841 2023 str.w r2, [r1, r3, lsl #2] - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - 80027b2: 4b3b ldr r3, [pc, #236] ; (80028a0 ) - 80027b4: 689b ldr r3, [r3, #8] - 80027b6: 61bb str r3, [r7, #24] - temp &= ~((uint32_t)iocurrent); - 80027b8: 693b ldr r3, [r7, #16] - 80027ba: 43db mvns r3, r3 - 80027bc: 69ba ldr r2, [r7, #24] - 80027be: 4013 ands r3, r2 - 80027c0: 61bb str r3, [r7, #24] - if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - 80027c2: 683b ldr r3, [r7, #0] - 80027c4: 685b ldr r3, [r3, #4] - 80027c6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 80027ca: 2b00 cmp r3, #0 - 80027cc: d003 beq.n 80027d6 - { - temp |= iocurrent; - 80027ce: 69ba ldr r2, [r7, #24] - 80027d0: 693b ldr r3, [r7, #16] - 80027d2: 4313 orrs r3, r2 - 80027d4: 61bb str r3, [r7, #24] - } - EXTI->RTSR = temp; - 80027d6: 4a32 ldr r2, [pc, #200] ; (80028a0 ) - 80027d8: 69bb ldr r3, [r7, #24] - 80027da: 6093 str r3, [r2, #8] - - temp = EXTI->FTSR; - 80027dc: 4b30 ldr r3, [pc, #192] ; (80028a0 ) - 80027de: 68db ldr r3, [r3, #12] - 80027e0: 61bb str r3, [r7, #24] - temp &= ~((uint32_t)iocurrent); - 80027e2: 693b ldr r3, [r7, #16] - 80027e4: 43db mvns r3, r3 - 80027e6: 69ba ldr r2, [r7, #24] - 80027e8: 4013 ands r3, r2 - 80027ea: 61bb str r3, [r7, #24] - if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - 80027ec: 683b ldr r3, [r7, #0] - 80027ee: 685b ldr r3, [r3, #4] - 80027f0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 80027f4: 2b00 cmp r3, #0 - 80027f6: d003 beq.n 8002800 - { - temp |= iocurrent; - 80027f8: 69ba ldr r2, [r7, #24] - 80027fa: 693b ldr r3, [r7, #16] - 80027fc: 4313 orrs r3, r2 - 80027fe: 61bb str r3, [r7, #24] - } - EXTI->FTSR = temp; - 8002800: 4a27 ldr r2, [pc, #156] ; (80028a0 ) - 8002802: 69bb ldr r3, [r7, #24] - 8002804: 60d3 str r3, [r2, #12] - - temp = EXTI->EMR; - 8002806: 4b26 ldr r3, [pc, #152] ; (80028a0 ) - 8002808: 685b ldr r3, [r3, #4] - 800280a: 61bb str r3, [r7, #24] - temp &= ~((uint32_t)iocurrent); - 800280c: 693b ldr r3, [r7, #16] - 800280e: 43db mvns r3, r3 - 8002810: 69ba ldr r2, [r7, #24] - 8002812: 4013 ands r3, r2 - 8002814: 61bb str r3, [r7, #24] - if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - 8002816: 683b ldr r3, [r7, #0] - 8002818: 685b ldr r3, [r3, #4] - 800281a: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800281e: 2b00 cmp r3, #0 - 8002820: d003 beq.n 800282a - { - temp |= iocurrent; - 8002822: 69ba ldr r2, [r7, #24] - 8002824: 693b ldr r3, [r7, #16] - 8002826: 4313 orrs r3, r2 - 8002828: 61bb str r3, [r7, #24] - } - EXTI->EMR = temp; - 800282a: 4a1d ldr r2, [pc, #116] ; (80028a0 ) - 800282c: 69bb ldr r3, [r7, #24] - 800282e: 6053 str r3, [r2, #4] - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - 8002830: 4b1b ldr r3, [pc, #108] ; (80028a0 ) - 8002832: 681b ldr r3, [r3, #0] - 8002834: 61bb str r3, [r7, #24] - temp &= ~((uint32_t)iocurrent); - 8002836: 693b ldr r3, [r7, #16] - 8002838: 43db mvns r3, r3 - 800283a: 69ba ldr r2, [r7, #24] - 800283c: 4013 ands r3, r2 - 800283e: 61bb str r3, [r7, #24] - if((GPIO_Init->Mode & EXTI_IT) != 0x00U) - 8002840: 683b ldr r3, [r7, #0] - 8002842: 685b ldr r3, [r3, #4] - 8002844: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8002848: 2b00 cmp r3, #0 - 800284a: d003 beq.n 8002854 - { - temp |= iocurrent; - 800284c: 69ba ldr r2, [r7, #24] - 800284e: 693b ldr r3, [r7, #16] - 8002850: 4313 orrs r3, r2 - 8002852: 61bb str r3, [r7, #24] - } - EXTI->IMR = temp; - 8002854: 4a12 ldr r2, [pc, #72] ; (80028a0 ) - 8002856: 69bb ldr r3, [r7, #24] - 8002858: 6013 str r3, [r2, #0] - for(position = 0U; position < GPIO_NUMBER; position++) - 800285a: 69fb ldr r3, [r7, #28] - 800285c: 3301 adds r3, #1 - 800285e: 61fb str r3, [r7, #28] - 8002860: 69fb ldr r3, [r7, #28] - 8002862: 2b0f cmp r3, #15 - 8002864: f67f ae90 bls.w 8002588 - } - } - } -} - 8002868: bf00 nop - 800286a: bf00 nop - 800286c: 3724 adds r7, #36 ; 0x24 - 800286e: 46bd mov sp, r7 - 8002870: f85d 7b04 ldr.w r7, [sp], #4 - 8002874: 4770 bx lr - 8002876: bf00 nop - 8002878: 40023800 .word 0x40023800 - 800287c: 40013800 .word 0x40013800 - 8002880: 40020000 .word 0x40020000 - 8002884: 40020400 .word 0x40020400 - 8002888: 40020800 .word 0x40020800 - 800288c: 40020c00 .word 0x40020c00 - 8002890: 40021000 .word 0x40021000 - 8002894: 40021400 .word 0x40021400 - 8002898: 40021800 .word 0x40021800 - 800289c: 40021c00 .word 0x40021c00 - 80028a0: 40013c00 .word 0x40013c00 - -080028a4 : - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - 80028a4: b480 push {r7} - 80028a6: b085 sub sp, #20 - 80028a8: af00 add r7, sp, #0 - 80028aa: 6078 str r0, [r7, #4] - 80028ac: 460b mov r3, r1 - 80028ae: 807b strh r3, [r7, #2] - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - 80028b0: 687b ldr r3, [r7, #4] - 80028b2: 691a ldr r2, [r3, #16] - 80028b4: 887b ldrh r3, [r7, #2] - 80028b6: 4013 ands r3, r2 - 80028b8: 2b00 cmp r3, #0 - 80028ba: d002 beq.n 80028c2 - { - bitstatus = GPIO_PIN_SET; - 80028bc: 2301 movs r3, #1 - 80028be: 73fb strb r3, [r7, #15] - 80028c0: e001 b.n 80028c6 - } - else - { - bitstatus = GPIO_PIN_RESET; - 80028c2: 2300 movs r3, #0 - 80028c4: 73fb strb r3, [r7, #15] - } - return bitstatus; - 80028c6: 7bfb ldrb r3, [r7, #15] -} - 80028c8: 4618 mov r0, r3 - 80028ca: 3714 adds r7, #20 - 80028cc: 46bd mov sp, r7 - 80028ce: f85d 7b04 ldr.w r7, [sp], #4 - 80028d2: 4770 bx lr - -080028d4 : - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - 80028d4: b480 push {r7} - 80028d6: b083 sub sp, #12 - 80028d8: af00 add r7, sp, #0 - 80028da: 6078 str r0, [r7, #4] - 80028dc: 460b mov r3, r1 - 80028de: 807b strh r3, [r7, #2] - 80028e0: 4613 mov r3, r2 - 80028e2: 707b strb r3, [r7, #1] - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - 80028e4: 787b ldrb r3, [r7, #1] - 80028e6: 2b00 cmp r3, #0 - 80028e8: d003 beq.n 80028f2 - { - GPIOx->BSRR = GPIO_Pin; - 80028ea: 887a ldrh r2, [r7, #2] - 80028ec: 687b ldr r3, [r7, #4] - 80028ee: 619a str r2, [r3, #24] - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; - } -} - 80028f0: e003 b.n 80028fa - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; - 80028f2: 887b ldrh r3, [r7, #2] - 80028f4: 041a lsls r2, r3, #16 - 80028f6: 687b ldr r3, [r7, #4] - 80028f8: 619a str r2, [r3, #24] -} - 80028fa: bf00 nop - 80028fc: 370c adds r7, #12 - 80028fe: 46bd mov sp, r7 - 8002900: f85d 7b04 ldr.w r7, [sp], #4 - 8002904: 4770 bx lr - ... - -08002908 : - * supported by this API. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - 8002908: b580 push {r7, lr} - 800290a: b086 sub sp, #24 - 800290c: af00 add r7, sp, #0 - 800290e: 6078 str r0, [r7, #4] - uint32_t tickstart, pll_config; - - /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) - 8002910: 687b ldr r3, [r7, #4] - 8002912: 2b00 cmp r3, #0 - 8002914: d101 bne.n 800291a - { - return HAL_ERROR; - 8002916: 2301 movs r3, #1 - 8002918: e267 b.n 8002dea - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 800291a: 687b ldr r3, [r7, #4] - 800291c: 681b ldr r3, [r3, #0] - 800291e: f003 0301 and.w r3, r3, #1 - 8002922: 2b00 cmp r3, #0 - 8002924: d075 beq.n 8002a12 - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - 8002926: 4b88 ldr r3, [pc, #544] ; (8002b48 ) - 8002928: 689b ldr r3, [r3, #8] - 800292a: f003 030c and.w r3, r3, #12 - 800292e: 2b04 cmp r3, #4 - 8002930: d00c beq.n 800294c - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 8002932: 4b85 ldr r3, [pc, #532] ; (8002b48 ) - 8002934: 689b ldr r3, [r3, #8] - 8002936: f003 030c and.w r3, r3, #12 - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - 800293a: 2b08 cmp r3, #8 - 800293c: d112 bne.n 8002964 - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 800293e: 4b82 ldr r3, [pc, #520] ; (8002b48 ) - 8002940: 685b ldr r3, [r3, #4] - 8002942: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8002946: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 800294a: d10b bne.n 8002964 - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 800294c: 4b7e ldr r3, [pc, #504] ; (8002b48 ) - 800294e: 681b ldr r3, [r3, #0] - 8002950: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8002954: 2b00 cmp r3, #0 - 8002956: d05b beq.n 8002a10 - 8002958: 687b ldr r3, [r7, #4] - 800295a: 685b ldr r3, [r3, #4] - 800295c: 2b00 cmp r3, #0 - 800295e: d157 bne.n 8002a10 - { - return HAL_ERROR; - 8002960: 2301 movs r3, #1 - 8002962: e242 b.n 8002dea - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8002964: 687b ldr r3, [r7, #4] - 8002966: 685b ldr r3, [r3, #4] - 8002968: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800296c: d106 bne.n 800297c - 800296e: 4b76 ldr r3, [pc, #472] ; (8002b48 ) - 8002970: 681b ldr r3, [r3, #0] - 8002972: 4a75 ldr r2, [pc, #468] ; (8002b48 ) - 8002974: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8002978: 6013 str r3, [r2, #0] - 800297a: e01d b.n 80029b8 - 800297c: 687b ldr r3, [r7, #4] - 800297e: 685b ldr r3, [r3, #4] - 8002980: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 - 8002984: d10c bne.n 80029a0 - 8002986: 4b70 ldr r3, [pc, #448] ; (8002b48 ) - 8002988: 681b ldr r3, [r3, #0] - 800298a: 4a6f ldr r2, [pc, #444] ; (8002b48 ) - 800298c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 8002990: 6013 str r3, [r2, #0] - 8002992: 4b6d ldr r3, [pc, #436] ; (8002b48 ) - 8002994: 681b ldr r3, [r3, #0] - 8002996: 4a6c ldr r2, [pc, #432] ; (8002b48 ) - 8002998: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 800299c: 6013 str r3, [r2, #0] - 800299e: e00b b.n 80029b8 - 80029a0: 4b69 ldr r3, [pc, #420] ; (8002b48 ) - 80029a2: 681b ldr r3, [r3, #0] - 80029a4: 4a68 ldr r2, [pc, #416] ; (8002b48 ) - 80029a6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 80029aa: 6013 str r3, [r2, #0] - 80029ac: 4b66 ldr r3, [pc, #408] ; (8002b48 ) - 80029ae: 681b ldr r3, [r3, #0] - 80029b0: 4a65 ldr r2, [pc, #404] ; (8002b48 ) - 80029b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 80029b6: 6013 str r3, [r2, #0] - - /* Check the HSE State */ - if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) - 80029b8: 687b ldr r3, [r7, #4] - 80029ba: 685b ldr r3, [r3, #4] - 80029bc: 2b00 cmp r3, #0 - 80029be: d013 beq.n 80029e8 - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80029c0: f7ff fcbe bl 8002340 - 80029c4: 6138 str r0, [r7, #16] - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80029c6: e008 b.n 80029da - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 80029c8: f7ff fcba bl 8002340 - 80029cc: 4602 mov r2, r0 - 80029ce: 693b ldr r3, [r7, #16] - 80029d0: 1ad3 subs r3, r2, r3 - 80029d2: 2b64 cmp r3, #100 ; 0x64 - 80029d4: d901 bls.n 80029da - { - return HAL_TIMEOUT; - 80029d6: 2303 movs r3, #3 - 80029d8: e207 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80029da: 4b5b ldr r3, [pc, #364] ; (8002b48 ) - 80029dc: 681b ldr r3, [r3, #0] - 80029de: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80029e2: 2b00 cmp r3, #0 - 80029e4: d0f0 beq.n 80029c8 - 80029e6: e014 b.n 8002a12 - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80029e8: f7ff fcaa bl 8002340 - 80029ec: 6138 str r0, [r7, #16] - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 80029ee: e008 b.n 8002a02 - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 80029f0: f7ff fca6 bl 8002340 - 80029f4: 4602 mov r2, r0 - 80029f6: 693b ldr r3, [r7, #16] - 80029f8: 1ad3 subs r3, r2, r3 - 80029fa: 2b64 cmp r3, #100 ; 0x64 - 80029fc: d901 bls.n 8002a02 - { - return HAL_TIMEOUT; - 80029fe: 2303 movs r3, #3 - 8002a00: e1f3 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8002a02: 4b51 ldr r3, [pc, #324] ; (8002b48 ) - 8002a04: 681b ldr r3, [r3, #0] - 8002a06: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8002a0a: 2b00 cmp r3, #0 - 8002a0c: d1f0 bne.n 80029f0 - 8002a0e: e000 b.n 8002a12 - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8002a10: bf00 nop - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8002a12: 687b ldr r3, [r7, #4] - 8002a14: 681b ldr r3, [r3, #0] - 8002a16: f003 0302 and.w r3, r3, #2 - 8002a1a: 2b00 cmp r3, #0 - 8002a1c: d063 beq.n 8002ae6 - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - 8002a1e: 4b4a ldr r3, [pc, #296] ; (8002b48 ) - 8002a20: 689b ldr r3, [r3, #8] - 8002a22: f003 030c and.w r3, r3, #12 - 8002a26: 2b00 cmp r3, #0 - 8002a28: d00b beq.n 8002a42 - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8002a2a: 4b47 ldr r3, [pc, #284] ; (8002b48 ) - 8002a2c: 689b ldr r3, [r3, #8] - 8002a2e: f003 030c and.w r3, r3, #12 - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - 8002a32: 2b08 cmp r3, #8 - 8002a34: d11c bne.n 8002a70 - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8002a36: 4b44 ldr r3, [pc, #272] ; (8002b48 ) - 8002a38: 685b ldr r3, [r3, #4] - 8002a3a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8002a3e: 2b00 cmp r3, #0 - 8002a40: d116 bne.n 8002a70 - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8002a42: 4b41 ldr r3, [pc, #260] ; (8002b48 ) - 8002a44: 681b ldr r3, [r3, #0] - 8002a46: f003 0302 and.w r3, r3, #2 - 8002a4a: 2b00 cmp r3, #0 - 8002a4c: d005 beq.n 8002a5a - 8002a4e: 687b ldr r3, [r7, #4] - 8002a50: 68db ldr r3, [r3, #12] - 8002a52: 2b01 cmp r3, #1 - 8002a54: d001 beq.n 8002a5a - { - return HAL_ERROR; - 8002a56: 2301 movs r3, #1 - 8002a58: e1c7 b.n 8002dea - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8002a5a: 4b3b ldr r3, [pc, #236] ; (8002b48 ) - 8002a5c: 681b ldr r3, [r3, #0] - 8002a5e: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 8002a62: 687b ldr r3, [r7, #4] - 8002a64: 691b ldr r3, [r3, #16] - 8002a66: 00db lsls r3, r3, #3 - 8002a68: 4937 ldr r1, [pc, #220] ; (8002b48 ) - 8002a6a: 4313 orrs r3, r2 - 8002a6c: 600b str r3, [r1, #0] - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8002a6e: e03a b.n 8002ae6 - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - 8002a70: 687b ldr r3, [r7, #4] - 8002a72: 68db ldr r3, [r3, #12] - 8002a74: 2b00 cmp r3, #0 - 8002a76: d020 beq.n 8002aba - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - 8002a78: 4b34 ldr r3, [pc, #208] ; (8002b4c ) - 8002a7a: 2201 movs r2, #1 - 8002a7c: 601a str r2, [r3, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8002a7e: f7ff fc5f bl 8002340 - 8002a82: 6138 str r0, [r7, #16] - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8002a84: e008 b.n 8002a98 - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8002a86: f7ff fc5b bl 8002340 - 8002a8a: 4602 mov r2, r0 - 8002a8c: 693b ldr r3, [r7, #16] - 8002a8e: 1ad3 subs r3, r2, r3 - 8002a90: 2b02 cmp r3, #2 - 8002a92: d901 bls.n 8002a98 - { - return HAL_TIMEOUT; - 8002a94: 2303 movs r3, #3 - 8002a96: e1a8 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8002a98: 4b2b ldr r3, [pc, #172] ; (8002b48 ) - 8002a9a: 681b ldr r3, [r3, #0] - 8002a9c: f003 0302 and.w r3, r3, #2 - 8002aa0: 2b00 cmp r3, #0 - 8002aa2: d0f0 beq.n 8002a86 - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8002aa4: 4b28 ldr r3, [pc, #160] ; (8002b48 ) - 8002aa6: 681b ldr r3, [r3, #0] - 8002aa8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 8002aac: 687b ldr r3, [r7, #4] - 8002aae: 691b ldr r3, [r3, #16] - 8002ab0: 00db lsls r3, r3, #3 - 8002ab2: 4925 ldr r1, [pc, #148] ; (8002b48 ) - 8002ab4: 4313 orrs r3, r2 - 8002ab6: 600b str r3, [r1, #0] - 8002ab8: e015 b.n 8002ae6 - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - 8002aba: 4b24 ldr r3, [pc, #144] ; (8002b4c ) - 8002abc: 2200 movs r2, #0 - 8002abe: 601a str r2, [r3, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8002ac0: f7ff fc3e bl 8002340 - 8002ac4: 6138 str r0, [r7, #16] - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8002ac6: e008 b.n 8002ada - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8002ac8: f7ff fc3a bl 8002340 - 8002acc: 4602 mov r2, r0 - 8002ace: 693b ldr r3, [r7, #16] - 8002ad0: 1ad3 subs r3, r2, r3 - 8002ad2: 2b02 cmp r3, #2 - 8002ad4: d901 bls.n 8002ada - { - return HAL_TIMEOUT; - 8002ad6: 2303 movs r3, #3 - 8002ad8: e187 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8002ada: 4b1b ldr r3, [pc, #108] ; (8002b48 ) - 8002adc: 681b ldr r3, [r3, #0] - 8002ade: f003 0302 and.w r3, r3, #2 - 8002ae2: 2b00 cmp r3, #0 - 8002ae4: d1f0 bne.n 8002ac8 - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8002ae6: 687b ldr r3, [r7, #4] - 8002ae8: 681b ldr r3, [r3, #0] - 8002aea: f003 0308 and.w r3, r3, #8 - 8002aee: 2b00 cmp r3, #0 - 8002af0: d036 beq.n 8002b60 - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - 8002af2: 687b ldr r3, [r7, #4] - 8002af4: 695b ldr r3, [r3, #20] - 8002af6: 2b00 cmp r3, #0 - 8002af8: d016 beq.n 8002b28 - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - 8002afa: 4b15 ldr r3, [pc, #84] ; (8002b50 ) - 8002afc: 2201 movs r2, #1 - 8002afe: 601a str r2, [r3, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8002b00: f7ff fc1e bl 8002340 - 8002b04: 6138 str r0, [r7, #16] - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8002b06: e008 b.n 8002b1a - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8002b08: f7ff fc1a bl 8002340 - 8002b0c: 4602 mov r2, r0 - 8002b0e: 693b ldr r3, [r7, #16] - 8002b10: 1ad3 subs r3, r2, r3 - 8002b12: 2b02 cmp r3, #2 - 8002b14: d901 bls.n 8002b1a - { - return HAL_TIMEOUT; - 8002b16: 2303 movs r3, #3 - 8002b18: e167 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8002b1a: 4b0b ldr r3, [pc, #44] ; (8002b48 ) - 8002b1c: 6f5b ldr r3, [r3, #116] ; 0x74 - 8002b1e: f003 0302 and.w r3, r3, #2 - 8002b22: 2b00 cmp r3, #0 - 8002b24: d0f0 beq.n 8002b08 - 8002b26: e01b b.n 8002b60 - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - 8002b28: 4b09 ldr r3, [pc, #36] ; (8002b50 ) - 8002b2a: 2200 movs r2, #0 - 8002b2c: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002b2e: f7ff fc07 bl 8002340 - 8002b32: 6138 str r0, [r7, #16] - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8002b34: e00e b.n 8002b54 - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8002b36: f7ff fc03 bl 8002340 - 8002b3a: 4602 mov r2, r0 - 8002b3c: 693b ldr r3, [r7, #16] - 8002b3e: 1ad3 subs r3, r2, r3 - 8002b40: 2b02 cmp r3, #2 - 8002b42: d907 bls.n 8002b54 - { - return HAL_TIMEOUT; - 8002b44: 2303 movs r3, #3 - 8002b46: e150 b.n 8002dea - 8002b48: 40023800 .word 0x40023800 - 8002b4c: 42470000 .word 0x42470000 - 8002b50: 42470e80 .word 0x42470e80 - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8002b54: 4b88 ldr r3, [pc, #544] ; (8002d78 ) - 8002b56: 6f5b ldr r3, [r3, #116] ; 0x74 - 8002b58: f003 0302 and.w r3, r3, #2 - 8002b5c: 2b00 cmp r3, #0 - 8002b5e: d1ea bne.n 8002b36 - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8002b60: 687b ldr r3, [r7, #4] - 8002b62: 681b ldr r3, [r3, #0] - 8002b64: f003 0304 and.w r3, r3, #4 - 8002b68: 2b00 cmp r3, #0 - 8002b6a: f000 8097 beq.w 8002c9c - { - FlagStatus pwrclkchanged = RESET; - 8002b6e: 2300 movs r3, #0 - 8002b70: 75fb strb r3, [r7, #23] - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8002b72: 4b81 ldr r3, [pc, #516] ; (8002d78 ) - 8002b74: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002b76: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8002b7a: 2b00 cmp r3, #0 - 8002b7c: d10f bne.n 8002b9e - { - __HAL_RCC_PWR_CLK_ENABLE(); - 8002b7e: 2300 movs r3, #0 - 8002b80: 60bb str r3, [r7, #8] - 8002b82: 4b7d ldr r3, [pc, #500] ; (8002d78 ) - 8002b84: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002b86: 4a7c ldr r2, [pc, #496] ; (8002d78 ) - 8002b88: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8002b8c: 6413 str r3, [r2, #64] ; 0x40 - 8002b8e: 4b7a ldr r3, [pc, #488] ; (8002d78 ) - 8002b90: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002b92: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8002b96: 60bb str r3, [r7, #8] - 8002b98: 68bb ldr r3, [r7, #8] - pwrclkchanged = SET; - 8002b9a: 2301 movs r3, #1 - 8002b9c: 75fb strb r3, [r7, #23] - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8002b9e: 4b77 ldr r3, [pc, #476] ; (8002d7c ) - 8002ba0: 681b ldr r3, [r3, #0] - 8002ba2: f403 7380 and.w r3, r3, #256 ; 0x100 - 8002ba6: 2b00 cmp r3, #0 - 8002ba8: d118 bne.n 8002bdc - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - 8002baa: 4b74 ldr r3, [pc, #464] ; (8002d7c ) - 8002bac: 681b ldr r3, [r3, #0] - 8002bae: 4a73 ldr r2, [pc, #460] ; (8002d7c ) - 8002bb0: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8002bb4: 6013 str r3, [r2, #0] - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - 8002bb6: f7ff fbc3 bl 8002340 - 8002bba: 6138 str r0, [r7, #16] - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8002bbc: e008 b.n 8002bd0 - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8002bbe: f7ff fbbf bl 8002340 - 8002bc2: 4602 mov r2, r0 - 8002bc4: 693b ldr r3, [r7, #16] - 8002bc6: 1ad3 subs r3, r2, r3 - 8002bc8: 2b02 cmp r3, #2 - 8002bca: d901 bls.n 8002bd0 - { - return HAL_TIMEOUT; - 8002bcc: 2303 movs r3, #3 - 8002bce: e10c b.n 8002dea - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8002bd0: 4b6a ldr r3, [pc, #424] ; (8002d7c ) - 8002bd2: 681b ldr r3, [r3, #0] - 8002bd4: f403 7380 and.w r3, r3, #256 ; 0x100 - 8002bd8: 2b00 cmp r3, #0 - 8002bda: d0f0 beq.n 8002bbe - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8002bdc: 687b ldr r3, [r7, #4] - 8002bde: 689b ldr r3, [r3, #8] - 8002be0: 2b01 cmp r3, #1 - 8002be2: d106 bne.n 8002bf2 - 8002be4: 4b64 ldr r3, [pc, #400] ; (8002d78 ) - 8002be6: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002be8: 4a63 ldr r2, [pc, #396] ; (8002d78 ) - 8002bea: f043 0301 orr.w r3, r3, #1 - 8002bee: 6713 str r3, [r2, #112] ; 0x70 - 8002bf0: e01c b.n 8002c2c - 8002bf2: 687b ldr r3, [r7, #4] - 8002bf4: 689b ldr r3, [r3, #8] - 8002bf6: 2b05 cmp r3, #5 - 8002bf8: d10c bne.n 8002c14 - 8002bfa: 4b5f ldr r3, [pc, #380] ; (8002d78 ) - 8002bfc: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002bfe: 4a5e ldr r2, [pc, #376] ; (8002d78 ) - 8002c00: f043 0304 orr.w r3, r3, #4 - 8002c04: 6713 str r3, [r2, #112] ; 0x70 - 8002c06: 4b5c ldr r3, [pc, #368] ; (8002d78 ) - 8002c08: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002c0a: 4a5b ldr r2, [pc, #364] ; (8002d78 ) - 8002c0c: f043 0301 orr.w r3, r3, #1 - 8002c10: 6713 str r3, [r2, #112] ; 0x70 - 8002c12: e00b b.n 8002c2c - 8002c14: 4b58 ldr r3, [pc, #352] ; (8002d78 ) - 8002c16: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002c18: 4a57 ldr r2, [pc, #348] ; (8002d78 ) - 8002c1a: f023 0301 bic.w r3, r3, #1 - 8002c1e: 6713 str r3, [r2, #112] ; 0x70 - 8002c20: 4b55 ldr r3, [pc, #340] ; (8002d78 ) - 8002c22: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002c24: 4a54 ldr r2, [pc, #336] ; (8002d78 ) - 8002c26: f023 0304 bic.w r3, r3, #4 - 8002c2a: 6713 str r3, [r2, #112] ; 0x70 - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - 8002c2c: 687b ldr r3, [r7, #4] - 8002c2e: 689b ldr r3, [r3, #8] - 8002c30: 2b00 cmp r3, #0 - 8002c32: d015 beq.n 8002c60 - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8002c34: f7ff fb84 bl 8002340 - 8002c38: 6138 str r0, [r7, #16] - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8002c3a: e00a b.n 8002c52 - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8002c3c: f7ff fb80 bl 8002340 - 8002c40: 4602 mov r2, r0 - 8002c42: 693b ldr r3, [r7, #16] - 8002c44: 1ad3 subs r3, r2, r3 - 8002c46: f241 3288 movw r2, #5000 ; 0x1388 - 8002c4a: 4293 cmp r3, r2 - 8002c4c: d901 bls.n 8002c52 - { - return HAL_TIMEOUT; - 8002c4e: 2303 movs r3, #3 - 8002c50: e0cb b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8002c52: 4b49 ldr r3, [pc, #292] ; (8002d78 ) - 8002c54: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002c56: f003 0302 and.w r3, r3, #2 - 8002c5a: 2b00 cmp r3, #0 - 8002c5c: d0ee beq.n 8002c3c - 8002c5e: e014 b.n 8002c8a - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002c60: f7ff fb6e bl 8002340 - 8002c64: 6138 str r0, [r7, #16] - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8002c66: e00a b.n 8002c7e - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8002c68: f7ff fb6a bl 8002340 - 8002c6c: 4602 mov r2, r0 - 8002c6e: 693b ldr r3, [r7, #16] - 8002c70: 1ad3 subs r3, r2, r3 - 8002c72: f241 3288 movw r2, #5000 ; 0x1388 - 8002c76: 4293 cmp r3, r2 - 8002c78: d901 bls.n 8002c7e - { - return HAL_TIMEOUT; - 8002c7a: 2303 movs r3, #3 - 8002c7c: e0b5 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8002c7e: 4b3e ldr r3, [pc, #248] ; (8002d78 ) - 8002c80: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002c82: f003 0302 and.w r3, r3, #2 - 8002c86: 2b00 cmp r3, #0 - 8002c88: d1ee bne.n 8002c68 - } - } - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - 8002c8a: 7dfb ldrb r3, [r7, #23] - 8002c8c: 2b01 cmp r3, #1 - 8002c8e: d105 bne.n 8002c9c - { - __HAL_RCC_PWR_CLK_DISABLE(); - 8002c90: 4b39 ldr r3, [pc, #228] ; (8002d78 ) - 8002c92: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002c94: 4a38 ldr r2, [pc, #224] ; (8002d78 ) - 8002c96: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8002c9a: 6413 str r3, [r2, #64] ; 0x40 - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 8002c9c: 687b ldr r3, [r7, #4] - 8002c9e: 699b ldr r3, [r3, #24] - 8002ca0: 2b00 cmp r3, #0 - 8002ca2: f000 80a1 beq.w 8002de8 - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - 8002ca6: 4b34 ldr r3, [pc, #208] ; (8002d78 ) - 8002ca8: 689b ldr r3, [r3, #8] - 8002caa: f003 030c and.w r3, r3, #12 - 8002cae: 2b08 cmp r3, #8 - 8002cb0: d05c beq.n 8002d6c - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 8002cb2: 687b ldr r3, [r7, #4] - 8002cb4: 699b ldr r3, [r3, #24] - 8002cb6: 2b02 cmp r3, #2 - 8002cb8: d141 bne.n 8002d3e - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 8002cba: 4b31 ldr r3, [pc, #196] ; (8002d80 ) - 8002cbc: 2200 movs r2, #0 - 8002cbe: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002cc0: f7ff fb3e bl 8002340 - 8002cc4: 6138 str r0, [r7, #16] - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8002cc6: e008 b.n 8002cda - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8002cc8: f7ff fb3a bl 8002340 - 8002ccc: 4602 mov r2, r0 - 8002cce: 693b ldr r3, [r7, #16] - 8002cd0: 1ad3 subs r3, r2, r3 - 8002cd2: 2b02 cmp r3, #2 - 8002cd4: d901 bls.n 8002cda - { - return HAL_TIMEOUT; - 8002cd6: 2303 movs r3, #3 - 8002cd8: e087 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8002cda: 4b27 ldr r3, [pc, #156] ; (8002d78 ) - 8002cdc: 681b ldr r3, [r3, #0] - 8002cde: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002ce2: 2b00 cmp r3, #0 - 8002ce4: d1f0 bne.n 8002cc8 - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - 8002ce6: 687b ldr r3, [r7, #4] - 8002ce8: 69da ldr r2, [r3, #28] - 8002cea: 687b ldr r3, [r7, #4] - 8002cec: 6a1b ldr r3, [r3, #32] - 8002cee: 431a orrs r2, r3 - 8002cf0: 687b ldr r3, [r7, #4] - 8002cf2: 6a5b ldr r3, [r3, #36] ; 0x24 - 8002cf4: 019b lsls r3, r3, #6 - 8002cf6: 431a orrs r2, r3 - 8002cf8: 687b ldr r3, [r7, #4] - 8002cfa: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002cfc: 085b lsrs r3, r3, #1 - 8002cfe: 3b01 subs r3, #1 - 8002d00: 041b lsls r3, r3, #16 - 8002d02: 431a orrs r2, r3 - 8002d04: 687b ldr r3, [r7, #4] - 8002d06: 6adb ldr r3, [r3, #44] ; 0x2c - 8002d08: 061b lsls r3, r3, #24 - 8002d0a: 491b ldr r1, [pc, #108] ; (8002d78 ) - 8002d0c: 4313 orrs r3, r2 - 8002d0e: 604b str r3, [r1, #4] - RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ - (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - 8002d10: 4b1b ldr r3, [pc, #108] ; (8002d80 ) - 8002d12: 2201 movs r2, #1 - 8002d14: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002d16: f7ff fb13 bl 8002340 - 8002d1a: 6138 str r0, [r7, #16] - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8002d1c: e008 b.n 8002d30 - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8002d1e: f7ff fb0f bl 8002340 - 8002d22: 4602 mov r2, r0 - 8002d24: 693b ldr r3, [r7, #16] - 8002d26: 1ad3 subs r3, r2, r3 - 8002d28: 2b02 cmp r3, #2 - 8002d2a: d901 bls.n 8002d30 - { - return HAL_TIMEOUT; - 8002d2c: 2303 movs r3, #3 - 8002d2e: e05c b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8002d30: 4b11 ldr r3, [pc, #68] ; (8002d78 ) - 8002d32: 681b ldr r3, [r3, #0] - 8002d34: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002d38: 2b00 cmp r3, #0 - 8002d3a: d0f0 beq.n 8002d1e - 8002d3c: e054 b.n 8002de8 - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 8002d3e: 4b10 ldr r3, [pc, #64] ; (8002d80 ) - 8002d40: 2200 movs r2, #0 - 8002d42: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002d44: f7ff fafc bl 8002340 - 8002d48: 6138 str r0, [r7, #16] - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8002d4a: e008 b.n 8002d5e - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8002d4c: f7ff faf8 bl 8002340 - 8002d50: 4602 mov r2, r0 - 8002d52: 693b ldr r3, [r7, #16] - 8002d54: 1ad3 subs r3, r2, r3 - 8002d56: 2b02 cmp r3, #2 - 8002d58: d901 bls.n 8002d5e - { - return HAL_TIMEOUT; - 8002d5a: 2303 movs r3, #3 - 8002d5c: e045 b.n 8002dea - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8002d5e: 4b06 ldr r3, [pc, #24] ; (8002d78 ) - 8002d60: 681b ldr r3, [r3, #0] - 8002d62: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002d66: 2b00 cmp r3, #0 - 8002d68: d1f0 bne.n 8002d4c - 8002d6a: e03d b.n 8002de8 - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 8002d6c: 687b ldr r3, [r7, #4] - 8002d6e: 699b ldr r3, [r3, #24] - 8002d70: 2b01 cmp r3, #1 - 8002d72: d107 bne.n 8002d84 - { - return HAL_ERROR; - 8002d74: 2301 movs r3, #1 - 8002d76: e038 b.n 8002dea - 8002d78: 40023800 .word 0x40023800 - 8002d7c: 40007000 .word 0x40007000 - 8002d80: 42470060 .word 0x42470060 - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->PLLCFGR; - 8002d84: 4b1b ldr r3, [pc, #108] ; (8002df4 ) - 8002d86: 685b ldr r3, [r3, #4] - 8002d88: 60fb str r3, [r7, #12] - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) -#else - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 8002d8a: 687b ldr r3, [r7, #4] - 8002d8c: 699b ldr r3, [r3, #24] - 8002d8e: 2b01 cmp r3, #1 - 8002d90: d028 beq.n 8002de4 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8002d92: 68fb ldr r3, [r7, #12] - 8002d94: f403 0280 and.w r2, r3, #4194304 ; 0x400000 - 8002d98: 687b ldr r3, [r7, #4] - 8002d9a: 69db ldr r3, [r3, #28] - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 8002d9c: 429a cmp r2, r3 - 8002d9e: d121 bne.n 8002de4 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 8002da0: 68fb ldr r3, [r7, #12] - 8002da2: f003 023f and.w r2, r3, #63 ; 0x3f - 8002da6: 687b ldr r3, [r7, #4] - 8002da8: 6a1b ldr r3, [r3, #32] - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8002daa: 429a cmp r2, r3 - 8002dac: d11a bne.n 8002de4 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 8002dae: 68fa ldr r2, [r7, #12] - 8002db0: f647 73c0 movw r3, #32704 ; 0x7fc0 - 8002db4: 4013 ands r3, r2 - 8002db6: 687a ldr r2, [r7, #4] - 8002db8: 6a52 ldr r2, [r2, #36] ; 0x24 - 8002dba: 0192 lsls r2, r2, #6 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 8002dbc: 4293 cmp r3, r2 - 8002dbe: d111 bne.n 8002de4 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 8002dc0: 68fb ldr r3, [r7, #12] - 8002dc2: f403 3240 and.w r2, r3, #196608 ; 0x30000 - 8002dc6: 687b ldr r3, [r7, #4] - 8002dc8: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002dca: 085b lsrs r3, r3, #1 - 8002dcc: 3b01 subs r3, #1 - 8002dce: 041b lsls r3, r3, #16 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 8002dd0: 429a cmp r2, r3 - 8002dd2: d107 bne.n 8002de4 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) - 8002dd4: 68fb ldr r3, [r7, #12] - 8002dd6: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 - 8002dda: 687b ldr r3, [r7, #4] - 8002ddc: 6adb ldr r3, [r3, #44] ; 0x2c - 8002dde: 061b lsls r3, r3, #24 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 8002de0: 429a cmp r2, r3 - 8002de2: d001 beq.n 8002de8 -#endif - { - return HAL_ERROR; - 8002de4: 2301 movs r3, #1 - 8002de6: e000 b.n 8002dea - } - } - } - } - return HAL_OK; - 8002de8: 2300 movs r3, #0 -} - 8002dea: 4618 mov r0, r3 - 8002dec: 3718 adds r7, #24 - 8002dee: 46bd mov sp, r7 - 8002df0: bd80 pop {r7, pc} - 8002df2: bf00 nop - 8002df4: 40023800 .word 0x40023800 - -08002df8 : - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - 8002df8: b580 push {r7, lr} - 8002dfa: b084 sub sp, #16 - 8002dfc: af00 add r7, sp, #0 - 8002dfe: 6078 str r0, [r7, #4] - 8002e00: 6039 str r1, [r7, #0] - uint32_t tickstart; - - /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) - 8002e02: 687b ldr r3, [r7, #4] - 8002e04: 2b00 cmp r3, #0 - 8002e06: d101 bne.n 8002e0c - { - return HAL_ERROR; - 8002e08: 2301 movs r3, #1 - 8002e0a: e0cc b.n 8002fa6 - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) - 8002e0c: 4b68 ldr r3, [pc, #416] ; (8002fb0 ) - 8002e0e: 681b ldr r3, [r3, #0] - 8002e10: f003 0307 and.w r3, r3, #7 - 8002e14: 683a ldr r2, [r7, #0] - 8002e16: 429a cmp r2, r3 - 8002e18: d90c bls.n 8002e34 - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 8002e1a: 4b65 ldr r3, [pc, #404] ; (8002fb0 ) - 8002e1c: 683a ldr r2, [r7, #0] - 8002e1e: b2d2 uxtb r2, r2 - 8002e20: 701a strb r2, [r3, #0] - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8002e22: 4b63 ldr r3, [pc, #396] ; (8002fb0 ) - 8002e24: 681b ldr r3, [r3, #0] - 8002e26: f003 0307 and.w r3, r3, #7 - 8002e2a: 683a ldr r2, [r7, #0] - 8002e2c: 429a cmp r2, r3 - 8002e2e: d001 beq.n 8002e34 - { - return HAL_ERROR; - 8002e30: 2301 movs r3, #1 - 8002e32: e0b8 b.n 8002fa6 - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8002e34: 687b ldr r3, [r7, #4] - 8002e36: 681b ldr r3, [r3, #0] - 8002e38: f003 0302 and.w r3, r3, #2 - 8002e3c: 2b00 cmp r3, #0 - 8002e3e: d020 beq.n 8002e82 - { - /* Set the highest APBx dividers in order to ensure that we do not go through - a non-spec phase whatever we decrease or increase HCLK. */ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8002e40: 687b ldr r3, [r7, #4] - 8002e42: 681b ldr r3, [r3, #0] - 8002e44: f003 0304 and.w r3, r3, #4 - 8002e48: 2b00 cmp r3, #0 - 8002e4a: d005 beq.n 8002e58 - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 8002e4c: 4b59 ldr r3, [pc, #356] ; (8002fb4 ) - 8002e4e: 689b ldr r3, [r3, #8] - 8002e50: 4a58 ldr r2, [pc, #352] ; (8002fb4 ) - 8002e52: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 - 8002e56: 6093 str r3, [r2, #8] - } - - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8002e58: 687b ldr r3, [r7, #4] - 8002e5a: 681b ldr r3, [r3, #0] - 8002e5c: f003 0308 and.w r3, r3, #8 - 8002e60: 2b00 cmp r3, #0 - 8002e62: d005 beq.n 8002e70 - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8002e64: 4b53 ldr r3, [pc, #332] ; (8002fb4 ) - 8002e66: 689b ldr r3, [r3, #8] - 8002e68: 4a52 ldr r2, [pc, #328] ; (8002fb4 ) - 8002e6a: f443 4360 orr.w r3, r3, #57344 ; 0xe000 - 8002e6e: 6093 str r3, [r2, #8] - } - - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 8002e70: 4b50 ldr r3, [pc, #320] ; (8002fb4 ) - 8002e72: 689b ldr r3, [r3, #8] - 8002e74: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8002e78: 687b ldr r3, [r7, #4] - 8002e7a: 689b ldr r3, [r3, #8] - 8002e7c: 494d ldr r1, [pc, #308] ; (8002fb4 ) - 8002e7e: 4313 orrs r3, r2 - 8002e80: 608b str r3, [r1, #8] - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8002e82: 687b ldr r3, [r7, #4] - 8002e84: 681b ldr r3, [r3, #0] - 8002e86: f003 0301 and.w r3, r3, #1 - 8002e8a: 2b00 cmp r3, #0 - 8002e8c: d044 beq.n 8002f18 - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8002e8e: 687b ldr r3, [r7, #4] - 8002e90: 685b ldr r3, [r3, #4] - 8002e92: 2b01 cmp r3, #1 - 8002e94: d107 bne.n 8002ea6 - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8002e96: 4b47 ldr r3, [pc, #284] ; (8002fb4 ) - 8002e98: 681b ldr r3, [r3, #0] - 8002e9a: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8002e9e: 2b00 cmp r3, #0 - 8002ea0: d119 bne.n 8002ed6 - { - return HAL_ERROR; - 8002ea2: 2301 movs r3, #1 - 8002ea4: e07f b.n 8002fa6 - } - } - /* PLL is selected as System Clock Source */ - else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 8002ea6: 687b ldr r3, [r7, #4] - 8002ea8: 685b ldr r3, [r3, #4] - 8002eaa: 2b02 cmp r3, #2 - 8002eac: d003 beq.n 8002eb6 - (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) - 8002eae: 687b ldr r3, [r7, #4] - 8002eb0: 685b ldr r3, [r3, #4] - else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 8002eb2: 2b03 cmp r3, #3 - 8002eb4: d107 bne.n 8002ec6 - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8002eb6: 4b3f ldr r3, [pc, #252] ; (8002fb4 ) - 8002eb8: 681b ldr r3, [r3, #0] - 8002eba: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002ebe: 2b00 cmp r3, #0 - 8002ec0: d109 bne.n 8002ed6 - { - return HAL_ERROR; - 8002ec2: 2301 movs r3, #1 - 8002ec4: e06f b.n 8002fa6 - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8002ec6: 4b3b ldr r3, [pc, #236] ; (8002fb4 ) - 8002ec8: 681b ldr r3, [r3, #0] - 8002eca: f003 0302 and.w r3, r3, #2 - 8002ece: 2b00 cmp r3, #0 - 8002ed0: d101 bne.n 8002ed6 - { - return HAL_ERROR; - 8002ed2: 2301 movs r3, #1 - 8002ed4: e067 b.n 8002fa6 - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8002ed6: 4b37 ldr r3, [pc, #220] ; (8002fb4 ) - 8002ed8: 689b ldr r3, [r3, #8] - 8002eda: f023 0203 bic.w r2, r3, #3 - 8002ede: 687b ldr r3, [r7, #4] - 8002ee0: 685b ldr r3, [r3, #4] - 8002ee2: 4934 ldr r1, [pc, #208] ; (8002fb4 ) - 8002ee4: 4313 orrs r3, r2 - 8002ee6: 608b str r3, [r1, #8] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8002ee8: f7ff fa2a bl 8002340 - 8002eec: 60f8 str r0, [r7, #12] - - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8002eee: e00a b.n 8002f06 - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8002ef0: f7ff fa26 bl 8002340 - 8002ef4: 4602 mov r2, r0 - 8002ef6: 68fb ldr r3, [r7, #12] - 8002ef8: 1ad3 subs r3, r2, r3 - 8002efa: f241 3288 movw r2, #5000 ; 0x1388 - 8002efe: 4293 cmp r3, r2 - 8002f00: d901 bls.n 8002f06 - { - return HAL_TIMEOUT; - 8002f02: 2303 movs r3, #3 - 8002f04: e04f b.n 8002fa6 - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8002f06: 4b2b ldr r3, [pc, #172] ; (8002fb4 ) - 8002f08: 689b ldr r3, [r3, #8] - 8002f0a: f003 020c and.w r2, r3, #12 - 8002f0e: 687b ldr r3, [r7, #4] - 8002f10: 685b ldr r3, [r3, #4] - 8002f12: 009b lsls r3, r3, #2 - 8002f14: 429a cmp r2, r3 - 8002f16: d1eb bne.n 8002ef0 - } - } - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) - 8002f18: 4b25 ldr r3, [pc, #148] ; (8002fb0 ) - 8002f1a: 681b ldr r3, [r3, #0] - 8002f1c: f003 0307 and.w r3, r3, #7 - 8002f20: 683a ldr r2, [r7, #0] - 8002f22: 429a cmp r2, r3 - 8002f24: d20c bcs.n 8002f40 - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 8002f26: 4b22 ldr r3, [pc, #136] ; (8002fb0 ) - 8002f28: 683a ldr r2, [r7, #0] - 8002f2a: b2d2 uxtb r2, r2 - 8002f2c: 701a strb r2, [r3, #0] - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8002f2e: 4b20 ldr r3, [pc, #128] ; (8002fb0 ) - 8002f30: 681b ldr r3, [r3, #0] - 8002f32: f003 0307 and.w r3, r3, #7 - 8002f36: 683a ldr r2, [r7, #0] - 8002f38: 429a cmp r2, r3 - 8002f3a: d001 beq.n 8002f40 - { - return HAL_ERROR; - 8002f3c: 2301 movs r3, #1 - 8002f3e: e032 b.n 8002fa6 - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8002f40: 687b ldr r3, [r7, #4] - 8002f42: 681b ldr r3, [r3, #0] - 8002f44: f003 0304 and.w r3, r3, #4 - 8002f48: 2b00 cmp r3, #0 - 8002f4a: d008 beq.n 8002f5e - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8002f4c: 4b19 ldr r3, [pc, #100] ; (8002fb4 ) - 8002f4e: 689b ldr r3, [r3, #8] - 8002f50: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 - 8002f54: 687b ldr r3, [r7, #4] - 8002f56: 68db ldr r3, [r3, #12] - 8002f58: 4916 ldr r1, [pc, #88] ; (8002fb4 ) - 8002f5a: 4313 orrs r3, r2 - 8002f5c: 608b str r3, [r1, #8] - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8002f5e: 687b ldr r3, [r7, #4] - 8002f60: 681b ldr r3, [r3, #0] - 8002f62: f003 0308 and.w r3, r3, #8 - 8002f66: 2b00 cmp r3, #0 - 8002f68: d009 beq.n 8002f7e - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8002f6a: 4b12 ldr r3, [pc, #72] ; (8002fb4 ) - 8002f6c: 689b ldr r3, [r3, #8] - 8002f6e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 8002f72: 687b ldr r3, [r7, #4] - 8002f74: 691b ldr r3, [r3, #16] - 8002f76: 00db lsls r3, r3, #3 - 8002f78: 490e ldr r1, [pc, #56] ; (8002fb4 ) - 8002f7a: 4313 orrs r3, r2 - 8002f7c: 608b str r3, [r1, #8] - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - 8002f7e: f000 f821 bl 8002fc4 - 8002f82: 4602 mov r2, r0 - 8002f84: 4b0b ldr r3, [pc, #44] ; (8002fb4 ) - 8002f86: 689b ldr r3, [r3, #8] - 8002f88: 091b lsrs r3, r3, #4 - 8002f8a: f003 030f and.w r3, r3, #15 - 8002f8e: 490a ldr r1, [pc, #40] ; (8002fb8 ) - 8002f90: 5ccb ldrb r3, [r1, r3] - 8002f92: fa22 f303 lsr.w r3, r2, r3 - 8002f96: 4a09 ldr r2, [pc, #36] ; (8002fbc ) - 8002f98: 6013 str r3, [r2, #0] - - /* Configure the source of time base considering new system clocks settings */ - HAL_InitTick (uwTickPrio); - 8002f9a: 4b09 ldr r3, [pc, #36] ; (8002fc0 ) - 8002f9c: 681b ldr r3, [r3, #0] - 8002f9e: 4618 mov r0, r3 - 8002fa0: f7ff f98a bl 80022b8 - - return HAL_OK; - 8002fa4: 2300 movs r3, #0 -} - 8002fa6: 4618 mov r0, r3 - 8002fa8: 3710 adds r7, #16 - 8002faa: 46bd mov sp, r7 - 8002fac: bd80 pop {r7, pc} - 8002fae: bf00 nop - 8002fb0: 40023c00 .word 0x40023c00 - 8002fb4: 40023800 .word 0x40023800 - 8002fb8: 08004b70 .word 0x08004b70 - 8002fbc: 2000267c .word 0x2000267c - 8002fc0: 20002680 .word 0x20002680 - -08002fc4 : - * - * - * @retval SYSCLK frequency - */ -__weak uint32_t HAL_RCC_GetSysClockFreq(void) -{ - 8002fc4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 8002fc8: b094 sub sp, #80 ; 0x50 - 8002fca: af00 add r7, sp, #0 - uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; - 8002fcc: 2300 movs r3, #0 - 8002fce: 647b str r3, [r7, #68] ; 0x44 - 8002fd0: 2300 movs r3, #0 - 8002fd2: 64fb str r3, [r7, #76] ; 0x4c - 8002fd4: 2300 movs r3, #0 - 8002fd6: 643b str r3, [r7, #64] ; 0x40 - uint32_t sysclockfreq = 0U; - 8002fd8: 2300 movs r3, #0 - 8002fda: 64bb str r3, [r7, #72] ; 0x48 - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - 8002fdc: 4b79 ldr r3, [pc, #484] ; (80031c4 ) - 8002fde: 689b ldr r3, [r3, #8] - 8002fe0: f003 030c and.w r3, r3, #12 - 8002fe4: 2b08 cmp r3, #8 - 8002fe6: d00d beq.n 8003004 - 8002fe8: 2b08 cmp r3, #8 - 8002fea: f200 80e1 bhi.w 80031b0 - 8002fee: 2b00 cmp r3, #0 - 8002ff0: d002 beq.n 8002ff8 - 8002ff2: 2b04 cmp r3, #4 - 8002ff4: d003 beq.n 8002ffe - 8002ff6: e0db b.n 80031b0 - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - 8002ff8: 4b73 ldr r3, [pc, #460] ; (80031c8 ) - 8002ffa: 64bb str r3, [r7, #72] ; 0x48 - break; - 8002ffc: e0db b.n 80031b6 - } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - { - sysclockfreq = HSE_VALUE; - 8002ffe: 4b73 ldr r3, [pc, #460] ; (80031cc ) - 8003000: 64bb str r3, [r7, #72] ; 0x48 - break; - 8003002: e0d8 b.n 80031b6 - } - case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - 8003004: 4b6f ldr r3, [pc, #444] ; (80031c4 ) - 8003006: 685b ldr r3, [r3, #4] - 8003008: f003 033f and.w r3, r3, #63 ; 0x3f - 800300c: 647b str r3, [r7, #68] ; 0x44 - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - 800300e: 4b6d ldr r3, [pc, #436] ; (80031c4 ) - 8003010: 685b ldr r3, [r3, #4] - 8003012: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8003016: 2b00 cmp r3, #0 - 8003018: d063 beq.n 80030e2 - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 800301a: 4b6a ldr r3, [pc, #424] ; (80031c4 ) - 800301c: 685b ldr r3, [r3, #4] - 800301e: 099b lsrs r3, r3, #6 - 8003020: 2200 movs r2, #0 - 8003022: 63bb str r3, [r7, #56] ; 0x38 - 8003024: 63fa str r2, [r7, #60] ; 0x3c - 8003026: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003028: f3c3 0308 ubfx r3, r3, #0, #9 - 800302c: 633b str r3, [r7, #48] ; 0x30 - 800302e: 2300 movs r3, #0 - 8003030: 637b str r3, [r7, #52] ; 0x34 - 8003032: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30 - 8003036: 4622 mov r2, r4 - 8003038: 462b mov r3, r5 - 800303a: f04f 0000 mov.w r0, #0 - 800303e: f04f 0100 mov.w r1, #0 - 8003042: 0159 lsls r1, r3, #5 - 8003044: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 8003048: 0150 lsls r0, r2, #5 - 800304a: 4602 mov r2, r0 - 800304c: 460b mov r3, r1 - 800304e: 4621 mov r1, r4 - 8003050: 1a51 subs r1, r2, r1 - 8003052: 6139 str r1, [r7, #16] - 8003054: 4629 mov r1, r5 - 8003056: eb63 0301 sbc.w r3, r3, r1 - 800305a: 617b str r3, [r7, #20] - 800305c: f04f 0200 mov.w r2, #0 - 8003060: f04f 0300 mov.w r3, #0 - 8003064: e9d7 ab04 ldrd sl, fp, [r7, #16] - 8003068: 4659 mov r1, fp - 800306a: 018b lsls r3, r1, #6 - 800306c: 4651 mov r1, sl - 800306e: ea43 6391 orr.w r3, r3, r1, lsr #26 - 8003072: 4651 mov r1, sl - 8003074: 018a lsls r2, r1, #6 - 8003076: 4651 mov r1, sl - 8003078: ebb2 0801 subs.w r8, r2, r1 - 800307c: 4659 mov r1, fp - 800307e: eb63 0901 sbc.w r9, r3, r1 - 8003082: f04f 0200 mov.w r2, #0 - 8003086: f04f 0300 mov.w r3, #0 - 800308a: ea4f 03c9 mov.w r3, r9, lsl #3 - 800308e: ea43 7358 orr.w r3, r3, r8, lsr #29 - 8003092: ea4f 02c8 mov.w r2, r8, lsl #3 - 8003096: 4690 mov r8, r2 - 8003098: 4699 mov r9, r3 - 800309a: 4623 mov r3, r4 - 800309c: eb18 0303 adds.w r3, r8, r3 - 80030a0: 60bb str r3, [r7, #8] - 80030a2: 462b mov r3, r5 - 80030a4: eb49 0303 adc.w r3, r9, r3 - 80030a8: 60fb str r3, [r7, #12] - 80030aa: f04f 0200 mov.w r2, #0 - 80030ae: f04f 0300 mov.w r3, #0 - 80030b2: e9d7 4502 ldrd r4, r5, [r7, #8] - 80030b6: 4629 mov r1, r5 - 80030b8: 024b lsls r3, r1, #9 - 80030ba: 4621 mov r1, r4 - 80030bc: ea43 53d1 orr.w r3, r3, r1, lsr #23 - 80030c0: 4621 mov r1, r4 - 80030c2: 024a lsls r2, r1, #9 - 80030c4: 4610 mov r0, r2 - 80030c6: 4619 mov r1, r3 - 80030c8: 6c7b ldr r3, [r7, #68] ; 0x44 - 80030ca: 2200 movs r2, #0 - 80030cc: 62bb str r3, [r7, #40] ; 0x28 - 80030ce: 62fa str r2, [r7, #44] ; 0x2c - 80030d0: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 - 80030d4: f7fd fbd2 bl 800087c <__aeabi_uldivmod> - 80030d8: 4602 mov r2, r0 - 80030da: 460b mov r3, r1 - 80030dc: 4613 mov r3, r2 - 80030de: 64fb str r3, [r7, #76] ; 0x4c - 80030e0: e058 b.n 8003194 - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 80030e2: 4b38 ldr r3, [pc, #224] ; (80031c4 ) - 80030e4: 685b ldr r3, [r3, #4] - 80030e6: 099b lsrs r3, r3, #6 - 80030e8: 2200 movs r2, #0 - 80030ea: 4618 mov r0, r3 - 80030ec: 4611 mov r1, r2 - 80030ee: f3c0 0308 ubfx r3, r0, #0, #9 - 80030f2: 623b str r3, [r7, #32] - 80030f4: 2300 movs r3, #0 - 80030f6: 627b str r3, [r7, #36] ; 0x24 - 80030f8: e9d7 8908 ldrd r8, r9, [r7, #32] - 80030fc: 4642 mov r2, r8 - 80030fe: 464b mov r3, r9 - 8003100: f04f 0000 mov.w r0, #0 - 8003104: f04f 0100 mov.w r1, #0 - 8003108: 0159 lsls r1, r3, #5 - 800310a: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 800310e: 0150 lsls r0, r2, #5 - 8003110: 4602 mov r2, r0 - 8003112: 460b mov r3, r1 - 8003114: 4641 mov r1, r8 - 8003116: ebb2 0a01 subs.w sl, r2, r1 - 800311a: 4649 mov r1, r9 - 800311c: eb63 0b01 sbc.w fp, r3, r1 - 8003120: f04f 0200 mov.w r2, #0 - 8003124: f04f 0300 mov.w r3, #0 - 8003128: ea4f 138b mov.w r3, fp, lsl #6 - 800312c: ea43 639a orr.w r3, r3, sl, lsr #26 - 8003130: ea4f 128a mov.w r2, sl, lsl #6 - 8003134: ebb2 040a subs.w r4, r2, sl - 8003138: eb63 050b sbc.w r5, r3, fp - 800313c: f04f 0200 mov.w r2, #0 - 8003140: f04f 0300 mov.w r3, #0 - 8003144: 00eb lsls r3, r5, #3 - 8003146: ea43 7354 orr.w r3, r3, r4, lsr #29 - 800314a: 00e2 lsls r2, r4, #3 - 800314c: 4614 mov r4, r2 - 800314e: 461d mov r5, r3 - 8003150: 4643 mov r3, r8 - 8003152: 18e3 adds r3, r4, r3 - 8003154: 603b str r3, [r7, #0] - 8003156: 464b mov r3, r9 - 8003158: eb45 0303 adc.w r3, r5, r3 - 800315c: 607b str r3, [r7, #4] - 800315e: f04f 0200 mov.w r2, #0 - 8003162: f04f 0300 mov.w r3, #0 - 8003166: e9d7 4500 ldrd r4, r5, [r7] - 800316a: 4629 mov r1, r5 - 800316c: 028b lsls r3, r1, #10 - 800316e: 4621 mov r1, r4 - 8003170: ea43 5391 orr.w r3, r3, r1, lsr #22 - 8003174: 4621 mov r1, r4 - 8003176: 028a lsls r2, r1, #10 - 8003178: 4610 mov r0, r2 - 800317a: 4619 mov r1, r3 - 800317c: 6c7b ldr r3, [r7, #68] ; 0x44 - 800317e: 2200 movs r2, #0 - 8003180: 61bb str r3, [r7, #24] - 8003182: 61fa str r2, [r7, #28] - 8003184: e9d7 2306 ldrd r2, r3, [r7, #24] - 8003188: f7fd fb78 bl 800087c <__aeabi_uldivmod> - 800318c: 4602 mov r2, r0 - 800318e: 460b mov r3, r1 - 8003190: 4613 mov r3, r2 - 8003192: 64fb str r3, [r7, #76] ; 0x4c - } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); - 8003194: 4b0b ldr r3, [pc, #44] ; (80031c4 ) - 8003196: 685b ldr r3, [r3, #4] - 8003198: 0c1b lsrs r3, r3, #16 - 800319a: f003 0303 and.w r3, r3, #3 - 800319e: 3301 adds r3, #1 - 80031a0: 005b lsls r3, r3, #1 - 80031a2: 643b str r3, [r7, #64] ; 0x40 - - sysclockfreq = pllvco/pllp; - 80031a4: 6cfa ldr r2, [r7, #76] ; 0x4c - 80031a6: 6c3b ldr r3, [r7, #64] ; 0x40 - 80031a8: fbb2 f3f3 udiv r3, r2, r3 - 80031ac: 64bb str r3, [r7, #72] ; 0x48 - break; - 80031ae: e002 b.n 80031b6 - } - default: - { - sysclockfreq = HSI_VALUE; - 80031b0: 4b05 ldr r3, [pc, #20] ; (80031c8 ) - 80031b2: 64bb str r3, [r7, #72] ; 0x48 - break; - 80031b4: bf00 nop - } - } - return sysclockfreq; - 80031b6: 6cbb ldr r3, [r7, #72] ; 0x48 -} - 80031b8: 4618 mov r0, r3 - 80031ba: 3750 adds r7, #80 ; 0x50 - 80031bc: 46bd mov sp, r7 - 80031be: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 80031c2: bf00 nop - 80031c4: 40023800 .word 0x40023800 - 80031c8: 00f42400 .word 0x00f42400 - 80031cc: 007a1200 .word 0x007a1200 - -080031d0 : - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - 80031d0: b580 push {r7, lr} - 80031d2: b082 sub sp, #8 - 80031d4: af00 add r7, sp, #0 - 80031d6: 6078 str r0, [r7, #4] - /* Check the SPI handle allocation */ - if (hspi == NULL) - 80031d8: 687b ldr r3, [r7, #4] - 80031da: 2b00 cmp r3, #0 - 80031dc: d101 bne.n 80031e2 - { - return HAL_ERROR; - 80031de: 2301 movs r3, #1 - 80031e0: e07b b.n 80032da - assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_NSS(hspi->Init.NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); - if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) - 80031e2: 687b ldr r3, [r7, #4] - 80031e4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80031e6: 2b00 cmp r3, #0 - 80031e8: d108 bne.n 80031fc - { - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - - if (hspi->Init.Mode == SPI_MODE_MASTER) - 80031ea: 687b ldr r3, [r7, #4] - 80031ec: 685b ldr r3, [r3, #4] - 80031ee: f5b3 7f82 cmp.w r3, #260 ; 0x104 - 80031f2: d009 beq.n 8003208 - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - } - else - { - /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ - hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - 80031f4: 687b ldr r3, [r7, #4] - 80031f6: 2200 movs r2, #0 - 80031f8: 61da str r2, [r3, #28] - 80031fa: e005 b.n 8003208 - else - { - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - - /* Force polarity and phase to TI protocaol requirements */ - hspi->Init.CLKPolarity = SPI_POLARITY_LOW; - 80031fc: 687b ldr r3, [r7, #4] - 80031fe: 2200 movs r2, #0 - 8003200: 611a str r2, [r3, #16] - hspi->Init.CLKPhase = SPI_PHASE_1EDGE; - 8003202: 687b ldr r3, [r7, #4] - 8003204: 2200 movs r2, #0 - 8003206: 615a str r2, [r3, #20] - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - } -#else - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - 8003208: 687b ldr r3, [r7, #4] - 800320a: 2200 movs r2, #0 - 800320c: 629a str r2, [r3, #40] ; 0x28 -#endif /* USE_SPI_CRC */ - - if (hspi->State == HAL_SPI_STATE_RESET) - 800320e: 687b ldr r3, [r7, #4] - 8003210: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 - 8003214: b2db uxtb r3, r3 - 8003216: 2b00 cmp r3, #0 - 8003218: d106 bne.n 8003228 - { - /* Allocate lock resource and initialize it */ - hspi->Lock = HAL_UNLOCKED; - 800321a: 687b ldr r3, [r7, #4] - 800321c: 2200 movs r2, #0 - 800321e: f883 2050 strb.w r2, [r3, #80] ; 0x50 - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - hspi->MspInitCallback(hspi); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); - 8003222: 6878 ldr r0, [r7, #4] - 8003224: f7fe fdfe bl 8001e24 -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - - hspi->State = HAL_SPI_STATE_BUSY; - 8003228: 687b ldr r3, [r7, #4] - 800322a: 2202 movs r2, #2 - 800322c: f883 2051 strb.w r2, [r3, #81] ; 0x51 - - /* Disable the selected SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - 8003230: 687b ldr r3, [r7, #4] - 8003232: 681b ldr r3, [r3, #0] - 8003234: 681a ldr r2, [r3, #0] - 8003236: 687b ldr r3, [r7, #4] - 8003238: 681b ldr r3, [r3, #0] - 800323a: f022 0240 bic.w r2, r2, #64 ; 0x40 - 800323e: 601a str r2, [r3, #0] - - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ - /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, - Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | - 8003240: 687b ldr r3, [r7, #4] - 8003242: 685b ldr r3, [r3, #4] - 8003244: f403 7282 and.w r2, r3, #260 ; 0x104 - 8003248: 687b ldr r3, [r7, #4] - 800324a: 689b ldr r3, [r3, #8] - 800324c: f403 4304 and.w r3, r3, #33792 ; 0x8400 - 8003250: 431a orrs r2, r3 - 8003252: 687b ldr r3, [r7, #4] - 8003254: 68db ldr r3, [r3, #12] - 8003256: f403 6300 and.w r3, r3, #2048 ; 0x800 - 800325a: 431a orrs r2, r3 - 800325c: 687b ldr r3, [r7, #4] - 800325e: 691b ldr r3, [r3, #16] - 8003260: f003 0302 and.w r3, r3, #2 - 8003264: 431a orrs r2, r3 - 8003266: 687b ldr r3, [r7, #4] - 8003268: 695b ldr r3, [r3, #20] - 800326a: f003 0301 and.w r3, r3, #1 - 800326e: 431a orrs r2, r3 - 8003270: 687b ldr r3, [r7, #4] - 8003272: 699b ldr r3, [r3, #24] - 8003274: f403 7300 and.w r3, r3, #512 ; 0x200 - 8003278: 431a orrs r2, r3 - 800327a: 687b ldr r3, [r7, #4] - 800327c: 69db ldr r3, [r3, #28] - 800327e: f003 0338 and.w r3, r3, #56 ; 0x38 - 8003282: 431a orrs r2, r3 - 8003284: 687b ldr r3, [r7, #4] - 8003286: 6a1b ldr r3, [r3, #32] - 8003288: f003 0380 and.w r3, r3, #128 ; 0x80 - 800328c: ea42 0103 orr.w r1, r2, r3 - 8003290: 687b ldr r3, [r7, #4] - 8003292: 6a9b ldr r3, [r3, #40] ; 0x28 - 8003294: f403 5200 and.w r2, r3, #8192 ; 0x2000 - 8003298: 687b ldr r3, [r7, #4] - 800329a: 681b ldr r3, [r3, #0] - 800329c: 430a orrs r2, r1 - 800329e: 601a str r2, [r3, #0] - (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | - (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | - (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); - - /* Configure : NSS management, TI Mode */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); - 80032a0: 687b ldr r3, [r7, #4] - 80032a2: 699b ldr r3, [r3, #24] - 80032a4: 0c1b lsrs r3, r3, #16 - 80032a6: f003 0104 and.w r1, r3, #4 - 80032aa: 687b ldr r3, [r7, #4] - 80032ac: 6a5b ldr r3, [r3, #36] ; 0x24 - 80032ae: f003 0210 and.w r2, r3, #16 - 80032b2: 687b ldr r3, [r7, #4] - 80032b4: 681b ldr r3, [r3, #0] - 80032b6: 430a orrs r2, r1 - 80032b8: 605a str r2, [r3, #4] - } -#endif /* USE_SPI_CRC */ - -#if defined(SPI_I2SCFGR_I2SMOD) - /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ - CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); - 80032ba: 687b ldr r3, [r7, #4] - 80032bc: 681b ldr r3, [r3, #0] - 80032be: 69da ldr r2, [r3, #28] - 80032c0: 687b ldr r3, [r7, #4] - 80032c2: 681b ldr r3, [r3, #0] - 80032c4: f422 6200 bic.w r2, r2, #2048 ; 0x800 - 80032c8: 61da str r2, [r3, #28] -#endif /* SPI_I2SCFGR_I2SMOD */ - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - 80032ca: 687b ldr r3, [r7, #4] - 80032cc: 2200 movs r2, #0 - 80032ce: 655a str r2, [r3, #84] ; 0x54 - hspi->State = HAL_SPI_STATE_READY; - 80032d0: 687b ldr r3, [r7, #4] - 80032d2: 2201 movs r2, #1 - 80032d4: f883 2051 strb.w r2, [r3, #81] ; 0x51 - - return HAL_OK; - 80032d8: 2300 movs r3, #0 -} - 80032da: 4618 mov r0, r3 - 80032dc: 3708 adds r7, #8 - 80032de: 46bd mov sp, r7 - 80032e0: bd80 pop {r7, pc} - -080032e2 : - * @param Size amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - 80032e2: b580 push {r7, lr} - 80032e4: b088 sub sp, #32 - 80032e6: af00 add r7, sp, #0 - 80032e8: 60f8 str r0, [r7, #12] - 80032ea: 60b9 str r1, [r7, #8] - 80032ec: 603b str r3, [r7, #0] - 80032ee: 4613 mov r3, r2 - 80032f0: 80fb strh r3, [r7, #6] - uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; - 80032f2: 2300 movs r3, #0 - 80032f4: 77fb strb r3, [r7, #31] - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - 80032f6: 68fb ldr r3, [r7, #12] - 80032f8: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 - 80032fc: 2b01 cmp r3, #1 - 80032fe: d101 bne.n 8003304 - 8003300: 2302 movs r3, #2 - 8003302: e126 b.n 8003552 - 8003304: 68fb ldr r3, [r7, #12] - 8003306: 2201 movs r2, #1 - 8003308: f883 2050 strb.w r2, [r3, #80] ; 0x50 - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - 800330c: f7ff f818 bl 8002340 - 8003310: 61b8 str r0, [r7, #24] - initial_TxXferCount = Size; - 8003312: 88fb ldrh r3, [r7, #6] - 8003314: 82fb strh r3, [r7, #22] - - if (hspi->State != HAL_SPI_STATE_READY) - 8003316: 68fb ldr r3, [r7, #12] - 8003318: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 - 800331c: b2db uxtb r3, r3 - 800331e: 2b01 cmp r3, #1 - 8003320: d002 beq.n 8003328 - { - errorcode = HAL_BUSY; - 8003322: 2302 movs r3, #2 - 8003324: 77fb strb r3, [r7, #31] - goto error; - 8003326: e10b b.n 8003540 - } - - if ((pData == NULL) || (Size == 0U)) - 8003328: 68bb ldr r3, [r7, #8] - 800332a: 2b00 cmp r3, #0 - 800332c: d002 beq.n 8003334 - 800332e: 88fb ldrh r3, [r7, #6] - 8003330: 2b00 cmp r3, #0 - 8003332: d102 bne.n 800333a - { - errorcode = HAL_ERROR; - 8003334: 2301 movs r3, #1 - 8003336: 77fb strb r3, [r7, #31] - goto error; - 8003338: e102 b.n 8003540 - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - 800333a: 68fb ldr r3, [r7, #12] - 800333c: 2203 movs r2, #3 - 800333e: f883 2051 strb.w r2, [r3, #81] ; 0x51 - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - 8003342: 68fb ldr r3, [r7, #12] - 8003344: 2200 movs r2, #0 - 8003346: 655a str r2, [r3, #84] ; 0x54 - hspi->pTxBuffPtr = (uint8_t *)pData; - 8003348: 68fb ldr r3, [r7, #12] - 800334a: 68ba ldr r2, [r7, #8] - 800334c: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferSize = Size; - 800334e: 68fb ldr r3, [r7, #12] - 8003350: 88fa ldrh r2, [r7, #6] - 8003352: 869a strh r2, [r3, #52] ; 0x34 - hspi->TxXferCount = Size; - 8003354: 68fb ldr r3, [r7, #12] - 8003356: 88fa ldrh r2, [r7, #6] - 8003358: 86da strh r2, [r3, #54] ; 0x36 - - /*Init field not used in handle to zero */ - hspi->pRxBuffPtr = (uint8_t *)NULL; - 800335a: 68fb ldr r3, [r7, #12] - 800335c: 2200 movs r2, #0 - 800335e: 639a str r2, [r3, #56] ; 0x38 - hspi->RxXferSize = 0U; - 8003360: 68fb ldr r3, [r7, #12] - 8003362: 2200 movs r2, #0 - 8003364: 879a strh r2, [r3, #60] ; 0x3c - hspi->RxXferCount = 0U; - 8003366: 68fb ldr r3, [r7, #12] - 8003368: 2200 movs r2, #0 - 800336a: 87da strh r2, [r3, #62] ; 0x3e - hspi->TxISR = NULL; - 800336c: 68fb ldr r3, [r7, #12] - 800336e: 2200 movs r2, #0 - 8003370: 645a str r2, [r3, #68] ; 0x44 - hspi->RxISR = NULL; - 8003372: 68fb ldr r3, [r7, #12] - 8003374: 2200 movs r2, #0 - 8003376: 641a str r2, [r3, #64] ; 0x40 - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - 8003378: 68fb ldr r3, [r7, #12] - 800337a: 689b ldr r3, [r3, #8] - 800337c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8003380: d10f bne.n 80033a2 - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - 8003382: 68fb ldr r3, [r7, #12] - 8003384: 681b ldr r3, [r3, #0] - 8003386: 681a ldr r2, [r3, #0] - 8003388: 68fb ldr r3, [r7, #12] - 800338a: 681b ldr r3, [r3, #0] - 800338c: f022 0240 bic.w r2, r2, #64 ; 0x40 - 8003390: 601a str r2, [r3, #0] - SPI_1LINE_TX(hspi); - 8003392: 68fb ldr r3, [r7, #12] - 8003394: 681b ldr r3, [r3, #0] - 8003396: 681a ldr r2, [r3, #0] - 8003398: 68fb ldr r3, [r7, #12] - 800339a: 681b ldr r3, [r3, #0] - 800339c: f442 4280 orr.w r2, r2, #16384 ; 0x4000 - 80033a0: 601a str r2, [r3, #0] - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - 80033a2: 68fb ldr r3, [r7, #12] - 80033a4: 681b ldr r3, [r3, #0] - 80033a6: 681b ldr r3, [r3, #0] - 80033a8: f003 0340 and.w r3, r3, #64 ; 0x40 - 80033ac: 2b40 cmp r3, #64 ; 0x40 - 80033ae: d007 beq.n 80033c0 - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - 80033b0: 68fb ldr r3, [r7, #12] - 80033b2: 681b ldr r3, [r3, #0] - 80033b4: 681a ldr r2, [r3, #0] - 80033b6: 68fb ldr r3, [r7, #12] - 80033b8: 681b ldr r3, [r3, #0] - 80033ba: f042 0240 orr.w r2, r2, #64 ; 0x40 - 80033be: 601a str r2, [r3, #0] - } - - /* Transmit data in 16 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) - 80033c0: 68fb ldr r3, [r7, #12] - 80033c2: 68db ldr r3, [r3, #12] - 80033c4: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 80033c8: d14b bne.n 8003462 - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 80033ca: 68fb ldr r3, [r7, #12] - 80033cc: 685b ldr r3, [r3, #4] - 80033ce: 2b00 cmp r3, #0 - 80033d0: d002 beq.n 80033d8 - 80033d2: 8afb ldrh r3, [r7, #22] - 80033d4: 2b01 cmp r3, #1 - 80033d6: d13e bne.n 8003456 - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - 80033d8: 68fb ldr r3, [r7, #12] - 80033da: 6b1b ldr r3, [r3, #48] ; 0x30 - 80033dc: 881a ldrh r2, [r3, #0] - 80033de: 68fb ldr r3, [r7, #12] - 80033e0: 681b ldr r3, [r3, #0] - 80033e2: 60da str r2, [r3, #12] - hspi->pTxBuffPtr += sizeof(uint16_t); - 80033e4: 68fb ldr r3, [r7, #12] - 80033e6: 6b1b ldr r3, [r3, #48] ; 0x30 - 80033e8: 1c9a adds r2, r3, #2 - 80033ea: 68fb ldr r3, [r7, #12] - 80033ec: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 80033ee: 68fb ldr r3, [r7, #12] - 80033f0: 8edb ldrh r3, [r3, #54] ; 0x36 - 80033f2: b29b uxth r3, r3 - 80033f4: 3b01 subs r3, #1 - 80033f6: b29a uxth r2, r3 - 80033f8: 68fb ldr r3, [r7, #12] - 80033fa: 86da strh r2, [r3, #54] ; 0x36 - } - /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0U) - 80033fc: e02b b.n 8003456 - { - /* Wait until TXE flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - 80033fe: 68fb ldr r3, [r7, #12] - 8003400: 681b ldr r3, [r3, #0] - 8003402: 689b ldr r3, [r3, #8] - 8003404: f003 0302 and.w r3, r3, #2 - 8003408: 2b02 cmp r3, #2 - 800340a: d112 bne.n 8003432 - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - 800340c: 68fb ldr r3, [r7, #12] - 800340e: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003410: 881a ldrh r2, [r3, #0] - 8003412: 68fb ldr r3, [r7, #12] - 8003414: 681b ldr r3, [r3, #0] - 8003416: 60da str r2, [r3, #12] - hspi->pTxBuffPtr += sizeof(uint16_t); - 8003418: 68fb ldr r3, [r7, #12] - 800341a: 6b1b ldr r3, [r3, #48] ; 0x30 - 800341c: 1c9a adds r2, r3, #2 - 800341e: 68fb ldr r3, [r7, #12] - 8003420: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 8003422: 68fb ldr r3, [r7, #12] - 8003424: 8edb ldrh r3, [r3, #54] ; 0x36 - 8003426: b29b uxth r3, r3 - 8003428: 3b01 subs r3, #1 - 800342a: b29a uxth r2, r3 - 800342c: 68fb ldr r3, [r7, #12] - 800342e: 86da strh r2, [r3, #54] ; 0x36 - 8003430: e011 b.n 8003456 - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - 8003432: f7fe ff85 bl 8002340 - 8003436: 4602 mov r2, r0 - 8003438: 69bb ldr r3, [r7, #24] - 800343a: 1ad3 subs r3, r2, r3 - 800343c: 683a ldr r2, [r7, #0] - 800343e: 429a cmp r2, r3 - 8003440: d803 bhi.n 800344a - 8003442: 683b ldr r3, [r7, #0] - 8003444: f1b3 3fff cmp.w r3, #4294967295 - 8003448: d102 bne.n 8003450 - 800344a: 683b ldr r3, [r7, #0] - 800344c: 2b00 cmp r3, #0 - 800344e: d102 bne.n 8003456 - { - errorcode = HAL_TIMEOUT; - 8003450: 2303 movs r3, #3 - 8003452: 77fb strb r3, [r7, #31] - goto error; - 8003454: e074 b.n 8003540 - while (hspi->TxXferCount > 0U) - 8003456: 68fb ldr r3, [r7, #12] - 8003458: 8edb ldrh r3, [r3, #54] ; 0x36 - 800345a: b29b uxth r3, r3 - 800345c: 2b00 cmp r3, #0 - 800345e: d1ce bne.n 80033fe - 8003460: e04c b.n 80034fc - } - } - /* Transmit data in 8 Bit mode */ - else - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 8003462: 68fb ldr r3, [r7, #12] - 8003464: 685b ldr r3, [r3, #4] - 8003466: 2b00 cmp r3, #0 - 8003468: d002 beq.n 8003470 - 800346a: 8afb ldrh r3, [r7, #22] - 800346c: 2b01 cmp r3, #1 - 800346e: d140 bne.n 80034f2 - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - 8003470: 68fb ldr r3, [r7, #12] - 8003472: 6b1a ldr r2, [r3, #48] ; 0x30 - 8003474: 68fb ldr r3, [r7, #12] - 8003476: 681b ldr r3, [r3, #0] - 8003478: 330c adds r3, #12 - 800347a: 7812 ldrb r2, [r2, #0] - 800347c: 701a strb r2, [r3, #0] - hspi->pTxBuffPtr += sizeof(uint8_t); - 800347e: 68fb ldr r3, [r7, #12] - 8003480: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003482: 1c5a adds r2, r3, #1 - 8003484: 68fb ldr r3, [r7, #12] - 8003486: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 8003488: 68fb ldr r3, [r7, #12] - 800348a: 8edb ldrh r3, [r3, #54] ; 0x36 - 800348c: b29b uxth r3, r3 - 800348e: 3b01 subs r3, #1 - 8003490: b29a uxth r2, r3 - 8003492: 68fb ldr r3, [r7, #12] - 8003494: 86da strh r2, [r3, #54] ; 0x36 - } - while (hspi->TxXferCount > 0U) - 8003496: e02c b.n 80034f2 - { - /* Wait until TXE flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - 8003498: 68fb ldr r3, [r7, #12] - 800349a: 681b ldr r3, [r3, #0] - 800349c: 689b ldr r3, [r3, #8] - 800349e: f003 0302 and.w r3, r3, #2 - 80034a2: 2b02 cmp r3, #2 - 80034a4: d113 bne.n 80034ce - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - 80034a6: 68fb ldr r3, [r7, #12] - 80034a8: 6b1a ldr r2, [r3, #48] ; 0x30 - 80034aa: 68fb ldr r3, [r7, #12] - 80034ac: 681b ldr r3, [r3, #0] - 80034ae: 330c adds r3, #12 - 80034b0: 7812 ldrb r2, [r2, #0] - 80034b2: 701a strb r2, [r3, #0] - hspi->pTxBuffPtr += sizeof(uint8_t); - 80034b4: 68fb ldr r3, [r7, #12] - 80034b6: 6b1b ldr r3, [r3, #48] ; 0x30 - 80034b8: 1c5a adds r2, r3, #1 - 80034ba: 68fb ldr r3, [r7, #12] - 80034bc: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 80034be: 68fb ldr r3, [r7, #12] - 80034c0: 8edb ldrh r3, [r3, #54] ; 0x36 - 80034c2: b29b uxth r3, r3 - 80034c4: 3b01 subs r3, #1 - 80034c6: b29a uxth r2, r3 - 80034c8: 68fb ldr r3, [r7, #12] - 80034ca: 86da strh r2, [r3, #54] ; 0x36 - 80034cc: e011 b.n 80034f2 - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - 80034ce: f7fe ff37 bl 8002340 - 80034d2: 4602 mov r2, r0 - 80034d4: 69bb ldr r3, [r7, #24] - 80034d6: 1ad3 subs r3, r2, r3 - 80034d8: 683a ldr r2, [r7, #0] - 80034da: 429a cmp r2, r3 - 80034dc: d803 bhi.n 80034e6 - 80034de: 683b ldr r3, [r7, #0] - 80034e0: f1b3 3fff cmp.w r3, #4294967295 - 80034e4: d102 bne.n 80034ec - 80034e6: 683b ldr r3, [r7, #0] - 80034e8: 2b00 cmp r3, #0 - 80034ea: d102 bne.n 80034f2 - { - errorcode = HAL_TIMEOUT; - 80034ec: 2303 movs r3, #3 - 80034ee: 77fb strb r3, [r7, #31] - goto error; - 80034f0: e026 b.n 8003540 - while (hspi->TxXferCount > 0U) - 80034f2: 68fb ldr r3, [r7, #12] - 80034f4: 8edb ldrh r3, [r3, #54] ; 0x36 - 80034f6: b29b uxth r3, r3 - 80034f8: 2b00 cmp r3, #0 - 80034fa: d1cd bne.n 8003498 - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - 80034fc: 69ba ldr r2, [r7, #24] - 80034fe: 6839 ldr r1, [r7, #0] - 8003500: 68f8 ldr r0, [r7, #12] - 8003502: f000 fa55 bl 80039b0 - 8003506: 4603 mov r3, r0 - 8003508: 2b00 cmp r3, #0 - 800350a: d002 beq.n 8003512 - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - 800350c: 68fb ldr r3, [r7, #12] - 800350e: 2220 movs r2, #32 - 8003510: 655a str r2, [r3, #84] ; 0x54 - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - 8003512: 68fb ldr r3, [r7, #12] - 8003514: 689b ldr r3, [r3, #8] - 8003516: 2b00 cmp r3, #0 - 8003518: d10a bne.n 8003530 - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - 800351a: 2300 movs r3, #0 - 800351c: 613b str r3, [r7, #16] - 800351e: 68fb ldr r3, [r7, #12] - 8003520: 681b ldr r3, [r3, #0] - 8003522: 68db ldr r3, [r3, #12] - 8003524: 613b str r3, [r7, #16] - 8003526: 68fb ldr r3, [r7, #12] - 8003528: 681b ldr r3, [r3, #0] - 800352a: 689b ldr r3, [r3, #8] - 800352c: 613b str r3, [r7, #16] - 800352e: 693b ldr r3, [r7, #16] - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - 8003530: 68fb ldr r3, [r7, #12] - 8003532: 6d5b ldr r3, [r3, #84] ; 0x54 - 8003534: 2b00 cmp r3, #0 - 8003536: d002 beq.n 800353e - { - errorcode = HAL_ERROR; - 8003538: 2301 movs r3, #1 - 800353a: 77fb strb r3, [r7, #31] - 800353c: e000 b.n 8003540 - } - -error: - 800353e: bf00 nop - hspi->State = HAL_SPI_STATE_READY; - 8003540: 68fb ldr r3, [r7, #12] - 8003542: 2201 movs r2, #1 - 8003544: f883 2051 strb.w r2, [r3, #81] ; 0x51 - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - 8003548: 68fb ldr r3, [r7, #12] - 800354a: 2200 movs r2, #0 - 800354c: f883 2050 strb.w r2, [r3, #80] ; 0x50 - return errorcode; - 8003550: 7ffb ldrb r3, [r7, #31] -} - 8003552: 4618 mov r0, r3 - 8003554: 3720 adds r7, #32 - 8003556: 46bd mov sp, r7 - 8003558: bd80 pop {r7, pc} - -0800355a : - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) -{ - 800355a: b580 push {r7, lr} - 800355c: b08c sub sp, #48 ; 0x30 - 800355e: af00 add r7, sp, #0 - 8003560: 60f8 str r0, [r7, #12] - 8003562: 60b9 str r1, [r7, #8] - 8003564: 607a str r2, [r7, #4] - 8003566: 807b strh r3, [r7, #2] -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ - - /* Variable used to alternate Rx and Tx during transfer */ - uint32_t txallowed = 1U; - 8003568: 2301 movs r3, #1 - 800356a: 62fb str r3, [r7, #44] ; 0x2c - HAL_StatusTypeDef errorcode = HAL_OK; - 800356c: 2300 movs r3, #0 - 800356e: f887 302b strb.w r3, [r7, #43] ; 0x2b - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - 8003572: 68fb ldr r3, [r7, #12] - 8003574: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 - 8003578: 2b01 cmp r3, #1 - 800357a: d101 bne.n 8003580 - 800357c: 2302 movs r3, #2 - 800357e: e18a b.n 8003896 - 8003580: 68fb ldr r3, [r7, #12] - 8003582: 2201 movs r2, #1 - 8003584: f883 2050 strb.w r2, [r3, #80] ; 0x50 - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - 8003588: f7fe feda bl 8002340 - 800358c: 6278 str r0, [r7, #36] ; 0x24 - - /* Init temporary variables */ - tmp_state = hspi->State; - 800358e: 68fb ldr r3, [r7, #12] - 8003590: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 - 8003594: f887 3023 strb.w r3, [r7, #35] ; 0x23 - tmp_mode = hspi->Init.Mode; - 8003598: 68fb ldr r3, [r7, #12] - 800359a: 685b ldr r3, [r3, #4] - 800359c: 61fb str r3, [r7, #28] - initial_TxXferCount = Size; - 800359e: 887b ldrh r3, [r7, #2] - 80035a0: 837b strh r3, [r7, #26] - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - 80035a2: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 - 80035a6: 2b01 cmp r3, #1 - 80035a8: d00f beq.n 80035ca - 80035aa: 69fb ldr r3, [r7, #28] - 80035ac: f5b3 7f82 cmp.w r3, #260 ; 0x104 - 80035b0: d107 bne.n 80035c2 - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) - 80035b2: 68fb ldr r3, [r7, #12] - 80035b4: 689b ldr r3, [r3, #8] - 80035b6: 2b00 cmp r3, #0 - 80035b8: d103 bne.n 80035c2 - 80035ba: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 - 80035be: 2b04 cmp r3, #4 - 80035c0: d003 beq.n 80035ca - { - errorcode = HAL_BUSY; - 80035c2: 2302 movs r3, #2 - 80035c4: f887 302b strb.w r3, [r7, #43] ; 0x2b - goto error; - 80035c8: e15b b.n 8003882 - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - 80035ca: 68bb ldr r3, [r7, #8] - 80035cc: 2b00 cmp r3, #0 - 80035ce: d005 beq.n 80035dc - 80035d0: 687b ldr r3, [r7, #4] - 80035d2: 2b00 cmp r3, #0 - 80035d4: d002 beq.n 80035dc - 80035d6: 887b ldrh r3, [r7, #2] - 80035d8: 2b00 cmp r3, #0 - 80035da: d103 bne.n 80035e4 - { - errorcode = HAL_ERROR; - 80035dc: 2301 movs r3, #1 - 80035de: f887 302b strb.w r3, [r7, #43] ; 0x2b - goto error; - 80035e2: e14e b.n 8003882 - } - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - 80035e4: 68fb ldr r3, [r7, #12] - 80035e6: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 - 80035ea: b2db uxtb r3, r3 - 80035ec: 2b04 cmp r3, #4 - 80035ee: d003 beq.n 80035f8 - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - 80035f0: 68fb ldr r3, [r7, #12] - 80035f2: 2205 movs r2, #5 - 80035f4: f883 2051 strb.w r2, [r3, #81] ; 0x51 - } - - /* Set the transaction information */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - 80035f8: 68fb ldr r3, [r7, #12] - 80035fa: 2200 movs r2, #0 - 80035fc: 655a str r2, [r3, #84] ; 0x54 - hspi->pRxBuffPtr = (uint8_t *)pRxData; - 80035fe: 68fb ldr r3, [r7, #12] - 8003600: 687a ldr r2, [r7, #4] - 8003602: 639a str r2, [r3, #56] ; 0x38 - hspi->RxXferCount = Size; - 8003604: 68fb ldr r3, [r7, #12] - 8003606: 887a ldrh r2, [r7, #2] - 8003608: 87da strh r2, [r3, #62] ; 0x3e - hspi->RxXferSize = Size; - 800360a: 68fb ldr r3, [r7, #12] - 800360c: 887a ldrh r2, [r7, #2] - 800360e: 879a strh r2, [r3, #60] ; 0x3c - hspi->pTxBuffPtr = (uint8_t *)pTxData; - 8003610: 68fb ldr r3, [r7, #12] - 8003612: 68ba ldr r2, [r7, #8] - 8003614: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount = Size; - 8003616: 68fb ldr r3, [r7, #12] - 8003618: 887a ldrh r2, [r7, #2] - 800361a: 86da strh r2, [r3, #54] ; 0x36 - hspi->TxXferSize = Size; - 800361c: 68fb ldr r3, [r7, #12] - 800361e: 887a ldrh r2, [r7, #2] - 8003620: 869a strh r2, [r3, #52] ; 0x34 - - /*Init field not used in handle to zero */ - hspi->RxISR = NULL; - 8003622: 68fb ldr r3, [r7, #12] - 8003624: 2200 movs r2, #0 - 8003626: 641a str r2, [r3, #64] ; 0x40 - hspi->TxISR = NULL; - 8003628: 68fb ldr r3, [r7, #12] - 800362a: 2200 movs r2, #0 - 800362c: 645a str r2, [r3, #68] ; 0x44 - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - 800362e: 68fb ldr r3, [r7, #12] - 8003630: 681b ldr r3, [r3, #0] - 8003632: 681b ldr r3, [r3, #0] - 8003634: f003 0340 and.w r3, r3, #64 ; 0x40 - 8003638: 2b40 cmp r3, #64 ; 0x40 - 800363a: d007 beq.n 800364c - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - 800363c: 68fb ldr r3, [r7, #12] - 800363e: 681b ldr r3, [r3, #0] - 8003640: 681a ldr r2, [r3, #0] - 8003642: 68fb ldr r3, [r7, #12] - 8003644: 681b ldr r3, [r3, #0] - 8003646: f042 0240 orr.w r2, r2, #64 ; 0x40 - 800364a: 601a str r2, [r3, #0] - } - - /* Transmit and Receive data in 16 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) - 800364c: 68fb ldr r3, [r7, #12] - 800364e: 68db ldr r3, [r3, #12] - 8003650: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 8003654: d178 bne.n 8003748 - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 8003656: 68fb ldr r3, [r7, #12] - 8003658: 685b ldr r3, [r3, #4] - 800365a: 2b00 cmp r3, #0 - 800365c: d002 beq.n 8003664 - 800365e: 8b7b ldrh r3, [r7, #26] - 8003660: 2b01 cmp r3, #1 - 8003662: d166 bne.n 8003732 - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - 8003664: 68fb ldr r3, [r7, #12] - 8003666: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003668: 881a ldrh r2, [r3, #0] - 800366a: 68fb ldr r3, [r7, #12] - 800366c: 681b ldr r3, [r3, #0] - 800366e: 60da str r2, [r3, #12] - hspi->pTxBuffPtr += sizeof(uint16_t); - 8003670: 68fb ldr r3, [r7, #12] - 8003672: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003674: 1c9a adds r2, r3, #2 - 8003676: 68fb ldr r3, [r7, #12] - 8003678: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 800367a: 68fb ldr r3, [r7, #12] - 800367c: 8edb ldrh r3, [r3, #54] ; 0x36 - 800367e: b29b uxth r3, r3 - 8003680: 3b01 subs r3, #1 - 8003682: b29a uxth r2, r3 - 8003684: 68fb ldr r3, [r7, #12] - 8003686: 86da strh r2, [r3, #54] ; 0x36 - } - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - 8003688: e053 b.n 8003732 - { - /* Check TXE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) - 800368a: 68fb ldr r3, [r7, #12] - 800368c: 681b ldr r3, [r3, #0] - 800368e: 689b ldr r3, [r3, #8] - 8003690: f003 0302 and.w r3, r3, #2 - 8003694: 2b02 cmp r3, #2 - 8003696: d11b bne.n 80036d0 - 8003698: 68fb ldr r3, [r7, #12] - 800369a: 8edb ldrh r3, [r3, #54] ; 0x36 - 800369c: b29b uxth r3, r3 - 800369e: 2b00 cmp r3, #0 - 80036a0: d016 beq.n 80036d0 - 80036a2: 6afb ldr r3, [r7, #44] ; 0x2c - 80036a4: 2b01 cmp r3, #1 - 80036a6: d113 bne.n 80036d0 - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - 80036a8: 68fb ldr r3, [r7, #12] - 80036aa: 6b1b ldr r3, [r3, #48] ; 0x30 - 80036ac: 881a ldrh r2, [r3, #0] - 80036ae: 68fb ldr r3, [r7, #12] - 80036b0: 681b ldr r3, [r3, #0] - 80036b2: 60da str r2, [r3, #12] - hspi->pTxBuffPtr += sizeof(uint16_t); - 80036b4: 68fb ldr r3, [r7, #12] - 80036b6: 6b1b ldr r3, [r3, #48] ; 0x30 - 80036b8: 1c9a adds r2, r3, #2 - 80036ba: 68fb ldr r3, [r7, #12] - 80036bc: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 80036be: 68fb ldr r3, [r7, #12] - 80036c0: 8edb ldrh r3, [r3, #54] ; 0x36 - 80036c2: b29b uxth r3, r3 - 80036c4: 3b01 subs r3, #1 - 80036c6: b29a uxth r2, r3 - 80036c8: 68fb ldr r3, [r7, #12] - 80036ca: 86da strh r2, [r3, #54] ; 0x36 - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - 80036cc: 2300 movs r3, #0 - 80036ce: 62fb str r3, [r7, #44] ; 0x2c - } -#endif /* USE_SPI_CRC */ - } - - /* Check RXNE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) - 80036d0: 68fb ldr r3, [r7, #12] - 80036d2: 681b ldr r3, [r3, #0] - 80036d4: 689b ldr r3, [r3, #8] - 80036d6: f003 0301 and.w r3, r3, #1 - 80036da: 2b01 cmp r3, #1 - 80036dc: d119 bne.n 8003712 - 80036de: 68fb ldr r3, [r7, #12] - 80036e0: 8fdb ldrh r3, [r3, #62] ; 0x3e - 80036e2: b29b uxth r3, r3 - 80036e4: 2b00 cmp r3, #0 - 80036e6: d014 beq.n 8003712 - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - 80036e8: 68fb ldr r3, [r7, #12] - 80036ea: 681b ldr r3, [r3, #0] - 80036ec: 68da ldr r2, [r3, #12] - 80036ee: 68fb ldr r3, [r7, #12] - 80036f0: 6b9b ldr r3, [r3, #56] ; 0x38 - 80036f2: b292 uxth r2, r2 - 80036f4: 801a strh r2, [r3, #0] - hspi->pRxBuffPtr += sizeof(uint16_t); - 80036f6: 68fb ldr r3, [r7, #12] - 80036f8: 6b9b ldr r3, [r3, #56] ; 0x38 - 80036fa: 1c9a adds r2, r3, #2 - 80036fc: 68fb ldr r3, [r7, #12] - 80036fe: 639a str r2, [r3, #56] ; 0x38 - hspi->RxXferCount--; - 8003700: 68fb ldr r3, [r7, #12] - 8003702: 8fdb ldrh r3, [r3, #62] ; 0x3e - 8003704: b29b uxth r3, r3 - 8003706: 3b01 subs r3, #1 - 8003708: b29a uxth r2, r3 - 800370a: 68fb ldr r3, [r7, #12] - 800370c: 87da strh r2, [r3, #62] ; 0x3e - /* Next Data is a Transmission (Tx). Tx is allowed */ - txallowed = 1U; - 800370e: 2301 movs r3, #1 - 8003710: 62fb str r3, [r7, #44] ; 0x2c - } - if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) - 8003712: f7fe fe15 bl 8002340 - 8003716: 4602 mov r2, r0 - 8003718: 6a7b ldr r3, [r7, #36] ; 0x24 - 800371a: 1ad3 subs r3, r2, r3 - 800371c: 6bba ldr r2, [r7, #56] ; 0x38 - 800371e: 429a cmp r2, r3 - 8003720: d807 bhi.n 8003732 - 8003722: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003724: f1b3 3fff cmp.w r3, #4294967295 - 8003728: d003 beq.n 8003732 - { - errorcode = HAL_TIMEOUT; - 800372a: 2303 movs r3, #3 - 800372c: f887 302b strb.w r3, [r7, #43] ; 0x2b - goto error; - 8003730: e0a7 b.n 8003882 - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - 8003732: 68fb ldr r3, [r7, #12] - 8003734: 8edb ldrh r3, [r3, #54] ; 0x36 - 8003736: b29b uxth r3, r3 - 8003738: 2b00 cmp r3, #0 - 800373a: d1a6 bne.n 800368a - 800373c: 68fb ldr r3, [r7, #12] - 800373e: 8fdb ldrh r3, [r3, #62] ; 0x3e - 8003740: b29b uxth r3, r3 - 8003742: 2b00 cmp r3, #0 - 8003744: d1a1 bne.n 800368a - 8003746: e07c b.n 8003842 - } - } - /* Transmit and Receive data in 8 Bit mode */ - else - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 8003748: 68fb ldr r3, [r7, #12] - 800374a: 685b ldr r3, [r3, #4] - 800374c: 2b00 cmp r3, #0 - 800374e: d002 beq.n 8003756 - 8003750: 8b7b ldrh r3, [r7, #26] - 8003752: 2b01 cmp r3, #1 - 8003754: d16b bne.n 800382e - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - 8003756: 68fb ldr r3, [r7, #12] - 8003758: 6b1a ldr r2, [r3, #48] ; 0x30 - 800375a: 68fb ldr r3, [r7, #12] - 800375c: 681b ldr r3, [r3, #0] - 800375e: 330c adds r3, #12 - 8003760: 7812 ldrb r2, [r2, #0] - 8003762: 701a strb r2, [r3, #0] - hspi->pTxBuffPtr += sizeof(uint8_t); - 8003764: 68fb ldr r3, [r7, #12] - 8003766: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003768: 1c5a adds r2, r3, #1 - 800376a: 68fb ldr r3, [r7, #12] - 800376c: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 800376e: 68fb ldr r3, [r7, #12] - 8003770: 8edb ldrh r3, [r3, #54] ; 0x36 - 8003772: b29b uxth r3, r3 - 8003774: 3b01 subs r3, #1 - 8003776: b29a uxth r2, r3 - 8003778: 68fb ldr r3, [r7, #12] - 800377a: 86da strh r2, [r3, #54] ; 0x36 - } - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - 800377c: e057 b.n 800382e - { - /* Check TXE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) - 800377e: 68fb ldr r3, [r7, #12] - 8003780: 681b ldr r3, [r3, #0] - 8003782: 689b ldr r3, [r3, #8] - 8003784: f003 0302 and.w r3, r3, #2 - 8003788: 2b02 cmp r3, #2 - 800378a: d11c bne.n 80037c6 - 800378c: 68fb ldr r3, [r7, #12] - 800378e: 8edb ldrh r3, [r3, #54] ; 0x36 - 8003790: b29b uxth r3, r3 - 8003792: 2b00 cmp r3, #0 - 8003794: d017 beq.n 80037c6 - 8003796: 6afb ldr r3, [r7, #44] ; 0x2c - 8003798: 2b01 cmp r3, #1 - 800379a: d114 bne.n 80037c6 - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - 800379c: 68fb ldr r3, [r7, #12] - 800379e: 6b1a ldr r2, [r3, #48] ; 0x30 - 80037a0: 68fb ldr r3, [r7, #12] - 80037a2: 681b ldr r3, [r3, #0] - 80037a4: 330c adds r3, #12 - 80037a6: 7812 ldrb r2, [r2, #0] - 80037a8: 701a strb r2, [r3, #0] - hspi->pTxBuffPtr++; - 80037aa: 68fb ldr r3, [r7, #12] - 80037ac: 6b1b ldr r3, [r3, #48] ; 0x30 - 80037ae: 1c5a adds r2, r3, #1 - 80037b0: 68fb ldr r3, [r7, #12] - 80037b2: 631a str r2, [r3, #48] ; 0x30 - hspi->TxXferCount--; - 80037b4: 68fb ldr r3, [r7, #12] - 80037b6: 8edb ldrh r3, [r3, #54] ; 0x36 - 80037b8: b29b uxth r3, r3 - 80037ba: 3b01 subs r3, #1 - 80037bc: b29a uxth r2, r3 - 80037be: 68fb ldr r3, [r7, #12] - 80037c0: 86da strh r2, [r3, #54] ; 0x36 - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - 80037c2: 2300 movs r3, #0 - 80037c4: 62fb str r3, [r7, #44] ; 0x2c - } -#endif /* USE_SPI_CRC */ - } - - /* Wait until RXNE flag is reset */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) - 80037c6: 68fb ldr r3, [r7, #12] - 80037c8: 681b ldr r3, [r3, #0] - 80037ca: 689b ldr r3, [r3, #8] - 80037cc: f003 0301 and.w r3, r3, #1 - 80037d0: 2b01 cmp r3, #1 - 80037d2: d119 bne.n 8003808 - 80037d4: 68fb ldr r3, [r7, #12] - 80037d6: 8fdb ldrh r3, [r3, #62] ; 0x3e - 80037d8: b29b uxth r3, r3 - 80037da: 2b00 cmp r3, #0 - 80037dc: d014 beq.n 8003808 - { - (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - 80037de: 68fb ldr r3, [r7, #12] - 80037e0: 681b ldr r3, [r3, #0] - 80037e2: 68da ldr r2, [r3, #12] - 80037e4: 68fb ldr r3, [r7, #12] - 80037e6: 6b9b ldr r3, [r3, #56] ; 0x38 - 80037e8: b2d2 uxtb r2, r2 - 80037ea: 701a strb r2, [r3, #0] - hspi->pRxBuffPtr++; - 80037ec: 68fb ldr r3, [r7, #12] - 80037ee: 6b9b ldr r3, [r3, #56] ; 0x38 - 80037f0: 1c5a adds r2, r3, #1 - 80037f2: 68fb ldr r3, [r7, #12] - 80037f4: 639a str r2, [r3, #56] ; 0x38 - hspi->RxXferCount--; - 80037f6: 68fb ldr r3, [r7, #12] - 80037f8: 8fdb ldrh r3, [r3, #62] ; 0x3e - 80037fa: b29b uxth r3, r3 - 80037fc: 3b01 subs r3, #1 - 80037fe: b29a uxth r2, r3 - 8003800: 68fb ldr r3, [r7, #12] - 8003802: 87da strh r2, [r3, #62] ; 0x3e - /* Next Data is a Transmission (Tx). Tx is allowed */ - txallowed = 1U; - 8003804: 2301 movs r3, #1 - 8003806: 62fb str r3, [r7, #44] ; 0x2c - } - if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) - 8003808: f7fe fd9a bl 8002340 - 800380c: 4602 mov r2, r0 - 800380e: 6a7b ldr r3, [r7, #36] ; 0x24 - 8003810: 1ad3 subs r3, r2, r3 - 8003812: 6bba ldr r2, [r7, #56] ; 0x38 - 8003814: 429a cmp r2, r3 - 8003816: d803 bhi.n 8003820 - 8003818: 6bbb ldr r3, [r7, #56] ; 0x38 - 800381a: f1b3 3fff cmp.w r3, #4294967295 - 800381e: d102 bne.n 8003826 - 8003820: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003822: 2b00 cmp r3, #0 - 8003824: d103 bne.n 800382e - { - errorcode = HAL_TIMEOUT; - 8003826: 2303 movs r3, #3 - 8003828: f887 302b strb.w r3, [r7, #43] ; 0x2b - goto error; - 800382c: e029 b.n 8003882 - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - 800382e: 68fb ldr r3, [r7, #12] - 8003830: 8edb ldrh r3, [r3, #54] ; 0x36 - 8003832: b29b uxth r3, r3 - 8003834: 2b00 cmp r3, #0 - 8003836: d1a2 bne.n 800377e - 8003838: 68fb ldr r3, [r7, #12] - 800383a: 8fdb ldrh r3, [r3, #62] ; 0x3e - 800383c: b29b uxth r3, r3 - 800383e: 2b00 cmp r3, #0 - 8003840: d19d bne.n 800377e - errorcode = HAL_ERROR; - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - 8003842: 6a7a ldr r2, [r7, #36] ; 0x24 - 8003844: 6bb9 ldr r1, [r7, #56] ; 0x38 - 8003846: 68f8 ldr r0, [r7, #12] - 8003848: f000 f8b2 bl 80039b0 - 800384c: 4603 mov r3, r0 - 800384e: 2b00 cmp r3, #0 - 8003850: d006 beq.n 8003860 - { - errorcode = HAL_ERROR; - 8003852: 2301 movs r3, #1 - 8003854: f887 302b strb.w r3, [r7, #43] ; 0x2b - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - 8003858: 68fb ldr r3, [r7, #12] - 800385a: 2220 movs r2, #32 - 800385c: 655a str r2, [r3, #84] ; 0x54 - goto error; - 800385e: e010 b.n 8003882 - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - 8003860: 68fb ldr r3, [r7, #12] - 8003862: 689b ldr r3, [r3, #8] - 8003864: 2b00 cmp r3, #0 - 8003866: d10b bne.n 8003880 - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - 8003868: 2300 movs r3, #0 - 800386a: 617b str r3, [r7, #20] - 800386c: 68fb ldr r3, [r7, #12] - 800386e: 681b ldr r3, [r3, #0] - 8003870: 68db ldr r3, [r3, #12] - 8003872: 617b str r3, [r7, #20] - 8003874: 68fb ldr r3, [r7, #12] - 8003876: 681b ldr r3, [r3, #0] - 8003878: 689b ldr r3, [r3, #8] - 800387a: 617b str r3, [r7, #20] - 800387c: 697b ldr r3, [r7, #20] - 800387e: e000 b.n 8003882 - } - -error : - 8003880: bf00 nop - hspi->State = HAL_SPI_STATE_READY; - 8003882: 68fb ldr r3, [r7, #12] - 8003884: 2201 movs r2, #1 - 8003886: f883 2051 strb.w r2, [r3, #81] ; 0x51 - __HAL_UNLOCK(hspi); - 800388a: 68fb ldr r3, [r7, #12] - 800388c: 2200 movs r2, #0 - 800388e: f883 2050 strb.w r2, [r3, #80] ; 0x50 - return errorcode; - 8003892: f897 302b ldrb.w r3, [r7, #43] ; 0x2b -} - 8003896: 4618 mov r0, r3 - 8003898: 3730 adds r7, #48 ; 0x30 - 800389a: 46bd mov sp, r7 - 800389c: bd80 pop {r7, pc} - ... - -080038a0 : - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, - uint32_t Timeout, uint32_t Tickstart) -{ - 80038a0: b580 push {r7, lr} - 80038a2: b088 sub sp, #32 - 80038a4: af00 add r7, sp, #0 - 80038a6: 60f8 str r0, [r7, #12] - 80038a8: 60b9 str r1, [r7, #8] - 80038aa: 603b str r3, [r7, #0] - 80038ac: 4613 mov r3, r2 - 80038ae: 71fb strb r3, [r7, #7] - __IO uint32_t count; - uint32_t tmp_timeout; - uint32_t tmp_tickstart; - - /* Adjust Timeout value in case of end of transfer */ - tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); - 80038b0: f7fe fd46 bl 8002340 - 80038b4: 4602 mov r2, r0 - 80038b6: 6abb ldr r3, [r7, #40] ; 0x28 - 80038b8: 1a9b subs r3, r3, r2 - 80038ba: 683a ldr r2, [r7, #0] - 80038bc: 4413 add r3, r2 - 80038be: 61fb str r3, [r7, #28] - tmp_tickstart = HAL_GetTick(); - 80038c0: f7fe fd3e bl 8002340 - 80038c4: 61b8 str r0, [r7, #24] - - /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ - count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); - 80038c6: 4b39 ldr r3, [pc, #228] ; (80039ac ) - 80038c8: 681b ldr r3, [r3, #0] - 80038ca: 015b lsls r3, r3, #5 - 80038cc: 0d1b lsrs r3, r3, #20 - 80038ce: 69fa ldr r2, [r7, #28] - 80038d0: fb02 f303 mul.w r3, r2, r3 - 80038d4: 617b str r3, [r7, #20] - - while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) - 80038d6: e054 b.n 8003982 - { - if (Timeout != HAL_MAX_DELAY) - 80038d8: 683b ldr r3, [r7, #0] - 80038da: f1b3 3fff cmp.w r3, #4294967295 - 80038de: d050 beq.n 8003982 - { - if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) - 80038e0: f7fe fd2e bl 8002340 - 80038e4: 4602 mov r2, r0 - 80038e6: 69bb ldr r3, [r7, #24] - 80038e8: 1ad3 subs r3, r2, r3 - 80038ea: 69fa ldr r2, [r7, #28] - 80038ec: 429a cmp r2, r3 - 80038ee: d902 bls.n 80038f6 - 80038f0: 69fb ldr r3, [r7, #28] - 80038f2: 2b00 cmp r3, #0 - 80038f4: d13d bne.n 8003972 - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - 80038f6: 68fb ldr r3, [r7, #12] - 80038f8: 681b ldr r3, [r3, #0] - 80038fa: 685a ldr r2, [r3, #4] - 80038fc: 68fb ldr r3, [r7, #12] - 80038fe: 681b ldr r3, [r3, #0] - 8003900: f022 02e0 bic.w r2, r2, #224 ; 0xe0 - 8003904: 605a str r2, [r3, #4] - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - 8003906: 68fb ldr r3, [r7, #12] - 8003908: 685b ldr r3, [r3, #4] - 800390a: f5b3 7f82 cmp.w r3, #260 ; 0x104 - 800390e: d111 bne.n 8003934 - 8003910: 68fb ldr r3, [r7, #12] - 8003912: 689b ldr r3, [r3, #8] - 8003914: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8003918: d004 beq.n 8003924 - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - 800391a: 68fb ldr r3, [r7, #12] - 800391c: 689b ldr r3, [r3, #8] - 800391e: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 8003922: d107 bne.n 8003934 - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - 8003924: 68fb ldr r3, [r7, #12] - 8003926: 681b ldr r3, [r3, #0] - 8003928: 681a ldr r2, [r3, #0] - 800392a: 68fb ldr r3, [r7, #12] - 800392c: 681b ldr r3, [r3, #0] - 800392e: f022 0240 bic.w r2, r2, #64 ; 0x40 - 8003932: 601a str r2, [r3, #0] - } - - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - 8003934: 68fb ldr r3, [r7, #12] - 8003936: 6a9b ldr r3, [r3, #40] ; 0x28 - 8003938: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 800393c: d10f bne.n 800395e - { - SPI_RESET_CRC(hspi); - 800393e: 68fb ldr r3, [r7, #12] - 8003940: 681b ldr r3, [r3, #0] - 8003942: 681a ldr r2, [r3, #0] - 8003944: 68fb ldr r3, [r7, #12] - 8003946: 681b ldr r3, [r3, #0] - 8003948: f422 5200 bic.w r2, r2, #8192 ; 0x2000 - 800394c: 601a str r2, [r3, #0] - 800394e: 68fb ldr r3, [r7, #12] - 8003950: 681b ldr r3, [r3, #0] - 8003952: 681a ldr r2, [r3, #0] - 8003954: 68fb ldr r3, [r7, #12] - 8003956: 681b ldr r3, [r3, #0] - 8003958: f442 5200 orr.w r2, r2, #8192 ; 0x2000 - 800395c: 601a str r2, [r3, #0] - } - - hspi->State = HAL_SPI_STATE_READY; - 800395e: 68fb ldr r3, [r7, #12] - 8003960: 2201 movs r2, #1 - 8003962: f883 2051 strb.w r2, [r3, #81] ; 0x51 - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - 8003966: 68fb ldr r3, [r7, #12] - 8003968: 2200 movs r2, #0 - 800396a: f883 2050 strb.w r2, [r3, #80] ; 0x50 - - return HAL_TIMEOUT; - 800396e: 2303 movs r3, #3 - 8003970: e017 b.n 80039a2 - } - /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if (count == 0U) - 8003972: 697b ldr r3, [r7, #20] - 8003974: 2b00 cmp r3, #0 - 8003976: d101 bne.n 800397c - { - tmp_timeout = 0U; - 8003978: 2300 movs r3, #0 - 800397a: 61fb str r3, [r7, #28] - } - count--; - 800397c: 697b ldr r3, [r7, #20] - 800397e: 3b01 subs r3, #1 - 8003980: 617b str r3, [r7, #20] - while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) - 8003982: 68fb ldr r3, [r7, #12] - 8003984: 681b ldr r3, [r3, #0] - 8003986: 689a ldr r2, [r3, #8] - 8003988: 68bb ldr r3, [r7, #8] - 800398a: 4013 ands r3, r2 - 800398c: 68ba ldr r2, [r7, #8] - 800398e: 429a cmp r2, r3 - 8003990: bf0c ite eq - 8003992: 2301 moveq r3, #1 - 8003994: 2300 movne r3, #0 - 8003996: b2db uxtb r3, r3 - 8003998: 461a mov r2, r3 - 800399a: 79fb ldrb r3, [r7, #7] - 800399c: 429a cmp r2, r3 - 800399e: d19b bne.n 80038d8 - } - } - - return HAL_OK; - 80039a0: 2300 movs r3, #0 -} - 80039a2: 4618 mov r0, r3 - 80039a4: 3720 adds r7, #32 - 80039a6: 46bd mov sp, r7 - 80039a8: bd80 pop {r7, pc} - 80039aa: bf00 nop - 80039ac: 2000267c .word 0x2000267c - -080039b0 : - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) -{ - 80039b0: b580 push {r7, lr} - 80039b2: b088 sub sp, #32 - 80039b4: af02 add r7, sp, #8 - 80039b6: 60f8 str r0, [r7, #12] - 80039b8: 60b9 str r1, [r7, #8] - 80039ba: 607a str r2, [r7, #4] - /* Timeout in µs */ - __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); - 80039bc: 4b1b ldr r3, [pc, #108] ; (8003a2c ) - 80039be: 681b ldr r3, [r3, #0] - 80039c0: 4a1b ldr r2, [pc, #108] ; (8003a30 ) - 80039c2: fba2 2303 umull r2, r3, r2, r3 - 80039c6: 0d5b lsrs r3, r3, #21 - 80039c8: f44f 727a mov.w r2, #1000 ; 0x3e8 - 80039cc: fb02 f303 mul.w r3, r2, r3 - 80039d0: 617b str r3, [r7, #20] - /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ - if (hspi->Init.Mode == SPI_MODE_MASTER) - 80039d2: 68fb ldr r3, [r7, #12] - 80039d4: 685b ldr r3, [r3, #4] - 80039d6: f5b3 7f82 cmp.w r3, #260 ; 0x104 - 80039da: d112 bne.n 8003a02 - { - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - 80039dc: 687b ldr r3, [r7, #4] - 80039de: 9300 str r3, [sp, #0] - 80039e0: 68bb ldr r3, [r7, #8] - 80039e2: 2200 movs r2, #0 - 80039e4: 2180 movs r1, #128 ; 0x80 - 80039e6: 68f8 ldr r0, [r7, #12] - 80039e8: f7ff ff5a bl 80038a0 - 80039ec: 4603 mov r3, r0 - 80039ee: 2b00 cmp r3, #0 - 80039f0: d016 beq.n 8003a20 - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - 80039f2: 68fb ldr r3, [r7, #12] - 80039f4: 6d5b ldr r3, [r3, #84] ; 0x54 - 80039f6: f043 0220 orr.w r2, r3, #32 - 80039fa: 68fb ldr r3, [r7, #12] - 80039fc: 655a str r2, [r3, #84] ; 0x54 - return HAL_TIMEOUT; - 80039fe: 2303 movs r3, #3 - 8003a00: e00f b.n 8003a22 - * User have to calculate the timeout value to fit with the time of 1 byte transfer. - * This time is directly link with the SPI clock from Master device. - */ - do - { - if (count == 0U) - 8003a02: 697b ldr r3, [r7, #20] - 8003a04: 2b00 cmp r3, #0 - 8003a06: d00a beq.n 8003a1e - { - break; - } - count--; - 8003a08: 697b ldr r3, [r7, #20] - 8003a0a: 3b01 subs r3, #1 - 8003a0c: 617b str r3, [r7, #20] - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); - 8003a0e: 68fb ldr r3, [r7, #12] - 8003a10: 681b ldr r3, [r3, #0] - 8003a12: 689b ldr r3, [r3, #8] - 8003a14: f003 0380 and.w r3, r3, #128 ; 0x80 - 8003a18: 2b80 cmp r3, #128 ; 0x80 - 8003a1a: d0f2 beq.n 8003a02 - 8003a1c: e000 b.n 8003a20 - break; - 8003a1e: bf00 nop - } - - return HAL_OK; - 8003a20: 2300 movs r3, #0 -} - 8003a22: 4618 mov r0, r3 - 8003a24: 3718 adds r7, #24 - 8003a26: 46bd mov sp, r7 - 8003a28: bd80 pop {r7, pc} - 8003a2a: bf00 nop - 8003a2c: 2000267c .word 0x2000267c - 8003a30: 165e9f81 .word 0x165e9f81 - -08003a34 <__errno>: - 8003a34: 4b01 ldr r3, [pc, #4] ; (8003a3c <__errno+0x8>) - 8003a36: 6818 ldr r0, [r3, #0] - 8003a38: 4770 bx lr - 8003a3a: bf00 nop - 8003a3c: 20002688 .word 0x20002688 - -08003a40 <__libc_init_array>: - 8003a40: b570 push {r4, r5, r6, lr} - 8003a42: 4d0d ldr r5, [pc, #52] ; (8003a78 <__libc_init_array+0x38>) - 8003a44: 4c0d ldr r4, [pc, #52] ; (8003a7c <__libc_init_array+0x3c>) - 8003a46: 1b64 subs r4, r4, r5 - 8003a48: 10a4 asrs r4, r4, #2 - 8003a4a: 2600 movs r6, #0 - 8003a4c: 42a6 cmp r6, r4 - 8003a4e: d109 bne.n 8003a64 <__libc_init_array+0x24> - 8003a50: 4d0b ldr r5, [pc, #44] ; (8003a80 <__libc_init_array+0x40>) - 8003a52: 4c0c ldr r4, [pc, #48] ; (8003a84 <__libc_init_array+0x44>) - 8003a54: f001 f858 bl 8004b08 <_init> - 8003a58: 1b64 subs r4, r4, r5 - 8003a5a: 10a4 asrs r4, r4, #2 - 8003a5c: 2600 movs r6, #0 - 8003a5e: 42a6 cmp r6, r4 - 8003a60: d105 bne.n 8003a6e <__libc_init_array+0x2e> - 8003a62: bd70 pop {r4, r5, r6, pc} - 8003a64: f855 3b04 ldr.w r3, [r5], #4 - 8003a68: 4798 blx r3 - 8003a6a: 3601 adds r6, #1 - 8003a6c: e7ee b.n 8003a4c <__libc_init_array+0xc> - 8003a6e: f855 3b04 ldr.w r3, [r5], #4 - 8003a72: 4798 blx r3 - 8003a74: 3601 adds r6, #1 - 8003a76: e7f2 b.n 8003a5e <__libc_init_array+0x1e> - 8003a78: 08004cd0 .word 0x08004cd0 - 8003a7c: 08004cd0 .word 0x08004cd0 - 8003a80: 08004cd0 .word 0x08004cd0 - 8003a84: 08004cd4 .word 0x08004cd4 - -08003a88 : - 8003a88: 4402 add r2, r0 - 8003a8a: 4603 mov r3, r0 - 8003a8c: 4293 cmp r3, r2 - 8003a8e: d100 bne.n 8003a92 - 8003a90: 4770 bx lr - 8003a92: f803 1b01 strb.w r1, [r3], #1 - 8003a96: e7f9 b.n 8003a8c - -08003a98 : - 8003a98: 4b16 ldr r3, [pc, #88] ; (8003af4 ) - 8003a9a: b510 push {r4, lr} - 8003a9c: 681c ldr r4, [r3, #0] - 8003a9e: 6ba3 ldr r3, [r4, #56] ; 0x38 - 8003aa0: b9b3 cbnz r3, 8003ad0 - 8003aa2: 2018 movs r0, #24 - 8003aa4: f000 f866 bl 8003b74 - 8003aa8: 63a0 str r0, [r4, #56] ; 0x38 - 8003aaa: b928 cbnz r0, 8003ab8 - 8003aac: 4602 mov r2, r0 - 8003aae: 4b12 ldr r3, [pc, #72] ; (8003af8 ) - 8003ab0: 4812 ldr r0, [pc, #72] ; (8003afc ) - 8003ab2: 214e movs r1, #78 ; 0x4e - 8003ab4: f000 f82e bl 8003b14 <__assert_func> - 8003ab8: 4a11 ldr r2, [pc, #68] ; (8003b00 ) - 8003aba: 4b12 ldr r3, [pc, #72] ; (8003b04 ) - 8003abc: e9c0 2300 strd r2, r3, [r0] - 8003ac0: 4b11 ldr r3, [pc, #68] ; (8003b08 ) - 8003ac2: 6083 str r3, [r0, #8] - 8003ac4: 230b movs r3, #11 - 8003ac6: 8183 strh r3, [r0, #12] - 8003ac8: 2201 movs r2, #1 - 8003aca: 2300 movs r3, #0 - 8003acc: e9c0 2304 strd r2, r3, [r0, #16] - 8003ad0: 6ba4 ldr r4, [r4, #56] ; 0x38 - 8003ad2: 4a0e ldr r2, [pc, #56] ; (8003b0c ) - 8003ad4: 6920 ldr r0, [r4, #16] - 8003ad6: 6963 ldr r3, [r4, #20] - 8003ad8: 490d ldr r1, [pc, #52] ; (8003b10 ) - 8003ada: 4342 muls r2, r0 - 8003adc: fb01 2203 mla r2, r1, r3, r2 - 8003ae0: fba0 0101 umull r0, r1, r0, r1 - 8003ae4: 1c43 adds r3, r0, #1 - 8003ae6: eb42 0001 adc.w r0, r2, r1 - 8003aea: e9c4 3004 strd r3, r0, [r4, #16] - 8003aee: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 - 8003af2: bd10 pop {r4, pc} - 8003af4: 20002688 .word 0x20002688 - 8003af8: 08004b84 .word 0x08004b84 - 8003afc: 08004b9b .word 0x08004b9b - 8003b00: abcd330e .word 0xabcd330e - 8003b04: e66d1234 .word 0xe66d1234 - 8003b08: 0005deec .word 0x0005deec - 8003b0c: 5851f42d .word 0x5851f42d - 8003b10: 4c957f2d .word 0x4c957f2d - -08003b14 <__assert_func>: - 8003b14: b51f push {r0, r1, r2, r3, r4, lr} - 8003b16: 4614 mov r4, r2 - 8003b18: 461a mov r2, r3 - 8003b1a: 4b09 ldr r3, [pc, #36] ; (8003b40 <__assert_func+0x2c>) - 8003b1c: 681b ldr r3, [r3, #0] - 8003b1e: 4605 mov r5, r0 - 8003b20: 68d8 ldr r0, [r3, #12] - 8003b22: b14c cbz r4, 8003b38 <__assert_func+0x24> - 8003b24: 4b07 ldr r3, [pc, #28] ; (8003b44 <__assert_func+0x30>) - 8003b26: 9100 str r1, [sp, #0] - 8003b28: e9cd 3401 strd r3, r4, [sp, #4] - 8003b2c: 4906 ldr r1, [pc, #24] ; (8003b48 <__assert_func+0x34>) - 8003b2e: 462b mov r3, r5 - 8003b30: f000 f80e bl 8003b50 - 8003b34: f000 fcc4 bl 80044c0 - 8003b38: 4b04 ldr r3, [pc, #16] ; (8003b4c <__assert_func+0x38>) - 8003b3a: 461c mov r4, r3 - 8003b3c: e7f3 b.n 8003b26 <__assert_func+0x12> - 8003b3e: bf00 nop - 8003b40: 20002688 .word 0x20002688 - 8003b44: 08004bf6 .word 0x08004bf6 - 8003b48: 08004c03 .word 0x08004c03 - 8003b4c: 08004c31 .word 0x08004c31 - -08003b50 : - 8003b50: b40e push {r1, r2, r3} - 8003b52: b503 push {r0, r1, lr} - 8003b54: 4601 mov r1, r0 - 8003b56: ab03 add r3, sp, #12 - 8003b58: 4805 ldr r0, [pc, #20] ; (8003b70 ) - 8003b5a: f853 2b04 ldr.w r2, [r3], #4 - 8003b5e: 6800 ldr r0, [r0, #0] - 8003b60: 9301 str r3, [sp, #4] - 8003b62: f000 f919 bl 8003d98 <_vfiprintf_r> - 8003b66: b002 add sp, #8 - 8003b68: f85d eb04 ldr.w lr, [sp], #4 - 8003b6c: b003 add sp, #12 - 8003b6e: 4770 bx lr - 8003b70: 20002688 .word 0x20002688 - -08003b74 : - 8003b74: 4b02 ldr r3, [pc, #8] ; (8003b80 ) - 8003b76: 4601 mov r1, r0 - 8003b78: 6818 ldr r0, [r3, #0] - 8003b7a: f000 b86f b.w 8003c5c <_malloc_r> - 8003b7e: bf00 nop - 8003b80: 20002688 .word 0x20002688 - -08003b84 <_free_r>: - 8003b84: b537 push {r0, r1, r2, r4, r5, lr} - 8003b86: 2900 cmp r1, #0 - 8003b88: d044 beq.n 8003c14 <_free_r+0x90> - 8003b8a: f851 3c04 ldr.w r3, [r1, #-4] - 8003b8e: 9001 str r0, [sp, #4] - 8003b90: 2b00 cmp r3, #0 - 8003b92: f1a1 0404 sub.w r4, r1, #4 - 8003b96: bfb8 it lt - 8003b98: 18e4 addlt r4, r4, r3 - 8003b9a: f000 feb9 bl 8004910 <__malloc_lock> - 8003b9e: 4a1e ldr r2, [pc, #120] ; (8003c18 <_free_r+0x94>) - 8003ba0: 9801 ldr r0, [sp, #4] - 8003ba2: 6813 ldr r3, [r2, #0] - 8003ba4: b933 cbnz r3, 8003bb4 <_free_r+0x30> - 8003ba6: 6063 str r3, [r4, #4] - 8003ba8: 6014 str r4, [r2, #0] - 8003baa: b003 add sp, #12 - 8003bac: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8003bb0: f000 beb4 b.w 800491c <__malloc_unlock> - 8003bb4: 42a3 cmp r3, r4 - 8003bb6: d908 bls.n 8003bca <_free_r+0x46> - 8003bb8: 6825 ldr r5, [r4, #0] - 8003bba: 1961 adds r1, r4, r5 - 8003bbc: 428b cmp r3, r1 - 8003bbe: bf01 itttt eq - 8003bc0: 6819 ldreq r1, [r3, #0] - 8003bc2: 685b ldreq r3, [r3, #4] - 8003bc4: 1949 addeq r1, r1, r5 - 8003bc6: 6021 streq r1, [r4, #0] - 8003bc8: e7ed b.n 8003ba6 <_free_r+0x22> - 8003bca: 461a mov r2, r3 - 8003bcc: 685b ldr r3, [r3, #4] - 8003bce: b10b cbz r3, 8003bd4 <_free_r+0x50> - 8003bd0: 42a3 cmp r3, r4 - 8003bd2: d9fa bls.n 8003bca <_free_r+0x46> - 8003bd4: 6811 ldr r1, [r2, #0] - 8003bd6: 1855 adds r5, r2, r1 - 8003bd8: 42a5 cmp r5, r4 - 8003bda: d10b bne.n 8003bf4 <_free_r+0x70> - 8003bdc: 6824 ldr r4, [r4, #0] - 8003bde: 4421 add r1, r4 - 8003be0: 1854 adds r4, r2, r1 - 8003be2: 42a3 cmp r3, r4 - 8003be4: 6011 str r1, [r2, #0] - 8003be6: d1e0 bne.n 8003baa <_free_r+0x26> - 8003be8: 681c ldr r4, [r3, #0] - 8003bea: 685b ldr r3, [r3, #4] - 8003bec: 6053 str r3, [r2, #4] - 8003bee: 4421 add r1, r4 - 8003bf0: 6011 str r1, [r2, #0] - 8003bf2: e7da b.n 8003baa <_free_r+0x26> - 8003bf4: d902 bls.n 8003bfc <_free_r+0x78> - 8003bf6: 230c movs r3, #12 - 8003bf8: 6003 str r3, [r0, #0] - 8003bfa: e7d6 b.n 8003baa <_free_r+0x26> - 8003bfc: 6825 ldr r5, [r4, #0] - 8003bfe: 1961 adds r1, r4, r5 - 8003c00: 428b cmp r3, r1 - 8003c02: bf04 itt eq - 8003c04: 6819 ldreq r1, [r3, #0] - 8003c06: 685b ldreq r3, [r3, #4] - 8003c08: 6063 str r3, [r4, #4] - 8003c0a: bf04 itt eq - 8003c0c: 1949 addeq r1, r1, r5 - 8003c0e: 6021 streq r1, [r4, #0] - 8003c10: 6054 str r4, [r2, #4] - 8003c12: e7ca b.n 8003baa <_free_r+0x26> - 8003c14: b003 add sp, #12 - 8003c16: bd30 pop {r4, r5, pc} - 8003c18: 2000279c .word 0x2000279c - -08003c1c : - 8003c1c: b570 push {r4, r5, r6, lr} - 8003c1e: 4e0e ldr r6, [pc, #56] ; (8003c58 ) - 8003c20: 460c mov r4, r1 - 8003c22: 6831 ldr r1, [r6, #0] - 8003c24: 4605 mov r5, r0 - 8003c26: b911 cbnz r1, 8003c2e - 8003c28: f000 fb7a bl 8004320 <_sbrk_r> - 8003c2c: 6030 str r0, [r6, #0] - 8003c2e: 4621 mov r1, r4 - 8003c30: 4628 mov r0, r5 - 8003c32: f000 fb75 bl 8004320 <_sbrk_r> - 8003c36: 1c43 adds r3, r0, #1 - 8003c38: d00a beq.n 8003c50 - 8003c3a: 1cc4 adds r4, r0, #3 - 8003c3c: f024 0403 bic.w r4, r4, #3 - 8003c40: 42a0 cmp r0, r4 - 8003c42: d007 beq.n 8003c54 - 8003c44: 1a21 subs r1, r4, r0 - 8003c46: 4628 mov r0, r5 - 8003c48: f000 fb6a bl 8004320 <_sbrk_r> - 8003c4c: 3001 adds r0, #1 - 8003c4e: d101 bne.n 8003c54 - 8003c50: f04f 34ff mov.w r4, #4294967295 - 8003c54: 4620 mov r0, r4 - 8003c56: bd70 pop {r4, r5, r6, pc} - 8003c58: 200027a0 .word 0x200027a0 - -08003c5c <_malloc_r>: - 8003c5c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8003c60: 1ccd adds r5, r1, #3 - 8003c62: f025 0503 bic.w r5, r5, #3 - 8003c66: 3508 adds r5, #8 - 8003c68: 2d0c cmp r5, #12 - 8003c6a: bf38 it cc - 8003c6c: 250c movcc r5, #12 - 8003c6e: 2d00 cmp r5, #0 - 8003c70: 4607 mov r7, r0 - 8003c72: db01 blt.n 8003c78 <_malloc_r+0x1c> - 8003c74: 42a9 cmp r1, r5 - 8003c76: d905 bls.n 8003c84 <_malloc_r+0x28> - 8003c78: 230c movs r3, #12 - 8003c7a: 603b str r3, [r7, #0] - 8003c7c: 2600 movs r6, #0 - 8003c7e: 4630 mov r0, r6 - 8003c80: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 8003c84: 4e2e ldr r6, [pc, #184] ; (8003d40 <_malloc_r+0xe4>) - 8003c86: f000 fe43 bl 8004910 <__malloc_lock> - 8003c8a: 6833 ldr r3, [r6, #0] - 8003c8c: 461c mov r4, r3 - 8003c8e: bb34 cbnz r4, 8003cde <_malloc_r+0x82> - 8003c90: 4629 mov r1, r5 - 8003c92: 4638 mov r0, r7 - 8003c94: f7ff ffc2 bl 8003c1c - 8003c98: 1c43 adds r3, r0, #1 - 8003c9a: 4604 mov r4, r0 - 8003c9c: d14d bne.n 8003d3a <_malloc_r+0xde> - 8003c9e: 6834 ldr r4, [r6, #0] - 8003ca0: 4626 mov r6, r4 - 8003ca2: 2e00 cmp r6, #0 - 8003ca4: d140 bne.n 8003d28 <_malloc_r+0xcc> - 8003ca6: 6823 ldr r3, [r4, #0] - 8003ca8: 4631 mov r1, r6 - 8003caa: 4638 mov r0, r7 - 8003cac: eb04 0803 add.w r8, r4, r3 - 8003cb0: f000 fb36 bl 8004320 <_sbrk_r> - 8003cb4: 4580 cmp r8, r0 - 8003cb6: d13a bne.n 8003d2e <_malloc_r+0xd2> - 8003cb8: 6821 ldr r1, [r4, #0] - 8003cba: 3503 adds r5, #3 - 8003cbc: 1a6d subs r5, r5, r1 - 8003cbe: f025 0503 bic.w r5, r5, #3 - 8003cc2: 3508 adds r5, #8 - 8003cc4: 2d0c cmp r5, #12 - 8003cc6: bf38 it cc - 8003cc8: 250c movcc r5, #12 - 8003cca: 4629 mov r1, r5 - 8003ccc: 4638 mov r0, r7 - 8003cce: f7ff ffa5 bl 8003c1c - 8003cd2: 3001 adds r0, #1 - 8003cd4: d02b beq.n 8003d2e <_malloc_r+0xd2> - 8003cd6: 6823 ldr r3, [r4, #0] - 8003cd8: 442b add r3, r5 - 8003cda: 6023 str r3, [r4, #0] - 8003cdc: e00e b.n 8003cfc <_malloc_r+0xa0> - 8003cde: 6822 ldr r2, [r4, #0] - 8003ce0: 1b52 subs r2, r2, r5 - 8003ce2: d41e bmi.n 8003d22 <_malloc_r+0xc6> - 8003ce4: 2a0b cmp r2, #11 - 8003ce6: d916 bls.n 8003d16 <_malloc_r+0xba> - 8003ce8: 1961 adds r1, r4, r5 - 8003cea: 42a3 cmp r3, r4 - 8003cec: 6025 str r5, [r4, #0] - 8003cee: bf18 it ne - 8003cf0: 6059 strne r1, [r3, #4] - 8003cf2: 6863 ldr r3, [r4, #4] - 8003cf4: bf08 it eq - 8003cf6: 6031 streq r1, [r6, #0] - 8003cf8: 5162 str r2, [r4, r5] - 8003cfa: 604b str r3, [r1, #4] - 8003cfc: 4638 mov r0, r7 - 8003cfe: f104 060b add.w r6, r4, #11 - 8003d02: f000 fe0b bl 800491c <__malloc_unlock> - 8003d06: f026 0607 bic.w r6, r6, #7 - 8003d0a: 1d23 adds r3, r4, #4 - 8003d0c: 1af2 subs r2, r6, r3 - 8003d0e: d0b6 beq.n 8003c7e <_malloc_r+0x22> - 8003d10: 1b9b subs r3, r3, r6 - 8003d12: 50a3 str r3, [r4, r2] - 8003d14: e7b3 b.n 8003c7e <_malloc_r+0x22> - 8003d16: 6862 ldr r2, [r4, #4] - 8003d18: 42a3 cmp r3, r4 - 8003d1a: bf0c ite eq - 8003d1c: 6032 streq r2, [r6, #0] - 8003d1e: 605a strne r2, [r3, #4] - 8003d20: e7ec b.n 8003cfc <_malloc_r+0xa0> - 8003d22: 4623 mov r3, r4 - 8003d24: 6864 ldr r4, [r4, #4] - 8003d26: e7b2 b.n 8003c8e <_malloc_r+0x32> - 8003d28: 4634 mov r4, r6 - 8003d2a: 6876 ldr r6, [r6, #4] - 8003d2c: e7b9 b.n 8003ca2 <_malloc_r+0x46> - 8003d2e: 230c movs r3, #12 - 8003d30: 603b str r3, [r7, #0] - 8003d32: 4638 mov r0, r7 - 8003d34: f000 fdf2 bl 800491c <__malloc_unlock> - 8003d38: e7a1 b.n 8003c7e <_malloc_r+0x22> - 8003d3a: 6025 str r5, [r4, #0] - 8003d3c: e7de b.n 8003cfc <_malloc_r+0xa0> - 8003d3e: bf00 nop - 8003d40: 2000279c .word 0x2000279c - -08003d44 <__sfputc_r>: - 8003d44: 6893 ldr r3, [r2, #8] - 8003d46: 3b01 subs r3, #1 - 8003d48: 2b00 cmp r3, #0 - 8003d4a: b410 push {r4} - 8003d4c: 6093 str r3, [r2, #8] - 8003d4e: da08 bge.n 8003d62 <__sfputc_r+0x1e> - 8003d50: 6994 ldr r4, [r2, #24] - 8003d52: 42a3 cmp r3, r4 - 8003d54: db01 blt.n 8003d5a <__sfputc_r+0x16> - 8003d56: 290a cmp r1, #10 - 8003d58: d103 bne.n 8003d62 <__sfputc_r+0x1e> - 8003d5a: f85d 4b04 ldr.w r4, [sp], #4 - 8003d5e: f000 baef b.w 8004340 <__swbuf_r> - 8003d62: 6813 ldr r3, [r2, #0] - 8003d64: 1c58 adds r0, r3, #1 - 8003d66: 6010 str r0, [r2, #0] - 8003d68: 7019 strb r1, [r3, #0] - 8003d6a: 4608 mov r0, r1 - 8003d6c: f85d 4b04 ldr.w r4, [sp], #4 - 8003d70: 4770 bx lr - -08003d72 <__sfputs_r>: - 8003d72: b5f8 push {r3, r4, r5, r6, r7, lr} - 8003d74: 4606 mov r6, r0 - 8003d76: 460f mov r7, r1 - 8003d78: 4614 mov r4, r2 - 8003d7a: 18d5 adds r5, r2, r3 - 8003d7c: 42ac cmp r4, r5 - 8003d7e: d101 bne.n 8003d84 <__sfputs_r+0x12> - 8003d80: 2000 movs r0, #0 - 8003d82: e007 b.n 8003d94 <__sfputs_r+0x22> - 8003d84: f814 1b01 ldrb.w r1, [r4], #1 - 8003d88: 463a mov r2, r7 - 8003d8a: 4630 mov r0, r6 - 8003d8c: f7ff ffda bl 8003d44 <__sfputc_r> - 8003d90: 1c43 adds r3, r0, #1 - 8003d92: d1f3 bne.n 8003d7c <__sfputs_r+0xa> - 8003d94: bdf8 pop {r3, r4, r5, r6, r7, pc} - ... - -08003d98 <_vfiprintf_r>: - 8003d98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8003d9c: 460d mov r5, r1 - 8003d9e: b09d sub sp, #116 ; 0x74 - 8003da0: 4614 mov r4, r2 - 8003da2: 4698 mov r8, r3 - 8003da4: 4606 mov r6, r0 - 8003da6: b118 cbz r0, 8003db0 <_vfiprintf_r+0x18> - 8003da8: 6983 ldr r3, [r0, #24] - 8003daa: b90b cbnz r3, 8003db0 <_vfiprintf_r+0x18> - 8003dac: f000 fcaa bl 8004704 <__sinit> - 8003db0: 4b89 ldr r3, [pc, #548] ; (8003fd8 <_vfiprintf_r+0x240>) - 8003db2: 429d cmp r5, r3 - 8003db4: d11b bne.n 8003dee <_vfiprintf_r+0x56> - 8003db6: 6875 ldr r5, [r6, #4] - 8003db8: 6e6b ldr r3, [r5, #100] ; 0x64 - 8003dba: 07d9 lsls r1, r3, #31 - 8003dbc: d405 bmi.n 8003dca <_vfiprintf_r+0x32> - 8003dbe: 89ab ldrh r3, [r5, #12] - 8003dc0: 059a lsls r2, r3, #22 - 8003dc2: d402 bmi.n 8003dca <_vfiprintf_r+0x32> - 8003dc4: 6da8 ldr r0, [r5, #88] ; 0x58 - 8003dc6: f000 fd3b bl 8004840 <__retarget_lock_acquire_recursive> - 8003dca: 89ab ldrh r3, [r5, #12] - 8003dcc: 071b lsls r3, r3, #28 - 8003dce: d501 bpl.n 8003dd4 <_vfiprintf_r+0x3c> - 8003dd0: 692b ldr r3, [r5, #16] - 8003dd2: b9eb cbnz r3, 8003e10 <_vfiprintf_r+0x78> - 8003dd4: 4629 mov r1, r5 - 8003dd6: 4630 mov r0, r6 - 8003dd8: f000 fb04 bl 80043e4 <__swsetup_r> - 8003ddc: b1c0 cbz r0, 8003e10 <_vfiprintf_r+0x78> - 8003dde: 6e6b ldr r3, [r5, #100] ; 0x64 - 8003de0: 07dc lsls r4, r3, #31 - 8003de2: d50e bpl.n 8003e02 <_vfiprintf_r+0x6a> - 8003de4: f04f 30ff mov.w r0, #4294967295 - 8003de8: b01d add sp, #116 ; 0x74 - 8003dea: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8003dee: 4b7b ldr r3, [pc, #492] ; (8003fdc <_vfiprintf_r+0x244>) - 8003df0: 429d cmp r5, r3 - 8003df2: d101 bne.n 8003df8 <_vfiprintf_r+0x60> - 8003df4: 68b5 ldr r5, [r6, #8] - 8003df6: e7df b.n 8003db8 <_vfiprintf_r+0x20> - 8003df8: 4b79 ldr r3, [pc, #484] ; (8003fe0 <_vfiprintf_r+0x248>) - 8003dfa: 429d cmp r5, r3 - 8003dfc: bf08 it eq - 8003dfe: 68f5 ldreq r5, [r6, #12] - 8003e00: e7da b.n 8003db8 <_vfiprintf_r+0x20> - 8003e02: 89ab ldrh r3, [r5, #12] - 8003e04: 0598 lsls r0, r3, #22 - 8003e06: d4ed bmi.n 8003de4 <_vfiprintf_r+0x4c> - 8003e08: 6da8 ldr r0, [r5, #88] ; 0x58 - 8003e0a: f000 fd1a bl 8004842 <__retarget_lock_release_recursive> - 8003e0e: e7e9 b.n 8003de4 <_vfiprintf_r+0x4c> - 8003e10: 2300 movs r3, #0 - 8003e12: 9309 str r3, [sp, #36] ; 0x24 - 8003e14: 2320 movs r3, #32 - 8003e16: f88d 3029 strb.w r3, [sp, #41] ; 0x29 - 8003e1a: f8cd 800c str.w r8, [sp, #12] - 8003e1e: 2330 movs r3, #48 ; 0x30 - 8003e20: f8df 81c0 ldr.w r8, [pc, #448] ; 8003fe4 <_vfiprintf_r+0x24c> - 8003e24: f88d 302a strb.w r3, [sp, #42] ; 0x2a - 8003e28: f04f 0901 mov.w r9, #1 - 8003e2c: 4623 mov r3, r4 - 8003e2e: 469a mov sl, r3 - 8003e30: f813 2b01 ldrb.w r2, [r3], #1 - 8003e34: b10a cbz r2, 8003e3a <_vfiprintf_r+0xa2> - 8003e36: 2a25 cmp r2, #37 ; 0x25 - 8003e38: d1f9 bne.n 8003e2e <_vfiprintf_r+0x96> - 8003e3a: ebba 0b04 subs.w fp, sl, r4 - 8003e3e: d00b beq.n 8003e58 <_vfiprintf_r+0xc0> - 8003e40: 465b mov r3, fp - 8003e42: 4622 mov r2, r4 - 8003e44: 4629 mov r1, r5 - 8003e46: 4630 mov r0, r6 - 8003e48: f7ff ff93 bl 8003d72 <__sfputs_r> - 8003e4c: 3001 adds r0, #1 - 8003e4e: f000 80aa beq.w 8003fa6 <_vfiprintf_r+0x20e> - 8003e52: 9a09 ldr r2, [sp, #36] ; 0x24 - 8003e54: 445a add r2, fp - 8003e56: 9209 str r2, [sp, #36] ; 0x24 - 8003e58: f89a 3000 ldrb.w r3, [sl] - 8003e5c: 2b00 cmp r3, #0 - 8003e5e: f000 80a2 beq.w 8003fa6 <_vfiprintf_r+0x20e> - 8003e62: 2300 movs r3, #0 - 8003e64: f04f 32ff mov.w r2, #4294967295 - 8003e68: e9cd 2305 strd r2, r3, [sp, #20] - 8003e6c: f10a 0a01 add.w sl, sl, #1 - 8003e70: 9304 str r3, [sp, #16] - 8003e72: 9307 str r3, [sp, #28] - 8003e74: f88d 3053 strb.w r3, [sp, #83] ; 0x53 - 8003e78: 931a str r3, [sp, #104] ; 0x68 - 8003e7a: 4654 mov r4, sl - 8003e7c: 2205 movs r2, #5 - 8003e7e: f814 1b01 ldrb.w r1, [r4], #1 - 8003e82: 4858 ldr r0, [pc, #352] ; (8003fe4 <_vfiprintf_r+0x24c>) - 8003e84: f7fc f9a4 bl 80001d0 - 8003e88: 9a04 ldr r2, [sp, #16] - 8003e8a: b9d8 cbnz r0, 8003ec4 <_vfiprintf_r+0x12c> - 8003e8c: 06d1 lsls r1, r2, #27 - 8003e8e: bf44 itt mi - 8003e90: 2320 movmi r3, #32 - 8003e92: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 8003e96: 0713 lsls r3, r2, #28 - 8003e98: bf44 itt mi - 8003e9a: 232b movmi r3, #43 ; 0x2b - 8003e9c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 8003ea0: f89a 3000 ldrb.w r3, [sl] - 8003ea4: 2b2a cmp r3, #42 ; 0x2a - 8003ea6: d015 beq.n 8003ed4 <_vfiprintf_r+0x13c> - 8003ea8: 9a07 ldr r2, [sp, #28] - 8003eaa: 4654 mov r4, sl - 8003eac: 2000 movs r0, #0 - 8003eae: f04f 0c0a mov.w ip, #10 - 8003eb2: 4621 mov r1, r4 - 8003eb4: f811 3b01 ldrb.w r3, [r1], #1 - 8003eb8: 3b30 subs r3, #48 ; 0x30 - 8003eba: 2b09 cmp r3, #9 - 8003ebc: d94e bls.n 8003f5c <_vfiprintf_r+0x1c4> - 8003ebe: b1b0 cbz r0, 8003eee <_vfiprintf_r+0x156> - 8003ec0: 9207 str r2, [sp, #28] - 8003ec2: e014 b.n 8003eee <_vfiprintf_r+0x156> - 8003ec4: eba0 0308 sub.w r3, r0, r8 - 8003ec8: fa09 f303 lsl.w r3, r9, r3 - 8003ecc: 4313 orrs r3, r2 - 8003ece: 9304 str r3, [sp, #16] - 8003ed0: 46a2 mov sl, r4 - 8003ed2: e7d2 b.n 8003e7a <_vfiprintf_r+0xe2> - 8003ed4: 9b03 ldr r3, [sp, #12] - 8003ed6: 1d19 adds r1, r3, #4 - 8003ed8: 681b ldr r3, [r3, #0] - 8003eda: 9103 str r1, [sp, #12] - 8003edc: 2b00 cmp r3, #0 - 8003ede: bfbb ittet lt - 8003ee0: 425b neglt r3, r3 - 8003ee2: f042 0202 orrlt.w r2, r2, #2 - 8003ee6: 9307 strge r3, [sp, #28] - 8003ee8: 9307 strlt r3, [sp, #28] - 8003eea: bfb8 it lt - 8003eec: 9204 strlt r2, [sp, #16] - 8003eee: 7823 ldrb r3, [r4, #0] - 8003ef0: 2b2e cmp r3, #46 ; 0x2e - 8003ef2: d10c bne.n 8003f0e <_vfiprintf_r+0x176> - 8003ef4: 7863 ldrb r3, [r4, #1] - 8003ef6: 2b2a cmp r3, #42 ; 0x2a - 8003ef8: d135 bne.n 8003f66 <_vfiprintf_r+0x1ce> - 8003efa: 9b03 ldr r3, [sp, #12] - 8003efc: 1d1a adds r2, r3, #4 - 8003efe: 681b ldr r3, [r3, #0] - 8003f00: 9203 str r2, [sp, #12] - 8003f02: 2b00 cmp r3, #0 - 8003f04: bfb8 it lt - 8003f06: f04f 33ff movlt.w r3, #4294967295 - 8003f0a: 3402 adds r4, #2 - 8003f0c: 9305 str r3, [sp, #20] - 8003f0e: f8df a0e4 ldr.w sl, [pc, #228] ; 8003ff4 <_vfiprintf_r+0x25c> - 8003f12: 7821 ldrb r1, [r4, #0] - 8003f14: 2203 movs r2, #3 - 8003f16: 4650 mov r0, sl - 8003f18: f7fc f95a bl 80001d0 - 8003f1c: b140 cbz r0, 8003f30 <_vfiprintf_r+0x198> - 8003f1e: 2340 movs r3, #64 ; 0x40 - 8003f20: eba0 000a sub.w r0, r0, sl - 8003f24: fa03 f000 lsl.w r0, r3, r0 - 8003f28: 9b04 ldr r3, [sp, #16] - 8003f2a: 4303 orrs r3, r0 - 8003f2c: 3401 adds r4, #1 - 8003f2e: 9304 str r3, [sp, #16] - 8003f30: f814 1b01 ldrb.w r1, [r4], #1 - 8003f34: 482c ldr r0, [pc, #176] ; (8003fe8 <_vfiprintf_r+0x250>) - 8003f36: f88d 1028 strb.w r1, [sp, #40] ; 0x28 - 8003f3a: 2206 movs r2, #6 - 8003f3c: f7fc f948 bl 80001d0 - 8003f40: 2800 cmp r0, #0 - 8003f42: d03f beq.n 8003fc4 <_vfiprintf_r+0x22c> - 8003f44: 4b29 ldr r3, [pc, #164] ; (8003fec <_vfiprintf_r+0x254>) - 8003f46: bb1b cbnz r3, 8003f90 <_vfiprintf_r+0x1f8> - 8003f48: 9b03 ldr r3, [sp, #12] - 8003f4a: 3307 adds r3, #7 - 8003f4c: f023 0307 bic.w r3, r3, #7 - 8003f50: 3308 adds r3, #8 - 8003f52: 9303 str r3, [sp, #12] - 8003f54: 9b09 ldr r3, [sp, #36] ; 0x24 - 8003f56: 443b add r3, r7 - 8003f58: 9309 str r3, [sp, #36] ; 0x24 - 8003f5a: e767 b.n 8003e2c <_vfiprintf_r+0x94> - 8003f5c: fb0c 3202 mla r2, ip, r2, r3 - 8003f60: 460c mov r4, r1 - 8003f62: 2001 movs r0, #1 - 8003f64: e7a5 b.n 8003eb2 <_vfiprintf_r+0x11a> - 8003f66: 2300 movs r3, #0 - 8003f68: 3401 adds r4, #1 - 8003f6a: 9305 str r3, [sp, #20] - 8003f6c: 4619 mov r1, r3 - 8003f6e: f04f 0c0a mov.w ip, #10 - 8003f72: 4620 mov r0, r4 - 8003f74: f810 2b01 ldrb.w r2, [r0], #1 - 8003f78: 3a30 subs r2, #48 ; 0x30 - 8003f7a: 2a09 cmp r2, #9 - 8003f7c: d903 bls.n 8003f86 <_vfiprintf_r+0x1ee> - 8003f7e: 2b00 cmp r3, #0 - 8003f80: d0c5 beq.n 8003f0e <_vfiprintf_r+0x176> - 8003f82: 9105 str r1, [sp, #20] - 8003f84: e7c3 b.n 8003f0e <_vfiprintf_r+0x176> - 8003f86: fb0c 2101 mla r1, ip, r1, r2 - 8003f8a: 4604 mov r4, r0 - 8003f8c: 2301 movs r3, #1 - 8003f8e: e7f0 b.n 8003f72 <_vfiprintf_r+0x1da> - 8003f90: ab03 add r3, sp, #12 - 8003f92: 9300 str r3, [sp, #0] - 8003f94: 462a mov r2, r5 - 8003f96: 4b16 ldr r3, [pc, #88] ; (8003ff0 <_vfiprintf_r+0x258>) - 8003f98: a904 add r1, sp, #16 - 8003f9a: 4630 mov r0, r6 - 8003f9c: f3af 8000 nop.w - 8003fa0: 4607 mov r7, r0 - 8003fa2: 1c78 adds r0, r7, #1 - 8003fa4: d1d6 bne.n 8003f54 <_vfiprintf_r+0x1bc> - 8003fa6: 6e6b ldr r3, [r5, #100] ; 0x64 - 8003fa8: 07d9 lsls r1, r3, #31 - 8003faa: d405 bmi.n 8003fb8 <_vfiprintf_r+0x220> - 8003fac: 89ab ldrh r3, [r5, #12] - 8003fae: 059a lsls r2, r3, #22 - 8003fb0: d402 bmi.n 8003fb8 <_vfiprintf_r+0x220> - 8003fb2: 6da8 ldr r0, [r5, #88] ; 0x58 - 8003fb4: f000 fc45 bl 8004842 <__retarget_lock_release_recursive> - 8003fb8: 89ab ldrh r3, [r5, #12] - 8003fba: 065b lsls r3, r3, #25 - 8003fbc: f53f af12 bmi.w 8003de4 <_vfiprintf_r+0x4c> - 8003fc0: 9809 ldr r0, [sp, #36] ; 0x24 - 8003fc2: e711 b.n 8003de8 <_vfiprintf_r+0x50> - 8003fc4: ab03 add r3, sp, #12 - 8003fc6: 9300 str r3, [sp, #0] - 8003fc8: 462a mov r2, r5 - 8003fca: 4b09 ldr r3, [pc, #36] ; (8003ff0 <_vfiprintf_r+0x258>) - 8003fcc: a904 add r1, sp, #16 - 8003fce: 4630 mov r0, r6 - 8003fd0: f000 f880 bl 80040d4 <_printf_i> - 8003fd4: e7e4 b.n 8003fa0 <_vfiprintf_r+0x208> - 8003fd6: bf00 nop - 8003fd8: 08004c88 .word 0x08004c88 - 8003fdc: 08004ca8 .word 0x08004ca8 - 8003fe0: 08004c68 .word 0x08004c68 - 8003fe4: 08004c32 .word 0x08004c32 - 8003fe8: 08004c3c .word 0x08004c3c - 8003fec: 00000000 .word 0x00000000 - 8003ff0: 08003d73 .word 0x08003d73 - 8003ff4: 08004c38 .word 0x08004c38 - -08003ff8 <_printf_common>: - 8003ff8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 8003ffc: 4616 mov r6, r2 - 8003ffe: 4699 mov r9, r3 - 8004000: 688a ldr r2, [r1, #8] - 8004002: 690b ldr r3, [r1, #16] - 8004004: f8dd 8020 ldr.w r8, [sp, #32] - 8004008: 4293 cmp r3, r2 - 800400a: bfb8 it lt - 800400c: 4613 movlt r3, r2 - 800400e: 6033 str r3, [r6, #0] - 8004010: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 - 8004014: 4607 mov r7, r0 - 8004016: 460c mov r4, r1 - 8004018: b10a cbz r2, 800401e <_printf_common+0x26> - 800401a: 3301 adds r3, #1 - 800401c: 6033 str r3, [r6, #0] - 800401e: 6823 ldr r3, [r4, #0] - 8004020: 0699 lsls r1, r3, #26 - 8004022: bf42 ittt mi - 8004024: 6833 ldrmi r3, [r6, #0] - 8004026: 3302 addmi r3, #2 - 8004028: 6033 strmi r3, [r6, #0] - 800402a: 6825 ldr r5, [r4, #0] - 800402c: f015 0506 ands.w r5, r5, #6 - 8004030: d106 bne.n 8004040 <_printf_common+0x48> - 8004032: f104 0a19 add.w sl, r4, #25 - 8004036: 68e3 ldr r3, [r4, #12] - 8004038: 6832 ldr r2, [r6, #0] - 800403a: 1a9b subs r3, r3, r2 - 800403c: 42ab cmp r3, r5 - 800403e: dc26 bgt.n 800408e <_printf_common+0x96> - 8004040: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 - 8004044: 1e13 subs r3, r2, #0 - 8004046: 6822 ldr r2, [r4, #0] - 8004048: bf18 it ne - 800404a: 2301 movne r3, #1 - 800404c: 0692 lsls r2, r2, #26 - 800404e: d42b bmi.n 80040a8 <_printf_common+0xb0> - 8004050: f104 0243 add.w r2, r4, #67 ; 0x43 - 8004054: 4649 mov r1, r9 - 8004056: 4638 mov r0, r7 - 8004058: 47c0 blx r8 - 800405a: 3001 adds r0, #1 - 800405c: d01e beq.n 800409c <_printf_common+0xa4> - 800405e: 6823 ldr r3, [r4, #0] - 8004060: 68e5 ldr r5, [r4, #12] - 8004062: 6832 ldr r2, [r6, #0] - 8004064: f003 0306 and.w r3, r3, #6 - 8004068: 2b04 cmp r3, #4 - 800406a: bf08 it eq - 800406c: 1aad subeq r5, r5, r2 - 800406e: 68a3 ldr r3, [r4, #8] - 8004070: 6922 ldr r2, [r4, #16] - 8004072: bf0c ite eq - 8004074: ea25 75e5 biceq.w r5, r5, r5, asr #31 - 8004078: 2500 movne r5, #0 - 800407a: 4293 cmp r3, r2 - 800407c: bfc4 itt gt - 800407e: 1a9b subgt r3, r3, r2 - 8004080: 18ed addgt r5, r5, r3 - 8004082: 2600 movs r6, #0 - 8004084: 341a adds r4, #26 - 8004086: 42b5 cmp r5, r6 - 8004088: d11a bne.n 80040c0 <_printf_common+0xc8> - 800408a: 2000 movs r0, #0 - 800408c: e008 b.n 80040a0 <_printf_common+0xa8> - 800408e: 2301 movs r3, #1 - 8004090: 4652 mov r2, sl - 8004092: 4649 mov r1, r9 - 8004094: 4638 mov r0, r7 - 8004096: 47c0 blx r8 - 8004098: 3001 adds r0, #1 - 800409a: d103 bne.n 80040a4 <_printf_common+0xac> - 800409c: f04f 30ff mov.w r0, #4294967295 - 80040a0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80040a4: 3501 adds r5, #1 - 80040a6: e7c6 b.n 8004036 <_printf_common+0x3e> - 80040a8: 18e1 adds r1, r4, r3 - 80040aa: 1c5a adds r2, r3, #1 - 80040ac: 2030 movs r0, #48 ; 0x30 - 80040ae: f881 0043 strb.w r0, [r1, #67] ; 0x43 - 80040b2: 4422 add r2, r4 - 80040b4: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 - 80040b8: f882 1043 strb.w r1, [r2, #67] ; 0x43 - 80040bc: 3302 adds r3, #2 - 80040be: e7c7 b.n 8004050 <_printf_common+0x58> - 80040c0: 2301 movs r3, #1 - 80040c2: 4622 mov r2, r4 - 80040c4: 4649 mov r1, r9 - 80040c6: 4638 mov r0, r7 - 80040c8: 47c0 blx r8 - 80040ca: 3001 adds r0, #1 - 80040cc: d0e6 beq.n 800409c <_printf_common+0xa4> - 80040ce: 3601 adds r6, #1 - 80040d0: e7d9 b.n 8004086 <_printf_common+0x8e> - ... - -080040d4 <_printf_i>: - 80040d4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 80040d8: 7e0f ldrb r7, [r1, #24] - 80040da: 9d0c ldr r5, [sp, #48] ; 0x30 - 80040dc: 2f78 cmp r7, #120 ; 0x78 - 80040de: 4691 mov r9, r2 - 80040e0: 4680 mov r8, r0 - 80040e2: 460c mov r4, r1 - 80040e4: 469a mov sl, r3 - 80040e6: f101 0243 add.w r2, r1, #67 ; 0x43 - 80040ea: d807 bhi.n 80040fc <_printf_i+0x28> - 80040ec: 2f62 cmp r7, #98 ; 0x62 - 80040ee: d80a bhi.n 8004106 <_printf_i+0x32> - 80040f0: 2f00 cmp r7, #0 - 80040f2: f000 80d8 beq.w 80042a6 <_printf_i+0x1d2> - 80040f6: 2f58 cmp r7, #88 ; 0x58 - 80040f8: f000 80a3 beq.w 8004242 <_printf_i+0x16e> - 80040fc: f104 0542 add.w r5, r4, #66 ; 0x42 - 8004100: f884 7042 strb.w r7, [r4, #66] ; 0x42 - 8004104: e03a b.n 800417c <_printf_i+0xa8> - 8004106: f1a7 0363 sub.w r3, r7, #99 ; 0x63 - 800410a: 2b15 cmp r3, #21 - 800410c: d8f6 bhi.n 80040fc <_printf_i+0x28> - 800410e: a101 add r1, pc, #4 ; (adr r1, 8004114 <_printf_i+0x40>) - 8004110: f851 f023 ldr.w pc, [r1, r3, lsl #2] - 8004114: 0800416d .word 0x0800416d - 8004118: 08004181 .word 0x08004181 - 800411c: 080040fd .word 0x080040fd - 8004120: 080040fd .word 0x080040fd - 8004124: 080040fd .word 0x080040fd - 8004128: 080040fd .word 0x080040fd - 800412c: 08004181 .word 0x08004181 - 8004130: 080040fd .word 0x080040fd - 8004134: 080040fd .word 0x080040fd - 8004138: 080040fd .word 0x080040fd - 800413c: 080040fd .word 0x080040fd - 8004140: 0800428d .word 0x0800428d - 8004144: 080041b1 .word 0x080041b1 - 8004148: 0800426f .word 0x0800426f - 800414c: 080040fd .word 0x080040fd - 8004150: 080040fd .word 0x080040fd - 8004154: 080042af .word 0x080042af - 8004158: 080040fd .word 0x080040fd - 800415c: 080041b1 .word 0x080041b1 - 8004160: 080040fd .word 0x080040fd - 8004164: 080040fd .word 0x080040fd - 8004168: 08004277 .word 0x08004277 - 800416c: 682b ldr r3, [r5, #0] - 800416e: 1d1a adds r2, r3, #4 - 8004170: 681b ldr r3, [r3, #0] - 8004172: 602a str r2, [r5, #0] - 8004174: f104 0542 add.w r5, r4, #66 ; 0x42 - 8004178: f884 3042 strb.w r3, [r4, #66] ; 0x42 - 800417c: 2301 movs r3, #1 - 800417e: e0a3 b.n 80042c8 <_printf_i+0x1f4> - 8004180: 6820 ldr r0, [r4, #0] - 8004182: 6829 ldr r1, [r5, #0] - 8004184: 0606 lsls r6, r0, #24 - 8004186: f101 0304 add.w r3, r1, #4 - 800418a: d50a bpl.n 80041a2 <_printf_i+0xce> - 800418c: 680e ldr r6, [r1, #0] - 800418e: 602b str r3, [r5, #0] - 8004190: 2e00 cmp r6, #0 - 8004192: da03 bge.n 800419c <_printf_i+0xc8> - 8004194: 232d movs r3, #45 ; 0x2d - 8004196: 4276 negs r6, r6 - 8004198: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 800419c: 485e ldr r0, [pc, #376] ; (8004318 <_printf_i+0x244>) - 800419e: 230a movs r3, #10 - 80041a0: e019 b.n 80041d6 <_printf_i+0x102> - 80041a2: 680e ldr r6, [r1, #0] - 80041a4: 602b str r3, [r5, #0] - 80041a6: f010 0f40 tst.w r0, #64 ; 0x40 - 80041aa: bf18 it ne - 80041ac: b236 sxthne r6, r6 - 80041ae: e7ef b.n 8004190 <_printf_i+0xbc> - 80041b0: 682b ldr r3, [r5, #0] - 80041b2: 6820 ldr r0, [r4, #0] - 80041b4: 1d19 adds r1, r3, #4 - 80041b6: 6029 str r1, [r5, #0] - 80041b8: 0601 lsls r1, r0, #24 - 80041ba: d501 bpl.n 80041c0 <_printf_i+0xec> - 80041bc: 681e ldr r6, [r3, #0] - 80041be: e002 b.n 80041c6 <_printf_i+0xf2> - 80041c0: 0646 lsls r6, r0, #25 - 80041c2: d5fb bpl.n 80041bc <_printf_i+0xe8> - 80041c4: 881e ldrh r6, [r3, #0] - 80041c6: 4854 ldr r0, [pc, #336] ; (8004318 <_printf_i+0x244>) - 80041c8: 2f6f cmp r7, #111 ; 0x6f - 80041ca: bf0c ite eq - 80041cc: 2308 moveq r3, #8 - 80041ce: 230a movne r3, #10 - 80041d0: 2100 movs r1, #0 - 80041d2: f884 1043 strb.w r1, [r4, #67] ; 0x43 - 80041d6: 6865 ldr r5, [r4, #4] - 80041d8: 60a5 str r5, [r4, #8] - 80041da: 2d00 cmp r5, #0 - 80041dc: bfa2 ittt ge - 80041de: 6821 ldrge r1, [r4, #0] - 80041e0: f021 0104 bicge.w r1, r1, #4 - 80041e4: 6021 strge r1, [r4, #0] - 80041e6: b90e cbnz r6, 80041ec <_printf_i+0x118> - 80041e8: 2d00 cmp r5, #0 - 80041ea: d04d beq.n 8004288 <_printf_i+0x1b4> - 80041ec: 4615 mov r5, r2 - 80041ee: fbb6 f1f3 udiv r1, r6, r3 - 80041f2: fb03 6711 mls r7, r3, r1, r6 - 80041f6: 5dc7 ldrb r7, [r0, r7] - 80041f8: f805 7d01 strb.w r7, [r5, #-1]! - 80041fc: 4637 mov r7, r6 - 80041fe: 42bb cmp r3, r7 - 8004200: 460e mov r6, r1 - 8004202: d9f4 bls.n 80041ee <_printf_i+0x11a> - 8004204: 2b08 cmp r3, #8 - 8004206: d10b bne.n 8004220 <_printf_i+0x14c> - 8004208: 6823 ldr r3, [r4, #0] - 800420a: 07de lsls r6, r3, #31 - 800420c: d508 bpl.n 8004220 <_printf_i+0x14c> - 800420e: 6923 ldr r3, [r4, #16] - 8004210: 6861 ldr r1, [r4, #4] - 8004212: 4299 cmp r1, r3 - 8004214: bfde ittt le - 8004216: 2330 movle r3, #48 ; 0x30 - 8004218: f805 3c01 strble.w r3, [r5, #-1] - 800421c: f105 35ff addle.w r5, r5, #4294967295 - 8004220: 1b52 subs r2, r2, r5 - 8004222: 6122 str r2, [r4, #16] - 8004224: f8cd a000 str.w sl, [sp] - 8004228: 464b mov r3, r9 - 800422a: aa03 add r2, sp, #12 - 800422c: 4621 mov r1, r4 - 800422e: 4640 mov r0, r8 - 8004230: f7ff fee2 bl 8003ff8 <_printf_common> - 8004234: 3001 adds r0, #1 - 8004236: d14c bne.n 80042d2 <_printf_i+0x1fe> - 8004238: f04f 30ff mov.w r0, #4294967295 - 800423c: b004 add sp, #16 - 800423e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8004242: 4835 ldr r0, [pc, #212] ; (8004318 <_printf_i+0x244>) - 8004244: f881 7045 strb.w r7, [r1, #69] ; 0x45 - 8004248: 6829 ldr r1, [r5, #0] - 800424a: 6823 ldr r3, [r4, #0] - 800424c: f851 6b04 ldr.w r6, [r1], #4 - 8004250: 6029 str r1, [r5, #0] - 8004252: 061d lsls r5, r3, #24 - 8004254: d514 bpl.n 8004280 <_printf_i+0x1ac> - 8004256: 07df lsls r7, r3, #31 - 8004258: bf44 itt mi - 800425a: f043 0320 orrmi.w r3, r3, #32 - 800425e: 6023 strmi r3, [r4, #0] - 8004260: b91e cbnz r6, 800426a <_printf_i+0x196> - 8004262: 6823 ldr r3, [r4, #0] - 8004264: f023 0320 bic.w r3, r3, #32 - 8004268: 6023 str r3, [r4, #0] - 800426a: 2310 movs r3, #16 - 800426c: e7b0 b.n 80041d0 <_printf_i+0xfc> - 800426e: 6823 ldr r3, [r4, #0] - 8004270: f043 0320 orr.w r3, r3, #32 - 8004274: 6023 str r3, [r4, #0] - 8004276: 2378 movs r3, #120 ; 0x78 - 8004278: 4828 ldr r0, [pc, #160] ; (800431c <_printf_i+0x248>) - 800427a: f884 3045 strb.w r3, [r4, #69] ; 0x45 - 800427e: e7e3 b.n 8004248 <_printf_i+0x174> - 8004280: 0659 lsls r1, r3, #25 - 8004282: bf48 it mi - 8004284: b2b6 uxthmi r6, r6 - 8004286: e7e6 b.n 8004256 <_printf_i+0x182> - 8004288: 4615 mov r5, r2 - 800428a: e7bb b.n 8004204 <_printf_i+0x130> - 800428c: 682b ldr r3, [r5, #0] - 800428e: 6826 ldr r6, [r4, #0] - 8004290: 6961 ldr r1, [r4, #20] - 8004292: 1d18 adds r0, r3, #4 - 8004294: 6028 str r0, [r5, #0] - 8004296: 0635 lsls r5, r6, #24 - 8004298: 681b ldr r3, [r3, #0] - 800429a: d501 bpl.n 80042a0 <_printf_i+0x1cc> - 800429c: 6019 str r1, [r3, #0] - 800429e: e002 b.n 80042a6 <_printf_i+0x1d2> - 80042a0: 0670 lsls r0, r6, #25 - 80042a2: d5fb bpl.n 800429c <_printf_i+0x1c8> - 80042a4: 8019 strh r1, [r3, #0] - 80042a6: 2300 movs r3, #0 - 80042a8: 6123 str r3, [r4, #16] - 80042aa: 4615 mov r5, r2 - 80042ac: e7ba b.n 8004224 <_printf_i+0x150> - 80042ae: 682b ldr r3, [r5, #0] - 80042b0: 1d1a adds r2, r3, #4 - 80042b2: 602a str r2, [r5, #0] - 80042b4: 681d ldr r5, [r3, #0] - 80042b6: 6862 ldr r2, [r4, #4] - 80042b8: 2100 movs r1, #0 - 80042ba: 4628 mov r0, r5 - 80042bc: f7fb ff88 bl 80001d0 - 80042c0: b108 cbz r0, 80042c6 <_printf_i+0x1f2> - 80042c2: 1b40 subs r0, r0, r5 - 80042c4: 6060 str r0, [r4, #4] - 80042c6: 6863 ldr r3, [r4, #4] - 80042c8: 6123 str r3, [r4, #16] - 80042ca: 2300 movs r3, #0 - 80042cc: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 80042d0: e7a8 b.n 8004224 <_printf_i+0x150> - 80042d2: 6923 ldr r3, [r4, #16] - 80042d4: 462a mov r2, r5 - 80042d6: 4649 mov r1, r9 - 80042d8: 4640 mov r0, r8 - 80042da: 47d0 blx sl - 80042dc: 3001 adds r0, #1 - 80042de: d0ab beq.n 8004238 <_printf_i+0x164> - 80042e0: 6823 ldr r3, [r4, #0] - 80042e2: 079b lsls r3, r3, #30 - 80042e4: d413 bmi.n 800430e <_printf_i+0x23a> - 80042e6: 68e0 ldr r0, [r4, #12] - 80042e8: 9b03 ldr r3, [sp, #12] - 80042ea: 4298 cmp r0, r3 - 80042ec: bfb8 it lt - 80042ee: 4618 movlt r0, r3 - 80042f0: e7a4 b.n 800423c <_printf_i+0x168> - 80042f2: 2301 movs r3, #1 - 80042f4: 4632 mov r2, r6 - 80042f6: 4649 mov r1, r9 - 80042f8: 4640 mov r0, r8 - 80042fa: 47d0 blx sl - 80042fc: 3001 adds r0, #1 - 80042fe: d09b beq.n 8004238 <_printf_i+0x164> - 8004300: 3501 adds r5, #1 - 8004302: 68e3 ldr r3, [r4, #12] - 8004304: 9903 ldr r1, [sp, #12] - 8004306: 1a5b subs r3, r3, r1 - 8004308: 42ab cmp r3, r5 - 800430a: dcf2 bgt.n 80042f2 <_printf_i+0x21e> - 800430c: e7eb b.n 80042e6 <_printf_i+0x212> - 800430e: 2500 movs r5, #0 - 8004310: f104 0619 add.w r6, r4, #25 - 8004314: e7f5 b.n 8004302 <_printf_i+0x22e> - 8004316: bf00 nop - 8004318: 08004c43 .word 0x08004c43 - 800431c: 08004c54 .word 0x08004c54 - -08004320 <_sbrk_r>: - 8004320: b538 push {r3, r4, r5, lr} - 8004322: 4d06 ldr r5, [pc, #24] ; (800433c <_sbrk_r+0x1c>) - 8004324: 2300 movs r3, #0 - 8004326: 4604 mov r4, r0 - 8004328: 4608 mov r0, r1 - 800432a: 602b str r3, [r5, #0] - 800432c: f7fd fe7c bl 8002028 <_sbrk> - 8004330: 1c43 adds r3, r0, #1 - 8004332: d102 bne.n 800433a <_sbrk_r+0x1a> - 8004334: 682b ldr r3, [r5, #0] - 8004336: b103 cbz r3, 800433a <_sbrk_r+0x1a> - 8004338: 6023 str r3, [r4, #0] - 800433a: bd38 pop {r3, r4, r5, pc} - 800433c: 200027a8 .word 0x200027a8 - -08004340 <__swbuf_r>: - 8004340: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004342: 460e mov r6, r1 - 8004344: 4614 mov r4, r2 - 8004346: 4605 mov r5, r0 - 8004348: b118 cbz r0, 8004352 <__swbuf_r+0x12> - 800434a: 6983 ldr r3, [r0, #24] - 800434c: b90b cbnz r3, 8004352 <__swbuf_r+0x12> - 800434e: f000 f9d9 bl 8004704 <__sinit> - 8004352: 4b21 ldr r3, [pc, #132] ; (80043d8 <__swbuf_r+0x98>) - 8004354: 429c cmp r4, r3 - 8004356: d12b bne.n 80043b0 <__swbuf_r+0x70> - 8004358: 686c ldr r4, [r5, #4] - 800435a: 69a3 ldr r3, [r4, #24] - 800435c: 60a3 str r3, [r4, #8] - 800435e: 89a3 ldrh r3, [r4, #12] - 8004360: 071a lsls r2, r3, #28 - 8004362: d52f bpl.n 80043c4 <__swbuf_r+0x84> - 8004364: 6923 ldr r3, [r4, #16] - 8004366: b36b cbz r3, 80043c4 <__swbuf_r+0x84> - 8004368: 6923 ldr r3, [r4, #16] - 800436a: 6820 ldr r0, [r4, #0] - 800436c: 1ac0 subs r0, r0, r3 - 800436e: 6963 ldr r3, [r4, #20] - 8004370: b2f6 uxtb r6, r6 - 8004372: 4283 cmp r3, r0 - 8004374: 4637 mov r7, r6 - 8004376: dc04 bgt.n 8004382 <__swbuf_r+0x42> - 8004378: 4621 mov r1, r4 - 800437a: 4628 mov r0, r5 - 800437c: f000 f92e bl 80045dc <_fflush_r> - 8004380: bb30 cbnz r0, 80043d0 <__swbuf_r+0x90> - 8004382: 68a3 ldr r3, [r4, #8] - 8004384: 3b01 subs r3, #1 - 8004386: 60a3 str r3, [r4, #8] - 8004388: 6823 ldr r3, [r4, #0] - 800438a: 1c5a adds r2, r3, #1 - 800438c: 6022 str r2, [r4, #0] - 800438e: 701e strb r6, [r3, #0] - 8004390: 6963 ldr r3, [r4, #20] - 8004392: 3001 adds r0, #1 - 8004394: 4283 cmp r3, r0 - 8004396: d004 beq.n 80043a2 <__swbuf_r+0x62> - 8004398: 89a3 ldrh r3, [r4, #12] - 800439a: 07db lsls r3, r3, #31 - 800439c: d506 bpl.n 80043ac <__swbuf_r+0x6c> - 800439e: 2e0a cmp r6, #10 - 80043a0: d104 bne.n 80043ac <__swbuf_r+0x6c> - 80043a2: 4621 mov r1, r4 - 80043a4: 4628 mov r0, r5 - 80043a6: f000 f919 bl 80045dc <_fflush_r> - 80043aa: b988 cbnz r0, 80043d0 <__swbuf_r+0x90> - 80043ac: 4638 mov r0, r7 - 80043ae: bdf8 pop {r3, r4, r5, r6, r7, pc} - 80043b0: 4b0a ldr r3, [pc, #40] ; (80043dc <__swbuf_r+0x9c>) - 80043b2: 429c cmp r4, r3 - 80043b4: d101 bne.n 80043ba <__swbuf_r+0x7a> - 80043b6: 68ac ldr r4, [r5, #8] - 80043b8: e7cf b.n 800435a <__swbuf_r+0x1a> - 80043ba: 4b09 ldr r3, [pc, #36] ; (80043e0 <__swbuf_r+0xa0>) - 80043bc: 429c cmp r4, r3 - 80043be: bf08 it eq - 80043c0: 68ec ldreq r4, [r5, #12] - 80043c2: e7ca b.n 800435a <__swbuf_r+0x1a> - 80043c4: 4621 mov r1, r4 - 80043c6: 4628 mov r0, r5 - 80043c8: f000 f80c bl 80043e4 <__swsetup_r> - 80043cc: 2800 cmp r0, #0 - 80043ce: d0cb beq.n 8004368 <__swbuf_r+0x28> - 80043d0: f04f 37ff mov.w r7, #4294967295 - 80043d4: e7ea b.n 80043ac <__swbuf_r+0x6c> - 80043d6: bf00 nop - 80043d8: 08004c88 .word 0x08004c88 - 80043dc: 08004ca8 .word 0x08004ca8 - 80043e0: 08004c68 .word 0x08004c68 - -080043e4 <__swsetup_r>: - 80043e4: 4b32 ldr r3, [pc, #200] ; (80044b0 <__swsetup_r+0xcc>) - 80043e6: b570 push {r4, r5, r6, lr} - 80043e8: 681d ldr r5, [r3, #0] - 80043ea: 4606 mov r6, r0 - 80043ec: 460c mov r4, r1 - 80043ee: b125 cbz r5, 80043fa <__swsetup_r+0x16> - 80043f0: 69ab ldr r3, [r5, #24] - 80043f2: b913 cbnz r3, 80043fa <__swsetup_r+0x16> - 80043f4: 4628 mov r0, r5 - 80043f6: f000 f985 bl 8004704 <__sinit> - 80043fa: 4b2e ldr r3, [pc, #184] ; (80044b4 <__swsetup_r+0xd0>) - 80043fc: 429c cmp r4, r3 - 80043fe: d10f bne.n 8004420 <__swsetup_r+0x3c> - 8004400: 686c ldr r4, [r5, #4] - 8004402: 89a3 ldrh r3, [r4, #12] - 8004404: f9b4 200c ldrsh.w r2, [r4, #12] - 8004408: 0719 lsls r1, r3, #28 - 800440a: d42c bmi.n 8004466 <__swsetup_r+0x82> - 800440c: 06dd lsls r5, r3, #27 - 800440e: d411 bmi.n 8004434 <__swsetup_r+0x50> - 8004410: 2309 movs r3, #9 - 8004412: 6033 str r3, [r6, #0] - 8004414: f042 0340 orr.w r3, r2, #64 ; 0x40 - 8004418: 81a3 strh r3, [r4, #12] - 800441a: f04f 30ff mov.w r0, #4294967295 - 800441e: e03e b.n 800449e <__swsetup_r+0xba> - 8004420: 4b25 ldr r3, [pc, #148] ; (80044b8 <__swsetup_r+0xd4>) - 8004422: 429c cmp r4, r3 - 8004424: d101 bne.n 800442a <__swsetup_r+0x46> - 8004426: 68ac ldr r4, [r5, #8] - 8004428: e7eb b.n 8004402 <__swsetup_r+0x1e> - 800442a: 4b24 ldr r3, [pc, #144] ; (80044bc <__swsetup_r+0xd8>) - 800442c: 429c cmp r4, r3 - 800442e: bf08 it eq - 8004430: 68ec ldreq r4, [r5, #12] - 8004432: e7e6 b.n 8004402 <__swsetup_r+0x1e> - 8004434: 0758 lsls r0, r3, #29 - 8004436: d512 bpl.n 800445e <__swsetup_r+0x7a> - 8004438: 6b61 ldr r1, [r4, #52] ; 0x34 - 800443a: b141 cbz r1, 800444e <__swsetup_r+0x6a> - 800443c: f104 0344 add.w r3, r4, #68 ; 0x44 - 8004440: 4299 cmp r1, r3 - 8004442: d002 beq.n 800444a <__swsetup_r+0x66> - 8004444: 4630 mov r0, r6 - 8004446: f7ff fb9d bl 8003b84 <_free_r> - 800444a: 2300 movs r3, #0 - 800444c: 6363 str r3, [r4, #52] ; 0x34 - 800444e: 89a3 ldrh r3, [r4, #12] - 8004450: f023 0324 bic.w r3, r3, #36 ; 0x24 - 8004454: 81a3 strh r3, [r4, #12] - 8004456: 2300 movs r3, #0 - 8004458: 6063 str r3, [r4, #4] - 800445a: 6923 ldr r3, [r4, #16] - 800445c: 6023 str r3, [r4, #0] - 800445e: 89a3 ldrh r3, [r4, #12] - 8004460: f043 0308 orr.w r3, r3, #8 - 8004464: 81a3 strh r3, [r4, #12] - 8004466: 6923 ldr r3, [r4, #16] - 8004468: b94b cbnz r3, 800447e <__swsetup_r+0x9a> - 800446a: 89a3 ldrh r3, [r4, #12] - 800446c: f403 7320 and.w r3, r3, #640 ; 0x280 - 8004470: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8004474: d003 beq.n 800447e <__swsetup_r+0x9a> - 8004476: 4621 mov r1, r4 - 8004478: 4630 mov r0, r6 - 800447a: f000 fa09 bl 8004890 <__smakebuf_r> - 800447e: 89a0 ldrh r0, [r4, #12] - 8004480: f9b4 200c ldrsh.w r2, [r4, #12] - 8004484: f010 0301 ands.w r3, r0, #1 - 8004488: d00a beq.n 80044a0 <__swsetup_r+0xbc> - 800448a: 2300 movs r3, #0 - 800448c: 60a3 str r3, [r4, #8] - 800448e: 6963 ldr r3, [r4, #20] - 8004490: 425b negs r3, r3 - 8004492: 61a3 str r3, [r4, #24] - 8004494: 6923 ldr r3, [r4, #16] - 8004496: b943 cbnz r3, 80044aa <__swsetup_r+0xc6> - 8004498: f010 0080 ands.w r0, r0, #128 ; 0x80 - 800449c: d1ba bne.n 8004414 <__swsetup_r+0x30> - 800449e: bd70 pop {r4, r5, r6, pc} - 80044a0: 0781 lsls r1, r0, #30 - 80044a2: bf58 it pl - 80044a4: 6963 ldrpl r3, [r4, #20] - 80044a6: 60a3 str r3, [r4, #8] - 80044a8: e7f4 b.n 8004494 <__swsetup_r+0xb0> - 80044aa: 2000 movs r0, #0 - 80044ac: e7f7 b.n 800449e <__swsetup_r+0xba> - 80044ae: bf00 nop - 80044b0: 20002688 .word 0x20002688 - 80044b4: 08004c88 .word 0x08004c88 - 80044b8: 08004ca8 .word 0x08004ca8 - 80044bc: 08004c68 .word 0x08004c68 - -080044c0 : - 80044c0: b508 push {r3, lr} - 80044c2: 2006 movs r0, #6 - 80044c4: f000 fa58 bl 8004978 - 80044c8: 2001 movs r0, #1 - 80044ca: f7fd fd35 bl 8001f38 <_exit> - ... - -080044d0 <__sflush_r>: - 80044d0: 898a ldrh r2, [r1, #12] - 80044d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 80044d6: 4605 mov r5, r0 - 80044d8: 0710 lsls r0, r2, #28 - 80044da: 460c mov r4, r1 - 80044dc: d458 bmi.n 8004590 <__sflush_r+0xc0> - 80044de: 684b ldr r3, [r1, #4] - 80044e0: 2b00 cmp r3, #0 - 80044e2: dc05 bgt.n 80044f0 <__sflush_r+0x20> - 80044e4: 6c0b ldr r3, [r1, #64] ; 0x40 - 80044e6: 2b00 cmp r3, #0 - 80044e8: dc02 bgt.n 80044f0 <__sflush_r+0x20> - 80044ea: 2000 movs r0, #0 - 80044ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 80044f0: 6ae6 ldr r6, [r4, #44] ; 0x2c - 80044f2: 2e00 cmp r6, #0 - 80044f4: d0f9 beq.n 80044ea <__sflush_r+0x1a> - 80044f6: 2300 movs r3, #0 - 80044f8: f412 5280 ands.w r2, r2, #4096 ; 0x1000 - 80044fc: 682f ldr r7, [r5, #0] - 80044fe: 602b str r3, [r5, #0] - 8004500: d032 beq.n 8004568 <__sflush_r+0x98> - 8004502: 6d60 ldr r0, [r4, #84] ; 0x54 - 8004504: 89a3 ldrh r3, [r4, #12] - 8004506: 075a lsls r2, r3, #29 - 8004508: d505 bpl.n 8004516 <__sflush_r+0x46> - 800450a: 6863 ldr r3, [r4, #4] - 800450c: 1ac0 subs r0, r0, r3 - 800450e: 6b63 ldr r3, [r4, #52] ; 0x34 - 8004510: b10b cbz r3, 8004516 <__sflush_r+0x46> - 8004512: 6c23 ldr r3, [r4, #64] ; 0x40 - 8004514: 1ac0 subs r0, r0, r3 - 8004516: 2300 movs r3, #0 - 8004518: 4602 mov r2, r0 - 800451a: 6ae6 ldr r6, [r4, #44] ; 0x2c - 800451c: 6a21 ldr r1, [r4, #32] - 800451e: 4628 mov r0, r5 - 8004520: 47b0 blx r6 - 8004522: 1c43 adds r3, r0, #1 - 8004524: 89a3 ldrh r3, [r4, #12] - 8004526: d106 bne.n 8004536 <__sflush_r+0x66> - 8004528: 6829 ldr r1, [r5, #0] - 800452a: 291d cmp r1, #29 - 800452c: d82c bhi.n 8004588 <__sflush_r+0xb8> - 800452e: 4a2a ldr r2, [pc, #168] ; (80045d8 <__sflush_r+0x108>) - 8004530: 40ca lsrs r2, r1 - 8004532: 07d6 lsls r6, r2, #31 - 8004534: d528 bpl.n 8004588 <__sflush_r+0xb8> - 8004536: 2200 movs r2, #0 - 8004538: 6062 str r2, [r4, #4] - 800453a: 04d9 lsls r1, r3, #19 - 800453c: 6922 ldr r2, [r4, #16] - 800453e: 6022 str r2, [r4, #0] - 8004540: d504 bpl.n 800454c <__sflush_r+0x7c> - 8004542: 1c42 adds r2, r0, #1 - 8004544: d101 bne.n 800454a <__sflush_r+0x7a> - 8004546: 682b ldr r3, [r5, #0] - 8004548: b903 cbnz r3, 800454c <__sflush_r+0x7c> - 800454a: 6560 str r0, [r4, #84] ; 0x54 - 800454c: 6b61 ldr r1, [r4, #52] ; 0x34 - 800454e: 602f str r7, [r5, #0] - 8004550: 2900 cmp r1, #0 - 8004552: d0ca beq.n 80044ea <__sflush_r+0x1a> - 8004554: f104 0344 add.w r3, r4, #68 ; 0x44 - 8004558: 4299 cmp r1, r3 - 800455a: d002 beq.n 8004562 <__sflush_r+0x92> - 800455c: 4628 mov r0, r5 - 800455e: f7ff fb11 bl 8003b84 <_free_r> - 8004562: 2000 movs r0, #0 - 8004564: 6360 str r0, [r4, #52] ; 0x34 - 8004566: e7c1 b.n 80044ec <__sflush_r+0x1c> - 8004568: 6a21 ldr r1, [r4, #32] - 800456a: 2301 movs r3, #1 - 800456c: 4628 mov r0, r5 - 800456e: 47b0 blx r6 - 8004570: 1c41 adds r1, r0, #1 - 8004572: d1c7 bne.n 8004504 <__sflush_r+0x34> - 8004574: 682b ldr r3, [r5, #0] - 8004576: 2b00 cmp r3, #0 - 8004578: d0c4 beq.n 8004504 <__sflush_r+0x34> - 800457a: 2b1d cmp r3, #29 - 800457c: d001 beq.n 8004582 <__sflush_r+0xb2> - 800457e: 2b16 cmp r3, #22 - 8004580: d101 bne.n 8004586 <__sflush_r+0xb6> - 8004582: 602f str r7, [r5, #0] - 8004584: e7b1 b.n 80044ea <__sflush_r+0x1a> - 8004586: 89a3 ldrh r3, [r4, #12] - 8004588: f043 0340 orr.w r3, r3, #64 ; 0x40 - 800458c: 81a3 strh r3, [r4, #12] - 800458e: e7ad b.n 80044ec <__sflush_r+0x1c> - 8004590: 690f ldr r7, [r1, #16] - 8004592: 2f00 cmp r7, #0 - 8004594: d0a9 beq.n 80044ea <__sflush_r+0x1a> - 8004596: 0793 lsls r3, r2, #30 - 8004598: 680e ldr r6, [r1, #0] - 800459a: bf08 it eq - 800459c: 694b ldreq r3, [r1, #20] - 800459e: 600f str r7, [r1, #0] - 80045a0: bf18 it ne - 80045a2: 2300 movne r3, #0 - 80045a4: eba6 0807 sub.w r8, r6, r7 - 80045a8: 608b str r3, [r1, #8] - 80045aa: f1b8 0f00 cmp.w r8, #0 - 80045ae: dd9c ble.n 80044ea <__sflush_r+0x1a> - 80045b0: 6a21 ldr r1, [r4, #32] - 80045b2: 6aa6 ldr r6, [r4, #40] ; 0x28 - 80045b4: 4643 mov r3, r8 - 80045b6: 463a mov r2, r7 - 80045b8: 4628 mov r0, r5 - 80045ba: 47b0 blx r6 - 80045bc: 2800 cmp r0, #0 - 80045be: dc06 bgt.n 80045ce <__sflush_r+0xfe> - 80045c0: 89a3 ldrh r3, [r4, #12] - 80045c2: f043 0340 orr.w r3, r3, #64 ; 0x40 - 80045c6: 81a3 strh r3, [r4, #12] - 80045c8: f04f 30ff mov.w r0, #4294967295 - 80045cc: e78e b.n 80044ec <__sflush_r+0x1c> - 80045ce: 4407 add r7, r0 - 80045d0: eba8 0800 sub.w r8, r8, r0 - 80045d4: e7e9 b.n 80045aa <__sflush_r+0xda> - 80045d6: bf00 nop - 80045d8: 20400001 .word 0x20400001 - -080045dc <_fflush_r>: - 80045dc: b538 push {r3, r4, r5, lr} - 80045de: 690b ldr r3, [r1, #16] - 80045e0: 4605 mov r5, r0 - 80045e2: 460c mov r4, r1 - 80045e4: b913 cbnz r3, 80045ec <_fflush_r+0x10> - 80045e6: 2500 movs r5, #0 - 80045e8: 4628 mov r0, r5 - 80045ea: bd38 pop {r3, r4, r5, pc} - 80045ec: b118 cbz r0, 80045f6 <_fflush_r+0x1a> - 80045ee: 6983 ldr r3, [r0, #24] - 80045f0: b90b cbnz r3, 80045f6 <_fflush_r+0x1a> - 80045f2: f000 f887 bl 8004704 <__sinit> - 80045f6: 4b14 ldr r3, [pc, #80] ; (8004648 <_fflush_r+0x6c>) - 80045f8: 429c cmp r4, r3 - 80045fa: d11b bne.n 8004634 <_fflush_r+0x58> - 80045fc: 686c ldr r4, [r5, #4] - 80045fe: f9b4 300c ldrsh.w r3, [r4, #12] - 8004602: 2b00 cmp r3, #0 - 8004604: d0ef beq.n 80045e6 <_fflush_r+0xa> - 8004606: 6e62 ldr r2, [r4, #100] ; 0x64 - 8004608: 07d0 lsls r0, r2, #31 - 800460a: d404 bmi.n 8004616 <_fflush_r+0x3a> - 800460c: 0599 lsls r1, r3, #22 - 800460e: d402 bmi.n 8004616 <_fflush_r+0x3a> - 8004610: 6da0 ldr r0, [r4, #88] ; 0x58 - 8004612: f000 f915 bl 8004840 <__retarget_lock_acquire_recursive> - 8004616: 4628 mov r0, r5 - 8004618: 4621 mov r1, r4 - 800461a: f7ff ff59 bl 80044d0 <__sflush_r> - 800461e: 6e63 ldr r3, [r4, #100] ; 0x64 - 8004620: 07da lsls r2, r3, #31 - 8004622: 4605 mov r5, r0 - 8004624: d4e0 bmi.n 80045e8 <_fflush_r+0xc> - 8004626: 89a3 ldrh r3, [r4, #12] - 8004628: 059b lsls r3, r3, #22 - 800462a: d4dd bmi.n 80045e8 <_fflush_r+0xc> - 800462c: 6da0 ldr r0, [r4, #88] ; 0x58 - 800462e: f000 f908 bl 8004842 <__retarget_lock_release_recursive> - 8004632: e7d9 b.n 80045e8 <_fflush_r+0xc> - 8004634: 4b05 ldr r3, [pc, #20] ; (800464c <_fflush_r+0x70>) - 8004636: 429c cmp r4, r3 - 8004638: d101 bne.n 800463e <_fflush_r+0x62> - 800463a: 68ac ldr r4, [r5, #8] - 800463c: e7df b.n 80045fe <_fflush_r+0x22> - 800463e: 4b04 ldr r3, [pc, #16] ; (8004650 <_fflush_r+0x74>) - 8004640: 429c cmp r4, r3 - 8004642: bf08 it eq - 8004644: 68ec ldreq r4, [r5, #12] - 8004646: e7da b.n 80045fe <_fflush_r+0x22> - 8004648: 08004c88 .word 0x08004c88 - 800464c: 08004ca8 .word 0x08004ca8 - 8004650: 08004c68 .word 0x08004c68 - -08004654 : - 8004654: 2300 movs r3, #0 - 8004656: b510 push {r4, lr} - 8004658: 4604 mov r4, r0 - 800465a: e9c0 3300 strd r3, r3, [r0] - 800465e: e9c0 3304 strd r3, r3, [r0, #16] - 8004662: 6083 str r3, [r0, #8] - 8004664: 8181 strh r1, [r0, #12] - 8004666: 6643 str r3, [r0, #100] ; 0x64 - 8004668: 81c2 strh r2, [r0, #14] - 800466a: 6183 str r3, [r0, #24] - 800466c: 4619 mov r1, r3 - 800466e: 2208 movs r2, #8 - 8004670: 305c adds r0, #92 ; 0x5c - 8004672: f7ff fa09 bl 8003a88 - 8004676: 4b05 ldr r3, [pc, #20] ; (800468c ) - 8004678: 6263 str r3, [r4, #36] ; 0x24 - 800467a: 4b05 ldr r3, [pc, #20] ; (8004690 ) - 800467c: 62a3 str r3, [r4, #40] ; 0x28 - 800467e: 4b05 ldr r3, [pc, #20] ; (8004694 ) - 8004680: 62e3 str r3, [r4, #44] ; 0x2c - 8004682: 4b05 ldr r3, [pc, #20] ; (8004698 ) - 8004684: 6224 str r4, [r4, #32] - 8004686: 6323 str r3, [r4, #48] ; 0x30 - 8004688: bd10 pop {r4, pc} - 800468a: bf00 nop - 800468c: 080049b1 .word 0x080049b1 - 8004690: 080049d3 .word 0x080049d3 - 8004694: 08004a0b .word 0x08004a0b - 8004698: 08004a2f .word 0x08004a2f - -0800469c <_cleanup_r>: - 800469c: 4901 ldr r1, [pc, #4] ; (80046a4 <_cleanup_r+0x8>) - 800469e: f000 b8af b.w 8004800 <_fwalk_reent> - 80046a2: bf00 nop - 80046a4: 080045dd .word 0x080045dd - -080046a8 <__sfmoreglue>: - 80046a8: b570 push {r4, r5, r6, lr} - 80046aa: 2268 movs r2, #104 ; 0x68 - 80046ac: 1e4d subs r5, r1, #1 - 80046ae: 4355 muls r5, r2 - 80046b0: 460e mov r6, r1 - 80046b2: f105 0174 add.w r1, r5, #116 ; 0x74 - 80046b6: f7ff fad1 bl 8003c5c <_malloc_r> - 80046ba: 4604 mov r4, r0 - 80046bc: b140 cbz r0, 80046d0 <__sfmoreglue+0x28> - 80046be: 2100 movs r1, #0 - 80046c0: e9c0 1600 strd r1, r6, [r0] - 80046c4: 300c adds r0, #12 - 80046c6: 60a0 str r0, [r4, #8] - 80046c8: f105 0268 add.w r2, r5, #104 ; 0x68 - 80046cc: f7ff f9dc bl 8003a88 - 80046d0: 4620 mov r0, r4 - 80046d2: bd70 pop {r4, r5, r6, pc} - -080046d4 <__sfp_lock_acquire>: - 80046d4: 4801 ldr r0, [pc, #4] ; (80046dc <__sfp_lock_acquire+0x8>) - 80046d6: f000 b8b3 b.w 8004840 <__retarget_lock_acquire_recursive> - 80046da: bf00 nop - 80046dc: 200027a5 .word 0x200027a5 - -080046e0 <__sfp_lock_release>: - 80046e0: 4801 ldr r0, [pc, #4] ; (80046e8 <__sfp_lock_release+0x8>) - 80046e2: f000 b8ae b.w 8004842 <__retarget_lock_release_recursive> - 80046e6: bf00 nop - 80046e8: 200027a5 .word 0x200027a5 - -080046ec <__sinit_lock_acquire>: - 80046ec: 4801 ldr r0, [pc, #4] ; (80046f4 <__sinit_lock_acquire+0x8>) - 80046ee: f000 b8a7 b.w 8004840 <__retarget_lock_acquire_recursive> - 80046f2: bf00 nop - 80046f4: 200027a6 .word 0x200027a6 - -080046f8 <__sinit_lock_release>: - 80046f8: 4801 ldr r0, [pc, #4] ; (8004700 <__sinit_lock_release+0x8>) - 80046fa: f000 b8a2 b.w 8004842 <__retarget_lock_release_recursive> - 80046fe: bf00 nop - 8004700: 200027a6 .word 0x200027a6 - -08004704 <__sinit>: - 8004704: b510 push {r4, lr} - 8004706: 4604 mov r4, r0 - 8004708: f7ff fff0 bl 80046ec <__sinit_lock_acquire> - 800470c: 69a3 ldr r3, [r4, #24] - 800470e: b11b cbz r3, 8004718 <__sinit+0x14> - 8004710: e8bd 4010 ldmia.w sp!, {r4, lr} - 8004714: f7ff bff0 b.w 80046f8 <__sinit_lock_release> - 8004718: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 - 800471c: 6523 str r3, [r4, #80] ; 0x50 - 800471e: 4b13 ldr r3, [pc, #76] ; (800476c <__sinit+0x68>) - 8004720: 4a13 ldr r2, [pc, #76] ; (8004770 <__sinit+0x6c>) - 8004722: 681b ldr r3, [r3, #0] - 8004724: 62a2 str r2, [r4, #40] ; 0x28 - 8004726: 42a3 cmp r3, r4 - 8004728: bf04 itt eq - 800472a: 2301 moveq r3, #1 - 800472c: 61a3 streq r3, [r4, #24] - 800472e: 4620 mov r0, r4 - 8004730: f000 f820 bl 8004774 <__sfp> - 8004734: 6060 str r0, [r4, #4] - 8004736: 4620 mov r0, r4 - 8004738: f000 f81c bl 8004774 <__sfp> - 800473c: 60a0 str r0, [r4, #8] - 800473e: 4620 mov r0, r4 - 8004740: f000 f818 bl 8004774 <__sfp> - 8004744: 2200 movs r2, #0 - 8004746: 60e0 str r0, [r4, #12] - 8004748: 2104 movs r1, #4 - 800474a: 6860 ldr r0, [r4, #4] - 800474c: f7ff ff82 bl 8004654 - 8004750: 68a0 ldr r0, [r4, #8] - 8004752: 2201 movs r2, #1 - 8004754: 2109 movs r1, #9 - 8004756: f7ff ff7d bl 8004654 - 800475a: 68e0 ldr r0, [r4, #12] - 800475c: 2202 movs r2, #2 - 800475e: 2112 movs r1, #18 - 8004760: f7ff ff78 bl 8004654 - 8004764: 2301 movs r3, #1 - 8004766: 61a3 str r3, [r4, #24] - 8004768: e7d2 b.n 8004710 <__sinit+0xc> - 800476a: bf00 nop - 800476c: 08004b80 .word 0x08004b80 - 8004770: 0800469d .word 0x0800469d - -08004774 <__sfp>: - 8004774: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004776: 4607 mov r7, r0 - 8004778: f7ff ffac bl 80046d4 <__sfp_lock_acquire> - 800477c: 4b1e ldr r3, [pc, #120] ; (80047f8 <__sfp+0x84>) - 800477e: 681e ldr r6, [r3, #0] - 8004780: 69b3 ldr r3, [r6, #24] - 8004782: b913 cbnz r3, 800478a <__sfp+0x16> - 8004784: 4630 mov r0, r6 - 8004786: f7ff ffbd bl 8004704 <__sinit> - 800478a: 3648 adds r6, #72 ; 0x48 - 800478c: e9d6 3401 ldrd r3, r4, [r6, #4] - 8004790: 3b01 subs r3, #1 - 8004792: d503 bpl.n 800479c <__sfp+0x28> - 8004794: 6833 ldr r3, [r6, #0] - 8004796: b30b cbz r3, 80047dc <__sfp+0x68> - 8004798: 6836 ldr r6, [r6, #0] - 800479a: e7f7 b.n 800478c <__sfp+0x18> - 800479c: f9b4 500c ldrsh.w r5, [r4, #12] - 80047a0: b9d5 cbnz r5, 80047d8 <__sfp+0x64> - 80047a2: 4b16 ldr r3, [pc, #88] ; (80047fc <__sfp+0x88>) - 80047a4: 60e3 str r3, [r4, #12] - 80047a6: f104 0058 add.w r0, r4, #88 ; 0x58 - 80047aa: 6665 str r5, [r4, #100] ; 0x64 - 80047ac: f000 f847 bl 800483e <__retarget_lock_init_recursive> - 80047b0: f7ff ff96 bl 80046e0 <__sfp_lock_release> - 80047b4: e9c4 5501 strd r5, r5, [r4, #4] - 80047b8: e9c4 5504 strd r5, r5, [r4, #16] - 80047bc: 6025 str r5, [r4, #0] - 80047be: 61a5 str r5, [r4, #24] - 80047c0: 2208 movs r2, #8 - 80047c2: 4629 mov r1, r5 - 80047c4: f104 005c add.w r0, r4, #92 ; 0x5c - 80047c8: f7ff f95e bl 8003a88 - 80047cc: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 - 80047d0: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 - 80047d4: 4620 mov r0, r4 - 80047d6: bdf8 pop {r3, r4, r5, r6, r7, pc} - 80047d8: 3468 adds r4, #104 ; 0x68 - 80047da: e7d9 b.n 8004790 <__sfp+0x1c> - 80047dc: 2104 movs r1, #4 - 80047de: 4638 mov r0, r7 - 80047e0: f7ff ff62 bl 80046a8 <__sfmoreglue> - 80047e4: 4604 mov r4, r0 - 80047e6: 6030 str r0, [r6, #0] - 80047e8: 2800 cmp r0, #0 - 80047ea: d1d5 bne.n 8004798 <__sfp+0x24> - 80047ec: f7ff ff78 bl 80046e0 <__sfp_lock_release> - 80047f0: 230c movs r3, #12 - 80047f2: 603b str r3, [r7, #0] - 80047f4: e7ee b.n 80047d4 <__sfp+0x60> - 80047f6: bf00 nop - 80047f8: 08004b80 .word 0x08004b80 - 80047fc: ffff0001 .word 0xffff0001 - -08004800 <_fwalk_reent>: - 8004800: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 8004804: 4606 mov r6, r0 - 8004806: 4688 mov r8, r1 - 8004808: f100 0448 add.w r4, r0, #72 ; 0x48 - 800480c: 2700 movs r7, #0 - 800480e: e9d4 9501 ldrd r9, r5, [r4, #4] - 8004812: f1b9 0901 subs.w r9, r9, #1 - 8004816: d505 bpl.n 8004824 <_fwalk_reent+0x24> - 8004818: 6824 ldr r4, [r4, #0] - 800481a: 2c00 cmp r4, #0 - 800481c: d1f7 bne.n 800480e <_fwalk_reent+0xe> - 800481e: 4638 mov r0, r7 - 8004820: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8004824: 89ab ldrh r3, [r5, #12] - 8004826: 2b01 cmp r3, #1 - 8004828: d907 bls.n 800483a <_fwalk_reent+0x3a> - 800482a: f9b5 300e ldrsh.w r3, [r5, #14] - 800482e: 3301 adds r3, #1 - 8004830: d003 beq.n 800483a <_fwalk_reent+0x3a> - 8004832: 4629 mov r1, r5 - 8004834: 4630 mov r0, r6 - 8004836: 47c0 blx r8 - 8004838: 4307 orrs r7, r0 - 800483a: 3568 adds r5, #104 ; 0x68 - 800483c: e7e9 b.n 8004812 <_fwalk_reent+0x12> - -0800483e <__retarget_lock_init_recursive>: - 800483e: 4770 bx lr - -08004840 <__retarget_lock_acquire_recursive>: - 8004840: 4770 bx lr - -08004842 <__retarget_lock_release_recursive>: - 8004842: 4770 bx lr - -08004844 <__swhatbuf_r>: - 8004844: b570 push {r4, r5, r6, lr} - 8004846: 460e mov r6, r1 - 8004848: f9b1 100e ldrsh.w r1, [r1, #14] - 800484c: 2900 cmp r1, #0 - 800484e: b096 sub sp, #88 ; 0x58 - 8004850: 4614 mov r4, r2 - 8004852: 461d mov r5, r3 - 8004854: da08 bge.n 8004868 <__swhatbuf_r+0x24> - 8004856: f9b6 300c ldrsh.w r3, [r6, #12] - 800485a: 2200 movs r2, #0 - 800485c: 602a str r2, [r5, #0] - 800485e: 061a lsls r2, r3, #24 - 8004860: d410 bmi.n 8004884 <__swhatbuf_r+0x40> - 8004862: f44f 6380 mov.w r3, #1024 ; 0x400 - 8004866: e00e b.n 8004886 <__swhatbuf_r+0x42> - 8004868: 466a mov r2, sp - 800486a: f000 f907 bl 8004a7c <_fstat_r> - 800486e: 2800 cmp r0, #0 - 8004870: dbf1 blt.n 8004856 <__swhatbuf_r+0x12> - 8004872: 9a01 ldr r2, [sp, #4] - 8004874: f402 4270 and.w r2, r2, #61440 ; 0xf000 - 8004878: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 - 800487c: 425a negs r2, r3 - 800487e: 415a adcs r2, r3 - 8004880: 602a str r2, [r5, #0] - 8004882: e7ee b.n 8004862 <__swhatbuf_r+0x1e> - 8004884: 2340 movs r3, #64 ; 0x40 - 8004886: 2000 movs r0, #0 - 8004888: 6023 str r3, [r4, #0] - 800488a: b016 add sp, #88 ; 0x58 - 800488c: bd70 pop {r4, r5, r6, pc} - ... - -08004890 <__smakebuf_r>: - 8004890: 898b ldrh r3, [r1, #12] - 8004892: b573 push {r0, r1, r4, r5, r6, lr} - 8004894: 079d lsls r5, r3, #30 - 8004896: 4606 mov r6, r0 - 8004898: 460c mov r4, r1 - 800489a: d507 bpl.n 80048ac <__smakebuf_r+0x1c> - 800489c: f104 0347 add.w r3, r4, #71 ; 0x47 - 80048a0: 6023 str r3, [r4, #0] - 80048a2: 6123 str r3, [r4, #16] - 80048a4: 2301 movs r3, #1 - 80048a6: 6163 str r3, [r4, #20] - 80048a8: b002 add sp, #8 - 80048aa: bd70 pop {r4, r5, r6, pc} - 80048ac: ab01 add r3, sp, #4 - 80048ae: 466a mov r2, sp - 80048b0: f7ff ffc8 bl 8004844 <__swhatbuf_r> - 80048b4: 9900 ldr r1, [sp, #0] - 80048b6: 4605 mov r5, r0 - 80048b8: 4630 mov r0, r6 - 80048ba: f7ff f9cf bl 8003c5c <_malloc_r> - 80048be: b948 cbnz r0, 80048d4 <__smakebuf_r+0x44> - 80048c0: f9b4 300c ldrsh.w r3, [r4, #12] - 80048c4: 059a lsls r2, r3, #22 - 80048c6: d4ef bmi.n 80048a8 <__smakebuf_r+0x18> - 80048c8: f023 0303 bic.w r3, r3, #3 - 80048cc: f043 0302 orr.w r3, r3, #2 - 80048d0: 81a3 strh r3, [r4, #12] - 80048d2: e7e3 b.n 800489c <__smakebuf_r+0xc> - 80048d4: 4b0d ldr r3, [pc, #52] ; (800490c <__smakebuf_r+0x7c>) - 80048d6: 62b3 str r3, [r6, #40] ; 0x28 - 80048d8: 89a3 ldrh r3, [r4, #12] - 80048da: 6020 str r0, [r4, #0] - 80048dc: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80048e0: 81a3 strh r3, [r4, #12] - 80048e2: 9b00 ldr r3, [sp, #0] - 80048e4: 6163 str r3, [r4, #20] - 80048e6: 9b01 ldr r3, [sp, #4] - 80048e8: 6120 str r0, [r4, #16] - 80048ea: b15b cbz r3, 8004904 <__smakebuf_r+0x74> - 80048ec: f9b4 100e ldrsh.w r1, [r4, #14] - 80048f0: 4630 mov r0, r6 - 80048f2: f000 f8d5 bl 8004aa0 <_isatty_r> - 80048f6: b128 cbz r0, 8004904 <__smakebuf_r+0x74> - 80048f8: 89a3 ldrh r3, [r4, #12] - 80048fa: f023 0303 bic.w r3, r3, #3 - 80048fe: f043 0301 orr.w r3, r3, #1 - 8004902: 81a3 strh r3, [r4, #12] - 8004904: 89a0 ldrh r0, [r4, #12] - 8004906: 4305 orrs r5, r0 - 8004908: 81a5 strh r5, [r4, #12] - 800490a: e7cd b.n 80048a8 <__smakebuf_r+0x18> - 800490c: 0800469d .word 0x0800469d - -08004910 <__malloc_lock>: - 8004910: 4801 ldr r0, [pc, #4] ; (8004918 <__malloc_lock+0x8>) - 8004912: f7ff bf95 b.w 8004840 <__retarget_lock_acquire_recursive> - 8004916: bf00 nop - 8004918: 200027a4 .word 0x200027a4 - -0800491c <__malloc_unlock>: - 800491c: 4801 ldr r0, [pc, #4] ; (8004924 <__malloc_unlock+0x8>) - 800491e: f7ff bf90 b.w 8004842 <__retarget_lock_release_recursive> - 8004922: bf00 nop - 8004924: 200027a4 .word 0x200027a4 - -08004928 <_raise_r>: - 8004928: 291f cmp r1, #31 - 800492a: b538 push {r3, r4, r5, lr} - 800492c: 4604 mov r4, r0 - 800492e: 460d mov r5, r1 - 8004930: d904 bls.n 800493c <_raise_r+0x14> - 8004932: 2316 movs r3, #22 - 8004934: 6003 str r3, [r0, #0] - 8004936: f04f 30ff mov.w r0, #4294967295 - 800493a: bd38 pop {r3, r4, r5, pc} - 800493c: 6c42 ldr r2, [r0, #68] ; 0x44 - 800493e: b112 cbz r2, 8004946 <_raise_r+0x1e> - 8004940: f852 3021 ldr.w r3, [r2, r1, lsl #2] - 8004944: b94b cbnz r3, 800495a <_raise_r+0x32> - 8004946: 4620 mov r0, r4 - 8004948: f000 f830 bl 80049ac <_getpid_r> - 800494c: 462a mov r2, r5 - 800494e: 4601 mov r1, r0 - 8004950: 4620 mov r0, r4 - 8004952: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 8004956: f000 b817 b.w 8004988 <_kill_r> - 800495a: 2b01 cmp r3, #1 - 800495c: d00a beq.n 8004974 <_raise_r+0x4c> - 800495e: 1c59 adds r1, r3, #1 - 8004960: d103 bne.n 800496a <_raise_r+0x42> - 8004962: 2316 movs r3, #22 - 8004964: 6003 str r3, [r0, #0] - 8004966: 2001 movs r0, #1 - 8004968: e7e7 b.n 800493a <_raise_r+0x12> - 800496a: 2400 movs r4, #0 - 800496c: f842 4025 str.w r4, [r2, r5, lsl #2] - 8004970: 4628 mov r0, r5 - 8004972: 4798 blx r3 - 8004974: 2000 movs r0, #0 - 8004976: e7e0 b.n 800493a <_raise_r+0x12> - -08004978 : - 8004978: 4b02 ldr r3, [pc, #8] ; (8004984 ) - 800497a: 4601 mov r1, r0 - 800497c: 6818 ldr r0, [r3, #0] - 800497e: f7ff bfd3 b.w 8004928 <_raise_r> - 8004982: bf00 nop - 8004984: 20002688 .word 0x20002688 - -08004988 <_kill_r>: - 8004988: b538 push {r3, r4, r5, lr} - 800498a: 4d07 ldr r5, [pc, #28] ; (80049a8 <_kill_r+0x20>) - 800498c: 2300 movs r3, #0 - 800498e: 4604 mov r4, r0 - 8004990: 4608 mov r0, r1 - 8004992: 4611 mov r1, r2 - 8004994: 602b str r3, [r5, #0] - 8004996: f7fd fabf bl 8001f18 <_kill> - 800499a: 1c43 adds r3, r0, #1 - 800499c: d102 bne.n 80049a4 <_kill_r+0x1c> - 800499e: 682b ldr r3, [r5, #0] - 80049a0: b103 cbz r3, 80049a4 <_kill_r+0x1c> - 80049a2: 6023 str r3, [r4, #0] - 80049a4: bd38 pop {r3, r4, r5, pc} - 80049a6: bf00 nop - 80049a8: 200027a8 .word 0x200027a8 - -080049ac <_getpid_r>: - 80049ac: f7fd baac b.w 8001f08 <_getpid> - -080049b0 <__sread>: - 80049b0: b510 push {r4, lr} - 80049b2: 460c mov r4, r1 - 80049b4: f9b1 100e ldrsh.w r1, [r1, #14] - 80049b8: f000 f894 bl 8004ae4 <_read_r> - 80049bc: 2800 cmp r0, #0 - 80049be: bfab itete ge - 80049c0: 6d63 ldrge r3, [r4, #84] ; 0x54 - 80049c2: 89a3 ldrhlt r3, [r4, #12] - 80049c4: 181b addge r3, r3, r0 - 80049c6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 - 80049ca: bfac ite ge - 80049cc: 6563 strge r3, [r4, #84] ; 0x54 - 80049ce: 81a3 strhlt r3, [r4, #12] - 80049d0: bd10 pop {r4, pc} - -080049d2 <__swrite>: - 80049d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 80049d6: 461f mov r7, r3 - 80049d8: 898b ldrh r3, [r1, #12] - 80049da: 05db lsls r3, r3, #23 - 80049dc: 4605 mov r5, r0 - 80049de: 460c mov r4, r1 - 80049e0: 4616 mov r6, r2 - 80049e2: d505 bpl.n 80049f0 <__swrite+0x1e> - 80049e4: f9b1 100e ldrsh.w r1, [r1, #14] - 80049e8: 2302 movs r3, #2 - 80049ea: 2200 movs r2, #0 - 80049ec: f000 f868 bl 8004ac0 <_lseek_r> - 80049f0: 89a3 ldrh r3, [r4, #12] - 80049f2: f9b4 100e ldrsh.w r1, [r4, #14] - 80049f6: f423 5380 bic.w r3, r3, #4096 ; 0x1000 - 80049fa: 81a3 strh r3, [r4, #12] - 80049fc: 4632 mov r2, r6 - 80049fe: 463b mov r3, r7 - 8004a00: 4628 mov r0, r5 - 8004a02: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 8004a06: f000 b817 b.w 8004a38 <_write_r> - -08004a0a <__sseek>: - 8004a0a: b510 push {r4, lr} - 8004a0c: 460c mov r4, r1 - 8004a0e: f9b1 100e ldrsh.w r1, [r1, #14] - 8004a12: f000 f855 bl 8004ac0 <_lseek_r> - 8004a16: 1c43 adds r3, r0, #1 - 8004a18: 89a3 ldrh r3, [r4, #12] - 8004a1a: bf15 itete ne - 8004a1c: 6560 strne r0, [r4, #84] ; 0x54 - 8004a1e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 - 8004a22: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 - 8004a26: 81a3 strheq r3, [r4, #12] - 8004a28: bf18 it ne - 8004a2a: 81a3 strhne r3, [r4, #12] - 8004a2c: bd10 pop {r4, pc} - -08004a2e <__sclose>: - 8004a2e: f9b1 100e ldrsh.w r1, [r1, #14] - 8004a32: f000 b813 b.w 8004a5c <_close_r> - ... - -08004a38 <_write_r>: - 8004a38: b538 push {r3, r4, r5, lr} - 8004a3a: 4d07 ldr r5, [pc, #28] ; (8004a58 <_write_r+0x20>) - 8004a3c: 4604 mov r4, r0 - 8004a3e: 4608 mov r0, r1 - 8004a40: 4611 mov r1, r2 - 8004a42: 2200 movs r2, #0 - 8004a44: 602a str r2, [r5, #0] - 8004a46: 461a mov r2, r3 - 8004a48: f7fd fa9d bl 8001f86 <_write> - 8004a4c: 1c43 adds r3, r0, #1 - 8004a4e: d102 bne.n 8004a56 <_write_r+0x1e> - 8004a50: 682b ldr r3, [r5, #0] - 8004a52: b103 cbz r3, 8004a56 <_write_r+0x1e> - 8004a54: 6023 str r3, [r4, #0] - 8004a56: bd38 pop {r3, r4, r5, pc} - 8004a58: 200027a8 .word 0x200027a8 - -08004a5c <_close_r>: - 8004a5c: b538 push {r3, r4, r5, lr} - 8004a5e: 4d06 ldr r5, [pc, #24] ; (8004a78 <_close_r+0x1c>) - 8004a60: 2300 movs r3, #0 - 8004a62: 4604 mov r4, r0 - 8004a64: 4608 mov r0, r1 - 8004a66: 602b str r3, [r5, #0] - 8004a68: f7fd faa9 bl 8001fbe <_close> - 8004a6c: 1c43 adds r3, r0, #1 - 8004a6e: d102 bne.n 8004a76 <_close_r+0x1a> - 8004a70: 682b ldr r3, [r5, #0] - 8004a72: b103 cbz r3, 8004a76 <_close_r+0x1a> - 8004a74: 6023 str r3, [r4, #0] - 8004a76: bd38 pop {r3, r4, r5, pc} - 8004a78: 200027a8 .word 0x200027a8 - -08004a7c <_fstat_r>: - 8004a7c: b538 push {r3, r4, r5, lr} - 8004a7e: 4d07 ldr r5, [pc, #28] ; (8004a9c <_fstat_r+0x20>) - 8004a80: 2300 movs r3, #0 - 8004a82: 4604 mov r4, r0 - 8004a84: 4608 mov r0, r1 - 8004a86: 4611 mov r1, r2 - 8004a88: 602b str r3, [r5, #0] - 8004a8a: f7fd faa4 bl 8001fd6 <_fstat> - 8004a8e: 1c43 adds r3, r0, #1 - 8004a90: d102 bne.n 8004a98 <_fstat_r+0x1c> - 8004a92: 682b ldr r3, [r5, #0] - 8004a94: b103 cbz r3, 8004a98 <_fstat_r+0x1c> - 8004a96: 6023 str r3, [r4, #0] - 8004a98: bd38 pop {r3, r4, r5, pc} - 8004a9a: bf00 nop - 8004a9c: 200027a8 .word 0x200027a8 - -08004aa0 <_isatty_r>: - 8004aa0: b538 push {r3, r4, r5, lr} - 8004aa2: 4d06 ldr r5, [pc, #24] ; (8004abc <_isatty_r+0x1c>) - 8004aa4: 2300 movs r3, #0 - 8004aa6: 4604 mov r4, r0 - 8004aa8: 4608 mov r0, r1 - 8004aaa: 602b str r3, [r5, #0] - 8004aac: f7fd faa3 bl 8001ff6 <_isatty> - 8004ab0: 1c43 adds r3, r0, #1 - 8004ab2: d102 bne.n 8004aba <_isatty_r+0x1a> - 8004ab4: 682b ldr r3, [r5, #0] - 8004ab6: b103 cbz r3, 8004aba <_isatty_r+0x1a> - 8004ab8: 6023 str r3, [r4, #0] - 8004aba: bd38 pop {r3, r4, r5, pc} - 8004abc: 200027a8 .word 0x200027a8 - -08004ac0 <_lseek_r>: - 8004ac0: b538 push {r3, r4, r5, lr} - 8004ac2: 4d07 ldr r5, [pc, #28] ; (8004ae0 <_lseek_r+0x20>) - 8004ac4: 4604 mov r4, r0 - 8004ac6: 4608 mov r0, r1 - 8004ac8: 4611 mov r1, r2 - 8004aca: 2200 movs r2, #0 - 8004acc: 602a str r2, [r5, #0] - 8004ace: 461a mov r2, r3 - 8004ad0: f7fd fa9c bl 800200c <_lseek> - 8004ad4: 1c43 adds r3, r0, #1 - 8004ad6: d102 bne.n 8004ade <_lseek_r+0x1e> - 8004ad8: 682b ldr r3, [r5, #0] - 8004ada: b103 cbz r3, 8004ade <_lseek_r+0x1e> - 8004adc: 6023 str r3, [r4, #0] - 8004ade: bd38 pop {r3, r4, r5, pc} - 8004ae0: 200027a8 .word 0x200027a8 - -08004ae4 <_read_r>: - 8004ae4: b538 push {r3, r4, r5, lr} - 8004ae6: 4d07 ldr r5, [pc, #28] ; (8004b04 <_read_r+0x20>) - 8004ae8: 4604 mov r4, r0 - 8004aea: 4608 mov r0, r1 - 8004aec: 4611 mov r1, r2 - 8004aee: 2200 movs r2, #0 - 8004af0: 602a str r2, [r5, #0] - 8004af2: 461a mov r2, r3 - 8004af4: f7fd fa2a bl 8001f4c <_read> - 8004af8: 1c43 adds r3, r0, #1 - 8004afa: d102 bne.n 8004b02 <_read_r+0x1e> - 8004afc: 682b ldr r3, [r5, #0] - 8004afe: b103 cbz r3, 8004b02 <_read_r+0x1e> - 8004b00: 6023 str r3, [r4, #0] - 8004b02: bd38 pop {r3, r4, r5, pc} - 8004b04: 200027a8 .word 0x200027a8 - -08004b08 <_init>: - 8004b08: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004b0a: bf00 nop - 8004b0c: bcf8 pop {r3, r4, r5, r6, r7} - 8004b0e: bc08 pop {r3} - 8004b10: 469e mov lr, r3 - 8004b12: 4770 bx lr - -08004b14 <_fini>: - 8004b14: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004b16: bf00 nop - 8004b18: bcf8 pop {r3, r4, r5, r6, r7} - 8004b1a: bc08 pop {r3} - 8004b1c: 469e mov lr, r3 - 8004b1e: 4770 bx lr diff --git a/Software/Flapy Bird/Debug/Flapy Bird.map b/Software/Flapy Bird/Debug/Flapy Bird.map deleted file mode 100644 index 6bc5603..0000000 --- a/Software/Flapy Bird/Debug/Flapy Bird.map +++ /dev/null @@ -1,3905 +0,0 @@ -Archive member included to satisfy reference by file (symbol) - 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c:/st/stm32cubeide_1.8.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (__libc_init_array) -c:/st/stm32cubeide_1.8.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(lib_a-memset.o) - c:/st/stm32cubeide_1.8.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (memset) 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Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - --include ../makefile.init - -RM := rm -rf - -# All of the sources participating in the build are defined here --include sources.mk --include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk --include Core/Startup/subdir.mk --include Core/Src/subdir.mk --include objects.mk - -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(S_DEPS)),) --include $(S_DEPS) -endif -ifneq ($(strip $(S_UPPER_DEPS)),) --include $(S_UPPER_DEPS) -endif -ifneq ($(strip $(C_DEPS)),) --include $(C_DEPS) -endif -endif - --include ../makefile.defs - -OPTIONAL_TOOL_DEPS := \ -$(wildcard ../makefile.defs) \ -$(wildcard ../makefile.init) \ -$(wildcard ../makefile.targets) \ - - -BUILD_ARTIFACT_NAME := Flapy Bird -BUILD_ARTIFACT_EXTENSION := elf -BUILD_ARTIFACT_PREFIX := -BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) - -# Add inputs and outputs from these tool invocations to the build variables -EXECUTABLES += \ -Flapy\ Bird.elf \ - -MAP_FILES += \ -Flapy\ Bird.map \ - -SIZE_OUTPUT += \ -default.size.stdout \ - -OBJDUMP_LIST += \ -Flapy\ Bird.list \ - - -# All Target -all: main-build - -# Main-build Target -main-build: Flapy\ Bird.elf secondary-outputs - -# Tool invocations -Flapy\ Bird.elf Flapy\ Bird.map: $(OBJS) $(USER_OBJS) C:\Users\jj\Desktop\Flapy\ Bird\STM32F407VGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) - arm-none-eabi-gcc -o "Flapy Bird.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"C:\Users\jj\Desktop\Flapy Bird\STM32F407VGTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="Flapy Bird.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group - @echo 'Finished building target: $@' - @echo ' ' - -default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) - arm-none-eabi-size $(EXECUTABLES) - @echo 'Finished building: $@' - @echo ' ' - -Flapy\ Bird.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) - arm-none-eabi-objdump -h -S $(EXECUTABLES) > "Flapy Bird.list" - @echo 'Finished building: $@' - @echo ' ' - -# Other Targets -clean: - -$(RM) Flapy\ Bird.elf Flapy\ Bird.list Flapy\ Bird.map Flapy\\ Bird.elf default.size.stdout - -@echo ' ' - -secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) - -fail-specified-linker-script-missing: - @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' - @exit 2 - -warn-no-linker-script-specified: - @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' - -.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified - --include ../makefile.targets diff --git a/Software/Flapy Bird/Debug/objects.list b/Software/Flapy Bird/Debug/objects.list deleted file mode 100644 index 38d0ec0..0000000 --- a/Software/Flapy Bird/Debug/objects.list +++ /dev/null @@ -1,25 +0,0 @@ -"./Core/Src/main.o" -"./Core/Src/ssd1289.o" -"./Core/Src/stm32f4xx_hal_msp.o" -"./Core/Src/stm32f4xx_it.o" -"./Core/Src/syscalls.o" -"./Core/Src/sysmem.o" -"./Core/Src/system_stm32f4xx.o" -"./Core/Src/xpt2046.o" -"./Core/Startup/startup_stm32f407vgtx.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" -"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" diff --git a/Software/Flapy Bird/Debug/objects.mk b/Software/Flapy Bird/Debug/objects.mk deleted file mode 100644 index e423e31..0000000 --- a/Software/Flapy Bird/Debug/objects.mk +++ /dev/null @@ -1,9 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - -USER_OBJS := - -LIBS := - diff --git a/Software/Flapy Bird/Debug/sources.mk b/Software/Flapy Bird/Debug/sources.mk deleted file mode 100644 index bbe77a8..0000000 --- a/Software/Flapy Bird/Debug/sources.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -# Toolchain: GNU Tools for STM32 (10.3-2021.10) -################################################################################ - -ELF_SRCS := -OBJ_SRCS := -S_SRCS := -C_SRCS := -S_UPPER_SRCS := -O_SRCS := -SIZE_OUTPUT := -OBJDUMP_LIST := -SU_FILES := -EXECUTABLES := -OBJS := -MAP_FILES := -S_DEPS := -S_UPPER_DEPS := -C_DEPS := - -# Every subdirectory with source files must be described here -SUBDIRS := \ -Core/Src \ -Core/Startup \ -Drivers/STM32F4xx_HAL_Driver/Src \ - diff --git a/Software/Flapy Bird/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/Software/Flapy Bird/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h deleted file mode 100644 index 874659c..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h +++ /dev/null @@ -1,15607 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f407xx.h - * @author MCD Application Team - * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32f407xx - * @{ - */ - -#ifndef __STM32F407xx_H -#define __STM32F407xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - RNG_IRQn = 80, /*!< RNG global Interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -} IRQn_Type; -/* Legacy define */ -#define HASH_RNG_IRQn RNG_IRQn - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1; - __IO uint32_t MACDBGR; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - - - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ - uint32_t RESERVED1; /*!< Reserved, 0x78 */ - uint32_t RESERVED2; /*!< Reserved, 0x7C */ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED3; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank2_3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ - __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @brief USB_OTG_Core_Registers - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ - __IO uint32_t CID; /*!< User ID Register 03Ch */ - uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ - __IO uint32_t DCTL; /*!< dev Control Register 804h */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ - uint32_t Reserved0C; /*!< Reserved 80Ch */ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ - uint32_t Reserved20; /*!< Reserved 820h */ - uint32_t Reserved9; /*!< Reserved 824h */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ - __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask 840h */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ -} USB_OTG_DeviceTypeDef; - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ - uint32_t Reserved40C; /*!< Reserved 40Ch */ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ - __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ - __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ - __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ - __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ - __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ - uint32_t Reserved[2]; /*!< Reserved */ -} USB_OTG_HostChannelTypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ -#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */ -#define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ -#define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define CCMDATARAM_END 0x1000FFFFUL /*!< CCM data RAM end address */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) -#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) -/* Legacy define */ -#define ADC_BASE ADC123_COMMON_BASE -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) -#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) -#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL) -#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) - - -/*!< Debug MCU registers base address */ -#define DBGMCU_BASE 0xE0042000UL -/*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE 0x40040000UL -#define USB_OTG_FS_PERIPH_BASE 0x50000000UL - -#define USB_OTG_GLOBAL_BASE 0x000UL -#define USB_OTG_DEVICE_BASE 0x800UL -#define USB_OTG_IN_ENDPOINT_BASE 0x900UL -#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL -#define USB_OTG_EP_REG_SIZE 0x20UL -#define USB_OTG_HOST_BASE 0x400UL -#define USB_OTG_HOST_PORT_BASE 0x440UL -#define USB_OTG_HOST_CHANNEL_BASE 0x500UL -#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL -#define USB_OTG_PCGCCTL_BASE 0xE00UL -#define USB_OTG_FIFO_BASE 0x1000UL -#define USB_OTG_FIFO_SIZE 0x1000UL - -#define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ -#define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */ -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC1 ((DAC_TypeDef *) DAC_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) -/* Legacy define */ -#define ADC ADC123_COMMON -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ -/** - * @} - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) - */ -#define ADC_MULTIMODE_SUPPORT /*!>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_armclang.h b/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 162a400..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1869 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_compiler.h b/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 94212eb..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,266 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_gcc.h b/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 2d9db15..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,2085 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.4 - * @date 09. April 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_iccarm.h b/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_iccarm.h deleted file mode 100644 index 11c4af0..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_iccarm.h +++ /dev/null @@ -1,935 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.7 - * @date 19. June 2018 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_version.h b/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_version.h deleted file mode 100644 index 660f612..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mbl.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 251e4ed..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1918 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 22. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mml.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 3a3148e..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2927 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 06. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0.h deleted file mode 100644 index f929bba..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,949 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 28. May 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0plus.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 424011a..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1083 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 28. May 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm1.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm1.h deleted file mode 100644 index 0ed678e..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm1.h +++ /dev/null @@ -1,976 +0,0 @@ -/**************************************************************************//** - * @file core_cm1.h - * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 23. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM1_H_GENERIC -#define __CORE_CM1_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M1 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM1 definitions */ -#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ - __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (1U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM1_H_DEPENDANT -#define __CORE_CM1_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM1_REV - #define __CM1_REV 0x0100U - #warning "__CM1_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ - -#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M1 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm23.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm23.h deleted file mode 100644 index acbc5df..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,1993 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 22. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm3.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm3.h deleted file mode 100644 index 74bff64..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1941 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm33.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm33.h deleted file mode 100644 index 6cd2db7..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,3002 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 06. July 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm4.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm4.h deleted file mode 100644 index 7d56873..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2129 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm7.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm7.h deleted file mode 100644 index a14dc62..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2671 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 04. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc000.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc000.h deleted file mode 100644 index 9b67c92..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1022 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 28. May 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc300.h b/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc300.h deleted file mode 100644 index 3e8a471..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1915 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.6 - * @date 04. June 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv7.h b/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index 0142203..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,270 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if non-shareable) or 010b (if shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv8.h b/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv8.h deleted file mode 100644 index 62571da..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/mpu_armv8.h +++ /dev/null @@ -1,333 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Msk) | \ - ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/Software/Flapy Bird/Drivers/CMSIS/Include/tz_context.h b/Software/Flapy Bird/Drivers/CMSIS/Include/tz_context.h deleted file mode 100644 index 0d09749..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/Software/Flapy Bird/Drivers/CMSIS/LICENSE.txt b/Software/Flapy Bird/Drivers/CMSIS/LICENSE.txt deleted file mode 100644 index 8dada3e..0000000 --- a/Software/Flapy Bird/Drivers/CMSIS/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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934f1f9..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,4014 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_HAL_LEGACY -#define STM32_HAL_LEGACY - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) -#define CRYP_DATATYPE_32B CRYP_NO_SWAP -#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP -#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP -#define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 - -#if defined(STM32H7) -#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT -#endif /* STM32H7 */ - -#if defined(STM32U5) -#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES -#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES -#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 -#endif /* STM32U5 */ - -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -#if defined(STM32U5) -#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE -#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE -#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#if defined(STM32C0) -#else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -#endif -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) -#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL -#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL -#endif - -#if defined(STM32U5) -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 -#endif - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) -#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID -#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID -#endif - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - -#if defined(STM32L4) - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif - -#endif /* STM32L4 */ - -#if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 -#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM -#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM - -#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM -#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM -#endif - -#if defined(STM32H7) - -#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - -#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX -#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 -#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT - -#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT -#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT - -#endif /* STM32H7 */ - -#if defined(STM32U5) -#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) || defined(STM32C0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else -#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE -#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE -#endif -#if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL -#endif /* STM32H7 */ -#if defined(STM32U5) -#define OB_USER_nRST_STOP OB_USER_NRST_STOP -#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY -#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW -#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 -#define OB_USER_nBOOT0 OB_USER_NBOOT0 -#define OB_nBOOT0_RESET OB_NBOOT0_RESET -#define OB_nBOOT0_SET OB_NBOOT0_SET -#endif /* STM32U5 */ - -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) -#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE -#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE -#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET -#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -#if defined(STM32G4) - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster -#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD -#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD -#endif /* STM32G4 */ - -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32H7) -#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 -#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 -#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 -#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 -#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 -#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 - -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ - defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) -#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS -#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS -#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ -#endif /* STM32H7 */ - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ - -#if defined(STM32L1) -#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 - -#if defined(STM32U5) -#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 */ -#if defined(STM32U5) -#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP -#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose - * @{ - */ -#if defined(STM32U5) -#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE - -#if defined(STM32G4) -#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig -#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable -#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable -#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset -#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A -#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B -#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL -#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL -#endif /* STM32G4 */ - -#if defined(STM32H7) -#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 - -#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 -#endif /* STM32H7 */ - -#if defined(STM32F3) -/** @brief Constants defining available sources associated to external events. - */ -#define HRTIM_EVENTSRC_1 (0x00000000U) -#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) -#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) -#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) - -/** @brief Constants defining the DLL calibration periods (in micro seconds) - */ -#define HRTIM_CALIBRATIONRATE_7300 0x00000000U -#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) -#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) -#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - -#endif /* STM32F3 */ -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue -/** - * @} - */ - -#if defined(STM32U5) -#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF -#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF -#define LPTIM_CHANNEL_ALL 0x00000000U -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) -#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID -#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID -#endif - -#if defined(STM32L4) || defined(STM32L5) -#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER -#elif defined(STM32G4) -#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED -#endif - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS - -#if defined(STM32H7) -#define I2S_IT_TXE I2S_IT_TXP -#define I2S_IT_RXNE I2S_IT_RXP - -#define I2S_FLAG_TXE I2S_FLAG_TXP -#define I2S_FLAG_RXNE I2S_FLAG_RXP -#endif - -#if defined(STM32F7) -#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -#if defined(STM32F7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ - -#if defined(STM32H7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT -#endif /* STM32H7 */ - -#if defined(STM32F7) || defined(STM32H7) -#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 -#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 -#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -#if defined(STM32H7) - -#define SPI_FLAG_TXE SPI_FLAG_TXP -#define SPI_FLAG_RXNE SPI_FLAG_RXP - -#define SPI_IT_TXE SPI_IT_TXP -#define SPI_IT_RXNE SPI_IT_RXP - -#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET -#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET -#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET -#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -#if defined(STM32L0) -#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO -#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO -#endif - -#if defined(STM32F3) -#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE -#endif - -#if defined(STM32H7) -#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 -#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 -#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 -#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 -#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 -#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 -#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 -#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 -#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 -#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 -#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 -#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 -#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 -#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 -#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 -#endif - -#if defined(STM32U5) || defined(STM32MP2) -#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS -#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK -#endif -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) || defined(STM32U5) -/** @defgroup DMA2D_Aliases DMA2D API Aliases - * @{ - */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort - for compatibility with legacy code */ -/** - * @} - */ - -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose - * @{ - */ - -#if defined(STM32U5) -#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr -#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT -#endif /* STM32U5 */ - -/** - * @} - */ - -#if !defined(STM32F2) -/** @defgroup HASH_alias HASH API alias - * @{ - */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ -/** - * - * @} - */ -#endif /* STM32F2 */ -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY - -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) - -#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt -#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End -#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT -#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT - -#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt -#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End -#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT -#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT - -#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt -#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End -#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT -#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT - -#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt -#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End -#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT -#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT - -#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) -#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode -#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode -#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode -#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode -#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT -#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT -#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT -#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA -#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA -#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA -#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ - -#if defined(STM32F4) -#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT -#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT -#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT -#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT -#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA -#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA -#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA -#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA -#endif /* STM32F4 */ -/** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ - -#if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler -#endif -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - -#if defined (STM32U5) -#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP -#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP -#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP -#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP -#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP -#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP -#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP -#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP -#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP -#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP -#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP -#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP -#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP - -#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP -#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP -#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP - -#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP -#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP -#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP -#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP -#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP -#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP -#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP -#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP -#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP -#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP -#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP -#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP -#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP -#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP - -#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP - -#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP -#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP -#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP -#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP -#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP -#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP -#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP -#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP -#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP -#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP -#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP -#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP -#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP -#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP - -#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP -#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP -#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP -#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP -#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP -#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP -#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP -#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP - -#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY -#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY -#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY - -#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN -#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN -#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN -#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN -#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN - -#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK -#endif - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) -#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro -#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT -#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback -#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent -#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT -#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#if defined(STM32H7) -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 -#else -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#endif /* STM32H7 */ -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -#if defined(STM32H7) -#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET - -#if defined(STM32H7) -#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE -#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE - -#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ -#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ - - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED -#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED -#endif - -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET - -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32L1) -#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#endif /* STM32L1 */ - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 -#if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL -#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE -#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE -#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE -#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE -#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE -#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE -#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE -#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE -#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE -#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK -#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 -#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 -#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 -#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE -#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE -#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE -#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE -#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG -#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE -#endif /* STM32U5 */ - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32C0) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) -#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE -#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE -#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE - -#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV -#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV -#endif - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) || defined(STM32L5) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) -#define USART_OVERSAMPLING_16 0x00000000U -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 - -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) -#endif /* STM32F0 || STM32F3 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop -#endif -/** - * @} - */ - -/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif /* STM32L4 || STM32F4 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32F7) -#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE -#endif /* STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_HAL_LEGACY */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h deleted file mode 100644 index f7eb847..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ /dev/null @@ -1,297 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_H -#define __STM32F4xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_conf.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -/** @defgroup HAL_TICK_FREQ Tick Frequency - * @{ - */ -typedef enum -{ - HAL_TICK_FREQ_10HZ = 100U, - HAL_TICK_FREQ_100HZ = 10U, - HAL_TICK_FREQ_1KHZ = 1U, - HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ -} HAL_TickFreqTypeDef; -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - -#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - -/** @brief Main Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) - -/** @brief System Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ - SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ - }while(0); - -/** @brief Embedded SRAM mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ - }while(0); - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) -/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ - }while(0); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ - }while(0); - -/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ - }while(0); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable - * @{ - */ -/** @brief SYSCFG Break Lockup lock - * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ - }while(0) -/** - * @} - */ - -/** @defgroup PVD_Lock_Enable PVD Lock - * @{ - */ -/** @brief SYSCFG Break PVD lock - * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register - * @note The selected configuration is locked and can be unlocked by system reset - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ - SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ - }while(0) -/** - * @} - */ -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ - ((FREQ) == HAL_TICK_FREQ_100HZ) || \ - ((FREQ) == HAL_TICK_FREQ_1KHZ)) -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Variables - * @{ - */ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern HAL_TickFreqTypeDef uwTickFreq; -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions - * @{ - */ -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and Configuration functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); -HAL_TickFreqTypeDef HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -void HAL_EnableCompensationCell(void); -void HAL_DisableCompensationCell(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -void HAL_EnableMemorySwappingBank(void); -void HAL_DisableMemorySwappingBank(void); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_H */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h deleted file mode 100644 index fdc96b5..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ /dev/null @@ -1,407 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CORTEX_H -#define __STM32F4xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types Cortex Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1U) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U -#define SYSTICK_CLKSOURCE_HCLK 0x00000004U - -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U -#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk -#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk -#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) - -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); - -#if (__MPU_PRESENT == 1U) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1U) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CORTEX_H */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h deleted file mode 100644 index f9bbec2..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_DEF -#define __STM32F4xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" -#include "Legacy/stm32_hal_legacy.h" -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ - -#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0U) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) - -#if (USE_RTOS == 1U) - /* Reserved for future use */ - #error "USE_RTOS should be 0 in the current HAL release" -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0U) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0U) -#endif /* USE_RTOS */ - -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif - #ifndef __packed - #define __packed __attribute__((packed)) - #endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END -#define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler V5*/ -#define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -/* ARM Compiler V4/V5 and V6 - -------------------------- - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) -/* ARM V4/V5 and V6 & GNU Compiler - ------------------------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F4xx_HAL_DEF */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h deleted file mode 100644 index 7ff3836..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h +++ /dev/null @@ -1,802 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_DMA_H -#define __STM32F4xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @brief DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_Channel_selection */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_Priority_level */ - - uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. - This parameter can be a value of @ref DMA_FIFO_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected stream */ - - uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_FIFO_threshold_level */ - - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ - HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ - HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ - HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Stream_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - - void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ - - uint32_t StreamIndex; /*!< DMA Stream Index */ - -}DMA_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @brief DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ -#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ -#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ -#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Channel_selection DMA Channel selection - * @brief DMA channel selection - * @{ - */ -#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ -#if defined (DMA_SxCR_CHSEL_3) -#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ -#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ -#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ -#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ -#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ -#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ -#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ -#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ -#endif /* DMA_SxCR_CHSEL_3 */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @brief DMA data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @brief DMA peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @brief DMA memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @brief DMA peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @brief DMA memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @brief DMA mode - * @{ - */ -#define DMA_NORMAL 0x00000000U /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ -#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @brief DMA priority levels - * @{ - */ -#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode - * @brief DMA FIFO direct mode - * @{ - */ -#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level - * @brief DMA FIFO level - * @{ - */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ -#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ -#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ -#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ -/** - * @} - */ - -/** @defgroup DMA_Memory_burst DMA Memory burst - * @brief DMA memory burst - * @{ - */ -#define DMA_MBURST_SINGLE 0x00000000U -#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) -#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) -#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) -/** - * @} - */ - -/** @defgroup DMA_Peripheral_burst DMA Peripheral burst - * @brief DMA peripheral burst - * @{ - */ -#define DMA_PBURST_SINGLE 0x00000000U -#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) -#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) -#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) -/** - * @} - */ - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @brief DMA interrupts definition - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) -#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) -#define DMA_IT_FE 0x00000080U -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @brief DMA flag definitions - * @{ - */ -#define DMA_FLAG_FEIF0_4 0x00000001U -#define DMA_FLAG_DMEIF0_4 0x00000004U -#define DMA_FLAG_TEIF0_4 0x00000008U -#define DMA_FLAG_HTIF0_4 0x00000010U -#define DMA_FLAG_TCIF0_4 0x00000020U -#define DMA_FLAG_FEIF1_5 0x00000040U -#define DMA_FLAG_DMEIF1_5 0x00000100U -#define DMA_FLAG_TEIF1_5 0x00000200U -#define DMA_FLAG_HTIF1_5 0x00000400U -#define DMA_FLAG_TCIF1_5 0x00000800U -#define DMA_FLAG_FEIF2_6 0x00010000U -#define DMA_FLAG_DMEIF2_6 0x00040000U -#define DMA_FLAG_TEIF2_6 0x00080000U -#define DMA_FLAG_HTIF2_6 0x00100000U -#define DMA_FLAG_TCIF2_6 0x00200000U -#define DMA_FLAG_FEIF3_7 0x00400000U -#define DMA_FLAG_DMEIF3_7 0x01000000U -#define DMA_FLAG_TEIF3_7 0x02000000U -#define DMA_FLAG_HTIF3_7 0x04000000U -#define DMA_FLAG_TCIF3_7 0x08000000U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @brief Reset DMA handle state - * @param __HANDLE__ specifies the DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__ DMA handle - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) - -/** - * @brief Enable the specified DMA Stream. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) - -/** - * @brief Disable the specified DMA Stream. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) - -/* Interrupt & Flag management */ - -/** - * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ - DMA_FLAG_TCIF3_7) - -/** - * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ - DMA_FLAG_HTIF3_7) - -/** - * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ - DMA_FLAG_TEIF3_7) - -/** - * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__ DMA handle - * @retval The specified FIFO error flag index. - */ -#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ - DMA_FLAG_FEIF3_7) - -/** - * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__ DMA handle - * @retval The specified direct mode error flag index. - */ -#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ - DMA_FLAG_DMEIF3_7) - -/** - * @brief Get the DMA Stream pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) - -/** - * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) - -/** - * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) - -/** - * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) - -/** - * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval The state of DMA_IT. - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ - ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ - ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) - -/** - * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__ DMA handle - * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__ DMA handle - * - * @retval The number of remaining data units in the current DMA Stream transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) - - -/* Include DMA HAL Extension module */ -#include "stm32f4xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @brief DMA Exported functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/** - * @} - */ -/* Private Constants -------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros - * @{ - */ -#if defined (DMA_SxCR_CHSEL_3) -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7) || \ - ((CHANNEL) == DMA_CHANNEL_8) || \ - ((CHANNEL) == DMA_CHANNEL_9) || \ - ((CHANNEL) == DMA_CHANNEL_10)|| \ - ((CHANNEL) == DMA_CHANNEL_11)|| \ - ((CHANNEL) == DMA_CHANNEL_12)|| \ - ((CHANNEL) == DMA_CHANNEL_13)|| \ - ((CHANNEL) == DMA_CHANNEL_14)|| \ - ((CHANNEL) == DMA_CHANNEL_15)) -#else -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7)) -#endif /* DMA_SxCR_CHSEL_3 */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR) || \ - ((MODE) == DMA_PFCTRL)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ - ((STATE) == DMA_FIFOMODE_ENABLE)) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ - ((BURST) == DMA_MBURST_INC4) || \ - ((BURST) == DMA_MBURST_INC8) || \ - ((BURST) == DMA_MBURST_INC16)) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ - ((BURST) == DMA_PBURST_INC4) || \ - ((BURST) == DMA_PBURST_INC8) || \ - ((BURST) == DMA_PBURST_INC16)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_DMA_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h deleted file mode 100644 index 9858c74..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_DMA_EX_H -#define __STM32F4xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @brief DMAEx Exported types - * @{ - */ - -/** - * @brief HAL DMA Memory definition - */ -typedef enum -{ - MEMORY0 = 0x00U, /*!< Memory 0 */ - MEMORY1 = 0x01U /*!< Memory 1 */ -}HAL_DMA_MemoryTypeDef; - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @brief DMAEx Exported functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); - -/** - * @} - */ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Functions DMAEx Private Functions - * @brief DMAEx Private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_HAL_DMA_EX_H*/ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h deleted file mode 100644 index b18a228..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h +++ /dev/null @@ -1,366 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_exti.h - * @author MCD Application Team - * @brief Header file of EXTI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS.Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32f4xx_HAL_EXTI_H -#define STM32f4xx_HAL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup EXTI EXTI - * @brief EXTI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Types EXTI Exported Types - * @{ - */ -typedef enum -{ - HAL_EXTI_COMMON_CB_ID = 0x00U -} EXTI_CallbackIDTypeDef; - -/** - * @brief EXTI Handle structure definition - */ -typedef struct -{ - uint32_t Line; /*!< Exti line number */ - void (* PendingCallback)(void); /*!< Exti pending callback */ -} EXTI_HandleTypeDef; - -/** - * @brief EXTI Configuration structure definition - */ -typedef struct -{ - uint32_t Line; /*!< The Exti line to be configured. This parameter - can be a value of @ref EXTI_Line */ - uint32_t Mode; /*!< The Exit Mode to be configured for a core. - This parameter can be a combination of @ref EXTI_Mode */ - uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter - can be a value of @ref EXTI_Trigger */ - uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. - This parameter is only possible for line 0 to 15. It - can be a value of @ref EXTI_GPIOSel */ -} EXTI_ConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_Line EXTI Line - * @{ - */ -#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ -#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ -#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ -#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ -#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ -#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ -#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ -#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ -#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ -#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ -#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ -#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ -#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ -#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ -#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ -#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ -#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#if defined(EXTI_IMR_IM18) -#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#else -#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ -#endif /* EXTI_IMR_IM18 */ -#if defined(EXTI_IMR_IM19) -#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#else -#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ -#endif /* EXTI_IMR_IM19 */ -#if defined(EXTI_IMR_IM20) -#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#else -#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ -#endif /* EXTI_IMR_IM20 */ -#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ -#if defined(EXTI_IMR_IM23) -#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ -#endif /* EXTI_IMR_IM23 */ - -/** - * @} - */ - -/** @defgroup EXTI_Mode EXTI Mode - * @{ - */ -#define EXTI_MODE_NONE 0x00000000u -#define EXTI_MODE_INTERRUPT 0x00000001u -#define EXTI_MODE_EVENT 0x00000002u -/** - * @} - */ - -/** @defgroup EXTI_Trigger EXTI Trigger - * @{ - */ - -#define EXTI_TRIGGER_NONE 0x00000000u -#define EXTI_TRIGGER_RISING 0x00000001u -#define EXTI_TRIGGER_FALLING 0x00000002u -#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) -/** - * @} - */ - -/** @defgroup EXTI_GPIOSel EXTI GPIOSel - * @brief - * @{ - */ -#define EXTI_GPIOA 0x00000000u -#define EXTI_GPIOB 0x00000001u -#define EXTI_GPIOC 0x00000002u -#if defined (GPIOD) -#define EXTI_GPIOD 0x00000003u -#endif /* GPIOD */ -#if defined (GPIOE) -#define EXTI_GPIOE 0x00000004u -#endif /* GPIOE */ -#if defined (GPIOF) -#define EXTI_GPIOF 0x00000005u -#endif /* GPIOF */ -#if defined (GPIOG) -#define EXTI_GPIOG 0x00000006u -#endif /* GPIOG */ -#if defined (GPIOH) -#define EXTI_GPIOH 0x00000007u -#endif /* GPIOH */ -#if defined (GPIOI) -#define EXTI_GPIOI 0x00000008u -#endif /* GPIOI */ -#if defined (GPIOJ) -#define EXTI_GPIOJ 0x00000009u -#endif /* GPIOJ */ -#if defined (GPIOK) -#define EXTI_GPIOK 0x0000000Au -#endif /* GPIOK */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -/** - * @brief EXTI Line property definition - */ -#define EXTI_PROPERTY_SHIFT 24u -#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) -#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) - -/** - * @brief EXTI bit usage - */ -#define EXTI_PIN_MASK 0x0000001Fu - -/** - * @brief EXTI Mask for interrupt & event mode - */ -#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) - -/** - * @brief EXTI Mask for trigger possibilities - */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) - -/** - * @brief EXTI Line number - */ -#if defined(EXTI_IMR_IM23) -#define EXTI_LINE_NB 24UL -#else -#define EXTI_LINE_NB 23UL -#endif /* EXTI_IMR_IM23 */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Macros EXTI Private Macros - * @{ - */ -#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) - -#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) - -#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) - -#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) - -#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) - -#if !defined (GPIOD) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOH)) -#elif !defined (GPIOE) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOH)) -#elif !defined (GPIOF) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOH)) -#elif !defined (GPIOI) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH)) -#elif !defined (GPIOJ) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI)) -#else -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI) || \ - ((__PORT__) == EXTI_GPIOJ) || \ - ((__PORT__) == EXTI_GPIOK)) -#endif /* GPIOD */ - -#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Functions EXTI Exported Functions - * @brief EXTI Exported Functions - * @{ - */ - -/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions - * @brief Configuration functions - * @{ - */ -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32f4xx_HAL_EXTI_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h deleted file mode 100644 index 26d789e..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h +++ /dev/null @@ -1,425 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_FLASH_H -#define __STM32F4xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_SECTERASE, - FLASH_PROC_MASSERASE, - FLASH_PROC_PROGRAM -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ - - __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ - - __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/ - - __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/ - - __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/ - - __IO uint32_t Address; /*Internal variable to save address selected for program*/ - - HAL_LockTypeDef Lock; /* FLASH locking object */ - - __IO uint32_t ErrorCode; /* FLASH error code */ - -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ -/** @defgroup FLASH_Error_Code FLASH Error Code - * @brief FLASH Error Code - * @{ - */ -#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ -#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ -#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ -#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ -#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */ -/** - * @} - */ - -/** @defgroup FLASH_Flag_definition FLASH Flag definition - * @brief Flag definition - * @{ - */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ -#if defined(FLASH_SR_RDERR) -#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ -#endif /* FLASH_SR_RDERR */ -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -/** - * @} - */ - -/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition - * @brief FLASH Interrupt definition - * @{ - */ -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE 0x00000000U -#define FLASH_PSIZE_HALF_WORD 0x00000100U -#define FLASH_PSIZE_WORD 0x00000200U -#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U -#define CR_PSIZE_MASK 0xFFFFFCFFU -/** - * @} - */ - -/** @defgroup FLASH_Keys FLASH Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 0x45670123U -#define FLASH_KEY2 0xCDEF89ABU -#define FLASH_OPT_KEY1 0x08192A3BU -#define FLASH_OPT_KEY2 0x4C5D6E7FU -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency - * The value of this parameter depend on device used within the same series - * @retval none - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) - -/** - * @brief Enable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) - -/** - * @brief Disable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) - -/** - * @brief Enable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) - -/** - * @brief Disable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) - -/** - * @brief Resets the FLASH instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ - FLASH->ACR &= ~FLASH_ACR_ICRST; \ - }while(0U) - -/** - * @brief Resets the FLASH data Cache. - * @note This function must be used only when the data Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ - FLASH->ACR &= ~FLASH_ACR_DCRST; \ - }while(0U) -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flags to check. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) - -/** - * @brief Clear the specified FLASH flags. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) - * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) -/** - * @} - */ - -/* Include FLASH HAL Extension module */ -#include "stm32f4xx_hal_flash_ex.h" -#include "stm32f4xx_hal_flash_ramfunc.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* Program operation functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -uint32_t HAL_FLASH_GetError(void); -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ - -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ - -/** - * @brief ACR register byte 0 (Bits[7:0]) base address - */ -#define ACR_BYTE0_ADDRESS 0x40023C00U -/** - * @brief OPTCR register byte 0 (Bits[7:0]) base address - */ -#define OPTCR_BYTE0_ADDRESS 0x40023C14U -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS 0x40023C15U -/** - * @brief OPTCR register byte 2 (Bits[23:16]) base address - */ -#define OPTCR_BYTE2_ADDRESS 0x40023C16U -/** - * @brief OPTCR register byte 3 (Bits[31:24]) base address - */ -#define OPTCR_BYTE3_ADDRESS 0x40023C17U - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters - * @{ - */ -#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ - ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_FLASH_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h deleted file mode 100644 index 1cf8c45..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h +++ /dev/null @@ -1,1063 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of FLASH HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_FLASH_EX_H -#define __STM32F4xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or sector Erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ - - uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled - This parameter must be a value of @ref FLASHEx_Sectors */ - - uint32_t NbSectors; /*!< Number of sectors to be erased. - This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ - - uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism - This parameter must be a value of @ref FLASHEx_Voltage_Range */ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ - - uint32_t WRPState; /*!< Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ - - uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. - The value of this parameter depend on device used within the same series */ - - uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. - This parameter must be a value of @ref FLASHEx_Banks */ - - uint32_t RDPLevel; /*!< Set the read protection level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - - uint32_t BORLevel; /*!< Set the BOR Level. - This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - - uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ - -} FLASH_OBProgramInitTypeDef; - -/** - * @brief FLASH Advanced Option Bytes Program structure definition - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured for extension. - This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ - - uint32_t PCROPState; /*!< PCROP activation or deactivation. - This parameter can be a value of @ref FLASHEx_PCROP_State */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\ - STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. - This parameter must be a value of @ref FLASHEx_Banks */ - - uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ - - uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ - - uint8_t BootConfig; /*!< Specifies Option bytes for boot config. - This parameter can be a value of @ref FLASHEx_Dual_Boot */ - -#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -}FLASH_AdvOBProgramInitTypeDef; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || - STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Type_Erase FLASH Type Erase - * @{ - */ -#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */ -#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */ -/** - * @} - */ - -/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range - * @{ - */ -#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */ -#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */ -#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */ -#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */ -/** - * @} - */ - -/** @defgroup FLASHEx_WRP_State FLASH WRP State - * @{ - */ -#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ -#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Type FLASH Option Type - * @{ - */ -#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection - * @{ - */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) -#define OB_RDP_LEVEL_1 ((uint8_t)0x55) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 - it s no more possible to go back to level 1 or 0 */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP - * @{ - */ -#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -/** - * @} - */ - - -/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY - * @{ - */ -#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -/** - * @} - */ - -/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -/** - * @} - */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup FLASHEx_PCROP_State FLASH PCROP State - * @{ - */ -#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */ -#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */ -/** - * @} - */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ - STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type - * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */ -#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -#define OPTIONBYTE_PCROP 0x00000001U /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ - (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) - -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F413xx) || defined(STM32F423xx) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F413xx || STM32F423xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F401xC) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F401xC */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ - defined(STM32F412Rx) || defined(STM32F412Cx) -#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F413xx) || defined(STM32F423xx) -#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F413xx || STM32F423xx */ - -#if defined(STM32F401xC) -#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F401xC */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ - defined(STM32F412Rx) || defined(STM32F412Cx) -#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ - STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASH Private Functions - * @{ - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); -void FLASH_FlushCaches(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_FLASH_EX_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h deleted file mode 100644 index 05917ec..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash_ramfunc.h - * @author MCD Application Team - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_RAMFUNC_H -#define __STM32F4xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_RAMFUNC_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 - * @{ - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h deleted file mode 100644 index 5f3d749..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_GPIO_H -#define __STM32F4xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_pins_define GPIO pins define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0x00WX00YZ - * - W : EXTI trigger detection on 3 bits - * - X : EXTI mode (IT or Event) on 2 bits - * - Y : Output type (Push Pull or Open Drain) on 1 bit - * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits - * @{ - */ -#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ - -/** - * @} - */ - -/** @defgroup GPIO_speed_define GPIO speed define - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ -/** - * @} - */ - - /** @defgroup GPIO_pull_define GPIO pull define - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ -#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/** - * @} - */ - -/* Include GPIO HAL Extension module */ -#include "stm32f4xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ -#define GPIO_MODE_Pos 0U -#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) -#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) -#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) -#define MODE_AF (0x2UL << GPIO_MODE_Pos) -#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) -#define OUTPUT_TYPE_Pos 4U -#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) -#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) -#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) -#define EXTI_MODE_Pos 16U -#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) -#define EXTI_IT (0x1UL << EXTI_MODE_Pos) -#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) -#define TRIGGER_MODE_Pos 20U -#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) -#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) -#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_GPIO_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h deleted file mode 100644 index 5e0b7cc..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h +++ /dev/null @@ -1,1590 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_GPIO_EX_H -#define __STM32F4xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection - * @{ - */ - -/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ -#if defined(STM32F429xx) || defined(STM32F439xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F429xx || STM32F439xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ -/** @brief GPIO_Legacy - */ -#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F427xx || STM32F437xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ -#if defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F407xx || STM32F417xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F405xx || STM32F415xx */ - -/*----------------------------------------------------------------------------*/ - -/*---------------------------------------- STM32F401xx------------------------*/ -#if defined(STM32F401xC) || defined(STM32F401xE) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ - - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F401xC || STM32F401xE */ -/*----------------------------------------------------------------------------*/ - -/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ -#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ -#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ -#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -/*----------------------------------------------------------------------------*/ - -/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ -#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */ -#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ -#define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ -#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ -#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ -#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ -#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F413xx || STM32F423xx */ - -/*---------------------------------------- STM32F411xx------------------------*/ -#if defined(STM32F411xE) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F411xE */ - -/*---------------------------------------- STM32F410xx------------------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#if defined(STM32F410Cx) || defined(STM32F410Rx) -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#endif /* STM32F410Cx || STM32F410Rx */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ -#if defined(STM32F410Cx) || defined(STM32F410Rx) -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#endif /* STM32F410Cx || STM32F410Rx */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -/*---------------------------------------- STM32F446xx -----------------------*/ -#if defined(STM32F446xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ -#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ -#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#endif /* STM32F446xx */ -/*----------------------------------------------------------------------------*/ - -/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ -#if defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ -#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#endif /* STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros - * @{ - */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions - * @{ - */ -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Constants GPIO Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Macros GPIO Private Macros - * @{ - */ -/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index - * @{ - */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U :\ - ((__GPIOx__) == (GPIOI))? 8U :\ - ((__GPIOx__) == (GPIOJ))? 9U : 10U) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ - -#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) -#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) -#endif /* STM32F412Vx */ -#if defined(STM32F412Rx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U : 7U) -#endif /* STM32F412Rx */ -#if defined(STM32F412Cx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) -#endif /* STM32F412Cx */ - -/** - * @} - */ - -/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function - * @{ - */ -/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ -#if defined(STM32F429xx) || defined(STM32F439xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF14_LTDC)) - -#endif /* STM32F429xx || STM32F439xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1)) - -#endif /* STM32F427xx || STM32F437xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ -#if defined(STM32F407xx) || defined(STM32F417xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) - -#endif /* STM32F407xx || STM32F417xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \ - ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) - -#endif /* STM32F405xx || STM32F415xx */ - -/*----------------------------------------------------------------------------*/ - -/*---------------------------------------- STM32F401xx------------------------*/ -#if defined(STM32F401xC) || defined(STM32F401xE) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \ - ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \ - ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT)) -#endif /* STM32F401xC || STM32F401xE */ -/*----------------------------------------------------------------------------*/ -/*---------------------------------------- STM32F410xx------------------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -/*---------------------------------------- STM32F411xx------------------------*/ -#if defined(STM32F411xE) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ - ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) - -#endif /* STM32F411xE */ -/*----------------------------------------------------------------------------*/ - -/*----------------------------------------------- STM32F446xx ----------------*/ -#if defined(STM32F446xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \ - ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ - ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI)) - -#endif /* STM32F446xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------------------------------- STM32F469xx/STM32F479xx --------*/ -#if defined(STM32F469xx) || defined(STM32F479xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ - ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \ - ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI)) - -#endif /* STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) -#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U)) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ -/*----------------------------------------------------------------------------*/ - -/*------------------STM32F413xx/STM32F423xx-----------------------------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) -#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U)) -#endif /* STM32F413xx || STM32F423xx */ -/*----------------------------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_GPIO_EX_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h deleted file mode 100644 index d97f255..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ /dev/null @@ -1,427 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_PWR_H -#define __STM32F4xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins - * @{ - */ -#define PWR_WAKEUP_PIN1 0x00000100U -/** - * @} - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage - (Compare internally to VREFINT) */ -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON 0x00000000U -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR -#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) - -/** - * @brief Enable the PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable the PVD EXTI Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ - }while(0U) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * This parameter can be: - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ - }while(0U) - -/** - * @brief checks whether the specified PVD Exti interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD Exti flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generates a Software interrupt on PVD EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) - -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32f4xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -/* PVD configuration */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes entry */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -/* Power PVD IRQ Handler */ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); - -/* Cortex System Control functions *******************************************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PWR_Private_Constants PWR Private Constants - * @{ - */ - -/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line - * @{ - */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ -/** - * @} - */ - -/** @defgroup PWR_register_alias_address PWR Register alias address - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define PWR_CR_OFFSET 0x00U -#define PWR_CSR_OFFSET 0x04U -#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) -#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) -/** - * @} - */ - -/** @defgroup PWR_CR_register_alias PWR CR Register alias address - * @{ - */ -/* --- CR Register ---*/ -/* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER PWR_CR_DBP_Pos -#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) - -/* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos -#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) - -/* Alias word address of VOS bit */ -#define VOS_BIT_NUMBER PWR_CR_VOS_Pos -#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) -/** - * @} - */ - -/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address - * @{ - */ -/* --- CSR Register ---*/ -/* Alias word address of EWUP bit */ -#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos -#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) -/** - * @} - */ - -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters - * @{ - */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F4xx_HAL_PWR_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h deleted file mode 100644 index 57fd4d9..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h +++ /dev/null @@ -1,340 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_PWR_EX_H -#define __STM32F4xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - -/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode - * @{ - */ -#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS -#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) -/** - * @} - */ - -/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag - * @{ - */ -#define PWR_FLAG_ODRDY PWR_CSR_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY -/** - * @} - */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale - * @{ - */ -#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ -#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ -#else -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to - 180 MHz by activating the over-drive mode. */ -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to - 168 MHz by activating the over-drive mode. */ -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ -/** - * @} - */ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins - * @{ - */ -#define PWR_WAKEUP_PIN2 0x00000080U -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define PWR_WAKEUP_PIN3 0x00000040U -#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ - STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -/** - * @} - */ -#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || - STM32F413xx || STM32F423xx */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ - -#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__ specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ - UNUSED(tmpreg); \ - } while(0U) -#else -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__ specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macros to enable or disable the Over drive mode. - * @note These macros can be used only for STM32F42xx/STM3243xx devices. - */ -#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE) -#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) - -/** @brief Macros to enable or disable the Over drive switching. - * @note These macros can be used only for STM32F42xx/STM3243xx devices. - */ -#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) -#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) - -/** @brief Macros to enable or disable the Under drive mode. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - */ -#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) -#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN)) - -/** @brief Check PWR flag is set or not. - * @note These macros can be used only for STM32F42xx/STM3243xx devices. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switching is ready - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the Under-Drive Ready flag. - * @note These macros can be used only for STM32F42xx/STM3243xx devices. - */ -#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ -void HAL_PWREx_EnableFlashPowerDown(void); -void HAL_PWREx_DisableFlashPowerDown(void); -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ - defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -void HAL_PWREx_EnableMainRegulatorLowVoltage(void); -void HAL_PWREx_DisableMainRegulatorLowVoltage(void); -void HAL_PWREx_EnableLowRegulatorLowVoltage(void); -void HAL_PWREx_DisableLowRegulatorLowVoltage(void); -#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\ - STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PWREx_Private_Constants PWREx Private Constants - * @{ - */ - -/** @defgroup PWREx_register_alias_address PWREx Register alias address - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -/* --- CR Register ---*/ -/* Alias word address of FPDS bit */ -#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos -#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) - -/* Alias word address of ODEN bit */ -#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos -#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) - -/* Alias word address of ODSWEN bit */ -#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos -#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) - -/* Alias word address of MRLVDS bit */ -#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos -#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) - -/* Alias word address of LPLVDS bit */ -#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos -#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) - - /** - * @} - */ - -/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address - * @{ - */ -/* --- CSR Register ---*/ -/* Alias word address of BRE bit */ -#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos -#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWREx_Private_Macros PWREx Private Macros - * @{ - */ - -/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters - * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) -#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#else -#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ - -#if defined(STM32F446xx) -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) -#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3)) -#else -#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) -#endif /* STM32F446xx */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F4xx_HAL_PWR_EX_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h deleted file mode 100644 index dcf5814..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ /dev/null @@ -1,1459 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RCC_H -#define __STM32F4xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/* Include RCC HAL Extended module */ -/* (include on top of file since RCC structures are defined in extended file) */ -#include "stm32f4xx_hal_rcc_ex.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ -}RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -}RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE 0x00000000U -#define RCC_OSCILLATORTYPE_HSE 0x00000001U -#define RCC_OSCILLATORTYPE_HSI 0x00000002U -#define RCC_OSCILLATORTYPE_LSE 0x00000004U -#define RCC_OSCILLATORTYPE_LSI 0x00000008U -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF 0x00000000U -#define RCC_HSE_ON RCC_CR_HSEON -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF 0x00000000U -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF ((uint8_t)0x00) -#define RCC_HSI_ON ((uint8_t)0x01) - -#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF ((uint8_t)0x00) -#define RCC_LSI_ON ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE ((uint8_t)0x00) -#define RCC_PLL_OFF ((uint8_t)0x01) -#define RCC_PLL_ON ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider - * @{ - */ -#define RCC_PLLP_DIV2 0x00000002U -#define RCC_PLLP_DIV4 0x00000004U -#define RCC_PLLP_DIV6 0x00000006U -#define RCC_PLLP_DIV8 0x00000008U -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI -#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK 0x00000001U -#define RCC_CLOCKTYPE_HCLK 0x00000002U -#define RCC_CLOCKTYPE_PCLK1 0x00000004U -#define RCC_CLOCKTYPE_PCLK2 0x00000008U -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for - * STM32F446xx devices. - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL -#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for - * STM32F446xx devices. - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U -#define RCC_RTCCLKSOURCE_LSE 0x00000100U -#define RCC_RTCCLKSOURCE_LSI 0x00000200U -#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U -#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U -#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U -#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U -#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U -#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U -#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U -#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U -#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U -#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U -#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U -#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U -#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U -#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U -#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U -#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U -#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U -#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U -#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U -#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U -#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U -#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U -#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U -#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U -#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U -#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U -#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U -#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U -#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U -#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U -#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U -/** - * @} - */ - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 0x00000000U -#define RCC_MCO2 0x00000001U -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_HSI 0x00000000U -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 -#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 0x00000000U -#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 -#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: 0XXYYYYYb - * - YYYYY : Flag position in the register - * - 0XX : Register index - * - 01: CR register - * - 10: BDCR register - * - 11: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x41) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) -#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) - -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) - -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) - -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) -#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) -#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) - -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) -#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) -/** - * @} - */ - -/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) - -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -/** - * @} - */ - -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wake-up from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) -#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICalibrationValue__ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ - RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) -#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. - * User should request a transition to HSE Off first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator. - * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0U) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * User should request a transition to LSE Off first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator. - * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0U) -/** - * @} - */ - -/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) -#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by - * a Power On Reset (POR). - * @param __RTCCLKSource__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wake-up source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) - -#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ - RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ - } while(0U) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** - * @brief Get the RTC and HSE clock divider (RTCPRE). - * @retval Returned value can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() - */ -#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) -#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) -#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) - -/** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) - -/** @brief Macro to configure the PLL multiplication factor. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - */ -#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ -/** - * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This - * parameter is available only for STM32F446xx devices. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter - * is available only for STM32F446xx devices. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -/** @brief Macro to configure the MCO1 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - */ -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @brief Macro to configure the MCO2 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have - * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). - */ -#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. - * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. - * @arg RCC_FLAG_PINRST: Pin reset. - * @arg RCC_FLAG_PORRST: POR/PDR reset. - * @arg RCC_FLAG_SFTRST: Software reset. - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. - * @arg RCC_FLAG_LPWRRST: Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define RCC_FLAG_MASK ((uint8_t)0x1FU) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ - -/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register --- */ -/* Alias word address of HSION bit */ -#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) -#define RCC_HSION_BIT_NUMBER 0x00U -#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) -/* Alias word address of CSSON bit */ -#define RCC_CSSON_BIT_NUMBER 0x13U -#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) -/* Alias word address of PLLON bit */ -#define RCC_PLLON_BIT_NUMBER 0x18U -#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) - -/* --- BDCR Register --- */ -/* Alias word address of RTCEN bit */ -#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) -#define RCC_RTCEN_BIT_NUMBER 0x0FU -#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) -/* Alias word address of BDRST bit */ -#define RCC_BDRST_BIT_NUMBER 0x10U -#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) - -/* --- CSR Register --- */ -/* Alias word address of LSION bit */ -#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) -#define RCC_LSION_BIT_NUMBER 0x00U -#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS 0x40023802U - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) - -/* BDCR register base address */ -#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) - -#define RCC_DBP_TIMEOUT_VALUE 2U -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT - -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE 2U /* 2 ms */ -#define LSI_TIMEOUT_VALUE 2U /* 2 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) - -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_BYPASS)) - -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) - -#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) - -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) - -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) - -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) - -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) - -#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) - -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ - ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ - ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ - ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ - ((HCLK) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) - -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ - ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ - ((PCLK) == RCC_HCLK_DIV16)) - -#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_5)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_RCC_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h deleted file mode 100644 index 909a717..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ /dev/null @@ -1,7111 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RCC_EX_H -#define __STM32F4xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 - except for STM32F411xE devices where the Min_Data = 192 */ - - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) - uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. - This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx - and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. - This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -}RCC_PLLInitTypeDef; - -#if defined(STM32F446xx) -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ - uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ - - uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. - This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ - - uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S */ -}RCC_PLLI2SInitTypeDef; - -/** - * @brief PLLSAI Clock structure definition - */ -typedef struct -{ - uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ - - uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. - This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ - - uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLSAI is selected as Clock Source SAI */ -}RCC_PLLSAIInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ - - uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLSAI is selected as Clock Source SAI */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - - uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ - - uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. - This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. - This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ - - uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ - - uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. - This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ - - uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. - This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. - This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F446xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. - This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ - - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. - This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ - uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ - - uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S */ -}RCC_PLLI2SInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S */ - -#if defined(STM32F413xx) || defined(STM32F423xx) - uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLL is selected as Clock Source SAI */ - - uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ -#endif /* STM32F413xx || STM32F423xx */ - - uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ - - uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. - This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. - This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ - - uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ - - uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. - This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. - This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ - - uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. - This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ - -#if defined(STM32F413xx) || defined(STM32F423xx) - uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. - This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ - - uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. - This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ - - uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ -#endif /* STM32F413xx || STM32F423xx */ - - uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. - This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ - - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. - This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ -}RCC_PLLI2SInitTypeDef; - -/** - * @brief PLLSAI Clock structure definition - */ -typedef struct -{ - uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ -#if defined(STM32F469xx) || defined(STM32F479xx) - uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. - This parameter is only available in STM32F469xx/STM32F479xx devices. - This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ -#endif /* STM32F469xx || STM32F479xx */ - - uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - - uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ - -}RCC_PLLSAIInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ - - uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLSAI is selected as Clock Source SAI */ - - uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. - This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. - This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ -#if defined(STM32F469xx) || defined(STM32F479xx) - uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. - This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. - This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ -#endif /* STM32F469xx || STM32F479xx */ -}RCC_PeriphCLKInitTypeDef; - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ -#if defined(STM32F411xE) - uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ -#endif /* STM32F411xE */ - - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 - Except for STM32F411xE devices where the Min_Data = 192. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - -}RCC_PLLI2SInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) - uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. - This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ -}RCC_PeriphCLKInitTypeDef; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection - * @{ - */ -/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) -#define RCC_PERIPHCLK_I2S_APB1 0x00000001U -#define RCC_PERIPHCLK_I2S_APB2 0x00000002U -#define RCC_PERIPHCLK_TIM 0x00000004U -#define RCC_PERIPHCLK_RTC 0x00000008U -#define RCC_PERIPHCLK_FMPI2C1 0x00000010U -#define RCC_PERIPHCLK_CLK48 0x00000020U -#define RCC_PERIPHCLK_SDIO 0x00000040U -#define RCC_PERIPHCLK_PLLI2S 0x00000080U -#define RCC_PERIPHCLK_DFSDM1 0x00000100U -#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U -#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ -#if defined(STM32F413xx) || defined(STM32F423xx) -#define RCC_PERIPHCLK_DFSDM2 0x00000400U -#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U -#define RCC_PERIPHCLK_LPTIM1 0x00001000U -#define RCC_PERIPHCLK_SAIA 0x00002000U -#define RCC_PERIPHCLK_SAIB 0x00004000U -#endif /* STM32F413xx || STM32F423xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------- Peripheral Clock source for STM32F410xx ----------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define RCC_PERIPHCLK_I2S 0x00000001U -#define RCC_PERIPHCLK_TIM 0x00000002U -#define RCC_PERIPHCLK_RTC 0x00000004U -#define RCC_PERIPHCLK_FMPI2C1 0x00000008U -#define RCC_PERIPHCLK_LPTIM1 0x00000010U -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -/*----------------------------------------------------------------------------*/ - -/*------------------- Peripheral Clock source for STM32F446xx ----------------*/ -#if defined(STM32F446xx) -#define RCC_PERIPHCLK_I2S_APB1 0x00000001U -#define RCC_PERIPHCLK_I2S_APB2 0x00000002U -#define RCC_PERIPHCLK_SAI1 0x00000004U -#define RCC_PERIPHCLK_SAI2 0x00000008U -#define RCC_PERIPHCLK_TIM 0x00000010U -#define RCC_PERIPHCLK_RTC 0x00000020U -#define RCC_PERIPHCLK_CEC 0x00000040U -#define RCC_PERIPHCLK_FMPI2C1 0x00000080U -#define RCC_PERIPHCLK_CLK48 0x00000100U -#define RCC_PERIPHCLK_SDIO 0x00000200U -#define RCC_PERIPHCLK_SPDIFRX 0x00000400U -#define RCC_PERIPHCLK_PLLI2S 0x00000800U -#endif /* STM32F446xx */ -/*-----------------------------------------------------------------------------*/ - -/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ -#if defined(STM32F469xx) || defined(STM32F479xx) -#define RCC_PERIPHCLK_I2S 0x00000001U -#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U -#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U -#define RCC_PERIPHCLK_LTDC 0x00000008U -#define RCC_PERIPHCLK_TIM 0x00000010U -#define RCC_PERIPHCLK_RTC 0x00000020U -#define RCC_PERIPHCLK_PLLI2S 0x00000040U -#define RCC_PERIPHCLK_CLK48 0x00000080U -#define RCC_PERIPHCLK_SDIO 0x00000100U -#endif /* STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -#define RCC_PERIPHCLK_I2S 0x00000001U -#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U -#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U -#define RCC_PERIPHCLK_LTDC 0x00000008U -#define RCC_PERIPHCLK_TIM 0x00000010U -#define RCC_PERIPHCLK_RTC 0x00000020U -#define RCC_PERIPHCLK_PLLI2S 0x00000040U -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -/*----------------------------------------------------------------------------*/ - -/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -#define RCC_PERIPHCLK_I2S 0x00000001U -#define RCC_PERIPHCLK_RTC 0x00000002U -#define RCC_PERIPHCLK_PLLI2S 0x00000004U -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -#define RCC_PERIPHCLK_TIM 0x00000008U -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ -/*----------------------------------------------------------------------------*/ -/** - * @} - */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ - defined(STM32F479xx) -/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source - * @{ - */ -#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SCLKSOURCE_EXT 0x00000001U -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ - -/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR - * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -#define RCC_PLLSAIDIVR_2 0x00000000U -#define RCC_PLLSAIDIVR_4 0x00010000U -#define RCC_PLLSAIDIVR_8 0x00020000U -#define RCC_PLLSAIDIVR_16 0x00030000U -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) -#define RCC_PLLI2SP_DIV2 0x00000002U -#define RCC_PLLI2SP_DIV4 0x00000004U -#define RCC_PLLI2SP_DIV6 0x00000006U -#define RCC_PLLI2SP_DIV8 0x00000008U -#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ -/** - * @} - */ - -/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define RCC_PLLSAIP_DIV2 0x00000002U -#define RCC_PLLSAIP_DIV4 0x00000004U -#define RCC_PLLSAIP_DIV6 0x00000006U -#define RCC_PLLSAIP_DIV8 0x00000008U -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source - * @{ - */ -#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U -#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U -#define RCC_SAIACLKSOURCE_EXT 0x00200000U -/** - * @} - */ - -/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source - * @{ - */ -#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U -#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U -#define RCC_SAIBCLKSOURCE_EXT 0x00800000U -/** - * @} - */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source - * @{ - */ -#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U -#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) -/** - * @} - */ - -/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source - * @{ - */ -#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U -#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) -/** - * @} - */ - -/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source - * @{ - */ -#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U -#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) -/** - * @} - */ -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F446xx) -/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U -#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) -#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) -#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) -/** - * @} - */ - -/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U -#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) -#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) -#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) -/** - * @} - */ - -/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source - * @{ - */ -#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) -#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) -#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) -/** - * @} - */ - -/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source - * @{ - */ -#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) -#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) -#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) -/** - * @} - */ - -/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source - * @{ - */ -#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) -#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source - * @{ - */ -#define RCC_CECCLKSOURCE_HSI 0x00000000U -#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) -/** - * @} - */ - -/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source - * @{ - */ -#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U -#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) -/** - * @} - */ - -/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source - * @{ - */ -#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U -#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) -/** - * @} - */ - -/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source - * @{ - */ -#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U -#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) -/** - * @} - */ - -#endif /* STM32F446xx */ - -#if defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source - * @{ - */ -#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U -#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) -#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) -#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) -/** - * @} - */ - -/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source - * @{ - */ -#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U -#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) -#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) -#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) -#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) -#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) -/** - * @} - */ - - -/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source - * @{ - */ -#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U -#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source - * @{ - */ -#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U -#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) -/** - * @} - */ - -#endif /* STM32F413xx || STM32F423xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source - * @{ - */ -#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U -#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U -#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source - * @{ - */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U -#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) -/** - * @} - */ - -/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source - * @{ - */ -#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) -#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) -#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) -/** - * @} - */ - -/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source - * @{ - */ -#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) -#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) -#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) -/** - * @} - */ - -/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source - * @{ - */ -#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) -#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source - * @{ - */ -#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U -#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) -/** - * @} - */ - -/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source - * @{ - */ -#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U -#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) -/** - * @} - */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) - -/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source - * @{ - */ -#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U -#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) -#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) -/** - * @} - */ - -/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source - * @{ - */ -#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) -#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) -#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) -#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) -/** - * @} - */ -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection - * @{ - */ -#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) -#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) -/** - * @} - */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ - STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection - * @{ - */ -#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) -#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) -/** - * @} - */ -#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ - STM32F412Rx || STM32F412Cx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source - * @{ - */ -#define RCC_MCO2SOURCE_SYSCLK 0x00000000U -#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 -#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 -#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || - STM32F412Rx || STM32F413xx | STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source - * @{ - */ -#define RCC_MCO2SOURCE_SYSCLK 0x00000000U -#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 -#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 -#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 -/** - * @} - */ -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ -/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) -#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) -#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) -#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) -#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) -#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) -#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) - -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETHMAC_CLK_ENABLE(); \ - __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ - __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0U) -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETH_CLK_DISABLE() do { \ - __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ - __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ - __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0U) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) -#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) - -#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) -#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) - -#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) -#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) -#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) - -#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ - -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - - -/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) -#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) - -#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) - -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) -#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) - -#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) -#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) - -#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) -#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) - -#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) -#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) -#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) - -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) - -#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) -#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) -#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) - -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) - -#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) - -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) - -#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) - -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) -#endif /* STM32F469xx || STM32F479xx */ -/** - * @} - */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#if defined(STM32F407xx)|| defined(STM32F417xx) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETHMAC_CLK_ENABLE(); \ - __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ - __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0U) - -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) -#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) -#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) -#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) -#define __HAL_RCC_ETH_CLK_DISABLE() do { \ - __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ - __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ - __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0U) -#endif /* STM32F407xx || STM32F417xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#if defined(STM32F407xx)|| defined(STM32F417xx) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) -#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) -#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -#endif /* STM32F407xx || STM32F417xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) - -#if defined(STM32F407xx)|| defined(STM32F417xx) -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* STM32F407xx || STM32F417xx */ - -#if defined(STM32F415xx) || defined(STM32F417xx) -#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F415xx || STM32F417xx */ -/** - * @} - */ - - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) - -#if defined(STM32F407xx)|| defined(STM32F417xx) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#endif /* STM32F407xx || STM32F417xx */ - -#if defined(STM32F415xx) || defined(STM32F417xx) -#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) - -#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F415xx || STM32F417xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) -#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) - /** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) - -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) - -#if defined(STM32F407xx)|| defined(STM32F417xx) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* STM32F407xx || STM32F417xx */ - -#if defined(STM32F415xx) || defined(STM32F417xx) -#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) - -#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F415xx || STM32F417xx */ - -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) - -#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) -#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) - -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) - -#if defined(STM32F407xx)|| defined(STM32F417xx) -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* STM32F407xx || STM32F417xx */ - -#if defined(STM32F415xx) || defined(STM32F417xx) -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F415xx || STM32F417xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) -#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) - -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -/** - * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------------- STM32F401xE/STM32F401xC --------------------------*/ -#if defined(STM32F401xC) || defined(STM32F401xE) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) - -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -/** - * @} - */ -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) - -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -/** - * @} - */ -#endif /* STM32F401xC || STM32F401xE*/ -/*----------------------------------------------------------------------------*/ - -/*-------------------------------- STM32F410xx -------------------------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB1) peripheral clock. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) -#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) -#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) - -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @{ - */ -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) -#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) - -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) -#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() -#define __HAL_RCC_AHB2_RELEASE_RESET() -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() -#define __HAL_RCC_AHB3_RELEASE_RESET() -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) -#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) - -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @{ - */ -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) -/** - * @} - */ - -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -/*----------------------------------------------------------------------------*/ - -/*-------------------------------- STM32F411xx -------------------------------*/ -#if defined(STM32F411xE) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @{ - */ -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) - -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) - -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @{ - */ -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) - -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -/** - * @} - */ -#endif /* STM32F411xE */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------------- STM32F446xx -----------------------------*/ -#if defined(STM32F446xx) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) -#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) - -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) - -#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) - -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) - -#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) - -#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) - -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) - -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) - -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) - -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -/** - * @} - */ - -#endif /* STM32F446xx */ -/*----------------------------------------------------------------------------*/ - -/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) - -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F423xx) -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) -#endif /* STM32F423xx */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0U) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F423xx) -#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) -#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) -#endif /* STM32F423xx */ - -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) - -#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) -#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) -#endif /* STM32F413xx || STM32F423xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ -/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) -#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) -#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) -#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) - -#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) - -#if defined(STM32F423xx) -#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) -#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) -#endif /* STM32F423xx */ - -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) - -#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) -#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) - -#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) -#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ -#if defined(STM32F412Cx) -#define __HAL_RCC_AHB3_FORCE_RESET() -#define __HAL_RCC_AHB3_RELEASE_RESET() - -#define __HAL_RCC_FSMC_FORCE_RESET() -#define __HAL_RCC_QSPI_FORCE_RESET() - -#define __HAL_RCC_FSMC_RELEASE_RESET() -#define __HAL_RCC_QSPI_RELEASE_RESET() -#endif /* STM32F412Cx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) -#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) -#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#if defined(STM32F423xx) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) -#endif /* STM32F423xx */ - -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) -/** - * @} - */ - -/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) - -#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ - -/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) -#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) -#endif /* STM32F413xx || STM32F423xx */ - -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) -#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) -#if defined(STM32F413xx) || defined(STM32F423xx) -#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) -#endif /* STM32F413xx || STM32F423xx */ -/** - * @} - */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------------------- PLL Configuration --------------------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * - * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ - STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ - (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ - ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ - ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) -#else -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432 - * Except for STM32F411xE devices where Min_Data = 192. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices - * where frequency is between 192 and 432 MHz. - * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * - * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ - (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ - ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) - #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ -/*----------------------------------------------------------------------------*/ - -/*----------------------------PLLI2S Configuration ---------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - -/** @brief Macros to enable or disable the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) -#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || - STM32F412Rx || STM32F412Cx */ -#if defined(STM32F446xx) -/** @brief Macro to configure the PLLI2S clock multiplication and division factors . - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 1 MHz to limit PLLI2S jitter. - * - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note the PLLI2SP parameter is only available with STM32F446xx Devices - * - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @param __PLLI2SQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ - ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) -#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) -/** @brief Macro to configure the PLLI2S clock multiplication and division factors . - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 1 MHz to limit PLLI2S jitter. - * - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @param __PLLI2SQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) -#else -/** @brief Macro to configure the PLLI2S clock multiplication and division factors . - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API). - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) -#endif /* STM32F446xx */ - -#if defined(STM32F411xE) -/** @brief Macro to configure the PLLI2S clock multiplication and division factors . - * @note This macro must be used only when the PLLI2S is disabled. - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLLI2S jitter. - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between Min_Data = 192 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - */ -#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) -#endif /* STM32F411xE */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx - * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - */ -#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ - ((__PLLI2SQ__) << 24U) |\ - ((__PLLI2SR__) << 28U)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------------------ PLLSAI Configuration ------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is only available with STM32F429x/439x Devices. - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) -#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) - -#if defined(STM32F446xx) -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * - * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 1 MHz to limit PLLI2S jitter. - * @note The PLLSAIM parameter is only used with STM32F446xx Devices - * - * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note the PLLSAIP parameter is only available with STM32F446xx Devices - * - * @param __PLLSAIQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * - * @param __PLLSAIR__ specifies the division factor for LTDC clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ - ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ - ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ - ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) -#endif /* STM32F446xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * - * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. - * This parameter must be a number in the range {2, 4, 6, or 8}. - * - * @param __PLLSAIQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * - * @param __PLLSAIR__ specifies the division factor for LTDC clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ - ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ - ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ - ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * - * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * - * @param __PLLSAIQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * - * @param __PLLSAIR__ specifies the division factor for LTDC clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ - ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ - ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) -/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ - */ -#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) - -/** @brief Macro to configure the SAI clock Divider coming from PLL. - * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLR) / __PLLDivR__ - */ -#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) -#endif /* STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ - */ -#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) - -/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between Min_Data = 1 and Max_Data = 32. - * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * - * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . - * This parameter must be a number between Min_Data = 2 and Max_Data = 16. - * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -/*----------------------------------------------------------------------------*/ - -/*------------------------- Peripheral Clock selection -----------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ - defined(STM32F479xx) -/** @brief Macro to configure the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__ specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. - * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin - * used as I2S clock source. - */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) - - -/** @brief Macro to get the I2S clock source (I2SCLK). - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. - * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin - * used as I2S clock source - */ -#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) -#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - -/** @brief Macro to configure SAI1BlockA clock source selection. - * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block A clock. - */ -#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) - -/** @brief Macro to configure SAI1BlockB clock source selection. - * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block B clock. - * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block B clock. - * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block B clock. - */ -#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F446xx) -/** @brief Macro to configure SAI1 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. - * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. - */ -#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) - -/** @brief Macro to Get SAI1 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. - */ -#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) - -/** @brief Macro to configure SAI2 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. - * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. - */ -#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) - -/** @brief Macro to Get SAI2 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. - */ -#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) - -/** @brief Macro to configure I2S APB1 clock source selection. - * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__ specifies the I2S APB1 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. - * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. - * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) - -/** @brief Macro to Get I2S APB1 clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. - * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. - * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) - -/** @brief Macro to configure I2S APB2 clock source selection. - * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__ specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. - * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. - * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) - -/** @brief Macro to Get I2S APB2 clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. - * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. - * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) - -/** @brief Macro to configure the CEC clock. - * @param __SOURCE__ specifies the CEC clock source. - * This parameter can be one of the following values: - * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - */ -#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the CEC clock. - * @retval The clock source can be one of the following values: - * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - */ -#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) - -/** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__ specifies the FMPI2C1 clock source. - * This parameter can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the FMPI2C1 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) - -/** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__ specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. - */ -#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the CLK48 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. - */ -#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) - -/** @brief Macro to configure the SDIO clock. - * @param __SOURCE__ specifies the SDIO clock source. - * This parameter can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the SDIO clock. - * @retval The clock source can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) - -/** @brief Macro to configure the SPDIFRX clock. - * @param __SOURCE__ specifies the SPDIFRX clock source. - * This parameter can be one of the following values: - * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. - * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. - */ -#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the SPDIFRX clock. - * @retval The clock source can be one of the following values: - * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. - * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. - */ -#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) -#endif /* STM32F446xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) - -/** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__ specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. - */ -#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the CLK48 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. - */ -#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) - -/** @brief Macro to configure the SDIO clock. - * @param __SOURCE__ specifies the SDIO clock source. - * This parameter can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the SDIO clock. - * @retval The clock source can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) - -/** @brief Macro to configure the DSI clock. - * @param __SOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the DSI clock. - * @retval The clock source can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) - -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) - /** @brief Macro to configure the DFSDM1 clock. - * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. - * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. - * @retval None - */ -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. - * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. - */ -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) - -/** @brief Macro to configure DFSDM1 Audio clock source selection. - * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ - STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__ specifies the DFSDM1 Audio clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock - */ -#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) - -/** @brief Macro to Get DFSDM1 Audio clock source selection. - * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ - STM32F413xx/STM32F423xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock - */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) - -#if defined(STM32F413xx) || defined(STM32F423xx) - /** @brief Macro to configure the DFSDM2 clock. - * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. - * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. - * @retval None - */ -#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. - * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. - */ -#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) - -/** @brief Macro to configure DFSDM1 Audio clock source selection. - * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__ specifies the DFSDM2 Audio clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock - */ -#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) - -/** @brief Macro to Get DFSDM2 Audio clock source selection. - * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock - */ -#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) - -/** @brief Macro to configure SAI1BlockA clock source selection. - * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) - -/** @brief Macro to Get SAI1 BlockA clock source selection. - * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. - * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) - -/** @brief Macro to configure SAI1 BlockB clock source selection. - * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) - -/** @brief Macro to Get SAI1 BlockB clock source selection. - * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @retval The clock source can be one of the following values: - * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. - * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) - -/** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the LPTIM1 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) -#endif /* STM32F413xx || STM32F423xx */ - -/** @brief Macro to configure I2S APB1 clock source selection. - * @param __SOURCE__ specifies the I2S APB1 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. - * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. - * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) - -/** @brief Macro to Get I2S APB1 clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. - * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. - * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) - -/** @brief Macro to configure I2S APB2 clock source selection. - * @param __SOURCE__ specifies the I2S APB2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. - * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. - * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) - -/** @brief Macro to Get I2S APB2 clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. - * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. - * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - */ -#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) - -/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). - * @note This macro must be called before enabling the I2S APB clock. - * @param __SOURCE__ specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. - * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin - * used as I2S clock source. - */ -#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) - -/** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__ specifies the FMPI2C1 clock source. - * This parameter can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the FMPI2C1 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) - -/** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__ specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. - */ -#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the CLK48 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. - * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock - */ -#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) - -/** @brief Macro to configure the SDIO clock. - * @param __SOURCE__ specifies the SDIO clock source. - * This parameter can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the SDIO clock. - * @retval The clock source can be one of the following values: - * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. - * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. - */ -#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) - -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** @brief Macro to configure I2S clock source selection. - * @param __SOURCE__ specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. - * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. - */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) - -/** @brief Macro to Get I2S clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. - * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. - */ -#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) - -/** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__ specifies the FMPI2C1 clock source. - * This parameter can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the FMPI2C1 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock - */ -#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) - -/** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) - -/** @brief Macro to Get the LPTIM1 clock. - * @retval The clock source can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** @brief Macro to configure the Timers clocks prescalers - * @note This feature is only available with STM32F429x/439x Devices. - * @param __PRESC__ specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - */ -#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ - STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ - STM32F423xx */ - -/*----------------------------------------------------------------------------*/ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @brief Enable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Disable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) - -/** @brief Clear the PLLSAI RDY interrupt pending bits. - */ -#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) - -/** @brief Check the PLLSAI RDY interrupt has occurred or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Check PLLSAI RDY flag is set or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** @brief Macros to enable or disable the RCC MCO1 feature. - */ -#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) -#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) - -/** @brief Macros to enable or disable the RCC MCO2 feature. - */ -#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) -#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) - -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); - -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -void HAL_RCCEx_SelectLSEMode(uint8_t Mode); -#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -#if defined(RCC_PLLI2S_SUPPORT) -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); -#endif /* RCC_PLLI2S_SUPPORT */ -#if defined(RCC_PLLSAI_SUPPORT) -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); -#endif /* RCC_PLLSAI_SUPPORT */ -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ - -/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -/* --- CR Register ---*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* Alias word address of PLLSAION bit */ -#define RCC_PLLSAION_BIT_NUMBER 0x1CU -#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) - -#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Alias word address of PLLI2SON bit */ -#define RCC_PLLI2SON_BIT_NUMBER 0x1AU -#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || - STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/* --- DCKCFGR Register ---*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ - defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Alias word address of TIMPRE bit */ -#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) -#define RCC_TIMPRE_BIT_NUMBER 0x18U -#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ - STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/* --- CFGR Register ---*/ -#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) -/* Alias word address of I2SSRC bit */ -#define RCC_I2SSRC_BIT_NUMBER 0x17U -#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) - -#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) -/* --- PLLI2SCFGR Register ---*/ -#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) -/* Alias word address of PLLI2SSRC bit */ -#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U -#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) - -#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/* Alias word address of MCO1EN bit */ -#define RCC_MCO1EN_BIT_NUMBER 0x8U -#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) - -/* Alias word address of MCO2EN bit */ -#define RCC_MCO2EN_BIT_NUMBER 0x9U -#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#define PLL_TIMEOUT_VALUE 2U /* 2 ms */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F446xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) -#endif /* STM32F446xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -#if defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) -#endif /* STM32F413xx || STM32F423xx */ - -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) - -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) - -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) - -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) - -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) - -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ - ((VALUE) == RCC_PLLSAIDIVR_4) ||\ - ((VALUE) == RCC_PLLSAIDIVR_8) ||\ - ((VALUE) == RCC_PLLSAIDIVR_16)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) - -#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ - ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) -#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ - ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) - -#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) - -#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) - -#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F446xx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ - ((VALUE) == RCC_PLLI2SP_DIV4) ||\ - ((VALUE) == RCC_PLLI2SP_DIV6) ||\ - ((VALUE) == RCC_PLLI2SP_DIV8)) - -#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) - -#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ - ((VALUE) == RCC_PLLSAIP_DIV4) ||\ - ((VALUE) == RCC_PLLSAIP_DIV6) ||\ - ((VALUE) == RCC_PLLSAIP_DIV8)) - -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) - -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) - -#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) - - #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) - -#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) - -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) - -#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ - ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) - -#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ - ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) - -#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) -#endif /* STM32F446xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ - ((VALUE) == RCC_PLLSAIP_DIV4) ||\ - ((VALUE) == RCC_PLLSAIP_DIV6) ||\ - ((VALUE) == RCC_PLLSAIP_DIV8)) - -#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ - ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) - -#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ - ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) - -#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) - -#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ - ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) - -#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) - -#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ - ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) - -#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) - - #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) - -#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ - ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) - -#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ - ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) - -#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ - ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) - -#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) - -#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) - -#if defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) - -#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ - ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) - -#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) - -#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ - ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) - -#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ - ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ - ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) - -#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) - -#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) - -#endif /* STM32F413xx || STM32F423xx */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ - STM32F412Rx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ - ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_RCC_EX_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h deleted file mode 100644 index 8c81414..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ /dev/null @@ -1,2146 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F4xx_HAL_TIM_H -#define STM32F4xx_HAL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and - Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and - Max_Data = 0xFFFF. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, - ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct -{ - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode - @note When the Master/slave mode is enabled, the effect of - an event on the trigger input (TRGI) is delayed to allow a - perfect synchronization between the current timer and its - slaves (through TRGO). It is not mandatory in case of timer - synchronization mode. */ -} TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct -{ - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -} TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ - - uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ - - uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ - -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -} HAL_TIM_StateTypeDef; - -/** - * @brief TIM Channel States definition - */ -typedef enum -{ - HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ - HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ - HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ -} HAL_TIM_ChannelStateTypeDef; - -/** - * @brief DMA Burst States definition - */ -typedef enum -{ - HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ - HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ - HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ -} HAL_TIM_DMABurstStateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -} HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -typedef struct __TIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ - __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ - void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ - void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ - void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ - void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ - void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ - void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ - void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ - void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ - void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} TIM_HandleTypeDef; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL TIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ -} HAL_TIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ - -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 0x00000000U -#define TIM_DMABASE_CR2 0x00000001U -#define TIM_DMABASE_SMCR 0x00000002U -#define TIM_DMABASE_DIER 0x00000003U -#define TIM_DMABASE_SR 0x00000004U -#define TIM_DMABASE_EGR 0x00000005U -#define TIM_DMABASE_CCMR1 0x00000006U -#define TIM_DMABASE_CCMR2 0x00000007U -#define TIM_DMABASE_CCER 0x00000008U -#define TIM_DMABASE_CNT 0x00000009U -#define TIM_DMABASE_PSC 0x0000000AU -#define TIM_DMABASE_ARR 0x0000000BU -#define TIM_DMABASE_RCR 0x0000000CU -#define TIM_DMABASE_CCR1 0x0000000DU -#define TIM_DMABASE_CCR2 0x0000000EU -#define TIM_DMABASE_CCR3 0x0000000FU -#define TIM_DMABASE_CCR4 0x00000010U -#define TIM_DMABASE_BDTR 0x00000011U -#define TIM_DMABASE_DCR 0x00000012U -#define TIM_DMABASE_DMAR 0x00000013U -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ -#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ -#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ -#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ - -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ -#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ -#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ -#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ -#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ -#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ -#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity - * @{ - */ -#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ -#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ -#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ -#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ -#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ -#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ -#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ -#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ -#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ -#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ -#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ -#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ -#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ -#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ -#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ -#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ -/** - * @} - */ - -/** @defgroup TIM_CC_DMA_Request CCx DMA request selection - * @{ - */ -#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ -#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ -#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ -#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ -#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ -#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ -#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ -#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ -#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ -#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ -#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ -#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ -#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ -#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ -#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ -#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ -#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ -#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ -#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ -#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ -#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ -#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ -#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ -#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ -#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ -#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ -#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ -#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ -#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ -#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ -#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ -#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ -#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ -#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been - * disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ - == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode - * or Encoder mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() - * function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__HANDLE__)->Instance->CCR4)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) - -/** - * @brief Enable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is enabled an active edge on the trigger input acts - * like a compare match on CCx output. Delay to sample the trigger - * input and to activate CCx output is reduced to 3 clock cycles. - * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) - -/** - * @brief Disable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is disabled CCx output behaves normally depending - * on counter and CCRx values even when the trigger is ON. The minimum - * delay to activate CCx output when an active edge occurs on the - * trigger input is 5 clock cycles. - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** @brief Select the Capture/compare DMA request source. - * @param __HANDLE__ specifies the TIM Handle. - * @param __CCDMA__ specifies Capture/compare DMA request source - * This parameter can be one of the following values: - * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event - * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event - * @retval None - */ -#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ - MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR)) - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) - -#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ - (__HANDLE__)->ChannelState[3]) - -#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) - -#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ - (__HANDLE__)->ChannelNState[3]) - -#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32f4xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -void TIM_ResetCallback(TIM_HandleTypeDef *htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F4xx_HAL_TIM_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h deleted file mode 100644 index 39fb500..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ /dev/null @@ -1,354 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F4xx_HAL_TIM_EX_H -#define STM32F4xx_HAL_TIM_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -#if defined (TIM2) -#if defined(TIM8) -#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ -#else -#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ -#endif /* TIM8 */ -#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ -#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ -#endif /* TIM2 */ - -#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */ -#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */ -#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */ -#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */ - -#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */ -#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */ -#if defined(SPDIFRX) -#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */ -#endif /* SPDIFRX*/ - -#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) -#define LPTIM_REMAP_MASK 0x10000000U - -#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */ -#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */ - -#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */ -#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */ - -#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */ -#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */ -#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#if defined(SPDIFRX) -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ - ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ - ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ - (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ - ((TIM_REMAP) == TIM_TIM5_LSI) || \ - ((TIM_REMAP) == TIM_TIM5_LSE) || \ - ((TIM_REMAP) == TIM_TIM5_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ - ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ - ((TIM_REMAP) == TIM_TIM11_HSE)))) -#elif defined(TIM2) -#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ - ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ - ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ - (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ - ((TIM_REMAP) == TIM_TIM5_LSI) || \ - ((TIM_REMAP) == TIM_TIM5_LSE) || \ - ((TIM_REMAP) == TIM_TIM5_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ - ((TIM_REMAP) == TIM_TIM11_HSE))) || \ - (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ - ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ - (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ - ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ - (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ - ((TIM_REMAP) == TIM_TIM9_LPTIM)))) -#elif defined(TIM8) -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ - ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ - ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ - (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ - ((TIM_REMAP) == TIM_TIM5_LSI) || \ - ((TIM_REMAP) == TIM_TIM5_LSE) || \ - ((TIM_REMAP) == TIM_TIM5_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ - ((TIM_REMAP) == TIM_TIM11_HSE)))) -#else -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ - ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ - ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ - (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ - ((TIM_REMAP) == TIM_TIM5_LSI) || \ - ((TIM_REMAP) == TIM_TIM5_LSE) || \ - ((TIM_REMAP) == TIM_TIM5_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ - ((TIM_REMAP) == TIM_TIM11_HSE)))) -#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ -#else -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ - ((TIM_REMAP) == TIM_TIM5_LSI) || \ - ((TIM_REMAP) == TIM_TIM5_LSE) || \ - ((TIM_REMAP) == TIM_TIM5_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ - ((TIM_REMAP) == TIM_TIM11_HSE)))) -#endif /* SPDIFRX */ - -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F4xx_HAL_TIM_EX_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h deleted file mode 100644 index 5083c10..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h +++ /dev/null @@ -1,2105 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_BUS_H -#define __STM32F4xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN -#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN -#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN -#if defined(GPIOD) -#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN -#endif /* GPIOD */ -#if defined(GPIOE) -#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN -#endif /* GPIOE */ -#if defined(GPIOF) -#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN -#endif /* GPIOF */ -#if defined(GPIOG) -#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN -#endif /* GPIOG */ -#if defined(GPIOH) -#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN -#endif /* GPIOH */ -#if defined(GPIOI) -#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN -#endif /* GPIOI */ -#if defined(GPIOJ) -#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN -#endif /* GPIOJ */ -#if defined(GPIOK) -#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN -#endif /* GPIOK */ -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN -#if defined(RCC_AHB1ENR_BKPSRAMEN) -#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN -#endif /* RCC_AHB1ENR_BKPSRAMEN */ -#if defined(RCC_AHB1ENR_CCMDATARAMEN) -#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN -#endif /* RCC_AHB1ENR_CCMDATARAMEN */ -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN -#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN -#if defined(RCC_AHB1ENR_RNGEN) -#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN -#endif /* RCC_AHB1ENR_RNGEN */ -#if defined(DMA2D) -#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN -#endif /* DMA2D */ -#if defined(ETH) -#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN -#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN -#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN -#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN -#endif /* ETH */ -#if defined(USB_OTG_HS) -#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN -#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN -#endif /* USB_OTG_HS */ -#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN -#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN -#if defined(RCC_AHB1LPENR_SRAM2LPEN) -#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN -#endif /* RCC_AHB1LPENR_SRAM2LPEN */ -#if defined(RCC_AHB1LPENR_SRAM3LPEN) -#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN -#endif /* RCC_AHB1LPENR_SRAM3LPEN */ -/** - * @} - */ - -#if defined(RCC_AHB2_SUPPORT) -/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH - * @{ - */ -#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(DCMI) -#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN -#endif /* DCMI */ -#if defined(CRYP) -#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN -#endif /* CRYP */ -#if defined(AES) -#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN -#endif /* AES */ -#if defined(HASH) -#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN -#endif /* HASH */ -#if defined(RCC_AHB2ENR_RNGEN) -#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN -#endif /* RCC_AHB2ENR_RNGEN */ -#if defined(USB_OTG_FS) -#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN -#endif /* USB_OTG_FS */ -/** - * @} - */ -#endif /* RCC_AHB2_SUPPORT */ - -#if defined(RCC_AHB3_SUPPORT) -/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH - * @{ - */ -#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(FSMC_Bank1) -#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN -#endif /* FSMC_Bank1 */ -#if defined(FMC_Bank1) -#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN -#endif /* FMC_Bank1 */ -#if defined(QUADSPI) -#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN -#endif /* QUADSPI */ -/** - * @} - */ -#endif /* RCC_AHB3_SUPPORT */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(TIM2) -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN -#endif /* TIM2 */ -#if defined(TIM3) -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN -#endif /* TIM3 */ -#if defined(TIM4) -#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN -#endif /* TIM4 */ -#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN -#if defined(TIM6) -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN -#endif /* TIM6 */ -#if defined(TIM7) -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN -#endif /* TIM7 */ -#if defined(TIM12) -#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN -#endif /* TIM12 */ -#if defined(TIM13) -#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN -#endif /* TIM13 */ -#if defined(TIM14) -#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN -#endif /* TIM14 */ -#if defined(LPTIM1) -#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN -#endif /* LPTIM1 */ -#if defined(RCC_APB1ENR_RTCAPBEN) -#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN -#endif /* RCC_APB1ENR_RTCAPBEN */ -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN -#if defined(SPI2) -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN -#endif /* SPI2 */ -#if defined(SPI3) -#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN -#endif /* SPI3 */ -#if defined(SPDIFRX) -#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN -#endif /* SPDIFRX */ -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN -#if defined(USART3) -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN -#endif /* USART3 */ -#if defined(UART4) -#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN -#endif /* UART4 */ -#if defined(UART5) -#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN -#endif /* UART5 */ -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN -#if defined(I2C3) -#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN -#endif /* I2C3 */ -#if defined(FMPI2C1) -#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN -#endif /* FMPI2C1 */ -#if defined(CAN1) -#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN -#endif /* CAN1 */ -#if defined(CAN2) -#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN -#endif /* CAN2 */ -#if defined(CAN3) -#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN -#endif /* CAN3 */ -#if defined(CEC) -#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN -#endif /* CEC */ -#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN -#if defined(DAC1) -#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN -#endif /* DAC1 */ -#if defined(UART7) -#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN -#endif /* UART7 */ -#if defined(UART8) -#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN -#endif /* UART8 */ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH - * @{ - */ -#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#if defined(TIM8) -#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN -#endif /* TIM8 */ -#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN -#if defined(USART6) -#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN -#endif /* USART6 */ -#if defined(UART9) -#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN -#endif /* UART9 */ -#if defined(UART10) -#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN -#endif /* UART10 */ -#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN -#if defined(ADC2) -#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN -#endif /* ADC2 */ -#if defined(ADC3) -#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN -#endif /* ADC3 */ -#if defined(SDIO) -#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN -#endif /* SDIO */ -#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#if defined(SPI4) -#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN -#endif /* SPI4 */ -#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN -#if defined(RCC_APB2ENR_EXTITEN) -#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN -#endif /* RCC_APB2ENR_EXTITEN */ -#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN -#if defined(TIM10) -#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN -#endif /* TIM10 */ -#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN -#if defined(SPI5) -#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN -#endif /* SPI5 */ -#if defined(SPI6) -#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN -#endif /* SPI6 */ -#if defined(SAI1) -#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN -#endif /* SAI1 */ -#if defined(SAI2) -#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN -#endif /* SAI2 */ -#if defined(LTDC) -#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN -#endif /* LTDC */ -#if defined(DSI) -#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN -#endif /* DSI */ -#if defined(DFSDM1_Channel0) -#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN -#endif /* DFSDM1_Channel0 */ -#if defined(DFSDM2_Channel0) -#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN -#endif /* DFSDM2_Channel0 */ -#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1ENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Enable AHB1 peripheral clocks in low-power mode - * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB1 peripheral clocks in low-power mode - * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1LPENR, Periphs); -} - -/** - * @} - */ - -#if defined(RCC_AHB2_SUPPORT) -/** @defgroup BUS_LL_EF_AHB2 AHB2 - * @{ - */ - -/** - * @brief Enable AHB2 peripherals clock. - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clock is enabled or not - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB2 peripherals clock. - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2ENR, Periphs); -} - -/** - * @brief Force AHB2 peripherals reset. - * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB2RSTR, Periphs); -} - -/** - * @brief Release AHB2 peripherals reset. - * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2RSTR, Periphs); -} - -/** - * @brief Enable AHB2 peripheral clocks in low-power mode - * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB2 peripheral clocks in low-power mode - * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2LPENR, Periphs); -} - -/** - * @} - */ -#endif /* RCC_AHB2_SUPPORT */ - -#if defined(RCC_AHB3_SUPPORT) -/** @defgroup BUS_LL_EF_AHB3 AHB3 - * @{ - */ - -/** - * @brief Enable AHB3 peripherals clock. - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB3 peripheral clock is enabled or not - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB3 peripherals clock. - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3ENR, Periphs); -} - -/** - * @brief Force AHB3 peripherals reset. - * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Release AHB3 peripherals reset. - * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Enable AHB3 peripheral clocks in low-power mode - * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n - * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n - * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB3 peripheral clocks in low-power mode - * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n - * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n - * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3LPENR, Periphs); -} - -/** - * @} - */ -#endif /* RCC_AHB3_SUPPORT */ - -/** @defgroup BUS_LL_EF_APB1 APB1 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n - * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n - * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n - * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n - * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n - * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n - * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Enable APB1 peripheral clocks in low-power mode - * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable APB1 peripheral clocks in low-power mode - * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1LPENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB2 APB2 - * @{ - */ - -/** - * @brief Enable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n - * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n - * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n - * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n - * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB2 peripheral clock is enabled or not - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n - * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n - * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n - * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n - * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Enable APB2 peripheral clocks in low-power mode - * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable APB2 peripheral clocks in low-power mode - * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2LPENR, Periphs); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_BUS_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h deleted file mode 100644 index d478e13..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ /dev/null @@ -1,637 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick - functions - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) MPU API to configure and enable regions - (MPU services provided only on some devices) - (+) API to access to MCU info (CPUID register) - (+) API to enable fault handler (SHCSR accesses) - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_CORTEX_H -#define __STM32F4xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type - * @{ - */ -#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ -#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ -#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ -/** - * @} - */ - -#if __MPU_PRESENT - -/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control - * @{ - */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ -#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION MPU Region Number - * @{ - */ -#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ -#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ -#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ -#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ -#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ -#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ -#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ -#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size - * @{ - */ -#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges - * @{ - */ -#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ -#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ -#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ -#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ -#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ -#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level - * @{ - */ -#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ -#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ -#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ -#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access - * @{ - */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access - * @{ - */ -#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ -#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access - * @{ - */ -#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ -#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access - * @{ - */ -#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ -#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ -/** - * @} - */ -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_HANDLER HANDLER - * @{ - */ - -/** - * @brief Enable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) -{ - /* Enable the system handler fault */ - SET_BIT(SCB->SHCSR, Fault); -} - -/** - * @brief Disable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) -{ - /* Disable the system handler fault */ - CLEAR_BIT(SCB->SHCSR, Fault); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Constant number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant - * @retval Value should be equal to 0xF for Cortex-M4 devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC24 for Cortex-M4 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -#if __MPU_PRESENT -/** @defgroup CORTEX_LL_EF_MPU MPU - * @{ - */ - -/** - * @brief Enable MPU with input options - * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable - * @param Options This parameter can be one of the following values: - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE - * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI - * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) -{ - /* Enable the MPU*/ - WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); - /* Ensure MPU settings take effects */ - __DSB(); - /* Sequence instruction fetches using update settings */ - __ISB(); -} - -/** - * @brief Disable MPU - * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable - * @retval None - */ -__STATIC_INLINE void LL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - /* Disable MPU*/ - WRITE_REG(MPU->CTRL, 0U); -} - -/** - * @brief Check if MPU is enabled or not - * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) -{ - return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); -} - -/** - * @brief Enable a MPU region - * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Enable the MPU region */ - SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @brief Configure and enable a region - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR ADDR LL_MPU_ConfigRegion\n - * MPU_RASR XN LL_MPU_ConfigRegion\n - * MPU_RASR AP LL_MPU_ConfigRegion\n - * MPU_RASR S LL_MPU_ConfigRegion\n - * MPU_RASR C LL_MPU_ConfigRegion\n - * MPU_RASR B LL_MPU_ConfigRegion\n - * MPU_RASR SIZE LL_MPU_ConfigRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Address Value of region base address - * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B - * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB - * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB - * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB - * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB - * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB - * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS - * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE - * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE - * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Set base address */ - WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); - /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); -} - -/** - * @brief Disable a region - * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n - * MPU_RASR ENABLE LL_MPU_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Disable the MPU region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @} - */ - -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_CORTEX_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h deleted file mode 100644 index 76444fc..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h +++ /dev/null @@ -1,2868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_DMA_H -#define __STM32F4xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ -static const uint8_t STREAM_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) -}; - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Constants DMA Private Constants - * @{ - */ -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Stream - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ - - uint32_t Channel; /*!< Specifies the peripheral channel. - This parameter can be a value of @ref DMA_LL_EC_CHANNEL - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ - - uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. - This parameter can be a value of @ref DMA_LL_FIFOMODE - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected stream - - This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ - - uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ - - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_LL_EC_MBURST - @note The burst mode is possible only if the address Increment mode is enabled. - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ - - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_LL_EC_PBURST - @note The burst mode is possible only if the address Increment mode is enabled. - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_LL_EC_STREAM STREAM - * @{ - */ -#define LL_DMA_STREAM_0 0x00000000U -#define LL_DMA_STREAM_1 0x00000001U -#define LL_DMA_STREAM_2 0x00000002U -#define LL_DMA_STREAM_3 0x00000003U -#define LL_DMA_STREAM_4 0x00000004U -#define LL_DMA_STREAM_5 0x00000005U -#define LL_DMA_STREAM_6 0x00000006U -#define LL_DMA_STREAM_7 0x00000007U -#define LL_DMA_STREAM_ALL 0xFFFF0000U -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION DIRECTION - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE MODE - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ -#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE - * @{ - */ -#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ -#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH PERIPH - * @{ - */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY MEMORY - * @{ - */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE - * @{ - */ -#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ -#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY PRIORITY - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ -#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ -#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ -#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ -#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ -#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ -#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ -#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ -#if defined (DMA_SxCR_CHSEL_3) -#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ -#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ -#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ -#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ -#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ -#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ -#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ -#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */ -#endif /* DMA_SxCR_CHSEL_3 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MBURST MBURST - * @{ - */ -#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ -#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ -#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ -#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PBURST PBURST - * @{ - */ -#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ -#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ -#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ -#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE - * @{ - */ -#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ -#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 - * @{ - */ -#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ -#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ -#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ -#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ -#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ -#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD - * @{ - */ -#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ -#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ -#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ -#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM - * @{ - */ -#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ -#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy - * @{ - */ -/** - * @brief Convert DMAx_Streamy into DMAx - * @param __STREAM_INSTANCE__ DMAx_Streamy - * @retval DMAx - */ -#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ -(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) - -/** - * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y - * @param __STREAM_INSTANCE__ DMAx_Streamy - * @retval LL_DMA_CHANNEL_y - */ -#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ -(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ - LL_DMA_STREAM_7) - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy - * @param __DMA_INSTANCE__ DMAx - * @param __STREAM__ LL_DMA_STREAM_y - * @retval DMAx_Streamy - */ -#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ - DMA2_Stream7) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA stream. - * @rmtoll CR EN LL_DMA_EnableStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); -} - -/** - * @brief Disable DMA stream. - * @rmtoll CR EN LL_DMA_DisableStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); -} - -/** - * @brief Check if DMA stream is enabled or disabled. - * @rmtoll CR EN LL_DMA_IsEnabledStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); -} - -/** - * @brief Configure all parameters linked to DMA transfer. - * @rmtoll CR DIR LL_DMA_ConfigTransfer\n - * CR CIRC LL_DMA_ConfigTransfer\n - * CR PINC LL_DMA_ConfigTransfer\n - * CR MINC LL_DMA_ConfigTransfer\n - * CR PSIZE LL_DMA_ConfigTransfer\n - * CR MSIZE LL_DMA_ConfigTransfer\n - * CR PL LL_DMA_ConfigTransfer\n - * CR PFCTRL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - *@retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, - DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CR DIR LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CR DIR LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); -} - -/** - * @brief Set DMA mode normal, circular or peripheral flow control. - * @rmtoll CR CIRC LL_DMA_SetMode\n - * CR PFCTRL LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_MODE_PFCTRL - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); -} - -/** - * @brief Get DMA mode normal, circular or peripheral flow control. - * @rmtoll CR CIRC LL_DMA_GetMode\n - * CR PFCTRL LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_MODE_PFCTRL - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param IncrementMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_PERIPH_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param IncrementMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); -} - -/** - * @brief Get Memory size. - * @rmtoll CR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); -} - -/** - * @brief Set Peripheral increment offset size. - * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param OffsetSize This parameter can be one of the following values: - * @arg @ref LL_DMA_OFFSETSIZE_PSIZE - * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); -} - -/** - * @brief Get Peripheral increment offset size. - * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_OFFSETSIZE_PSIZE - * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 - */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); -} - -/** - * @brief Set Stream priority level. - * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); -} - -/** - * @brief Get Stream priority level. - * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @rmtoll NDTR NDT LL_DMA_SetDataLength - * @note This action has no effect if - * stream is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param NbData Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @rmtoll NDTR NDT LL_DMA_GetDataLength - * @note Once the stream is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); -} - -/** - * @brief Select Channel number associated to the Stream. - * @rmtoll CR CHSEL LL_DMA_SetChannelSelection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); -} - -/** - * @brief Get the Channel number associated to the Stream. - * @rmtoll CR CHSEL LL_DMA_GetChannelSelection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); -} - -/** - * @brief Set Memory burst transfer configuration. - * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Mburst This parameter can be one of the following values: - * @arg @ref LL_DMA_MBURST_SINGLE - * @arg @ref LL_DMA_MBURST_INC4 - * @arg @ref LL_DMA_MBURST_INC8 - * @arg @ref LL_DMA_MBURST_INC16 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); -} - -/** - * @brief Get Memory burst transfer configuration. - * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MBURST_SINGLE - * @arg @ref LL_DMA_MBURST_INC4 - * @arg @ref LL_DMA_MBURST_INC8 - * @arg @ref LL_DMA_MBURST_INC16 - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); -} - -/** - * @brief Set Peripheral burst transfer configuration. - * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Pburst This parameter can be one of the following values: - * @arg @ref LL_DMA_PBURST_SINGLE - * @arg @ref LL_DMA_PBURST_INC4 - * @arg @ref LL_DMA_PBURST_INC8 - * @arg @ref LL_DMA_PBURST_INC16 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); -} - -/** - * @brief Get Peripheral burst transfer configuration. - * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PBURST_SINGLE - * @arg @ref LL_DMA_PBURST_INC4 - * @arg @ref LL_DMA_PBURST_INC8 - * @arg @ref LL_DMA_PBURST_INC16 - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); -} - -/** - * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. - * @rmtoll CR CT LL_DMA_SetCurrentTargetMem - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param CurrentMemory This parameter can be one of the following values: - * @arg @ref LL_DMA_CURRENTTARGETMEM0 - * @arg @ref LL_DMA_CURRENTTARGETMEM1 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); -} - -/** - * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. - * @rmtoll CR CT LL_DMA_GetCurrentTargetMem - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_CURRENTTARGETMEM0 - * @arg @ref LL_DMA_CURRENTTARGETMEM1 - */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); -} - -/** - * @brief Enable the double buffer mode. - * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); -} - -/** - * @brief Disable the double buffer mode. - * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); -} - -/** - * @brief Get FIFO status. - * @rmtoll FCR FS LL_DMA_GetFIFOStatus - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_FIFOSTATUS_0_25 - * @arg @ref LL_DMA_FIFOSTATUS_25_50 - * @arg @ref LL_DMA_FIFOSTATUS_50_75 - * @arg @ref LL_DMA_FIFOSTATUS_75_100 - * @arg @ref LL_DMA_FIFOSTATUS_EMPTY - * @arg @ref LL_DMA_FIFOSTATUS_FULL - */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); -} - -/** - * @brief Disable Fifo mode. - * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); -} - -/** - * @brief Enable Fifo mode. - * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); -} - -/** - * @brief Select FIFO threshold. - * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); -} - -/** - * @brief Get FIFO threshold. - * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); -} - -/** - * @brief Configure the FIFO . - * @rmtoll FCR FTH LL_DMA_ConfigFifo\n - * FCR DMDIS LL_DMA_ConfigFifo - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param FifoMode This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOMODE_ENABLE - * @arg @ref LL_DMA_FIFOMODE_DISABLE - * @param FifoThreshold This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA stream is enabled. - * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n - * PAR PA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param SrcAddress Between 0 to 0xFFFFFFFF - * @param DstAddress Between 0 to 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @rmtoll PAR PA LL_DMA_SetPeriphAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param PeriphAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); -} - -/** - * @brief Get the Memory address. - * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); -} - -/** - * @brief Get the Peripheral address. - * @rmtoll PAR PA LL_DMA_GetPeriphAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); - } - -/** - * @brief Get the Memory to Memory Source address. - * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) - { - return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); - } - -/** - * @brief Get the Memory to Memory Destination address. - * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); -} - -/** - * @brief Set Memory 1 address (used in case of Double buffer mode). - * @rmtoll M1AR M1A LL_DMA_SetMemory1Address - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Address Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); -} - -/** - * @brief Get Memory 1 address (used in case of Double buffer mode). - * @rmtoll M1AR M1A LL_DMA_GetMemory1Address - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Stream 0 half transfer flag. - * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); -} - -/** - * @brief Get Stream 1 half transfer flag. - * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); -} - -/** - * @brief Get Stream 2 half transfer flag. - * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); -} - -/** - * @brief Get Stream 3 half transfer flag. - * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); -} - -/** - * @brief Get Stream 4 half transfer flag. - * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); -} - -/** - * @brief Get Stream 5 half transfer flag. - * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); -} - -/** - * @brief Get Stream 6 half transfer flag. - * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); -} - -/** - * @brief Get Stream 7 half transfer flag. - * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); -} - -/** - * @brief Get Stream 0 transfer complete flag. - * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); -} - -/** - * @brief Get Stream 1 transfer complete flag. - * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); -} - -/** - * @brief Get Stream 2 transfer complete flag. - * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); -} - -/** - * @brief Get Stream 3 transfer complete flag. - * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); -} - -/** - * @brief Get Stream 4 transfer complete flag. - * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); -} - -/** - * @brief Get Stream 5 transfer complete flag. - * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); -} - -/** - * @brief Get Stream 6 transfer complete flag. - * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); -} - -/** - * @brief Get Stream 7 transfer complete flag. - * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); -} - -/** - * @brief Get Stream 0 transfer error flag. - * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); -} - -/** - * @brief Get Stream 1 transfer error flag. - * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); -} - -/** - * @brief Get Stream 2 transfer error flag. - * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); -} - -/** - * @brief Get Stream 3 transfer error flag. - * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); -} - -/** - * @brief Get Stream 4 transfer error flag. - * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); -} - -/** - * @brief Get Stream 5 transfer error flag. - * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); -} - -/** - * @brief Get Stream 6 transfer error flag. - * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); -} - -/** - * @brief Get Stream 7 transfer error flag. - * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); -} - -/** - * @brief Get Stream 0 direct mode error flag. - * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); -} - -/** - * @brief Get Stream 1 direct mode error flag. - * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); -} - -/** - * @brief Get Stream 2 direct mode error flag. - * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); -} - -/** - * @brief Get Stream 3 direct mode error flag. - * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); -} - -/** - * @brief Get Stream 4 direct mode error flag. - * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); -} - -/** - * @brief Get Stream 5 direct mode error flag. - * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); -} - -/** - * @brief Get Stream 6 direct mode error flag. - * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); -} - -/** - * @brief Get Stream 7 direct mode error flag. - * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); -} - -/** - * @brief Get Stream 0 FIFO error flag. - * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); -} - -/** - * @brief Get Stream 1 FIFO error flag. - * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); -} - -/** - * @brief Get Stream 2 FIFO error flag. - * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); -} - -/** - * @brief Get Stream 3 FIFO error flag. - * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); -} - -/** - * @brief Get Stream 4 FIFO error flag. - * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); -} - -/** - * @brief Get Stream 5 FIFO error flag. - * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); -} - -/** - * @brief Get Stream 6 FIFO error flag. - * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); -} - -/** - * @brief Get Stream 7 FIFO error flag. - * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); -} - -/** - * @brief Clear Stream 0 half transfer flag. - * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); -} - -/** - * @brief Clear Stream 1 half transfer flag. - * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); -} - -/** - * @brief Clear Stream 2 half transfer flag. - * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); -} - -/** - * @brief Clear Stream 3 half transfer flag. - * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); -} - -/** - * @brief Clear Stream 4 half transfer flag. - * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); -} - -/** - * @brief Clear Stream 5 half transfer flag. - * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); -} - -/** - * @brief Clear Stream 6 half transfer flag. - * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); -} - -/** - * @brief Clear Stream 7 half transfer flag. - * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); -} - -/** - * @brief Clear Stream 0 transfer complete flag. - * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); -} - -/** - * @brief Clear Stream 1 transfer complete flag. - * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); -} - -/** - * @brief Clear Stream 2 transfer complete flag. - * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); -} - -/** - * @brief Clear Stream 3 transfer complete flag. - * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); -} - -/** - * @brief Clear Stream 4 transfer complete flag. - * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); -} - -/** - * @brief Clear Stream 5 transfer complete flag. - * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); -} - -/** - * @brief Clear Stream 6 transfer complete flag. - * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); -} - -/** - * @brief Clear Stream 7 transfer complete flag. - * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); -} - -/** - * @brief Clear Stream 0 transfer error flag. - * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); -} - -/** - * @brief Clear Stream 1 transfer error flag. - * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); -} - -/** - * @brief Clear Stream 2 transfer error flag. - * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); -} - -/** - * @brief Clear Stream 3 transfer error flag. - * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); -} - -/** - * @brief Clear Stream 4 transfer error flag. - * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); -} - -/** - * @brief Clear Stream 5 transfer error flag. - * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); -} - -/** - * @brief Clear Stream 6 transfer error flag. - * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); -} - -/** - * @brief Clear Stream 7 transfer error flag. - * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); -} - -/** - * @brief Clear Stream 0 direct mode error flag. - * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); -} - -/** - * @brief Clear Stream 1 direct mode error flag. - * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); -} - -/** - * @brief Clear Stream 2 direct mode error flag. - * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); -} - -/** - * @brief Clear Stream 3 direct mode error flag. - * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); -} - -/** - * @brief Clear Stream 4 direct mode error flag. - * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); -} - -/** - * @brief Clear Stream 5 direct mode error flag. - * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); -} - -/** - * @brief Clear Stream 6 direct mode error flag. - * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); -} - -/** - * @brief Clear Stream 7 direct mode error flag. - * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); -} - -/** - * @brief Clear Stream 0 FIFO error flag. - * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); -} - -/** - * @brief Clear Stream 1 FIFO error flag. - * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); -} - -/** - * @brief Clear Stream 2 FIFO error flag. - * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); -} - -/** - * @brief Clear Stream 3 FIFO error flag. - * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); -} - -/** - * @brief Clear Stream 4 FIFO error flag. - * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); -} - -/** - * @brief Clear Stream 5 FIFO error flag. - * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); -} - -/** - * @brief Clear Stream 6 FIFO error flag. - * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); -} - -/** - * @brief Clear Stream 7 FIFO error flag. - * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); -} - -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); -} - -/** - * @brief Enable Direct mode error interrupt. - * @rmtoll CR DMEIE LL_DMA_EnableIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); -} - -/** - * @brief Enable FIFO error interrupt. - * @rmtoll FCR FEIE LL_DMA_EnableIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); -} - -/** - * @brief Disable Direct mode error interrupt. - * @rmtoll CR DMEIE LL_DMA_DisableIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); -} - -/** - * @brief Disable FIFO error interrupt. - * @rmtoll FCR FEIE LL_DMA_DisableIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); -} - -/** - * @brief Check if Half transfer interrupt is enabled. - * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); -} - -/** - * @brief Check if Transfer error nterrup is enabled. - * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); -} - -/** - * @brief Check if Transfer complete interrupt is enabled. - * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); -} - -/** - * @brief Check if Direct mode error interrupt is enabled. - * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); -} - -/** - * @brief Check if FIFO error interrupt is enabled. - * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_DMA_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h deleted file mode 100644 index 65ab691..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h +++ /dev/null @@ -1,954 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS.Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_EXTI_H -#define __STM32F4xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#if defined(EXTI_IMR_IM16) -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#endif -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#endif -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#if defined(EXTI_IMR_IM20) -#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ -#endif -#if defined(EXTI_IMR_IM21) -#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ -#endif -#if defined(EXTI_IMR_IM22) -#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ -#endif -#if defined(EXTI_IMR_IM23) -#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ -#endif -#if defined(EXTI_IMR_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ -#endif -#if defined(EXTI_IMR_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ -#endif -#if defined(EXTI_IMR_IM26) -#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ -#endif -#if defined(EXTI_IMR_IM27) -#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ -#endif -#if defined(EXTI_IMR_IM28) -#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ -#endif -#if defined(EXTI_IMR_IM29) -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ -#endif -#if defined(EXTI_IMR_IM30) -#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ -#endif -#if defined(EXTI_IMR_IM31) -#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ -#endif -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ - - -#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); - -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - - -/** - * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); -} - - -/** - * @brief Clear ExtLine Flags for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19(*) - * @arg @ref LL_EXTI_LINE_20(*) - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_EXTI_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h deleted file mode 100644 index 6bee7fd..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h +++ /dev/null @@ -1,981 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_GPIO_H -#define __STM32F4xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) - -/** @defgroup GPIO_LL GPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ - GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ - GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ - GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ - GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ - GPIO_BSRR_BS_15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ -#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ -#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ -#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ -#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ -#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ -#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ -#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, - (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, - (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, - (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); -} - - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) -{ - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, (PinMask << 16)); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - uint32_t odr = READ_REG(GPIOx->ODR); - WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_GPIO_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h deleted file mode 100644 index ea23dc5..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h +++ /dev/null @@ -1,985 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_PWR_H -#define __STM32F4xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ -#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ -#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */ -#if defined(PWR_CSR_EWUP) -#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */ -#elif defined(PWR_CSR_EWUP1) -#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ -#endif /* PWR_CSR_EWUP */ -#if defined(PWR_CSR_EWUP2) -#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#endif /* PWR_CSR_EWUP2 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ -#endif /* PWR_CSR_EWUP3 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage - * @{ - */ -#if defined(PWR_CR_VOS_0) -#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0) -#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) -#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */ -#else -#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS) -#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U -#endif /* PWR_CR_VOS_0 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_MODE_PWR Mode Power - * @{ - */ -#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ -#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) -#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ -#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ -#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) -#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */ -#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode - * @{ - */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level - * @{ - */ -#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ -#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ -#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ -#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ -#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ -#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ -#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ -#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ -/** - * @} - */ -/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins - * @{ - */ -#if defined(PWR_CSR_EWUP) -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */ -#endif /* PWR_CSR_EWUP */ -#if defined(PWR_CSR_EWUP1) -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ -#endif /* PWR_CSR_EWUP1 */ -#if defined(PWR_CSR_EWUP2) -#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */ -#endif /* PWR_CSR_EWUP2 */ -#if defined(PWR_CSR_EWUP3) -#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */ -#endif /* PWR_CSR_EWUP3 */ -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_Configuration Configuration - * @{ - */ -#if defined(PWR_CR_FISSR) -/** - * @brief Enable FLASH interface STOP while system Run is ON - * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP - * @note This mode is enabled only with STOP low power mode. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void) -{ - SET_BIT(PWR->CR, PWR_CR_FISSR); -} - -/** - * @brief Disable FLASH Interface STOP while system Run is ON - * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_FISSR); -} - -/** - * @brief Check if FLASH Interface STOP while system Run feature is enabled - * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR)); -} -#endif /* PWR_CR_FISSR */ - -#if defined(PWR_CR_FMSSR) -/** - * @brief Enable FLASH Memory STOP while system Run is ON - * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP - * @note This mode is enabled only with STOP low power mode. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void) -{ - SET_BIT(PWR->CR, PWR_CR_FMSSR); -} - -/** - * @brief Disable FLASH Memory STOP while system Run is ON - * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); -} - -/** - * @brief Check if FLASH Memory STOP while system Run feature is enabled - * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR)); -} -#endif /* PWR_CR_FMSSR */ -#if defined(PWR_CR_UDEN) -/** - * @brief Enable Under Drive Mode - * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main Regulator or the low power Regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage Regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_UDEN); -} - -/** - * @brief Disable Under Drive Mode - * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_UDEN); -} - -/** - * @brief Check if Under Drive Mode is enabled - * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN)); -} -#endif /* PWR_CR_UDEN */ - -#if defined(PWR_CR_ODSWEN) -/** - * @brief Enable Over drive switching - * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) -{ - SET_BIT(PWR->CR, PWR_CR_ODSWEN); -} - -/** - * @brief Disable Over drive switching - * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN); -} - -/** - * @brief Check if Over drive switching is enabled - * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN)); -} -#endif /* PWR_CR_ODSWEN */ -#if defined(PWR_CR_ODEN) -/** - * @brief Enable Over drive Mode - * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_ODEN); -} - -/** - * @brief Disable Over drive Mode - * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_ODEN); -} - -/** - * @brief Check if Over drive switching is enabled - * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN)); -} -#endif /* PWR_CR_ODEN */ -#if defined(PWR_CR_MRUDS) -/** - * @brief Enable Main Regulator in deepsleep under-drive Mode - * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_MRUDS); -} - -/** - * @brief Disable Main Regulator in deepsleep under-drive Mode - * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_MRUDS); -} - -/** - * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled - * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS)); -} -#endif /* PWR_CR_MRUDS */ - -#if defined(PWR_CR_LPUDS) -/** - * @brief Enable Low Power Regulator in deepsleep under-drive Mode - * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_LPUDS); -} - -/** - * @brief Disable Low Power Regulator in deepsleep under-drive Mode - * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_LPUDS); -} - -/** - * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled - * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS)); -} -#endif /* PWR_CR_LPUDS */ - -#if defined(PWR_CR_MRLVDS) -/** - * @brief Enable Main Regulator low voltage Mode - * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_MRLVDS); -} - -/** - * @brief Disable Main Regulator low voltage Mode - * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS); -} - -/** - * @brief Check if Main Regulator low voltage Mode is enabled - * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS)); -} -#endif /* PWR_CR_MRLVDS */ - -#if defined(PWR_CR_LPLVDS) -/** - * @brief Enable Low Power Regulator low voltage Mode - * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void) -{ - SET_BIT(PWR->CR, PWR_CR_LPLVDS); -} - -/** - * @brief Disable Low Power Regulator low voltage Mode - * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS); -} - -/** - * @brief Check if Low Power Regulator low voltage Mode is enabled - * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS)); -} -#endif /* PWR_CR_LPLVDS */ -/** - * @brief Set the main internal Regulator output voltage - * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling - * @param VoltageScaling This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) -{ - MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); -} - -/** - * @brief Get the main internal Regulator output voltage - * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); -} -/** - * @brief Enable the Flash Power Down in Stop Mode - * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) -{ - SET_BIT(PWR->CR, PWR_CR_FPDS); -} - -/** - * @brief Disable the Flash Power Down in Stop Mode - * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_FPDS); -} - -/** - * @brief Check if the Flash Power Down in Stop Mode is enabled - * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS)); -} - -/** - * @brief Enable access to the backup domain - * @rmtoll CR DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Disable access to the backup domain - * @rmtoll CR DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_DBP); -} - -/** - * @brief Check if the backup domain is enabled - * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); -} -/** - * @brief Enable the backup Regulator - * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator - * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. - * The LL_PWR_EnableBkUpAccess() must be called before using this API. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) -{ - SET_BIT(PWR->CSR, PWR_CSR_BRE); -} - -/** - * @brief Disable the backup Regulator - * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator - * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. - * The LL_PWR_EnableBkUpAccess() must be called before using this API. - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) -{ - CLEAR_BIT(PWR->CSR, PWR_CSR_BRE); -} - -/** - * @brief Check if the backup Regulator is enabled - * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE)); -} - -/** - * @brief Set voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_SetRegulModeDS - * @param RegulMode This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) -{ - MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); -} - -/** - * @brief Get voltage Regulator mode during deep sleep mode - * @rmtoll CR LPDS LL_PWR_GetRegulModeDS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); -} - -/** - * @brief Set Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n - * @rmtoll CR FPDS LL_PWR_SetPowerMode\n - * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n - * @rmtoll CR FPDS LL_PWR_SetPowerMode\n - * @rmtoll CR LPDS LL_PWR_SetPowerMode - * @param PDMode This parameter can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) - * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) - * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) - * - * (*) not available on all devices - * @arg @ref LL_PWR_MODE_STANDBY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) -{ -#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode); -#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode); -#else - MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); -#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ -} - -/** - * @brief Get Power Down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode\n - * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n - * @rmtoll CR FPDS LL_PWR_GetPowerMode\n - * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n - * @rmtoll CR FPDS LL_PWR_GetPowerMode\n - * @rmtoll CR LPDS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) - * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) - * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) - * - * (*) not available on all devices - * @arg @ref LL_PWR_MODE_STANDBY - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ -#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS))); -#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS))); -#else - return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); -#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ -} - -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector - * @rmtoll CR PLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); -} - -/** - * @brief Get the voltage threshold detection - * @rmtoll CR PLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); -} - -/** - * @brief Enable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Disable Power Voltage Detector - * @rmtoll CR PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR, PWR_CR_PVDE); -} - -/** - * @brief Check if Power Voltage Detector is enabled - * @rmtoll CR PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); -} - -/** - * @brief Enable the WakeUp PINx functionality - * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 (*) - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Disable the WakeUp PINx functionality - * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 (*) - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * - * (*) not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CSR, WakeUpPin); -} - -/** - * @brief Check if the WakeUp PINx functionality is enabled - * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 (*) - * @arg @ref LL_PWR_WAKEUP_PIN3 (*) - * - * (*) not available on all devices - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); -} - - -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Wake-up Flag - * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); -} - -/** - * @brief Get Standby Flag - * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); -} - -/** - * @brief Get Backup Regulator ready Flag - * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR)); -} -/** - * @brief Indicate whether VDD voltage is below the selected PVD threshold - * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); -} - -/** - * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level - * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) -{ - return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); -} -#if defined(PWR_CR_ODEN) -/** - * @brief Indicate whether the Over-Drive mode is ready or not - * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY)); -} -#endif /* PWR_CR_ODEN */ - -#if defined(PWR_CR_ODSWEN) -/** - * @brief Indicate whether the Over-Drive mode switching is ready or not - * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY)); -} -#endif /* PWR_CR_ODSWEN */ - -#if defined(PWR_CR_UDEN) -/** - * @brief Indicate whether the Under-Drive mode is ready or not - * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) -{ - return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY)); -} -#endif /* PWR_CR_UDEN */ -/** - * @brief Clear Standby Flag - * @rmtoll CR CSBF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - SET_BIT(PWR->CR, PWR_CR_CSBF); -} - -/** - * @brief Clear Wake-up Flags - * @rmtoll CR CWUF LL_PWR_ClearFlag_WU - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) -{ - SET_BIT(PWR->CR, PWR_CR_CWUF); -} -#if defined(PWR_CSR_UDRDY) -/** - * @brief Clear Under-Drive ready Flag - * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) -{ - WRITE_REG(PWR->CSR, PWR_CSR_UDRDY); -} -#endif /* PWR_CSR_UDRDY */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_PWR_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h deleted file mode 100644 index 1df1b58..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h +++ /dev/null @@ -1,7096 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_RCC_H -#define __STM32F4xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -#if defined(RCC_DCKCFGR_PLLSAIDIVR) -static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; -#endif /* RCC_DCKCFGR_PLLSAIDIVR */ - -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ - -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ -#endif /* EXTERNAL_CLOCK_VALUE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#if defined(RCC_PLLI2S_SUPPORT) -#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ -#endif /* RCC_PLLI2S_SUPPORT */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ -#endif /* RCC_PLLSAI_SUPPORT */ -#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#if defined(RCC_PLLI2S_SUPPORT) -#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ -#endif /* RCC_PLLI2S_SUPPORT */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ -#endif /* RCC_PLLSAI_SUPPORT */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#if defined(RCC_CSR_BORRSTF) -#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ -#endif /* RCC_CSR_BORRSTF */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#if defined(RCC_PLLI2S_SUPPORT) -#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ -#endif /* RCC_PLLI2S_SUPPORT */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ -#endif /* RCC_PLLSAI_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -#if defined(RCC_CFGR_SW_PLLR) -#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ -#endif /* RCC_CFGR_SW_PLLR */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -#if defined(RCC_PLLR_SYSCLK_SUPPORT) -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ -#endif /* RCC_PLLR_SYSCLK_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) - * @{ - */ -#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ -#if defined(RCC_CFGR_MCO2) -#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ -#endif /* RCC_CFGR_MCO2 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ -#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ -#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ -#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ -#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ -#if defined(RCC_CFGR_MCO2PRE) -#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ -#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ -#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ -#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ -#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ -#endif /* RCC_CFGR_MCO2PRE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock - * @{ - */ -#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ -#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ -#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ -#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ -#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ -#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ -#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ -#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ -#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ -#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ -#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ -#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ -#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ -#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ -#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ -#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ -#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ -#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ -#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ -#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ -#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ -#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ -#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ -#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ -#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ -#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ -#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ -#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ -#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ -#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ -#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -#if defined(FMPI2C1) -/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection - * @{ - */ -#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ -#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ -#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ -/** - * @} - */ -#endif /* FMPI2C1 */ - -#if defined(LPTIM1) -/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ -/** - * @} - */ -#endif /* LPTIM1 */ - -#if defined(SAI1) -/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection - * @{ - */ -#if defined(RCC_DCKCFGR_SAI1SRC) -#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ -#endif /* RCC_DCKCFGR_SAI1SRC */ -#if defined(RCC_DCKCFGR_SAI2SRC) -#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ -#endif /* RCC_DCKCFGR_SAI2SRC */ -#if defined(RCC_DCKCFGR_SAI1ASRC) -#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) -#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ -#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ -#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ -#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ -#else -#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ -#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ -#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ -#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ -#endif /* RCC_DCKCFGR_SAI1ASRC */ -#if defined(RCC_DCKCFGR_SAI1BSRC) -#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) -#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ -#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ -#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ -#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ -#else -#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ -#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ -#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ -#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ -#endif /* RCC_DCKCFGR_SAI1BSRC */ -/** - * @} - */ -#endif /* SAI1 */ - -#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) -/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection - * @{ - */ -#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ -#if defined(RCC_DCKCFGR_SDIOSEL) -#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ -#else -#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ -#endif /* RCC_DCKCFGR_SDIOSEL */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ -#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ -/** - * @} - */ -#endif /* DSI */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ -#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ -/** - * @} - */ -#endif /* CEC */ - -/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection - * @{ - */ -#if defined(RCC_CFGR_I2SSRC) -#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ -#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ -#endif /* RCC_CFGR_I2SSRC */ -#if defined(RCC_DCKCFGR_I2SSRC) -#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ -#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ -#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ -#endif /* RCC_DCKCFGR_I2SSRC */ -#if defined(RCC_DCKCFGR_I2S1SRC) -#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ -#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ -#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ -#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ -#endif /* RCC_DCKCFGR_I2S1SRC */ -#if defined(RCC_DCKCFGR_I2S2SRC) -#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ -#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ -#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ -#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ -#endif /* RCC_DCKCFGR_I2S2SRC */ -/** - * @} - */ - -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection - * @{ - */ -#if defined(RCC_DCKCFGR_CK48MSEL) -#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ -#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ -#endif /* RCC_DCKCFGR_CK48MSEL */ -#if defined(RCC_DCKCFGR2_CK48MSEL) -#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ -#endif /* RCC_PLLSAI_SUPPORT */ -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) -#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ -#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ -#endif /* RCC_DCKCFGR2_CK48MSEL */ -/** - * @} - */ - -#if defined(RNG) -/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection - * @{ - */ -#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ -#endif /* RCC_PLLSAI_SUPPORT */ -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) -#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ -#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ -/** - * @} - */ -#endif /* RNG */ - -#if defined(USB_OTG_FS) || defined(USB_OTG_HS) -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ -#if defined(RCC_PLLSAI_SUPPORT) -#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ -#endif /* RCC_PLLSAI_SUPPORT */ -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) -#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ -#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ -/** - * @} - */ -#endif /* USB_OTG_FS || USB_OTG_HS */ - -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ - -#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) -/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection - * @{ - */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ -#if defined(DFSDM2_Channel0) -#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ -#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ -#endif /* DFSDM2_Channel0 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection - * @{ - */ -#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ -#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ -#if defined(DFSDM2_Channel0) -#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ -#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ -#endif /* DFSDM2_Channel0 */ -/** - * @} - */ -#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ - -#if defined(FMPI2C1) -/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source - * @{ - */ -#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ -/** - * @} - */ -#endif /* FMPI2C1 */ - -#if defined(SPDIFRX) -/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection - * @{ - */ -#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ -#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ -/** - * @} - */ -#endif /* SPDIFRX */ - -#if defined(LPTIM1) -/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ -/** - * @} - */ -#endif /* LPTIM1 */ - -#if defined(SAI1) -/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source - * @{ - */ -#if defined(RCC_DCKCFGR_SAI1ASRC) -#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ -#endif /* RCC_DCKCFGR_SAI1ASRC */ -#if defined(RCC_DCKCFGR_SAI1BSRC) -#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ -#endif /* RCC_DCKCFGR_SAI1BSRC */ -#if defined(RCC_DCKCFGR_SAI1SRC) -#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ -#endif /* RCC_DCKCFGR_SAI1SRC */ -#if defined(RCC_DCKCFGR_SAI2SRC) -#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ -#endif /* RCC_DCKCFGR_SAI2SRC */ -/** - * @} - */ -#endif /* SAI1 */ - -#if defined(SDIO) -/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source - * @{ - */ -#if defined(RCC_DCKCFGR_SDIOSEL) -#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ -#elif defined(RCC_DCKCFGR2_SDIOSEL) -#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ -#else -#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ -#endif -/** - * @} - */ -#endif /* SDIO */ - -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source - * @{ - */ -#if defined(RCC_DCKCFGR_CK48MSEL) -#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ -#endif /* RCC_DCKCFGR_CK48MSEL */ -#if defined(RCC_DCKCFGR2_CK48MSEL) -#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ -#endif /* RCC_DCKCFGR_CK48MSEL */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ - -#if defined(RNG) -/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source - * @{ - */ -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ -#else -#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ -/** - * @} - */ -#endif /* RNG */ - -#if defined(USB_OTG_FS) || defined(USB_OTG_HS) -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ -#else -#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ -/** - * @} - */ -#endif /* USB_OTG_FS || USB_OTG_HS */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ -/** - * @} - */ -#endif /* CEC */ - -/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source - * @{ - */ -#if defined(RCC_CFGR_I2SSRC) -#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ -#endif /* RCC_CFGR_I2SSRC */ -#if defined(RCC_DCKCFGR_I2SSRC) -#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ -#endif /* RCC_DCKCFGR_I2SSRC */ -#if defined(RCC_DCKCFGR_I2S1SRC) -#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ -#endif /* RCC_DCKCFGR_I2S1SRC */ -#if defined(RCC_DCKCFGR_I2S2SRC) -#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ -#endif /* RCC_DCKCFGR_I2S2SRC */ -/** - * @} - */ - -#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) -/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source - * @{ - */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ -#if defined(DFSDM2_Channel0) -#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ -#endif /* DFSDM2_Channel0 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source - * @{ - */ -#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ -#if defined(DFSDM2_Channel0) -#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ -#endif /* DFSDM2_Channel0 */ -/** - * @} - */ -#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ - -#if defined(SPDIFRX) -/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source - * @{ - */ -#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ -/** - * @} - */ -#endif /* SPDIFRX */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ -/** - * @} - */ -#endif /* DSI */ - -#if defined(LTDC) -/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source - * @{ - */ -#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ -/** - * @} - */ -#endif /* LTDC */ - - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ -/** - * @} - */ - -#if defined(RCC_DCKCFGR_TIMPRE) -/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection - * @{ - */ -#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ -#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_TIMPRE */ - -/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source - * @{ - */ -#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ -#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) -#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ -#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor - * @{ - */ -#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ -#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ -#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ -#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ -#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ -#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ -#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ -#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ -#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ -#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ -#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ -#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ -#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ -#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ -#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ -#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ -#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ -#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ -#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ -#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ -#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ -#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ -#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ -#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ -#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ -#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ -#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ -#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ -#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ -#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ -#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ -#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ -#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ -#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ -#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ -#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ -#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ -#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ -#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ -#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ -#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ -#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ -#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ -#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ -#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ -#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ -#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ -#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ -#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ -#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ -#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ -#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ -#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ -#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ -#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ -#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ -#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ -#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ -#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ -#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ -#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ -#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ -/** - * @} - */ - -#if defined(RCC_PLLCFGR_PLLR) -/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) - * @{ - */ -#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ -#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ -#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ -#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ -#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ -#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ -/** - * @} - */ -#endif /* RCC_PLLCFGR_PLLR */ - -#if defined(RCC_DCKCFGR_PLLDIVR) -/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) - * @{ - */ -#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ -#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ -#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ -#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ -#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ -#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ -#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ -#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ -#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ -#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ -#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ -#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ -#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ -#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ -#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ -#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ -#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ -#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ -#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ -#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ -#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ -#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ -#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ -#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ -#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ -#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ -#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ -#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ -#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ -#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ -#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_PLLDIVR */ - -/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) - * @{ - */ -#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) - * @{ - */ -#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ -#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ -#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ -#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ -#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ -#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ -#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ -#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ -#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ -#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ -#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ -#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ -#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ -#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection - * @{ - */ -#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ -#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ -/** - * @} - */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) - * @{ - */ -#if defined(RCC_PLLI2SCFGR_PLLI2SM) -#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ -#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ -#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ -#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ -#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ -#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ -#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ -#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ -#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ -#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ -#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ -#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ -#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ -#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ -#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ -#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ -#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ -#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ -#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ -#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ -#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ -#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ -#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ -#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ -#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ -#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ -#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ -#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ -#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ -#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ -#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ -#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ -#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ -#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ -#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ -#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ -#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ -#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ -#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ -#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ -#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ -#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ -#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ -#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ -#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ -#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ -#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ -#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ -#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ -#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ -#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ -#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ -#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ -#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ -#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ -#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ -#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ -#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ -#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ -#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ -#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ -#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ -#else -#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ -#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ -#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ -#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ -#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ -#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ -#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ -#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ -#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ -#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ -#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ -#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ -#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ -#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ -#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ -#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ -#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ -#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ -#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ -#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ -#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ -#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ -#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ -#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ -#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ -#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ -#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ -#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ -#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ -#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ -#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ -#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ -#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ -#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ -#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ -#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ -#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ -#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ -#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ -#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ -#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ -#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ -#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ -#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ -#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ -#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ -#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ -#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ -#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ -#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ -#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ -#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ -#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ -#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ -#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ -#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ -#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ -#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ -#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ -#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ -#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ -#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ -/** - * @} - */ - -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) -/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) - * @{ - */ -#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ -#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ -#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ -#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ -#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ -#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ -#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ -#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ -#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ -#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ -#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ -#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ -#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ -#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ -/** - * @} - */ -#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ - -#if defined(RCC_DCKCFGR_PLLI2SDIVQ) -/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) - * @{ - */ -#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ -#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ -#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ -#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ -#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ -#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ -#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ -#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ -#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ -#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ -#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ -#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ -#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ -#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ -#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ -#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ -#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ -#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ -#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ -#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ -#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ -#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ -#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ -#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ -#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ -#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ -#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ -#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ -#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ -#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ -#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ -#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ - -#if defined(RCC_DCKCFGR_PLLI2SDIVR) -/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) - * @{ - */ -#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ -#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ -#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ -#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ -#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ -#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ -#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ -#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ -#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ -#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ -#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ -#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ -#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ -#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ -#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ -#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ -#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ -#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ -#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ -#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ -#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ -#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ -#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ -#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ -#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ -#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ -#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ -#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ -#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ -#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ -#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_PLLI2SDIVR */ - -/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) - * @{ - */ -#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ -#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ -#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ -#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ -#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ -#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ -/** - * @} - */ - -#if defined(RCC_PLLI2SCFGR_PLLI2SP) -/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) - * @{ - */ -#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ -#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ -#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ -#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ -/** - * @} - */ -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) - * @{ - */ -#if defined(RCC_PLLSAICFGR_PLLSAIM) -#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ -#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ -#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ -#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ -#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ -#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ -#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ -#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ -#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ -#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ -#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ -#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ -#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ -#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ -#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ -#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ -#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ -#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ -#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ -#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ -#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ -#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ -#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ -#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ -#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ -#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ -#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ -#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ -#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ -#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ -#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ -#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ -#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ -#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ -#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ -#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ -#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ -#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ -#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ -#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ -#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ -#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ -#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ -#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ -#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ -#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ -#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ -#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ -#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ -#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ -#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ -#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ -#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ -#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ -#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ -#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ -#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ -#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ -#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ -#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ -#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ -#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ -#else -#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ -#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ -#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ -#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ -#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ -#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ -#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ -#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ -#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ -#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ -#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ -#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ -#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ -#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ -#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ -#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ -#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ -#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ -#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ -#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ -#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ -#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ -#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ -#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ -#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ -#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ -#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ -#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ -#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ -#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ -#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ -#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ -#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ -#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ -#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ -#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ -#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ -#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ -#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ -#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ -#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ -#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ -#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ -#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ -#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ -#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ -#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ -#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ -#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ -#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ -#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ -#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ -#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ -#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ -#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ -#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ -#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ -#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ -#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ -#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ -#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ -#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ -#endif /* RCC_PLLSAICFGR_PLLSAIM */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) - * @{ - */ -#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ -#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ -#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ -#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ -#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ -#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ -#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ -#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ -#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ -#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ -#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ -#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ -#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ -#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ -/** - * @} - */ - -#if defined(RCC_DCKCFGR_PLLSAIDIVQ) -/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) - * @{ - */ -#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ -#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ -#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ -#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ -#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ -#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ -#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ -#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ -#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ -#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ -#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ -#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ -#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ -#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ -#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ -#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ -#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ -#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ -#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ -#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ -#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ -#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ -#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ -#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ -#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ -#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ -#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ -#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ -#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ -#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ -#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ -#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_PLLSAIDIVQ */ - -#if defined(RCC_PLLSAICFGR_PLLSAIR) -/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) - * @{ - */ -#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ -#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ -#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ -#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ -#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ -#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ -/** - * @} - */ -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - -#if defined(RCC_DCKCFGR_PLLSAIDIVR) -/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) - * @{ - */ -#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ -#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ -#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ -#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR_PLLSAIDIVR */ - -#if defined(RCC_PLLSAICFGR_PLLSAIP) -/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) - * @{ - */ -#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ -#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ -#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ -#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ -/** - * @} - */ -#endif /* RCC_PLLSAICFGR_PLLSAIP */ -#endif /* RCC_PLLSAI_SUPPORT */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -/** - * @brief Helper macro to calculate the PLLCLK frequency on system domain - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) - -#if defined(RCC_PLLR_SYSCLK_SUPPORT) -/** - * @brief Helper macro to calculate the PLLRCLK frequency on system domain - * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) - -#endif /* RCC_PLLR_SYSCLK_SUPPORT */ - -/** - * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain - * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) - -#if defined(DSI) -/** - * @brief Helper macro to calculate the PLLCLK frequency used on DSI - * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) -#endif /* DSI */ - -#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) -/** - * @brief Helper macro to calculate the PLLCLK frequency used on I2S - * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) -#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ - -#if defined(SPDIFRX) -/** - * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX - * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) -#endif /* SPDIFRX */ - -#if defined(RCC_PLLCFGR_PLLR) -#if defined(SAI1) -/** - * @brief Helper macro to calculate the PLLCLK frequency used on SAI - * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @param __PLLDIVR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) - * - * (*) value not defined in all devices. - * @retval PLL clock frequency (in Hz) - */ -#if defined(RCC_DCKCFGR_PLLDIVR) -#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) -#else -#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) -#endif /* RCC_DCKCFGR_PLLDIVR */ -#endif /* SAI1 */ -#endif /* RCC_PLLCFGR_PLLR */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain - * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param __PLLSAIN__ Between 49/50(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLSAIQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - * @param __PLLSAIDIVQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) - -#if defined(RCC_PLLSAICFGR_PLLSAIP) -/** - * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain - * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param __PLLSAIN__ Between 50 and 432 - * @param __PLLSAIP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) -#endif /* RCC_PLLSAICFGR_PLLSAIP */ - -#if defined(LTDC) -/** - * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain - * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param __PLLSAIN__ Between 49/50(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLSAIR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - * @param __PLLSAIDIVR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) -#endif /* LTDC */ -#endif /* RCC_PLLSAI_SUPPORT */ - -#if defined(RCC_PLLI2S_SUPPORT) -#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) -/** - * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param __PLLI2SN__ Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLI2SQ_R__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) - * - * (*) value not defined in all devices. - * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) - * - * (*) value not defined in all devices. - * @retval PLLI2S clock frequency (in Hz) - */ -#if defined(RCC_DCKCFGR_PLLI2SDIVQ) -#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) -#else -#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) - -#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ -#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ - -#if defined(SPDIFRX) -/** - * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param __PLLI2SN__ Between 50 and 432 - * @param __PLLI2SP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) - -#endif /* SPDIFRX */ - -/** - * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param __PLLI2SN__ Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param __PLLI2SR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) - -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) -/** - * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param __PLLI2SN__ Between 50 and 432 - * @param __PLLI2SQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) - -#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ -#endif /* RCC_PLLI2S_SUPPORT */ - -/** - * @brief Helper macro to calculate the HCLK frequency - * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) - -/** - * @brief Helper macro to calculate the PCLK2 frequency (ABP2) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB2PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval PCLK2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 16, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value Between Min_Data = 0 and Max_Data = 31 - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0 and Max_Data = 31 - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); -} - -#if defined(RCC_BDCR_LSEMOD) -/** - * @brief Enable LSE high drive mode. - * @note LSE high drive mode can be enabled only when the LSE clock is disabled - * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); -} - -/** - * @brief Disable LSE high drive mode. - * @note LSE high drive mode can be disabled only when the LSE clock is disabled - * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); -} -#endif /* RCC_BDCR_LSEMOD */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); -} - -/** - * @brief Set APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); -} - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); -} - -/** - * @brief Get APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -#if defined(RCC_CFGR_MCO1EN) -/** - * @brief Enable MCO1 output - * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MCO1_Enable(void) -{ - SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); -} - -/** - * @brief Disable MCO1 output - * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MCO1_Disable(void) -{ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); -} -#endif /* RCC_CFGR_MCO1EN */ - -#if defined(RCC_CFGR_MCO2EN) -/** - * @brief Enable MCO2 output - * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MCO2_Enable(void) -{ - SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); -} - -/** - * @brief Disable MCO2 output - * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MCO2_Disable(void) -{ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); -} -#endif /* RCC_CFGR_MCO2EN */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n - * CFGR MCO1PRE LL_RCC_ConfigMCO\n - * CFGR MCO2 LL_RCC_ConfigMCO\n - * CFGR MCO2PRE LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK - * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S - * @arg @ref LL_RCC_MCO2SOURCE_HSE - * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 - * @arg @ref LL_RCC_MCO1_DIV_3 - * @arg @ref LL_RCC_MCO1_DIV_4 - * @arg @ref LL_RCC_MCO1_DIV_5 - * @arg @ref LL_RCC_MCO2_DIV_1 - * @arg @ref LL_RCC_MCO2_DIV_2 - * @arg @ref LL_RCC_MCO2_DIV_3 - * @arg @ref LL_RCC_MCO2_DIV_4 - * @arg @ref LL_RCC_MCO2_DIV_5 - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ - MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ -#if defined(FMPI2C1) -/** - * @brief Configure FMPI2C clock source - * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource - * @param FMPI2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); -} -#endif /* FMPI2C1 */ - -#if defined(LPTIM1) -/** - * @brief Configure LPTIMx clock source - * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource - * @param LPTIMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); -} -#endif /* LPTIM1 */ - -#if defined(SAI1) -/** - * @brief Configure SAIx clock source - * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n - * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n - * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n - * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource - * @param SAIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) -{ - MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); -} -#endif /* SAI1 */ - -#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) -/** - * @brief Configure SDIO clock source - * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n - * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource - * @param SDIOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK - * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) -{ -#if defined(RCC_DCKCFGR_SDIOSEL) - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); -#else - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); -#endif /* RCC_DCKCFGR_SDIOSEL */ -} -#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ - -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -/** - * @brief Configure 48Mhz domain clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource - * @param CK48MxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); -#else - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} - -#if defined(RNG) -/** - * @brief Configure RNG clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource - * @param RNGxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); -#else - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} -#endif /* RNG */ - -#if defined(USB_OTG_FS) || defined(USB_OTG_HS) -/** - * @brief Configure USB clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); -#else - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} -#endif /* USB_OTG_FS || USB_OTG_HS */ -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ - -#if defined(CEC) -/** - * @brief Configure CEC clock source - * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); -} -#endif /* CEC */ - -/** - * @brief Configure I2S clock source - * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n - * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n - * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n - * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) -{ -#if defined(RCC_CFGR_I2SSRC) - MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); -#else - MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); -#endif /* RCC_CFGR_I2SSRC */ -} - -#if defined(DSI) -/** - * @brief Configure DSI clock source - * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); -} -#endif /* DSI */ - -#if defined(DFSDM1_Channel0) -/** - * @brief Configure DFSDM Audio clock source - * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n - * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 - * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) - * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); -} - -/** - * @brief Configure DFSDM Kernel clock source - * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) - * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); -} -#endif /* DFSDM1_Channel0 */ - -#if defined(SPDIFRX) -/** - * @brief Configure SPDIFRX clock source - * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource - * @param SPDIFRXxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); -} -#endif /* SPDIFRX */ - -#if defined(FMPI2C1) -/** - * @brief Get FMPI2C clock source - * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource - * @param FMPI2Cx This parameter can be one of the following values: - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); -} -#endif /* FMPI2C1 */ - -#if defined(LPTIM1) -/** - * @brief Get LPTIMx clock source - * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource - * @param LPTIMx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); -} -#endif /* LPTIM1 */ - -#if defined(SAI1) -/** - * @brief Get SAIx clock source - * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n - * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n - * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n - * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource - * @param SAIx This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); -} -#endif /* SAI1 */ - -#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) -/** - * @brief Get SDIOx clock source - * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n - * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource - * @param SDIOx This parameter can be one of the following values: - * @arg @ref LL_RCC_SDIO_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK - * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK - */ -__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) -{ -#if defined(RCC_DCKCFGR_SDIOSEL) - return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); -#else - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); -#endif /* RCC_DCKCFGR_SDIOSEL */ -} -#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ - -#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) -/** - * @brief Get 48Mhz domain clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource - * @param CK48Mx This parameter can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); -#else - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} - -#if defined(RNG) -/** - * @brief Get RNGx clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource - * @param RNGx This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); -#else - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} -#endif /* RNG */ - -#if defined(USB_OTG_FS) || defined(USB_OTG_HS) -/** - * @brief Get USBx clock source - * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n - * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ -#if defined(RCC_DCKCFGR_CK48MSEL) - return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); -#else - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); -#endif /* RCC_DCKCFGR_CK48MSEL */ -} -#endif /* USB_OTG_FS || USB_OTG_HS */ -#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ - -#if defined(CEC) -/** - * @brief Get CEC Clock Source - * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource - * @param CECx This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); -} -#endif /* CEC */ - -/** - * @brief Get I2S Clock Source - * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n - * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n - * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n - * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource - * @param I2Sx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE - * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) - * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) -{ -#if defined(RCC_CFGR_I2SSRC) - return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); -#else - return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); -#endif /* RCC_CFGR_I2SSRC */ -} - -#if defined(DFSDM1_Channel0) -/** - * @brief Get DFSDM Audio Clock Source - * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n - * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource - * @param DFSDMx This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE - * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 - * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) - * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); -} - -/** - * @brief Get DFSDM Audio Clock Source - * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource - * @param DFSDMx This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE - * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) - * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); -} -#endif /* DFSDM1_Channel0 */ - -#if defined(SPDIFRX) -/** - * @brief Get SPDIFRX clock source - * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource - * @param SPDIFRXx This parameter can be one of the following values: - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); -} -#endif /* SPDIFRX */ - -#if defined(DSI) -/** - * @brief Get DSI Clock Source - * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource - * @param DSIx This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL - */ -__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); -} -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed anymore unless - * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is - * set). The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Set HSE Prescalers for RTC Clock - * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_NOCLOCK - * @arg @ref LL_RCC_RTC_HSE_DIV_2 - * @arg @ref LL_RCC_RTC_HSE_DIV_3 - * @arg @ref LL_RCC_RTC_HSE_DIV_4 - * @arg @ref LL_RCC_RTC_HSE_DIV_5 - * @arg @ref LL_RCC_RTC_HSE_DIV_6 - * @arg @ref LL_RCC_RTC_HSE_DIV_7 - * @arg @ref LL_RCC_RTC_HSE_DIV_8 - * @arg @ref LL_RCC_RTC_HSE_DIV_9 - * @arg @ref LL_RCC_RTC_HSE_DIV_10 - * @arg @ref LL_RCC_RTC_HSE_DIV_11 - * @arg @ref LL_RCC_RTC_HSE_DIV_12 - * @arg @ref LL_RCC_RTC_HSE_DIV_13 - * @arg @ref LL_RCC_RTC_HSE_DIV_14 - * @arg @ref LL_RCC_RTC_HSE_DIV_15 - * @arg @ref LL_RCC_RTC_HSE_DIV_16 - * @arg @ref LL_RCC_RTC_HSE_DIV_17 - * @arg @ref LL_RCC_RTC_HSE_DIV_18 - * @arg @ref LL_RCC_RTC_HSE_DIV_19 - * @arg @ref LL_RCC_RTC_HSE_DIV_20 - * @arg @ref LL_RCC_RTC_HSE_DIV_21 - * @arg @ref LL_RCC_RTC_HSE_DIV_22 - * @arg @ref LL_RCC_RTC_HSE_DIV_23 - * @arg @ref LL_RCC_RTC_HSE_DIV_24 - * @arg @ref LL_RCC_RTC_HSE_DIV_25 - * @arg @ref LL_RCC_RTC_HSE_DIV_26 - * @arg @ref LL_RCC_RTC_HSE_DIV_27 - * @arg @ref LL_RCC_RTC_HSE_DIV_28 - * @arg @ref LL_RCC_RTC_HSE_DIV_29 - * @arg @ref LL_RCC_RTC_HSE_DIV_30 - * @arg @ref LL_RCC_RTC_HSE_DIV_31 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); -} - -/** - * @brief Get HSE Prescalers for RTC Clock - * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_NOCLOCK - * @arg @ref LL_RCC_RTC_HSE_DIV_2 - * @arg @ref LL_RCC_RTC_HSE_DIV_3 - * @arg @ref LL_RCC_RTC_HSE_DIV_4 - * @arg @ref LL_RCC_RTC_HSE_DIV_5 - * @arg @ref LL_RCC_RTC_HSE_DIV_6 - * @arg @ref LL_RCC_RTC_HSE_DIV_7 - * @arg @ref LL_RCC_RTC_HSE_DIV_8 - * @arg @ref LL_RCC_RTC_HSE_DIV_9 - * @arg @ref LL_RCC_RTC_HSE_DIV_10 - * @arg @ref LL_RCC_RTC_HSE_DIV_11 - * @arg @ref LL_RCC_RTC_HSE_DIV_12 - * @arg @ref LL_RCC_RTC_HSE_DIV_13 - * @arg @ref LL_RCC_RTC_HSE_DIV_14 - * @arg @ref LL_RCC_RTC_HSE_DIV_15 - * @arg @ref LL_RCC_RTC_HSE_DIV_16 - * @arg @ref LL_RCC_RTC_HSE_DIV_17 - * @arg @ref LL_RCC_RTC_HSE_DIV_18 - * @arg @ref LL_RCC_RTC_HSE_DIV_19 - * @arg @ref LL_RCC_RTC_HSE_DIV_20 - * @arg @ref LL_RCC_RTC_HSE_DIV_21 - * @arg @ref LL_RCC_RTC_HSE_DIV_22 - * @arg @ref LL_RCC_RTC_HSE_DIV_23 - * @arg @ref LL_RCC_RTC_HSE_DIV_24 - * @arg @ref LL_RCC_RTC_HSE_DIV_25 - * @arg @ref LL_RCC_RTC_HSE_DIV_26 - * @arg @ref LL_RCC_RTC_HSE_DIV_27 - * @arg @ref LL_RCC_RTC_HSE_DIV_28 - * @arg @ref LL_RCC_RTC_HSE_DIV_29 - * @arg @ref LL_RCC_RTC_HSE_DIV_30 - * @arg @ref LL_RCC_RTC_HSE_DIV_31 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); -} - -/** - * @} - */ - -#if defined(RCC_DCKCFGR_TIMPRE) -/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM - * @{ - */ - -/** - * @brief Set Timers Clock Prescalers - * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_TIM_PRESCALER_TWICE - * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); -} - -/** - * @brief Get Timers Clock Prescalers - * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_TIM_PRESCALER_TWICE - * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES - */ -__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); -} - -/** - * @} - */ -#endif /* RCC_DCKCFGR_TIMPRE */ - -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); -} - -/** - * @brief Configure PLL used for SYSCLK Domain - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLP can be written only when PLL is disabled - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLP_R This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - * @arg @ref LL_RCC_PLLR_DIV_2 (*) - * @arg @ref LL_RCC_PLLR_DIV_3 (*) - * @arg @ref LL_RCC_PLLR_DIV_4 (*) - * @arg @ref LL_RCC_PLLR_DIV_5 (*) - * @arg @ref LL_RCC_PLLR_DIV_6 (*) - * @arg @ref LL_RCC_PLLR_DIV_7 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); -#if defined(RCC_PLLR_SYSCLK_SUPPORT) - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); -#endif /* RCC_PLLR_SYSCLK_SUPPORT */ -} - -/** - * @brief Configure PLL used for 48Mhz domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLQ can be written only when PLL is disabled - * @note This can be selected for USB, RNG, SDIO - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); -} - -#if defined(DSI) -/** - * @brief Configure PLL used for DSI clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLL is disabled - * @note This can be selected for DSI - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); -} -#endif /* DSI */ - -#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) -/** - * @brief Configure PLL used for I2S clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLL is disabled - * @note This can be selected for I2S - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); -} -#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ - -#if defined(SPDIFRX) -/** - * @brief Configure PLL used for SPDIFRX clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLL is disabled - * @note This can be selected for SPDIFRX - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); -} -#endif /* SPDIFRX */ - -#if defined(RCC_PLLCFGR_PLLR) -#if defined(SAI1) -/** - * @brief Configure PLL used for SAI clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLL is disabled - * @note This can be selected for SAI - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n - * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @param PLLDIVR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) - * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -#if defined(RCC_DCKCFGR_PLLDIVR) -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) -#else -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -#endif /* RCC_DCKCFGR_PLLDIVR */ -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); -#if defined(RCC_DCKCFGR_PLLDIVR) - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); -#endif /* RCC_DCKCFGR_PLLDIVR */ -} -#endif /* SAI1 */ -#endif /* RCC_PLLCFGR_PLLR */ - -/** - * @brief Configure PLL clock source - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - -/** - * @brief Get Main PLL multiplication factor for VCO - * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN - * @retval Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); -} - -/** - * @brief Get Main PLL division factor for PLLP - * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); -} - -/** - * @brief Get Main PLL division factor for PLLQ - * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) - * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); -} - -#if defined(RCC_PLLCFGR_PLLR) -/** - * @brief Get Main PLL division factor for PLLR - * @note used for PLLCLK (system clock) - * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); -} -#endif /* RCC_PLLCFGR_PLLR */ - -#if defined(RCC_DCKCFGR_PLLDIVR) -/** - * @brief Get Main PLL division factor for PLLDIVR - * @note used for PLLSAICLK (SAI1 and SAI2 clock) - * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLDIVR_DIV_1 - * @arg @ref LL_RCC_PLLDIVR_DIV_2 - * @arg @ref LL_RCC_PLLDIVR_DIV_3 - * @arg @ref LL_RCC_PLLDIVR_DIV_4 - * @arg @ref LL_RCC_PLLDIVR_DIV_5 - * @arg @ref LL_RCC_PLLDIVR_DIV_6 - * @arg @ref LL_RCC_PLLDIVR_DIV_7 - * @arg @ref LL_RCC_PLLDIVR_DIV_8 - * @arg @ref LL_RCC_PLLDIVR_DIV_9 - * @arg @ref LL_RCC_PLLDIVR_DIV_10 - * @arg @ref LL_RCC_PLLDIVR_DIV_11 - * @arg @ref LL_RCC_PLLDIVR_DIV_12 - * @arg @ref LL_RCC_PLLDIVR_DIV_13 - * @arg @ref LL_RCC_PLLDIVR_DIV_14 - * @arg @ref LL_RCC_PLLDIVR_DIV_15 - * @arg @ref LL_RCC_PLLDIVR_DIV_16 - * @arg @ref LL_RCC_PLLDIVR_DIV_17 - * @arg @ref LL_RCC_PLLDIVR_DIV_18 - * @arg @ref LL_RCC_PLLDIVR_DIV_19 - * @arg @ref LL_RCC_PLLDIVR_DIV_20 - * @arg @ref LL_RCC_PLLDIVR_DIV_21 - * @arg @ref LL_RCC_PLLDIVR_DIV_22 - * @arg @ref LL_RCC_PLLDIVR_DIV_23 - * @arg @ref LL_RCC_PLLDIVR_DIV_24 - * @arg @ref LL_RCC_PLLDIVR_DIV_25 - * @arg @ref LL_RCC_PLLDIVR_DIV_26 - * @arg @ref LL_RCC_PLLDIVR_DIV_27 - * @arg @ref LL_RCC_PLLDIVR_DIV_28 - * @arg @ref LL_RCC_PLLDIVR_DIV_29 - * @arg @ref LL_RCC_PLLDIVR_DIV_30 - * @arg @ref LL_RCC_PLLDIVR_DIV_31 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); -} -#endif /* RCC_DCKCFGR_PLLDIVR */ - -/** - * @brief Get Division factor for the main PLL and other PLL - * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); -} - -/** - * @brief Configure Spread Spectrum used for PLL - * @note These bits must be written before enabling PLL - * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n - * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n - * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum - * @param Mod Between Min_Data=0 and Max_Data=8191 - * @param Inc Between Min_Data=0 and Max_Data=32767 - * @param Sel This parameter can be one of the following values: - * @arg @ref LL_RCC_SPREAD_SELECT_CENTER - * @arg @ref LL_RCC_SPREAD_SELECT_DOWN - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) -{ - MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); -} - -/** - * @brief Get Spread Spectrum Modulation Period for PLL - * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation - * @retval Between Min_Data=0 and Max_Data=8191 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); -} - -/** - * @brief Get Spread Spectrum Incrementation Step for PLL - * @note Must be written before enabling PLL - * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation - * @retval Between Min_Data=0 and Max_Data=32767 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); -} - -/** - * @brief Get Spread Spectrum Selection for PLL - * @note Must be written before enabling PLL - * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SPREAD_SELECT_CENTER - * @arg @ref LL_RCC_SPREAD_SELECT_DOWN - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); -} - -/** - * @brief Enable Spread Spectrum for PLL. - * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) -{ - SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); -} - -/** - * @brief Disable Spread Spectrum for PLL. - * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) -{ - CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); -} - -/** - * @} - */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** @defgroup RCC_LL_EF_PLLI2S PLLI2S - * @{ - */ - -/** - * @brief Enable PLLI2S - * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLI2SON); -} - -/** - * @brief Disable PLLI2S - * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); -} - -/** - * @brief Check if PLLI2S Ready - * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); -} - -#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) -/** - * @brief Configure PLLI2S used for SAI domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled - * @note This can be selected for SAI - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n - * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n - * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) - * - * (*) value not defined in all devices. - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param PLLN Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLQ_R This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) - * - * (*) value not defined in all devices. - * @param PLLDIVQ_R This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); - MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); -#if defined(RCC_DCKCFGR_PLLI2SDIVQ) - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); -#else - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); -#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ -} -#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ - -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) -/** - * @brief Configure PLLI2S used for 48Mhz domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLQ can be written only when PLLI2S is disabled - * @note This can be selected for RNG, USB, SDIO - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n - * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n - * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n - * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) - * - * (*) value not defined in all devices. - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); - MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); -} -#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ - -#if defined(SPDIFRX) -/** - * @brief Configure PLLI2S used for SPDIFRX domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLP can be written only when PLLI2S is disabled - * @note This can be selected for SPDIFRX - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLP This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); -} -#endif /* SPDIFRX */ - -/** - * @brief Configure PLLI2S used for I2S1 domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLR can be written only when PLLI2S is disabled - * @note This can be selected for I2S - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) - * - * (*) value not defined in all devices. - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - * @param PLLN Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); - MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); -} - -/** - * @brief Get I2SPLL multiplication factor for VCO - * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN - * @retval Between 50/192(*) and 432 - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); -} - -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) -/** - * @brief Get I2SPLL division factor for PLLI2SQ - * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); -} -#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ - -/** - * @brief Get I2SPLL division factor for PLLI2SR - * @note used for PLLI2SCLK (I2S clock) - * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); -} - -#if defined(RCC_PLLI2SCFGR_PLLI2SP) -/** - * @brief Get I2SPLL division factor for PLLI2SP - * @note used for PLLSPDIFRXCLK (SPDIFRX clock) - * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); -} -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ - -#if defined(RCC_DCKCFGR_PLLI2SDIVQ) -/** - * @brief Get I2SPLL division factor for PLLI2SDIVQ - * @note used PLLSAICLK selected (SAI clock) - * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); -} -#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ - -#if defined(RCC_DCKCFGR_PLLI2SDIVR) -/** - * @brief Get I2SPLL division factor for PLLI2SDIVR - * @note used PLLSAICLK selected (SAI clock) - * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 - * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); -} -#endif /* RCC_DCKCFGR_PLLI2SDIVR */ - -/** - * @brief Get division factor for PLLI2S input clock - * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n - * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SM_DIV_2 - * @arg @ref LL_RCC_PLLI2SM_DIV_3 - * @arg @ref LL_RCC_PLLI2SM_DIV_4 - * @arg @ref LL_RCC_PLLI2SM_DIV_5 - * @arg @ref LL_RCC_PLLI2SM_DIV_6 - * @arg @ref LL_RCC_PLLI2SM_DIV_7 - * @arg @ref LL_RCC_PLLI2SM_DIV_8 - * @arg @ref LL_RCC_PLLI2SM_DIV_9 - * @arg @ref LL_RCC_PLLI2SM_DIV_10 - * @arg @ref LL_RCC_PLLI2SM_DIV_11 - * @arg @ref LL_RCC_PLLI2SM_DIV_12 - * @arg @ref LL_RCC_PLLI2SM_DIV_13 - * @arg @ref LL_RCC_PLLI2SM_DIV_14 - * @arg @ref LL_RCC_PLLI2SM_DIV_15 - * @arg @ref LL_RCC_PLLI2SM_DIV_16 - * @arg @ref LL_RCC_PLLI2SM_DIV_17 - * @arg @ref LL_RCC_PLLI2SM_DIV_18 - * @arg @ref LL_RCC_PLLI2SM_DIV_19 - * @arg @ref LL_RCC_PLLI2SM_DIV_20 - * @arg @ref LL_RCC_PLLI2SM_DIV_21 - * @arg @ref LL_RCC_PLLI2SM_DIV_22 - * @arg @ref LL_RCC_PLLI2SM_DIV_23 - * @arg @ref LL_RCC_PLLI2SM_DIV_24 - * @arg @ref LL_RCC_PLLI2SM_DIV_25 - * @arg @ref LL_RCC_PLLI2SM_DIV_26 - * @arg @ref LL_RCC_PLLI2SM_DIV_27 - * @arg @ref LL_RCC_PLLI2SM_DIV_28 - * @arg @ref LL_RCC_PLLI2SM_DIV_29 - * @arg @ref LL_RCC_PLLI2SM_DIV_30 - * @arg @ref LL_RCC_PLLI2SM_DIV_31 - * @arg @ref LL_RCC_PLLI2SM_DIV_32 - * @arg @ref LL_RCC_PLLI2SM_DIV_33 - * @arg @ref LL_RCC_PLLI2SM_DIV_34 - * @arg @ref LL_RCC_PLLI2SM_DIV_35 - * @arg @ref LL_RCC_PLLI2SM_DIV_36 - * @arg @ref LL_RCC_PLLI2SM_DIV_37 - * @arg @ref LL_RCC_PLLI2SM_DIV_38 - * @arg @ref LL_RCC_PLLI2SM_DIV_39 - * @arg @ref LL_RCC_PLLI2SM_DIV_40 - * @arg @ref LL_RCC_PLLI2SM_DIV_41 - * @arg @ref LL_RCC_PLLI2SM_DIV_42 - * @arg @ref LL_RCC_PLLI2SM_DIV_43 - * @arg @ref LL_RCC_PLLI2SM_DIV_44 - * @arg @ref LL_RCC_PLLI2SM_DIV_45 - * @arg @ref LL_RCC_PLLI2SM_DIV_46 - * @arg @ref LL_RCC_PLLI2SM_DIV_47 - * @arg @ref LL_RCC_PLLI2SM_DIV_48 - * @arg @ref LL_RCC_PLLI2SM_DIV_49 - * @arg @ref LL_RCC_PLLI2SM_DIV_50 - * @arg @ref LL_RCC_PLLI2SM_DIV_51 - * @arg @ref LL_RCC_PLLI2SM_DIV_52 - * @arg @ref LL_RCC_PLLI2SM_DIV_53 - * @arg @ref LL_RCC_PLLI2SM_DIV_54 - * @arg @ref LL_RCC_PLLI2SM_DIV_55 - * @arg @ref LL_RCC_PLLI2SM_DIV_56 - * @arg @ref LL_RCC_PLLI2SM_DIV_57 - * @arg @ref LL_RCC_PLLI2SM_DIV_58 - * @arg @ref LL_RCC_PLLI2SM_DIV_59 - * @arg @ref LL_RCC_PLLI2SM_DIV_60 - * @arg @ref LL_RCC_PLLI2SM_DIV_61 - * @arg @ref LL_RCC_PLLI2SM_DIV_62 - * @arg @ref LL_RCC_PLLI2SM_DIV_63 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) -{ -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); -#else - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n - * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) -{ -#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) - uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); - uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; - return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); -#else - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ -} - -/** - * @} - */ -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** @defgroup RCC_LL_EF_PLLSAI PLLSAI - * @{ - */ - -/** - * @brief Enable PLLSAI - * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLSAION); -} - -/** - * @brief Disable PLLSAI - * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); -} - -/** - * @brief Check if PLLSAI Ready - * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); -} - -/** - * @brief Configure PLLSAI used for SAI domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLQ can be written only when PLLSAI is disabled - * @note This can be selected for SAI - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n - * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param PLLN Between 49/50(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - * @param PLLDIVQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); -#if defined(RCC_PLLSAICFGR_PLLSAIM) - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLSAICFGR_PLLSAIM */ - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); -} - -#if defined(RCC_PLLSAICFGR_PLLSAIP) -/** - * @brief Configure PLLSAI used for 48Mhz domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLP can be written only when PLLSAI is disabled - * @note This can be selected for USB, RNG, SDIO - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLP This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); -#if defined(RCC_PLLSAICFGR_PLLSAIM) - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); -#else - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); -#endif /* RCC_PLLSAICFGR_PLLSAIM */ - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); -} -#endif /* RCC_PLLSAICFGR_PLLSAIP */ - -#if defined(LTDC) -/** - * @brief Configure PLLSAI used for LTDC domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI(*) are disabled - * @note PLLN/PLLR can be written only when PLLSAI is disabled - * @note This can be selected for LTDC - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - * @param PLLN Between 49/50(*) and 432 - * - * (*) value not defined in all devices. - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - * @param PLLDIVR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); - MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); -} -#endif /* LTDC */ - -/** - * @brief Get division factor for PLLSAI input clock - * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n - * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIM_DIV_2 - * @arg @ref LL_RCC_PLLSAIM_DIV_3 - * @arg @ref LL_RCC_PLLSAIM_DIV_4 - * @arg @ref LL_RCC_PLLSAIM_DIV_5 - * @arg @ref LL_RCC_PLLSAIM_DIV_6 - * @arg @ref LL_RCC_PLLSAIM_DIV_7 - * @arg @ref LL_RCC_PLLSAIM_DIV_8 - * @arg @ref LL_RCC_PLLSAIM_DIV_9 - * @arg @ref LL_RCC_PLLSAIM_DIV_10 - * @arg @ref LL_RCC_PLLSAIM_DIV_11 - * @arg @ref LL_RCC_PLLSAIM_DIV_12 - * @arg @ref LL_RCC_PLLSAIM_DIV_13 - * @arg @ref LL_RCC_PLLSAIM_DIV_14 - * @arg @ref LL_RCC_PLLSAIM_DIV_15 - * @arg @ref LL_RCC_PLLSAIM_DIV_16 - * @arg @ref LL_RCC_PLLSAIM_DIV_17 - * @arg @ref LL_RCC_PLLSAIM_DIV_18 - * @arg @ref LL_RCC_PLLSAIM_DIV_19 - * @arg @ref LL_RCC_PLLSAIM_DIV_20 - * @arg @ref LL_RCC_PLLSAIM_DIV_21 - * @arg @ref LL_RCC_PLLSAIM_DIV_22 - * @arg @ref LL_RCC_PLLSAIM_DIV_23 - * @arg @ref LL_RCC_PLLSAIM_DIV_24 - * @arg @ref LL_RCC_PLLSAIM_DIV_25 - * @arg @ref LL_RCC_PLLSAIM_DIV_26 - * @arg @ref LL_RCC_PLLSAIM_DIV_27 - * @arg @ref LL_RCC_PLLSAIM_DIV_28 - * @arg @ref LL_RCC_PLLSAIM_DIV_29 - * @arg @ref LL_RCC_PLLSAIM_DIV_30 - * @arg @ref LL_RCC_PLLSAIM_DIV_31 - * @arg @ref LL_RCC_PLLSAIM_DIV_32 - * @arg @ref LL_RCC_PLLSAIM_DIV_33 - * @arg @ref LL_RCC_PLLSAIM_DIV_34 - * @arg @ref LL_RCC_PLLSAIM_DIV_35 - * @arg @ref LL_RCC_PLLSAIM_DIV_36 - * @arg @ref LL_RCC_PLLSAIM_DIV_37 - * @arg @ref LL_RCC_PLLSAIM_DIV_38 - * @arg @ref LL_RCC_PLLSAIM_DIV_39 - * @arg @ref LL_RCC_PLLSAIM_DIV_40 - * @arg @ref LL_RCC_PLLSAIM_DIV_41 - * @arg @ref LL_RCC_PLLSAIM_DIV_42 - * @arg @ref LL_RCC_PLLSAIM_DIV_43 - * @arg @ref LL_RCC_PLLSAIM_DIV_44 - * @arg @ref LL_RCC_PLLSAIM_DIV_45 - * @arg @ref LL_RCC_PLLSAIM_DIV_46 - * @arg @ref LL_RCC_PLLSAIM_DIV_47 - * @arg @ref LL_RCC_PLLSAIM_DIV_48 - * @arg @ref LL_RCC_PLLSAIM_DIV_49 - * @arg @ref LL_RCC_PLLSAIM_DIV_50 - * @arg @ref LL_RCC_PLLSAIM_DIV_51 - * @arg @ref LL_RCC_PLLSAIM_DIV_52 - * @arg @ref LL_RCC_PLLSAIM_DIV_53 - * @arg @ref LL_RCC_PLLSAIM_DIV_54 - * @arg @ref LL_RCC_PLLSAIM_DIV_55 - * @arg @ref LL_RCC_PLLSAIM_DIV_56 - * @arg @ref LL_RCC_PLLSAIM_DIV_57 - * @arg @ref LL_RCC_PLLSAIM_DIV_58 - * @arg @ref LL_RCC_PLLSAIM_DIV_59 - * @arg @ref LL_RCC_PLLSAIM_DIV_60 - * @arg @ref LL_RCC_PLLSAIM_DIV_61 - * @arg @ref LL_RCC_PLLSAIM_DIV_62 - * @arg @ref LL_RCC_PLLSAIM_DIV_63 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) -{ -#if defined(RCC_PLLSAICFGR_PLLSAIM) - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); -#else - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); -#endif /* RCC_PLLSAICFGR_PLLSAIM */ -} - -/** - * @brief Get SAIPLL multiplication factor for VCO - * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN - * @retval Between 49/50(*) and 432 - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); -} - -/** - * @brief Get SAIPLL division factor for PLLSAIQ - * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); -} - -#if defined(RCC_PLLSAICFGR_PLLSAIR) -/** - * @brief Get SAIPLL division factor for PLLSAIR - * @note used for PLLSAICLK (SAI clock) - * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); -} -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - -#if defined(RCC_PLLSAICFGR_PLLSAIP) -/** - * @brief Get SAIPLL division factor for PLLSAIP - * @note used for PLL48MCLK (48M domain clock) - * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); -} -#endif /* RCC_PLLSAICFGR_PLLSAIP */ - -/** - * @brief Get SAIPLL division factor for PLLSAIDIVQ - * @note used PLLSAICLK selected (SAI clock) - * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); -} - -#if defined(RCC_DCKCFGR_PLLSAIDIVR) -/** - * @brief Get SAIPLL division factor for PLLSAIDIVR - * @note used for LTDC domain clock - * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); -} -#endif /* RCC_DCKCFGR_PLLSAIDIVR */ - -/** - * @} - */ -#endif /* RCC_PLLSAI_SUPPORT */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); -} - -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Clear PLLI2S ready interrupt flag - * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); -} - -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Clear PLLSAI ready interrupt flag - * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); -} - -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_CSSC); -} - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); -} - -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Check if PLLI2S ready interrupt occurred or not - * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Check if PLLSAI ready interrupt occurred or not - * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); -} -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); -} - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); -} - -/** - * @brief Check if RCC flag POR/PDR reset is set or not. - * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); -} - -#if defined(RCC_CSR_BORRSTF) -/** - * @brief Check if RCC flag BOR reset is set or not. - * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); -} -#endif /* RCC_CSR_BORRSTF */ - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Enable PLLI2S ready interrupt - * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); -} -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Enable PLLSAI ready interrupt - * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); -} -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Disable PLLI2S ready interrupt - * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); -} - -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Disable PLLSAI ready interrupt - * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); -} -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); -} - -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); -} - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); -} - -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); -} -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -#if defined(FMPI2C1) -uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); -#endif /* FMPI2C1 */ -#if defined(LPTIM1) -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); -#endif /* LPTIM1 */ -#if defined(SAI1) -uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); -#endif /* SAI1 */ -#if defined(SDIO) -uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); -#endif /* SDIO */ -#if defined(RNG) -uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); -#endif /* RNG */ -#if defined(USB_OTG_FS) || defined(USB_OTG_HS) -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#endif /* USB_OTG_FS || USB_OTG_HS */ -#if defined(DFSDM1_Channel0) -uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); -uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); -#endif /* DFSDM1_Channel0 */ -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); -#if defined(CEC) -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); -#endif /* CEC */ -#if defined(LTDC) -uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); -#endif /* LTDC */ -#if defined(SPDIFRX) -uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); -#endif /* SPDIFRX */ -#if defined(DSI) -uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); -#endif /* DSI */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_RCC_H */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h deleted file mode 100644 index 84ea5c4..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h +++ /dev/null @@ -1,1711 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - * - ****************************************************************************** - * @attention - * - *Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - - @endverbatim - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_SYSTEM_H -#define __STM32F4xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP -* @{ -*/ -#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ -#if defined(FSMC_Bank1) -#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ -#endif /* FSMC_Bank1 */ -#if defined(FMC_Bank1) -#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */ -#endif /* FMC_Bank1 */ -#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ - -/** - * @} - */ - -#if defined(SYSCFG_PMC_MII_RMII_SEL) - /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC -* @{ -*/ -#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */ -#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ - -/** - * @} - */ -#endif /* SYSCFG_PMC_MII_RMII_SEL */ - - - -#if defined(SYSCFG_MEMRMP_UFB_MODE) -/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE - * @{ - */ -#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) - and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ -#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) - and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ -/** - * @} - */ -#endif /* SYSCFG_MEMRMP_UFB_MODE */ -/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS - * @{ - */ -#if defined(SYSCFG_CFGR_FMPI2C1_SCL) -#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/ -#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT - * @{ - */ -#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ -#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ -#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ -#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ -#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ -#if defined(GPIOF) -#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ -#endif /* GPIOF */ -#if defined(GPIOG) -#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ -#endif /* GPIOG */ -#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */ -#if defined(GPIOI) -#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */ -#endif /* GPIOI */ -#if defined(GPIOJ) -#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */ -#endif /* GPIOJ */ -#if defined(GPIOK) -#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */ -#endif /* GPIOK */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE - * @{ - */ -#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK - * @{ - */ -#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 - with Break Input of TIM1/8 */ -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input - and also the PVDE and PLS bits of the Power Control Interface */ -#endif /* SYSCFG_CFGR2_CLL */ -/** - * @} - */ - -#if defined(SYSCFG_MCHDLYCR_BSCKSEL) -/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL - * @{ - */ -#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000 -#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN - * @{ - */ -#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN -#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL - * @{ - */ -#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL -#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL - -#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000) -#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL) -#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000) -#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL) -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL - * @{ - */ -#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL -#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL - -#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000) -#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL) -#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000) -#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL) -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL - * @{ - */ -#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL - * @{ - */ -#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG - * @{ - */ -#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL - * @{ - */ -#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL -/** - * @} - */ - -/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG - * @{ - */ -#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG -/** - * @} - */ -/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL - * @{ - */ -#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000 -#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL -/** - * @} - */ -#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ - -/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment - * @{ - */ -#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ -#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ -#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP) -#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */ -#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) -#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ -#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) -#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ -#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ -#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ -#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ -#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */ -#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ -#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ -#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ -#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ -#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ -#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ -#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ -#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ -#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ -#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ -#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ -#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ -#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ -#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ -#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ -/** - * @brief Set memory mapping at address 0x00000000 - * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory - * @param Memory This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - * @arg @ref LL_SYSCFG_REMAP_FSMC (*) - * @arg @ref LL_SYSCFG_REMAP_FMC (*) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) -{ - MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); -} - -/** - * @brief Get memory mapping at address 0x00000000 - * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - * @arg @ref LL_SYSCFG_REMAP_FSMC (*) - * @arg @ref LL_SYSCFG_REMAP_FMC (*) - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); -} - -#if defined(SYSCFG_MEMRMP_SWP_FMC) -/** - * @brief Enables the FMC Memory Mapping Swapping - * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping - * @note SDRAM is accessible at 0x60000000 and NOR/RAM - * is accessible at 0xC0000000 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) -{ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); -} - -/** - * @brief Disables the FMC Memory Mapping Swapping - * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping - * @note SDRAM is accessible at 0xC0000000 (default mapping) - * and NOR/RAM is accessible at 0x60000000 (default mapping) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) -{ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); -} - -#endif /* SYSCFG_MEMRMP_SWP_FMC */ -/** - * @brief Enables the Compensation cell Power Down - * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) -{ - SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Disables the Compensation cell Power Down - * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Get Compensation Cell ready Flag - * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) -{ - return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); -} - -#if defined(SYSCFG_PMC_MII_RMII_SEL) -/** - * @brief Select Ethernet PHY interface - * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface - * @param Interface This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_PMC_ETHMII - * @arg @ref LL_SYSCFG_PMC_ETHRMII - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) -{ - MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); -} - -/** - * @brief Get Ethernet PHY interface - * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_PMC_ETHMII - * @arg @ref LL_SYSCFG_PMC_ETHRMII - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); -} -#endif /* SYSCFG_PMC_MII_RMII_SEL */ - - - -#if defined(SYSCFG_MEMRMP_UFB_MODE) -/** - * @brief Select Flash bank mode (Bank flashed at 0x08000000) - * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode - * @param Bank This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_BANKMODE_BANK1 - * @arg @ref LL_SYSCFG_BANKMODE_BANK2 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) -{ - MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank); -} - -/** - * @brief Get Flash bank mode (Bank flashed at 0x08000000) - * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_BANKMODE_BANK1 - * @arg @ref LL_SYSCFG_BANKMODE_BANK2 - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE)); -} -#endif /* SYSCFG_MEMRMP_UFB_MODE */ - -#if defined(SYSCFG_CFGR_FMPI2C1_SCL) -/** - * @brief Enable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - SET_BIT(SYSCFG->CFGR, ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus); -} -#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ - -/** - * @brief Configure source input for the EXTI external interrupt. - * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource - * @param Port This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD - * @arg @ref LL_SYSCFG_EXTI_PORTE - * @arg @ref LL_SYSCFG_EXTI_PORTF (*) - * @arg @ref LL_SYSCFG_EXTI_PORTG (*) - * @arg @ref LL_SYSCFG_EXTI_PORTH - * - * (*) value not defined in all devices - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) -{ - MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD - * @arg @ref LL_SYSCFG_EXTI_PORTE - * @arg @ref LL_SYSCFG_EXTI_PORTF (*) - * @arg @ref LL_SYSCFG_EXTI_PORTG (*) - * @arg @ref LL_SYSCFG_EXTI_PORTH - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) -{ - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); -} - -#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -/** - * @brief Set connections to TIM1/8 break inputs - * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n - * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs - * @param Break This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) -{ - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); -} - -/** - * @brief Get connections to TIM1/8 Break inputs - * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n - * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)); -} -#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ -#if defined(SYSCFG_MCHDLYCR_BSCKSEL) -/** - * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. - * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 - * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource); -} -/** - * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. - * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 - * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL)); -} -/** - * @brief Enables the DFSDM1 or DFSDM2 Delay clock - * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock - * @param MCHDLY This parameter can be one of the following values - * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN - * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY) -{ - SET_BIT(SYSCFG->MCHDLYCR, MCHDLY); -} - -/** - * @brief Disables the DFSDM1 or the DFSDM2 Delay clock - * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock - * @param MCHDLY This parameter can be one of the following values - * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN - * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY) -{ - CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY); -} - -/** - * @brief Select the source for DFSDM1 or DFSDM2 DatIn0 - * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); -} -/** - * @brief Get the source for DFSDM1 or DFSDM2 DatIn0. - * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn0 - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); -} -/** - * @brief Select the source for DFSDM1 or DFSDM2 DatIn2 - * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); -} -/** - * @brief Get the source for DFSDM1 or DFSDM2 DatIn2. - * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn2 - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM4 OC2 - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM4 OC2 - * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM4 OC1 - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM4 OC1 - * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 - * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL)); -} - -/** - * @brief Select the DFSDM1 Clock In - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD - * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource); -} -/** - * @brief GET the DFSDM1 Clock In - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD - * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG)); -} - -/** - * @brief Select the DFSDM1 Clock Out - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_CKOUT - * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource); -} -/** - * @brief GET the DFSDM1 Clock Out - * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM1_CKOUT - * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL)); -} - -/** - * @brief Enables the DFSDM2 Delay clock - * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void) -{ - SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); -} - -/** - * @brief Disables the DFSDM2 Delay clock - * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void) -{ - CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); -} -/** - * @brief Select the source for DFSDM2 DatIn0 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source); -} -/** - * @brief Get the source for DFSDM2 DatIn0. - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL)); -} - -/** - * @brief Select the source for DFSDM2 DatIn2 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source); -} -/** - * @brief Get the source for DFSDM2 DatIn2. - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL)); -} - -/** - * @brief Select the source for DFSDM2 DatIn4 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source); -} -/** - * @brief Get the source for DFSDM2 DatIn4. - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL)); -} - -/** - * @brief Select the source for DFSDM2 DatIn6 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source); -} -/** - * @brief Get the source for DFSDM2 DatIn6. - * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD - * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC4 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC3 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC2 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC2 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL)); -} - -/** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC1 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source); -} -/** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC1 - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 - * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL)); -} - -/** - * @brief Select the DFSDM2 Clock In - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD - * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource); -} -/** - * @brief GET the DFSDM2 Clock In - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD - * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG)); -} - -/** - * @brief Select the DFSDM2 Clock Out - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_CKOUT - * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource) -{ - MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource); -} -/** - * @brief GET the DFSDM2 Clock Out - * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DFSDM2_CKOUT - * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL)); -} - -#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ -/** - * @} - */ - - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413 - * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419 - * @note For STM32F401xx devices, the device ID is 0x423 - * @note For STM32F401xx devices, the device ID is 0x433 - * @note For STM32F411xx devices, the device ID is 0x431 - * @note For STM32F410xx devices, the device ID is 0x458 - * @note For STM32F412xx devices, the device ID is 0x441 - * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463 - * @note For STM32F446xx devices, the device ID is 0x421 - * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434 - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices - For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices - For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices - For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices - For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices - For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Set Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment - * @param PinAssignment This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) -{ - MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); -} - -/** - * @brief Get Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment - * @retval Returned value can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Freeze APB2 peripherals - * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB2FZ, Periphs); -} - -/** - * @brief Unfreeze APB2 peripherals - * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB2FZ, Periphs); -} -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Prefetch - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); -} - -/** - * @brief Disable Prefetch - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); -} - -/** - * @brief Check if Prefetch buffer is enabled - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); -} - -/** - * @brief Enable Instruction cache - * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableInstCache(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); -} - -/** - * @brief Disable Instruction cache - * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableInstCache(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); -} - -/** - * @brief Enable Data cache - * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableDataCache(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); -} - -/** - * @brief Disable Data cache - * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableDataCache(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); -} - -/** - * @brief Enable Instruction cache reset - * @note bit can be written only when the instruction cache is disabled - * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); -} - -/** - * @brief Disable Instruction cache reset - * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); -} - -/** - * @brief Enable Data cache reset - * @note bit can be written only when the data cache is disabled - * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); -} - -/** - * @brief Disable Data cache reset - * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_SYSTEM_H */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h deleted file mode 100644 index 2b254a1..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_UTILS_H -#define __STM32F4xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @brief Package data register base address - */ -#define PACKAGE_BASE_ADDRESS PACKAGE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLM; /*!< Division factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - - uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE - and Max_Data = @ref RCC_PLLN_MIN_VALUE - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - - uint32_t PLLP; /*!< Division for the main system clock. - This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB2_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB2Prescaler(). */ - -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE - * @{ - */ -#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF); -} - -/** - * @brief Get Package type - * @retval Returned value can be one of the following values: - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_GetPackageType(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); -} - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LL_UTILS_H */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt deleted file mode 100644 index 3edc4d1..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt +++ /dev/null @@ -1,6 +0,0 @@ -This software component is provided to you as part of a software package and -applicable license terms are in the Package_license file. If you received this -software component outside of a package or without applicable license terms, -the terms of the BSD-3-Clause license shall apply. -You may obtain a copy of the BSD-3-Clause at: -https://opensource.org/licenses/BSD-3-Clause diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c deleted file mode 100644 index 9ba2ba7..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ /dev/null @@ -1,615 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup HAL_Private_Constants - * @{ - */ -/** - * @brief STM32F4xx HAL Driver version number V1.8.1 - */ -#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ -#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ - |(__STM32F4xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK 0x00000FFFU - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of UFB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos -#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) -#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos -#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) - -/* --- MCHDLYCR Register ---*/ -/* Alias word address of BSCKSEL bit */ -#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) -#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos -#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup HAL_Private_Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) De-Initializes common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief This function is used to initialize the HAL Library; it must be the first - * instruction to be executed in the main program (before to call any other - * HAL function), it performs the following: - * Configure the Flash prefetch, instruction and Data caches. - * Configures the SysTick to generate an interrupt each 1 millisecond, - * which is clocked by the HSI (at this stage, the clock is not yet - * configured and thus the system is running from the internal HSI at 16 MHz). - * Set NVIC Group Priority to 4. - * Calls the HAL_MspInit() callback function defined in user file - * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization - * - * @note SysTick is used as time base for the HAL_Delay() function, the application - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch, Instruction cache, Data cache */ -#if (INSTRUCTION_CACHE_ENABLE != 0U) - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); -#endif /* INSTRUCTION_CACHE_ENABLE */ - -#if (DATA_CACHE_ENABLE != 0U) - __HAL_FLASH_DATA_CACHE_ENABLE(); -#endif /* DATA_CACHE_ENABLE */ - -#if (PREFETCH_ENABLE != 0U) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += uwTickFreq; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @retval Status - */ -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_TickFreqTypeDef prevTickFreq; - - assert_param(IS_TICKFREQ(Freq)); - - if (uwTickFreq != Freq) - { - /* Back up uwTickFreq frequency */ - prevTickFreq = uwTickFreq; - - /* Update uwTickFreq global variable used by HAL_InitTick() */ - uwTickFreq = Freq; - - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - - if (status != HAL_OK) - { - /* Restore previous tick frequency */ - uwTickFreq = prevTickFreq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval tick period in Hz - */ -HAL_TickFreqTypeDef HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)(uwTickFreq); - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F4xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Enables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_EnableCompensationCell(void) -{ - *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE; -} - -/** - * @brief Power-down the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_DisableCompensationCell(void) -{ - *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; -} - -/** - * @brief Returns first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return (READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Returns second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Returns third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Enables the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_EnableMemorySwappingBank(void) -{ - *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_DisableMemorySwappingBank(void) -{ - *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c deleted file mode 100644 index 98515c5..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ /dev/null @@ -1,502 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M4 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest preemption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value 0x0F. - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32f4xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (preemption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PreemptPriority The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00U; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -#if (__MPU_PRESENT == 1U) -/** - * @brief Disables the MPU - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0U; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Ensure MPU setting take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00U; - MPU->RASR = 0x00U; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PriorityGroup the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c deleted file mode 100644 index 3dbb477..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ /dev/null @@ -1,1305 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM/FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Stream, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Stream Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), - Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. - - -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: - __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred. - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - (+) Use HAL_DMA_Abort() function to abort the current transfer. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - [..] - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort_IT() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - Half-Word data size for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two half words will be packed and written in - a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - and Destination. In this case the Peripheral Data Size will be applied to both Source - and Destination. - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register */ - __IO uint32_t Reserved0; - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ -} DMA_Base_Registers; - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Constants - * @{ - */ - #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Stream priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - uint32_t tickstart = HAL_GetTick(); - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); - /* Check the memory burst, peripheral burst and FIFO threshold parameters only - when FIFO mode is enabled */ - if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) - { - assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); - } - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Get the CR register value */ - tmp = hdma->Instance->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ - tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); - - /* Prepare the DMA Stream configuration */ - tmp |= hdma->Init.Channel | hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get memory burst and peripheral burst */ - tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; - } - - /* Write to DMA Stream CR register */ - hdma->Instance->CR = tmp; - - /* Get the FCR register value */ - tmp = hdma->Instance->FCR; - - /* Clear Direct mode and FIFO threshold bits */ - tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Prepare the DMA Stream FIFO configuration */ - tmp |= hdma->Init.FIFOMode; - - /* The FIFO threshold is not used when the FIFO mode is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get the FIFO threshold */ - tmp |= hdma->Init.FIFOThreshold; - - /* Check compatibility between FIFO threshold level and size of the memory burst */ - /* for INCR4, INCR8, INCR16 bursts */ - if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) - { - if (DMA_CheckFifoParam(hdma) != HAL_OK) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_PARAM; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_ERROR; - } - } - } - - /* Write to DMA Stream FCR */ - hdma->Instance->FCR = tmp; - - /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate - DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clear all interrupt flags */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the DMA peripheral - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the DMA peripheral state */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - /* Return error status */ - return HAL_BUSY; - } - - /* Check the parameters */ - assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Streamx */ - __HAL_DMA_DISABLE(hdma); - - /* Reset DMA Streamx control register */ - hdma->Instance->CR = 0U; - - /* Reset DMA Streamx number of data to transfer register */ - hdma->Instance->NDTR = 0U; - - /* Reset DMA Streamx peripheral address register */ - hdma->Instance->PAR = 0U; - - /* Reset DMA Streamx memory 0 address register */ - hdma->Instance->M0AR = 0U; - - /* Reset DMA Streamx memory 1 address register */ - hdma->Instance->M1AR = 0U; - - /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = 0x00000021U; - - /* Get DMA steam Base Address */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clean all callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferM1CpltCallback = NULL; - hdma->XferM1HalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Reset the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Reset the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Starts the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - - if(hdma->XferHalfCpltCallback != NULL) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Aborts the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * - * @note After disabling a DMA Stream, a check for wait until the DMA Stream is - * effectively disabled is added. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - uint32_t tickstart = HAL_GetTick(); - - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - } - return HAL_OK; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - return HAL_ERROR; - } - else - { - /* Set Abort State */ - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - } - - return HAL_OK; -} - -/** - * @brief Polling for transfer complete. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CompleteLevel Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. - * This model could be used for debug purpose. - * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t mask_cpltlevel; - uint32_t tickstart = HAL_GetTick(); - uint32_t tmpisr; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* No transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode and double buffering mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Transfer Complete flag */ - mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - } - else - { - /* Half Transfer Complete flag */ - mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - } - - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - tmpisr = regs->ISR; - - while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) - { - /* Check for the Timeout (Not applicable in circular mode)*/ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } - - /* Get the ISR register value */ - tmpisr = regs->ISR; - - if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - } - } - - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - HAL_DMA_Abort(hdma); - - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - } - else - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; - } - - return status; -} - -/** - * @brief Handles DMA interrupt request. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t tmpisr; - __IO uint32_t count = 0U; - uint32_t timeout = SystemCoreClock / 9600U; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - tmpisr = regs->ISR; - - /* Transfer Error Interrupt management ***************************************/ - if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { - /* Disable the transfer error interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TE); - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - } - } - /* FIFO Error Interrupt management ******************************************/ - if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) - { - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - } - } - /* Direct Mode Error Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) - { - /* Clear the direct mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - } - } - /* Half Transfer Complete Interrupt management ******************************/ - if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferM1HalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferM1HalfCpltCallback(hdma); - } - } - } - else - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the half transfer interrupt */ - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - } - } - /* Transfer Complete Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) - { - /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - - if(HAL_DMA_STATE_ABORT == hdma->State) - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - return; - } - - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferM1CpltCallback != NULL) - { - /* Transfer complete Callback for memory1 */ - hdma->XferM1CpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete Callback for memory0 */ - hdma->XferCpltCallback(hdma); - } - } - } - /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ - else - { - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the transfer complete interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - } - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - } - } - - /* manage error case */ - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - do - { - if (++count > timeout) - { - break; - } - } - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - } - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifier - * a DMA_HandleTypeDef structure as parameter. - * @param pCallback pointer to private callback function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) -{ - - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifier - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferM1CpltCallback = NULL; - hdma->XferM1HalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear DBM bit */ - hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); - - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @brief Returns the DMA Stream base address depending on stream number - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval Stream base address - */ -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) -{ - uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; - - /* lookup table for necessary bitshift of flags within status registers */ - static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; - hdma->StreamIndex = flagBitshiftOffset[stream_number]; - - if (stream_number > 3U) - { - /* return pointer to HISR and HIFCR */ - hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); - } - else - { - /* return pointer to LISR and LIFCR */ - hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); - } - - return hdma->StreamBaseAddress; -} - -/** - * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = hdma->Init.FIFOThreshold; - - /* Memory Data size equal to Byte */ - if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_FULL: - break; - default: - break; - } - } - - /* Memory Data size equal to Half-Word */ - else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_FULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - /* Memory Data size equal to Word */ - else - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_HALFFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_FULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - return status; -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c deleted file mode 100644 index 7167e77..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c +++ /dev/null @@ -1,313 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_dma_ex.c - * @author MCD Application Team - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the DMA Extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA Extension HAL driver can be used as follows: - (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function - for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. - - -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. - -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. - -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private Constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMAEx_Private_Functions - * @{ - */ -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - - -/** @addtogroup DMAEx_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer with interrupt - (+) Change on the fly the memory0 or memory1 address. - -@endverbatim - * @{ - */ - - -/** - * @brief Starts the multi_buffer DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - } - else - { - /* Process Locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Enable the double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Return error status */ - status = HAL_BUSY; - } - } - return status; -} - -/** - * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Check callback functions */ - if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) - { - hdma->ErrorCode = HAL_DMA_ERROR_PARAM; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Enable the Double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Change the memory0 or memory1 address on the fly. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param Address The new address - * @param memory the memory to be changed, This parameter can be one of - * the following values: - * MEMORY0 / - * MEMORY1 - * @note The MEMORY0 address can be changed only when the current transfer use - * MEMORY1 and the MEMORY1 address can be changed only when the current - * transfer use MEMORY0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) -{ - if(memory == MEMORY0) - { - /* change the memory0 address */ - hdma->Instance->M0AR = Address; - } - else - { - /* change the memory1 address */ - hdma->Instance->M1AR = Address; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMAEx_Private_Functions - * @{ - */ - -/** - * @brief Set the DMA Transfer parameter. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c deleted file mode 100644 index 04b5215..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ /dev/null @@ -1,547 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_exti.c - * @author MCD Application Team - * @brief EXTI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### EXTI Peripheral features ##### - ============================================================================== - [..] - (+) Each Exti line can be configured within this driver. - - (+) Exti line can be configured in 3 different modes - (++) Interrupt - (++) Event - (++) Both of them - - (+) Configurable Exti lines can be configured with 3 different triggers - (++) Rising - (++) Falling - (++) Both of them - - (+) When set in interrupt mode, configurable Exti lines have two different - interrupts pending registers which allow to distinguish which transition - occurs: - (++) Rising edge pending interrupt - (++) Falling - - (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can - be selected through multiplexer. - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). - (++) Choose the interrupt line number by setting "Line" member from - EXTI_ConfigTypeDef structure. - (++) Configure the interrupt and/or event mode using "Mode" member from - EXTI_ConfigTypeDef structure. - (++) For configurable lines, configure rising and/or falling trigger - "Trigger" member from EXTI_ConfigTypeDef structure. - (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" - member from GPIO_InitTypeDef structure. - - (#) Get current Exti configuration of a dedicated line using - HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - - (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). - (++) Provide exiting handle as first parameter. - (++) Provide which callback will be registered using one value from - EXTI_CallbackIDTypeDef. - (++) Provide callback function pointer. - - (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rule: - * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out - * of bounds [0,3] in following API : - * HAL_EXTI_SetConfigLine - * HAL_EXTI_GetConfigLine - * HAL_EXTI_ClearConfigLine - */ - -#ifdef HAL_EXTI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup EXTI_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * -@verbatim - =============================================================================== - ##### Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Set configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on EXTI configuration to be set. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_EXTI_LINE(pExtiConfig->Line)); - assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - - /* Assign line number to handle */ - hexti->Line = pExtiConfig->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); - - /* Configure rising trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) - { - EXTI->RTSR |= maskline; - } - else - { - EXTI->RTSR &= ~maskline; - } - - /* Configure falling trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) - { - EXTI->FTSR |= maskline; - } - else - { - EXTI->FTSR &= ~maskline; - } - - - /* Configure gpio port selection in case of gpio exti line */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - /* Configure interrupt mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) - { - EXTI->IMR |= maskline; - } - else - { - EXTI->IMR &= ~maskline; - } - - /* Configure event mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) - { - EXTI->EMR |= maskline; - } - else - { - EXTI->EMR &= ~maskline; - } - - return HAL_OK; -} - -/** - * @brief Get configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on structure to store Exti configuration. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* Store handle line number to configuration structure */ - pExtiConfig->Line = hexti->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Get core mode : interrupt */ - - /* Check if selected line is enable */ - if ((EXTI->IMR & maskline) != 0x00u) - { - pExtiConfig->Mode = EXTI_MODE_INTERRUPT; - } - else - { - pExtiConfig->Mode = EXTI_MODE_NONE; - } - - /* Get event mode */ - /* Check if selected line is enable */ - if ((EXTI->EMR & maskline) != 0x00u) - { - pExtiConfig->Mode |= EXTI_MODE_EVENT; - } - - /* Get default Trigger and GPIOSel configuration */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; - - /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - /* Check if configuration of selected line is enable */ - if ((EXTI->RTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; - } - - /* Get falling configuration */ - /* Check if configuration of selected line is enable */ - if ((EXTI->FTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; - } - - /* Get Gpio port selection for gpio lines */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u ); - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u); - } - } - - return HAL_OK; -} - -/** - * @brief Clear whole configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Clear interrupt mode */ - EXTI->IMR = (EXTI->IMR & ~maskline); - - /* 2] Clear event mode */ - EXTI->EMR = (EXTI->EMR & ~maskline); - - /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0x00u) - { - EXTI->RTSR = (EXTI->RTSR & ~maskline); - EXTI->FTSR = (EXTI->FTSR & ~maskline); - - /* Get Gpio port selection for gpio lines */ - if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - return HAL_OK; -} - -/** - * @brief Register callback for a dedicated Exti line. - * @param hexti Exti handle. - * @param CallbackID User callback identifier. - * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. - * @param pPendingCbfn function pointer to be stored as callback. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_EXTI_COMMON_CB_ID: - hexti->PendingCallback = pPendingCbfn; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Store line number as handle private field. - * @param hexti Exti handle. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - else - { - /* Store line number as handle private field */ - hexti->Line = ExtiLine; - - return HAL_OK; - } -} - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Handle EXTI interrupt request. - * @param hexti Exti handle. - * @retval none. - */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t maskline; - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Get pending bit */ - regval = (EXTI->PR & maskline); - if (regval != 0x00u) - { - /* Clear pending bit */ - EXTI->PR = maskline; - - /* Call callback */ - if (hexti->PendingCallback != NULL) - { - hexti->PendingCallback(); - } - } -} - -/** - * @brief Get interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be checked. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval 1 if interrupt is pending else 0. - */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* return 1 if bit is set else 0 */ - regval = ((EXTI->PR & maskline) >> linepos); - return regval; -} - -/** - * @brief Clear interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be clear. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval None. - */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Clear Pending bit */ - EXTI->PR = maskline; -} - -/** - * @brief Generate a software interrupt for a dedicated line. - * @param hexti Exti handle. - * @retval None. - */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Generate Software interrupt */ - EXTI->SWIER = maskline; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_EXTI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c deleted file mode 100644 index 2830da0..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ /dev/null @@ -1,775 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) 64 cache lines of 128 bits on I-Code - (+) 8 cache lines of 128 bits on D-Code - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F4xx devices. - - (#) FLASH Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: byte, half word, word and double word - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Wait for last FLASH operation according to its status - (++) Get error flag status by calling HAL_SetErrorCode() - - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the Instruction cache and the Data cache - (+) Reset the Instruction cache and the Data cache - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variable used for Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -/* Program operations */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); -static void FLASH_Program_Word(uint32_t Address, uint32_t Data); -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); -static void FLASH_SetErrorCode(void); - -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - } - else - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - pFlash.Address = Address; - - if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - } - else - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - } - - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t addresstmp = 0U; - - /* Check FLASH operation error flags */ -#if defined(FLASH_SR_RDERR) - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) -#else - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) -#endif /* FLASH_SR_RDERR */ - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) - { - /*return the faulty sector*/ - addresstmp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFFU; - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /*return the faulty bank*/ - addresstmp = pFlash.Bank; - } - else - { - /*return the faulty address*/ - addresstmp = pFlash.Address; - } - - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(addresstmp); - - /*Stop the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) - { - /*Nb of sector to erased can be decreased*/ - pFlash.NbSectorsToErase--; - - /* Check if there are still sectors to erase*/ - if(pFlash.NbSectorsToErase != 0U) - { - addresstmp = pFlash.Sector; - /*Indicate user which sector has been erased*/ - HAL_FLASH_EndOfOperationCallback(addresstmp); - - /*Increment sector number*/ - pFlash.Sector++; - addresstmp = pFlash.Sector; - FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); - } - else - { - /*No more sectors to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase sectors procedure*/ - pFlash.Sector = addresstmp = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - } - } - else - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /* MassErase ended. Return the selected bank */ - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Bank); - } - else - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Operation is completed, disable the PG, SER, SNB and MER Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); - - /* Disable End of FLASH Operation interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); - - /* Disable Error source interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Sectors Erase: Sector which has been erased - * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Sectors Erase: Sector number which returned an error - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be a combination of: - * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operationtimeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Clear Error Code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } -#if defined(FLASH_SR_RDERR) - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) -#else - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) -#endif /* FLASH_SR_RDERR */ - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* If there is no error flag set */ - return HAL_OK; - -} - -/** - * @brief Program a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and Vpp in the range 7V to 9V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - /* Program first word */ - *(__IO uint32_t*)Address = (uint32_t)Data; - - /* Barrier to ensure programming is performed in 2 steps, in right order - (independently of compiler optimization behavior) */ - __ISB(); - - /* Program second word */ - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); -} - - -/** - * @brief Program word (32-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Word(uint32_t Address, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; -} - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.1V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; -} - -/** - * @brief Program byte (8-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 1.8V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; -} - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - - /* Clear FLASH write protection error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - - /* Clear FLASH Programming alignment error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; - - /* Clear FLASH Programming parallelism error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; - - /* Clear FLASH Programming sequence error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); - } -#if defined(FLASH_SR_RDERR) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - - /* Clear FLASH Proprietary readout protection error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); - } -#endif /* FLASH_SR_RDERR */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; - - /* Clear FLASH Operation error pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); - } -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c deleted file mode 100644 index d99eace..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ /dev/null @@ -1,1347 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extension peripheral: - * + Extended programming operations functions - * - @verbatim - ============================================================================== - ##### Flash Extension features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and - STM32F429xx/439xx devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) PCROP protection for all banks - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx - devices. It includes - (#) FLASH Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: Erase sector, erase all sectors - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : - (++) Extended space (bank 2) erase function - (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) - (++) Dual Boot activation - (++) Write protection configuration for bank 2 - (++) PCROP protection configuration and control for both banks - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/* Option bytes control */ -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby); -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); -static uint8_t FLASH_OB_GetUser(void); -static uint16_t FLASH_OB_GetWRP(void); -static uint8_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetBOR(void); - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ - defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); -static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx - STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extension FLASH - programming operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] SectorError pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFFU means that all the sectors have been correctly erased) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /*Initialization of SectorError variable*/ - *SectorError = 0xFFFFFFFFU; - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - } - else - { - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - /* Erase by sector by sector to be done*/ - for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) - { - FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the SER and SNB Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty sector*/ - *SectorError = index; - break; - } - } - } - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - pFlash.Bank = pEraseInit->Banks; - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); - } - else - { - /* Erase by sector to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; - pFlash.NbSectorsToErase = pEraseInit->NbSectors; - pFlash.Sector = pEraseInit->Sector; - pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; - - /*Erase 1st sector and wait for IT*/ - FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); - } - - return status; -} - -/** - * @brief Program option bytes - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /*Write protection configuration*/ - if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); - } - } - - /*Read protection configuration*/ - if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - } - - /*USER configuration*/ - if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NO_RST, - pOBInit->USERConfig & OB_STDBY_NO_RST); - } - - /*BOR Level configuration*/ - if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; - - /*Get WRP*/ - pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR(); -} - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Program option bytes - * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OBEX(pAdvOBInit->OptionType)); - - /*Program PCROP option byte*/ - if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) - { - /* Check the parameters */ - assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ - defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ - status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || - STM32F413xx || STM32F423xx */ - } - else - { - /*Disable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ - defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ - status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || - STM32F413xx || STM32F423xx */ - } - } - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - /*Program BOOT config option byte*/ - if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) - { - status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); - } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - - return status; -} - -/** - * @brief Get the OBEX byte configuration - * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ - defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) - /*Get Sector*/ - pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ - /*Get Sector for Bank1*/ - pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); - - /*Get Sector for Bank2*/ - pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); - - /*Get Boot config OB*/ - pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || - STM32F413xx || STM32F423xx */ -} - -/** - * @brief Select the Protection Mode - * - * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted - * Global Read Out Protection modification (from level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ - * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) -{ - uint8_t optiontmp = 0xFF; - - /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - - /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); - - return HAL_OK; -} - -/** - * @brief Deselect the Protection Mode - * - * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted - * Global Read Out Protection modification (from level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ - * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) -{ - uint8_t optiontmp = 0xFF; - - /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - - /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); - - return HAL_OK; -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ - STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || - STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -/** - * @} - */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @param Banks Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * - * @retval HAL Status - */ -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - assert_param(IS_FLASH_BANK(Banks)); - - /* if the previous operation is completed, proceed to erase all sectors */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - - if (Banks == FLASH_BANK_BOTH) - { - /* bank1 & bank2 will be erased*/ - FLASH->CR |= FLASH_MER_BIT; - } - else if (Banks == FLASH_BANK_1) - { - /*Only bank1 will be erased*/ - FLASH->CR |= FLASH_CR_MER1; - } - else - { - /*Only bank2 will be erased*/ - FLASH->CR |= FLASH_CR_MER2; - } - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0U; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if (VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ - if (Sector > FLASH_SECTOR_11) - { - Sector += 4U; - } - /* If the previous operation is completed, proceed to erase the sector */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= tmp_psize; - CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); - FLASH->CR |= FLASH_CR_STRT; -} - -/** - * @brief Enable the write protection of the desired bank1 or bank 2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param WRPSector specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 - * @arg OB_WRP_SECTOR_All - * @note BANK2 starts from OB_WRP_SECTOR_12 - * - * @param Banks Enable write protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: WRP on all sectors of bank1 - * @arg FLASH_BANK_2: WRP on all sectors of bank2 - * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 - * - * @retval HAL FLASH State - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) - { - if (WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12)); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); - } - } - else - { - /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); - } - - /*Write protection on all sector of BANK2*/ - if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); - } - } - - } - return status; -} - -/** - * @brief Disable the write protection of the desired bank1 or bank 2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param WRPSector specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 - * @arg OB_WRP_Sector_All - * @note BANK2 starts from OB_WRP_SECTOR_12 - * - * @param Banks Disable write protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) - { - if (WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; - } - } - else - { - /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); - } - - /*Write protection on all sector of BANK2*/ - if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); - } - } - - } - - return status; -} - -/** - * @brief Configure the Dual Bank Boot. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param BootConfig specifies the Dual Bank Boot Option byte. - * This parameter can be one of the following values: - * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable - * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled - * @retval None - */ -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_BOOT(BootConfig)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Set Dual Bank Boot */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig; - } - - return status; -} - -/** - * @brief Enable the read/write protection (PCROP) of the desired - * sectors of Bank 1 and/or Bank 2. - * @note This function can be used only for STM32F42xxx/43xxx devices. - * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 - * @arg OB_PCROP_SECTOR__All - * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 - * @arg OB_PCROP_SECTOR__All - * @param Banks Enable PCROP protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: WRP on all sectors of bank1 - * @arg FLASH_BANK_2: WRP on all sectors of bank2 - * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) - { - assert_param(IS_OB_PCROP(SectorBank1)); - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; - } - else - { - assert_param(IS_OB_PCROP(SectorBank2)); - /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; - } - - /*Write protection on all sector of BANK2*/ - if (Banks == FLASH_BANK_BOTH) - { - assert_param(IS_OB_PCROP(SectorBank2)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; - } - } - - } - - return status; -} - - -/** - * @brief Disable the read/write protection (PCROP) of the desired - * sectors of Bank 1 and/or Bank 2. - * @note This function can be used only for STM32F42xxx/43xxx devices. - * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 - * @arg OB_PCROP_SECTOR__All - * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 - * @arg OB_PCROP_SECTOR__All - * @param Banks Disable PCROP protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: WRP on all sectors of bank1 - * @arg FLASH_BANK_2: WRP on all sectors of bank2 - * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) - { - assert_param(IS_OB_PCROP(SectorBank1)); - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); - } - else - { - /*Write protection done on sectors of BANK2*/ - assert_param(IS_OB_PCROP(SectorBank2)); - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); - } - - /*Write protection on all sector of BANK2*/ - if (Banks == FLASH_BANK_BOTH) - { - assert_param(IS_OB_PCROP(SectorBank2)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); - } - } - - } - - return status; - -} - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) -/** - * @brief Mass erase of FLASH memory - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @param Banks Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * - * @retval None - */ -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - assert_param(IS_FLASH_BANK(Banks)); - - /* If the previous operation is completed, proceed to erase all sectors */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0U; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if (VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* If the previous operation is completed, proceed to erase the sector */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - FLASH->CR |= tmp_psize; - CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); - FLASH->CR |= FLASH_CR_STRT; -} - -/** - * @brief Enable the write protection of the desired bank 1 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param WRPSector specifies the sector(s) to be write protected. - * The value of this parameter depend on device used within the same series - * - * @param Banks Enable write protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: WRP on all sectors of bank1 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); - } - - return status; -} - -/** - * @brief Disable the write protection of the desired bank 1 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param WRPSector specifies the sector(s) to be write protected. - * The value of this parameter depend on device used within the same series - * - * @param Banks Enable write protection on all the sectors for the specific bank - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: WRP on all sectors of bank1 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - assert_param(IS_FLASH_BANK(Banks)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; - } - - return status; -} -#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx - STM32F413xx || STM32F423xx */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ - defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Enable the read/write protection (PCROP) of the desired sectors. - * @note This function can be used only for STM32F401xx devices. - * @param Sector specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 - * @arg OB_PCROP_Sector_All - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(Sector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; - } - - return status; -} - - -/** - * @brief Disable the read/write protection (PCROP) of the desired sectors. - * @note This function can be used only for STM32F401xx devices. - * @param Sector specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 - * @arg OB_PCROP_Sector_All - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(Sector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector); - } - - return status; - -} -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx - STM32F413xx || STM32F423xx */ - -/** - * @brief Set the read protection level. - * @param Level specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(Level)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level; - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Iwdg Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby) -{ - uint8_t optiontmp = 0xFF; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); - } - - return status; -} - -/** - * @brief Set the BOR Level. - * @param Level specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(Level)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; - - return HAL_OK; - -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint8_t)(FLASH->OPTCR & 0xE0)); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint16_t FLASH Write Protection Option Bytes value - */ -static uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FLASH ReadOut Protection Status: - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint8_t FLASH_OB_GetRDP(void) -{ - uint8_t readstatus = OB_RDP_LEVEL_0; - - if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) - { - readstatus = OB_RDP_LEVEL_2; - } - else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) - { - readstatus = OB_RDP_LEVEL_0; - } - else - { - readstatus = OB_RDP_LEVEL_1; - } - - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @retval uint8_t The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -static uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @brief Flush the instruction and data caches - * @retval None - */ -void FLASH_FlushCaches(void) -{ - /* Flush instruction cache */ - if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - /* Reset instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - /* Enable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - } - - /* Flush data cache */ - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - /* Reset data cache */ - __HAL_FLASH_DATA_CACHE_RESET(); - /* Enable data cache */ - __HAL_FLASH_DATA_CACHE_ENABLE(); - } -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c deleted file mode 100644 index 952595b..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ /dev/null @@ -1,172 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_flash_ramfunc.c - * @author MCD Application Team - * @brief FLASH RAMFUNC module driver. - * This file provides a FLASH firmware functions which should be - * executed from internal SRAM - * + Stop/Start the flash interface while System Run - * + Enable/Disable the flash sleep while System Run - @verbatim - ============================================================================== - ##### APIs executed from Internal RAM ##### - ============================================================================== - [..] - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are be executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC - * @brief FLASH functions executed from RAM - * @{ - */ -#ifdef HAL_FLASH_MODULE_ENABLED -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Stop the flash interface while System Run - * @note This mode is only available for STM32F41xxx/STM32F446xx devices. - * @note This mode couldn't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) -{ - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Stop the flash interface while System Run */ - SET_BIT(PWR->CR, PWR_CR_FISSR); - - return HAL_OK; -} - -/** - * @brief Start the flash interface while System Run - * @note This mode is only available for STM32F411xx/STM32F446xx devices. - * @note This mode couldn't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) -{ - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Start the flash interface while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FISSR); - - return HAL_OK; -} - -/** - * @brief Enable the flash sleep while System Run - * @note This mode is only available for STM32F41xxx/STM32F446xx devices. - * @note This mode could n't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) -{ - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable the flash sleep while System Run */ - SET_BIT(PWR->CR, PWR_CR_FMSSR); - - return HAL_OK; -} - -/** - * @brief Disable the flash sleep while System Run - * @note This mode is only available for STM32F41xxx/STM32F446xx devices. - * @note This mode couldn't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) -{ - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Disable the flash sleep while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c deleted file mode 100644 index b3ce9bb..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ /dev/null @@ -1,533 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each - port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software - in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) Alternate function mode - (+) External interrupt/event lines - - [..] - During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ - -#define GPIO_NUMBER 16U -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize and de-initialize the GPIOs - to be ready for use. - -@endverbatim - * @{ - */ - - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or - * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position; - uint32_t ioposition = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t temp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - - /* Configure the port pins */ - for(position = 0U; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = 0x01U << position; - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - - if(iocurrent == ioposition) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Output or Alternate function mode selection */ - if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - temp |= (GPIO_Init->Speed << (position * 2U)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - GPIOx->OTYPER = temp; - } - - if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - { - /* Check the parameters */ - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); - temp |= ((GPIO_Init->Pull) << (position * 2U)); - GPIOx->PUPDR = temp; - } - - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3U]; - temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2U]; - temp &= ~(0x0FU << (4U * (position & 0x03U))); - temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - SYSCFG->EXTICR[position >> 2U] = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - { - temp |= iocurrent; - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - { - temp |= iocurrent; - } - EXTI->FTSR = temp; - - temp = EXTI->EMR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - { - temp |= iocurrent; - } - EXTI->EMR = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & EXTI_IT) != 0x00U) - { - temp |= iocurrent; - } - EXTI->IMR = temp; - } - } - } -} - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or - * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position; - uint32_t ioposition = 0x00U; - uint32_t iocurrent = 0x00U; - uint32_t tmp = 0x00U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Configure the port pins */ - for(position = 0U; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = 0x01U << position; - /* Get the current IO position */ - iocurrent = (GPIO_Pin) & ioposition; - - if(iocurrent == ioposition) - { - /*------------------------- EXTI Mode Configuration --------------------*/ - tmp = SYSCFG->EXTICR[position >> 2U]; - tmp &= (0x0FU << (4U * (position & 0x03U))); - if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~((uint32_t)iocurrent); - EXTI->EMR &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->FTSR &= ~((uint32_t)iocurrent); - EXTI->RTSR &= ~((uint32_t)iocurrent); - - /* Configure the External Interrupt or event for the current IO */ - tmp = 0x0FU << (4U * (position & 0x03U)); - SYSCFG->EXTICR[position >> 2U] &= ~tmp; - } - - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floating Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - } - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or - * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or - * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; - } -} - -/** - * @brief Toggles the specified GPIO pins. - * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or - * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin Specifies the pins to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t odr; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* get current Output Data Register value */ - odr = GPIOx->ODR; - - /* Set selected pins that were at low level, and reset ones that were high */ - GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family - * @param GPIO_Pin specifies the port bit to be locked. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKR register. This read is mandatory to complete key lock sequence */ - tmp = GPIOx->LCKR; - - /* Read again in order to confirm lock is active */ - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin Specifies the pins connected EXTI line - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callbacks. - * @param GPIO_Pin Specifies the pins connected EXTI line - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c deleted file mode 100644 index b4bb483..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ /dev/null @@ -1,571 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWR_Private_Constants - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT 0x00010000U -#define PVD_MODE_EVT 0x00020000U -#define PVD_RISING_EDGE 0x00000001U -#define PVD_FALLING_EDGE 0x00000002U -/** - * @} - */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @note The following sequence is required to bypass the delay between - * DBP bit programming and the effective enabling of the backup domain. - * Please check the Errata Sheet for more details under "Possible delay - * in backup domain protection disabling/enabling after programming the - * DBP bit" section. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - __IO uint32_t dummyread; - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; - dummyread = PWR->CR; - UNUSED(dummyread); -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @note The following sequence is required to bypass the delay between - * DBP bit programming and the effective disabling of the backup domain. - * Please check the Errata Sheet for more details under "Possible delay - * in backup domain protection disabling/enabling after programming the - * DBP bit" section. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - __IO uint32_t dummyread; - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; - dummyread = PWR->CR; - UNUSED(dummyread); -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** Wake-up pin configuration *** - ================================ - [..] - (+) Wake-up pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. - (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 - (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - -@@- The Regulator parameter is not used for the STM32F4 family - and is kept as parameter just to maintain compatibility with the - lower power families (STM32L). - (+) Exit: - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. - It can be switched on again by software after exiting the Stop mode using - the HAL_PWREx_DisableFlashPowerDown() function. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (+) Exit: - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - (+) - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (++) Entry: - (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (++) Exit: - (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wake-up (AWU) from low-power mode *** - ============================================= - [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wake-up event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wake-up mode). - - (+) RTC auto-wake-up (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to - configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the Wake-up PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - /* Enable the wake up pin */ - SET_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Disables the Wake-up PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - /* Disable the wake up pin */ - CLEAR_BIT(PWR->CSR, WakeUpPinx); -} - -/** - * @brief Enters Sleep mode. - * - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * - * @note In Sleep mode, the systick is stopped to avoid exit from this mode with - * systick interrupt when used as time base for Timeout - * - * @param Regulator Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @note This parameter is not used for the STM32F4 family and is kept as parameter - * just to maintain compatibility with the lower power families. - * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wake-up event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - SET_BIT(PWR->CR, PWR_CR_PDDS); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR Exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c deleted file mode 100644 index 77f9c35..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c +++ /dev/null @@ -1,600 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of PWR extension peripheral: - * + Peripheral Extended features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWREx_Private_Constants - * @{ - */ -#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U -#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U -#define PWR_BKPREG_TIMEOUT_VALUE 1000U -#define PWR_VOSRDY_TIMEOUT_VALUE 1000U -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== - - *** Main and Backup Regulators configuration *** - ================================================ - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the HAL_PWREx_EnableBkUpReg() function to - enable the low power backup regulator. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by a tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the Flash - programming manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() - macro which configure VOS bit in PWR_CR register - - Refer to the product datasheets for more details. - - *** FLASH Power Down configuration **** - ======================================= - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. - - (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL - is OFF and the HSI or HSE clock source is selected as system clock. - The new value programmed is active only when the PLL is ON. - When the PLL is OFF, the voltage scale 3 is automatically selected. - Refer to the datasheets for more details. - - *** Over-Drive and Under-Drive configuration **** - ================================================= - [..] - (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has - 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and - disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator - supplies a low power voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) -{ - uint32_t tickstart = 0U; - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Disables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) -{ - uint32_t tickstart = 0U; - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Enables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_EnableFlashPowerDown(void) -{ - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_DisableFlashPowerDown(void) -{ - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; -} - -/** - * @brief Return Voltage Scaling Range. - * @retval The configured scale for the regulator voltage(VOS bit field). - * The returned value can be one of the following: - * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - return (PWR->CR & PWR_CR_VOS); -} - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, - * the maximum value of fHCLK = 168 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, - * the maximum value of fHCLK = 144 MHz. - * @note When moving from Range 1 to Range 2, the system frequency must be decreased to - * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. - * When moving from Range 2 to Range 1, the system frequency can be increased to - * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t tickstart = 0U; - - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - - /* Enable PWR RCC Clock Peripheral */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Set Range */ - __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) - { - if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ - defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ - defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, - * the maximum value of fHCLK is 168 MHz. It can be extended to - * 180 MHz by activating the over-drive mode. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, - * the maximum value of fHCLK is 144 MHz. It can be extended to, - * 168 MHz by activating the over-drive mode. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, - * the maximum value of fHCLK is 120 MHz. - * @note To update the system clock frequency(SYSCLK): - * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). - * - Call the HAL_RCC_OscConfig() to configure the PLL. - * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. - * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). - * @note The scale can be modified only when the HSI or HSE clock source is selected - * as system clock source, otherwise the API returns HAL_ERROR. - * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits - * value in the PWR_CR1 register are not taken in account. - * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. - * @note The new voltage scale is active only when the PLL is ON. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t tickstart = 0U; - - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - - /* Enable PWR RCC Clock Peripheral */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - /* Disable the main PLL */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set Range */ - __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - - /* Enable the main PLL */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) - { - if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ - defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Enables Main Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. - * @retval None - */ -void HAL_PWREx_EnableMainRegulatorLowVoltage(void) -{ - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables Main Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xxdevices. - * @retval None - */ -void HAL_PWREx_DisableMainRegulatorLowVoltage(void) -{ - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables Low Power Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. - * @retval None - */ -void HAL_PWREx_EnableLowRegulatorLowVoltage(void) -{ - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables Low Power Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. - * @retval None - */ -void HAL_PWREx_DisableLowRegulatorLowVoltage(void) -{ - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; -} - -#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || - STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Activates the Over-Drive mode. - * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. - * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) -{ - uint32_t tickstart = 0U; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ - __HAL_PWR_OVERDRIVE_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Enable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Deactivates the Over-Drive mode. - * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. - * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) -{ - uint32_t tickstart = 0U; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Disable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Disable the Over-drive */ - __HAL_PWR_OVERDRIVE_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * - * @note When exiting Stop mode by issuing an interrupt or a wake-up event, - * the HSI RC oscillator is selected as system clock. - * - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param Regulator specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction - * @retval None - */ -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg1 = 0U; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable the Under-drive Mode ---------------------------------------------*/ - /* Clear Under-drive flag */ - __HAL_PWR_CLEAR_ODRUDR_FLAG(); - - /* Enable the Under-drive */ - __HAL_PWR_UNDERDRIVE_ENABLE(); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg1 = PWR->CR; - /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ - tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tmpreg1 |= Regulator; - - /* Store the new value */ - PWR->CR = tmpreg1; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - return HAL_OK; -} - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c deleted file mode 100644 index f187348..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ /dev/null @@ -1,1122 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle - after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle - after the clock enable bit is set on the hardware register - - [..] - Implemented Workaround: - (+) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/* Private macro -------------------------------------------------------------*/ -#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define MCO2_GPIO_PORT GPIOC -#define MCO2_PIN GPIO_PIN_9 -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 168 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M4 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - - [..] System, AHB and APB busses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum - frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. - Depending on the device voltage range, the maximum frequency should - be adapted accordingly (refer to the product datasheets for more details). - - (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, - the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. - Depending on the device voltage range, the maximum frequency should - be adapted accordingly (refer to the product datasheets for more details). - - (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. - Depending on the device voltage range, the maximum frequency should - be adapted accordingly (refer to the product datasheets for more details). - - (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. - Depending on the device voltage range, the maximum frequency should - be adapted accordingly (refer to the product datasheets for more details). - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - return HAL_OK; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this API. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this API. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart, pll_config; - - /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ - (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->PLLCFGR; -#if defined (RCC_PLLCFGR_PLLR) - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) -#else - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) -#endif - { - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart; - - /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - /* Set the highest APBx dividers in order to ensure that we do not go through - a non-spec phase whatever we decrease or increase HCLK. */ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - } - - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - } - - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings */ - HAL_InitTick (uwTickPrio); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - -@endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). - * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). - * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv specifies the MCOx prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have - * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef GPIO_InitStruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - /* RCC_MCO1 */ - if(RCC_MCOx == RCC_MCO1) - { - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO1 Clock Enable */ - __MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); - - /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ -#if defined(RCC_CFGR_MCO1EN) - __HAL_RCC_MCO1_ENABLE(); -#endif /* RCC_CFGR_MCO1EN */ - } -#if defined(RCC_CFGR_MCO2) - else - { - assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - - /* MCO2 Clock Enable */ - __MCO2_CLK_ENABLE(); - - /* Configure the MCO2 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO2_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); - - /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ -#if defined(RCC_CFGR_MCO2EN) - __HAL_RCC_MCO2_ENABLE(); -#endif /* RCC_CFGR_MCO2EN */ - } -#endif /* RCC_CFGR_MCO2 */ -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; -} - -/** - * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -__weak uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; - uint32_t sysclockfreq = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); - - sysclockfreq = pllvco/pllp; - break; - } - default: - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); -} - -/** - * @brief Configures the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval None - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c deleted file mode 100644 index 5076628..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ /dev/null @@ -1,3784 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCCEx HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register are set to their reset values. - -@endverbatim - * @{ - */ - -#if defined(STM32F446xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; - uint32_t plli2sp = 0U; - uint32_t plli2sq = 0U; - uint32_t plli2sr = 0U; - uint32_t pllsaip = 0U; - uint32_t pllsaiq = 0U; - uint32_t plli2sused = 0U; - uint32_t pllsaiused = 0U; - - /* Check the peripheral clock selection parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------ I2S APB1 configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- I2S APB2 configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*--------------------------- SAI1 configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - { - pllsaiused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*-------------------------- SAI2 configuration ----------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - - /* Configure SAI2 Clock source */ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - { - pllsaiused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------------- RTC configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- TIM configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - /* Configure Timer Prescaler */ - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- FMPI2C1 Configuration -----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - - /* Configure the FMPI2C1 clock source */ - __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------ CEC Configuration -------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - { - /* Check the parameters */ - assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - - /* Configure the CEC clock source */ - __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*----------------------------- CLK48 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the CLK48 clock source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - - /* Enable the PLLSAI when it's used as clock source for CLK48 */ - if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) - { - pllsaiused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------------- SDIO Configuration -------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - - /* Configure the SDIO clock source */ - __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------ SPDIFRX Configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - /* Check the parameters */ - assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); - - /* Configure the SPDIFRX clock source */ - __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); - /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ - if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- PLLI2S Configuration ------------------------*/ - /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, - I2S on APB2 or SPDIFRX */ - if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) - { - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* check for common PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - { - /* Check for PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - /* Check for PLLI2S/DIVQ parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------------- PLLSAI Configuration -----------------------*/ - /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ - if(pllsaiused == 1U) - { - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - { - /* check for PLLSAIQ Parameter */ - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - /* check for PLLSAI/DIVQ Parameter */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ - /* In Case of PLLI2S is selected as source clock for CLK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* Configure the PLLSAI division factors */ - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ - /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U); - } - - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\ - RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\ - RCC_PERIPHCLK_SPDIFRX; - - /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); - - /* Get the SAI1 clock configuration ----------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - - /* Get the SAI2 clock configuration ----------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - - /* Get the I2S APB1 clock configuration ------------------------------------*/ - PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - - /* Get the I2S APB2 clock configuration ------------------------------------*/ - PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - - /* Get the RTC Clock configuration -----------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the CEC clock configuration -----------------------------------------*/ - PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - - /* Get the FMPI2C1 clock configuration -------------------------------------*/ - PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - - /* Get the CLK48 clock configuration ----------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDIO clock configuration ----------------------------------------*/ - PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - - /* Get the SPDIFRX clock configuration -------------------------------------*/ - PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); - - /* Get the TIM Prescaler configuration -------------------------------------*/ - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock - * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock - * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock - * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t tmpreg1 = 0U; - /* This variable used to store the SAI clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - /* This variable used to store the SAI clock source */ - uint32_t saiclocksource = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: - { - saiclocksource = RCC->DCKCFGR; - saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); - switch (saiclocksource) - { - case 0U: /* PLLSAI is the clock source for SAI*/ - { - /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); - } - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; - frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); - frequency = frequency/(tmpreg1); - break; - } - case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ - case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; - frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); - frequency = frequency/(tmpreg1); - break; - } - case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ - case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ - { - /* Configure the PLLI2S division factor */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - /* SAI_CLK_x = PLL_VCO Output/PLLR */ - tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; - frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1); - break; - } - case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - frequency = (uint32_t)(HSI_VALUE); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - frequency = (uint32_t)(HSE_VALUE); - } - break; - } - default : - { - break; - } - } - break; - } - case RCC_PERIPHCLK_I2S_APB1: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_PLLI2S: - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_PLLR: - { - /* Configure the PLL division factor R */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); - /* I2S_CLK = PLL_VCO Output/PLLR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); - break; - } - /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ - case RCC_I2SAPB1CLKSOURCE_PLLSRC: - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - frequency = HSE_VALUE; - } - else - { - frequency = HSI_VALUE; - } - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - case RCC_PERIPHCLK_I2S_APB2: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_PLLI2S: - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_PLLR: - { - /* Configure the PLL division factor R */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); - /* I2S_CLK = PLL_VCO Output/PLLR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); - break; - } - /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ - case RCC_I2SAPB2CLKSOURCE_PLLSRC: - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - frequency = HSE_VALUE; - } - else - { - frequency = HSI_VALUE; - } - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F446xx */ - -#if defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC, RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; - uint32_t pllsaip = 0U; - uint32_t pllsaiq = 0U; - uint32_t pllsair = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*--------------------------- CLK48 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the CLK48 clock source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------ SDIO Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - - /* Configure the SDIO clock source */ - __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ - /*------------------- Common configuration SAI/I2S -------------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /*---------------------- I2S configuration -------------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) - { - /* Check the PLLI2S division factors */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Configure the PLLI2S multiplication and division factors */ - __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ - /*----------------------- Common configuration SAI/LTDC --------------------*/ - /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for these peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && - (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) - { - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) - { - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); - /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*---------------------------- LTDC configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - { - assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); - /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } - - /*---------------------------- CLK48 configuration ------------------------*/ - /* Configure the PLLSAI when it is used as clock source for CLK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && - (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) - { - assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - - /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); - } - - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - - /*--------------------------------------------------------------------------*/ - - /*---------------------------- RTC configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- TIM configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - return HAL_OK; -} - -/** - * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\ - RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; - - /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); - PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); - /* Get the RTC Clock configuration -----------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the CLK48 clock configuration -------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDIO clock configuration ----------------------------------------*/ - PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* This variable used to store the I2S clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_I2S: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SCLKSOURCE_PLLI2S: - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F469xx || STM32F479xx */ - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; -#if defined(STM32F413xx) || defined(STM32F423xx) - uint32_t plli2sq = 0U; -#endif /* STM32F413xx || STM32F423xx */ - uint32_t plli2sused = 0U; - - /* Check the peripheral clock selection parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------------------- I2S APB1 configuration ---------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------------------- I2S APB2 configuration ---------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - -#if defined(STM32F413xx) || defined(STM32F423xx) - /*----------------------- SAI1 Block A configuration -----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) - { - plli2sused = 1U; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) - { - /* Check for PLL/DIVR parameters */ - assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ - __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); - } - } - /*--------------------------------------------------------------------------*/ - - /*---------------------- SAI1 Block B configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) - { - plli2sused = 1U; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) - { - /* Check for PLL/DIVR parameters */ - assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ - __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); - } - } - /*--------------------------------------------------------------------------*/ -#endif /* STM32F413xx || STM32F423xx */ - - /*------------------------------------ RTC configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------------ TIM configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - /* Configure Timer Prescaler */ - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------------- FMPI2C1 Configuration --------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - - /* Configure the FMPI2C1 clock source */ - __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------------- CLK48 Configuration ----------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the SDIO clock source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - - /* Enable the PLLI2S when it's used as clock source for CLK48 */ - if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) - { - plli2sused = 1U; - } - } - /*--------------------------------------------------------------------------*/ - - /*------------------------------------- SDIO Configuration -----------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - - /* Configure the SDIO clock source */ - __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*-------------------------------------- PLLI2S Configuration --------------*/ - /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or - I2S on APB2*/ - if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) - { - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* check for common PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection)); - assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - /*-------------------- Set the PLL I2S clock -----------------------------*/ - __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); - - /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ))) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - -#if defined(STM32F413xx) || defined(STM32F423xx) - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) - { - /* Check for PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - /* Check for PLLI2S/DIVR parameters */ - assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); - - /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); - } -#endif /* STM32F413xx || STM32F423xx */ - - /*----------------- In Case of PLLI2S is just selected ------------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ - /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - /*--------------------------------------------------------------------------*/ - - /*-------------------- DFSDM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*-------------------- DFSDM1 Audio clock source configuration -------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); - - /* Configure the DFSDM1 Audio interface clock source */ - __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } - /*--------------------------------------------------------------------------*/ - -#if defined(STM32F413xx) || defined(STM32F423xx) - /*-------------------- DFSDM2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*-------------------- DFSDM2 Audio clock source configuration -------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection)); - - /* Configure the DFSDM1 Audio interface clock source */ - __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- LPTIM1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - - /* Configure the LPTIM1 clock source */ - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - /*--------------------------------------------------------------------------*/ -#endif /* STM32F413xx || STM32F423xx */ - - return HAL_OK; -} - -/** - * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\ - RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ - RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 |\ - RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB; -#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 |\ - RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ - RCC_PERIPHCLK_DFSDM1_AUDIO; -#endif /* STM32F413xx || STM32F423xx */ - - - - /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); -#if defined(STM32F413xx) || defined(STM32F423xx) - /* Get the PLL/PLLI2S division factors -------------------------------------*/ - PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); - PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); -#endif /* STM32F413xx || STM32F423xx */ - - /* Get the I2S APB1 clock configuration ------------------------------------*/ - PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - - /* Get the I2S APB2 clock configuration ------------------------------------*/ - PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - - /* Get the RTC Clock configuration -----------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the FMPI2C1 clock configuration -------------------------------------*/ - PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - - /* Get the CLK48 clock configuration ---------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDIO clock configuration ----------------------------------------*/ - PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - - /* Get the DFSDM1 clock configuration --------------------------------------*/ - PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - - /* Get the DFSDM1 Audio clock configuration --------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - -#if defined(STM32F413xx) || defined(STM32F423xx) - /* Get the DFSDM2 clock configuration --------------------------------------*/ - PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); - - /* Get the DFSDM2 Audio clock configuration --------------------------------*/ - PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); - - /* Get the LPTIM1 clock configuration --------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the SAI1 Block Aclock configuration ---------------------------------*/ - PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); - - /* Get the SAI1 Block B clock configuration --------------------------------*/ - PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); -#endif /* STM32F413xx || STM32F423xx */ - - /* Get the TIM Prescaler configuration -------------------------------------*/ - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(I2S..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock - * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* This variable used to store the I2S clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_I2S_APB1: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_PLLI2S: - { - if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - } - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_PLLR: - { - /* Configure the PLL division factor R */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); - /* I2S_CLK = PLL_VCO Output/PLLR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); - break; - } - /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ - case RCC_I2SAPB1CLKSOURCE_PLLSRC: - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - frequency = HSE_VALUE; - } - else - { - frequency = HSI_VALUE; - } - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - case RCC_PERIPHCLK_I2S_APB2: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_PLLI2S: - { - if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - } - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_PLLR: - { - /* Configure the PLL division factor R */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); - /* I2S_CLK = PLL_VCO Output/PLLR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); - break; - } - /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ - case RCC_I2SAPB2CLKSOURCE_PLLSRC: - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - frequency = HSE_VALUE; - } - else - { - frequency = HSI_VALUE; - } - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the - * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup - * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*---------------------------- RTC configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- TIM configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- FMPI2C1 Configuration -----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - - /* Configure the FMPI2C1 clock source */ - __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- LPTIM1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - - /* Configure the LPTIM1 clock source */ - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*---------------------------- I2S Configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); - - /* Configure the I2S clock source */ - __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); - } - - return HAL_OK; -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } - /* Get the FMPI2C1 clock configuration -------------------------------------*/ - PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - - /* Get the I2S clock configuration -----------------------------------------*/ - PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); - - -} -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* This variable used to store the I2S clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_I2S: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPBCLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ - case RCC_I2SAPBCLKSOURCE_PLLR: - { - /* Configure the PLL division factor R */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLL_VCO Output = PLL_VCO Input * PLLN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); - /* I2S_CLK = PLL_VCO Output/PLLR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); - break; - } - /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ - case RCC_I2SAPBCLKSOURCE_PLLSRC: - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - frequency = HSE_VALUE; - } - else - { - frequency = HSI_VALUE; - } - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) and RCC_BDCR register are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ - /*----------------------- Common configuration SAI/I2S ---------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /*---------------------------- I2S configuration -------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) - { - /* Check the PLLI2S division factors */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Configure the PLLI2S multiplication and division factors */ - __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - /*--------------------------------------------------------------------------*/ - - /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ - /*----------------------- Common configuration SAI/LTDC --------------------*/ - /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) - { - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) - { - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*---------------------------- LTDC configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - { - assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - - /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- RTC configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - /*--------------------------------------------------------------------------*/ - - /*---------------------------- TIM configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - return HAL_OK; -} - -/** - * @brief Configures the PeriphClkInit according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); - PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); - /* Get the RTC Clock configuration -----------------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* This variable used to store the I2S clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_I2S: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SCLKSOURCE_PLLI2S: - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the - * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup - * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg1 = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*---------------------------- I2S configuration ---------------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); -#if defined(STM32F411xE) - assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); -#endif /* STM32F411xE */ - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - -#if defined(STM32F411xE) - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); -#else - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); -#endif /* STM32F411xE */ - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - - /*---------------------------- RTC configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); - if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg1; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) - /*---------------------------- TIM configuration ---------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ - return HAL_OK; -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; - - /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); -#if defined(STM32F411xE) - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); -#endif /* STM32F411xE */ - /* Get the RTC Clock configuration -----------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) - /* Get the TIM Prescaler configuration -------------------------------------*/ - if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ -} - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - /* This variable used to store the I2S clock frequency (value in Hz) */ - uint32_t frequency = 0U; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0U; - uint32_t srcclk = 0U; - /* This variable used to store the VCO Output (value in Hz) */ - uint32_t vcooutput = 0U; - switch (PeriphClk) - { - case RCC_PERIPHCLK_I2S: - { - /* Get the current I2S source */ - srcclk = __HAL_RCC_GET_I2S_SOURCE(); - switch (srcclk) - { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: - { - /* Set the I2S clock to the external clock value */ - frequency = EXTERNAL_CLOCK_VALUE; - break; - } - /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ - case RCC_I2SCLKSOURCE_PLLI2S: - { -#if defined(STM32F411xE) - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } -#else - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* Get the I2S source clock value */ - vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } -#endif /* STM32F411xE */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); - /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ - frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); - break; - } - /* Clock not enabled for I2S*/ - default: - { - frequency = 0U; - break; - } - } - break; - } - } - return frequency; -} -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Select LSE mode - * - * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. - * - * @param Mode specifies the LSE mode. - * This parameter can be one of the following values: - * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection - * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection - * @retval None - */ -void HAL_RCCEx_SelectLSEMode(uint8_t Mode) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_MODE(Mode)); - if(Mode == RCC_LSE_HIGHDRIVE_MODE) - { - SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } - else - { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } -} - -#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * -@verbatim - =============================================================================== - ##### Extended clock management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the - activation or deactivation of PLLI2S, PLLSAI. -@endverbatim - * @{ - */ - -#if defined(RCC_PLLI2S_SUPPORT) -/** - * @brief Enable PLLI2S. - * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that - * contains the configuration information for the PLLI2S - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) -{ - uint32_t tickstart; - - /* Check for parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); -#if defined(RCC_PLLI2SCFGR_PLLI2SM) - assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); -#endif /* RCC_PLLI2SCFGR_PLLI2SM */ -#if defined(RCC_PLLI2SCFGR_PLLI2SP) - assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ -#if defined(RCC_PLLI2SCFGR_PLLI2SQ) - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); -#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Wait till PLLI2S is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Configure the PLLI2S division factors */ -#if defined(STM32F446xx) - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ - /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ - PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ - defined(STM32F413xx) || defined(STM32F423xx) - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ - /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ - PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F469xx) || defined(STM32F479xx) - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ - /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#elif defined(STM32F411xE) - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); -#else - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); -#endif /* STM32F446xx */ - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Wait till PLLI2S is ready */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable PLLI2S. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) -{ - uint32_t tickstart; - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Wait till PLLI2S is disabled */ - tickstart = HAL_GetTick(); - while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) -/** - * @brief Enable PLLSAI. - * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that - * contains the configuration information for the PLLSAI - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) -{ - uint32_t tickstart; - - /* Check for parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); - assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); -#if defined(RCC_PLLSAICFGR_PLLSAIM) - assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); -#endif /* RCC_PLLSAICFGR_PLLSAIM */ -#if defined(RCC_PLLSAICFGR_PLLSAIP) - assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); -#endif /* RCC_PLLSAICFGR_PLLSAIP */ -#if defined(RCC_PLLSAICFGR_PLLSAIR) - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - - /* Disable the PLLSAI */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Wait till PLLSAI is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Configure the PLLSAI division factors */ -#if defined(STM32F446xx) - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ - /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ - /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ - /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ - PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); -#elif defined(STM32F469xx) || defined(STM32F479xx) - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ - /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ - /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ - /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ - PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); -#else - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ - /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ - /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); -#endif /* STM32F446xx */ - - /* Enable the PLLSAI */ - __HAL_RCC_PLLSAI_ENABLE(); - - /* Wait till PLLSAI is ready */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable PLLSAI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) -{ - uint32_t tickstart; - - /* Disable the PLLSAI */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Wait till PLLSAI is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -#endif /* RCC_PLLSAI_SUPPORT */ - -/** - * @} - */ - -#if defined(STM32F446xx) -/** - * @brief Returns the SYSCLK frequency - * - * @note This function implementation is valid only for STM32F446xx devices. - * @note This function add the PLL/PLLR System clock source - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t pllm = 0U; - uint32_t pllvco = 0U; - uint32_t pllp = 0U; - uint32_t pllr = 0U; - uint32_t sysclockfreq = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); - - sysclockfreq = pllvco/pllp; - break; - } - case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); - - sysclockfreq = pllvco/pllr; - break; - } - default: - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} -#endif /* STM32F446xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL, PLLI2S and PLLSAI OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart; - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Set HSION bit to the reset value */ - SET_BIT(RCC->CR, RCC_CR_HSION); - - /* Wait till HSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set HSITRIM[4:0] bits to the reset value */ - SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Wait till clock switch is ready */ - while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear HSEON, HSEBYP and CSSON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); - - /* Wait till HSE is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear PLLON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); - - /* Wait till PLL is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - -#if defined(RCC_PLLI2S_SUPPORT) - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset PLLI2SON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); - - /* Wait till PLLI2S is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } -#endif /* RCC_PLLI2S_SUPPORT */ - -#if defined(RCC_PLLSAI_SUPPORT) - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset PLLSAI bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); - - /* Wait till PLLSAI is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } -#endif /* RCC_PLLSAI_SUPPORT */ - - /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ - defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; -#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) - RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; -#else - RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ - - /* Reset PLLI2SCFGR register to default value */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ - defined(STM32F423xx) || defined(STM32F446xx) - RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; -#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; -#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; -#elif defined(STM32F411xE) - RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ - - /* Reset PLLSAICFGR register */ -#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; -#elif defined(STM32F446xx) - RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ - - /* Disable all interrupts */ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); - -#if defined(RCC_CIR_PLLI2SRDYIE) - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); -#endif /* RCC_CIR_PLLI2SRDYIE */ - -#if defined(RCC_CIR_PLLSAIRDYIE) - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); -#endif /* RCC_CIR_PLLSAIRDYIE */ - - /* Clear all interrupt flags */ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); - -#if defined(RCC_CIR_PLLI2SRDYC) - SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); -#endif /* RCC_CIR_PLLI2SRDYC */ - -#if defined(RCC_CIR_PLLSAIRDYC) - SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); -#endif /* RCC_CIR_PLLSAIRDYC */ - - /* Clear LSION bit */ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); - - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; - - /* Adapt Systick interrupt period */ - if(HAL_InitTick(uwTickPrio) != HAL_OK) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } -} - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this API. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this API. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note This function add the PLL/PLLR factor management during PLL configuration this feature - * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart, pll_config; - - /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ -#if defined(STM32F446xx) - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) -#else - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) -#endif /* STM32F446xx */ - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ -#if defined(STM32F446xx) - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) -#else - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) -#endif /* STM32F446xx */ - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ - (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ - (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->PLLCFGR; -#if defined (RCC_PLLCFGR_PLLR) - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) -#else - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) -#endif - { - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. - * - * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. - * @note This function add the PLL/PLLR factor management - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); -} -#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c deleted file mode 100644 index 1ca1781..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ /dev/null @@ -1,7621 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + TIM Time Base Initialization - * + TIM Time Base Start - * + TIM Time Base Start Interruption - * + TIM Time Base Start DMA - * + TIM Output Compare/PWM Initialization - * + TIM Output Compare/PWM Channel Configuration - * + TIM Output Compare/PWM Start - * + TIM Output Compare/PWM Start Interruption - * + TIM Output Compare/PWM Start DMA - * + TIM Input Capture Initialization - * + TIM Input Capture Channel Configuration - * + TIM Input Capture Start - * + TIM Input Capture Start Interruption - * + TIM Input Capture Start DMA - * + TIM One Pulse Initialization - * + TIM One Pulse Channel Configuration - * + TIM One Pulse Start - * + TIM Encoder Interface Initialization - * + TIM Encoder Interface Start - * + TIM Encoder Interface Start Interruption - * + TIM Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + TIM OCRef clear configuration - * + TIM External Clock configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental encoder for positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_TIM_RegisterCallback() to register a callback. - HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - - [..] - Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - - [..] - These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. - (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. - (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. - (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. - (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. - (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. - (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - (+) CommutationCallback : TIM Commutation Callback. - (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. - (+) BreakCallback : TIM Break Callback. - - [..] -By default, after the Init and when the state is HAL_TIM_STATE_RESET -all interrupt callbacks are set to the corresponding weak functions: - examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init / DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit - keep and use the user MspInit / MspDeInit callbacks(registered beforehand) - - [..] - Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit / MspDeInit that can be registered / unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_TIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Base_MspInitCallback == NULL) - { - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Base_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Base_MspDeInitCallback == NULL) - { - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Base_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - if (htim->State == HAL_TIM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * -@verbatim - ============================================================================== - ##### TIM Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the TIM Output Compare. - (+) Stop the TIM Output Compare. - (+) Start the TIM Output Compare and enable interrupt. - (+) Stop the TIM Output Compare and disable interrupt. - (+) Start the TIM Output Compare and enable DMA transfer. - (+) Stop the TIM Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OC_MspInitCallback == NULL) - { - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OC_MspDeInitCallback == NULL) - { - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * -@verbatim - ============================================================================== - ##### TIM PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM PWM. - (+) De-initialize the TIM PWM. - (+) Start the TIM PWM. - (+) Stop the TIM PWM. - (+) Start the TIM PWM and enable interrupt. - (+) Stop the TIM PWM and disable interrupt. - (+) Start the TIM PWM and enable DMA transfer. - (+) Stop the TIM PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->PWM_MspInitCallback == NULL) - { - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->PWM_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->PWM_MspDeInitCallback == NULL) - { - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - } - /* DeInit the low level hardware */ - htim->PWM_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * -@verbatim - ============================================================================== - ##### TIM Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the TIM Input Capture. - (+) Stop the TIM Input Capture. - (+) Start the TIM Input Capture and enable interrupt. - (+) Stop the TIM Input Capture and disable interrupt. - (+) Start the TIM Input Capture and enable DMA transfer. - (+) Stop the TIM Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->IC_MspInitCallback == NULL) - { - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->IC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->IC_MspDeInitCallback == NULL) - { - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->IC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM Input Capture handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * -@verbatim - ============================================================================== - ##### TIM One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the TIM One Pulse. - (+) Stop the TIM One Pulse. - (+) Start the TIM One Pulse and enable interrupt. - (+) Stop the TIM One Pulse and disable interrupt. - (+) Start the TIM One Pulse and enable DMA transfer. - (+) Stop the TIM One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @note When the timer instance is initialized in One Pulse mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM One Pulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OnePulse_MspInitCallback == NULL) - { - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OnePulse_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OnePulse_MspDeInitCallback == NULL) - { - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OnePulse_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * -@verbatim - ============================================================================== - ##### TIM Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the TIM Encoder. - (+) Stop the TIM Encoder. - (+) Start the TIM Encoder and enable interrupt. - (+) Stop the TIM Encoder and disable interrupt. - (+) Start the TIM Encoder and enable DMA transfer. - (+) Stop the TIM Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together - * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource - * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa - * @note When the timer instance is initialized in Encoder mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Encoder_MspInitCallback == NULL) - { - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Encoder_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS and ECE bits */ - htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Encoder_MspDeInitCallback == NULL) - { - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Encoder_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData1 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData2 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - default: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break input event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->BreakCallback(htim); -#else - HAL_TIMEx_BreakCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM commutation event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_4) - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - else - { - status = HAL_ERROR; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM output channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM input Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @note To output a waveform with a minimum delay user can enable the fast - * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx - * output is forced in response to the edge detection on TIx input, - * without taking in account the comparison. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel) -{ - HAL_StatusTypeDef status = HAL_OK; - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if (OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - status = HAL_ERROR; - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - HAL_StatusTypeDef status; - - status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - - - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA stream) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - HAL_StatusTypeDef status; - - status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA stream) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @note Basic timers can only generate an update event. - * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. - * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances - * supporting a break input. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - break; - } - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (Channel) - { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - default: - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - break; - } - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - break; - } - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - break; - } - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - break; - } - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - break; - } - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - break; - } - - case TIM_CLOCKSOURCE_ITR0: - case TIM_CLOCKSOURCE_ITR1: - case TIM_CLOCKSOURCE_ITR2: - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } - - default: - status = HAL_ERROR; - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) TIM Period elapsed callback - (+) TIM Output Compare callback - (+) TIM Input capture callback - (+) TIM Trigger callback - (+) TIM Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Period elapsed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture half complete callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User TIM callback to be used instead of the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = pCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = pCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Unregister a TIM callback - * TIM callback is redirected to the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - /* Legacy weak Period Elapsed Callback */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - /* Legacy weak Period Elapsed half complete Callback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - /* Legacy weak Trigger Callback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - /* Legacy weak Trigger half complete Callback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - /* Legacy weak IC Capture Callback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - /* Legacy weak IC Capture half complete Callback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - /* Legacy weak OC Delay Elapsed Callback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - /* Legacy weak PWM Pulse Finished Callback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - /* Legacy weak PWM Pulse Finished half complete Callback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - /* Legacy weak Error Callback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - /* Legacy weak Commutation Callback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - /* Legacy weak Commutation half complete Callback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - /* Legacy weak Break Callback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Output Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder Interface handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM handle - * @retval Active channel - */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) -{ - return htim->Channel; -} - -/** - * @brief Return actual state of the TIM channel. - * @param htim TIM handle - * @param Channel TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval TIM Channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - return channel_state; -} - -/** - * @brief Return actual state of a DMA burst operation. - * @param htim TIM handle - * @retval DMA burst state - */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - - return htim->DMABurstState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedHalfCpltCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureHalfCpltCallback(htim); -#else - HAL_TIM_IC_CaptureHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Period Elapse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedHalfCpltCallback(htim); -#else - HAL_TIM_PeriodElapsedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerHalfCpltCallback(htim); -#else - HAL_TIM_TriggerHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter (only for advanced timer) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Timer Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Slave Timer configuration function - * @param htim TIM handle - * @param sSlaveConfig Slave timer configuration - * @retval None - */ -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) - { - return HAL_ERROR; - } - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - break; - } - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_ITR0: - case TIM_TS_ITR1: - case TIM_TS_ITR2: - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) -{ - uint32_t tmpsmcr; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param htim pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void TIM_ResetCallback(TIM_HandleTypeDef *htim) -{ - /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - htim->TriggerCallback = HAL_TIM_TriggerCallback; - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - htim->ErrorCallback = HAL_TIM_ErrorCallback; - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - htim->BreakCallback = HAL_TIMEx_BreakCallback; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c deleted file mode 100644 index 092175f..0000000 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ /dev/null @@ -1,2428 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Timer remapping capabilities configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), - HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), - HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), - HAL_TIMEx_HallSensor_Start_IT(). - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @note When the timer instance is initialized in Hall Sensor Interface mode, - * timer channels 1 and channel 2 are reserved and cannot be used for - * other purpose. - * @param htim TIM Hall Sensor Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy week callbacks */ - TIM_ResetCallback(htim); - - if (htim->HallSensor_MspInitCallback == NULL) - { - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->HallSensor_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->HallSensor_MspDeInitCallback == NULL) - { - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - } - /* DeInit the low level hardware */ - htim->HallSensor_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream for Capture 1*/ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - /* Enable the Commutation Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @note Interrupts can be generated when an active level is detected on the - * break input, the break 2 input or the system break input. Break - * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - /* Keep this variable initialized to 0 as it is used to configure BDTR register */ - uint32_t tmpbdtr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * For TIM1, the parameter can have the following values: (**) - * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 is connected to TIM3 TRGO - * @arg TIM_TIM1_LPTIM: TIM1 ITR2 is connected to LPTIM1 output - * - * For TIM2, the parameter can have the following values: (**) - * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 is connected to TIM8 TRGO (*) - * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 is connected to PTP trigger output (*) - * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 is connected to OTG FS SOF - * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 is connected to OTG FS SOF - * - * For TIM5, the parameter can have the following values: - * @arg TIM_TIM5_GPIO: TIM5 TI4 is connected to GPIO - * @arg TIM_TIM5_LSI: TIM5 TI4 is connected to LSI - * @arg TIM_TIM5_LSE: TIM5 TI4 is connected to LSE - * @arg TIM_TIM5_RTC: TIM5 TI4 is connected to the RTC wakeup interrupt - * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 is connected to TIM3 TRGO (*) - * @arg TIM_TIM5_LPTIM: TIM5 ITR1 is connected to LPTIM1 output (*) - * - * For TIM9, the parameter can have the following values: (**) - * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO - * @arg TIM_TIM9_LPTIM: TIM9 ITR1 is connected to LPTIM1 output - * - * For TIM11, the parameter can have the following values: - * @arg TIM_TIM11_GPIO: TIM11 TI1 is connected to GPIO - * @arg TIM_TIM11_HSE: TIM11 TI1 is connected to HSE_RTC clock - * @arg TIM_TIM11_SPDIFRX: TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC (*) - * - * (*) Value not defined in all devices. \n - * (**) Register not available in all devices. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - - /* Check parameters */ - assert_param(IS_TIM_REMAP(htim->Instance, Remap)); - - __HAL_LOCK(htim); - -#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) - if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) - { - /* Connect TIMx internal trigger to LPTIM1 output */ - __HAL_RCC_LPTIM1_CLK_ENABLE(); - MODIFY_REG(LPTIM1->OR, - (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), - Remap & ~(LPTIM_REMAP_MASK)); - } - else - { - /* Set the Timer remapping configuration */ - WRITE_REG(htim->Instance->OR, Remap); - } -#else - /* Set the Timer remapping configuration */ - WRITE_REG(htim->Instance->OR, Remap); -#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */ - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutCallback could be implemented in the user file - */ -} -/** - * @brief Hall commutation changed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return actual state of the TIM complementary channel. - * @param htim TIM handle - * @param ChannelN TIM Complementary channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @retval TIM Complementary channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); - - channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - - return channel_state; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Commutation half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationHalfCpltCallback(htim); -#else - HAL_TIMEx_CommutHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - - -/** - * @brief TIM DMA Delay Pulse complete callback (complementary channel). - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA error callback (complementary channel) - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp; - - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/Software/Flapy Bird/Flapy Bird.ioc b/Software/Flapy Bird/Flapy Bird.ioc deleted file mode 100644 index 3c35f87..0000000 --- a/Software/Flapy Bird/Flapy Bird.ioc +++ /dev/null @@ -1,281 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -File.Version=6 -GPIO.groupedBy=Group By Peripherals -KeepUserPlacement=false -Mcu.CPN=STM32F407VGT6 -Mcu.Family=STM32F4 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SPI3 -Mcu.IP3=SYS -Mcu.IPNb=4 -Mcu.Name=STM32F407V(E-G)Tx -Mcu.Package=LQFP100 -Mcu.Pin0=PE2 -Mcu.Pin1=PE3 -Mcu.Pin10=PE10 -Mcu.Pin11=PE11 -Mcu.Pin12=PE12 -Mcu.Pin13=PE13 -Mcu.Pin14=PE14 -Mcu.Pin15=PE15 -Mcu.Pin16=PB10 -Mcu.Pin17=PD1 -Mcu.Pin18=PD3 -Mcu.Pin19=PD4 -Mcu.Pin2=PE4 -Mcu.Pin20=PD5 -Mcu.Pin21=PD6 -Mcu.Pin22=PD7 -Mcu.Pin23=PB3 -Mcu.Pin24=PB4 -Mcu.Pin25=PB5 -Mcu.Pin26=PE0 -Mcu.Pin27=PE1 -Mcu.Pin28=VP_SYS_VS_Systick -Mcu.Pin3=PE5 -Mcu.Pin4=PE6 -Mcu.Pin5=PH0-OSC_IN -Mcu.Pin6=PH1-OSC_OUT -Mcu.Pin7=PE7 -Mcu.Pin8=PE8 -Mcu.Pin9=PE9 -Mcu.PinsNb=29 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32F407VGTx -MxCube.Version=6.6.1 -MxDb.Version=DB.6.0.60 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false -PB10.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PB10.GPIO_Label=CS -PB10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PB10.Locked=true -PB10.PinState=GPIO_PIN_SET -PB10.Signal=GPIO_Output -PB3.Locked=true -PB3.Mode=Full_Duplex_Master -PB3.Signal=SPI3_SCK -PB4.Locked=true -PB4.Mode=Full_Duplex_Master -PB4.Signal=SPI3_MISO -PB5.Locked=true -PB5.Mode=Full_Duplex_Master -PB5.Signal=SPI3_MOSI -PD1.GPIOParameters=GPIO_Label -PD1.GPIO_Label=T_IRQ -PD1.Locked=true -PD1.Signal=GPIO_Input -PD3.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PD3.GPIO_Label=RESET -PD3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD3.Locked=true -PD3.PinState=GPIO_PIN_SET -PD3.Signal=GPIO_Output -PD4.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PD4.GPIO_Label=RD -PD4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD4.Locked=true -PD4.PinState=GPIO_PIN_SET -PD4.Signal=GPIO_Output -PD5.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PD5.GPIO_Label=WR -PD5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD5.Locked=true -PD5.PinState=GPIO_PIN_SET -PD5.Signal=GPIO_Output -PD6.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PD6.GPIO_Label=RS -PD6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD6.Locked=true -PD6.PinState=GPIO_PIN_SET -PD6.Signal=GPIO_Output -PD7.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PD7.GPIO_Label=T_CS -PD7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD7.Locked=true -PD7.PinState=GPIO_PIN_SET -PD7.Signal=GPIO_Output -PE0.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE0.GPIO_Label=D0 -PE0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE0.Locked=true -PE0.PinState=GPIO_PIN_SET -PE0.Signal=GPIO_Output -PE1.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE1.GPIO_Label=D1 -PE1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE1.Locked=true -PE1.PinState=GPIO_PIN_SET -PE1.Signal=GPIO_Output -PE10.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE10.GPIO_Label=D10 -PE10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE10.Locked=true -PE10.PinState=GPIO_PIN_SET -PE10.Signal=GPIO_Output -PE11.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE11.GPIO_Label=D11 -PE11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE11.Locked=true -PE11.PinState=GPIO_PIN_SET -PE11.Signal=GPIO_Output -PE12.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE12.GPIO_Label=D12 -PE12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE12.Locked=true -PE12.PinState=GPIO_PIN_SET -PE12.Signal=GPIO_Output -PE13.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE13.GPIO_Label=D13 -PE13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE13.Locked=true -PE13.PinState=GPIO_PIN_SET -PE13.Signal=GPIO_Output -PE14.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE14.GPIO_Label=D14 -PE14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE14.Locked=true -PE14.PinState=GPIO_PIN_SET -PE14.Signal=GPIO_Output -PE15.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE15.GPIO_Label=D15 -PE15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE15.Locked=true -PE15.PinState=GPIO_PIN_SET -PE15.Signal=GPIO_Output -PE2.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE2.GPIO_Label=D2 -PE2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE2.Locked=true -PE2.PinState=GPIO_PIN_SET -PE2.Signal=GPIO_Output -PE3.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE3.GPIO_Label=D3 -PE3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE3.Locked=true -PE3.PinState=GPIO_PIN_SET -PE3.Signal=GPIO_Output -PE4.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE4.GPIO_Label=D4 -PE4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE4.Locked=true -PE4.PinState=GPIO_PIN_SET -PE4.Signal=GPIO_Output -PE5.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE5.GPIO_Label=D5 -PE5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE5.Locked=true -PE5.PinState=GPIO_PIN_SET -PE5.Signal=GPIO_Output -PE6.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE6.GPIO_Label=D6 -PE6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE6.Locked=true -PE6.PinState=GPIO_PIN_SET -PE6.Signal=GPIO_Output -PE7.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE7.GPIO_Label=D7 -PE7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE7.Locked=true -PE7.PinState=GPIO_PIN_SET -PE7.Signal=GPIO_Output -PE8.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE8.GPIO_Label=D8 -PE8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE8.Locked=true -PE8.PinState=GPIO_PIN_SET -PE8.Signal=GPIO_Output -PE9.GPIOParameters=GPIO_Speed,PinState,GPIO_Label -PE9.GPIO_Label=D9 -PE9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE9.Locked=true -PE9.PinState=GPIO_PIN_SET -PE9.Signal=GPIO_Output -PH0-OSC_IN.Mode=HSE-External-Oscillator -PH0-OSC_IN.Signal=RCC_OSC_IN -PH1-OSC_OUT.Mode=HSE-External-Oscillator -PH1-OSC_OUT.Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F407VGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.27.1 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Core/Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=Flapy Bird.ioc -ProjectManager.ProjectName=Flapy Bird -ProjectManager.RegisterCallBack= -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=STM32CubeIDE -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_I2S3_Init-I2S3-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_USB_HOST_Init-USB_HOST-false-HAL-false -RCC.48MHZClocksFreq_Value=48000000 -RCC.AHBFreq_Value=168000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV4 -RCC.APB1Freq_Value=42000000 -RCC.APB1TimFreq_Value=84000000 -RCC.APB2CLKDivider=RCC_HCLK_DIV2 -RCC.APB2Freq_Value=84000000 -RCC.APB2TimFreq_Value=168000000 -RCC.CortexFreq_Value=168000000 -RCC.EthernetFreq_Value=168000000 -RCC.FCLKCortexFreq_Value=168000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=168000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2SClocksFreq_Value=96000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S -RCC.LSI_VALUE=32000 -RCC.MCO2PinFreq_Value=168000000 -RCC.PLLCLKFreq_Value=168000000 -RCC.PLLM=8 -RCC.PLLN=336 -RCC.PLLQ=7 -RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.RTCFreq_Value=32000 -RCC.RTCHSEDivFreq_Value=4000000 -RCC.SYSCLKFreq_VALUE=168000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.VCOI2SOutputFreq_Value=192000000 -RCC.VCOInputFreq_Value=1000000 -RCC.VCOOutputFreq_Value=336000000 -RCC.VcooutputI2S=96000000 -SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 -SPI3.CalculateBaudRate=2.625 MBits/s -SPI3.Direction=SPI_DIRECTION_2LINES -SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler -SPI3.Mode=SPI_MODE_MASTER -SPI3.VirtualType=VM_MASTER -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=STM32F407G-DISC1 -boardIOC=true -isbadioc=false diff --git a/Software/Flapy Bird/Flapy Bird.launch b/Software/Flapy Bird/Flapy Bird.launch deleted file mode 100644 index 993164a..0000000 --- a/Software/Flapy Bird/Flapy Bird.launch +++ /dev/null @@ -1,79 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git "a/Software/Flapy Bird/LCD_Final_v2.pdf - Profil 1 \342\200\223 Microsoft_ Edge 08.09.2022 00_32_12 (2).png" "b/Software/Flapy Bird/LCD_Final_v2.pdf - Profil 1 \342\200\223 Microsoft_ Edge 08.09.2022 00_32_12 (2).png" deleted file mode 100644 index 6845c59..0000000 Binary files "a/Software/Flapy Bird/LCD_Final_v2.pdf - Profil 1 \342\200\223 Microsoft_ Edge 08.09.2022 00_32_12 (2).png" and /dev/null differ diff --git a/Software/Flapy Bird/STM32F407VGTX_FLASH.ld b/Software/Flapy Bird/STM32F407VGTX_FLASH.ld deleted file mode 100644 index b1aa530..0000000 --- a/Software/Flapy Bird/STM32F407VGTX_FLASH.ld +++ /dev/null @@ -1,206 +0,0 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** Abstract : Linker script for STM32F407G-DISC1 Board embedding STM32F407VGTx Device from stm32f4 series -** 1024Kbytes FLASH -** 64Kbytes CCMRAM -** 128Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2022 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200 ; /* required amount of heap */ -_Min_Stack_Size = 0x400 ; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - _siccmram = LOADADDR(.ccmram); - - /* CCM-RAM section - * - * IMPORTANT NOTE! - * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. - */ - .ccmram : - { - . = ALIGN(4); - _sccmram = .; /* create a global symbol at ccmram start */ - *(.ccmram) - *(.ccmram*) - - . = ALIGN(4); - _eccmram = .; /* create a global symbol at ccmram end */ - } >CCMRAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/Software/Flapy Bird/STM32F407VGTX_RAM.ld b/Software/Flapy Bird/STM32F407VGTX_RAM.ld deleted file mode 100644 index 95f6fee..0000000 --- a/Software/Flapy Bird/STM32F407VGTX_RAM.ld +++ /dev/null @@ -1,206 +0,0 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld (debug in RAM dedicated) -** -** @author : Auto-generated by STM32CubeIDE -** -** Abstract : Linker script for STM32F407G-DISC1 Board embedding STM32F407VGTx Device from stm32f4 series -** 1024Kbytes FLASH -** 64Kbytes CCMRAM -** 128Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2022 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "RAM" Ram type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >RAM - - /* The program code and other data into "RAM" Ram type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >RAM - - /* Constant data into "RAM" Ram type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >RAM - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >RAM - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >RAM - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >RAM - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >RAM - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >RAM - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM - - _siccmram = LOADADDR(.ccmram); - - /* CCM-RAM section - * - * IMPORTANT NOTE! - * If initialized variables will be placed in this section, - * the startup code needs to be modified to copy the init-values. - */ - .ccmram : - { - . = ALIGN(4); - _sccmram = .; /* create a global symbol at ccmram start */ - *(.ccmram) - *(.ccmram*) - - . = ALIGN(4); - _eccmram = .; /* create a global symbol at ccmram end */ - } >CCMRAM AT> RAM - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/Software/stm32project/.cproject b/Software/stm32project/.cproject index 257dee6..7d302ed 100644 --- a/Software/stm32project/.cproject +++ b/Software/stm32project/.cproject @@ -23,7 +23,7 @@ @@ -63,6 +65,8 @@ @@ -162,6 +169,7 @@ + diff --git a/Software/stm32project/.mxproject b/Software/stm32project/.mxproject index 32693b2..e107714 100644 --- a/Software/stm32project/.mxproject +++ b/Software/stm32project/.mxproject @@ -1,35 +1,61 @@ [PreviousLibFiles] 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+SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\adc.c;Core\Src\dma.c;Core\Src\i2c.c;Core\Src\usart.c;Core\Src\spi.c;Core\Src\tim.c;USB_DEVICE\App\usb_device.c;USB_DEVICE\Target\usbd_conf.c;USB_DEVICE\App\usbd_desc.c;USB_DEVICE\App\usbd_cdc_if.c;Core\Src\stm32l4xx_it.c;Core\Src\stm32l4xx_hal_msp.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Src\usbd_cdc.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c;Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Src\usbd_cdc.c;Drivers\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c;Core\Src\system_stm32l4xx.c;;;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_core.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c;Middlewares\ST\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Src\usbd_cdc.c; +HeaderPath=Drivers\STM32L4xx_HAL_Driver\Inc;Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32L4xx\Include;Drivers\CMSIS\Include;Middlewares\Third_Party\NimaLTD_Driver\SPIF;Core\Inc;I-CUBE-SPIF;USB_DEVICE\App;USB_DEVICE\Target; CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=6 -HeaderFiles#0=..\USB_DEVICE\App\usb_device.h -HeaderFiles#1=..\USB_DEVICE\Target\usbd_conf.h -HeaderFiles#2=..\USB_DEVICE\App\usbd_desc.h -HeaderFiles#3=..\Core\Inc\stm32l4xx_it.h -HeaderFiles#4=..\Core\Inc\stm32l4xx_hal_conf.h -HeaderFiles#5=..\Core\Inc\main.h -HeaderFolderListSize=3 -HeaderPath#0=..\USB_DEVICE\App -HeaderPath#1=..\USB_DEVICE\Target -HeaderPath#2=..\Core\Inc +HeaderFileListSize=15 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\adc.h +HeaderFiles#2=..\Core\Inc\dma.h +HeaderFiles#3=..\Core\Inc\i2c.h +HeaderFiles#4=..\Core\Inc\usart.h +HeaderFiles#5=..\I-CUBE-SPIF\.\NimaLTD.I-CUBE-SPIF_conf.h +HeaderFiles#6=..\Core\Inc\spi.h +HeaderFiles#7=..\Core\Inc\tim.h +HeaderFiles#8=..\USB_DEVICE\App\usb_device.h +HeaderFiles#9=..\USB_DEVICE\Target\usbd_conf.h +HeaderFiles#10=..\USB_DEVICE\App\usbd_desc.h +HeaderFiles#11=..\USB_DEVICE\App\usbd_cdc_if.h +HeaderFiles#12=..\Core\Inc\stm32l4xx_it.h +HeaderFiles#13=..\Core\Inc\stm32l4xx_hal_conf.h +HeaderFiles#14=..\Core\Inc\main.h +HeaderFolderListSize=4 +HeaderPath#0=..\Core\Inc +HeaderPath#1=..\I-CUBE-SPIF\. +HeaderPath#2=..\USB_DEVICE\App +HeaderPath#3=..\USB_DEVICE\Target HeaderFiles=; -SourceFileListSize=6 -SourceFiles#0=..\USB_DEVICE\App\usb_device.c -SourceFiles#1=..\USB_DEVICE\Target\usbd_conf.c -SourceFiles#2=..\USB_DEVICE\App\usbd_desc.c -SourceFiles#3=..\Core\Src\stm32l4xx_it.c -SourceFiles#4=..\Core\Src\stm32l4xx_hal_msp.c -SourceFiles#5=..\Core\Src\main.c +SourceFileListSize=14 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\adc.c +SourceFiles#2=..\Core\Src\dma.c +SourceFiles#3=..\Core\Src\i2c.c +SourceFiles#4=..\Core\Src\usart.c +SourceFiles#5=..\Core\Src\spi.c +SourceFiles#6=..\Core\Src\tim.c +SourceFiles#7=..\USB_DEVICE\App\usb_device.c +SourceFiles#8=..\USB_DEVICE\Target\usbd_conf.c +SourceFiles#9=..\USB_DEVICE\App\usbd_desc.c +SourceFiles#10=..\USB_DEVICE\App\usbd_cdc_if.c +SourceFiles#11=..\Core\Src\stm32l4xx_it.c +SourceFiles#12=..\Core\Src\stm32l4xx_hal_msp.c +SourceFiles#13=..\Core\Src\main.c SourceFolderListSize=3 -SourcePath#0=..\USB_DEVICE\App -SourcePath#1=..\USB_DEVICE\Target -SourcePath#2=..\Core\Src +SourcePath#0=..\Core\Src +SourcePath#1=..\USB_DEVICE\App +SourcePath#2=..\USB_DEVICE\Target SourceFiles=; +[ThirdPartyIp] +ThirdPartyIpNumber=1 +ThirdPartyIpName#0=NimaLTD.I-CUBE-SPIF.2.3.2 + +[ThirdPartyIp#NimaLTD.I-CUBE-SPIF.2.3.2] +header=Middlewares\Third_Party\NimaLTD_Driver\SPIF\spif.h; +source=Middlewares\Third_Party\NimaLTD_Driver\SPIF\spif.c; + diff --git a/Software/stm32project/.settings/language.settings.xml b/Software/stm32project/.settings/language.settings.xml index efcb4f3..4f1e2a4 100644 --- a/Software/stm32project/.settings/language.settings.xml +++ b/Software/stm32project/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/Software/stm32project/Core/Inc/adc.h b/Software/stm32project/Core/Inc/adc.h new file mode 100644 index 0000000..5692f38 --- /dev/null +++ b/Software/stm32project/Core/Inc/adc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.h + * @brief This file contains all the function prototypes for + * the adc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern ADC_HandleTypeDef hadc1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_ADC1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_H__ */ + diff --git a/Software/stm32project/Core/Inc/dma.h b/Software/stm32project/Core/Inc/dma.h new file mode 100644 index 0000000..f3b1a09 --- /dev/null +++ b/Software/stm32project/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/Software/stm32project/Core/Inc/gpio.h b/Software/stm32project/Core/Inc/gpio.h new file mode 100644 index 0000000..708bac7 --- /dev/null +++ b/Software/stm32project/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Software/stm32project/Core/Inc/i2c.h b/Software/stm32project/Core/Inc/i2c.h new file mode 100644 index 0000000..27a3ff7 --- /dev/null +++ b/Software/stm32project/Core/Inc/i2c.h @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +extern I2C_HandleTypeDef hi2c3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); +void MX_I2C3_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/Software/stm32project/Core/Inc/main.h b/Software/stm32project/Core/Inc/main.h index 74c2290..8fbb272 100644 --- a/Software/stm32project/Core/Inc/main.h +++ b/Software/stm32project/Core/Inc/main.h @@ -57,6 +57,8 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define FLASH_CS_Pin GPIO_PIN_0 +#define FLASH_CS_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ diff --git a/Software/stm32project/Core/Inc/spi.h b/Software/stm32project/Core/Inc/spi.h new file mode 100644 index 0000000..69969f0 --- /dev/null +++ b/Software/stm32project/Core/Inc/spi.h @@ -0,0 +1,56 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "nmea_parse.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SPI_HandleTypeDef hspi1; + +/* USER CODE BEGIN Private defines */ +#define MAX_WRITE_PAGE 25599 //25599 +/* USER CODE END Private defines */ + +void MX_SPI1_Init(void); + +/* USER CODE BEGIN Prototypes */ +int csvframe(uint8_t* buffer,float temp,float vbat,GPS * gpsdata,int otherval1,float otherval2); +void writebuffertoflash(uint8_t * buffer,int bufferlenght); +void getindex(void); +void storeindex(void); +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + diff --git a/Software/stm32project/Core/Inc/ssd1306.h b/Software/stm32project/Core/Inc/ssd1306.h index 1380df6..0034f47 100644 --- a/Software/stm32project/Core/Inc/ssd1306.h +++ b/Software/stm32project/Core/Inc/ssd1306.h @@ -109,6 +109,7 @@ void ssd1306_FillRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD13 void ssd1306_DrawBitmap(uint8_t x, uint8_t y, const unsigned char* bitmap, uint8_t w, uint8_t h, SSD1306_COLOR color); void ssd1306_Drawarrow(uint8_t x,uint8_t y, uint8_t type,SSD1306_COLOR color); void ssd1306_Drawarrow2(uint8_t x,uint8_t y, uint8_t r,float angle); +void batterygauge(float vbat,int x, int y,int currentsquare); /** * @brief Sets the contrast of the display. diff --git a/Software/stm32project/Core/Inc/statemachine.h b/Software/stm32project/Core/Inc/statemachine.h index c7897d4..013d225 100644 --- a/Software/stm32project/Core/Inc/statemachine.h +++ b/Software/stm32project/Core/Inc/statemachine.h @@ -24,7 +24,9 @@ typedef enum{ STATE_HEURE, STATE_INFO, STATE_CHRONOMETER, - STATE_MEMTEST + STATE_BALISE, + STATE_USB + }STATE_TYPE; @@ -71,6 +73,28 @@ typedef enum{ }KEYBOARD; +typedef enum{ + GIF1, + GIF2, + GIF3, + GIF4 + +}GIF; + +typedef enum{ + USBSTATE1, + USBSTATE2, + USBSTATE3 + +}USBSTATE; + +typedef enum{ + BALISESTATE1, + BALISESTATE2, + BALISESTATE3 + +}BALISESTATE; + typedef struct { uint8_t MODIFIER; diff --git a/Software/stm32project/Core/Inc/stm32l4xx_hal_conf.h b/Software/stm32project/Core/Inc/stm32l4xx_hal_conf.h index a0dc0ff..67c33a5 100644 --- a/Software/stm32project/Core/Inc/stm32l4xx_hal_conf.h +++ b/Software/stm32project/Core/Inc/stm32l4xx_hal_conf.h @@ -74,7 +74,7 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SWPMI_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED diff --git a/Software/stm32project/Core/Inc/stm32l4xx_it.h b/Software/stm32project/Core/Inc/stm32l4xx_it.h index 70af769..6040468 100644 --- a/Software/stm32project/Core/Inc/stm32l4xx_it.h +++ b/Software/stm32project/Core/Inc/stm32l4xx_it.h @@ -55,10 +55,10 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); +void EXTI1_IRQHandler(void); void DMA1_Channel1_IRQHandler(void); void ADC1_IRQHandler(void); -void EXTI15_10_IRQHandler(void); -void TIM7_IRQHandler(void); +void EXTI9_5_IRQHandler(void); void USB_IRQHandler(void); void DMA2_Channel7_IRQHandler(void); void LPUART1_IRQHandler(void); diff --git a/Software/stm32project/Core/Inc/tim.h b/Software/stm32project/Core/Inc/tim.h new file mode 100644 index 0000000..ae4feac --- /dev/null +++ b/Software/stm32project/Core/Inc/tim.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/Software/stm32project/Core/Inc/usart.h b/Software/stm32project/Core/Inc/usart.h new file mode 100644 index 0000000..0c80db0 --- /dev/null +++ b/Software/stm32project/Core/Inc/usart.h @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef hlpuart1; + +extern UART_HandleTypeDef huart1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_LPUART1_UART_Init(void); +void MX_USART1_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/Software/stm32project/Core/Src/adc.c b/Software/stm32project/Core/Src/adc.c new file mode 100644 index 0000000..01f6afd --- /dev/null +++ b/Software/stm32project/Core/Src/adc.c @@ -0,0 +1,198 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.c + * @brief This file provides code for the configuration + * of the ADC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "adc.h" + +/* USER CODE BEGIN 0 */ + +extern uint16_t rawdata[3]; +extern float temp; +extern float vrefint; +extern float vbat; +float tscal2=1365.0; +float tscal1=1034.0; +/* USER CODE END 0 */ + +ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; + +/* ADC1 init function */ +void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + + /** Common config + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.ContinuousConvMode = ENABLE; + hadc1.Init.NbrOfConversion = 3; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.OversamplingMode = DISABLE; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_VREFINT; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; + sConfig.Rank = ADC_REGULAR_RANK_2; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_9; + sConfig.Rank = ADC_REGULAR_RANK_3; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* ADC1 clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA4 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Channel1; + hdma_adc1.Init.Request = DMA_REQUEST_0; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_NORMAL; + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ADC1_IRQn); + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } +} + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) +{ + + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA4 ------> ADC1_IN9 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); + + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); + + /* ADC1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(ADC1_IRQn); + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){ + + if(hadc->Instance==ADC1){ + vrefint=(float) ((4095.0*1.212)/rawdata[0]); +// vtemp=(float) ((vrefint*rawdata[1])/4095.0); + temp=(float) (((100.0)/(tscal2-tscal1))*(rawdata[1]*(vrefint/3.0)-tscal1))+30.0; + vbat=(float) 2*(rawdata[2]/4095.0)*vrefint; + + } + HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 3); + + + +} +/* USER CODE END 1 */ diff --git a/Software/stm32project/Core/Src/dma.c b/Software/stm32project/Core/Src/dma.c new file mode 100644 index 0000000..c725f04 --- /dev/null +++ b/Software/stm32project/Core/Src/dma.c @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + /* DMA2_Channel7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Channel7_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Channel7_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/Software/stm32project/Core/Src/gpio.c b/Software/stm32project/Core/Src/gpio.c new file mode 100644 index 0000000..adc3a46 --- /dev/null +++ b/Software/stm32project/Core/Src/gpio.c @@ -0,0 +1,94 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(FLASH_CS_GPIO_Port, FLASH_CS_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : PA1 */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = FLASH_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(FLASH_CS_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PB1 */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI1_IRQn, 1, 0); + HAL_NVIC_EnableIRQ(EXTI1_IRQn); + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 1, 0); + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Software/stm32project/Core/Src/i2c.c b/Software/stm32project/Core/Src/i2c.c new file mode 100644 index 0000000..35cb95b --- /dev/null +++ b/Software/stm32project/Core/Src/i2c.c @@ -0,0 +1,249 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c1; +I2C_HandleTypeDef hi2c3; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x00202538; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} +/* I2C3 init function */ +void MX_I2C3_Init(void) +{ + + /* USER CODE BEGIN I2C3_Init 0 */ + + /* USER CODE END I2C3_Init 0 */ + + /* USER CODE BEGIN I2C3_Init 1 */ + + /* USER CODE END I2C3_Init 1 */ + hi2c3.Instance = I2C3; + hi2c3.Init.Timing = 0x00100618; + hi2c3.Init.OwnAddress1 = 0; + hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c3.Init.OwnAddress2 = 0; + hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c3) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) + { + Error_Handler(); + } + + /** I2C Fast mode Plus enable + */ + HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3); + /* USER CODE BEGIN I2C3_Init 2 */ + + /* USER CODE END I2C3_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + else if(i2cHandle->Instance==I2C3) + { + /* USER CODE BEGIN I2C3_MspInit 0 */ + + /* USER CODE END I2C3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C3; + PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_SYSCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C3 GPIO Configuration + PA7 ------> I2C3_SCL + PB4 (NJTRST) ------> I2C3_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C3 clock enable */ + __HAL_RCC_I2C3_CLK_ENABLE(); + /* USER CODE BEGIN I2C3_MspInit 1 */ + + /* USER CODE END I2C3_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + else if(i2cHandle->Instance==I2C3) + { + /* USER CODE BEGIN I2C3_MspDeInit 0 */ + + /* USER CODE END I2C3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C3_CLK_DISABLE(); + + /**I2C3 GPIO Configuration + PA7 ------> I2C3_SCL + PB4 (NJTRST) ------> I2C3_SDA + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4); + + /* USER CODE BEGIN I2C3_MspDeInit 1 */ + + /* USER CODE END I2C3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Software/stm32project/Core/Src/main.c b/Software/stm32project/Core/Src/main.c index 837ac0f..526293d 100644 --- a/Software/stm32project/Core/Src/main.c +++ b/Software/stm32project/Core/Src/main.c @@ -18,7 +18,14 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" +#include "adc.h" +#include "dma.h" +#include "i2c.h" +#include "usart.h" +#include "spi.h" +#include "tim.h" #include "usb_device.h" +#include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -29,6 +36,7 @@ #include "statemachine.h" #include "nmea_parse.h" #include "stm32l4xx_hal.h" +#include "spif.h" /* USER CODE END Includes */ @@ -48,16 +56,6 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; -DMA_HandleTypeDef hdma_adc1; - -I2C_HandleTypeDef hi2c3; - -UART_HandleTypeDef hlpuart1; -DMA_HandleTypeDef hdma_lpuart_rx; - -TIM_HandleTypeDef htim2; -TIM_HandleTypeDef htim7; /* USER CODE BEGIN PV */ @@ -70,18 +68,15 @@ GPS myData;//structure stockant toutes les informations que l'on souhaite obten int BTN_A=0;//variables servants à stocker les appuie sur le bouton a ou b, elles ne prendrons que les valeurs 0 ou 1. int BTN_B=0; STATE_TYPE state=STATE_SPEED;//état principaux de la machine à état -int boumheure=0;//variable pour le compte à rebours -int boumminutes=0;//de meme -int choose=0;//variable servant à switcher lecran montré sur l'état compte à rebours en fonction de si l'heure a été choisie de fin a été choisie ou non. HEURE hrstate=STATE_DIGIT; SPEED spdstate=STATE_SUMMARY; POS posstate=STATE_SUMMARY1; CHRONO chronostate=STATE_RESET; KEYBOARD keyboardstate=STATE_MARCHE; -float tscal2=1365.0; -float tscal1=1034.0; +GIF gifstate=GIF1; keyboardHID keyboardhid = {0,0,0,0,0,0,0,0}; - +SPIF_HandleTypeDef hspif1; +extern SPI_HandleTypeDef hspi1; const unsigned char startimg[] = {//image de démarrage 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -118,10 +113,20 @@ const unsigned char startimg[] = {//image de démarrage 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -uint16_t rawdata[2]; +uint16_t rawdata[3]; float temp=0.0; float vrefint=0; +float vbat=0; +extern char str[20]; +uint8_t flashwrite[256]; +uint8_t flashread[256]; +extern uint8_t indexbuffer[50]; +int pageoffset=0; +int pagenumber=0; +int sectoreraseen=0; +uint8_t numbuf1[10]; +uint8_t numbuf2[10]; @@ -131,13 +136,6 @@ float vrefint=0; /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); void PeriphCommonClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_DMA_Init(void); -static void MX_I2C3_Init(void); -static void MX_LPUART1_UART_Init(void); -static void MX_ADC1_Init(void); -static void MX_TIM2_Init(void); -static void MX_TIM7_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -148,7 +146,7 @@ static void MX_TIM7_Init(void); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)//lors d'un appuie sur un bouton, le systeme s'interrompt afin d'arriver dans cette fonction redefinie avec en parametre d'entre , le bouton sur lequel l'on a appuiyé { - if(GPIO_Pin==GPIO_PIN_14){ + if(GPIO_Pin==GPIO_PIN_8){ // ssd1306_SetCursor(33, 44); // ssd1306_WriteString("btna", Font_6x8, White); // ssd1306_UpdateScreen(); @@ -156,7 +154,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)//lors d'un appuie sur un bouton, } - if(GPIO_Pin==GPIO_PIN_15){ + if(GPIO_Pin==GPIO_PIN_1){ //ssd1306_SetCursor(33, 44); //ssd1306_WriteString("btnb", Font_6x8, White); //ssd1306_UpdateScreen(); @@ -164,48 +162,6 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)//lors d'un appuie sur un bouton, } } - - void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ - oldPos = newPos; //keep track of the last position in the buffer - if(oldPos + 64 > DataBuffer_SIZE){ //if the buffer is full, parse it, then reset the buffer - - uint16_t datatocopy = DataBuffer_SIZE-oldPos; // find out how much space is left in the main buffer - memcpy ((uint8_t *)DataBuffer+oldPos, RxBuffer, datatocopy); // copy data in that remaining space - - oldPos = 0; // point to the start of the buffer - memcpy ((uint8_t *)DataBuffer, (uint8_t *)RxBuffer+datatocopy, (64-datatocopy)); // copy the remaining data - newPos = (64-datatocopy); // update the position - } - else{ - memcpy((uint8_t *)DataBuffer+oldPos, RxBuffer, 64); //copy received data to the buffer - newPos = 64+oldPos; //update buffer position - - } - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//on recoit par dma à nouveau 64 caractères - __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT);//on desactive l'interruption afin de ne pas être interrompu tout le temps - - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//l'appel de cette fonction réactive l'intérruption. -} - -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){ - - if(hadc->Instance==ADC1){ - vrefint=(float) ((4095.0*1.212)/rawdata[0]); -// vtemp=(float) ((vrefint*rawdata[1])/4095.0); - temp=(float) (((100.0)/(tscal2-tscal1))*(rawdata[1]*(vrefint/3.0)-tscal1))+30.0; - - } - HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 2); - - - -} - - - - - - /* USER CODE END 0 */ /** @@ -244,8 +200,10 @@ int main(void) MX_LPUART1_UART_Init(); MX_ADC1_Init(); MX_TIM2_Init(); - MX_TIM7_Init(); MX_USB_DEVICE_Init(); + MX_I2C1_Init(); + MX_USART1_UART_Init(); + MX_SPI1_Init(); /* USER CODE BEGIN 2 */ @@ -258,21 +216,32 @@ int main(void) ssd1306_DrawBitmap(32, 32, startimg, 64, 64, White); ssd1306_UpdateScreen(); - HAL_GPIO_WritePin(GPIOA,GPIO_PIN_1,GPIO_PIN_SET); - HAL_Delay(1000); + HAL_Delay(500); - HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 2); + HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 3); HAL_TIM_Base_Start(&htim2); - HAL_TIM_Base_Start(&htim7); HAL_UART_Abort(&hlpuart1); - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//lancement du dma pour le gps + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE); - ssd1306_Fill(Black); + memset(flashread,'1',256); + memset(flashwrite,'\0',256); + SPIF_Init(&hspif1, &hspi1, GPIOB, GPIO_PIN_0); + ssd1306_Fill(Black); + getindex(); + snprintf((uint8_t*)str,20, "off=%d",pageoffset); + ssd1306_SetCursor(32,40); + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + snprintf((uint8_t*)str,20, "page=%d",pagenumber); + ssd1306_SetCursor(32,48); + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + ssd1306_UpdateScreen(); + + HAL_Delay(1000); @@ -291,6 +260,21 @@ int main(void) /* USER CODE BEGIN 3 */ +// ssd1306_SetCursor(32, 32); +// +// for(int i=0;i<256;i++){ +// +// ssd1306_SetCursor(32, 32); +// HAL_Delay(100); +// +// ssd1306_Fill(Black); +// snprintf(str,20, "%d",flashread[i]); +// ssd1306_WriteString(str, Font_6x8, White); +// +// } + + + statemachine(); ssd1306_UpdateScreen(); @@ -300,6 +284,7 @@ int main(void) + } /* USER CODE END 3 */ } @@ -380,302 +365,6 @@ void PeriphCommonClock_Config(void) } } -/** - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) -{ - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - - /** Common config - */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - hadc1.Init.LowPowerAutoWait = DISABLE; - hadc1.Init.ContinuousConvMode = ENABLE; - hadc1.Init.NbrOfConversion = 2; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; - hadc1.Init.OversamplingMode = DISABLE; - if (HAL_ADC_Init(&hadc1) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_VREFINT; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; - sConfig.SingleDiff = ADC_SINGLE_ENDED; - sConfig.OffsetNumber = ADC_OFFSET_NONE; - sConfig.Offset = 0; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; - sConfig.Rank = ADC_REGULAR_RANK_2; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - -/** - * @brief I2C3 Initialization Function - * @param None - * @retval None - */ -static void MX_I2C3_Init(void) -{ - - /* USER CODE BEGIN I2C3_Init 0 */ - - /* USER CODE END I2C3_Init 0 */ - - /* USER CODE BEGIN I2C3_Init 1 */ - - /* USER CODE END I2C3_Init 1 */ - hi2c3.Instance = I2C3; - hi2c3.Init.Timing = 0x00100618; - hi2c3.Init.OwnAddress1 = 0; - hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - hi2c3.Init.OwnAddress2 = 0; - hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - if (HAL_I2C_Init(&hi2c3) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Analogue filter - */ - if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Digital filter - */ - if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) - { - Error_Handler(); - } - - /** I2C Fast mode Plus enable - */ - HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3); - /* USER CODE BEGIN I2C3_Init 2 */ - - /* USER CODE END I2C3_Init 2 */ - -} - -/** - * @brief LPUART1 Initialization Function - * @param None - * @retval None - */ -static void MX_LPUART1_UART_Init(void) -{ - - /* USER CODE BEGIN LPUART1_Init 0 */ - - /* USER CODE END LPUART1_Init 0 */ - - /* USER CODE BEGIN LPUART1_Init 1 */ - - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 9600; - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LPUART1_Init 2 */ - - /* USER CODE END LPUART1_Init 2 */ - -} - -/** - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM2_Init(void) -{ - - /* USER CODE BEGIN TIM2_Init 0 */ - - /* USER CODE END TIM2_Init 0 */ - - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM2_Init 1 */ - - /* USER CODE END TIM2_Init 1 */ - htim2.Instance = TIM2; - htim2.Init.Prescaler = 400-1; - htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - htim2.Init.Period = 10000-1; - htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim2) != HAL_OK) - { - Error_Handler(); - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM2_Init 2 */ - - /* USER CODE END TIM2_Init 2 */ - -} - -/** - * @brief TIM7 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM7_Init(void) -{ - - /* USER CODE BEGIN TIM7_Init 0 */ - - /* USER CODE END TIM7_Init 0 */ - - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM7_Init 1 */ - - /* USER CODE END TIM7_Init 1 */ - htim7.Instance = TIM7; - htim7.Init.Prescaler = 10000-1; - htim7.Init.CounterMode = TIM_COUNTERMODE_UP; - htim7.Init.Period = 8000-1; - htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim7) != HAL_OK) - { - Error_Handler(); - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN TIM7_Init 2 */ - - /* USER CODE END TIM7_Init 2 */ - -} - -/** - * Enable DMA controller clock - */ -static void MX_DMA_Init(void) -{ - - /* DMA controller clock enable */ - __HAL_RCC_DMA1_CLK_ENABLE(); - __HAL_RCC_DMA2_CLK_ENABLE(); - - /* DMA interrupt init */ - /* DMA1_Channel1_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - /* DMA2_Channel7_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Channel7_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(DMA2_Channel7_IRQn); - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; -/* USER CODE BEGIN MX_GPIO_Init_1 */ -/* USER CODE END MX_GPIO_Init_1 */ - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); - - /*Configure GPIO pins : PC14 PC15 */ - GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /*Configure GPIO pin : PA1 */ - GPIO_InitStruct.Pin = GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); - -/* USER CODE BEGIN MX_GPIO_Init_2 */ -/* USER CODE END MX_GPIO_Init_2 */ -} - /* USER CODE BEGIN 4 */ /* USER CODE END 4 */ diff --git a/Software/stm32project/Core/Src/spi.c b/Software/stm32project/Core/Src/spi.c new file mode 100644 index 0000000..53f2c01 --- /dev/null +++ b/Software/stm32project/Core/Src/spi.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + + +/* USER CODE BEGIN 0 */ +#include +#include +#include "statemachine.h" +#include "spif.h" +#include "nmea_parse.h" +#include "ssd1306.h" +extern float temp; +extern float vbat; +extern GPS myData; +uint8_t indexbuffer[50];//pageindex,pagenumber,sectornumber +extern SPIF_HandleTypeDef hspif1; +extern int pageoffset; +extern int pagenumber; +extern uint8_t numbuf1[10]; +extern uint8_t numbuf2[10]; +extern int sectoreraseen; +/* USER CODE END 0 */ + +SPI_HandleTypeDef hspi1; + +/* SPI1 init function */ +void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 7; + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* SPI1 clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PB5 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) +{ + + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PB5 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ +int csvframe(uint8_t* buffer,float temp,float vbat,GPS * gpsdata,int otherval1,float otherval2){ + int framesize=0; + framesize=snprintf((uint8_t*)buffer,256, "%0.2f,%0.2f,%0.2f,%0.7f,%0.7f,%0.2f,%d,%0.2f;\n\r",temp,vbat,gpsdata->speed,gpsdata->latitude,gpsdata->longitude,gpsdata->altitude,otherval1,otherval2); + return framesize; +} + + +void storeindex(void){ + int writepage=MAX_WRITE_PAGE+1; + uint8_t writebuffer[100]; + memset((uint8_t*)writebuffer,'\0',100); + snprintf((uint8_t*)writebuffer,100, "%d$%d$",pageoffset,pagenumber); + SPIF_EraseSector(&hspif1, (int)floor((writepage)/16)); + SPIF_WritePage(&hspif1,writepage, (uint8_t *)writebuffer, 100,0); + +} + +void getindex(void){ + int readpage=MAX_WRITE_PAGE+1; + SPIF_ReadPage(&hspif1, readpage, (uint8_t *)indexbuffer, 50, 0); + memset(numbuf1,'$',10); + memset(numbuf2,'$',10); + int cnt=0; + if((indexbuffer[0]&0x0F)<10 ){ + while(indexbuffer[cnt]!='$'){ + + numbuf1[cnt]=indexbuffer[cnt]; + cnt++; + } + cnt++; + int cnt1=0; + while(indexbuffer[cnt]!='$'){ + + numbuf2[cnt1]=indexbuffer[cnt]; + cnt1++; + cnt++; + } + + pageoffset=atoi((uint8_t*)numbuf1); + pagenumber=atoi((uint8_t*)numbuf2); + } + else{ + storeindex(); + } + +} + +void writebuffertoflash(uint8_t * buffer,int bufferlenght){ + if((pagenumber+1)%16==0){ + if(sectoreraseen==0){ + SPIF_EraseSector(&hspif1, (int)floor((pagenumber+1)/16)); + sectoreraseen=1; + } + + } + if(bufferlenght+pageoffset<256){ + SPIF_WritePage(&hspif1,pagenumber, (uint8_t *)buffer, bufferlenght,pageoffset); + pageoffset=pageoffset+bufferlenght; + } + else{ + SPIF_WritePage(&hspif1,pagenumber, (uint8_t *)buffer, 256-pageoffset,pageoffset); + HAL_Delay(100); + SPIF_WritePage(&hspif1,pagenumber+1, (uint8_t *)buffer+(256-pageoffset), bufferlenght-(256-pageoffset),0); + pagenumber=pagenumber+1; + sectoreraseen=0; + pageoffset=(bufferlenght-(256-pageoffset)); + } + storeindex(); + +} + +/* USER CODE END 1 */ diff --git a/Software/stm32project/Core/Src/ssd1306.c b/Software/stm32project/Core/Src/ssd1306.c index 40a3065..1d197d0 100644 --- a/Software/stm32project/Core/Src/ssd1306.c +++ b/Software/stm32project/Core/Src/ssd1306.c @@ -662,6 +662,59 @@ void ssd1306_Drawarrow2(uint8_t x,uint8_t y, uint8_t r,float angle){ +} + +void batterygauge(float vbat,int x, int y,int currentsquare){ + ssd1306_Line(x+15,y+1,x+15,y+5, White); + ssd1306_Line(x+16,y+1,x+16,y+5, White); + ssd1306_DrawRectangle(x, y, x+14, y+6, White); + if(vbat<=3.7){ + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + if(currentsquare==1){ + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + } + else{ + + } + } + if(vbat>3.7 && vbat<= 3.9){ + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + if(currentsquare==1){ + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + } + else{ + + } + + } + if(vbat>3.9 && vbat<=4.1){ + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + + if(currentsquare==1){ + ssd1306_DrawRectangle(x+8, y+2, x+9, y+4, White); + + } + else{ + + } + } + + if(vbat>4.1){ + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + ssd1306_DrawRectangle(x+8, y+2, x+9, y+4, White); + if(currentsquare==1){ + ssd1306_DrawRectangle(x+11, y+2, x+12, y+4, White); + } + else{ + + } + } + + + + } diff --git a/Software/stm32project/Core/Src/statemachine.c b/Software/stm32project/Core/Src/statemachine.c index 6919028..c73475d 100644 --- a/Software/stm32project/Core/Src/statemachine.c +++ b/Software/stm32project/Core/Src/statemachine.c @@ -15,49 +15,63 @@ #include #include "usbd_def.h" #include "usbd_core.h" -#include "usbd_hid.h" +#include "spif.h" +#include "spi.h" extern int BTN_A; extern int BTN_B; extern uint8_t RxBuffer[RxBuffer_SIZE]; extern uint8_t DataBuffer[DataBuffer_SIZE]; +extern uint8_t flashwrite[256]; +extern uint8_t flashread[256]; extern STATE_TYPE state; extern GPS myData; -float vitmax=0.0; -COMPTEUR statecpt=STATE_HEURES; -extern int boumheure; -extern int boumminutes; -extern int choose; extern HEURE hrstate; extern SPEED spdstate; extern POS posstate; extern CHRONO chronostate; -extern KEYBOARD keyboardstate; - - +extern GIF gifstate; +USBSTATE usbstate=USBSTATE1; +BALISESTATE balisestate=BALISESTATE1; +float vitmax=0.0; float seconde=0; float min=0; -extern __IO uint32_t uwTick; uint32_t starttime=0; uint32_t calctime=0; extern float temp; +extern float vbat; uint8_t usbbuffer[64]; uint8_t usbtransmitbuf[64]; uint8_t gpscommand[100]; -int keycount=0; -extern keyboardHID keyboardhid; char str[20]; extern USBD_HandleTypeDef hUsbDeviceFS; extern UART_HandleTypeDef hlpuart1; extern DMA_HandleTypeDef hdma_lpuart_rx; +float t1=0; +float t2=0; +float t3=0; +float moy=0; +float framerate=0; +extern const unsigned char* epd_bitmap_allArray[57]; +extern const unsigned char* gif2allArray[31]; +extern const unsigned char* gif3allArray[74]; +extern SPIF_HandleTypeDef hspif1; +uint8_t str1[50]; +int flashbufferlen=0; +extern int pageoffset; +extern int pagenumber; +extern int sectoreraseen; +extern uint8_t indexbuffer[50]; +extern uint8_t numbuf1[10]; +extern uint8_t numbuf2[10]; +int erasetime=0; +int erasedisplay=0; +int usbtransmiten=0; - - -//le code qui permet d'avoir les ecran de donnée que l'on souhaite, changeable a souhait on peut d'ailleur rajouter des état ou rajouter des fonctionnalité au sein de chaque état, pas encore décidé de la version définitive. void statemachine(void){ switch(state){ case STATE_SPEED: @@ -101,6 +115,7 @@ void statemachine(void){ ssd1306_WriteString("Speed 1", Font_6x8, White); ssd1306_SetCursor(32, 44); ssd1306_WriteString("Wait GPS", Font_6x8, White); + batterygauge(vbat,35, 54,1); free(str); } if(BTN_B>=1){ @@ -142,8 +157,7 @@ void statemachine(void){ ssd1306_SetCursor(32, 32); snprintf(str,15, "%0.1f",(myData.speed)*3.6); ssd1306_WriteString(str, Font_11x18, White); - ssd1306_SetCursor(32, 54); - ssd1306_WriteString("kmh", Font_6x8, White); + batterygauge(vbat,35, 54,1); free(str); } @@ -153,6 +167,7 @@ void statemachine(void){ ssd1306_WriteString("Speed 3", Font_6x8, White); ssd1306_SetCursor(32, 44); ssd1306_WriteString("Wait GPS", Font_6x8, White); + batterygauge(vbat,35, 54,1); free(str); } @@ -170,6 +185,7 @@ void statemachine(void){ if(BTN_A>=1){ state++; BTN_A=0; + BTN_B=0; } break; @@ -202,6 +218,8 @@ void statemachine(void){ ssd1306_WriteString("Pos1", Font_6x8, White); ssd1306_SetCursor(32, 44); ssd1306_WriteString("Wait GPS", Font_6x8, White); + ssd1306_SetCursor(32, 54); + batterygauge(vbat,35, 54,1); free(str); } if(BTN_B>=1){ @@ -316,6 +334,9 @@ void statemachine(void){ if(BTN_A>=1){ state++; BTN_A=0; + BTN_B=0; + + } break; @@ -402,7 +423,7 @@ void statemachine(void){ snprintf(str,15, "hdop=%.1f",myData.hdop);//sert a connaitre la qualitée du fix si proche de 1 voir inférieur alors le fix est tres bon ssd1306_SetCursor(32, 32); ssd1306_WriteString(str, Font_6x8, White); - snprintf(str,15, "SatNb :%d",myData.satelliteCount); + snprintf(str,20, "v=%0.2fV",vbat); ssd1306_SetCursor(32, 42); ssd1306_WriteString(str, Font_6x8, White); ssd1306_SetCursor(32, 50); @@ -415,7 +436,8 @@ void statemachine(void){ ssd1306_SetCursor(32, 32); ssd1306_WriteString("INFO", Font_6x8, White); ssd1306_SetCursor(32, 41); - ssd1306_WriteString("Wait GPS", Font_6x8, White); + snprintf(str,15, "vbat=%0.2fV",vbat); + ssd1306_WriteString(str, Font_6x8, White); ssd1306_SetCursor(32, 50); snprintf(str,15, "T=%0.2fC",temp); ssd1306_WriteString(str, Font_6x8, White); @@ -481,52 +503,86 @@ void statemachine(void){ if(BTN_A>=1){ - state++; - uint8_t baudchange[]={0x24, 0x50, 0x4D, 0x54,0x4B ,0x32, 0x35 ,0x31 ,0x2C ,0x33, 0x38, 0x34 ,0x30, 0x30 ,0x2A, 0x32 ,0x37, 0x0A}; - __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT); - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)baudchange,18); - uint8_t disablenmea[]={0x24, 0x50, 0x4D, 0x54, 0x4B, 0x33, 0x31, 0x34, 0x2C, 0x30, 0x2C, 0x31, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, - 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2A, 0x32, 0x39};//$PMTK314,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0*29 - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)disablenmea,49); - uint8_t updaterate[]={0x24, 0x50, 0x4D, 0x54, 0x4B, 0x32, 0x32, 0x30, 0x2C, 0x20, 0x32, 0x30, 0x30, 0x2A, 0x32, 0x43};//$PMTK220, 200*2C - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)updaterate,16); - HAL_UART_Abort(&hlpuart1); - HAL_UART_DeInit(&hlpuart1); - hlpuart1.Init.BaudRate = 38400; - HAL_UART_Init(&hlpuart1); - HAL_UART_Abort(&hlpuart1); - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE); + state++; BTN_A=0; BTN_B=0; } break; - case STATE_MEMTEST: + + case STATE_BALISE: ssd1306_Fill(Black); - ssd1306_SetCursor(32, 32); - ssd1306_WriteString("test", Font_6x8, White); - nmea_parse(&myData, DataBuffer); + ssd1306_SetCursor(32,32); + ssd1306_WriteString("balise",Font_6x8,White); + switch(balisestate){ + case BALISESTATE1: + ssd1306_SetCursor(32,40); + ssd1306_WriteString("do nothing",Font_6x8,White); - snprintf(str,15, "spd=%.1f",myData.speed);//sert a connaitre la qualitée du fix si proche de 1 voir inférieur alors le fix est tres bon - ssd1306_SetCursor(32, 40); - ssd1306_WriteString(str, Font_6x8, White); - snprintf(str,15, "SatNb :%d",myData.satelliteCount); - ssd1306_SetCursor(32, 48); - ssd1306_WriteString(str, Font_6x8, White); - free(str); + if(BTN_B>=1){ + balisestate++; + BTN_B=0; + BTN_A=0; + } + break; + case BALISESTATE2: + + nmea_parse(&myData, DataBuffer); + if(pagenumber+1=1){ + balisestate--; + BTN_B=0; + BTN_A=0; + } + + } + + + + else{ + balisestate=2; + } + + + + break; + + case BALISESTATE3: + ssd1306_SetCursor(32,32); + ssd1306_WriteString("fin de",Font_6x8,White); + ssd1306_SetCursor(32,40); + ssd1306_WriteString("memoire",Font_6x8,White); + ssd1306_SetCursor(32,48); + snprintf((uint8_t *)str1,50,"%d,%d",pageoffset,pagenumber); + ssd1306_WriteString((uint8_t*)str1,Font_6x8,White); + break; + + + + } + if(BTN_A>=1){ - state--; - state--; - state--; - state--; - state--; - BTN_A=0; - BTN_B=0; - } + state++; + BTN_A=0; + BTN_B=0; + + + } + @@ -534,56 +590,130 @@ void statemachine(void){ break; + case STATE_USB: + ssd1306_Fill(Black); + ssd1306_SetCursor(32,32); + ssd1306_WriteString("usb",Font_6x8,White); + switch(usbstate){ + case USBSTATE1: + ssd1306_SetCursor(32,40); + ssd1306_WriteString("do nothing",Font_6x8,White); + usbtransmiten=0; + + if(BTN_B>=1){ + usbstate++; + BTN_B=0; + BTN_A=0; + } + if(BTN_A>=1){ + state--; + state--; + state--; + state--; + state--; + state--; + BTN_A=0; + BTN_B=0; + + + } + + + + break; + case USBSTATE2: + ssd1306_SetCursor(32,40); + ssd1306_WriteString("Push A",Font_6x8,White); + ssd1306_SetCursor(32,48); + ssd1306_WriteString("to erase",Font_6x8,White); + + if(erasedisplay==1){ + snprintf((uint8_t *)str,50,"t=%0.2f",(float)erasetime/1000); + ssd1306_SetCursor(32,56); + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + } + + + if(BTN_A>=1){ + erasetime=HAL_GetTick(); + SPIF_EraseChip(&hspif1); + erasetime=HAL_GetTick()-erasetime; + erasedisplay=1; + pageoffset=0; + pagenumber=0; + storeindex(); + BTN_A=0; + BTN_B=0; + } + + if(BTN_B>=1){ + + usbstate++; + BTN_B=0; + BTN_A=0; + } + + break; + + case USBSTATE3: + ssd1306_SetCursor(32,40); + ssd1306_WriteString("write",Font_6x8,White); + int i=0; + if(usbtransmiten==0){ + while(i<=pagenumber){ + SPIF_ReadPage(&hspif1,i, (uint8_t *)flashread, 256, 0); + CDC_Transmit_FS((uint8_t * )flashread,256); + HAL_Delay(100); + i++; + } + usbtransmiten=1; + } + else{ + + } + + + if(BTN_B>=1){ + usbstate--; + usbstate--; + BTN_B=0; + BTN_A=0; + } + if(BTN_A>=1){ + state--; + state--; + state--; + state--; + state--; + state--; + BTN_A=0; + BTN_B=0; + + + } + break; + + + + } + + + + + + + break; + } return ; } -// HAL_Delay(100); -// for(int i=0;i<10;i++){ -// displaybuf[i]=usbbuffer[i]; -// } -// ssd1306_WriteString((uint8_t*)displaybuf, Font_6x8, White); -// -// -// if(strcmp((uint8_t*)displaybuf,"temp")==0){ -// ssd1306_SetCursor(32, 48); -// snprintf((uint8_t*)usbtransmitbuf,64, "la temperature du processeur est de:%0.2fC\n",temp); -// snprintf(str,15, "T=%0.2fC",temp); -// ssd1306_WriteString(str, Font_6x8, White); -// } -// else{ -// ssd1306_SetCursor(32, 48); -// ssd1306_WriteString("nonvalide", Font_6x8, White); -// snprintf((uint8_t*)usbtransmitbuf,64, "Veuillez ecrire quelque chose\n"); -// -// } -// CDC_Transmit_FS((uint8_t * )usbtransmitbuf,strlen(usbtransmitbuf)); - - - -// ee_read(0, 2048, (uint8_t *)eepromold); -// while((eepromold[eeindex]&0xFF)!=0xFF){ -// eeindex++; -// } -// ee_format(0); -// -// memset((uint8_t*)strb,'0',10); -// memset((uint8_t*)eepromnew,'a',2048); -// memcpy((uint8_t*)eepromnew,(uint8_t*)eepromold,eeindex); -// -// snprintf((uint8_t*)strb,10, "%0.2f\n",temp); -// memcpy((uint8_t*)eepromnew[eeindex],(uint8_t*)strb,10); -// eeindex=eeindex+10; -// ee_write(0, 2048, (uint8_t *)eepromnew); -// ssd1306_SetCursor(32, 42); -// snprintf(str,15, "%d",eeindex); -// ssd1306_WriteString(str, Font_6x8, White); -// HAL_Delay(100); -// if(eeindex>=2048){ -// eeindex=0; -// } + + + + diff --git a/Software/stm32project/Core/Src/stm32l4xx_hal_msp.c b/Software/stm32project/Core/Src/stm32l4xx_hal_msp.c index 2f5834d..9e27b25 100644 --- a/Software/stm32project/Core/Src/stm32l4xx_hal_msp.c +++ b/Software/stm32project/Core/Src/stm32l4xx_hal_msp.c @@ -24,9 +24,6 @@ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ -extern DMA_HandleTypeDef hdma_adc1; - -extern DMA_HandleTypeDef hdma_lpuart_rx; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -80,352 +77,6 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } -/** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ADC_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA4 ------> ADC1_IN9 - */ - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* ADC1 DMA Init */ - /* ADC1 Init */ - hdma_adc1.Instance = DMA1_Channel1; - hdma_adc1.Init.Request = DMA_REQUEST_0; - hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; - hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - hdma_adc1.Init.Mode = DMA_NORMAL; - hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); - - /* ADC1 interrupt Init */ - HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(ADC1_IRQn); - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } - -} - -/** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA4 ------> ADC1_IN9 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); - - /* ADC1 DMA DeInit */ - HAL_DMA_DeInit(hadc->DMA_Handle); - - /* ADC1 interrupt DeInit */ - HAL_NVIC_DisableIRQ(ADC1_IRQn); - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - -} - -/** -* @brief I2C MSP Initialization -* This function configures the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hi2c->Instance==I2C3) - { - /* USER CODE BEGIN I2C3_MspInit 0 */ - - /* USER CODE END I2C3_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C3; - PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**I2C3 GPIO Configuration - PA7 ------> I2C3_SCL - PB4 (NJTRST) ------> I2C3_SDA - */ - GPIO_InitStruct.Pin = GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_I2C3_CLK_ENABLE(); - /* USER CODE BEGIN I2C3_MspInit 1 */ - - /* USER CODE END I2C3_MspInit 1 */ - } - -} - -/** -* @brief I2C MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) -{ - if(hi2c->Instance==I2C3) - { - /* USER CODE BEGIN I2C3_MspDeInit 0 */ - - /* USER CODE END I2C3_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_I2C3_CLK_DISABLE(); - - /**I2C3 GPIO Configuration - PA7 ------> I2C3_SCL - PB4 (NJTRST) ------> I2C3_SDA - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4); - - /* USER CODE BEGIN I2C3_MspDeInit 1 */ - - /* USER CODE END I2C3_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(huart->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* LPUART1 DMA Init */ - /* LPUART_RX Init */ - hdma_lpuart_rx.Instance = DMA2_Channel7; - hdma_lpuart_rx.Init.Request = DMA_REQUEST_4; - hdma_lpuart_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_lpuart_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_lpuart_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_lpuart_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_lpuart_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_lpuart_rx.Init.Mode = DMA_NORMAL; - hdma_lpuart_rx.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_lpuart_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_lpuart_rx); - - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - - /* LPUART1 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - - /* LPUART1 interrupt DeInit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - - /* USER CODE END LPUART1_MspDeInit 1 */ - } - -} - -/** -* @brief TIM_Base MSP Initialization -* This function configures the hardware resources used in this example -* @param htim_base: TIM_Base handle pointer -* @retval None -*/ -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) -{ - if(htim_base->Instance==TIM2) - { - /* USER CODE BEGIN TIM2_MspInit 0 */ - - /* USER CODE END TIM2_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_TIM2_CLK_ENABLE(); - /* USER CODE BEGIN TIM2_MspInit 1 */ - - /* USER CODE END TIM2_MspInit 1 */ - } - else if(htim_base->Instance==TIM7) - { - /* USER CODE BEGIN TIM7_MspInit 0 */ - - /* USER CODE END TIM7_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_TIM7_CLK_ENABLE(); - /* TIM7 interrupt Init */ - HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM7_IRQn); - /* USER CODE BEGIN TIM7_MspInit 1 */ - - /* USER CODE END TIM7_MspInit 1 */ - } - -} - -/** -* @brief TIM_Base MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param htim_base: TIM_Base handle pointer -* @retval None -*/ -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) -{ - if(htim_base->Instance==TIM2) - { - /* USER CODE BEGIN TIM2_MspDeInit 0 */ - - /* USER CODE END TIM2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM2_CLK_DISABLE(); - /* USER CODE BEGIN TIM2_MspDeInit 1 */ - - /* USER CODE END TIM2_MspDeInit 1 */ - } - else if(htim_base->Instance==TIM7) - { - /* USER CODE BEGIN TIM7_MspDeInit 0 */ - - /* USER CODE END TIM7_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_TIM7_CLK_DISABLE(); - - /* TIM7 interrupt DeInit */ - HAL_NVIC_DisableIRQ(TIM7_IRQn); - /* USER CODE BEGIN TIM7_MspDeInit 1 */ - - /* USER CODE END TIM7_MspDeInit 1 */ - } - -} - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Software/stm32project/Core/Src/stm32l4xx_it.c b/Software/stm32project/Core/Src/stm32l4xx_it.c index 2a58c4c..fb01ddd 100644 --- a/Software/stm32project/Core/Src/stm32l4xx_it.c +++ b/Software/stm32project/Core/Src/stm32l4xx_it.c @@ -22,7 +22,6 @@ #include "stm32l4xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ -#include "ssd1306.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -42,6 +41,7 @@ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ +extern int cont=0; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -60,9 +60,7 @@ extern DMA_HandleTypeDef hdma_adc1; extern ADC_HandleTypeDef hadc1; extern DMA_HandleTypeDef hdma_lpuart_rx; extern UART_HandleTypeDef hlpuart1; -extern TIM_HandleTypeDef htim7; /* USER CODE BEGIN EV */ -int distanceparcouru=0; /* USER CODE END EV */ /******************************************************************************/ @@ -94,10 +92,12 @@ void HardFault_Handler(void) while (1) { /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - ssd1306_Fill(Black); - ssd1306_SetCursor(33, 36); - ssd1306_WriteString("hard_fault", Font_6x8, White); - ssd1306_UpdateScreen(); + //ssd1306_Fill(Black); + //ssd1306_SetCursor(33, 36); + //ssd1306_WriteString("rincee en", Font_6x8, White); + //ssd1306_SetCursor(33, 46); + //ssd1306_WriteString("code", Font_6x8, White); + //ssd1306_UpdateScreen(); /* USER CODE END W1_HardFault_IRQn 0 */ } @@ -193,7 +193,6 @@ void PendSV_Handler(void) void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ - distanceparcouru+=1; /* USER CODE END SysTick_IRQn 0 */ @@ -210,6 +209,20 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32l4xx.s). */ /******************************************************************************/ +/** + * @brief This function handles EXTI line1 interrupt. + */ +void EXTI1_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI1_IRQn 0 */ + + /* USER CODE END EXTI1_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + /* USER CODE BEGIN EXTI1_IRQn 1 */ + + /* USER CODE END EXTI1_IRQn 1 */ +} + /** * @brief This function handles DMA1 channel1 global interrupt. */ @@ -239,33 +252,17 @@ void ADC1_IRQHandler(void) } /** - * @brief This function handles EXTI line[15:10] interrupts. - */ -void EXTI15_10_IRQHandler(void) -{ - /* USER CODE BEGIN EXTI15_10_IRQn 0 */ - - /* USER CODE END EXTI15_10_IRQn 0 */ - HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); - HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); - /* USER CODE BEGIN EXTI15_10_IRQn 1 */ - - /* USER CODE END EXTI15_10_IRQn 1 */ -} - -/** - * @brief This function handles TIM7 global interrupt. + * @brief This function handles EXTI line[9:5] interrupts. */ -void TIM7_IRQHandler(void) +void EXTI9_5_IRQHandler(void) { - /* USER CODE BEGIN TIM7_IRQn 0 */ - distanceparcouru+=1; + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ - /* USER CODE END TIM7_IRQn 0 */ - HAL_TIM_IRQHandler(&htim7); - /* USER CODE BEGIN TIM7_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ - /* USER CODE END TIM7_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 1 */ } /** diff --git a/Software/stm32project/Core/Src/tim.c b/Software/stm32project/Core/Src/tim.c new file mode 100644 index 0000000..15a74b6 --- /dev/null +++ b/Software/stm32project/Core/Src/tim.c @@ -0,0 +1,104 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim2; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 400-1; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 10000-1; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Software/stm32project/Core/Src/usart.c b/Software/stm32project/Core/Src/usart.c new file mode 100644 index 0000000..8a61d0a --- /dev/null +++ b/Software/stm32project/Core/Src/usart.c @@ -0,0 +1,260 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ +extern uint16_t oldPos; +extern uint16_t newPos; +extern uint8_t RxBuffer[RxBuffer_SIZE]; +extern uint8_t DataBuffer[DataBuffer_SIZE]; +/* USER CODE END 0 */ + +UART_HandleTypeDef hlpuart1; +UART_HandleTypeDef huart1; +DMA_HandleTypeDef hdma_lpuart_rx; + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 9600; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* LPUART1 DMA Init */ + /* LPUART_RX Init */ + hdma_lpuart_rx.Instance = DMA2_Channel7; + hdma_lpuart_rx.Init.Request = DMA_REQUEST_4; + hdma_lpuart_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_lpuart_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_lpuart_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_lpuart_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_lpuart_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_lpuart_rx.Init.Mode = DMA_NORMAL; + hdma_lpuart_rx.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_lpuart_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_lpuart_rx); + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB6 ------> USART1_TX + PB7 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); + + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* LPUART1 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + + /* USER CODE END LPUART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB6 ------> USART1_TX + PB7 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ + oldPos = newPos; //keep track of the last position in the buffer + if(oldPos + 64 > DataBuffer_SIZE){ //if the buffer is full, parse it, then reset the buffer + + uint16_t datatocopy = DataBuffer_SIZE-oldPos; // find out how much space is left in the main buffer + memcpy ((uint8_t *)DataBuffer+oldPos, RxBuffer, datatocopy); // copy data in that remaining space + + oldPos = 0; // point to the start of the buffer + memcpy ((uint8_t *)DataBuffer, (uint8_t *)RxBuffer+datatocopy, (64-datatocopy)); // copy the remaining data + newPos = (64-datatocopy); // update the position + } + else{ + memcpy((uint8_t *)DataBuffer+oldPos, RxBuffer, 64); //copy received data to the buffer + newPos = 64+oldPos; //update buffer position + + } + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//on recoit par dma à nouveau 64 caractères + __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT);//on desactive l'interruption afin de ne pas être interrompu tout le temps + + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//l'appel de cette fonction réactive l'intérruption. +} +/* USER CODE END 1 */ diff --git a/Software/stm32project/Debug/Core/Src/adc.cyclo b/Software/stm32project/Debug/Core/Src/adc.cyclo new file mode 100644 index 0000000..987e3b3 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/adc.cyclo @@ -0,0 +1,4 @@ +../Core/Src/adc.c:37:6:MX_ADC1_Init 5 +../Core/Src/adc.c:108:6:HAL_ADC_MspInit 3 +../Core/Src/adc.c:156:6:HAL_ADC_MspDeInit 2 +../Core/Src/adc.c:184:6:HAL_ADC_ConvCpltCallback 2 diff --git a/Software/stm32project/Debug/Core/Src/adc.d b/Software/stm32project/Debug/Core/Src/adc.d new file mode 100644 index 0000000..a7ae1ae --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/adc.d @@ -0,0 +1,79 @@ +Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/adc.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/adc.o b/Software/stm32project/Debug/Core/Src/adc.o new file mode 100644 index 0000000..0f0b643 Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/adc.o differ diff --git a/Software/stm32project/Debug/Core/Src/adc.su b/Software/stm32project/Debug/Core/Src/adc.su new file mode 100644 index 0000000..59f824d --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/adc.su @@ -0,0 +1,4 @@ +../Core/Src/adc.c:37:6:MX_ADC1_Init 32 static +../Core/Src/adc.c:108:6:HAL_ADC_MspInit 48 static +../Core/Src/adc.c:156:6:HAL_ADC_MspDeInit 16 static +../Core/Src/adc.c:184:6:HAL_ADC_ConvCpltCallback 32 static diff --git a/Software/stm32project/Debug/Core/Src/dma.cyclo b/Software/stm32project/Debug/Core/Src/dma.cyclo new file mode 100644 index 0000000..a9d9f42 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/dma.cyclo @@ -0,0 +1 @@ +../Core/Src/dma.c:39:6:MX_DMA_Init 1 diff --git a/Software/stm32project/Debug/Core/Src/dma.d b/Software/stm32project/Debug/Core/Src/dma.d new file mode 100644 index 0000000..c7c6863 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/dma.d @@ -0,0 +1,79 @@ +Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/dma.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/dma.o b/Software/stm32project/Debug/Core/Src/dma.o new file mode 100644 index 0000000..ba1e029 Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/dma.o differ diff --git a/Software/stm32project/Debug/Core/Src/dma.su b/Software/stm32project/Debug/Core/Src/dma.su new file mode 100644 index 0000000..802020b --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/dma.su @@ -0,0 +1 @@ +../Core/Src/dma.c:39:6:MX_DMA_Init 16 static diff --git a/Software/stm32project/Debug/Core/Src/gpio.cyclo b/Software/stm32project/Debug/Core/Src/gpio.cyclo new file mode 100644 index 0000000..56b6958 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/gpio.cyclo @@ -0,0 +1 @@ +../Core/Src/gpio.c:42:6:MX_GPIO_Init 1 diff --git a/Software/stm32project/Debug/Core/Src/gpio.d b/Software/stm32project/Debug/Core/Src/gpio.d new file mode 100644 index 0000000..8903f67 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/gpio.d @@ -0,0 +1,79 @@ +Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/gpio.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/gpio.o b/Software/stm32project/Debug/Core/Src/gpio.o new file mode 100644 index 0000000..7f9c634 Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/gpio.o differ diff --git a/Software/stm32project/Debug/Core/Src/gpio.su b/Software/stm32project/Debug/Core/Src/gpio.su new file mode 100644 index 0000000..f003919 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/gpio.su @@ -0,0 +1 @@ +../Core/Src/gpio.c:42:6:MX_GPIO_Init 40 static diff --git a/Software/stm32project/Debug/Core/Src/i2c.cyclo b/Software/stm32project/Debug/Core/Src/i2c.cyclo new file mode 100644 index 0000000..295d342 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/i2c.cyclo @@ -0,0 +1,4 @@ +../Core/Src/i2c.c:31:6:MX_I2C1_Init 4 +../Core/Src/i2c.c:74:6:MX_I2C3_Init 4 +../Core/Src/i2c.c:121:6:HAL_I2C_MspInit 5 +../Core/Src/i2c.c:202:6:HAL_I2C_MspDeInit 3 diff --git a/Software/stm32project/Debug/Core/Src/i2c.d b/Software/stm32project/Debug/Core/Src/i2c.d new file mode 100644 index 0000000..03f6170 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/i2c.d @@ -0,0 +1,79 @@ +Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/i2c.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/i2c.o b/Software/stm32project/Debug/Core/Src/i2c.o new file mode 100644 index 0000000..6dc9e3f Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/i2c.o differ diff --git a/Software/stm32project/Debug/Core/Src/i2c.su b/Software/stm32project/Debug/Core/Src/i2c.su new file mode 100644 index 0000000..5cae3f8 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/i2c.su @@ -0,0 +1,4 @@ +../Core/Src/i2c.c:31:6:MX_I2C1_Init 8 static +../Core/Src/i2c.c:74:6:MX_I2C3_Init 8 static +../Core/Src/i2c.c:121:6:HAL_I2C_MspInit 144 static +../Core/Src/i2c.c:202:6:HAL_I2C_MspDeInit 16 static diff --git a/Software/stm32project/Debug/Core/Src/main.cyclo b/Software/stm32project/Debug/Core/Src/main.cyclo index 704c680..449fd76 100644 --- a/Software/stm32project/Debug/Core/Src/main.cyclo +++ b/Software/stm32project/Debug/Core/Src/main.cyclo @@ -1,14 +1,5 @@ -../Core/Src/main.c:149:6:HAL_GPIO_EXTI_Callback 3 -../Core/Src/main.c:168:7:HAL_UART_RxCpltCallback 3 -../Core/Src/main.c:190:6:HAL_ADC_ConvCpltCallback 2 -../Core/Src/main.c:215:5:main 1 -../Core/Src/main.c:311:6:SystemClock_Config 4 -../Core/Src/main.c:361:6:PeriphCommonClock_Config 2 -../Core/Src/main.c:388:13:MX_ADC1_Init 4 -../Core/Src/main.c:455:13:MX_I2C3_Init 4 -../Core/Src/main.c:507:13:MX_LPUART1_UART_Init 2 -../Core/Src/main.c:541:13:MX_TIM2_Init 4 -../Core/Src/main.c:586:13:MX_TIM7_Init 3 -../Core/Src/main.c:622:13:MX_DMA_Init 1 -../Core/Src/main.c:644:13:MX_GPIO_Init 1 -../Core/Src/main.c:687:6:Error_Handler 1 +../Core/Src/main.c:147:6:HAL_GPIO_EXTI_Callback 3 +../Core/Src/main.c:171:5:main 1 +../Core/Src/main.c:296:6:SystemClock_Config 4 +../Core/Src/main.c:346:6:PeriphCommonClock_Config 2 +../Core/Src/main.c:376:6:Error_Handler 1 diff --git a/Software/stm32project/Debug/Core/Src/main.d b/Software/stm32project/Debug/Core/Src/main.d index 669a2d5..a7b0a1e 100644 --- a/Software/stm32project/Debug/Core/Src/main.d +++ b/Software/stm32project/Debug/Core/Src/main.d @@ -31,16 +31,22 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ - ../USB_DEVICE/App/usb_device.h \ + ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/dma.h ../Core/Inc/i2c.h \ + ../Core/Inc/usart.h ../Core/Inc/spi.h ../Core/Inc/nmea_parse.h \ + ../Core/Inc/tim.h ../USB_DEVICE/App/usb_device.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ - ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/ssd1306.h \ - ../Core/Inc/ssd1306_conf.h ../Core/Inc/ssd1306_fonts.h \ - ../Core/Inc/main.h ../Core/Inc/statemachine.h ../Core/Inc/ssd1306.h \ - ../Core/Inc/nmea_parse.h + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/gpio.h \ + ../Core/Inc/ssd1306.h ../Core/Inc/ssd1306_conf.h \ + ../Core/Inc/ssd1306_fonts.h ../Core/Inc/statemachine.h \ + ../Core/Inc/ssd1306.h ../Core/Inc/nmea_parse.h \ + ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h \ + ../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h ../Core/Inc/main.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: ../Core/Inc/stm32l4xx_hal_conf.h: @@ -74,17 +80,29 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: +../Core/Inc/adc.h: +../Core/Inc/main.h: +../Core/Inc/dma.h: +../Core/Inc/i2c.h: +../Core/Inc/usart.h: +../Core/Inc/spi.h: +../Core/Inc/nmea_parse.h: +../Core/Inc/tim.h: ../USB_DEVICE/App/usb_device.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: ../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/gpio.h: ../Core/Inc/ssd1306.h: ../Core/Inc/ssd1306_conf.h: ../Core/Inc/ssd1306_fonts.h: -../Core/Inc/main.h: ../Core/Inc/statemachine.h: ../Core/Inc/ssd1306.h: ../Core/Inc/nmea_parse.h: +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h: +../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h: diff --git a/Software/stm32project/Debug/Core/Src/main.o b/Software/stm32project/Debug/Core/Src/main.o index 24dcf91..9f779a9 100644 Binary files a/Software/stm32project/Debug/Core/Src/main.o and b/Software/stm32project/Debug/Core/Src/main.o differ diff --git a/Software/stm32project/Debug/Core/Src/main.su b/Software/stm32project/Debug/Core/Src/main.su index 49c80ae..0af3ea6 100644 --- a/Software/stm32project/Debug/Core/Src/main.su +++ b/Software/stm32project/Debug/Core/Src/main.su @@ -1,14 +1,5 @@ -../Core/Src/main.c:149:6:HAL_GPIO_EXTI_Callback 16 static -../Core/Src/main.c:168:7:HAL_UART_RxCpltCallback 40 static -../Core/Src/main.c:190:6:HAL_ADC_ConvCpltCallback 32 static -../Core/Src/main.c:215:5:main 16 static -../Core/Src/main.c:311:6:SystemClock_Config 96 static -../Core/Src/main.c:361:6:PeriphCommonClock_Config 96 static -../Core/Src/main.c:388:13:MX_ADC1_Init 32 static -../Core/Src/main.c:455:13:MX_I2C3_Init 8 static -../Core/Src/main.c:507:13:MX_LPUART1_UART_Init 8 static -../Core/Src/main.c:541:13:MX_TIM2_Init 40 static -../Core/Src/main.c:586:13:MX_TIM7_Init 24 static -../Core/Src/main.c:622:13:MX_DMA_Init 16 static -../Core/Src/main.c:644:13:MX_GPIO_Init 40 static -../Core/Src/main.c:687:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:147:6:HAL_GPIO_EXTI_Callback 16 static +../Core/Src/main.c:171:5:main 16 static +../Core/Src/main.c:296:6:SystemClock_Config 96 static +../Core/Src/main.c:346:6:PeriphCommonClock_Config 96 static +../Core/Src/main.c:376:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Software/stm32project/Debug/Core/Src/nmea_parse.d b/Software/stm32project/Debug/Core/Src/nmea_parse.d index 8b87d5f..db8fcc6 100644 --- a/Software/stm32project/Debug/Core/Src/nmea_parse.d +++ b/Software/stm32project/Debug/Core/Src/nmea_parse.d @@ -31,6 +31,8 @@ Core/Src/nmea_parse.o: ../Core/Src/nmea_parse.c ../Core/Inc/nmea_parse.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Core/Src/nmea_parse.o: ../Core/Src/nmea_parse.c ../Core/Inc/nmea_parse.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Core/Src/nmea_parse.o b/Software/stm32project/Debug/Core/Src/nmea_parse.o index 5a4b2e4..4db165e 100644 Binary files a/Software/stm32project/Debug/Core/Src/nmea_parse.o and b/Software/stm32project/Debug/Core/Src/nmea_parse.o differ diff --git a/Software/stm32project/Debug/Core/Src/spi.cyclo b/Software/stm32project/Debug/Core/Src/spi.cyclo new file mode 100644 index 0000000..0864cfa --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/spi.cyclo @@ -0,0 +1,7 @@ +../Core/Src/spi.c:46:6:MX_SPI1_Init 2 +../Core/Src/spi.c:80:6:HAL_SPI_MspInit 2 +../Core/Src/spi.c:119:6:HAL_SPI_MspDeInit 2 +../Core/Src/spi.c:146:5:csvframe 1 +../Core/Src/spi.c:153:6:storeindex 2 +../Core/Src/spi.c:163:6:getindex 4 +../Core/Src/spi.c:193:6:writebuffertoflash 5 diff --git a/Software/stm32project/Debug/Core/Src/spi.d b/Software/stm32project/Debug/Core/Src/spi.d new file mode 100644 index 0000000..c50fa3b --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/spi.d @@ -0,0 +1,94 @@ +Core/Src/spi.o: ../Core/Src/spi.c ../Core/Inc/spi.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ + ../Core/Inc/nmea_parse.h ../Core/Inc/statemachine.h \ + ../Core/Inc/ssd1306.h ../Core/Inc/ssd1306_conf.h \ + ../Core/Inc/ssd1306_fonts.h \ + ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h \ + ../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h ../Core/Inc/nmea_parse.h \ + ../Core/Inc/ssd1306.h +../Core/Inc/spi.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: +../Core/Inc/nmea_parse.h: +../Core/Inc/statemachine.h: +../Core/Inc/ssd1306.h: +../Core/Inc/ssd1306_conf.h: +../Core/Inc/ssd1306_fonts.h: +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h: +../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h: +../Core/Inc/nmea_parse.h: +../Core/Inc/ssd1306.h: diff --git a/Software/stm32project/Debug/Core/Src/spi.o b/Software/stm32project/Debug/Core/Src/spi.o new file mode 100644 index 0000000..ca5a5cf Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/spi.o differ diff --git a/Software/stm32project/Debug/Core/Src/spi.su b/Software/stm32project/Debug/Core/Src/spi.su new file mode 100644 index 0000000..37fe668 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/spi.su @@ -0,0 +1,7 @@ +../Core/Src/spi.c:46:6:MX_SPI1_Init 8 static +../Core/Src/spi.c:80:6:HAL_SPI_MspInit 48 static +../Core/Src/spi.c:119:6:HAL_SPI_MspDeInit 16 static +../Core/Src/spi.c:146:5:csvframe 152 static +../Core/Src/spi.c:153:6:storeindex 120 static +../Core/Src/spi.c:163:6:getindex 32 static +../Core/Src/spi.c:193:6:writebuffertoflash 24 static diff --git a/Software/stm32project/Debug/Core/Src/ssd1306.cyclo b/Software/stm32project/Debug/Core/Src/ssd1306.cyclo index 6281479..2cec9be 100644 --- a/Software/stm32project/Debug/Core/Src/ssd1306.cyclo +++ b/Software/stm32project/Debug/Core/Src/ssd1306.cyclo @@ -25,3 +25,4 @@ ../Core/Src/ssd1306.c:524:9:ssd1306_GetDisplayOn 1 ../Core/Src/ssd1306.c:528:6:ssd1306_Drawarrow 9 ../Core/Src/ssd1306.c:637:6:ssd1306_Drawarrow2 3 +../Core/Src/ssd1306.c:667:6:batterygauge 11 diff --git a/Software/stm32project/Debug/Core/Src/ssd1306.d b/Software/stm32project/Debug/Core/Src/ssd1306.d index 2a9bd56..c673edb 100644 --- a/Software/stm32project/Debug/Core/Src/ssd1306.d +++ b/Software/stm32project/Debug/Core/Src/ssd1306.d @@ -32,6 +32,8 @@ Core/Src/ssd1306.o: ../Core/Src/ssd1306.c ../Core/Inc/ssd1306.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -72,6 +74,8 @@ Core/Src/ssd1306.o: ../Core/Src/ssd1306.c ../Core/Inc/ssd1306.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Core/Src/ssd1306.o b/Software/stm32project/Debug/Core/Src/ssd1306.o index 7af6376..855c5bb 100644 Binary files a/Software/stm32project/Debug/Core/Src/ssd1306.o and b/Software/stm32project/Debug/Core/Src/ssd1306.o differ diff --git a/Software/stm32project/Debug/Core/Src/ssd1306.su b/Software/stm32project/Debug/Core/Src/ssd1306.su index afc6cc2..9d2d5be 100644 --- a/Software/stm32project/Debug/Core/Src/ssd1306.su +++ b/Software/stm32project/Debug/Core/Src/ssd1306.su @@ -25,3 +25,4 @@ ../Core/Src/ssd1306.c:524:9:ssd1306_GetDisplayOn 4 static ../Core/Src/ssd1306.c:528:6:ssd1306_Drawarrow 32 static ../Core/Src/ssd1306.c:637:6:ssd1306_Drawarrow2 56 static +../Core/Src/ssd1306.c:667:6:batterygauge 40 static diff --git a/Software/stm32project/Debug/Core/Src/ssd1306_fonts.o b/Software/stm32project/Debug/Core/Src/ssd1306_fonts.o index ddbd0a8..2e28ee7 100644 Binary files a/Software/stm32project/Debug/Core/Src/ssd1306_fonts.o and b/Software/stm32project/Debug/Core/Src/ssd1306_fonts.o differ diff --git a/Software/stm32project/Debug/Core/Src/statemachine.cyclo b/Software/stm32project/Debug/Core/Src/statemachine.cyclo index b83a04a..b6f9bd2 100644 --- a/Software/stm32project/Debug/Core/Src/statemachine.cyclo +++ b/Software/stm32project/Debug/Core/Src/statemachine.cyclo @@ -1 +1 @@ -../Core/Src/statemachine.c:61:6:statemachine 54 +../Core/Src/statemachine.c:75:6:statemachine 75 diff --git a/Software/stm32project/Debug/Core/Src/statemachine.d b/Software/stm32project/Debug/Core/Src/statemachine.d index 0cd736d..6fdbc01 100644 --- a/Software/stm32project/Debug/Core/Src/statemachine.d +++ b/Software/stm32project/Debug/Core/Src/statemachine.d @@ -31,6 +31,8 @@ Core/Src/statemachine.o: ../Core/Src/statemachine.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -46,8 +48,9 @@ Core/Src/statemachine.o: ../Core/Src/statemachine.c ../Core/Inc/main.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ - ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ - ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h + ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h \ + ../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h ../Core/Inc/spi.h \ + ../Core/Inc/nmea_parse.h ../Core/Inc/main.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: ../Core/Inc/stm32l4xx_hal_conf.h: @@ -81,6 +84,8 @@ Core/Src/statemachine.o: ../Core/Src/statemachine.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: @@ -99,5 +104,7 @@ Core/Src/statemachine.o: ../Core/Src/statemachine.c ../Core/Inc/main.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: -../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h: +../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h: +../Core/Inc/spi.h: +../Core/Inc/nmea_parse.h: diff --git a/Software/stm32project/Debug/Core/Src/statemachine.o b/Software/stm32project/Debug/Core/Src/statemachine.o index 72653a2..e4c2001 100644 Binary files a/Software/stm32project/Debug/Core/Src/statemachine.o and b/Software/stm32project/Debug/Core/Src/statemachine.o differ diff --git a/Software/stm32project/Debug/Core/Src/statemachine.su b/Software/stm32project/Debug/Core/Src/statemachine.su index 7a7f1cc..840f281 100644 --- a/Software/stm32project/Debug/Core/Src/statemachine.su +++ b/Software/stm32project/Debug/Core/Src/statemachine.su @@ -1 +1 @@ -../Core/Src/statemachine.c:61:6:statemachine 232 static +../Core/Src/statemachine.c:75:6:statemachine 152 static diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.cyclo b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.cyclo index a60d133..241993e 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.cyclo +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.cyclo @@ -1,9 +1 @@ -../Core/Src/stm32l4xx_hal_msp.c:67:6:HAL_MspInit 1 -../Core/Src/stm32l4xx_hal_msp.c:89:6:HAL_ADC_MspInit 3 -../Core/Src/stm32l4xx_hal_msp.c:143:6:HAL_ADC_MspDeInit 2 -../Core/Src/stm32l4xx_hal_msp.c:176:6:HAL_I2C_MspInit 3 -../Core/Src/stm32l4xx_hal_msp.c:230:6:HAL_I2C_MspDeInit 2 -../Core/Src/stm32l4xx_hal_msp.c:261:6:HAL_UART_MspInit 4 -../Core/Src/stm32l4xx_hal_msp.c:329:6:HAL_UART_MspDeInit 2 -../Core/Src/stm32l4xx_hal_msp.c:363:6:HAL_TIM_Base_MspInit 3 -../Core/Src/stm32l4xx_hal_msp.c:399:6:HAL_TIM_Base_MspDeInit 3 +../Core/Src/stm32l4xx_hal_msp.c:64:6:HAL_MspInit 1 diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.d b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.d index 43b8e92..5f04ad5 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.d +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.d @@ -31,6 +31,8 @@ Core/Src/stm32l4xx_hal_msp.o: ../Core/Src/stm32l4xx_hal_msp.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Core/Src/stm32l4xx_hal_msp.o: ../Core/Src/stm32l4xx_hal_msp.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.o b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.o index a6b7461..c4fb83f 100644 Binary files a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.o and b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.o differ diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.su b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.su index 89639d1..e2d447d 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.su +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_hal_msp.su @@ -1,9 +1 @@ -../Core/Src/stm32l4xx_hal_msp.c:67:6:HAL_MspInit 16 static -../Core/Src/stm32l4xx_hal_msp.c:89:6:HAL_ADC_MspInit 48 static -../Core/Src/stm32l4xx_hal_msp.c:143:6:HAL_ADC_MspDeInit 16 static -../Core/Src/stm32l4xx_hal_msp.c:176:6:HAL_I2C_MspInit 136 static -../Core/Src/stm32l4xx_hal_msp.c:230:6:HAL_I2C_MspDeInit 16 static -../Core/Src/stm32l4xx_hal_msp.c:261:6:HAL_UART_MspInit 128 static -../Core/Src/stm32l4xx_hal_msp.c:329:6:HAL_UART_MspDeInit 16 static -../Core/Src/stm32l4xx_hal_msp.c:363:6:HAL_TIM_Base_MspInit 24 static -../Core/Src/stm32l4xx_hal_msp.c:399:6:HAL_TIM_Base_MspDeInit 16 static +../Core/Src/stm32l4xx_hal_msp.c:64:6:HAL_MspInit 16 static diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.cyclo b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.cyclo index dab441e..71ede61 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.cyclo +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.cyclo @@ -1,5 +1,5 @@ -../Core/Src/stm32l4xx_it.c:74:6:NMI_Handler 1 -../Core/Src/stm32l4xx_it.c:89:6:HardFault_Handler 1 +../Core/Src/stm32l4xx_it.c:72:6:NMI_Handler 1 +../Core/Src/stm32l4xx_it.c:87:6:HardFault_Handler 1 ../Core/Src/stm32l4xx_it.c:109:6:MemManage_Handler 1 ../Core/Src/stm32l4xx_it.c:124:6:BusFault_Handler 1 ../Core/Src/stm32l4xx_it.c:139:6:UsageFault_Handler 1 @@ -7,10 +7,10 @@ ../Core/Src/stm32l4xx_it.c:167:6:DebugMon_Handler 1 ../Core/Src/stm32l4xx_it.c:180:6:PendSV_Handler 1 ../Core/Src/stm32l4xx_it.c:193:6:SysTick_Handler 1 -../Core/Src/stm32l4xx_it.c:216:6:DMA1_Channel1_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:230:6:ADC1_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:244:6:EXTI15_10_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:259:6:TIM7_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:274:6:USB_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:288:6:DMA2_Channel7_IRQHandler 1 -../Core/Src/stm32l4xx_it.c:302:6:LPUART1_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:215:6:EXTI1_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:229:6:DMA1_Channel1_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:243:6:ADC1_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:257:6:EXTI9_5_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:271:6:USB_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:285:6:DMA2_Channel7_IRQHandler 1 +../Core/Src/stm32l4xx_it.c:299:6:LPUART1_IRQHandler 1 diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.d b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.d index be75033..c20fb9c 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.d +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.d @@ -31,13 +31,13 @@ Core/Src/stm32l4xx_it.o: ../Core/Src/stm32l4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ - ../Core/Inc/stm32l4xx_it.h ../Core/Inc/ssd1306.h \ - ../Core/Inc/ssd1306_conf.h ../Core/Inc/ssd1306_fonts.h \ - ../Core/Inc/main.h + ../Core/Inc/stm32l4xx_it.h ../Core/Inc/main.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: ../Core/Inc/stm32l4xx_hal_conf.h: @@ -71,12 +71,10 @@ Core/Src/stm32l4xx_it.o: ../Core/Src/stm32l4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: ../Core/Inc/stm32l4xx_it.h: -../Core/Inc/ssd1306.h: -../Core/Inc/ssd1306_conf.h: -../Core/Inc/ssd1306_fonts.h: -../Core/Inc/main.h: diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.o b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.o index 24751aa..fe7f70c 100644 Binary files a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.o and b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.o differ diff --git a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.su b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.su index 4ceca50..d5c7740 100644 --- a/Software/stm32project/Debug/Core/Src/stm32l4xx_it.su +++ b/Software/stm32project/Debug/Core/Src/stm32l4xx_it.su @@ -1,5 +1,5 @@ -../Core/Src/stm32l4xx_it.c:74:6:NMI_Handler 4 static -../Core/Src/stm32l4xx_it.c:89:6:HardFault_Handler 8 static +../Core/Src/stm32l4xx_it.c:72:6:NMI_Handler 4 static +../Core/Src/stm32l4xx_it.c:87:6:HardFault_Handler 4 static ../Core/Src/stm32l4xx_it.c:109:6:MemManage_Handler 4 static ../Core/Src/stm32l4xx_it.c:124:6:BusFault_Handler 4 static ../Core/Src/stm32l4xx_it.c:139:6:UsageFault_Handler 4 static @@ -7,10 +7,10 @@ ../Core/Src/stm32l4xx_it.c:167:6:DebugMon_Handler 4 static ../Core/Src/stm32l4xx_it.c:180:6:PendSV_Handler 4 static ../Core/Src/stm32l4xx_it.c:193:6:SysTick_Handler 8 static -../Core/Src/stm32l4xx_it.c:216:6:DMA1_Channel1_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:230:6:ADC1_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:244:6:EXTI15_10_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:259:6:TIM7_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:274:6:USB_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:288:6:DMA2_Channel7_IRQHandler 8 static -../Core/Src/stm32l4xx_it.c:302:6:LPUART1_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:215:6:EXTI1_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:229:6:DMA1_Channel1_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:243:6:ADC1_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:257:6:EXTI9_5_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:271:6:USB_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:285:6:DMA2_Channel7_IRQHandler 8 static +../Core/Src/stm32l4xx_it.c:299:6:LPUART1_IRQHandler 8 static diff --git a/Software/stm32project/Debug/Core/Src/subdir.mk b/Software/stm32project/Debug/Core/Src/subdir.mk index 926b590..cb02fb9 100644 --- a/Software/stm32project/Debug/Core/Src/subdir.mk +++ b/Software/stm32project/Debug/Core/Src/subdir.mk @@ -5,8 +5,13 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ +../Core/Src/adc.c \ +../Core/Src/dma.c \ +../Core/Src/gpio.c \ +../Core/Src/i2c.c \ ../Core/Src/main.c \ ../Core/Src/nmea_parse.c \ +../Core/Src/spi.c \ ../Core/Src/ssd1306.c \ ../Core/Src/ssd1306_fonts.c \ ../Core/Src/statemachine.c \ @@ -14,11 +19,18 @@ C_SRCS += \ ../Core/Src/stm32l4xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ -../Core/Src/system_stm32l4xx.c +../Core/Src/system_stm32l4xx.c \ +../Core/Src/tim.c \ +../Core/Src/usart.c OBJS += \ +./Core/Src/adc.o \ +./Core/Src/dma.o \ +./Core/Src/gpio.o \ +./Core/Src/i2c.o \ ./Core/Src/main.o \ ./Core/Src/nmea_parse.o \ +./Core/Src/spi.o \ ./Core/Src/ssd1306.o \ ./Core/Src/ssd1306_fonts.o \ ./Core/Src/statemachine.o \ @@ -26,11 +38,18 @@ OBJS += \ ./Core/Src/stm32l4xx_it.o \ ./Core/Src/syscalls.o \ ./Core/Src/sysmem.o \ -./Core/Src/system_stm32l4xx.o +./Core/Src/system_stm32l4xx.o \ +./Core/Src/tim.o \ +./Core/Src/usart.o C_DEPS += \ +./Core/Src/adc.d \ +./Core/Src/dma.d \ +./Core/Src/gpio.d \ +./Core/Src/i2c.d \ ./Core/Src/main.d \ ./Core/Src/nmea_parse.d \ +./Core/Src/spi.d \ ./Core/Src/ssd1306.d \ ./Core/Src/ssd1306_fonts.d \ ./Core/Src/statemachine.d \ @@ -38,17 +57,19 @@ C_DEPS += \ ./Core/Src/stm32l4xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ -./Core/Src/system_stm32l4xx.d +./Core/Src/system_stm32l4xx.d \ +./Core/Src/tim.d \ +./Core/Src/usart.d # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: - -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/nmea_parse.cyclo ./Core/Src/nmea_parse.d ./Core/Src/nmea_parse.o ./Core/Src/nmea_parse.su ./Core/Src/ssd1306.cyclo ./Core/Src/ssd1306.d ./Core/Src/ssd1306.o ./Core/Src/ssd1306.su ./Core/Src/ssd1306_fonts.cyclo ./Core/Src/ssd1306_fonts.d ./Core/Src/ssd1306_fonts.o ./Core/Src/ssd1306_fonts.su ./Core/Src/statemachine.cyclo ./Core/Src/statemachine.d ./Core/Src/statemachine.o ./Core/Src/statemachine.su ./Core/Src/stm32l4xx_hal_msp.cyclo ./Core/Src/stm32l4xx_hal_msp.d ./Core/Src/stm32l4xx_hal_msp.o ./Core/Src/stm32l4xx_hal_msp.su ./Core/Src/stm32l4xx_it.cyclo ./Core/Src/stm32l4xx_it.d ./Core/Src/stm32l4xx_it.o ./Core/Src/stm32l4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32l4xx.cyclo ./Core/Src/system_stm32l4xx.d ./Core/Src/system_stm32l4xx.o ./Core/Src/system_stm32l4xx.su + -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/i2c.cyclo ./Core/Src/i2c.d ./Core/Src/i2c.o ./Core/Src/i2c.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/nmea_parse.cyclo ./Core/Src/nmea_parse.d ./Core/Src/nmea_parse.o ./Core/Src/nmea_parse.su ./Core/Src/spi.cyclo ./Core/Src/spi.d ./Core/Src/spi.o ./Core/Src/spi.su ./Core/Src/ssd1306.cyclo ./Core/Src/ssd1306.d ./Core/Src/ssd1306.o ./Core/Src/ssd1306.su ./Core/Src/ssd1306_fonts.cyclo ./Core/Src/ssd1306_fonts.d ./Core/Src/ssd1306_fonts.o ./Core/Src/ssd1306_fonts.su ./Core/Src/statemachine.cyclo ./Core/Src/statemachine.d ./Core/Src/statemachine.o ./Core/Src/statemachine.su ./Core/Src/stm32l4xx_hal_msp.cyclo ./Core/Src/stm32l4xx_hal_msp.d ./Core/Src/stm32l4xx_hal_msp.o ./Core/Src/stm32l4xx_hal_msp.su ./Core/Src/stm32l4xx_it.cyclo ./Core/Src/stm32l4xx_it.d ./Core/Src/stm32l4xx_it.o ./Core/Src/stm32l4xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32l4xx.cyclo ./Core/Src/system_stm32l4xx.d ./Core/Src/system_stm32l4xx.o ./Core/Src/system_stm32l4xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su .PHONY: clean-Core-2f-Src diff --git a/Software/stm32project/Debug/Core/Src/syscalls.o b/Software/stm32project/Debug/Core/Src/syscalls.o index 76ce5d8..0648380 100644 Binary files a/Software/stm32project/Debug/Core/Src/syscalls.o and b/Software/stm32project/Debug/Core/Src/syscalls.o differ diff --git a/Software/stm32project/Debug/Core/Src/sysmem.o b/Software/stm32project/Debug/Core/Src/sysmem.o index c55ece4..41b89db 100644 Binary files a/Software/stm32project/Debug/Core/Src/sysmem.o and b/Software/stm32project/Debug/Core/Src/sysmem.o differ diff --git a/Software/stm32project/Debug/Core/Src/system_stm32l4xx.d b/Software/stm32project/Debug/Core/Src/system_stm32l4xx.d index 670cb4b..656aefc 100644 --- a/Software/stm32project/Debug/Core/Src/system_stm32l4xx.d +++ b/Software/stm32project/Debug/Core/Src/system_stm32l4xx.d @@ -31,6 +31,8 @@ Core/Src/system_stm32l4xx.o: ../Core/Src/system_stm32l4xx.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -67,6 +69,8 @@ Core/Src/system_stm32l4xx.o: ../Core/Src/system_stm32l4xx.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Core/Src/system_stm32l4xx.o b/Software/stm32project/Debug/Core/Src/system_stm32l4xx.o index 2389f21..74369a6 100644 Binary files a/Software/stm32project/Debug/Core/Src/system_stm32l4xx.o and b/Software/stm32project/Debug/Core/Src/system_stm32l4xx.o differ diff --git a/Software/stm32project/Debug/Core/Src/tim.cyclo b/Software/stm32project/Debug/Core/Src/tim.cyclo new file mode 100644 index 0000000..ea75dd7 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/tim.cyclo @@ -0,0 +1,3 @@ +../Core/Src/tim.c:30:6:MX_TIM2_Init 4 +../Core/Src/tim.c:70:6:HAL_TIM_Base_MspInit 2 +../Core/Src/tim.c:86:6:HAL_TIM_Base_MspDeInit 2 diff --git a/Software/stm32project/Debug/Core/Src/tim.d b/Software/stm32project/Debug/Core/Src/tim.d new file mode 100644 index 0000000..dc20f05 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/tim.d @@ -0,0 +1,79 @@ +Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/tim.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/tim.o b/Software/stm32project/Debug/Core/Src/tim.o new file mode 100644 index 0000000..8a6b0e0 Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/tim.o differ diff --git a/Software/stm32project/Debug/Core/Src/tim.su b/Software/stm32project/Debug/Core/Src/tim.su new file mode 100644 index 0000000..48deab5 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/tim.su @@ -0,0 +1,3 @@ +../Core/Src/tim.c:30:6:MX_TIM2_Init 40 static +../Core/Src/tim.c:70:6:HAL_TIM_Base_MspInit 24 static +../Core/Src/tim.c:86:6:HAL_TIM_Base_MspDeInit 16 static diff --git a/Software/stm32project/Debug/Core/Src/usart.cyclo b/Software/stm32project/Debug/Core/Src/usart.cyclo new file mode 100644 index 0000000..81b3689 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/usart.cyclo @@ -0,0 +1,5 @@ +../Core/Src/usart.c:36:6:MX_LPUART1_UART_Init 2 +../Core/Src/usart.c:66:6:MX_USART1_UART_Init 2 +../Core/Src/usart.c:96:6:HAL_UART_MspInit 6 +../Core/Src/usart.c:192:6:HAL_UART_MspDeInit 3 +../Core/Src/usart.c:239:6:HAL_UART_RxCpltCallback 3 diff --git a/Software/stm32project/Debug/Core/Src/usart.d b/Software/stm32project/Debug/Core/Src/usart.d new file mode 100644 index 0000000..bf45710 --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/usart.d @@ -0,0 +1,79 @@ +Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \ + ../Core/Inc/main.h ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Core/Src/usart.o b/Software/stm32project/Debug/Core/Src/usart.o new file mode 100644 index 0000000..067eb3e Binary files /dev/null and b/Software/stm32project/Debug/Core/Src/usart.o differ diff --git a/Software/stm32project/Debug/Core/Src/usart.su b/Software/stm32project/Debug/Core/Src/usart.su new file mode 100644 index 0000000..f01941a --- /dev/null +++ b/Software/stm32project/Debug/Core/Src/usart.su @@ -0,0 +1,5 @@ +../Core/Src/usart.c:36:6:MX_LPUART1_UART_Init 8 static +../Core/Src/usart.c:66:6:MX_USART1_UART_Init 8 static +../Core/Src/usart.c:96:6:HAL_UART_MspInit 136 static +../Core/Src/usart.c:192:6:HAL_UART_MspDeInit 16 static +../Core/Src/usart.c:239:6:HAL_UART_RxCpltCallback 40 static diff --git a/Software/stm32project/Debug/Core/Startup/startup_stm32l432kcux.o b/Software/stm32project/Debug/Core/Startup/startup_stm32l432kcux.o index 72189dc..332ffa3 100644 Binary files a/Software/stm32project/Debug/Core/Startup/startup_stm32l432kcux.o and b/Software/stm32project/Debug/Core/Startup/startup_stm32l432kcux.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d index a7ba9e4..acdc0c2 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o index 689d3a4..528db24 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d index dcaf82a..67dc914 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o index 8d1c20b..4cdcead 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d index f97879b..28ad610 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o index 0f74ab4..1d56a59 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d index e4dcf62..524016c 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o index 2849817..e28d244 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d index 785e3c6..0c722d1 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o index a304c18..a256dc8 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d index 68850ad..a78d9b4 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o index a372502..4648c04 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d index 06b4e93..e2e20d9 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o index 45612a7..8d795ff 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d index 19135b6..3f68580 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o index 6bd96a8..41294c7 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d index 8e382cc..17488f4 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o index ec6ccac..00fb444 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d index 75fe1d1..1dfeca5 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o index 83a2ba4..1eb8634 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d index 2a7d4d0..a8dca95 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o index 72c8df9..60e5d43 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d index a2ecc7f..1a3f9e9 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o index 7f7bdd6..9bf7e05 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d index bf4b0be..53d2036 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o index dd3d4aa..0f46f7f 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d index a954c6e..b171cd9 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o index 2c0bbbd..d0ea199 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d index d812992..125e5ac 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o index 605e3ba..3d70bb5 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d index 36fdb2b..9002ac0 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o index 67239e6..97d86e6 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d index 51cadd2..c0db161 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o index e11c114..2acbe9b 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d index 303098d..0f581b8 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o index 928cde4..757f25c 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d index 541faa0..8d889cf 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o index ed779ff..a42f197 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.cyclo b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.cyclo new file mode 100644 index 0000000..ef59bdd --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.cyclo @@ -0,0 +1,56 @@ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:314:19:HAL_SPI_Init 8 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:489:19:HAL_SPI_DeInit 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:533:13:HAL_SPI_MspInit 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:549:13:HAL_SPI_MspDeInit 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:821:19:HAL_SPI_Transmit 27 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1011:19:HAL_SPI_Receive 23 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1256:19:HAL_SPI_TransmitReceive 43 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1602:19:HAL_SPI_Transmit_IT 8 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1688:19:HAL_SPI_Receive_IT 10 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1797:19:HAL_SPI_TransmitReceive_IT 14 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1907:19:HAL_SPI_Transmit_DMA 11 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2031:19:HAL_SPI_Receive_DMA 13 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2175:19:HAL_SPI_TransmitReceive_DMA 19 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2365:19:HAL_SPI_Abort 18 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2525:19:HAL_SPI_Abort_IT 19 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2686:19:HAL_SPI_DMAPause 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2706:19:HAL_SPI_DMAResume 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2726:19:HAL_SPI_DMAStop 5 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2766:6:HAL_SPI_IRQHandler 21 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2873:13:HAL_SPI_TxCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2889:13:HAL_SPI_RxCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2905:13:HAL_SPI_TxRxCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2921:13:HAL_SPI_TxHalfCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2937:13:HAL_SPI_RxHalfCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2953:13:HAL_SPI_TxRxHalfCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2969:13:HAL_SPI_ErrorCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2987:13:HAL_SPI_AbortCpltCallback 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3022:22:HAL_SPI_GetState 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3034:10:HAL_SPI_GetError 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3059:13:SPI_DMATransmitCplt 5 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3116:13:SPI_DMAReceiveCplt 6 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3233:13:SPI_DMATransmitReceiveCplt 4 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3333:13:SPI_DMAHalfTransmitCplt 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3351:13:SPI_DMAHalfReceiveCplt 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3369:13:SPI_DMAHalfTransmitReceiveCplt 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3387:13:SPI_DMAError 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3410:13:SPI_DMAAbortOnError 1 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3432:13:SPI_DMATxAbortCallback 6 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3498:13:SPI_DMARxAbortCallback 6 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3563:13:SPI_2linesRxISR_8BIT 5 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3648:13:SPI_2linesTxISR_8BIT 4 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3695:13:SPI_2linesRxISR_16BIT 3 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3751:13:SPI_2linesTxISR_16BIT 3 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3816:13:SPI_RxISR_8BIT 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3872:13:SPI_RxISR_16BIT 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3905:13:SPI_TxISR_8BIT 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3930:13:SPI_TxISR_16BIT 2 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3960:26:SPI_WaitFlagStateUntilTimeout 10 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4029:26:SPI_WaitFifoStateUntilTimeout 12 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4109:26:SPI_EndRxTransaction 9 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4145:26:SPI_EndRxTxTransaction 4 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4177:13:SPI_CloseRxTx_ISR 4 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4254:13:SPI_CloseRx_ISR 3 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4311:13:SPI_CloseTx_ISR 4 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4360:13:SPI_AbortRx_ISR 5 +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4404:13:SPI_AbortTx_ISR 10 diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d new file mode 100644 index 0000000..a45d1cf --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d @@ -0,0 +1,78 @@ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o: \ + ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o new file mode 100644 index 0000000..7420ae9 Binary files /dev/null and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.su b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.su new file mode 100644 index 0000000..467a73c --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.su @@ -0,0 +1,56 @@ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:314:19:HAL_SPI_Init 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:489:19:HAL_SPI_DeInit 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:533:13:HAL_SPI_MspInit 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:549:13:HAL_SPI_MspDeInit 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:821:19:HAL_SPI_Transmit 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1011:19:HAL_SPI_Receive 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1256:19:HAL_SPI_TransmitReceive 48 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1602:19:HAL_SPI_Transmit_IT 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1688:19:HAL_SPI_Receive_IT 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1797:19:HAL_SPI_TransmitReceive_IT 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:1907:19:HAL_SPI_Transmit_DMA 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2031:19:HAL_SPI_Receive_DMA 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2175:19:HAL_SPI_TransmitReceive_DMA 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2365:19:HAL_SPI_Abort 48 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2525:19:HAL_SPI_Abort_IT 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2686:19:HAL_SPI_DMAPause 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2706:19:HAL_SPI_DMAResume 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2726:19:HAL_SPI_DMAStop 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2766:6:HAL_SPI_IRQHandler 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2873:13:HAL_SPI_TxCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2889:13:HAL_SPI_RxCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2905:13:HAL_SPI_TxRxCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2921:13:HAL_SPI_TxHalfCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2937:13:HAL_SPI_RxHalfCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2953:13:HAL_SPI_TxRxHalfCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2969:13:HAL_SPI_ErrorCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:2987:13:HAL_SPI_AbortCpltCallback 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3022:22:HAL_SPI_GetState 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3034:10:HAL_SPI_GetError 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3059:13:SPI_DMATransmitCplt 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3116:13:SPI_DMAReceiveCplt 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3233:13:SPI_DMATransmitReceiveCplt 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3333:13:SPI_DMAHalfTransmitCplt 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3351:13:SPI_DMAHalfReceiveCplt 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3369:13:SPI_DMAHalfTransmitReceiveCplt 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3387:13:SPI_DMAError 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3410:13:SPI_DMAAbortOnError 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3432:13:SPI_DMATxAbortCallback 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3498:13:SPI_DMARxAbortCallback 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3563:13:SPI_2linesRxISR_8BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3648:13:SPI_2linesTxISR_8BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3695:13:SPI_2linesRxISR_16BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3751:13:SPI_2linesTxISR_16BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3816:13:SPI_RxISR_8BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3872:13:SPI_RxISR_16BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3905:13:SPI_TxISR_8BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3930:13:SPI_TxISR_16BIT 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:3960:26:SPI_WaitFlagStateUntilTimeout 40 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4029:26:SPI_WaitFifoStateUntilTimeout 48 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4109:26:SPI_EndRxTransaction 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4145:26:SPI_EndRxTxTransaction 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4177:13:SPI_CloseRxTx_ISR 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4254:13:SPI_CloseRx_ISR 16 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4311:13:SPI_CloseTx_ISR 24 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4360:13:SPI_AbortRx_ISR 32 static +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c:4404:13:SPI_AbortTx_ISR 32 static diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.cyclo b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.cyclo new file mode 100644 index 0000000..6bfdf67 --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.cyclo @@ -0,0 +1 @@ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c:79:19:HAL_SPIEx_FlushRxFifo 3 diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d new file mode 100644 index 0000000..0e062ba --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d @@ -0,0 +1,78 @@ +Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o: \ + ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o new file mode 100644 index 0000000..ae260fb Binary files /dev/null and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.su b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.su new file mode 100644 index 0000000..4069b89 --- /dev/null +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.su @@ -0,0 +1 @@ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c:79:19:HAL_SPIEx_FlushRxFifo 24 static diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d index 116731b..5cc9d5e 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o index bad8144..0f02e2c 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d index 8968c61..da25c48 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o index f8bbfa1..1f3c197 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d index 124fc58..edafcf6 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o index a1dd355..1744449 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d index 52a47c4..3681e3b 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o index 00fad3f..4af3b8f 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d index 019e974..2a16ddd 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d @@ -32,6 +32,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -68,6 +70,8 @@ Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o index 91eb7e6..05f83f2 100644 Binary files a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o and b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o differ diff --git a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk index bd79e0f..aedfc7f 100644 --- a/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk +++ b/Software/stm32project/Debug/Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk @@ -24,6 +24,8 @@ C_SRCS += \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c \ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \ +../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \ ../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c \ @@ -50,6 +52,8 @@ OBJS += \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o \ +./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o \ +./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o \ @@ -76,6 +80,8 @@ C_DEPS += \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d \ +./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d \ +./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d \ ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d \ @@ -85,12 +91,13 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Drivers/STM32L4xx_HAL_Driver/Src/%.o Drivers/STM32L4xx_HAL_Driver/Src/%.su Drivers/STM32L4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32L4xx_HAL_Driver/Src/%.c Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Drivers-2f-STM32L4xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32L4xx_HAL_Driver-2f-Src: - -$(RM) ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.su + -$(RM) ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.su ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.cyclo ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o + -$(RM) ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.su .PHONY: clean-Drivers-2f-STM32L4xx_HAL_Driver-2f-Src diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk index ded5a51..f672966 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk @@ -4,6 +4,24 @@ ################################################################################ # Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c + +OBJS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + +C_DEPS += \ +./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d + # Each subdirectory must supply rules for building sources it contributes +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-CDC-2f-Src + +clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-CDC-2f-Src: + -$(RM) ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.cyclo ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su + +.PHONY: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-CDC-2f-Src diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.cyclo b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.cyclo new file mode 100644 index 0000000..e9038f4 --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.cyclo @@ -0,0 +1,15 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:287:16:USBD_CDC_Init 5 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:388:16:USBD_CDC_DeInit 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:432:16:USBD_CDC_Setup 14 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:536:16:USBD_CDC_DataIn 5 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:577:16:USBD_CDC_DataOut 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:603:16:USBD_CDC_EP0_RxReady 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:629:17:USBD_CDC_GetFSCfgDesc 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:660:17:USBD_CDC_GetHSCfgDesc 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:691:17:USBD_CDC_GetOtherSpeedCfgDesc 4 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:722:10:USBD_CDC_GetDeviceQualifierDescriptor 1 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:735:9:USBD_CDC_RegisterInterface 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:763:9:USBD_CDC_SetTxBuffer 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:786:9:USBD_CDC_SetRxBuffer 2 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:813:9:USBD_CDC_TransmitPacket 3 +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:853:9:USBD_CDC_ReceivePacket 3 diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d new file mode 100644 index 0000000..86baeab --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.d @@ -0,0 +1,95 @@ +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o: \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o new file mode 100644 index 0000000..50da04f Binary files /dev/null and b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o differ diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su new file mode 100644 index 0000000..5cc914d --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.su @@ -0,0 +1,15 @@ +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:287:16:USBD_CDC_Init 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:388:16:USBD_CDC_DeInit 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:432:16:USBD_CDC_Setup 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:536:16:USBD_CDC_DataIn 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:577:16:USBD_CDC_DataOut 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:603:16:USBD_CDC_EP0_RxReady 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:629:17:USBD_CDC_GetFSCfgDesc 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:660:17:USBD_CDC_GetHSCfgDesc 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:691:17:USBD_CDC_GetOtherSpeedCfgDesc 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:722:10:USBD_CDC_GetDeviceQualifierDescriptor 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:735:9:USBD_CDC_RegisterInterface 16 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:763:9:USBD_CDC_SetTxBuffer 32 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:786:9:USBD_CDC_SetRxBuffer 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:813:9:USBD_CDC_TransmitPacket 24 static +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c:853:9:USBD_CDC_ReceivePacket 24 static diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk index b8b1cb0..798189e 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Class-2f-HID-2f-Src diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo deleted file mode 100644 index d8331e4..0000000 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.cyclo +++ /dev/null @@ -1,10 +0,0 @@ -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:279:16:USBD_HID_Init 3 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:326:16:USBD_HID_DeInit 2 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:357:16:USBD_HID_Setup 18 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:489:9:USBD_HID_SendReport 4 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:522:10:USBD_HID_GetPollingInterval 2 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:552:17:USBD_HID_GetFSCfgDesc 2 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:572:17:USBD_HID_GetHSCfgDesc 2 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:592:17:USBD_HID_GetOtherSpeedCfgDesc 2 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:613:16:USBD_HID_DataIn 1 -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:630:17:USBD_HID_GetDeviceQualifierDesc 1 diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d index 54113ea..1154fe7 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.d @@ -36,6 +36,8 @@ Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -81,6 +83,8 @@ Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o index 6e16245..54cc925 100644 Binary files a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o and b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o differ diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su deleted file mode 100644 index a2d7b87..0000000 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.su +++ /dev/null @@ -1,10 +0,0 @@ -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:279:16:USBD_HID_Init 24 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:326:16:USBD_HID_DeInit 16 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:357:16:USBD_HID_Setup 32 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:489:9:USBD_HID_SendReport 32 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:522:10:USBD_HID_GetPollingInterval 24 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:552:17:USBD_HID_GetFSCfgDesc 24 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:572:17:USBD_HID_GetHSCfgDesc 24 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:592:17:USBD_HID_GetOtherSpeedCfgDesc 24 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:613:16:USBD_HID_DataIn 16 static -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c:630:17:USBD_HID_GetDeviceQualifierDesc 16 static diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk index b12bee8..74b5e36 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk @@ -22,7 +22,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.o Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.su Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.cyclo: ../Middlewares/ST/STM32_USB_Device_Library/Core/Src/%.c Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Middlewares-2f-ST-2f-STM32_USB_Device_Library-2f-Core-2f-Src diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d index a0da6c1..6e42dd6 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.d @@ -34,6 +34,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -77,6 +79,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o index 3fb2b56..dcae8f6 100644 Binary files a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o and b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o differ diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d index 058e6cd..5f88472 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.d @@ -35,6 +35,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -79,6 +81,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o index 8e5a03a..c617aab 100644 Binary files a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o and b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o differ diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d index 02e493d..89055b1 100644 --- a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d +++ b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.d @@ -35,6 +35,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -78,6 +80,8 @@ Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o: \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o index da6de00..df6ed89 100644 Binary files a/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o and b/Software/stm32project/Debug/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o differ diff --git a/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.cyclo b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.cyclo new file mode 100644 index 0000000..d34339f --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.cyclo @@ -0,0 +1,31 @@ +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:118:6:SPIF_Delay 1 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:137:6:SPIF_Lock 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:148:6:SPIF_UnLock 1 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:155:6:SPIF_CsPin 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:163:6:SPIF_TransmitReceive 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:205:6:SPIF_Transmit 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:247:6:SPIF_Receive 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:289:6:SPIF_WriteEnable 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:305:6:SPIF_WriteDisable 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:321:9:SPIF_ReadReg1 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:337:9:SPIF_ReadReg2 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:353:9:SPIF_ReadReg3 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:369:6:SPIF_WriteReg1 3 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:399:6:SPIF_WriteReg2 3 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:429:6:SPIF_WriteReg3 3 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:459:6:SPIF_WaitForWriting 3 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:482:6:SPIF_FindChip 23 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:625:6:SPIF_WriteFn 10 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:713:6:SPIF_ReadFn 5 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:790:6:SPIF_Init 8 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:836:6:SPIF_EraseChip 4 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:882:6:SPIF_EraseSector 7 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:954:6:SPIF_EraseBlock 7 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1029:6:SPIF_WriteAddress 5 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1083:6:SPIF_WritePage 1 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1107:6:SPIF_WriteSector 6 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1160:6:SPIF_WriteBlock 6 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1213:6:SPIF_ReadAddress 1 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1236:6:SPIF_ReadPage 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1265:6:SPIF_ReadSector 2 +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1294:6:SPIF_ReadBlock 2 diff --git a/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.d b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.d new file mode 100644 index 0000000..9618989 --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.d @@ -0,0 +1,86 @@ +Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o: \ + ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c \ + ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h \ + ../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h ../Core/Inc/spi.h \ + ../Core/Inc/main.h ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ + ../Core/Inc/nmea_parse.h +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h: +../I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h: +../Core/Inc/spi.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: +../Core/Inc/nmea_parse.h: diff --git a/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o new file mode 100644 index 0000000..e0f6524 Binary files /dev/null and b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o differ diff --git a/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.su b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.su new file mode 100644 index 0000000..eaa81da --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.su @@ -0,0 +1,31 @@ +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:118:6:SPIF_Delay 16 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:137:6:SPIF_Lock 16 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:148:6:SPIF_UnLock 16 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:155:6:SPIF_CsPin 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:163:6:SPIF_TransmitReceive 40 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:205:6:SPIF_Transmit 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:247:6:SPIF_Receive 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:289:6:SPIF_WriteEnable 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:305:6:SPIF_WriteDisable 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:321:9:SPIF_ReadReg1 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:337:9:SPIF_ReadReg2 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:353:9:SPIF_ReadReg3 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:369:6:SPIF_WriteReg1 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:399:6:SPIF_WriteReg2 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:429:6:SPIF_WriteReg3 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:459:6:SPIF_WaitForWriting 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:482:6:SPIF_FindChip 40 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:625:6:SPIF_WriteFn 48 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:713:6:SPIF_ReadFn 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:790:6:SPIF_Init 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:836:6:SPIF_EraseChip 24 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:882:6:SPIF_EraseSector 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:954:6:SPIF_EraseBlock 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1029:6:SPIF_WriteAddress 64 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1083:6:SPIF_WritePage 40 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1107:6:SPIF_WriteSector 56 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1160:6:SPIF_WriteBlock 56 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1213:6:SPIF_ReadAddress 32 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1236:6:SPIF_ReadPage 40 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1265:6:SPIF_ReadSector 40 static +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c:1294:6:SPIF_ReadBlock 40 static diff --git a/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/subdir.mk b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/subdir.mk new file mode 100644 index 0000000..eeb2fac --- /dev/null +++ b/Software/stm32project/Debug/Middlewares/Third_Party/NimaLTD_Driver/SPIF/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c + +OBJS += \ +./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + +C_DEPS += \ +./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/NimaLTD_Driver/SPIF/%.o Middlewares/Third_Party/NimaLTD_Driver/SPIF/%.su Middlewares/Third_Party/NimaLTD_Driver/SPIF/%.cyclo: ../Middlewares/Third_Party/NimaLTD_Driver/SPIF/%.c Middlewares/Third_Party/NimaLTD_Driver/SPIF/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-NimaLTD_Driver-2f-SPIF + +clean-Middlewares-2f-Third_Party-2f-NimaLTD_Driver-2f-SPIF: + -$(RM) ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.cyclo ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-NimaLTD_Driver-2f-SPIF + diff --git a/Software/stm32project/Debug/USB_DEVICE/App/subdir.mk b/Software/stm32project/Debug/USB_DEVICE/App/subdir.mk index 74abf6d..dea1fce 100644 --- a/Software/stm32project/Debug/USB_DEVICE/App/subdir.mk +++ b/Software/stm32project/Debug/USB_DEVICE/App/subdir.mk @@ -6,25 +6,28 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../USB_DEVICE/App/usb_device.c \ +../USB_DEVICE/App/usbd_cdc_if.c \ ../USB_DEVICE/App/usbd_desc.c OBJS += \ ./USB_DEVICE/App/usb_device.o \ +./USB_DEVICE/App/usbd_cdc_if.o \ ./USB_DEVICE/App/usbd_desc.o C_DEPS += \ ./USB_DEVICE/App/usb_device.d \ +./USB_DEVICE/App/usbd_cdc_if.d \ ./USB_DEVICE/App/usbd_desc.d # Each subdirectory must supply rules for building sources it contributes USB_DEVICE/App/%.o USB_DEVICE/App/%.su USB_DEVICE/App/%.cyclo: ../USB_DEVICE/App/%.c USB_DEVICE/App/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-USB_DEVICE-2f-App clean-USB_DEVICE-2f-App: - -$(RM) ./USB_DEVICE/App/usb_device.cyclo ./USB_DEVICE/App/usb_device.d ./USB_DEVICE/App/usb_device.o ./USB_DEVICE/App/usb_device.su ./USB_DEVICE/App/usbd_desc.cyclo ./USB_DEVICE/App/usbd_desc.d ./USB_DEVICE/App/usbd_desc.o ./USB_DEVICE/App/usbd_desc.su + -$(RM) ./USB_DEVICE/App/usb_device.cyclo ./USB_DEVICE/App/usb_device.d ./USB_DEVICE/App/usb_device.o ./USB_DEVICE/App/usb_device.su ./USB_DEVICE/App/usbd_cdc_if.cyclo ./USB_DEVICE/App/usbd_cdc_if.d ./USB_DEVICE/App/usbd_cdc_if.o ./USB_DEVICE/App/usbd_cdc_if.su ./USB_DEVICE/App/usbd_desc.cyclo ./USB_DEVICE/App/usbd_desc.d ./USB_DEVICE/App/usbd_desc.o ./USB_DEVICE/App/usbd_desc.su .PHONY: clean-USB_DEVICE-2f-App diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.cyclo b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.cyclo index f784d56..60b4c2d 100644 --- a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.cyclo +++ b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.cyclo @@ -1 +1 @@ -../USB_DEVICE/App/usb_device.c:64:6:MX_USB_DEVICE_Init 4 +../USB_DEVICE/App/usb_device.c:65:6:MX_USB_DEVICE_Init 5 diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.d b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.d index c72d63e..f0bb52f 100644 --- a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.d +++ b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.d @@ -32,6 +32,8 @@ USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -44,8 +46,9 @@ USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ ../USB_DEVICE/App/usbd_desc.h \ - ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ - ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h + ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../USB_DEVICE/App/usbd_cdc_if.h ../USB_DEVICE/App/usb_device.h: ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: @@ -79,6 +82,8 @@ USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: @@ -92,5 +97,6 @@ USB_DEVICE/App/usb_device.o: ../USB_DEVICE/App/usb_device.c \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: ../USB_DEVICE/App/usbd_desc.h: -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../USB_DEVICE/App/usbd_cdc_if.h: diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.o b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.o index 00d381d..6ea8b5b 100644 Binary files a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.o and b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.o differ diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.su b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.su index ddfa262..1a9f440 100644 --- a/Software/stm32project/Debug/USB_DEVICE/App/usb_device.su +++ b/Software/stm32project/Debug/USB_DEVICE/App/usb_device.su @@ -1 +1 @@ -../USB_DEVICE/App/usb_device.c:64:6:MX_USB_DEVICE_Init 8 static +../USB_DEVICE/App/usb_device.c:65:6:MX_USB_DEVICE_Init 8 static diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.cyclo b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.cyclo new file mode 100644 index 0000000..8cd8925 --- /dev/null +++ b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.cyclo @@ -0,0 +1,6 @@ +../USB_DEVICE/App/usbd_cdc_if.c:152:15:CDC_Init_FS 1 +../USB_DEVICE/App/usbd_cdc_if.c:166:15:CDC_DeInit_FS 1 +../USB_DEVICE/App/usbd_cdc_if.c:180:15:CDC_Control_FS 1 +../USB_DEVICE/App/usbd_cdc_if.c:261:15:CDC_Receive_FS 1 +../USB_DEVICE/App/usbd_cdc_if.c:281:9:CDC_Transmit_FS 2 +../USB_DEVICE/App/usbd_cdc_if.c:307:15:CDC_TransmitCplt_FS 1 diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.d b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.d new file mode 100644 index 0000000..c43db69 --- /dev/null +++ b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.d @@ -0,0 +1,94 @@ +USB_DEVICE/App/usbd_cdc_if.o: ../USB_DEVICE/App/usbd_cdc_if.c \ + ../USB_DEVICE/App/usbd_cdc_if.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + ../USB_DEVICE/Target/usbd_conf.h ../Core/Inc/main.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h \ + ../Core/Inc/stm32l4xx_hal_conf.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +../USB_DEVICE/App/usbd_cdc_if.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +../USB_DEVICE/Target/usbd_conf.h: +../Core/Inc/main.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h: +../Core/Inc/stm32l4xx_hal_conf.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.o b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.o new file mode 100644 index 0000000..c90a999 Binary files /dev/null and b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.o differ diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.su b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.su new file mode 100644 index 0000000..88544bc --- /dev/null +++ b/Software/stm32project/Debug/USB_DEVICE/App/usbd_cdc_if.su @@ -0,0 +1,6 @@ +../USB_DEVICE/App/usbd_cdc_if.c:152:15:CDC_Init_FS 8 static +../USB_DEVICE/App/usbd_cdc_if.c:166:15:CDC_DeInit_FS 4 static +../USB_DEVICE/App/usbd_cdc_if.c:180:15:CDC_Control_FS 16 static +../USB_DEVICE/App/usbd_cdc_if.c:261:15:CDC_Receive_FS 16 static +../USB_DEVICE/App/usbd_cdc_if.c:281:9:CDC_Transmit_FS 24 static +../USB_DEVICE/App/usbd_cdc_if.c:307:15:CDC_TransmitCplt_FS 32 static diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.d b/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.d index f1902e3..9fd02f8 100644 --- a/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.d +++ b/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.d @@ -33,6 +33,8 @@ USB_DEVICE/App/usbd_desc.o: ../USB_DEVICE/App/usbd_desc.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -78,6 +80,8 @@ USB_DEVICE/App/usbd_desc.o: ../USB_DEVICE/App/usbd_desc.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: diff --git a/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.o b/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.o index 2e7c9d9..00e167e 100644 Binary files a/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.o and b/Software/stm32project/Debug/USB_DEVICE/App/usbd_desc.o differ diff --git a/Software/stm32project/Debug/USB_DEVICE/Target/subdir.mk b/Software/stm32project/Debug/USB_DEVICE/Target/subdir.mk index bb472df..f2b91df 100644 --- a/Software/stm32project/Debug/USB_DEVICE/Target/subdir.mk +++ b/Software/stm32project/Debug/USB_DEVICE/Target/subdir.mk @@ -16,7 +16,7 @@ C_DEPS += \ # Each subdirectory must supply rules for building sources it contributes USB_DEVICE/Target/%.o USB_DEVICE/Target/%.su USB_DEVICE/Target/%.cyclo: ../USB_DEVICE/Target/%.c USB_DEVICE/Target/subdir.mk - arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L432xx -c -I../Core/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc -I../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L4xx/Include -I../Drivers/CMSIS/Include -I../USB_DEVICE/App -I../USB_DEVICE/Target -I../Middlewares/ST/STM32_USB_Device_Library/Core/Inc -I../I-CUBE-SPIF -I../Middlewares/Third_Party/NimaLTD_Driver/SPIF -I../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-USB_DEVICE-2f-Target diff --git a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.cyclo b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.cyclo index abf83c4..c3ddef3 100644 --- a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.cyclo +++ b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.cyclo @@ -12,21 +12,21 @@ ../USB_DEVICE/Target/usbd_conf.c:275:6:HAL_PCD_ConnectCallback 1 ../USB_DEVICE/Target/usbd_conf.c:289:6:HAL_PCD_DisconnectCallback 1 ../USB_DEVICE/Target/usbd_conf.c:304:20:USBD_LL_Init 2 -../USB_DEVICE/Target/usbd_conf.c:356:20:USBD_LL_DeInit 5 -../USB_DEVICE/Target/usbd_conf.c:388:20:USBD_LL_Start 5 -../USB_DEVICE/Target/usbd_conf.c:420:20:USBD_LL_Stop 5 -../USB_DEVICE/Target/usbd_conf.c:455:20:USBD_LL_OpenEP 5 -../USB_DEVICE/Target/usbd_conf.c:488:20:USBD_LL_CloseEP 5 -../USB_DEVICE/Target/usbd_conf.c:521:20:USBD_LL_FlushEP 5 -../USB_DEVICE/Target/usbd_conf.c:554:20:USBD_LL_StallEP 5 -../USB_DEVICE/Target/usbd_conf.c:587:20:USBD_LL_ClearStallEP 5 -../USB_DEVICE/Target/usbd_conf.c:620:9:USBD_LL_IsStallEP 2 -../USB_DEVICE/Target/usbd_conf.c:640:20:USBD_LL_SetUSBAddress 5 -../USB_DEVICE/Target/usbd_conf.c:675:20:USBD_LL_Transmit 5 -../USB_DEVICE/Target/usbd_conf.c:710:20:USBD_LL_PrepareReceive 5 -../USB_DEVICE/Target/usbd_conf.c:743:10:USBD_LL_GetRxDataSize 1 -../USB_DEVICE/Target/usbd_conf.c:754:6:HAL_PCDEx_LPM_Callback 5 -../USB_DEVICE/Target/usbd_conf.c:787:6:USBD_LL_Delay 1 -../USB_DEVICE/Target/usbd_conf.c:797:7:USBD_static_malloc 1 -../USB_DEVICE/Target/usbd_conf.c:808:6:USBD_static_free 1 -../USB_DEVICE/Target/usbd_conf.c:819:13:SystemClockConfig_Resume 1 +../USB_DEVICE/Target/usbd_conf.c:358:20:USBD_LL_DeInit 5 +../USB_DEVICE/Target/usbd_conf.c:390:20:USBD_LL_Start 5 +../USB_DEVICE/Target/usbd_conf.c:422:20:USBD_LL_Stop 5 +../USB_DEVICE/Target/usbd_conf.c:457:20:USBD_LL_OpenEP 5 +../USB_DEVICE/Target/usbd_conf.c:490:20:USBD_LL_CloseEP 5 +../USB_DEVICE/Target/usbd_conf.c:523:20:USBD_LL_FlushEP 5 +../USB_DEVICE/Target/usbd_conf.c:556:20:USBD_LL_StallEP 5 +../USB_DEVICE/Target/usbd_conf.c:589:20:USBD_LL_ClearStallEP 5 +../USB_DEVICE/Target/usbd_conf.c:622:9:USBD_LL_IsStallEP 2 +../USB_DEVICE/Target/usbd_conf.c:642:20:USBD_LL_SetUSBAddress 5 +../USB_DEVICE/Target/usbd_conf.c:677:20:USBD_LL_Transmit 5 +../USB_DEVICE/Target/usbd_conf.c:712:20:USBD_LL_PrepareReceive 5 +../USB_DEVICE/Target/usbd_conf.c:745:10:USBD_LL_GetRxDataSize 1 +../USB_DEVICE/Target/usbd_conf.c:756:6:HAL_PCDEx_LPM_Callback 5 +../USB_DEVICE/Target/usbd_conf.c:789:6:USBD_LL_Delay 1 +../USB_DEVICE/Target/usbd_conf.c:799:7:USBD_static_malloc 1 +../USB_DEVICE/Target/usbd_conf.c:810:6:USBD_static_free 1 +../USB_DEVICE/Target/usbd_conf.c:821:13:SystemClockConfig_Resume 1 diff --git a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.d b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.d index 6954ba6..8e61d22 100644 --- a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.d +++ b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.d @@ -31,6 +31,8 @@ USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h \ + ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h \ @@ -42,7 +44,7 @@ USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ - ../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h \ + ../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: ../Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h: @@ -76,6 +78,8 @@ USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h: +../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h: ../Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h: @@ -88,5 +92,5 @@ USB_DEVICE/Target/usbd_conf.o: ../USB_DEVICE/Target/usbd_conf.c \ ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: -../Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h: +../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h: ../Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: diff --git a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.o b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.o index 50db2f5..7251080 100644 Binary files a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.o and b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.o differ diff --git a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.su b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.su index 17dd494..45c7d96 100644 --- a/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.su +++ b/Software/stm32project/Debug/USB_DEVICE/Target/usbd_conf.su @@ -12,21 +12,21 @@ ../USB_DEVICE/Target/usbd_conf.c:275:6:HAL_PCD_ConnectCallback 16 static ../USB_DEVICE/Target/usbd_conf.c:289:6:HAL_PCD_DisconnectCallback 16 static ../USB_DEVICE/Target/usbd_conf.c:304:20:USBD_LL_Init 16 static -../USB_DEVICE/Target/usbd_conf.c:356:20:USBD_LL_DeInit 24 static -../USB_DEVICE/Target/usbd_conf.c:388:20:USBD_LL_Start 24 static -../USB_DEVICE/Target/usbd_conf.c:420:20:USBD_LL_Stop 24 static -../USB_DEVICE/Target/usbd_conf.c:455:20:USBD_LL_OpenEP 24 static -../USB_DEVICE/Target/usbd_conf.c:488:20:USBD_LL_CloseEP 24 static -../USB_DEVICE/Target/usbd_conf.c:521:20:USBD_LL_FlushEP 24 static -../USB_DEVICE/Target/usbd_conf.c:554:20:USBD_LL_StallEP 24 static -../USB_DEVICE/Target/usbd_conf.c:587:20:USBD_LL_ClearStallEP 24 static -../USB_DEVICE/Target/usbd_conf.c:620:9:USBD_LL_IsStallEP 24 static -../USB_DEVICE/Target/usbd_conf.c:640:20:USBD_LL_SetUSBAddress 24 static -../USB_DEVICE/Target/usbd_conf.c:675:20:USBD_LL_Transmit 32 static -../USB_DEVICE/Target/usbd_conf.c:710:20:USBD_LL_PrepareReceive 32 static -../USB_DEVICE/Target/usbd_conf.c:743:10:USBD_LL_GetRxDataSize 16 static -../USB_DEVICE/Target/usbd_conf.c:754:6:HAL_PCDEx_LPM_Callback 16 static -../USB_DEVICE/Target/usbd_conf.c:787:6:USBD_LL_Delay 16 static -../USB_DEVICE/Target/usbd_conf.c:797:7:USBD_static_malloc 16 static -../USB_DEVICE/Target/usbd_conf.c:808:6:USBD_static_free 16 static -../USB_DEVICE/Target/usbd_conf.c:819:13:SystemClockConfig_Resume 8 static +../USB_DEVICE/Target/usbd_conf.c:358:20:USBD_LL_DeInit 24 static +../USB_DEVICE/Target/usbd_conf.c:390:20:USBD_LL_Start 24 static +../USB_DEVICE/Target/usbd_conf.c:422:20:USBD_LL_Stop 24 static +../USB_DEVICE/Target/usbd_conf.c:457:20:USBD_LL_OpenEP 24 static +../USB_DEVICE/Target/usbd_conf.c:490:20:USBD_LL_CloseEP 24 static +../USB_DEVICE/Target/usbd_conf.c:523:20:USBD_LL_FlushEP 24 static +../USB_DEVICE/Target/usbd_conf.c:556:20:USBD_LL_StallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:589:20:USBD_LL_ClearStallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:622:9:USBD_LL_IsStallEP 24 static +../USB_DEVICE/Target/usbd_conf.c:642:20:USBD_LL_SetUSBAddress 24 static +../USB_DEVICE/Target/usbd_conf.c:677:20:USBD_LL_Transmit 32 static +../USB_DEVICE/Target/usbd_conf.c:712:20:USBD_LL_PrepareReceive 32 static +../USB_DEVICE/Target/usbd_conf.c:745:10:USBD_LL_GetRxDataSize 16 static +../USB_DEVICE/Target/usbd_conf.c:756:6:HAL_PCDEx_LPM_Callback 16 static +../USB_DEVICE/Target/usbd_conf.c:789:6:USBD_LL_Delay 16 static +../USB_DEVICE/Target/usbd_conf.c:799:7:USBD_static_malloc 16 static +../USB_DEVICE/Target/usbd_conf.c:810:6:USBD_static_free 16 static +../USB_DEVICE/Target/usbd_conf.c:821:13:SystemClockConfig_Resume 8 static diff --git a/Software/stm32project/Debug/makefile b/Software/stm32project/Debug/makefile index 14b15e9..09d073c 100644 --- a/Software/stm32project/Debug/makefile +++ b/Software/stm32project/Debug/makefile @@ -11,8 +11,9 @@ RM := rm -rf -include sources.mk -include USB_DEVICE/Target/subdir.mk -include USB_DEVICE/App/subdir.mk +-include Middlewares/Third_Party/NimaLTD_Driver/SPIF/subdir.mk -include Middlewares/ST/STM32_USB_Device_Library/Core/Src/subdir.mk --include Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/subdir.mk +-include Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/subdir.mk -include Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk -include Core/Startup/subdir.mk -include Core/Src/subdir.mk @@ -64,8 +65,8 @@ all: main-build main-build: projet\ vf.elf secondary-outputs # Tool invocations -projet\ vf.elf projet\ vf.map: $(OBJS) $(USER_OBJS) C:\Users\mathi\Documents\GitHub\Keyring-GPSTRACKER\Software\stm32project\STM32L432KCUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) - arm-none-eabi-gcc -o "projet vf.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"C:\Users\mathi\Documents\GitHub\Keyring-GPSTRACKER\Software\stm32project\STM32L432KCUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="projet vf.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -u _printf_float -u _scanf_float -Wl,--start-group -lc -lm -Wl,--end-group +projet\ vf.elf projet\ vf.map: $(OBJS) $(USER_OBJS) C:\Users\mathieu\Documents\GitHub\Keyring-GPSTRACKER\Software\stm32project\STM32L432KCUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "projet vf.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"C:\Users\mathieu\Documents\GitHub\Keyring-GPSTRACKER\Software\stm32project\STM32L432KCUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="projet vf.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -u _printf_float -u _scanf_float -Wl,--start-group -lc -lm -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' diff --git a/Software/stm32project/Debug/objects.list b/Software/stm32project/Debug/objects.list index c5ff172..a842510 100644 --- a/Software/stm32project/Debug/objects.list +++ b/Software/stm32project/Debug/objects.list @@ -1,5 +1,10 @@ +"./Core/Src/adc.o" +"./Core/Src/dma.o" +"./Core/Src/gpio.o" +"./Core/Src/i2c.o" "./Core/Src/main.o" "./Core/Src/nmea_parse.o" +"./Core/Src/spi.o" "./Core/Src/ssd1306.o" "./Core/Src/ssd1306_fonts.o" "./Core/Src/statemachine.o" @@ -8,6 +13,8 @@ "./Core/Src/syscalls.o" "./Core/Src/sysmem.o" "./Core/Src/system_stm32l4xx.o" +"./Core/Src/tim.o" +"./Core/Src/usart.o" "./Core/Startup/startup_stm32l432kcux.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o" @@ -28,15 +35,19 @@ "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o" +"./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o" +"./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o" "./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o" -"./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o" +"./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o" "./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o" "./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o" "./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o" +"./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o" "./USB_DEVICE/App/usb_device.o" +"./USB_DEVICE/App/usbd_cdc_if.o" "./USB_DEVICE/App/usbd_desc.o" "./USB_DEVICE/Target/usbd_conf.o" diff --git a/Software/stm32project/Debug/projet vf.elf b/Software/stm32project/Debug/projet vf.elf index 5698339..6fed663 100644 Binary files a/Software/stm32project/Debug/projet vf.elf and b/Software/stm32project/Debug/projet vf.elf differ diff --git a/Software/stm32project/Debug/projet vf.list b/Software/stm32project/Debug/projet vf.list index e48aacb..514b5f7 100644 --- a/Software/stm32project/Debug/projet vf.list +++ b/Software/stm32project/Debug/projet vf.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000018c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00016744 08000190 08000190 00010190 2**4 + 1 .text 00018bf4 08000190 08000190 00010190 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000024b0 080168d8 080168d8 000268d8 2**3 + 2 .rodata 000024d8 08018d88 08018d88 00028d88 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08018d88 08018d88 00030314 2**0 + 3 .ARM.extab 00000000 0801b260 0801b260 000302f4 2**0 CONTENTS - 4 .ARM 00000008 08018d88 08018d88 00028d88 2**2 + 4 .ARM 00000008 0801b260 0801b260 0002b260 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08018d90 08018d90 00030314 2**0 + 5 .preinit_array 00000000 0801b268 0801b268 000302f4 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08018d90 08018d90 00028d90 2**2 + 6 .init_array 00000004 0801b268 0801b268 0002b268 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08018d94 08018d94 00028d94 2**2 + 7 .fini_array 00000004 0801b26c 0801b26c 0002b26c 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 00000314 20000000 08018d98 00030000 2**2 + 8 .data 000002f4 20000000 0801b270 00030000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 000012c0 20000318 080190ac 00030318 2**3 + 9 .bss 00002098 200002f8 0801b564 000302f8 2**3 ALLOC - 10 ._user_heap_stack 00000600 200015d8 080190ac 000315d8 2**0 + 10 ._user_heap_stack 00000600 20002390 0801b564 00032390 2**0 ALLOC - 11 .ARM.attributes 00000030 00000000 00000000 00030314 2**0 + 11 .ARM.attributes 00000030 00000000 00000000 000302f4 2**0 CONTENTS, READONLY - 12 .comment 00000043 00000000 00000000 00030344 2**0 + 12 .comment 00000043 00000000 00000000 00030324 2**0 CONTENTS, READONLY - 13 .debug_info 00024753 00000000 00000000 00030387 2**0 + 13 .debug_info 0002b520 00000000 00000000 00030367 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_abbrev 00004e93 00000000 00000000 00054ada 2**0 + 14 .debug_abbrev 00006168 00000000 00000000 0005b887 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_aranges 00001e60 00000000 00000000 00059970 2**3 + 15 .debug_aranges 000022a8 00000000 00000000 000619f0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_rnglists 00001777 00000000 00000000 0005b7d0 2**0 + 16 .debug_rnglists 00001aac 00000000 00000000 00063c98 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_macro 00027bc2 00000000 00000000 0005cf47 2**0 + 17 .debug_macro 00029f9c 00000000 00000000 00065744 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_line 0002734b 00000000 00000000 00084b09 2**0 + 18 .debug_line 0002fa85 00000000 00000000 0008f6e0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .debug_str 000e5170 00000000 00000000 000abe54 2**0 + 19 .debug_str 000e89c3 00000000 00000000 000bf165 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 20 .debug_frame 00009a94 00000000 00000000 00190fc4 2**2 + 20 .debug_frame 0000aafc 00000000 00000000 001a7b28 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000077 00000000 00000000 0019aa58 2**0 + 21 .debug_line_str 00000078 00000000 00000000 001b2624 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -62,9 +62,9 @@ Disassembly of section .text: 80001a2: 2301 movs r3, #1 80001a4: 7023 strb r3, [r4, #0] 80001a6: bd10 pop {r4, pc} - 80001a8: 20000318 .word 0x20000318 + 80001a8: 200002f8 .word 0x200002f8 80001ac: 00000000 .word 0x00000000 - 80001b0: 080168bc .word 0x080168bc + 80001b0: 08018d6c .word 0x08018d6c 080001b4 : 80001b4: b508 push {r3, lr} @@ -75,8 +75,8 @@ Disassembly of section .text: 80001be: f3af 8000 nop.w 80001c2: bd08 pop {r3, pc} 80001c4: 00000000 .word 0x00000000 - 80001c8: 2000031c .word 0x2000031c - 80001cc: 080168bc .word 0x080168bc + 80001c8: 200002fc .word 0x200002fc + 80001cc: 08018d6c .word 0x08018d6c 080001d0 : 80001d0: f001 01ff and.w r1, r1, #255 ; 0xff @@ -1323,49234 +1323,54925 @@ Disassembly of section .text: 8000fec: 4770 bx lr 8000fee: bf00 nop -08000ff0 : -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ +08000ff0 : +ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; - -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)//lors d'un appuie sur un bouton, le systeme s'interrompt afin d'arriver dans cette fonction redefinie avec en parametre d'entre , le bouton sur lequel l'on a appuiyé +/* ADC1 init function */ +void MX_ADC1_Init(void) { - 8000ff0: b480 push {r7} - 8000ff2: b083 sub sp, #12 + 8000ff0: b580 push {r7, lr} + 8000ff2: b086 sub sp, #24 8000ff4: af00 add r7, sp, #0 - 8000ff6: 4603 mov r3, r0 - 8000ff8: 80fb strh r3, [r7, #6] - if(GPIO_Pin==GPIO_PIN_14){ - 8000ffa: 88fb ldrh r3, [r7, #6] - 8000ffc: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 8001000: d104 bne.n 800100c -// ssd1306_SetCursor(33, 44); -// ssd1306_WriteString("btna", Font_6x8, White); -// ssd1306_UpdateScreen(); - BTN_A++;//sert à reconnaitre lorsque le bouto na est appuyer, cette variable est mise à 1 par un e interruption. - 8001002: 4b0a ldr r3, [pc, #40] ; (800102c ) - 8001004: 681b ldr r3, [r3, #0] - 8001006: 3301 adds r3, #1 - 8001008: 4a08 ldr r2, [pc, #32] ; (800102c ) - 800100a: 6013 str r3, [r2, #0] - - - } - if(GPIO_Pin==GPIO_PIN_15){ - 800100c: 88fb ldrh r3, [r7, #6] - 800100e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8001012: d104 bne.n 800101e - //ssd1306_SetCursor(33, 44); - //ssd1306_WriteString("btnb", Font_6x8, White); - //ssd1306_UpdateScreen(); - BTN_B++;//de meme pour le bouton b - 8001014: 4b06 ldr r3, [pc, #24] ; (8001030 ) - 8001016: 681b ldr r3, [r3, #0] - 8001018: 3301 adds r3, #1 - 800101a: 4a05 ldr r2, [pc, #20] ; (8001030 ) - 800101c: 6013 str r3, [r2, #0] - - } -} - 800101e: bf00 nop - 8001020: 370c adds r7, #12 - 8001022: 46bd mov sp, r7 - 8001024: f85d 7b04 ldr.w r7, [sp], #4 - 8001028: 4770 bx lr - 800102a: bf00 nop - 800102c: 20000820 .word 0x20000820 - 8001030: 20000824 .word 0x20000824 - -08001034 : - - void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ - 8001034: b5f0 push {r4, r5, r6, r7, lr} - 8001036: b085 sub sp, #20 - 8001038: af00 add r7, sp, #0 - 800103a: 6078 str r0, [r7, #4] - oldPos = newPos; //keep track of the last position in the buffer - 800103c: 4b2e ldr r3, [pc, #184] ; (80010f8 ) - 800103e: 881a ldrh r2, [r3, #0] - 8001040: 4b2e ldr r3, [pc, #184] ; (80010fc ) - 8001042: 801a strh r2, [r3, #0] - if(oldPos + 64 > DataBuffer_SIZE){ //if the buffer is full, parse it, then reset the buffer - 8001044: 4b2d ldr r3, [pc, #180] ; (80010fc ) - 8001046: 881b ldrh r3, [r3, #0] - 8001048: f5b3 7fe0 cmp.w r3, #448 ; 0x1c0 - 800104c: d922 bls.n 8001094 - - uint16_t datatocopy = DataBuffer_SIZE-oldPos; // find out how much space is left in the main buffer - 800104e: 4b2b ldr r3, [pc, #172] ; (80010fc ) - 8001050: 881b ldrh r3, [r3, #0] - 8001052: f5c3 7300 rsb r3, r3, #512 ; 0x200 - 8001056: 81fb strh r3, [r7, #14] - memcpy ((uint8_t *)DataBuffer+oldPos, RxBuffer, datatocopy); // copy data in that remaining space - 8001058: 4b28 ldr r3, [pc, #160] ; (80010fc ) - 800105a: 881b ldrh r3, [r3, #0] - 800105c: 461a mov r2, r3 - 800105e: 4b28 ldr r3, [pc, #160] ; (8001100 ) - 8001060: 4413 add r3, r2 - 8001062: 89fa ldrh r2, [r7, #14] - 8001064: 4927 ldr r1, [pc, #156] ; (8001104 ) - 8001066: 4618 mov r0, r3 - 8001068: f011 fe13 bl 8012c92 - - oldPos = 0; // point to the start of the buffer - 800106c: 4b23 ldr r3, [pc, #140] ; (80010fc ) - 800106e: 2200 movs r2, #0 - 8001070: 801a strh r2, [r3, #0] - memcpy ((uint8_t *)DataBuffer, (uint8_t *)RxBuffer+datatocopy, (64-datatocopy)); // copy the remaining data - 8001072: 89fb ldrh r3, [r7, #14] - 8001074: 4a23 ldr r2, [pc, #140] ; (8001104 ) - 8001076: 1899 adds r1, r3, r2 - 8001078: 89fb ldrh r3, [r7, #14] - 800107a: f1c3 0340 rsb r3, r3, #64 ; 0x40 - 800107e: 461a mov r2, r3 - 8001080: 481f ldr r0, [pc, #124] ; (8001100 ) - 8001082: f011 fe06 bl 8012c92 - newPos = (64-datatocopy); // update the position - 8001086: 89fb ldrh r3, [r7, #14] - 8001088: f1c3 0340 rsb r3, r3, #64 ; 0x40 - 800108c: b29a uxth r2, r3 - 800108e: 4b1a ldr r3, [pc, #104] ; (80010f8 ) - 8001090: 801a strh r2, [r3, #0] - 8001092: e01b b.n 80010cc - } - else{ - memcpy((uint8_t *)DataBuffer+oldPos, RxBuffer, 64); //copy received data to the buffer - 8001094: 4b19 ldr r3, [pc, #100] ; (80010fc ) - 8001096: 881b ldrh r3, [r3, #0] - 8001098: 461a mov r2, r3 - 800109a: 4b19 ldr r3, [pc, #100] ; (8001100 ) - 800109c: 4413 add r3, r2 - 800109e: 4a19 ldr r2, [pc, #100] ; (8001104 ) - 80010a0: 4614 mov r4, r2 - 80010a2: 469c mov ip, r3 - 80010a4: f104 0e40 add.w lr, r4, #64 ; 0x40 - 80010a8: 4665 mov r5, ip - 80010aa: 4626 mov r6, r4 - 80010ac: ce0f ldmia r6!, {r0, r1, r2, r3} - 80010ae: 6028 str r0, [r5, #0] - 80010b0: 6069 str r1, [r5, #4] - 80010b2: 60aa str r2, [r5, #8] - 80010b4: 60eb str r3, [r5, #12] - 80010b6: 3410 adds r4, #16 - 80010b8: f10c 0c10 add.w ip, ip, #16 - 80010bc: 4574 cmp r4, lr - 80010be: d1f3 bne.n 80010a8 - newPos = 64+oldPos; //update buffer position - 80010c0: 4b0e ldr r3, [pc, #56] ; (80010fc ) - 80010c2: 881b ldrh r3, [r3, #0] - 80010c4: 3340 adds r3, #64 ; 0x40 - 80010c6: b29a uxth r2, r3 - 80010c8: 4b0b ldr r3, [pc, #44] ; (80010f8 ) - 80010ca: 801a strh r2, [r3, #0] - - } - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//on recoit par dma à nouveau 64 caractères - 80010cc: 2240 movs r2, #64 ; 0x40 - 80010ce: 490d ldr r1, [pc, #52] ; (8001104 ) - 80010d0: 480d ldr r0, [pc, #52] ; (8001108 ) - 80010d2: f009 fcd3 bl 800aa7c - __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT);//on desactive l'interruption afin de ne pas être interrompu tout le temps - 80010d6: 4b0d ldr r3, [pc, #52] ; (800110c ) - 80010d8: 681b ldr r3, [r3, #0] - 80010da: 681a ldr r2, [r3, #0] - 80010dc: 4b0b ldr r3, [pc, #44] ; (800110c ) - 80010de: 681b ldr r3, [r3, #0] - 80010e0: f022 0204 bic.w r2, r2, #4 - 80010e4: 601a str r2, [r3, #0] - - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//l'appel de cette fonction réactive l'intérruption. - 80010e6: 2240 movs r2, #64 ; 0x40 - 80010e8: 4906 ldr r1, [pc, #24] ; (8001104 ) - 80010ea: 4807 ldr r0, [pc, #28] ; (8001108 ) - 80010ec: f009 fcc6 bl 800aa7c -} - 80010f0: bf00 nop - 80010f2: 3714 adds r7, #20 - 80010f4: 46bd mov sp, r7 - 80010f6: bdf0 pop {r4, r5, r6, r7, pc} - 80010f8: 2000059e .word 0x2000059e - 80010fc: 2000059c .word 0x2000059c - 8001100: 200005e0 .word 0x200005e0 - 8001104: 200005a0 .word 0x200005a0 - 8001108: 20000434 .word 0x20000434 - 800110c: 200004bc .word 0x200004bc - -08001110 : - -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){ - 8001110: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} - 8001114: b082 sub sp, #8 - 8001116: af00 add r7, sp, #0 - 8001118: 6078 str r0, [r7, #4] - - if(hadc->Instance==ADC1){ - 800111a: 687b ldr r3, [r7, #4] - 800111c: 681b ldr r3, [r3, #0] - 800111e: 4a3c ldr r2, [pc, #240] ; (8001210 ) - 8001120: 4293 cmp r3, r2 - 8001122: d166 bne.n 80011f2 - vrefint=(float) ((4095.0*1.212)/rawdata[0]); - 8001124: 4b3b ldr r3, [pc, #236] ; (8001214 ) - 8001126: 881b ldrh r3, [r3, #0] - 8001128: 4618 mov r0, r3 - 800112a: f7ff f9fb bl 8000524 <__aeabi_i2d> - 800112e: 4602 mov r2, r0 - 8001130: 460b mov r3, r1 - 8001132: a135 add r1, pc, #212 ; (adr r1, 8001208 ) - 8001134: e9d1 0100 ldrd r0, r1, [r1] - 8001138: f7ff fb88 bl 800084c <__aeabi_ddiv> - 800113c: 4602 mov r2, r0 - 800113e: 460b mov r3, r1 - 8001140: 4610 mov r0, r2 - 8001142: 4619 mov r1, r3 - 8001144: f7ff fd50 bl 8000be8 <__aeabi_d2f> - 8001148: 4603 mov r3, r0 - 800114a: 4a33 ldr r2, [pc, #204] ; (8001218 ) - 800114c: 6013 str r3, [r2, #0] -// vtemp=(float) ((vrefint*rawdata[1])/4095.0); - temp=(float) (((100.0)/(tscal2-tscal1))*(rawdata[1]*(vrefint/3.0)-tscal1))+30.0; - 800114e: 4b33 ldr r3, [pc, #204] ; (800121c ) - 8001150: ed93 7a00 vldr s14, [r3] - 8001154: 4b32 ldr r3, [pc, #200] ; (8001220 ) - 8001156: edd3 7a00 vldr s15, [r3] - 800115a: ee77 7a67 vsub.f32 s15, s14, s15 - 800115e: ee17 0a90 vmov r0, s15 - 8001162: f7ff f9f1 bl 8000548 <__aeabi_f2d> - 8001166: 4602 mov r2, r0 - 8001168: 460b mov r3, r1 - 800116a: f04f 0000 mov.w r0, #0 - 800116e: 492d ldr r1, [pc, #180] ; (8001224 ) - 8001170: f7ff fb6c bl 800084c <__aeabi_ddiv> - 8001174: 4602 mov r2, r0 - 8001176: 460b mov r3, r1 - 8001178: 4690 mov r8, r2 - 800117a: 4699 mov r9, r3 - 800117c: 4b25 ldr r3, [pc, #148] ; (8001214 ) - 800117e: 885b ldrh r3, [r3, #2] - 8001180: 4618 mov r0, r3 - 8001182: f7ff f9cf bl 8000524 <__aeabi_i2d> - 8001186: 4604 mov r4, r0 - 8001188: 460d mov r5, r1 - 800118a: 4b23 ldr r3, [pc, #140] ; (8001218 ) - 800118c: 681b ldr r3, [r3, #0] - 800118e: 4618 mov r0, r3 - 8001190: f7ff f9da bl 8000548 <__aeabi_f2d> - 8001194: f04f 0200 mov.w r2, #0 - 8001198: 4b23 ldr r3, [pc, #140] ; (8001228 ) - 800119a: f7ff fb57 bl 800084c <__aeabi_ddiv> - 800119e: 4602 mov r2, r0 - 80011a0: 460b mov r3, r1 - 80011a2: 4620 mov r0, r4 - 80011a4: 4629 mov r1, r5 - 80011a6: f7ff fa27 bl 80005f8 <__aeabi_dmul> - 80011aa: 4602 mov r2, r0 - 80011ac: 460b mov r3, r1 - 80011ae: 4614 mov r4, r2 - 80011b0: 461d mov r5, r3 - 80011b2: 4b1b ldr r3, [pc, #108] ; (8001220 ) - 80011b4: 681b ldr r3, [r3, #0] - 80011b6: 4618 mov r0, r3 - 80011b8: f7ff f9c6 bl 8000548 <__aeabi_f2d> - 80011bc: 4602 mov r2, r0 - 80011be: 460b mov r3, r1 - 80011c0: 4620 mov r0, r4 - 80011c2: 4629 mov r1, r5 - 80011c4: f7ff f860 bl 8000288 <__aeabi_dsub> - 80011c8: 4602 mov r2, r0 - 80011ca: 460b mov r3, r1 - 80011cc: 4640 mov r0, r8 - 80011ce: 4649 mov r1, r9 - 80011d0: f7ff fa12 bl 80005f8 <__aeabi_dmul> - 80011d4: 4602 mov r2, r0 - 80011d6: 460b mov r3, r1 - 80011d8: 4610 mov r0, r2 - 80011da: 4619 mov r1, r3 - 80011dc: f7ff fd04 bl 8000be8 <__aeabi_d2f> - 80011e0: ee07 0a10 vmov s14, r0 - 80011e4: eef3 7a0e vmov.f32 s15, #62 ; 0x41f00000 30.0 - 80011e8: ee77 7a27 vadd.f32 s15, s14, s15 - 80011ec: 4b0f ldr r3, [pc, #60] ; (800122c ) - 80011ee: edc3 7a00 vstr s15, [r3] - - } - HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 2); - 80011f2: 2202 movs r2, #2 - 80011f4: 4907 ldr r1, [pc, #28] ; (8001214 ) - 80011f6: 480e ldr r0, [pc, #56] ; (8001230 ) - 80011f8: f003 fd2c bl 8004c54 - - - -} - 80011fc: bf00 nop - 80011fe: 3708 adds r7, #8 - 8001200: 46bd mov sp, r7 - 8001202: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} - 8001206: bf00 nop - 8001208: d70a3d70 .word 0xd70a3d70 - 800120c: 40b36323 .word 0x40b36323 - 8001210: 50040000 .word 0x50040000 - 8001214: 20000830 .word 0x20000830 - 8001218: 20000838 .word 0x20000838 - 800121c: 20000000 .word 0x20000000 - 8001220: 20000004 .word 0x20000004 - 8001224: 40590000 .word 0x40590000 - 8001228: 40080000 .word 0x40080000 - 800122c: 20000834 .word 0x20000834 - 8001230: 20000334 .word 0x20000334 - -08001234
: -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - 8001234: b580 push {r7, lr} - 8001236: b082 sub sp, #8 - 8001238: af02 add r7, sp, #8 - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - 800123a: f003 f956 bl 80044ea - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - 800123e: f000 f859 bl 80012f4 - -/* Configure the peripherals common clocks */ - PeriphCommonClock_Config(); - 8001242: f000 f8aa bl 800139a - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - 8001246: f000 fa75 bl 8001734 - MX_DMA_Init(); - 800124a: f000 fa41 bl 80016d0 - MX_I2C3_Init(); - 800124e: f000 f949 bl 80014e4 - MX_LPUART1_UART_Init(); - 8001252: f000 f98b bl 800156c - MX_ADC1_Init(); - 8001256: f000 f8cf bl 80013f8 - MX_TIM2_Init(); - 800125a: f000 f9b3 bl 80015c4 - MX_TIM7_Init(); - 800125e: f000 f9ff bl 8001660 - MX_USB_DEVICE_Init(); - 8001262: f00e ffc5 bl 80101f0 - /* USER CODE BEGIN 2 */ - - - - ssd1306_Init(); - 8001266: f000 fecb bl 8002000 - - HAL_Delay(100); - 800126a: 2064 movs r0, #100 ; 0x64 - 800126c: f003 f9b2 bl 80045d4 - ssd1306_Fill(Black); - 8001270: 2000 movs r0, #0 - 8001272: f000 ff2f bl 80020d4 - - ssd1306_DrawBitmap(32, 32, startimg, 64, 64, White); - 8001276: 2301 movs r3, #1 - 8001278: 9301 str r3, [sp, #4] - 800127a: 2340 movs r3, #64 ; 0x40 - 800127c: 9300 str r3, [sp, #0] - 800127e: 2340 movs r3, #64 ; 0x40 - 8001280: 4a15 ldr r2, [pc, #84] ; (80012d8 ) - 8001282: 2120 movs r1, #32 - 8001284: 2020 movs r0, #32 - 8001286: f001 f9f7 bl 8002678 - ssd1306_UpdateScreen(); - 800128a: f000 ff3b bl 8002104 - - HAL_GPIO_WritePin(GPIOA,GPIO_PIN_1,GPIO_PIN_SET); - 800128e: 2201 movs r2, #1 - 8001290: 2102 movs r1, #2 - 8001292: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 8001296: f005 faed bl 8006874 - HAL_Delay(1000); - 800129a: f44f 707a mov.w r0, #1000 ; 0x3e8 - 800129e: f003 f999 bl 80045d4 - - HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 2); - 80012a2: 2202 movs r2, #2 - 80012a4: 490d ldr r1, [pc, #52] ; (80012dc ) - 80012a6: 480e ldr r0, [pc, #56] ; (80012e0 ) - 80012a8: f003 fcd4 bl 8004c54 - HAL_TIM_Base_Start(&htim2); - 80012ac: 480d ldr r0, [pc, #52] ; (80012e4 ) - 80012ae: f008 ff2f bl 800a110 - HAL_TIM_Base_Start(&htim7); - 80012b2: 480d ldr r0, [pc, #52] ; (80012e8 ) - 80012b4: f008 ff2c bl 800a110 - - HAL_UART_Abort(&hlpuart1); - 80012b8: 480c ldr r0, [pc, #48] ; (80012ec ) - 80012ba: f009 fc2b bl 800ab14 - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//lancement du dma pour le gps - 80012be: 2240 movs r2, #64 ; 0x40 - 80012c0: 490b ldr r1, [pc, #44] ; (80012f0 ) - 80012c2: 480a ldr r0, [pc, #40] ; (80012ec ) - 80012c4: f009 fbda bl 800aa7c - - ssd1306_Fill(Black); - 80012c8: 2000 movs r0, #0 - 80012ca: f000 ff03 bl 80020d4 - - /* USER CODE BEGIN 3 */ - - - - statemachine(); - 80012ce: f001 fa5f bl 8002790 - ssd1306_UpdateScreen(); - 80012d2: f000 ff17 bl 8002104 - statemachine(); - 80012d6: e7fa b.n 80012ce - 80012d8: 08016b14 .word 0x08016b14 - 80012dc: 20000830 .word 0x20000830 - 80012e0: 20000334 .word 0x20000334 - 80012e4: 20000504 .word 0x20000504 - 80012e8: 20000550 .word 0x20000550 - 80012ec: 20000434 .word 0x20000434 - 80012f0: 200005a0 .word 0x200005a0 - -080012f4 : -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - 80012f4: b580 push {r7, lr} - 80012f6: b096 sub sp, #88 ; 0x58 - 80012f8: af00 add r7, sp, #0 - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 80012fa: f107 0314 add.w r3, r7, #20 - 80012fe: 2244 movs r2, #68 ; 0x44 - 8001300: 2100 movs r1, #0 - 8001302: 4618 mov r0, r3 - 8001304: f011 fba9 bl 8012a5a - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8001308: 463b mov r3, r7 - 800130a: 2200 movs r2, #0 - 800130c: 601a str r2, [r3, #0] - 800130e: 605a str r2, [r3, #4] - 8001310: 609a str r2, [r3, #8] - 8001312: 60da str r2, [r3, #12] - 8001314: 611a str r2, [r3, #16] - - /** Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - 8001316: f44f 7000 mov.w r0, #512 ; 0x200 - 800131a: f007 fd1b bl 8008d54 - 800131e: 4603 mov r3, r0 - 8001320: 2b00 cmp r3, #0 - 8001322: d001 beq.n 8001328 - { - Error_Handler(); - 8001324: f000 fa68 bl 80017f8 - } - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - 8001328: 2310 movs r3, #16 - 800132a: 617b str r3, [r7, #20] - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - 800132c: 2301 movs r3, #1 - 800132e: 62fb str r3, [r7, #44] ; 0x2c - RCC_OscInitStruct.MSICalibrationValue = 0; - 8001330: 2300 movs r3, #0 - 8001332: 633b str r3, [r7, #48] ; 0x30 - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; - 8001334: 2360 movs r3, #96 ; 0x60 - 8001336: 637b str r3, [r7, #52] ; 0x34 - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 8001338: 2302 movs r3, #2 - 800133a: 63fb str r3, [r7, #60] ; 0x3c - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - 800133c: 2301 movs r3, #1 - 800133e: 643b str r3, [r7, #64] ; 0x40 - RCC_OscInitStruct.PLL.PLLM = 1; - 8001340: 2301 movs r3, #1 - 8001342: 647b str r3, [r7, #68] ; 0x44 - RCC_OscInitStruct.PLL.PLLN = 20; - 8001344: 2314 movs r3, #20 - 8001346: 64bb str r3, [r7, #72] ; 0x48 - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; - 8001348: 2307 movs r3, #7 - 800134a: 64fb str r3, [r7, #76] ; 0x4c - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - 800134c: 2302 movs r3, #2 - 800134e: 653b str r3, [r7, #80] ; 0x50 - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - 8001350: 2302 movs r3, #2 - 8001352: 657b str r3, [r7, #84] ; 0x54 - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8001354: f107 0314 add.w r3, r7, #20 - 8001358: 4618 mov r0, r3 - 800135a: f007 fd61 bl 8008e20 - 800135e: 4603 mov r3, r0 - 8001360: 2b00 cmp r3, #0 - 8001362: d001 beq.n 8001368 - { - Error_Handler(); - 8001364: f000 fa48 bl 80017f8 - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8001368: 230f movs r3, #15 - 800136a: 603b str r3, [r7, #0] - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 800136c: 2303 movs r3, #3 - 800136e: 607b str r3, [r7, #4] - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 8001370: 2300 movs r3, #0 - 8001372: 60bb str r3, [r7, #8] - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - 8001374: f44f 63a0 mov.w r3, #1280 ; 0x500 - 8001378: 60fb str r3, [r7, #12] - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 800137a: 2300 movs r3, #0 - 800137c: 613b str r3, [r7, #16] - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - 800137e: 463b mov r3, r7 - 8001380: 2102 movs r1, #2 - 8001382: 4618 mov r0, r3 - 8001384: f008 f960 bl 8009648 - 8001388: 4603 mov r3, r0 - 800138a: 2b00 cmp r3, #0 - 800138c: d001 beq.n 8001392 - { - Error_Handler(); - 800138e: f000 fa33 bl 80017f8 - } -} - 8001392: bf00 nop - 8001394: 3758 adds r7, #88 ; 0x58 - 8001396: 46bd mov sp, r7 - 8001398: bd80 pop {r7, pc} - -0800139a : -/** - * @brief Peripherals Common Clock Configuration - * @retval None - */ -void PeriphCommonClock_Config(void) -{ - 800139a: b580 push {r7, lr} - 800139c: b096 sub sp, #88 ; 0x58 - 800139e: af00 add r7, sp, #0 - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 80013a0: 1d3b adds r3, r7, #4 - 80013a2: 2254 movs r2, #84 ; 0x54 - 80013a4: 2100 movs r1, #0 - 80013a6: 4618 mov r0, r3 - 80013a8: f011 fb57 bl 8012a5a - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC; - 80013ac: f44f 43c0 mov.w r3, #24576 ; 0x6000 - 80013b0: 607b str r3, [r7, #4] - PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; - 80013b2: f04f 5380 mov.w r3, #268435456 ; 0x10000000 - 80013b6: 64fb str r3, [r7, #76] ; 0x4c - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - 80013b8: f04f 6380 mov.w r3, #67108864 ; 0x4000000 - 80013bc: 647b str r3, [r7, #68] ; 0x44 - PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; - 80013be: 2301 movs r3, #1 - 80013c0: 60bb str r3, [r7, #8] - PeriphClkInit.PLLSAI1.PLLSAI1M = 1; - 80013c2: 2301 movs r3, #1 - 80013c4: 60fb str r3, [r7, #12] - PeriphClkInit.PLLSAI1.PLLSAI1N = 24; - 80013c6: 2318 movs r3, #24 - 80013c8: 613b str r3, [r7, #16] - PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; - 80013ca: 2307 movs r3, #7 - 80013cc: 617b str r3, [r7, #20] - PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; - 80013ce: 2302 movs r3, #2 - 80013d0: 61bb str r3, [r7, #24] - PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; - 80013d2: 2302 movs r3, #2 - 80013d4: 61fb str r3, [r7, #28] - PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK; - 80013d6: f04f 7388 mov.w r3, #17825792 ; 0x1100000 - 80013da: 623b str r3, [r7, #32] - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 80013dc: 1d3b adds r3, r7, #4 - 80013de: 4618 mov r0, r3 - 80013e0: f008 fb56 bl 8009a90 - 80013e4: 4603 mov r3, r0 - 80013e6: 2b00 cmp r3, #0 - 80013e8: d001 beq.n 80013ee - { - Error_Handler(); - 80013ea: f000 fa05 bl 80017f8 - } -} - 80013ee: bf00 nop - 80013f0: 3758 adds r7, #88 ; 0x58 - 80013f2: 46bd mov sp, r7 - 80013f4: bd80 pop {r7, pc} - ... - -080013f8 : - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) -{ - 80013f8: b580 push {r7, lr} - 80013fa: b086 sub sp, #24 - 80013fc: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; - 80013fe: 463b mov r3, r7 - 8001400: 2200 movs r2, #0 - 8001402: 601a str r2, [r3, #0] - 8001404: 605a str r2, [r3, #4] - 8001406: 609a str r2, [r3, #8] - 8001408: 60da str r2, [r3, #12] - 800140a: 611a str r2, [r3, #16] - 800140c: 615a str r2, [r3, #20] + 8000ff6: 463b mov r3, r7 + 8000ff8: 2200 movs r2, #0 + 8000ffa: 601a str r2, [r3, #0] + 8000ffc: 605a str r2, [r3, #4] + 8000ffe: 609a str r2, [r3, #8] + 8001000: 60da str r2, [r3, #12] + 8001002: 611a str r2, [r3, #16] + 8001004: 615a str r2, [r3, #20] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; - 800140e: 4b31 ldr r3, [pc, #196] ; (80014d4 ) - 8001410: 4a31 ldr r2, [pc, #196] ; (80014d8 ) - 8001412: 601a str r2, [r3, #0] + 8001006: 4b38 ldr r3, [pc, #224] ; (80010e8 ) + 8001008: 4a38 ldr r2, [pc, #224] ; (80010ec ) + 800100a: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; - 8001414: 4b2f ldr r3, [pc, #188] ; (80014d4 ) - 8001416: 2200 movs r2, #0 - 8001418: 605a str r2, [r3, #4] + 800100c: 4b36 ldr r3, [pc, #216] ; (80010e8 ) + 800100e: 2200 movs r2, #0 + 8001010: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; - 800141a: 4b2e ldr r3, [pc, #184] ; (80014d4 ) - 800141c: 2200 movs r2, #0 - 800141e: 609a str r2, [r3, #8] + 8001012: 4b35 ldr r3, [pc, #212] ; (80010e8 ) + 8001014: 2200 movs r2, #0 + 8001016: 609a str r2, [r3, #8] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 8001420: 4b2c ldr r3, [pc, #176] ; (80014d4 ) - 8001422: 2200 movs r2, #0 - 8001424: 60da str r2, [r3, #12] + 8001018: 4b33 ldr r3, [pc, #204] ; (80010e8 ) + 800101a: 2200 movs r2, #0 + 800101c: 60da str r2, [r3, #12] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; - 8001426: 4b2b ldr r3, [pc, #172] ; (80014d4 ) - 8001428: 2201 movs r2, #1 - 800142a: 611a str r2, [r3, #16] + 800101e: 4b32 ldr r3, [pc, #200] ; (80010e8 ) + 8001020: 2201 movs r2, #1 + 8001022: 611a str r2, [r3, #16] hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - 800142c: 4b29 ldr r3, [pc, #164] ; (80014d4 ) - 800142e: 2204 movs r2, #4 - 8001430: 615a str r2, [r3, #20] + 8001024: 4b30 ldr r3, [pc, #192] ; (80010e8 ) + 8001026: 2204 movs r2, #4 + 8001028: 615a str r2, [r3, #20] hadc1.Init.LowPowerAutoWait = DISABLE; - 8001432: 4b28 ldr r3, [pc, #160] ; (80014d4 ) - 8001434: 2200 movs r2, #0 - 8001436: 761a strb r2, [r3, #24] + 800102a: 4b2f ldr r3, [pc, #188] ; (80010e8 ) + 800102c: 2200 movs r2, #0 + 800102e: 761a strb r2, [r3, #24] hadc1.Init.ContinuousConvMode = ENABLE; - 8001438: 4b26 ldr r3, [pc, #152] ; (80014d4 ) - 800143a: 2201 movs r2, #1 - 800143c: 765a strb r2, [r3, #25] - hadc1.Init.NbrOfConversion = 2; - 800143e: 4b25 ldr r3, [pc, #148] ; (80014d4 ) - 8001440: 2202 movs r2, #2 - 8001442: 61da str r2, [r3, #28] + 8001030: 4b2d ldr r3, [pc, #180] ; (80010e8 ) + 8001032: 2201 movs r2, #1 + 8001034: 765a strb r2, [r3, #25] + hadc1.Init.NbrOfConversion = 3; + 8001036: 4b2c ldr r3, [pc, #176] ; (80010e8 ) + 8001038: 2203 movs r2, #3 + 800103a: 61da str r2, [r3, #28] hadc1.Init.DiscontinuousConvMode = DISABLE; - 8001444: 4b23 ldr r3, [pc, #140] ; (80014d4 ) - 8001446: 2200 movs r2, #0 - 8001448: f883 2020 strb.w r2, [r3, #32] + 800103c: 4b2a ldr r3, [pc, #168] ; (80010e8 ) + 800103e: 2200 movs r2, #0 + 8001040: f883 2020 strb.w r2, [r3, #32] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; - 800144c: 4b21 ldr r3, [pc, #132] ; (80014d4 ) - 800144e: f44f 62d8 mov.w r2, #1728 ; 0x6c0 - 8001452: 629a str r2, [r3, #40] ; 0x28 + 8001044: 4b28 ldr r3, [pc, #160] ; (80010e8 ) + 8001046: f44f 62d8 mov.w r2, #1728 ; 0x6c0 + 800104a: 629a str r2, [r3, #40] ; 0x28 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; - 8001454: 4b1f ldr r3, [pc, #124] ; (80014d4 ) - 8001456: f44f 6280 mov.w r2, #1024 ; 0x400 - 800145a: 62da str r2, [r3, #44] ; 0x2c + 800104c: 4b26 ldr r3, [pc, #152] ; (80010e8 ) + 800104e: f44f 6280 mov.w r2, #1024 ; 0x400 + 8001052: 62da str r2, [r3, #44] ; 0x2c hadc1.Init.DMAContinuousRequests = DISABLE; - 800145c: 4b1d ldr r3, [pc, #116] ; (80014d4 ) - 800145e: 2200 movs r2, #0 - 8001460: f883 2030 strb.w r2, [r3, #48] ; 0x30 + 8001054: 4b24 ldr r3, [pc, #144] ; (80010e8 ) + 8001056: 2200 movs r2, #0 + 8001058: f883 2030 strb.w r2, [r3, #48] ; 0x30 hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; - 8001464: 4b1b ldr r3, [pc, #108] ; (80014d4 ) - 8001466: 2200 movs r2, #0 - 8001468: 635a str r2, [r3, #52] ; 0x34 + 800105c: 4b22 ldr r3, [pc, #136] ; (80010e8 ) + 800105e: 2200 movs r2, #0 + 8001060: 635a str r2, [r3, #52] ; 0x34 hadc1.Init.OversamplingMode = DISABLE; - 800146a: 4b1a ldr r3, [pc, #104] ; (80014d4 ) - 800146c: 2200 movs r2, #0 - 800146e: f883 2038 strb.w r2, [r3, #56] ; 0x38 + 8001062: 4b21 ldr r3, [pc, #132] ; (80010e8 ) + 8001064: 2200 movs r2, #0 + 8001066: f883 2038 strb.w r2, [r3, #56] ; 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) - 8001472: 4818 ldr r0, [pc, #96] ; (80014d4 ) - 8001474: f003 faac bl 80049d0 - 8001478: 4603 mov r3, r0 - 800147a: 2b00 cmp r3, #0 - 800147c: d001 beq.n 8001482 + 800106a: 481f ldr r0, [pc, #124] ; (80010e8 ) + 800106c: f004 fafa bl 8005664 + 8001070: 4603 mov r3, r0 + 8001072: 2b00 cmp r3, #0 + 8001074: d001 beq.n 800107a { Error_Handler(); - 800147e: f000 f9bb bl 80017f8 + 8001076: f000 fcbc bl 80019f2 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; - 8001482: 4b16 ldr r3, [pc, #88] ; (80014dc ) - 8001484: 603b str r3, [r7, #0] + 800107a: 4b1d ldr r3, [pc, #116] ; (80010f0 ) + 800107c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; - 8001486: 2306 movs r3, #6 - 8001488: 607b str r3, [r7, #4] + 800107e: 2306 movs r3, #6 + 8001080: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; - 800148a: 2307 movs r3, #7 - 800148c: 60bb str r3, [r7, #8] + 8001082: 2307 movs r3, #7 + 8001084: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; - 800148e: 237f movs r3, #127 ; 0x7f - 8001490: 60fb str r3, [r7, #12] + 8001086: 237f movs r3, #127 ; 0x7f + 8001088: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; - 8001492: 2304 movs r3, #4 - 8001494: 613b str r3, [r7, #16] + 800108a: 2304 movs r3, #4 + 800108c: 613b str r3, [r7, #16] sConfig.Offset = 0; - 8001496: 2300 movs r3, #0 - 8001498: 617b str r3, [r7, #20] + 800108e: 2300 movs r3, #0 + 8001090: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 800149a: 463b mov r3, r7 - 800149c: 4619 mov r1, r3 - 800149e: 480d ldr r0, [pc, #52] ; (80014d4 ) - 80014a0: f003 fe2e bl 8005100 - 80014a4: 4603 mov r3, r0 - 80014a6: 2b00 cmp r3, #0 - 80014a8: d001 beq.n 80014ae + 8001092: 463b mov r3, r7 + 8001094: 4619 mov r1, r3 + 8001096: 4814 ldr r0, [pc, #80] ; (80010e8 ) + 8001098: f004 fe7c bl 8005d94 + 800109c: 4603 mov r3, r0 + 800109e: 2b00 cmp r3, #0 + 80010a0: d001 beq.n 80010a6 { Error_Handler(); - 80014aa: f000 f9a5 bl 80017f8 + 80010a2: f000 fca6 bl 80019f2 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; - 80014ae: 4b0c ldr r3, [pc, #48] ; (80014e0 ) - 80014b0: 603b str r3, [r7, #0] + 80010a6: 4b13 ldr r3, [pc, #76] ; (80010f4 ) + 80010a8: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; - 80014b2: 230c movs r3, #12 - 80014b4: 607b str r3, [r7, #4] + 80010aa: 230c movs r3, #12 + 80010ac: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - 80014b6: 463b mov r3, r7 - 80014b8: 4619 mov r1, r3 - 80014ba: 4806 ldr r0, [pc, #24] ; (80014d4 ) - 80014bc: f003 fe20 bl 8005100 - 80014c0: 4603 mov r3, r0 - 80014c2: 2b00 cmp r3, #0 - 80014c4: d001 beq.n 80014ca - { - Error_Handler(); - 80014c6: f000 f997 bl 80017f8 - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - 80014ca: bf00 nop - 80014cc: 3718 adds r7, #24 - 80014ce: 46bd mov sp, r7 - 80014d0: bd80 pop {r7, pc} - 80014d2: bf00 nop - 80014d4: 20000334 .word 0x20000334 - 80014d8: 50040000 .word 0x50040000 - 80014dc: 80000001 .word 0x80000001 - 80014e0: c7520000 .word 0xc7520000 - -080014e4 : - * @brief I2C3 Initialization Function - * @param None - * @retval None - */ -static void MX_I2C3_Init(void) -{ - 80014e4: b580 push {r7, lr} - 80014e6: af00 add r7, sp, #0 - /* USER CODE END I2C3_Init 0 */ - - /* USER CODE BEGIN I2C3_Init 1 */ - - /* USER CODE END I2C3_Init 1 */ - hi2c3.Instance = I2C3; - 80014e8: 4b1d ldr r3, [pc, #116] ; (8001560 ) - 80014ea: 4a1e ldr r2, [pc, #120] ; (8001564 ) - 80014ec: 601a str r2, [r3, #0] - hi2c3.Init.Timing = 0x00100618; - 80014ee: 4b1c ldr r3, [pc, #112] ; (8001560 ) - 80014f0: 4a1d ldr r2, [pc, #116] ; (8001568 ) - 80014f2: 605a str r2, [r3, #4] - hi2c3.Init.OwnAddress1 = 0; - 80014f4: 4b1a ldr r3, [pc, #104] ; (8001560 ) - 80014f6: 2200 movs r2, #0 - 80014f8: 609a str r2, [r3, #8] - hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - 80014fa: 4b19 ldr r3, [pc, #100] ; (8001560 ) - 80014fc: 2201 movs r2, #1 - 80014fe: 60da str r2, [r3, #12] - hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - 8001500: 4b17 ldr r3, [pc, #92] ; (8001560 ) - 8001502: 2200 movs r2, #0 - 8001504: 611a str r2, [r3, #16] - hi2c3.Init.OwnAddress2 = 0; - 8001506: 4b16 ldr r3, [pc, #88] ; (8001560 ) - 8001508: 2200 movs r2, #0 - 800150a: 615a str r2, [r3, #20] - hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - 800150c: 4b14 ldr r3, [pc, #80] ; (8001560 ) - 800150e: 2200 movs r2, #0 - 8001510: 619a str r2, [r3, #24] - hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - 8001512: 4b13 ldr r3, [pc, #76] ; (8001560 ) - 8001514: 2200 movs r2, #0 - 8001516: 61da str r2, [r3, #28] - hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - 8001518: 4b11 ldr r3, [pc, #68] ; (8001560 ) - 800151a: 2200 movs r2, #0 - 800151c: 621a str r2, [r3, #32] - if (HAL_I2C_Init(&hi2c3) != HAL_OK) - 800151e: 4810 ldr r0, [pc, #64] ; (8001560 ) - 8001520: f005 f9d8 bl 80068d4 - 8001524: 4603 mov r3, r0 - 8001526: 2b00 cmp r3, #0 - 8001528: d001 beq.n 800152e - { - Error_Handler(); - 800152a: f000 f965 bl 80017f8 - } - - /** Configure Analogue filter - */ - if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) - 800152e: 2100 movs r1, #0 - 8001530: 480b ldr r0, [pc, #44] ; (8001560 ) - 8001532: f005 fde3 bl 80070fc - 8001536: 4603 mov r3, r0 - 8001538: 2b00 cmp r3, #0 - 800153a: d001 beq.n 8001540 + 80010ae: 463b mov r3, r7 + 80010b0: 4619 mov r1, r3 + 80010b2: 480d ldr r0, [pc, #52] ; (80010e8 ) + 80010b4: f004 fe6e bl 8005d94 + 80010b8: 4603 mov r3, r0 + 80010ba: 2b00 cmp r3, #0 + 80010bc: d001 beq.n 80010c2 { Error_Handler(); - 800153c: f000 f95c bl 80017f8 + 80010be: f000 fc98 bl 80019f2 } - /** Configure Digital filter + /** Configure Regular Channel */ - if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) - 8001540: 2100 movs r1, #0 - 8001542: 4807 ldr r0, [pc, #28] ; (8001560 ) - 8001544: f005 fe25 bl 8007192 - 8001548: 4603 mov r3, r0 - 800154a: 2b00 cmp r3, #0 - 800154c: d001 beq.n 8001552 + sConfig.Channel = ADC_CHANNEL_9; + 80010c2: 4b0d ldr r3, [pc, #52] ; (80010f8 ) + 80010c4: 603b str r3, [r7, #0] + sConfig.Rank = ADC_REGULAR_RANK_3; + 80010c6: 2312 movs r3, #18 + 80010c8: 607b str r3, [r7, #4] + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 80010ca: 463b mov r3, r7 + 80010cc: 4619 mov r1, r3 + 80010ce: 4806 ldr r0, [pc, #24] ; (80010e8 ) + 80010d0: f004 fe60 bl 8005d94 + 80010d4: 4603 mov r3, r0 + 80010d6: 2b00 cmp r3, #0 + 80010d8: d001 beq.n 80010de { Error_Handler(); - 800154e: f000 f953 bl 80017f8 + 80010da: f000 fc8a bl 80019f2 } + /* USER CODE BEGIN ADC1_Init 2 */ - /** I2C Fast mode Plus enable - */ - HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3); - 8001552: f44f 0080 mov.w r0, #4194304 ; 0x400000 - 8001556: f005 fe69 bl 800722c - /* USER CODE BEGIN I2C3_Init 2 */ - - /* USER CODE END I2C3_Init 2 */ + /* USER CODE END ADC1_Init 2 */ } - 800155a: bf00 nop - 800155c: bd80 pop {r7, pc} - 800155e: bf00 nop - 8001560: 200003e0 .word 0x200003e0 - 8001564: 40005c00 .word 0x40005c00 - 8001568: 00100618 .word 0x00100618 + 80010de: bf00 nop + 80010e0: 3718 adds r7, #24 + 80010e2: 46bd mov sp, r7 + 80010e4: bd80 pop {r7, pc} + 80010e6: bf00 nop + 80010e8: 20000314 .word 0x20000314 + 80010ec: 50040000 .word 0x50040000 + 80010f0: 80000001 .word 0x80000001 + 80010f4: c7520000 .word 0xc7520000 + 80010f8: 25b00200 .word 0x25b00200 -0800156c : - * @brief LPUART1 Initialization Function - * @param None - * @retval None - */ -static void MX_LPUART1_UART_Init(void) -{ - 800156c: b580 push {r7, lr} - 800156e: af00 add r7, sp, #0 - /* USER CODE END LPUART1_Init 0 */ +080010fc : - /* USER CODE BEGIN LPUART1_Init 1 */ +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + 80010fc: b580 push {r7, lr} + 80010fe: b08a sub sp, #40 ; 0x28 + 8001100: af00 add r7, sp, #0 + 8001102: 6078 str r0, [r7, #4] - /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - 8001570: 4b12 ldr r3, [pc, #72] ; (80015bc ) - 8001572: 4a13 ldr r2, [pc, #76] ; (80015c0 ) - 8001574: 601a str r2, [r3, #0] - hlpuart1.Init.BaudRate = 9600; - 8001576: 4b11 ldr r3, [pc, #68] ; (80015bc ) - 8001578: f44f 5216 mov.w r2, #9600 ; 0x2580 - 800157c: 605a str r2, [r3, #4] - hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; - 800157e: 4b0f ldr r3, [pc, #60] ; (80015bc ) - 8001580: 2200 movs r2, #0 - 8001582: 609a str r2, [r3, #8] - hlpuart1.Init.StopBits = UART_STOPBITS_1; - 8001584: 4b0d ldr r3, [pc, #52] ; (80015bc ) - 8001586: 2200 movs r2, #0 - 8001588: 60da str r2, [r3, #12] - hlpuart1.Init.Parity = UART_PARITY_NONE; - 800158a: 4b0c ldr r3, [pc, #48] ; (80015bc ) - 800158c: 2200 movs r2, #0 - 800158e: 611a str r2, [r3, #16] - hlpuart1.Init.Mode = UART_MODE_TX_RX; - 8001590: 4b0a ldr r3, [pc, #40] ; (80015bc ) - 8001592: 220c movs r2, #12 - 8001594: 615a str r2, [r3, #20] - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8001596: 4b09 ldr r3, [pc, #36] ; (80015bc ) - 8001598: 2200 movs r2, #0 - 800159a: 619a str r2, [r3, #24] - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 800159c: 4b07 ldr r3, [pc, #28] ; (80015bc ) - 800159e: 2200 movs r2, #0 - 80015a0: 621a str r2, [r3, #32] - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 80015a2: 4b06 ldr r3, [pc, #24] ; (80015bc ) - 80015a4: 2200 movs r2, #0 - 80015a6: 625a str r2, [r3, #36] ; 0x24 - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - 80015a8: 4804 ldr r0, [pc, #16] ; (80015bc ) - 80015aa: f009 f97d bl 800a8a8 - 80015ae: 4603 mov r3, r0 - 80015b0: 2b00 cmp r3, #0 - 80015b2: d001 beq.n 80015b8 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001104: f107 0314 add.w r3, r7, #20 + 8001108: 2200 movs r2, #0 + 800110a: 601a str r2, [r3, #0] + 800110c: 605a str r2, [r3, #4] + 800110e: 609a str r2, [r3, #8] + 8001110: 60da str r2, [r3, #12] + 8001112: 611a str r2, [r3, #16] + if(adcHandle->Instance==ADC1) + 8001114: 687b ldr r3, [r7, #4] + 8001116: 681b ldr r3, [r3, #0] + 8001118: 4a2f ldr r2, [pc, #188] ; (80011d8 ) + 800111a: 4293 cmp r3, r2 + 800111c: d157 bne.n 80011ce { - Error_Handler(); - 80015b4: f000 f920 bl 80017f8 - } - /* USER CODE BEGIN LPUART1_Init 2 */ + /* USER CODE BEGIN ADC1_MspInit 0 */ - /* USER CODE END LPUART1_Init 2 */ + /* USER CODE END ADC1_MspInit 0 */ + /* ADC1 clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + 800111e: 4b2f ldr r3, [pc, #188] ; (80011dc ) + 8001120: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001122: 4a2e ldr r2, [pc, #184] ; (80011dc ) + 8001124: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 8001128: 64d3 str r3, [r2, #76] ; 0x4c + 800112a: 4b2c ldr r3, [pc, #176] ; (80011dc ) + 800112c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800112e: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8001132: 613b str r3, [r7, #16] + 8001134: 693b ldr r3, [r7, #16] -} - 80015b8: bf00 nop - 80015ba: bd80 pop {r7, pc} - 80015bc: 20000434 .word 0x20000434 - 80015c0: 40008000 .word 0x40008000 - -080015c4 : - * @brief TIM2 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM2_Init(void) -{ - 80015c4: b580 push {r7, lr} - 80015c6: b088 sub sp, #32 - 80015c8: af00 add r7, sp, #0 - - /* USER CODE BEGIN TIM2_Init 0 */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001136: 4b29 ldr r3, [pc, #164] ; (80011dc ) + 8001138: 6cdb ldr r3, [r3, #76] ; 0x4c + 800113a: 4a28 ldr r2, [pc, #160] ; (80011dc ) + 800113c: f043 0301 orr.w r3, r3, #1 + 8001140: 64d3 str r3, [r2, #76] ; 0x4c + 8001142: 4b26 ldr r3, [pc, #152] ; (80011dc ) + 8001144: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001146: f003 0301 and.w r3, r3, #1 + 800114a: 60fb str r3, [r7, #12] + 800114c: 68fb ldr r3, [r7, #12] + /**ADC1 GPIO Configuration + PA4 ------> ADC1_IN9 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + 800114e: 2310 movs r3, #16 + 8001150: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; + 8001152: 230b movs r3, #11 + 8001154: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001156: 2300 movs r3, #0 + 8001158: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800115a: f107 0314 add.w r3, r7, #20 + 800115e: 4619 mov r1, r3 + 8001160: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001164: f005 fed8 bl 8006f18 - /* USER CODE END TIM2_Init 0 */ + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Channel1; + 8001168: 4b1d ldr r3, [pc, #116] ; (80011e0 ) + 800116a: 4a1e ldr r2, [pc, #120] ; (80011e4 ) + 800116c: 601a str r2, [r3, #0] + hdma_adc1.Init.Request = DMA_REQUEST_0; + 800116e: 4b1c ldr r3, [pc, #112] ; (80011e0 ) + 8001170: 2200 movs r2, #0 + 8001172: 605a str r2, [r3, #4] + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8001174: 4b1a ldr r3, [pc, #104] ; (80011e0 ) + 8001176: 2200 movs r2, #0 + 8001178: 609a str r2, [r3, #8] + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + 800117a: 4b19 ldr r3, [pc, #100] ; (80011e0 ) + 800117c: 2200 movs r2, #0 + 800117e: 60da str r2, [r3, #12] + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + 8001180: 4b17 ldr r3, [pc, #92] ; (80011e0 ) + 8001182: 2280 movs r2, #128 ; 0x80 + 8001184: 611a str r2, [r3, #16] + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + 8001186: 4b16 ldr r3, [pc, #88] ; (80011e0 ) + 8001188: f44f 7280 mov.w r2, #256 ; 0x100 + 800118c: 615a str r2, [r3, #20] + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + 800118e: 4b14 ldr r3, [pc, #80] ; (80011e0 ) + 8001190: f44f 6280 mov.w r2, #1024 ; 0x400 + 8001194: 619a str r2, [r3, #24] + hdma_adc1.Init.Mode = DMA_NORMAL; + 8001196: 4b12 ldr r3, [pc, #72] ; (80011e0 ) + 8001198: 2200 movs r2, #0 + 800119a: 61da str r2, [r3, #28] + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + 800119c: 4b10 ldr r3, [pc, #64] ; (80011e0 ) + 800119e: 2200 movs r2, #0 + 80011a0: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + 80011a2: 480f ldr r0, [pc, #60] ; (80011e0 ) + 80011a4: f005 fc36 bl 8006a14 + 80011a8: 4603 mov r3, r0 + 80011aa: 2b00 cmp r3, #0 + 80011ac: d001 beq.n 80011b2 + { + Error_Handler(); + 80011ae: f000 fc20 bl 80019f2 + } - TIM_ClockConfigTypeDef sClockSourceConfig = {0}; - 80015ca: f107 0310 add.w r3, r7, #16 - 80015ce: 2200 movs r2, #0 - 80015d0: 601a str r2, [r3, #0] - 80015d2: 605a str r2, [r3, #4] - 80015d4: 609a str r2, [r3, #8] - 80015d6: 60da str r2, [r3, #12] - TIM_MasterConfigTypeDef sMasterConfig = {0}; - 80015d8: 1d3b adds r3, r7, #4 - 80015da: 2200 movs r2, #0 - 80015dc: 601a str r2, [r3, #0] - 80015de: 605a str r2, [r3, #4] - 80015e0: 609a str r2, [r3, #8] + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + 80011b2: 687b ldr r3, [r7, #4] + 80011b4: 4a0a ldr r2, [pc, #40] ; (80011e0 ) + 80011b6: 64da str r2, [r3, #76] ; 0x4c + 80011b8: 4a09 ldr r2, [pc, #36] ; (80011e0 ) + 80011ba: 687b ldr r3, [r7, #4] + 80011bc: 6293 str r3, [r2, #40] ; 0x28 - /* USER CODE BEGIN TIM2_Init 1 */ + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); + 80011be: 2200 movs r2, #0 + 80011c0: 2100 movs r1, #0 + 80011c2: 2012 movs r0, #18 + 80011c4: f005 fbef bl 80069a6 + HAL_NVIC_EnableIRQ(ADC1_IRQn); + 80011c8: 2012 movs r0, #18 + 80011ca: f005 fc08 bl 80069de + /* USER CODE BEGIN ADC1_MspInit 1 */ - /* USER CODE END TIM2_Init 1 */ - htim2.Instance = TIM2; - 80015e2: 4b1e ldr r3, [pc, #120] ; (800165c ) - 80015e4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 - 80015e8: 601a str r2, [r3, #0] - htim2.Init.Prescaler = 400-1; - 80015ea: 4b1c ldr r3, [pc, #112] ; (800165c ) - 80015ec: f240 128f movw r2, #399 ; 0x18f - 80015f0: 605a str r2, [r3, #4] - htim2.Init.CounterMode = TIM_COUNTERMODE_UP; - 80015f2: 4b1a ldr r3, [pc, #104] ; (800165c ) - 80015f4: 2200 movs r2, #0 - 80015f6: 609a str r2, [r3, #8] - htim2.Init.Period = 10000-1; - 80015f8: 4b18 ldr r3, [pc, #96] ; (800165c ) - 80015fa: f242 720f movw r2, #9999 ; 0x270f - 80015fe: 60da str r2, [r3, #12] - htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - 8001600: 4b16 ldr r3, [pc, #88] ; (800165c ) - 8001602: 2200 movs r2, #0 - 8001604: 611a str r2, [r3, #16] - htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8001606: 4b15 ldr r3, [pc, #84] ; (800165c ) - 8001608: 2200 movs r2, #0 - 800160a: 619a str r2, [r3, #24] - if (HAL_TIM_Base_Init(&htim2) != HAL_OK) - 800160c: 4813 ldr r0, [pc, #76] ; (800165c ) - 800160e: f008 fd27 bl 800a060 - 8001612: 4603 mov r3, r0 - 8001614: 2b00 cmp r3, #0 - 8001616: d001 beq.n 800161c - { - Error_Handler(); - 8001618: f000 f8ee bl 80017f8 - } - sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; - 800161c: f44f 5380 mov.w r3, #4096 ; 0x1000 - 8001620: 613b str r3, [r7, #16] - if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) - 8001622: f107 0310 add.w r3, r7, #16 - 8001626: 4619 mov r1, r3 - 8001628: 480c ldr r0, [pc, #48] ; (800165c ) - 800162a: f008 febf bl 800a3ac - 800162e: 4603 mov r3, r0 - 8001630: 2b00 cmp r3, #0 - 8001632: d001 beq.n 8001638 - { - Error_Handler(); - 8001634: f000 f8e0 bl 80017f8 - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - 8001638: 2320 movs r3, #32 - 800163a: 607b str r3, [r7, #4] - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 800163c: 2300 movs r3, #0 - 800163e: 60fb str r3, [r7, #12] - if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) - 8001640: 1d3b adds r3, r7, #4 - 8001642: 4619 mov r1, r3 - 8001644: 4805 ldr r0, [pc, #20] ; (800165c ) - 8001646: f009 f8ab bl 800a7a0 - 800164a: 4603 mov r3, r0 - 800164c: 2b00 cmp r3, #0 - 800164e: d001 beq.n 8001654 - { - Error_Handler(); - 8001650: f000 f8d2 bl 80017f8 + /* USER CODE END ADC1_MspInit 1 */ } - /* USER CODE BEGIN TIM2_Init 2 */ - - /* USER CODE END TIM2_Init 2 */ - } - 8001654: bf00 nop - 8001656: 3720 adds r7, #32 - 8001658: 46bd mov sp, r7 - 800165a: bd80 pop {r7, pc} - 800165c: 20000504 .word 0x20000504 - -08001660 : - * @brief TIM7 Initialization Function - * @param None - * @retval None - */ -static void MX_TIM7_Init(void) -{ - 8001660: b580 push {r7, lr} - 8001662: b084 sub sp, #16 - 8001664: af00 add r7, sp, #0 - - /* USER CODE BEGIN TIM7_Init 0 */ + 80011ce: bf00 nop + 80011d0: 3728 adds r7, #40 ; 0x28 + 80011d2: 46bd mov sp, r7 + 80011d4: bd80 pop {r7, pc} + 80011d6: bf00 nop + 80011d8: 50040000 .word 0x50040000 + 80011dc: 40021000 .word 0x40021000 + 80011e0: 20000378 .word 0x20000378 + 80011e4: 40020008 .word 0x40020008 - /* USER CODE END TIM7_Init 0 */ - - TIM_MasterConfigTypeDef sMasterConfig = {0}; - 8001666: 1d3b adds r3, r7, #4 - 8001668: 2200 movs r2, #0 - 800166a: 601a str r2, [r3, #0] - 800166c: 605a str r2, [r3, #4] - 800166e: 609a str r2, [r3, #8] - - /* USER CODE BEGIN TIM7_Init 1 */ - - /* USER CODE END TIM7_Init 1 */ - htim7.Instance = TIM7; - 8001670: 4b15 ldr r3, [pc, #84] ; (80016c8 ) - 8001672: 4a16 ldr r2, [pc, #88] ; (80016cc ) - 8001674: 601a str r2, [r3, #0] - htim7.Init.Prescaler = 10000-1; - 8001676: 4b14 ldr r3, [pc, #80] ; (80016c8 ) - 8001678: f242 720f movw r2, #9999 ; 0x270f - 800167c: 605a str r2, [r3, #4] - htim7.Init.CounterMode = TIM_COUNTERMODE_UP; - 800167e: 4b12 ldr r3, [pc, #72] ; (80016c8 ) - 8001680: 2200 movs r2, #0 - 8001682: 609a str r2, [r3, #8] - htim7.Init.Period = 8000-1; - 8001684: 4b10 ldr r3, [pc, #64] ; (80016c8 ) - 8001686: f641 723f movw r2, #7999 ; 0x1f3f - 800168a: 60da str r2, [r3, #12] - htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 800168c: 4b0e ldr r3, [pc, #56] ; (80016c8 ) - 800168e: 2200 movs r2, #0 - 8001690: 619a str r2, [r3, #24] - if (HAL_TIM_Base_Init(&htim7) != HAL_OK) - 8001692: 480d ldr r0, [pc, #52] ; (80016c8 ) - 8001694: f008 fce4 bl 800a060 - 8001698: 4603 mov r3, r0 - 800169a: 2b00 cmp r3, #0 - 800169c: d001 beq.n 80016a2 - { - Error_Handler(); - 800169e: f000 f8ab bl 80017f8 +080011e8 : + /* USER CODE END ADC1_MspDeInit 1 */ } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - 80016a2: 2300 movs r3, #0 - 80016a4: 607b str r3, [r7, #4] - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - 80016a6: 2300 movs r3, #0 - 80016a8: 60fb str r3, [r7, #12] - if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK) - 80016aa: 1d3b adds r3, r7, #4 - 80016ac: 4619 mov r1, r3 - 80016ae: 4806 ldr r0, [pc, #24] ; (80016c8 ) - 80016b0: f009 f876 bl 800a7a0 - 80016b4: 4603 mov r3, r0 - 80016b6: 2b00 cmp r3, #0 - 80016b8: d001 beq.n 80016be - { - Error_Handler(); - 80016ba: f000 f89d bl 80017f8 - } - /* USER CODE BEGIN TIM7_Init 2 */ +} - /* USER CODE END TIM7_Init 2 */ +/* USER CODE BEGIN 1 */ +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){ + 80011e8: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 80011ec: b082 sub sp, #8 + 80011ee: af00 add r7, sp, #0 + 80011f0: 6078 str r0, [r7, #4] -} - 80016be: bf00 nop - 80016c0: 3710 adds r7, #16 - 80016c2: 46bd mov sp, r7 - 80016c4: bd80 pop {r7, pc} - 80016c6: bf00 nop - 80016c8: 20000550 .word 0x20000550 - 80016cc: 40001400 .word 0x40001400 + if(hadc->Instance==ADC1){ + 80011f2: 687b ldr r3, [r7, #4] + 80011f4: 681b ldr r3, [r3, #0] + 80011f6: 4a54 ldr r2, [pc, #336] ; (8001348 ) + 80011f8: 4293 cmp r3, r2 + 80011fa: f040 8091 bne.w 8001320 + vrefint=(float) ((4095.0*1.212)/rawdata[0]); + 80011fe: 4b53 ldr r3, [pc, #332] ; (800134c ) + 8001200: 881b ldrh r3, [r3, #0] + 8001202: 4618 mov r0, r3 + 8001204: f7ff f98e bl 8000524 <__aeabi_i2d> + 8001208: 4602 mov r2, r0 + 800120a: 460b mov r3, r1 + 800120c: a14a add r1, pc, #296 ; (adr r1, 8001338 ) + 800120e: e9d1 0100 ldrd r0, r1, [r1] + 8001212: f7ff fb1b bl 800084c <__aeabi_ddiv> + 8001216: 4602 mov r2, r0 + 8001218: 460b mov r3, r1 + 800121a: 4610 mov r0, r2 + 800121c: 4619 mov r1, r3 + 800121e: f7ff fce3 bl 8000be8 <__aeabi_d2f> + 8001222: 4603 mov r3, r0 + 8001224: 4a4a ldr r2, [pc, #296] ; (8001350 ) + 8001226: 6013 str r3, [r2, #0] +// vtemp=(float) ((vrefint*rawdata[1])/4095.0); + temp=(float) (((100.0)/(tscal2-tscal1))*(rawdata[1]*(vrefint/3.0)-tscal1))+30.0; + 8001228: 4b4a ldr r3, [pc, #296] ; (8001354 ) + 800122a: ed93 7a00 vldr s14, [r3] + 800122e: 4b4a ldr r3, [pc, #296] ; (8001358 ) + 8001230: edd3 7a00 vldr s15, [r3] + 8001234: ee77 7a67 vsub.f32 s15, s14, s15 + 8001238: ee17 0a90 vmov r0, s15 + 800123c: f7ff f984 bl 8000548 <__aeabi_f2d> + 8001240: 4602 mov r2, r0 + 8001242: 460b mov r3, r1 + 8001244: f04f 0000 mov.w r0, #0 + 8001248: 4944 ldr r1, [pc, #272] ; (800135c ) + 800124a: f7ff faff bl 800084c <__aeabi_ddiv> + 800124e: 4602 mov r2, r0 + 8001250: 460b mov r3, r1 + 8001252: 4690 mov r8, r2 + 8001254: 4699 mov r9, r3 + 8001256: 4b3d ldr r3, [pc, #244] ; (800134c ) + 8001258: 885b ldrh r3, [r3, #2] + 800125a: 4618 mov r0, r3 + 800125c: f7ff f962 bl 8000524 <__aeabi_i2d> + 8001260: 4604 mov r4, r0 + 8001262: 460d mov r5, r1 + 8001264: 4b3a ldr r3, [pc, #232] ; (8001350 ) + 8001266: 681b ldr r3, [r3, #0] + 8001268: 4618 mov r0, r3 + 800126a: f7ff f96d bl 8000548 <__aeabi_f2d> + 800126e: f04f 0200 mov.w r2, #0 + 8001272: 4b3b ldr r3, [pc, #236] ; (8001360 ) + 8001274: f7ff faea bl 800084c <__aeabi_ddiv> + 8001278: 4602 mov r2, r0 + 800127a: 460b mov r3, r1 + 800127c: 4620 mov r0, r4 + 800127e: 4629 mov r1, r5 + 8001280: f7ff f9ba bl 80005f8 <__aeabi_dmul> + 8001284: 4602 mov r2, r0 + 8001286: 460b mov r3, r1 + 8001288: 4614 mov r4, r2 + 800128a: 461d mov r5, r3 + 800128c: 4b32 ldr r3, [pc, #200] ; (8001358 ) + 800128e: 681b ldr r3, [r3, #0] + 8001290: 4618 mov r0, r3 + 8001292: f7ff f959 bl 8000548 <__aeabi_f2d> + 8001296: 4602 mov r2, r0 + 8001298: 460b mov r3, r1 + 800129a: 4620 mov r0, r4 + 800129c: 4629 mov r1, r5 + 800129e: f7fe fff3 bl 8000288 <__aeabi_dsub> + 80012a2: 4602 mov r2, r0 + 80012a4: 460b mov r3, r1 + 80012a6: 4640 mov r0, r8 + 80012a8: 4649 mov r1, r9 + 80012aa: f7ff f9a5 bl 80005f8 <__aeabi_dmul> + 80012ae: 4602 mov r2, r0 + 80012b0: 460b mov r3, r1 + 80012b2: 4610 mov r0, r2 + 80012b4: 4619 mov r1, r3 + 80012b6: f7ff fc97 bl 8000be8 <__aeabi_d2f> + 80012ba: ee07 0a10 vmov s14, r0 + 80012be: eef3 7a0e vmov.f32 s15, #62 ; 0x41f00000 30.0 + 80012c2: ee77 7a27 vadd.f32 s15, s14, s15 + 80012c6: 4b27 ldr r3, [pc, #156] ; (8001364 ) + 80012c8: edc3 7a00 vstr s15, [r3] + vbat=(float) 2*(rawdata[2]/4095.0)*vrefint; + 80012cc: 4b1f ldr r3, [pc, #124] ; (800134c ) + 80012ce: 889b ldrh r3, [r3, #4] + 80012d0: 4618 mov r0, r3 + 80012d2: f7ff f927 bl 8000524 <__aeabi_i2d> + 80012d6: a31a add r3, pc, #104 ; (adr r3, 8001340 ) + 80012d8: e9d3 2300 ldrd r2, r3, [r3] + 80012dc: f7ff fab6 bl 800084c <__aeabi_ddiv> + 80012e0: 4602 mov r2, r0 + 80012e2: 460b mov r3, r1 + 80012e4: 4610 mov r0, r2 + 80012e6: 4619 mov r1, r3 + 80012e8: 4602 mov r2, r0 + 80012ea: 460b mov r3, r1 + 80012ec: f7fe ffce bl 800028c <__adddf3> + 80012f0: 4602 mov r2, r0 + 80012f2: 460b mov r3, r1 + 80012f4: 4614 mov r4, r2 + 80012f6: 461d mov r5, r3 + 80012f8: 4b15 ldr r3, [pc, #84] ; (8001350 ) + 80012fa: 681b ldr r3, [r3, #0] + 80012fc: 4618 mov r0, r3 + 80012fe: f7ff f923 bl 8000548 <__aeabi_f2d> + 8001302: 4602 mov r2, r0 + 8001304: 460b mov r3, r1 + 8001306: 4620 mov r0, r4 + 8001308: 4629 mov r1, r5 + 800130a: f7ff f975 bl 80005f8 <__aeabi_dmul> + 800130e: 4602 mov r2, r0 + 8001310: 460b mov r3, r1 + 8001312: 4610 mov r0, r2 + 8001314: 4619 mov r1, r3 + 8001316: f7ff fc67 bl 8000be8 <__aeabi_d2f> + 800131a: 4603 mov r3, r0 + 800131c: 4a12 ldr r2, [pc, #72] ; (8001368 ) + 800131e: 6013 str r3, [r2, #0] -080016d0 : + } + HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 3); + 8001320: 2203 movs r2, #3 + 8001322: 490a ldr r1, [pc, #40] ; (800134c ) + 8001324: 4811 ldr r0, [pc, #68] ; (800136c ) + 8001326: f004 fadf bl 80058e8 + + + +} + 800132a: bf00 nop + 800132c: 3708 adds r7, #8 + 800132e: 46bd mov sp, r7 + 8001330: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 8001334: f3af 8000 nop.w + 8001338: d70a3d70 .word 0xd70a3d70 + 800133c: 40b36323 .word 0x40b36323 + 8001340: 00000000 .word 0x00000000 + 8001344: 40affe00 .word 0x40affe00 + 8001348: 50040000 .word 0x50040000 + 800134c: 20000720 .word 0x20000720 + 8001350: 2000072c .word 0x2000072c + 8001354: 20000000 .word 0x20000000 + 8001358: 20000004 .word 0x20000004 + 800135c: 40590000 .word 0x40590000 + 8001360: 40080000 .word 0x40080000 + 8001364: 20000728 .word 0x20000728 + 8001368: 20000730 .word 0x20000730 + 800136c: 20000314 .word 0x20000314 + +08001370 : /** * Enable DMA controller clock */ -static void MX_DMA_Init(void) +void MX_DMA_Init(void) { - 80016d0: b580 push {r7, lr} - 80016d2: b082 sub sp, #8 - 80016d4: af00 add r7, sp, #0 + 8001370: b580 push {r7, lr} + 8001372: b082 sub sp, #8 + 8001374: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); - 80016d6: 4b16 ldr r3, [pc, #88] ; (8001730 ) - 80016d8: 6c9b ldr r3, [r3, #72] ; 0x48 - 80016da: 4a15 ldr r2, [pc, #84] ; (8001730 ) - 80016dc: f043 0301 orr.w r3, r3, #1 - 80016e0: 6493 str r3, [r2, #72] ; 0x48 - 80016e2: 4b13 ldr r3, [pc, #76] ; (8001730 ) - 80016e4: 6c9b ldr r3, [r3, #72] ; 0x48 - 80016e6: f003 0301 and.w r3, r3, #1 - 80016ea: 607b str r3, [r7, #4] - 80016ec: 687b ldr r3, [r7, #4] + 8001376: 4b16 ldr r3, [pc, #88] ; (80013d0 ) + 8001378: 6c9b ldr r3, [r3, #72] ; 0x48 + 800137a: 4a15 ldr r2, [pc, #84] ; (80013d0 ) + 800137c: f043 0301 orr.w r3, r3, #1 + 8001380: 6493 str r3, [r2, #72] ; 0x48 + 8001382: 4b13 ldr r3, [pc, #76] ; (80013d0 ) + 8001384: 6c9b ldr r3, [r3, #72] ; 0x48 + 8001386: f003 0301 and.w r3, r3, #1 + 800138a: 607b str r3, [r7, #4] + 800138c: 687b ldr r3, [r7, #4] __HAL_RCC_DMA2_CLK_ENABLE(); - 80016ee: 4b10 ldr r3, [pc, #64] ; (8001730 ) - 80016f0: 6c9b ldr r3, [r3, #72] ; 0x48 - 80016f2: 4a0f ldr r2, [pc, #60] ; (8001730 ) - 80016f4: f043 0302 orr.w r3, r3, #2 - 80016f8: 6493 str r3, [r2, #72] ; 0x48 - 80016fa: 4b0d ldr r3, [pc, #52] ; (8001730 ) - 80016fc: 6c9b ldr r3, [r3, #72] ; 0x48 - 80016fe: f003 0302 and.w r3, r3, #2 - 8001702: 603b str r3, [r7, #0] - 8001704: 683b ldr r3, [r7, #0] + 800138e: 4b10 ldr r3, [pc, #64] ; (80013d0 ) + 8001390: 6c9b ldr r3, [r3, #72] ; 0x48 + 8001392: 4a0f ldr r2, [pc, #60] ; (80013d0 ) + 8001394: f043 0302 orr.w r3, r3, #2 + 8001398: 6493 str r3, [r2, #72] ; 0x48 + 800139a: 4b0d ldr r3, [pc, #52] ; (80013d0 ) + 800139c: 6c9b ldr r3, [r3, #72] ; 0x48 + 800139e: f003 0302 and.w r3, r3, #2 + 80013a2: 603b str r3, [r7, #0] + 80013a4: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); - 8001706: 2200 movs r2, #0 - 8001708: 2100 movs r1, #0 - 800170a: 200b movs r0, #11 - 800170c: f004 fb25 bl 8005d5a + 80013a6: 2200 movs r2, #0 + 80013a8: 2100 movs r1, #0 + 80013aa: 200b movs r0, #11 + 80013ac: f005 fafb bl 80069a6 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - 8001710: 200b movs r0, #11 - 8001712: f004 fb3e bl 8005d92 + 80013b0: 200b movs r0, #11 + 80013b2: f005 fb14 bl 80069de /* DMA2_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Channel7_IRQn, 0, 0); - 8001716: 2200 movs r2, #0 - 8001718: 2100 movs r1, #0 - 800171a: 2045 movs r0, #69 ; 0x45 - 800171c: f004 fb1d bl 8005d5a + 80013b6: 2200 movs r2, #0 + 80013b8: 2100 movs r1, #0 + 80013ba: 2045 movs r0, #69 ; 0x45 + 80013bc: f005 faf3 bl 80069a6 HAL_NVIC_EnableIRQ(DMA2_Channel7_IRQn); - 8001720: 2045 movs r0, #69 ; 0x45 - 8001722: f004 fb36 bl 8005d92 + 80013c0: 2045 movs r0, #69 ; 0x45 + 80013c2: f005 fb0c bl 80069de } - 8001726: bf00 nop - 8001728: 3708 adds r7, #8 - 800172a: 46bd mov sp, r7 - 800172c: bd80 pop {r7, pc} - 800172e: bf00 nop - 8001730: 40021000 .word 0x40021000 + 80013c6: bf00 nop + 80013c8: 3708 adds r7, #8 + 80013ca: 46bd mov sp, r7 + 80013cc: bd80 pop {r7, pc} + 80013ce: bf00 nop + 80013d0: 40021000 .word 0x40021000 -08001734 : - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) +080013d4 : + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) { - 8001734: b580 push {r7, lr} - 8001736: b088 sub sp, #32 - 8001738: af00 add r7, sp, #0 + 80013d4: b580 push {r7, lr} + 80013d6: b088 sub sp, #32 + 80013d8: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800173a: f107 030c add.w r3, r7, #12 - 800173e: 2200 movs r2, #0 - 8001740: 601a str r2, [r3, #0] - 8001742: 605a str r2, [r3, #4] - 8001744: 609a str r2, [r3, #8] - 8001746: 60da str r2, [r3, #12] - 8001748: 611a str r2, [r3, #16] -/* USER CODE BEGIN MX_GPIO_Init_1 */ -/* USER CODE END MX_GPIO_Init_1 */ + 80013da: f107 030c add.w r3, r7, #12 + 80013de: 2200 movs r2, #0 + 80013e0: 601a str r2, [r3, #0] + 80013e2: 605a str r2, [r3, #4] + 80013e4: 609a str r2, [r3, #8] + 80013e6: 60da str r2, [r3, #12] + 80013e8: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - 800174a: 4b29 ldr r3, [pc, #164] ; (80017f0 ) - 800174c: 6cdb ldr r3, [r3, #76] ; 0x4c - 800174e: 4a28 ldr r2, [pc, #160] ; (80017f0 ) - 8001750: f043 0304 orr.w r3, r3, #4 - 8001754: 64d3 str r3, [r2, #76] ; 0x4c - 8001756: 4b26 ldr r3, [pc, #152] ; (80017f0 ) - 8001758: 6cdb ldr r3, [r3, #76] ; 0x4c - 800175a: f003 0304 and.w r3, r3, #4 - 800175e: 60bb str r3, [r7, #8] - 8001760: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8001762: 4b23 ldr r3, [pc, #140] ; (80017f0 ) - 8001764: 6cdb ldr r3, [r3, #76] ; 0x4c - 8001766: 4a22 ldr r2, [pc, #136] ; (80017f0 ) - 8001768: f043 0301 orr.w r3, r3, #1 - 800176c: 64d3 str r3, [r2, #76] ; 0x4c - 800176e: 4b20 ldr r3, [pc, #128] ; (80017f0 ) - 8001770: 6cdb ldr r3, [r3, #76] ; 0x4c - 8001772: f003 0301 and.w r3, r3, #1 - 8001776: 607b str r3, [r7, #4] - 8001778: 687b ldr r3, [r7, #4] + 80013ea: 4b38 ldr r3, [pc, #224] ; (80014cc ) + 80013ec: 6cdb ldr r3, [r3, #76] ; 0x4c + 80013ee: 4a37 ldr r2, [pc, #220] ; (80014cc ) + 80013f0: f043 0301 orr.w r3, r3, #1 + 80013f4: 64d3 str r3, [r2, #76] ; 0x4c + 80013f6: 4b35 ldr r3, [pc, #212] ; (80014cc ) + 80013f8: 6cdb ldr r3, [r3, #76] ; 0x4c + 80013fa: f003 0301 and.w r3, r3, #1 + 80013fe: 60bb str r3, [r7, #8] + 8001400: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 800177a: 4b1d ldr r3, [pc, #116] ; (80017f0 ) - 800177c: 6cdb ldr r3, [r3, #76] ; 0x4c - 800177e: 4a1c ldr r2, [pc, #112] ; (80017f0 ) - 8001780: f043 0302 orr.w r3, r3, #2 - 8001784: 64d3 str r3, [r2, #76] ; 0x4c - 8001786: 4b1a ldr r3, [pc, #104] ; (80017f0 ) - 8001788: 6cdb ldr r3, [r3, #76] ; 0x4c - 800178a: f003 0302 and.w r3, r3, #2 - 800178e: 603b str r3, [r7, #0] - 8001790: 683b ldr r3, [r7, #0] + 8001402: 4b32 ldr r3, [pc, #200] ; (80014cc ) + 8001404: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001406: 4a31 ldr r2, [pc, #196] ; (80014cc ) + 8001408: f043 0302 orr.w r3, r3, #2 + 800140c: 64d3 str r3, [r2, #76] ; 0x4c + 800140e: 4b2f ldr r3, [pc, #188] ; (80014cc ) + 8001410: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001412: f003 0302 and.w r3, r3, #2 + 8001416: 607b str r3, [r7, #4] + 8001418: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); - 8001792: 2200 movs r2, #0 - 8001794: 2102 movs r1, #2 - 8001796: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 800179a: f005 f86b bl 8006874 - - /*Configure GPIO pins : PC14 PC15 */ - GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; - 800179e: f44f 4340 mov.w r3, #49152 ; 0xc000 - 80017a2: 60fb str r3, [r7, #12] - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - 80017a4: f44f 1388 mov.w r3, #1114112 ; 0x110000 - 80017a8: 613b str r3, [r7, #16] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 80017aa: 2300 movs r3, #0 - 80017ac: 617b str r3, [r7, #20] - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 80017ae: f107 030c add.w r3, r7, #12 - 80017b2: 4619 mov r1, r3 - 80017b4: 480f ldr r0, [pc, #60] ; (80017f4 ) - 80017b6: f004 fe29 bl 800640c + 800141a: 2200 movs r2, #0 + 800141c: 2102 movs r1, #2 + 800141e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001422: f005 fee3 bl 80071ec + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(FLASH_CS_GPIO_Port, FLASH_CS_Pin, GPIO_PIN_RESET); + 8001426: 2200 movs r2, #0 + 8001428: 2101 movs r1, #1 + 800142a: 4829 ldr r0, [pc, #164] ; (80014d0 ) + 800142c: f005 fede bl 80071ec /*Configure GPIO pin : PA1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; - 80017ba: 2302 movs r3, #2 - 80017bc: 60fb str r3, [r7, #12] + 8001430: 2302 movs r3, #2 + 8001432: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001434: 2301 movs r3, #1 + 8001436: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001438: 2300 movs r3, #0 + 800143a: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800143c: 2300 movs r3, #0 + 800143e: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001440: f107 030c add.w r3, r7, #12 + 8001444: 4619 mov r1, r3 + 8001446: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 800144a: f005 fd65 bl 8006f18 + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = FLASH_CS_Pin; + 800144e: 2301 movs r3, #1 + 8001450: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80017be: 2301 movs r3, #1 - 80017c0: 613b str r3, [r7, #16] + 8001452: 2301 movs r3, #1 + 8001454: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80017c2: 2300 movs r3, #0 - 80017c4: 617b str r3, [r7, #20] + 8001456: 2300 movs r3, #0 + 8001458: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80017c6: 2300 movs r3, #0 - 80017c8: 61bb str r3, [r7, #24] + 800145a: 2300 movs r3, #0 + 800145c: 61bb str r3, [r7, #24] + HAL_GPIO_Init(FLASH_CS_GPIO_Port, &GPIO_InitStruct); + 800145e: f107 030c add.w r3, r7, #12 + 8001462: 4619 mov r1, r3 + 8001464: 481a ldr r0, [pc, #104] ; (80014d0 ) + 8001466: f005 fd57 bl 8006f18 + + /*Configure GPIO pin : PB1 */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + 800146a: 2302 movs r3, #2 + 800146c: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 800146e: f44f 1304 mov.w r3, #2162688 ; 0x210000 + 8001472: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001474: 2300 movs r3, #0 + 8001476: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001478: f107 030c add.w r3, r7, #12 + 800147c: 4619 mov r1, r3 + 800147e: 4814 ldr r0, [pc, #80] ; (80014d0 ) + 8001480: f005 fd4a bl 8006f18 + + /*Configure GPIO pin : PA8 */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + 8001484: f44f 7380 mov.w r3, #256 ; 0x100 + 8001488: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 800148a: f44f 1304 mov.w r3, #2162688 ; 0x210000 + 800148e: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001490: 2300 movs r3, #0 + 8001492: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80017ca: f107 030c add.w r3, r7, #12 - 80017ce: 4619 mov r1, r3 - 80017d0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 80017d4: f004 fe1a bl 800640c + 8001494: f107 030c add.w r3, r7, #12 + 8001498: 4619 mov r1, r3 + 800149a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 800149e: f005 fd3b bl 8006f18 /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); - 80017d8: 2200 movs r2, #0 - 80017da: 2100 movs r1, #0 - 80017dc: 2028 movs r0, #40 ; 0x28 - 80017de: f004 fabc bl 8005d5a - HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); - 80017e2: 2028 movs r0, #40 ; 0x28 - 80017e4: f004 fad5 bl 8005d92 - -/* USER CODE BEGIN MX_GPIO_Init_2 */ -/* USER CODE END MX_GPIO_Init_2 */ -} - 80017e8: bf00 nop - 80017ea: 3720 adds r7, #32 - 80017ec: 46bd mov sp, r7 - 80017ee: bd80 pop {r7, pc} - 80017f0: 40021000 .word 0x40021000 - 80017f4: 48000800 .word 0x48000800 - -080017f8 : -/** - * @brief This function is executed in case of error occurrence. - * @retval None + HAL_NVIC_SetPriority(EXTI1_IRQn, 1, 0); + 80014a2: 2200 movs r2, #0 + 80014a4: 2101 movs r1, #1 + 80014a6: 2007 movs r0, #7 + 80014a8: f005 fa7d bl 80069a6 + HAL_NVIC_EnableIRQ(EXTI1_IRQn); + 80014ac: 2007 movs r0, #7 + 80014ae: f005 fa96 bl 80069de + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 1, 0); + 80014b2: 2200 movs r2, #0 + 80014b4: 2101 movs r1, #1 + 80014b6: 2017 movs r0, #23 + 80014b8: f005 fa75 bl 80069a6 + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + 80014bc: 2017 movs r0, #23 + 80014be: f005 fa8e bl 80069de + +} + 80014c2: bf00 nop + 80014c4: 3720 adds r7, #32 + 80014c6: 46bd mov sp, r7 + 80014c8: bd80 pop {r7, pc} + 80014ca: bf00 nop + 80014cc: 40021000 .word 0x40021000 + 80014d0: 48000400 .word 0x48000400 + +080014d4 : +I2C_HandleTypeDef hi2c1; +I2C_HandleTypeDef hi2c3; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + 80014d4: b580 push {r7, lr} + 80014d6: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 80014d8: 4b1b ldr r3, [pc, #108] ; (8001548 ) + 80014da: 4a1c ldr r2, [pc, #112] ; (800154c ) + 80014dc: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x00202538; + 80014de: 4b1a ldr r3, [pc, #104] ; (8001548 ) + 80014e0: 4a1b ldr r2, [pc, #108] ; (8001550 ) + 80014e2: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 80014e4: 4b18 ldr r3, [pc, #96] ; (8001548 ) + 80014e6: 2200 movs r2, #0 + 80014e8: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 80014ea: 4b17 ldr r3, [pc, #92] ; (8001548 ) + 80014ec: 2201 movs r2, #1 + 80014ee: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 80014f0: 4b15 ldr r3, [pc, #84] ; (8001548 ) + 80014f2: 2200 movs r2, #0 + 80014f4: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 80014f6: 4b14 ldr r3, [pc, #80] ; (8001548 ) + 80014f8: 2200 movs r2, #0 + 80014fa: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 80014fc: 4b12 ldr r3, [pc, #72] ; (8001548 ) + 80014fe: 2200 movs r2, #0 + 8001500: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001502: 4b11 ldr r3, [pc, #68] ; (8001548 ) + 8001504: 2200 movs r2, #0 + 8001506: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001508: 4b0f ldr r3, [pc, #60] ; (8001548 ) + 800150a: 2200 movs r2, #0 + 800150c: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800150e: 480e ldr r0, [pc, #56] ; (8001548 ) + 8001510: f005 fe9c bl 800724c + 8001514: 4603 mov r3, r0 + 8001516: 2b00 cmp r3, #0 + 8001518: d001 beq.n 800151e + { + Error_Handler(); + 800151a: f000 fa6a bl 80019f2 + } + + /** Configure Analogue filter */ -void Error_Handler(void) -{ - 80017f8: b480 push {r7} - 80017fa: af00 add r7, sp, #0 - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); - 80017fc: b672 cpsid i -} - 80017fe: bf00 nop - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - 8001800: e7fe b.n 8001800 + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800151e: 2100 movs r1, #0 + 8001520: 4809 ldr r0, [pc, #36] ; (8001548 ) + 8001522: f006 faa7 bl 8007a74 + 8001526: 4603 mov r3, r0 + 8001528: 2b00 cmp r3, #0 + 800152a: d001 beq.n 8001530 + { + Error_Handler(); + 800152c: f000 fa61 bl 80019f2 + } -08001802 : -//on a une fonction de decodage par typme de trame interressante, puis une fonction nmea_parse servant à mettre à jour la structure de donnée avec lesdonnées presentes dans le databuffer, qui lui se met à jour tout seul. + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 8001530: 2100 movs r1, #0 + 8001532: 4805 ldr r0, [pc, #20] ; (8001548 ) + 8001534: f006 fae9 bl 8007b0a + 8001538: 4603 mov r3, r0 + 800153a: 2b00 cmp r3, #0 + 800153c: d001 beq.n 8001542 + { + Error_Handler(); + 800153e: f000 fa58 bl 80019f2 + } + /* USER CODE BEGIN I2C1_Init 2 */ -char *data[15]; + /* USER CODE END I2C1_Init 2 */ -int gps_checksum(char *nmea_data) +} + 8001542: bf00 nop + 8001544: bd80 pop {r7, pc} + 8001546: bf00 nop + 8001548: 200003c0 .word 0x200003c0 + 800154c: 40005400 .word 0x40005400 + 8001550: 00202538 .word 0x00202538 + +08001554 : +/* I2C3 init function */ +void MX_I2C3_Init(void) { - 8001802: b580 push {r7, lr} - 8001804: b086 sub sp, #24 - 8001806: af00 add r7, sp, #0 - 8001808: 6078 str r0, [r7, #4] - //if you point a string with less than 5 characters the function will read outside of scope and crash the mcu. - if(strlen(nmea_data) < 5) return 0; - 800180a: 6878 ldr r0, [r7, #4] - 800180c: f7fe fd30 bl 8000270 - 8001810: 4603 mov r3, r0 - 8001812: 2b04 cmp r3, #4 - 8001814: d801 bhi.n 800181a - 8001816: 2300 movs r3, #0 - 8001818: e038 b.n 800188c - char recv_crc[2]; - recv_crc[0] = nmea_data[strlen(nmea_data) - 4]; - 800181a: 6878 ldr r0, [r7, #4] - 800181c: f7fe fd28 bl 8000270 - 8001820: 4603 mov r3, r0 - 8001822: 3b04 subs r3, #4 - 8001824: 687a ldr r2, [r7, #4] - 8001826: 4413 add r3, r2 - 8001828: 781b ldrb r3, [r3, #0] - 800182a: 723b strb r3, [r7, #8] - recv_crc[1] = nmea_data[strlen(nmea_data) - 3]; - 800182c: 6878 ldr r0, [r7, #4] - 800182e: f7fe fd1f bl 8000270 - 8001832: 4603 mov r3, r0 - 8001834: 3b03 subs r3, #3 - 8001836: 687a ldr r2, [r7, #4] - 8001838: 4413 add r3, r2 - 800183a: 781b ldrb r3, [r3, #0] - 800183c: 727b strb r3, [r7, #9] - int crc = 0; - 800183e: 2300 movs r3, #0 - 8001840: 617b str r3, [r7, #20] - int i; + 8001554: b580 push {r7, lr} + 8001556: af00 add r7, sp, #0 + /* USER CODE END I2C3_Init 0 */ - //exclude the CRLF plus CRC with an * from the end - for (i = 0; i < strlen(nmea_data) - 5; i ++) { - 8001842: 2300 movs r3, #0 - 8001844: 613b str r3, [r7, #16] - 8001846: e00a b.n 800185e - crc ^= nmea_data[i]; - 8001848: 693b ldr r3, [r7, #16] - 800184a: 687a ldr r2, [r7, #4] - 800184c: 4413 add r3, r2 - 800184e: 781b ldrb r3, [r3, #0] - 8001850: 461a mov r2, r3 - 8001852: 697b ldr r3, [r7, #20] - 8001854: 4053 eors r3, r2 - 8001856: 617b str r3, [r7, #20] - for (i = 0; i < strlen(nmea_data) - 5; i ++) { - 8001858: 693b ldr r3, [r7, #16] - 800185a: 3301 adds r3, #1 - 800185c: 613b str r3, [r7, #16] - 800185e: 6878 ldr r0, [r7, #4] - 8001860: f7fe fd06 bl 8000270 - 8001864: 4603 mov r3, r0 - 8001866: 1f5a subs r2, r3, #5 - 8001868: 693b ldr r3, [r7, #16] - 800186a: 429a cmp r2, r3 - 800186c: d8ec bhi.n 8001848 - } - int receivedHash = strtol(recv_crc, NULL, 16); - 800186e: f107 0308 add.w r3, r7, #8 - 8001872: 2210 movs r2, #16 - 8001874: 2100 movs r1, #0 - 8001876: 4618 mov r0, r3 - 8001878: f010 f916 bl 8011aa8 - 800187c: 60f8 str r0, [r7, #12] - if (crc == receivedHash) { - 800187e: 697a ldr r2, [r7, #20] - 8001880: 68fb ldr r3, [r7, #12] - 8001882: 429a cmp r2, r3 - 8001884: d101 bne.n 800188a - return 1; - 8001886: 2301 movs r3, #1 - 8001888: e000 b.n 800188c - } - else{ - return 0; - 800188a: 2300 movs r3, #0 - } -} - 800188c: 4618 mov r0, r3 - 800188e: 3718 adds r7, #24 - 8001890: 46bd mov sp, r7 - 8001892: bd80 pop {r7, pc} + /* USER CODE BEGIN I2C3_Init 1 */ -08001894 : + /* USER CODE END I2C3_Init 1 */ + hi2c3.Instance = I2C3; + 8001558: 4b1d ldr r3, [pc, #116] ; (80015d0 ) + 800155a: 4a1e ldr r2, [pc, #120] ; (80015d4 ) + 800155c: 601a str r2, [r3, #0] + hi2c3.Init.Timing = 0x00100618; + 800155e: 4b1c ldr r3, [pc, #112] ; (80015d0 ) + 8001560: 4a1d ldr r2, [pc, #116] ; (80015d8 ) + 8001562: 605a str r2, [r3, #4] + hi2c3.Init.OwnAddress1 = 0; + 8001564: 4b1a ldr r3, [pc, #104] ; (80015d0 ) + 8001566: 2200 movs r2, #0 + 8001568: 609a str r2, [r3, #8] + hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 800156a: 4b19 ldr r3, [pc, #100] ; (80015d0 ) + 800156c: 2201 movs r2, #1 + 800156e: 60da str r2, [r3, #12] + hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001570: 4b17 ldr r3, [pc, #92] ; (80015d0 ) + 8001572: 2200 movs r2, #0 + 8001574: 611a str r2, [r3, #16] + hi2c3.Init.OwnAddress2 = 0; + 8001576: 4b16 ldr r3, [pc, #88] ; (80015d0 ) + 8001578: 2200 movs r2, #0 + 800157a: 615a str r2, [r3, #20] + hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 800157c: 4b14 ldr r3, [pc, #80] ; (80015d0 ) + 800157e: 2200 movs r2, #0 + 8001580: 619a str r2, [r3, #24] + hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001582: 4b13 ldr r3, [pc, #76] ; (80015d0 ) + 8001584: 2200 movs r2, #0 + 8001586: 61da str r2, [r3, #28] + hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001588: 4b11 ldr r3, [pc, #68] ; (80015d0 ) + 800158a: 2200 movs r2, #0 + 800158c: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c3) != HAL_OK) + 800158e: 4810 ldr r0, [pc, #64] ; (80015d0 ) + 8001590: f005 fe5c bl 800724c + 8001594: 4603 mov r3, r0 + 8001596: 2b00 cmp r3, #0 + 8001598: d001 beq.n 800159e + { + Error_Handler(); + 800159a: f000 fa2a bl 80019f2 + } -int nmea_GPGGA(GPS *gps_data, char*inputString){ - 8001894: b590 push {r4, r7, lr} - 8001896: b0b7 sub sp, #220 ; 0xdc - 8001898: af00 add r7, sp, #0 - 800189a: 6078 str r0, [r7, #4] - 800189c: 6039 str r1, [r7, #0] - char *values[25]; - int counter = 0; - 800189e: 2300 movs r3, #0 - 80018a0: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 - memset(values, 0, sizeof(values)); - 80018a4: f107 0320 add.w r3, r7, #32 - 80018a8: 2264 movs r2, #100 ; 0x64 - 80018aa: 2100 movs r1, #0 - 80018ac: 4618 mov r0, r3 - 80018ae: f011 f8d4 bl 8012a5a - char *marker = strtok(inputString, ","); - 80018b2: 49c2 ldr r1, [pc, #776] ; (8001bbc ) - 80018b4: 6838 ldr r0, [r7, #0] - 80018b6: f011 f8eb bl 8012a90 - 80018ba: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0 - while (marker != NULL) { - 80018be: e027 b.n 8001910 - values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! - 80018c0: f8d7 00d0 ldr.w r0, [r7, #208] ; 0xd0 - 80018c4: f7fe fcd4 bl 8000270 - 80018c8: 4603 mov r3, r0 - 80018ca: 1c5a adds r2, r3, #1 - 80018cc: f8d7 40d4 ldr.w r4, [r7, #212] ; 0xd4 - 80018d0: 1c63 adds r3, r4, #1 - 80018d2: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 - 80018d6: 4610 mov r0, r2 - 80018d8: f00f f92c bl 8010b34 - 80018dc: 4603 mov r3, r0 - 80018de: 461a mov r2, r3 - 80018e0: 00a3 lsls r3, r4, #2 - 80018e2: 33d8 adds r3, #216 ; 0xd8 - 80018e4: 443b add r3, r7 - 80018e6: f843 2cb8 str.w r2, [r3, #-184] - strcpy(values[counter - 1], marker); - 80018ea: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 80018ee: 3b01 subs r3, #1 - 80018f0: 009b lsls r3, r3, #2 - 80018f2: 33d8 adds r3, #216 ; 0xd8 - 80018f4: 443b add r3, r7 - 80018f6: f853 3cb8 ldr.w r3, [r3, #-184] - 80018fa: f8d7 10d0 ldr.w r1, [r7, #208] ; 0xd0 - 80018fe: 4618 mov r0, r3 - 8001900: f011 f9bf bl 8012c82 - marker = strtok(NULL, ","); - 8001904: 49ad ldr r1, [pc, #692] ; (8001bbc ) - 8001906: 2000 movs r0, #0 - 8001908: f011 f8c2 bl 8012a90 - 800190c: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0 - while (marker != NULL) { - 8001910: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0 - 8001914: 2b00 cmp r3, #0 - 8001916: d1d3 bne.n 80018c0 - } - char lonSide = values[5][0]; - 8001918: 6b7b ldr r3, [r7, #52] ; 0x34 - 800191a: 781b ldrb r3, [r3, #0] - 800191c: f887 30b7 strb.w r3, [r7, #183] ; 0xb7 - char latSide = values[3][0]; - 8001920: 6afb ldr r3, [r7, #44] ; 0x2c - 8001922: 781b ldrb r3, [r3, #0] - 8001924: f887 30b6 strb.w r3, [r7, #182] ; 0xb6 - strcpy(gps_data->lastMeasure, values[1]); - 8001928: 687b ldr r3, [r7, #4] - 800192a: 332c adds r3, #44 ; 0x2c - 800192c: 6a7a ldr r2, [r7, #36] ; 0x24 - 800192e: 4611 mov r1, r2 - 8001930: 4618 mov r0, r3 - 8001932: f011 f9a6 bl 8012c82 - if(latSide == 'S' || latSide == 'N'){ - 8001936: f897 30b6 ldrb.w r3, [r7, #182] ; 0xb6 - 800193a: 2b53 cmp r3, #83 ; 0x53 - 800193c: d004 beq.n 8001948 - 800193e: f897 30b6 ldrb.w r3, [r7, #182] ; 0xb6 - 8001942: 2b4e cmp r3, #78 ; 0x4e - 8001944: f040 8159 bne.w 8001bfa - char lat_d[2]; - char lat_m[7]; - for (int z = 0; z < 2; z++) lat_d[z] = values[2][z]; - 8001948: 2300 movs r3, #0 - 800194a: f8c7 30cc str.w r3, [r7, #204] ; 0xcc - 800194e: e010 b.n 8001972 - 8001950: 6aba ldr r2, [r7, #40] ; 0x28 - 8001952: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 8001956: 4413 add r3, r2 - 8001958: 7819 ldrb r1, [r3, #0] - 800195a: f107 021c add.w r2, r7, #28 - 800195e: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 8001962: 4413 add r3, r2 - 8001964: 460a mov r2, r1 - 8001966: 701a strb r2, [r3, #0] - 8001968: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 800196c: 3301 adds r3, #1 - 800196e: f8c7 30cc str.w r3, [r7, #204] ; 0xcc - 8001972: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 8001976: 2b01 cmp r3, #1 - 8001978: ddea ble.n 8001950 - for (int z = 0; z < 6; z++) lat_m[z] = values[2][z + 2]; - 800197a: 2300 movs r3, #0 - 800197c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 - 8001980: e011 b.n 80019a6 - 8001982: 6aba ldr r2, [r7, #40] ; 0x28 - 8001984: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 8001988: 3302 adds r3, #2 - 800198a: 4413 add r3, r2 - 800198c: 7819 ldrb r1, [r3, #0] - 800198e: f107 0214 add.w r2, r7, #20 - 8001992: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 8001996: 4413 add r3, r2 - 8001998: 460a mov r2, r1 - 800199a: 701a strb r2, [r3, #0] - 800199c: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 80019a0: 3301 adds r3, #1 - 80019a2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 - 80019a6: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 80019aa: 2b05 cmp r3, #5 - 80019ac: dde9 ble.n 8001982 + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800159e: 2100 movs r1, #0 + 80015a0: 480b ldr r0, [pc, #44] ; (80015d0 ) + 80015a2: f006 fa67 bl 8007a74 + 80015a6: 4603 mov r3, r0 + 80015a8: 2b00 cmp r3, #0 + 80015aa: d001 beq.n 80015b0 + { + Error_Handler(); + 80015ac: f000 fa21 bl 80019f2 + } - int lat_deg_strtol = strtol(lat_d, NULL, 10); - 80019ae: f107 031c add.w r3, r7, #28 - 80019b2: 220a movs r2, #10 - 80019b4: 2100 movs r1, #0 - 80019b6: 4618 mov r0, r3 - 80019b8: f010 f876 bl 8011aa8 - 80019bc: f8c7 00b0 str.w r0, [r7, #176] ; 0xb0 - float lat_min_strtof = strtof(lat_m, NULL); - 80019c0: f107 0314 add.w r3, r7, #20 - 80019c4: 2100 movs r1, #0 - 80019c6: 4618 mov r0, r3 - 80019c8: f00f ff84 bl 80118d4 - 80019cc: ed87 0a2b vstr s0, [r7, #172] ; 0xac - double lat_deg = lat_deg_strtol + lat_min_strtof / 60; - 80019d0: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 - 80019d4: ee07 3a90 vmov s15, r3 - 80019d8: eeb8 7ae7 vcvt.f32.s32 s14, s15 - 80019dc: edd7 6a2b vldr s13, [r7, #172] ; 0xac - 80019e0: ed9f 6a77 vldr s12, [pc, #476] ; 8001bc0 - 80019e4: eec6 7a86 vdiv.f32 s15, s13, s12 - 80019e8: ee77 7a27 vadd.f32 s15, s14, s15 - 80019ec: ee17 0a90 vmov r0, s15 - 80019f0: f7fe fdaa bl 8000548 <__aeabi_f2d> - 80019f4: 4602 mov r2, r0 - 80019f6: 460b mov r3, r1 - 80019f8: e9c7 2328 strd r2, r3, [r7, #160] ; 0xa0 + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) + 80015b0: 2100 movs r1, #0 + 80015b2: 4807 ldr r0, [pc, #28] ; (80015d0 ) + 80015b4: f006 faa9 bl 8007b0a + 80015b8: 4603 mov r3, r0 + 80015ba: 2b00 cmp r3, #0 + 80015bc: d001 beq.n 80015c2 + { + Error_Handler(); + 80015be: f000 fa18 bl 80019f2 + } - char lon_d[3]; - char lon_m[7]; + /** I2C Fast mode Plus enable + */ + HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3); + 80015c2: f44f 0080 mov.w r0, #4194304 ; 0x400000 + 80015c6: f006 faed bl 8007ba4 + /* USER CODE BEGIN I2C3_Init 2 */ - for (int z = 0; z < 3; z++) lon_d[z] = values[4][z]; - 80019fc: 2300 movs r3, #0 - 80019fe: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 - 8001a02: e010 b.n 8001a26 - 8001a04: 6b3a ldr r2, [r7, #48] ; 0x30 - 8001a06: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 8001a0a: 4413 add r3, r2 - 8001a0c: 7819 ldrb r1, [r3, #0] - 8001a0e: f107 0210 add.w r2, r7, #16 - 8001a12: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 8001a16: 4413 add r3, r2 - 8001a18: 460a mov r2, r1 - 8001a1a: 701a strb r2, [r3, #0] - 8001a1c: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 8001a20: 3301 adds r3, #1 - 8001a22: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 - 8001a26: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 8001a2a: 2b02 cmp r3, #2 - 8001a2c: ddea ble.n 8001a04 - for (int z = 0; z < 6; z++) lon_m[z] = values[4][z + 3]; - 8001a2e: 2300 movs r3, #0 - 8001a30: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 - 8001a34: e011 b.n 8001a5a - 8001a36: 6b3a ldr r2, [r7, #48] ; 0x30 - 8001a38: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8001a3c: 3303 adds r3, #3 - 8001a3e: 4413 add r3, r2 - 8001a40: 7819 ldrb r1, [r3, #0] - 8001a42: f107 0208 add.w r2, r7, #8 - 8001a46: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8001a4a: 4413 add r3, r2 - 8001a4c: 460a mov r2, r1 - 8001a4e: 701a strb r2, [r3, #0] - 8001a50: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8001a54: 3301 adds r3, #1 - 8001a56: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 - 8001a5a: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8001a5e: 2b05 cmp r3, #5 - 8001a60: dde9 ble.n 8001a36 + /* USER CODE END I2C3_Init 2 */ - int lon_deg_strtol = strtol(lon_d, NULL, 10); - 8001a62: f107 0310 add.w r3, r7, #16 - 8001a66: 220a movs r2, #10 - 8001a68: 2100 movs r1, #0 - 8001a6a: 4618 mov r0, r3 - 8001a6c: f010 f81c bl 8011aa8 - 8001a70: f8c7 009c str.w r0, [r7, #156] ; 0x9c - float lon_min_strtof = strtof(lon_m, NULL); - 8001a74: f107 0308 add.w r3, r7, #8 - 8001a78: 2100 movs r1, #0 - 8001a7a: 4618 mov r0, r3 - 8001a7c: f00f ff2a bl 80118d4 - 8001a80: ed87 0a26 vstr s0, [r7, #152] ; 0x98 - double lon_deg = lon_deg_strtol + lon_min_strtof / 60; - 8001a84: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c - 8001a88: ee07 3a90 vmov s15, r3 - 8001a8c: eeb8 7ae7 vcvt.f32.s32 s14, s15 - 8001a90: edd7 6a26 vldr s13, [r7, #152] ; 0x98 - 8001a94: ed9f 6a4a vldr s12, [pc, #296] ; 8001bc0 - 8001a98: eec6 7a86 vdiv.f32 s15, s13, s12 - 8001a9c: ee77 7a27 vadd.f32 s15, s14, s15 - 8001aa0: ee17 0a90 vmov r0, s15 - 8001aa4: f7fe fd50 bl 8000548 <__aeabi_f2d> - 8001aa8: 4602 mov r2, r0 - 8001aaa: 460b mov r3, r1 - 8001aac: e9c7 2324 strd r2, r3, [r7, #144] ; 0x90 +} + 80015ca: bf00 nop + 80015cc: bd80 pop {r7, pc} + 80015ce: bf00 nop + 80015d0: 20000414 .word 0x20000414 + 80015d4: 40005c00 .word 0x40005c00 + 80015d8: 00100618 .word 0x00100618 - if(lat_deg!=0 && lon_deg!=0 && lat_deg<90 && lon_deg<180){ - 8001ab0: f04f 0200 mov.w r2, #0 - 8001ab4: f04f 0300 mov.w r3, #0 - 8001ab8: e9d7 0128 ldrd r0, r1, [r7, #160] ; 0xa0 - 8001abc: f7ff f804 bl 8000ac8 <__aeabi_dcmpeq> - 8001ac0: 4603 mov r3, r0 - 8001ac2: 2b00 cmp r3, #0 - 8001ac4: d176 bne.n 8001bb4 - 8001ac6: f04f 0200 mov.w r2, #0 - 8001aca: f04f 0300 mov.w r3, #0 - 8001ace: e9d7 0124 ldrd r0, r1, [r7, #144] ; 0x90 - 8001ad2: f7fe fff9 bl 8000ac8 <__aeabi_dcmpeq> - 8001ad6: 4603 mov r3, r0 - 8001ad8: 2b00 cmp r3, #0 - 8001ada: d16b bne.n 8001bb4 - 8001adc: f04f 0200 mov.w r2, #0 - 8001ae0: 4b38 ldr r3, [pc, #224] ; (8001bc4 ) - 8001ae2: e9d7 0128 ldrd r0, r1, [r7, #160] ; 0xa0 - 8001ae6: f7fe fff9 bl 8000adc <__aeabi_dcmplt> - 8001aea: 4603 mov r3, r0 - 8001aec: 2b00 cmp r3, #0 - 8001aee: d061 beq.n 8001bb4 - 8001af0: f04f 0200 mov.w r2, #0 - 8001af4: 4b34 ldr r3, [pc, #208] ; (8001bc8 ) - 8001af6: e9d7 0124 ldrd r0, r1, [r7, #144] ; 0x90 - 8001afa: f7fe ffef bl 8000adc <__aeabi_dcmplt> - 8001afe: 4603 mov r3, r0 - 8001b00: 2b00 cmp r3, #0 - 8001b02: d057 beq.n 8001bb4 - gps_data->latitude = lat_deg; - 8001b04: 6879 ldr r1, [r7, #4] - 8001b06: e9d7 2328 ldrd r2, r3, [r7, #160] ; 0xa0 - 8001b0a: e9c1 2300 strd r2, r3, [r1] - gps_data->latSide = latSide; - 8001b0e: 687b ldr r3, [r7, #4] - 8001b10: f897 20b6 ldrb.w r2, [r7, #182] ; 0xb6 - 8001b14: 721a strb r2, [r3, #8] - gps_data->longitude = lon_deg; - 8001b16: 6879 ldr r1, [r7, #4] - 8001b18: e9d7 2324 ldrd r2, r3, [r7, #144] ; 0x90 - 8001b1c: e9c1 2304 strd r2, r3, [r1, #16] - gps_data->lonSide = lonSide; - 8001b20: 687b ldr r3, [r7, #4] - 8001b22: f897 20b7 ldrb.w r2, [r7, #183] ; 0xb7 - 8001b26: 761a strb r2, [r3, #24] - float altitude = strtof(values[9], NULL); - 8001b28: 6c7b ldr r3, [r7, #68] ; 0x44 - 8001b2a: 2100 movs r1, #0 - 8001b2c: 4618 mov r0, r3 - 8001b2e: f00f fed1 bl 80118d4 - 8001b32: ed87 0a23 vstr s0, [r7, #140] ; 0x8c - gps_data->altitude = altitude!=0 ? altitude : gps_data->altitude; - 8001b36: edd7 7a23 vldr s15, [r7, #140] ; 0x8c - 8001b3a: eef5 7a40 vcmp.f32 s15, #0.0 - 8001b3e: eef1 fa10 vmrs APSR_nzcv, fpscr - 8001b42: d102 bne.n 8001b4a - 8001b44: 687b ldr r3, [r7, #4] - 8001b46: 69db ldr r3, [r3, #28] - 8001b48: e001 b.n 8001b4e - 8001b4a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8001b4e: 687a ldr r2, [r7, #4] - 8001b50: 61d3 str r3, [r2, #28] - gps_data->satelliteCount = strtol(values[7], NULL, 10); - 8001b52: 6bfb ldr r3, [r7, #60] ; 0x3c - 8001b54: 220a movs r2, #10 - 8001b56: 2100 movs r1, #0 - 8001b58: 4618 mov r0, r3 - 8001b5a: f00f ffa5 bl 8011aa8 - 8001b5e: 4602 mov r2, r0 - 8001b60: 687b ldr r3, [r7, #4] - 8001b62: 625a str r2, [r3, #36] ; 0x24 +080015dc : - int fixQuality = strtol(values[6], NULL, 10); - 8001b64: 6bbb ldr r3, [r7, #56] ; 0x38 - 8001b66: 220a movs r2, #10 - 8001b68: 2100 movs r1, #0 - 8001b6a: 4618 mov r0, r3 - 8001b6c: f00f ff9c bl 8011aa8 - 8001b70: f8c7 0088 str.w r0, [r7, #136] ; 0x88 - gps_data->fix = fixQuality > 0 ? 1 : 0; - 8001b74: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 - 8001b78: 2b00 cmp r3, #0 - 8001b7a: bfcc ite gt - 8001b7c: 2301 movgt r3, #1 - 8001b7e: 2300 movle r3, #0 - 8001b80: b2db uxtb r3, r3 - 8001b82: 461a mov r2, r3 - 8001b84: 687b ldr r3, [r7, #4] - 8001b86: 629a str r2, [r3, #40] ; 0x28 +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + 80015dc: b580 push {r7, lr} + 80015de: b0a2 sub sp, #136 ; 0x88 + 80015e0: af00 add r7, sp, #0 + 80015e2: 6078 str r0, [r7, #4] - float hdop = strtof(values[8], NULL); - 8001b88: 6c3b ldr r3, [r7, #64] ; 0x40 - 8001b8a: 2100 movs r1, #0 - 8001b8c: 4618 mov r0, r3 - 8001b8e: f00f fea1 bl 80118d4 - 8001b92: ed87 0a21 vstr s0, [r7, #132] ; 0x84 - gps_data->hdop = hdop!=0 ? hdop : gps_data->hdop; - 8001b96: edd7 7a21 vldr s15, [r7, #132] ; 0x84 - 8001b9a: eef5 7a40 vcmp.f32 s15, #0.0 - 8001b9e: eef1 fa10 vmrs APSR_nzcv, fpscr - 8001ba2: d102 bne.n 8001baa - 8001ba4: 687b ldr r3, [r7, #4] - 8001ba6: 6a1b ldr r3, [r3, #32] - 8001ba8: e001 b.n 8001bae - 8001baa: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 8001bae: 687a ldr r2, [r7, #4] - 8001bb0: 6213 str r3, [r2, #32] - if(lat_deg!=0 && lon_deg!=0 && lat_deg<90 && lon_deg<180){ - 8001bb2: e022 b.n 8001bfa - } - else { - for(int i=0; i - 8001bbc: 080168d8 .word 0x080168d8 - 8001bc0: 42700000 .word 0x42700000 - 8001bc4: 40568000 .word 0x40568000 - 8001bc8: 40668000 .word 0x40668000 - 8001bcc: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 8001bd0: 009b lsls r3, r3, #2 - 8001bd2: 33d8 adds r3, #216 ; 0xd8 - 8001bd4: 443b add r3, r7 - 8001bd6: f853 3cb8 ldr.w r3, [r3, #-184] - 8001bda: 4618 mov r0, r3 - 8001bdc: f00e ffb2 bl 8010b44 - 8001be0: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 8001be4: 3301 adds r3, #1 - 8001be6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc - 8001bea: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc - 8001bee: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 8001bf2: 429a cmp r2, r3 - 8001bf4: dbea blt.n 8001bcc - return 0; - 8001bf6: 2300 movs r3, #0 - 8001bf8: e019 b.n 8001c2e - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80015e4: f107 0374 add.w r3, r7, #116 ; 0x74 + 80015e8: 2200 movs r2, #0 + 80015ea: 601a str r2, [r3, #0] + 80015ec: 605a str r2, [r3, #4] + 80015ee: 609a str r2, [r3, #8] + 80015f0: 60da str r2, [r3, #12] + 80015f2: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 80015f4: f107 0320 add.w r3, r7, #32 + 80015f8: 2254 movs r2, #84 ; 0x54 + 80015fa: 2100 movs r1, #0 + 80015fc: 4618 mov r0, r3 + 80015fe: f013 fc84 bl 8014f0a + if(i2cHandle->Instance==I2C1) + 8001602: 687b ldr r3, [r7, #4] + 8001604: 681b ldr r3, [r3, #0] + 8001606: 4a50 ldr r2, [pc, #320] ; (8001748 ) + 8001608: 4293 cmp r3, r2 + 800160a: d13a bne.n 8001682 + + /* USER CODE END I2C1_MspInit 0 */ + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; + 800160c: 2340 movs r3, #64 ; 0x40 + 800160e: 623b str r3, [r7, #32] + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 8001610: 2300 movs r3, #0 + 8001612: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8001614: f107 0320 add.w r3, r7, #32 + 8001618: 4618 mov r0, r3 + 800161a: f008 ff0d bl 800a438 + 800161e: 4603 mov r3, r0 + 8001620: 2b00 cmp r3, #0 + 8001622: d001 beq.n 8001628 + { + Error_Handler(); + 8001624: f000 f9e5 bl 80019f2 } - for(int i=0; i - 8001c02: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 8001c06: 009b lsls r3, r3, #2 - 8001c08: 33d8 adds r3, #216 ; 0xd8 - 8001c0a: 443b add r3, r7 - 8001c0c: f853 3cb8 ldr.w r3, [r3, #-184] - 8001c10: 4618 mov r0, r3 - 8001c12: f00e ff97 bl 8010b44 - 8001c16: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 8001c1a: 3301 adds r3, #1 - 8001c1c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 - 8001c20: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8 - 8001c24: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 8001c28: 429a cmp r2, r3 - 8001c2a: dbea blt.n 8001c02 - return 1; - 8001c2c: 2301 movs r3, #1 -} - 8001c2e: 4618 mov r0, r3 - 8001c30: 37dc adds r7, #220 ; 0xdc - 8001c32: 46bd mov sp, r7 - 8001c34: bd90 pop {r4, r7, pc} - 8001c36: bf00 nop + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001628: 4b48 ldr r3, [pc, #288] ; (800174c ) + 800162a: 6cdb ldr r3, [r3, #76] ; 0x4c + 800162c: 4a47 ldr r2, [pc, #284] ; (800174c ) + 800162e: f043 0301 orr.w r3, r3, #1 + 8001632: 64d3 str r3, [r2, #76] ; 0x4c + 8001634: 4b45 ldr r3, [pc, #276] ; (800174c ) + 8001636: 6cdb ldr r3, [r3, #76] ; 0x4c + 8001638: f003 0301 and.w r3, r3, #1 + 800163c: 61fb str r3, [r7, #28] + 800163e: 69fb ldr r3, [r7, #28] + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 8001640: f44f 63c0 mov.w r3, #1536 ; 0x600 + 8001644: 677b str r3, [r7, #116] ; 0x74 + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001646: 2312 movs r3, #18 + 8001648: 67bb str r3, [r7, #120] ; 0x78 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800164a: 2300 movs r3, #0 + 800164c: 67fb str r3, [r7, #124] ; 0x7c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800164e: 2303 movs r3, #3 + 8001650: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8001654: 2304 movs r3, #4 + 8001656: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800165a: f107 0374 add.w r3, r7, #116 ; 0x74 + 800165e: 4619 mov r1, r3 + 8001660: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001664: f005 fc58 bl 8006f18 + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8001668: 4b38 ldr r3, [pc, #224] ; (800174c ) + 800166a: 6d9b ldr r3, [r3, #88] ; 0x58 + 800166c: 4a37 ldr r2, [pc, #220] ; (800174c ) + 800166e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8001672: 6593 str r3, [r2, #88] ; 0x58 + 8001674: 4b35 ldr r3, [pc, #212] ; (800174c ) + 8001676: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001678: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800167c: 61bb str r3, [r7, #24] + 800167e: 69bb ldr r3, [r7, #24] + __HAL_RCC_I2C3_CLK_ENABLE(); + /* USER CODE BEGIN I2C3_MspInit 1 */ -08001c38 : - - -int nmea_GPGSA(GPS *gps_data, char*inputString){ - 8001c38: b590 push {r4, r7, lr} - 8001c3a: b0a3 sub sp, #140 ; 0x8c - 8001c3c: af00 add r7, sp, #0 - 8001c3e: 6078 str r0, [r7, #4] - 8001c40: 6039 str r1, [r7, #0] - char *values[25]; - int counter = 0; - 8001c42: 2300 movs r3, #0 - 8001c44: f8c7 3084 str.w r3, [r7, #132] ; 0x84 - memset(values, 0, sizeof(values)); - 8001c48: f107 030c add.w r3, r7, #12 - 8001c4c: 2264 movs r2, #100 ; 0x64 - 8001c4e: 2100 movs r1, #0 - 8001c50: 4618 mov r0, r3 - 8001c52: f010 ff02 bl 8012a5a - char *marker = strtok(inputString, ","); - 8001c56: 493b ldr r1, [pc, #236] ; (8001d44 ) - 8001c58: 6838 ldr r0, [r7, #0] - 8001c5a: f010 ff19 bl 8012a90 - 8001c5e: f8c7 0080 str.w r0, [r7, #128] ; 0x80 - while (marker != NULL) { - 8001c62: e027 b.n 8001cb4 - values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! - 8001c64: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8001c68: f7fe fb02 bl 8000270 - 8001c6c: 4603 mov r3, r0 - 8001c6e: 1c5a adds r2, r3, #1 - 8001c70: f8d7 4084 ldr.w r4, [r7, #132] ; 0x84 - 8001c74: 1c63 adds r3, r4, #1 - 8001c76: f8c7 3084 str.w r3, [r7, #132] ; 0x84 - 8001c7a: 4610 mov r0, r2 - 8001c7c: f00e ff5a bl 8010b34 - 8001c80: 4603 mov r3, r0 - 8001c82: 461a mov r2, r3 - 8001c84: 00a3 lsls r3, r4, #2 - 8001c86: 3388 adds r3, #136 ; 0x88 - 8001c88: 443b add r3, r7 - 8001c8a: f843 2c7c str.w r2, [r3, #-124] - strcpy(values[counter - 1], marker); - 8001c8e: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 8001c92: 3b01 subs r3, #1 - 8001c94: 009b lsls r3, r3, #2 - 8001c96: 3388 adds r3, #136 ; 0x88 - 8001c98: 443b add r3, r7 - 8001c9a: f853 3c7c ldr.w r3, [r3, #-124] - 8001c9e: f8d7 1080 ldr.w r1, [r7, #128] ; 0x80 - 8001ca2: 4618 mov r0, r3 - 8001ca4: f010 ffed bl 8012c82 - marker = strtok(NULL, ","); - 8001ca8: 4926 ldr r1, [pc, #152] ; (8001d44 ) - 8001caa: 2000 movs r0, #0 - 8001cac: f010 fef0 bl 8012a90 - 8001cb0: f8c7 0080 str.w r0, [r7, #128] ; 0x80 - while (marker != NULL) { - 8001cb4: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 8001cb8: 2b00 cmp r3, #0 - 8001cba: d1d3 bne.n 8001c64 - } - int fix = strtol(values[2], NULL, 10); - 8001cbc: 697b ldr r3, [r7, #20] - 8001cbe: 220a movs r2, #10 - 8001cc0: 2100 movs r1, #0 - 8001cc2: 4618 mov r0, r3 - 8001cc4: f00f fef0 bl 8011aa8 - 8001cc8: 6738 str r0, [r7, #112] ; 0x70 - gps_data->fix = fix > 1 ? 1 : 0; - 8001cca: 6f3b ldr r3, [r7, #112] ; 0x70 - 8001ccc: 2b01 cmp r3, #1 - 8001cce: bfcc ite gt - 8001cd0: 2301 movgt r3, #1 - 8001cd2: 2300 movle r3, #0 - 8001cd4: b2db uxtb r3, r3 - 8001cd6: 461a mov r2, r3 - 8001cd8: 687b ldr r3, [r7, #4] - 8001cda: 629a str r2, [r3, #40] ; 0x28 - int satelliteCount = 0; - 8001cdc: 2300 movs r3, #0 - 8001cde: 67fb str r3, [r7, #124] ; 0x7c - for(int i=3; i<15; i++){ - 8001ce0: 2303 movs r3, #3 - 8001ce2: 67bb str r3, [r7, #120] ; 0x78 - 8001ce4: e00e b.n 8001d04 - if(values[i][0] != '\0'){ - 8001ce6: 6fbb ldr r3, [r7, #120] ; 0x78 - 8001ce8: 009b lsls r3, r3, #2 - 8001cea: 3388 adds r3, #136 ; 0x88 - 8001cec: 443b add r3, r7 - 8001cee: f853 3c7c ldr.w r3, [r3, #-124] - 8001cf2: 781b ldrb r3, [r3, #0] - 8001cf4: 2b00 cmp r3, #0 - 8001cf6: d002 beq.n 8001cfe - satelliteCount++; - 8001cf8: 6ffb ldr r3, [r7, #124] ; 0x7c - 8001cfa: 3301 adds r3, #1 - 8001cfc: 67fb str r3, [r7, #124] ; 0x7c - for(int i=3; i<15; i++){ - 8001cfe: 6fbb ldr r3, [r7, #120] ; 0x78 - 8001d00: 3301 adds r3, #1 - 8001d02: 67bb str r3, [r7, #120] ; 0x78 - 8001d04: 6fbb ldr r3, [r7, #120] ; 0x78 - 8001d06: 2b0e cmp r3, #14 - 8001d08: dded ble.n 8001ce6 - } - } - gps_data->satelliteCount = satelliteCount; - 8001d0a: 687b ldr r3, [r7, #4] - 8001d0c: 6ffa ldr r2, [r7, #124] ; 0x7c - 8001d0e: 625a str r2, [r3, #36] ; 0x24 - for(int i=0; i - 8001d16: 6f7b ldr r3, [r7, #116] ; 0x74 - 8001d18: 009b lsls r3, r3, #2 - 8001d1a: 3388 adds r3, #136 ; 0x88 - 8001d1c: 443b add r3, r7 - 8001d1e: f853 3c7c ldr.w r3, [r3, #-124] - 8001d22: 4618 mov r0, r3 - 8001d24: f00e ff0e bl 8010b44 - 8001d28: 6f7b ldr r3, [r7, #116] ; 0x74 - 8001d2a: 3301 adds r3, #1 - 8001d2c: 677b str r3, [r7, #116] ; 0x74 - 8001d2e: 6f7a ldr r2, [r7, #116] ; 0x74 - 8001d30: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 8001d34: 429a cmp r2, r3 - 8001d36: dbee blt.n 8001d16 - return 1; - 8001d38: 2301 movs r3, #1 + /* USER CODE END I2C3_MspInit 1 */ + } } - 8001d3a: 4618 mov r0, r3 - 8001d3c: 378c adds r7, #140 ; 0x8c - 8001d3e: 46bd mov sp, r7 - 8001d40: bd90 pop {r4, r7, pc} - 8001d42: bf00 nop - 8001d44: 080168d8 .word 0x080168d8 - -08001d48 : + 8001680: e05d b.n 800173e + else if(i2cHandle->Instance==I2C3) + 8001682: 687b ldr r3, [r7, #4] + 8001684: 681b ldr r3, [r3, #0] + 8001686: 4a32 ldr r2, [pc, #200] ; (8001750 ) + 8001688: 4293 cmp r3, r2 + 800168a: d158 bne.n 800173e + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C3; + 800168c: f44f 7380 mov.w r3, #256 ; 0x100 + 8001690: 623b str r3, [r7, #32] + PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_SYSCLK; + 8001692: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8001696: 653b str r3, [r7, #80] ; 0x50 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8001698: f107 0320 add.w r3, r7, #32 + 800169c: 4618 mov r0, r3 + 800169e: f008 fecb bl 800a438 + 80016a2: 4603 mov r3, r0 + 80016a4: 2b00 cmp r3, #0 + 80016a6: d001 beq.n 80016ac + Error_Handler(); + 80016a8: f000 f9a3 bl 80019f2 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80016ac: 4b27 ldr r3, [pc, #156] ; (800174c ) + 80016ae: 6cdb ldr r3, [r3, #76] ; 0x4c + 80016b0: 4a26 ldr r2, [pc, #152] ; (800174c ) + 80016b2: f043 0301 orr.w r3, r3, #1 + 80016b6: 64d3 str r3, [r2, #76] ; 0x4c + 80016b8: 4b24 ldr r3, [pc, #144] ; (800174c ) + 80016ba: 6cdb ldr r3, [r3, #76] ; 0x4c + 80016bc: f003 0301 and.w r3, r3, #1 + 80016c0: 617b str r3, [r7, #20] + 80016c2: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80016c4: 4b21 ldr r3, [pc, #132] ; (800174c ) + 80016c6: 6cdb ldr r3, [r3, #76] ; 0x4c + 80016c8: 4a20 ldr r2, [pc, #128] ; (800174c ) + 80016ca: f043 0302 orr.w r3, r3, #2 + 80016ce: 64d3 str r3, [r2, #76] ; 0x4c + 80016d0: 4b1e ldr r3, [pc, #120] ; (800174c ) + 80016d2: 6cdb ldr r3, [r3, #76] ; 0x4c + 80016d4: f003 0302 and.w r3, r3, #2 + 80016d8: 613b str r3, [r7, #16] + 80016da: 693b ldr r3, [r7, #16] + GPIO_InitStruct.Pin = GPIO_PIN_7; + 80016dc: 2380 movs r3, #128 ; 0x80 + 80016de: 677b str r3, [r7, #116] ; 0x74 + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 80016e0: 2312 movs r3, #18 + 80016e2: 67bb str r3, [r7, #120] ; 0x78 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80016e4: 2300 movs r3, #0 + 80016e6: 67fb str r3, [r7, #124] ; 0x7c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80016e8: 2303 movs r3, #3 + 80016ea: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + 80016ee: 2304 movs r3, #4 + 80016f0: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80016f4: f107 0374 add.w r3, r7, #116 ; 0x74 + 80016f8: 4619 mov r1, r3 + 80016fa: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 80016fe: f005 fc0b bl 8006f18 + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8001702: 2310 movs r3, #16 + 8001704: 677b str r3, [r7, #116] ; 0x74 + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001706: 2312 movs r3, #18 + 8001708: 67bb str r3, [r7, #120] ; 0x78 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800170a: 2300 movs r3, #0 + 800170c: 67fb str r3, [r7, #124] ; 0x7c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800170e: 2303 movs r3, #3 + 8001710: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + 8001714: 2304 movs r3, #4 + 8001716: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800171a: f107 0374 add.w r3, r7, #116 ; 0x74 + 800171e: 4619 mov r1, r3 + 8001720: 480c ldr r0, [pc, #48] ; (8001754 ) + 8001722: f005 fbf9 bl 8006f18 + __HAL_RCC_I2C3_CLK_ENABLE(); + 8001726: 4b09 ldr r3, [pc, #36] ; (800174c ) + 8001728: 6d9b ldr r3, [r3, #88] ; 0x58 + 800172a: 4a08 ldr r2, [pc, #32] ; (800174c ) + 800172c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8001730: 6593 str r3, [r2, #88] ; 0x58 + 8001732: 4b06 ldr r3, [pc, #24] ; (800174c ) + 8001734: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001736: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800173a: 60fb str r3, [r7, #12] + 800173c: 68fb ldr r3, [r7, #12] +} + 800173e: bf00 nop + 8001740: 3788 adds r7, #136 ; 0x88 + 8001742: 46bd mov sp, r7 + 8001744: bd80 pop {r7, pc} + 8001746: bf00 nop + 8001748: 40005400 .word 0x40005400 + 800174c: 40021000 .word 0x40021000 + 8001750: 40005c00 .word 0x40005c00 + 8001754: 48000400 .word 0x48000400 + +08001758 : +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)//lors d'un appuie sur un bouton, le systeme s'interrompt afin d'arriver dans cette fonction redefinie avec en parametre d'entre , le bouton sur lequel l'on a appuiyé +{ + 8001758: b480 push {r7} + 800175a: b083 sub sp, #12 + 800175c: af00 add r7, sp, #0 + 800175e: 4603 mov r3, r0 + 8001760: 80fb strh r3, [r7, #6] + if(GPIO_Pin==GPIO_PIN_8){ + 8001762: 88fb ldrh r3, [r7, #6] + 8001764: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8001768: d104 bne.n 8001774 +// ssd1306_SetCursor(33, 44); +// ssd1306_WriteString("btna", Font_6x8, White); +// ssd1306_UpdateScreen(); + BTN_A++;//sert à reconnaitre lorsque le bouto na est appuyer, cette variable est mise à 1 par un e interruption. + 800176a: 4b09 ldr r3, [pc, #36] ; (8001790 ) + 800176c: 681b ldr r3, [r3, #0] + 800176e: 3301 adds r3, #1 + 8001770: 4a07 ldr r2, [pc, #28] ; (8001790 ) + 8001772: 6013 str r3, [r2, #0] -int nmea_GNRMC(GPS *gps_data, char*inputString){ - 8001d48: b590 push {r4, r7, lr} - 8001d4a: b0a1 sub sp, #132 ; 0x84 - 8001d4c: af00 add r7, sp, #0 - 8001d4e: 6078 str r0, [r7, #4] - 8001d50: 6039 str r1, [r7, #0] - char *values[25]; - int counter = 0; - 8001d52: 2300 movs r3, #0 - 8001d54: 67fb str r3, [r7, #124] ; 0x7c - memset(values, 0, sizeof(values)); - 8001d56: f107 030c add.w r3, r7, #12 - 8001d5a: 2264 movs r2, #100 ; 0x64 - 8001d5c: 2100 movs r1, #0 - 8001d5e: 4618 mov r0, r3 - 8001d60: f010 fe7b bl 8012a5a - char *marker = strtok(inputString, ","); - 8001d64: 4930 ldr r1, [pc, #192] ; (8001e28 ) - 8001d66: 6838 ldr r0, [r7, #0] - 8001d68: f010 fe92 bl 8012a90 - 8001d6c: 67b8 str r0, [r7, #120] ; 0x78 - while (marker != NULL) { - 8001d6e: e021 b.n 8001db4 - values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! - 8001d70: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8001d72: f7fe fa7d bl 8000270 - 8001d76: 4603 mov r3, r0 - 8001d78: 1c5a adds r2, r3, #1 - 8001d7a: 6ffc ldr r4, [r7, #124] ; 0x7c - 8001d7c: 1c63 adds r3, r4, #1 - 8001d7e: 67fb str r3, [r7, #124] ; 0x7c - 8001d80: 4610 mov r0, r2 - 8001d82: f00e fed7 bl 8010b34 - 8001d86: 4603 mov r3, r0 - 8001d88: 461a mov r2, r3 - 8001d8a: 00a3 lsls r3, r4, #2 - 8001d8c: 3380 adds r3, #128 ; 0x80 - 8001d8e: 443b add r3, r7 - 8001d90: f843 2c74 str.w r2, [r3, #-116] - strcpy(values[counter - 1], marker); - 8001d94: 6ffb ldr r3, [r7, #124] ; 0x7c - 8001d96: 3b01 subs r3, #1 - 8001d98: 009b lsls r3, r3, #2 - 8001d9a: 3380 adds r3, #128 ; 0x80 - 8001d9c: 443b add r3, r7 - 8001d9e: f853 3c74 ldr.w r3, [r3, #-116] - 8001da2: 6fb9 ldr r1, [r7, #120] ; 0x78 - 8001da4: 4618 mov r0, r3 - 8001da6: f010 ff6c bl 8012c82 - marker = strtok(NULL, ","); - 8001daa: 491f ldr r1, [pc, #124] ; (8001e28 ) - 8001dac: 2000 movs r0, #0 - 8001dae: f010 fe6f bl 8012a90 - 8001db2: 67b8 str r0, [r7, #120] ; 0x78 - while (marker != NULL) { - 8001db4: 6fbb ldr r3, [r7, #120] ; 0x78 - 8001db6: 2b00 cmp r3, #0 - 8001db8: d1da bne.n 8001d70 - } - float speed = strtof(values[7], NULL); - 8001dba: 6abb ldr r3, [r7, #40] ; 0x28 - 8001dbc: 2100 movs r1, #0 - 8001dbe: 4618 mov r0, r3 - 8001dc0: f00f fd88 bl 80118d4 - 8001dc4: ed87 0a1c vstr s0, [r7, #112] ; 0x70 - gps_data->speed=speed/(1.944); - 8001dc8: 6f38 ldr r0, [r7, #112] ; 0x70 - 8001dca: f7fe fbbd bl 8000548 <__aeabi_f2d> - 8001dce: a314 add r3, pc, #80 ; (adr r3, 8001e20 ) - 8001dd0: e9d3 2300 ldrd r2, r3, [r3] - 8001dd4: f7fe fd3a bl 800084c <__aeabi_ddiv> - 8001dd8: 4602 mov r2, r0 - 8001dda: 460b mov r3, r1 - 8001ddc: 4610 mov r0, r2 - 8001dde: 4619 mov r1, r3 - 8001de0: f7fe ff02 bl 8000be8 <__aeabi_d2f> - 8001de4: 4602 mov r2, r0 - 8001de6: 687b ldr r3, [r7, #4] - 8001de8: 639a str r2, [r3, #56] ; 0x38 + } + if(GPIO_Pin==GPIO_PIN_1){ + 8001774: 88fb ldrh r3, [r7, #6] + 8001776: 2b02 cmp r3, #2 + 8001778: d104 bne.n 8001784 + //ssd1306_SetCursor(33, 44); + //ssd1306_WriteString("btnb", Font_6x8, White); + //ssd1306_UpdateScreen(); + BTN_B++;//de meme pour le bouton b + 800177a: 4b06 ldr r3, [pc, #24] ; (8001794 ) + 800177c: 681b ldr r3, [r3, #0] + 800177e: 3301 adds r3, #1 + 8001780: 4a04 ldr r2, [pc, #16] ; (8001794 ) + 8001782: 6013 str r3, [r2, #0] - for(int i=0; i - 8001df0: 6f7b ldr r3, [r7, #116] ; 0x74 - 8001df2: 009b lsls r3, r3, #2 - 8001df4: 3380 adds r3, #128 ; 0x80 - 8001df6: 443b add r3, r7 - 8001df8: f853 3c74 ldr.w r3, [r3, #-116] - 8001dfc: 4618 mov r0, r3 - 8001dfe: f00e fea1 bl 8010b44 - 8001e02: 6f7b ldr r3, [r7, #116] ; 0x74 - 8001e04: 3301 adds r3, #1 - 8001e06: 677b str r3, [r7, #116] ; 0x74 - 8001e08: 6f7a ldr r2, [r7, #116] ; 0x74 - 8001e0a: 6ffb ldr r3, [r7, #124] ; 0x7c - 8001e0c: 429a cmp r2, r3 - 8001e0e: dbef blt.n 8001df0 - return 1; - 8001e10: 2301 movs r3, #1 + } } - 8001e12: 4618 mov r0, r3 - 8001e14: 3784 adds r7, #132 ; 0x84 - 8001e16: 46bd mov sp, r7 - 8001e18: bd90 pop {r4, r7, pc} - 8001e1a: bf00 nop - 8001e1c: f3af 8000 nop.w - 8001e20: be76c8b4 .word 0xbe76c8b4 - 8001e24: 3fff1a9f .word 0x3fff1a9f - 8001e28: 080168d8 .word 0x080168d8 + 8001784: bf00 nop + 8001786: 370c adds r7, #12 + 8001788: 46bd mov sp, r7 + 800178a: f85d 7b04 ldr.w r7, [sp], #4 + 800178e: 4770 bx lr + 8001790: 200006f0 .word 0x200006f0 + 8001794: 200006f4 .word 0x200006f4 -08001e2c : +08001798
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8001798: b580 push {r7, lr} + 800179a: b082 sub sp, #8 + 800179c: af02 add r7, sp, #8 + /* USER CODE END 1 */ + /* MCU Configuration--------------------------------------------------------*/ + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800179e: f003 fcee bl 800517e + /* USER CODE BEGIN Init */ -void nmea_parse(GPS *gps_data, uint8_t *buffer){ - 8001e2c: b590 push {r4, r7, lr} - 8001e2e: b087 sub sp, #28 - 8001e30: af00 add r7, sp, #0 - 8001e32: 6078 str r0, [r7, #4] - 8001e34: 6039 str r1, [r7, #0] - memset(data, 0, sizeof(data)); - 8001e36: 223c movs r2, #60 ; 0x3c - 8001e38: 2100 movs r1, #0 - 8001e3a: 484e ldr r0, [pc, #312] ; (8001f74 ) - 8001e3c: f010 fe0d bl 8012a5a - char * token = strtok(buffer, "$"); - 8001e40: 494d ldr r1, [pc, #308] ; (8001f78 ) - 8001e42: 6838 ldr r0, [r7, #0] - 8001e44: f010 fe24 bl 8012a90 - 8001e48: 6178 str r0, [r7, #20] - int cnt = 0; - 8001e4a: 2300 movs r3, #0 - 8001e4c: 613b str r3, [r7, #16] - while(token !=NULL){ - 8001e4e: e01d b.n 8001e8c - data[cnt++] = malloc(strlen(token)+1); //free later!!!!! - 8001e50: 6978 ldr r0, [r7, #20] - 8001e52: f7fe fa0d bl 8000270 - 8001e56: 4603 mov r3, r0 - 8001e58: 1c5a adds r2, r3, #1 - 8001e5a: 693c ldr r4, [r7, #16] - 8001e5c: 1c63 adds r3, r4, #1 - 8001e5e: 613b str r3, [r7, #16] - 8001e60: 4610 mov r0, r2 - 8001e62: f00e fe67 bl 8010b34 - 8001e66: 4603 mov r3, r0 - 8001e68: 461a mov r2, r3 - 8001e6a: 4b42 ldr r3, [pc, #264] ; (8001f74 ) - 8001e6c: f843 2024 str.w r2, [r3, r4, lsl #2] - strcpy(data[cnt-1], token); - 8001e70: 693b ldr r3, [r7, #16] - 8001e72: 3b01 subs r3, #1 - 8001e74: 4a3f ldr r2, [pc, #252] ; (8001f74 ) - 8001e76: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001e7a: 6979 ldr r1, [r7, #20] - 8001e7c: 4618 mov r0, r3 - 8001e7e: f010 ff00 bl 8012c82 - token = strtok(NULL, "$"); - 8001e82: 493d ldr r1, [pc, #244] ; (8001f78 ) - 8001e84: 2000 movs r0, #0 - 8001e86: f010 fe03 bl 8012a90 - 8001e8a: 6178 str r0, [r7, #20] - while(token !=NULL){ - 8001e8c: 697b ldr r3, [r7, #20] - 8001e8e: 2b00 cmp r3, #0 - 8001e90: d1de bne.n 8001e50 - } - for(int i = 0; i - if(strstr(data[i], "\r\n")!=NULL && gps_checksum(data[i])){ - 8001e98: 4a36 ldr r2, [pc, #216] ; (8001f74 ) - 8001e9a: 68fb ldr r3, [r7, #12] - 8001e9c: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001ea0: 4936 ldr r1, [pc, #216] ; (8001f7c ) - 8001ea2: 4618 mov r0, r3 - 8001ea4: f010 fe50 bl 8012b48 - 8001ea8: 4603 mov r3, r0 - 8001eaa: 2b00 cmp r3, #0 - 8001eac: d044 beq.n 8001f38 - 8001eae: 4a31 ldr r2, [pc, #196] ; (8001f74 ) - 8001eb0: 68fb ldr r3, [r7, #12] - 8001eb2: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001eb6: 4618 mov r0, r3 - 8001eb8: f7ff fca3 bl 8001802 - 8001ebc: 4603 mov r3, r0 - 8001ebe: 2b00 cmp r3, #0 - 8001ec0: d03a beq.n 8001f38 - if(strstr(data[i], "GNRMC")!=NULL){ - 8001ec2: 4a2c ldr r2, [pc, #176] ; (8001f74 ) - 8001ec4: 68fb ldr r3, [r7, #12] - 8001ec6: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001eca: 492d ldr r1, [pc, #180] ; (8001f80 ) - 8001ecc: 4618 mov r0, r3 - 8001ece: f010 fe3b bl 8012b48 - 8001ed2: 4603 mov r3, r0 - 8001ed4: 2b00 cmp r3, #0 - 8001ed6: d008 beq.n 8001eea - nmea_GNRMC(gps_data, data[i]); - 8001ed8: 4a26 ldr r2, [pc, #152] ; (8001f74 ) - 8001eda: 68fb ldr r3, [r7, #12] - 8001edc: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001ee0: 4619 mov r1, r3 - 8001ee2: 6878 ldr r0, [r7, #4] - 8001ee4: f7ff ff30 bl 8001d48 - 8001ee8: e026 b.n 8001f38 - } - else if(strstr(data[i], "GNGSA")!=NULL){ - 8001eea: 4a22 ldr r2, [pc, #136] ; (8001f74 ) - 8001eec: 68fb ldr r3, [r7, #12] - 8001eee: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001ef2: 4924 ldr r1, [pc, #144] ; (8001f84 ) - 8001ef4: 4618 mov r0, r3 - 8001ef6: f010 fe27 bl 8012b48 - 8001efa: 4603 mov r3, r0 - 8001efc: 2b00 cmp r3, #0 - 8001efe: d008 beq.n 8001f12 - nmea_GPGSA(gps_data, data[i]); - 8001f00: 4a1c ldr r2, [pc, #112] ; (8001f74 ) - 8001f02: 68fb ldr r3, [r7, #12] - 8001f04: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001f08: 4619 mov r1, r3 - 8001f0a: 6878 ldr r0, [r7, #4] - 8001f0c: f7ff fe94 bl 8001c38 - 8001f10: e012 b.n 8001f38 - } - else if(strstr(data[i], "GNGGA")!=NULL){ - 8001f12: 4a18 ldr r2, [pc, #96] ; (8001f74 ) - 8001f14: 68fb ldr r3, [r7, #12] - 8001f16: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001f1a: 491b ldr r1, [pc, #108] ; (8001f88 ) - 8001f1c: 4618 mov r0, r3 - 8001f1e: f010 fe13 bl 8012b48 - 8001f22: 4603 mov r3, r0 - 8001f24: 2b00 cmp r3, #0 - 8001f26: d007 beq.n 8001f38 - nmea_GPGGA(gps_data, data[i]); - 8001f28: 4a12 ldr r2, [pc, #72] ; (8001f74 ) - 8001f2a: 68fb ldr r3, [r7, #12] - 8001f2c: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001f30: 4619 mov r1, r3 - 8001f32: 6878 ldr r0, [r7, #4] - 8001f34: f7ff fcae bl 8001894 - for(int i = 0; i - } - } + /* USER CODE END Init */ - } - for(int i = 0; i - 8001f4c: 4a09 ldr r2, [pc, #36] ; (8001f74 ) - 8001f4e: 68bb ldr r3, [r7, #8] - 8001f50: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001f54: 4618 mov r0, r3 - 8001f56: f00e fdf5 bl 8010b44 - 8001f5a: 68bb ldr r3, [r7, #8] - 8001f5c: 3301 adds r3, #1 - 8001f5e: 60bb str r3, [r7, #8] - 8001f60: 68ba ldr r2, [r7, #8] - 8001f62: 693b ldr r3, [r7, #16] - 8001f64: 429a cmp r2, r3 - 8001f66: dbf1 blt.n 8001f4c - - -} - 8001f68: bf00 nop - 8001f6a: bf00 nop - 8001f6c: 371c adds r7, #28 - 8001f6e: 46bd mov sp, r7 - 8001f70: bd90 pop {r4, r7, pc} - 8001f72: bf00 nop - 8001f74: 2000083c .word 0x2000083c - 8001f78: 080168dc .word 0x080168dc - 8001f7c: 080168e0 .word 0x080168e0 - 8001f80: 080168e4 .word 0x080168e4 - 8001f84: 080168ec .word 0x080168ec - 8001f88: 080168f4 .word 0x080168f4 - -08001f8c : -#include -#include -#include // For memcpy + /* Configure the system clock */ + SystemClock_Config(); + 80017a2: f000 f8a5 bl 80018f0 +/* Configure the peripherals common clocks */ + PeriphCommonClock_Config(); + 80017a6: f000 f8f6 bl 8001996 + /* USER CODE BEGIN SysInit */ -void ssd1306_Reset(void) { - 8001f8c: b480 push {r7} - 8001f8e: af00 add r7, sp, #0 - /* for I2C - do nothing */ -} - 8001f90: bf00 nop - 8001f92: 46bd mov sp, r7 - 8001f94: f85d 7b04 ldr.w r7, [sp], #4 - 8001f98: 4770 bx lr - ... + /* USER CODE END SysInit */ -08001f9c : + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80017aa: f7ff fe13 bl 80013d4 + MX_DMA_Init(); + 80017ae: f7ff fddf bl 8001370 + MX_I2C3_Init(); + 80017b2: f7ff fecf bl 8001554 + MX_LPUART1_UART_Init(); + 80017b6: f003 fb1f bl 8004df8 + MX_ADC1_Init(); + 80017ba: f7ff fc19 bl 8000ff0 + MX_TIM2_Init(); + 80017be: f003 faaf bl 8004d20 + MX_USB_DEVICE_Init(); + 80017c2: f010 fe73 bl 80124ac + MX_I2C1_Init(); + 80017c6: f7ff fe85 bl 80014d4 + MX_USART1_UART_Init(); + 80017ca: f003 fb41 bl 8004e50 + MX_SPI1_Init(); + 80017ce: f000 fcdd bl 800218c + /* USER CODE BEGIN 2 */ -// Send a byte to the command register -void ssd1306_WriteCommand(uint8_t byte) { - 8001f9c: b580 push {r7, lr} - 8001f9e: b086 sub sp, #24 - 8001fa0: af04 add r7, sp, #16 - 8001fa2: 4603 mov r3, r0 - 8001fa4: 71fb strb r3, [r7, #7] - HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x00, 1, &byte, 1, HAL_MAX_DELAY); - 8001fa6: f04f 33ff mov.w r3, #4294967295 - 8001faa: 9302 str r3, [sp, #8] - 8001fac: 2301 movs r3, #1 - 8001fae: 9301 str r3, [sp, #4] - 8001fb0: 1dfb adds r3, r7, #7 - 8001fb2: 9300 str r3, [sp, #0] - 8001fb4: 2301 movs r3, #1 - 8001fb6: 2200 movs r2, #0 - 8001fb8: 2178 movs r1, #120 ; 0x78 - 8001fba: 4803 ldr r0, [pc, #12] ; (8001fc8 ) - 8001fbc: f004 fd26 bl 8006a0c -} - 8001fc0: bf00 nop - 8001fc2: 3708 adds r7, #8 - 8001fc4: 46bd mov sp, r7 - 8001fc6: bd80 pop {r7, pc} - 8001fc8: 200003e0 .word 0x200003e0 - -08001fcc : -// Send data -void ssd1306_WriteData(uint8_t* buffer, size_t buff_size) { - 8001fcc: b580 push {r7, lr} - 8001fce: b086 sub sp, #24 - 8001fd0: af04 add r7, sp, #16 - 8001fd2: 6078 str r0, [r7, #4] - 8001fd4: 6039 str r1, [r7, #0] - HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x40, 1, buffer, buff_size, HAL_MAX_DELAY); - 8001fd6: 683b ldr r3, [r7, #0] - 8001fd8: b29b uxth r3, r3 - 8001fda: f04f 32ff mov.w r2, #4294967295 - 8001fde: 9202 str r2, [sp, #8] - 8001fe0: 9301 str r3, [sp, #4] - 8001fe2: 687b ldr r3, [r7, #4] - 8001fe4: 9300 str r3, [sp, #0] - 8001fe6: 2301 movs r3, #1 - 8001fe8: 2240 movs r2, #64 ; 0x40 - 8001fea: 2178 movs r1, #120 ; 0x78 - 8001fec: 4803 ldr r0, [pc, #12] ; (8001ffc ) - 8001fee: f004 fd0d bl 8006a0c -} - 8001ff2: bf00 nop - 8001ff4: 3708 adds r7, #8 - 8001ff6: 46bd mov sp, r7 - 8001ff8: bd80 pop {r7, pc} - 8001ffa: bf00 nop - 8001ffc: 200003e0 .word 0x200003e0 - -08002000 : - } - return ret; -} -/* Initialize the oled screen */ -void ssd1306_Init(void) { - 8002000: b580 push {r7, lr} - 8002002: af00 add r7, sp, #0 - // Reset OLED - ssd1306_Reset(); - 8002004: f7ff ffc2 bl 8001f8c + ssd1306_Init(); + 80017d2: f000 ff43 bl 800265c - // Wait for the screen to boot - HAL_Delay(100); - 8002008: 2064 movs r0, #100 ; 0x64 - 800200a: f002 fae3 bl 80045d4 + HAL_Delay(100); + 80017d6: 2064 movs r0, #100 ; 0x64 + 80017d8: f003 fd46 bl 8005268 + ssd1306_Fill(Black); + 80017dc: 2000 movs r0, #0 + 80017de: f000 ffa7 bl 8002730 - // Init OLED - ssd1306_SetDisplayOn(0); //display off - 800200e: 2000 movs r0, #0 - 8002010: f000 fba0 bl 8002754 + ssd1306_DrawBitmap(32, 32, startimg, 64, 64, White); + 80017e2: 2301 movs r3, #1 + 80017e4: 9301 str r3, [sp, #4] + 80017e6: 2340 movs r3, #64 ; 0x40 + 80017e8: 9300 str r3, [sp, #0] + 80017ea: 2340 movs r3, #64 ; 0x40 + 80017ec: 4a2f ldr r2, [pc, #188] ; (80018ac ) + 80017ee: 2120 movs r1, #32 + 80017f0: 2020 movs r0, #32 + 80017f2: f001 fa6f bl 8002cd4 + ssd1306_UpdateScreen(); + 80017f6: f000 ffb3 bl 8002760 - ssd1306_WriteCommand(0x20); //Set Memory Addressing Mode - 8002014: 2020 movs r0, #32 - 8002016: f7ff ffc1 bl 8001f9c - ssd1306_WriteCommand(0x00); // 00b,Horizontal Addressing Mode; 01b,Vertical Addressing Mode; - 800201a: 2000 movs r0, #0 - 800201c: f7ff ffbe bl 8001f9c - // 10b,Page Addressing Mode (RESET); 11b,Invalid + HAL_Delay(500); + 80017fa: f44f 70fa mov.w r0, #500 ; 0x1f4 + 80017fe: f003 fd33 bl 8005268 - ssd1306_WriteCommand(0xB0); //Set Page Start Address for Page Addressing Mode,0-7 - 8002020: 20b0 movs r0, #176 ; 0xb0 - 8002022: f7ff ffbb bl 8001f9c + HAL_ADC_Start_DMA(&hadc1,(uint32_t*)rawdata, 3); + 8001802: 2203 movs r2, #3 + 8001804: 492a ldr r1, [pc, #168] ; (80018b0 ) + 8001806: 482b ldr r0, [pc, #172] ; (80018b4 ) + 8001808: f004 f86e bl 80058e8 + HAL_TIM_Base_Start(&htim2); + 800180c: 482a ldr r0, [pc, #168] ; (80018b8 ) + 800180e: f00a f881 bl 800b914 -#ifdef SSD1306_MIRROR_VERT - ssd1306_WriteCommand(0xC0); // Mirror vertically -#else - ssd1306_WriteCommand(0xC8); //Set COM Output Scan Direction - 8002026: 20c8 movs r0, #200 ; 0xc8 - 8002028: f7ff ffb8 bl 8001f9c -#endif + HAL_UART_Abort(&hlpuart1); + 8001812: 482a ldr r0, [pc, #168] ; (80018bc ) + 8001814: f00a fb92 bl 800bf3c + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE); + 8001818: 2240 movs r2, #64 ; 0x40 + 800181a: 4929 ldr r1, [pc, #164] ; (80018c0 ) + 800181c: 4827 ldr r0, [pc, #156] ; (80018bc ) + 800181e: f00a fb41 bl 800bea4 + + memset(flashread,'1',256); + 8001822: f44f 7280 mov.w r2, #256 ; 0x100 + 8001826: 2131 movs r1, #49 ; 0x31 + 8001828: 4826 ldr r0, [pc, #152] ; (80018c4 ) + 800182a: f013 fb6e bl 8014f0a + memset(flashwrite,'\0',256); + 800182e: f44f 7280 mov.w r2, #256 ; 0x100 + 8001832: 2100 movs r1, #0 + 8001834: 4824 ldr r0, [pc, #144] ; (80018c8 ) + 8001836: f013 fb68 bl 8014f0a + + SPIF_Init(&hspif1, &hspi1, GPIOB, GPIO_PIN_0); + 800183a: 2301 movs r3, #1 + 800183c: 4a23 ldr r2, [pc, #140] ; (80018cc ) + 800183e: 4924 ldr r1, [pc, #144] ; (80018d0 ) + 8001840: 4824 ldr r0, [pc, #144] ; (80018d4 ) + 8001842: f010 fcd0 bl 80121e6 - ssd1306_WriteCommand(0x00); //---set low column address - 800202c: 2000 movs r0, #0 - 800202e: f7ff ffb5 bl 8001f9c - ssd1306_WriteCommand(0x10); //---set high column address - 8002032: 2010 movs r0, #16 - 8002034: f7ff ffb2 bl 8001f9c + ssd1306_Fill(Black); + 8001846: 2000 movs r0, #0 + 8001848: f000 ff72 bl 8002730 + + getindex(); + 800184c: f000 fdd2 bl 80023f4 + + snprintf((uint8_t*)str,20, "off=%d",pageoffset); + 8001850: 4b21 ldr r3, [pc, #132] ; (80018d8 ) + 8001852: 681b ldr r3, [r3, #0] + 8001854: 4a21 ldr r2, [pc, #132] ; (80018dc ) + 8001856: 2114 movs r1, #20 + 8001858: 4821 ldr r0, [pc, #132] ; (80018e0 ) + 800185a: f013 fabf bl 8014ddc + ssd1306_SetCursor(32,40); + 800185e: 2128 movs r1, #40 ; 0x28 + 8001860: 2020 movs r0, #32 + 8001862: f001 f8a7 bl 80029b4 + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + 8001866: 4a1f ldr r2, [pc, #124] ; (80018e4 ) + 8001868: 2301 movs r3, #1 + 800186a: ca06 ldmia r2, {r1, r2} + 800186c: 481c ldr r0, [pc, #112] ; (80018e0 ) + 800186e: f001 f87b bl 8002968 + snprintf((uint8_t*)str,20, "page=%d",pagenumber); + 8001872: 4b1d ldr r3, [pc, #116] ; (80018e8 ) + 8001874: 681b ldr r3, [r3, #0] + 8001876: 4a1d ldr r2, [pc, #116] ; (80018ec ) + 8001878: 2114 movs r1, #20 + 800187a: 4819 ldr r0, [pc, #100] ; (80018e0 ) + 800187c: f013 faae bl 8014ddc + ssd1306_SetCursor(32,48); + 8001880: 2130 movs r1, #48 ; 0x30 + 8001882: 2020 movs r0, #32 + 8001884: f001 f896 bl 80029b4 + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + 8001888: 4a16 ldr r2, [pc, #88] ; (80018e4 ) + 800188a: 2301 movs r3, #1 + 800188c: ca06 ldmia r2, {r1, r2} + 800188e: 4814 ldr r0, [pc, #80] ; (80018e0 ) + 8001890: f001 f86a bl 8002968 + ssd1306_UpdateScreen(); + 8001894: f000 ff64 bl 8002760 - ssd1306_WriteCommand(0x40); //--set start line address - CHECK - 8002038: 2040 movs r0, #64 ; 0x40 - 800203a: f7ff ffaf bl 8001f9c + HAL_Delay(1000); + 8001898: f44f 707a mov.w r0, #1000 ; 0x3e8 + 800189c: f003 fce4 bl 8005268 +// } - ssd1306_SetContrast(0xFF); - 800203e: 20ff movs r0, #255 ; 0xff - 8002040: f000 fb75 bl 800272e -#ifdef SSD1306_MIRROR_HORIZ - ssd1306_WriteCommand(0xA0); // Mirror horizontally -#else - ssd1306_WriteCommand(0xA1); //--set segment re-map 0 to 127 - CHECK - 8002044: 20a1 movs r0, #161 ; 0xa1 - 8002046: f7ff ffa9 bl 8001f9c -#endif -#ifdef SSD1306_INVERSE_COLOR - ssd1306_WriteCommand(0xA7); //--set inverse color -#else - ssd1306_WriteCommand(0xA6); //--set normal color - 800204a: 20a6 movs r0, #166 ; 0xa6 - 800204c: f7ff ffa6 bl 8001f9c -// Set multiplex ratio. -#if (SSD1306_HEIGHT == 128) - // Found in the Luma Python lib for SH1106. - ssd1306_WriteCommand(0xFF); -#else - ssd1306_WriteCommand(0xA8); //--set multiplex ratio(1 to 64) - CHECK - 8002050: 20a8 movs r0, #168 ; 0xa8 - 8002052: f7ff ffa3 bl 8001f9c -#endif -#if (SSD1306_HEIGHT == 32) - ssd1306_WriteCommand(0x1F); // -#elif (SSD1306_HEIGHT == 64) - ssd1306_WriteCommand(0x3F); // - 8002056: 203f movs r0, #63 ; 0x3f - 8002058: f7ff ffa0 bl 8001f9c - ssd1306_WriteCommand(0x3F); // Seems to work for 128px high displays too. -#else -#error "Only 32, 64, or 128 lines of height are supported!" -#endif + statemachine(); + 80018a0: f001 fc22 bl 80030e8 + ssd1306_UpdateScreen(); + 80018a4: f000 ff5c bl 8002760 + statemachine(); + 80018a8: e7fa b.n 80018a0 + 80018aa: bf00 nop + 80018ac: 08018fec .word 0x08018fec + 80018b0: 20000720 .word 0x20000720 + 80018b4: 20000314 .word 0x20000314 + 80018b8: 20000ea4 .word 0x20000ea4 + 80018bc: 20000ef0 .word 0x20000ef0 + 80018c0: 2000046c .word 0x2000046c + 80018c4: 20000834 .word 0x20000834 + 80018c8: 20000734 .word 0x20000734 + 80018cc: 48000400 .word 0x48000400 + 80018d0: 200009c8 .word 0x200009c8 + 80018d4: 20000700 .word 0x20000700 + 80018d8: 20000934 .word 0x20000934 + 80018dc: 08018d88 .word 0x08018d88 + 80018e0: 20000e48 .word 0x20000e48 + 80018e4: 20000008 .word 0x20000008 + 80018e8: 20000938 .word 0x20000938 + 80018ec: 08018d90 .word 0x08018d90 + +080018f0 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80018f0: b580 push {r7, lr} + 80018f2: b096 sub sp, #88 ; 0x58 + 80018f4: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80018f6: f107 0314 add.w r3, r7, #20 + 80018fa: 2244 movs r2, #68 ; 0x44 + 80018fc: 2100 movs r1, #0 + 80018fe: 4618 mov r0, r3 + 8001900: f013 fb03 bl 8014f0a + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8001904: 463b mov r3, r7 + 8001906: 2200 movs r2, #0 + 8001908: 601a str r2, [r3, #0] + 800190a: 605a str r2, [r3, #4] + 800190c: 609a str r2, [r3, #8] + 800190e: 60da str r2, [r3, #12] + 8001910: 611a str r2, [r3, #16] - ssd1306_WriteCommand(0xA4); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content - 800205c: 20a4 movs r0, #164 ; 0xa4 - 800205e: f7ff ff9d bl 8001f9c + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + 8001912: f44f 7000 mov.w r0, #512 ; 0x200 + 8001916: f007 fef1 bl 80096fc + 800191a: 4603 mov r3, r0 + 800191c: 2b00 cmp r3, #0 + 800191e: d001 beq.n 8001924 + { + Error_Handler(); + 8001920: f000 f867 bl 80019f2 + } - ssd1306_WriteCommand(0xD3); //-set display offset - CHECK - 8002062: 20d3 movs r0, #211 ; 0xd3 - 8002064: f7ff ff9a bl 8001f9c - ssd1306_WriteCommand(0x00); //-not offset - 8002068: 2000 movs r0, #0 - 800206a: f7ff ff97 bl 8001f9c + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + 8001924: 2310 movs r3, #16 + 8001926: 617b str r3, [r7, #20] + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + 8001928: 2301 movs r3, #1 + 800192a: 62fb str r3, [r7, #44] ; 0x2c + RCC_OscInitStruct.MSICalibrationValue = 0; + 800192c: 2300 movs r3, #0 + 800192e: 633b str r3, [r7, #48] ; 0x30 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + 8001930: 2360 movs r3, #96 ; 0x60 + 8001932: 637b str r3, [r7, #52] ; 0x34 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8001934: 2302 movs r3, #2 + 8001936: 63fb str r3, [r7, #60] ; 0x3c + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + 8001938: 2301 movs r3, #1 + 800193a: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.PLL.PLLM = 1; + 800193c: 2301 movs r3, #1 + 800193e: 647b str r3, [r7, #68] ; 0x44 + RCC_OscInitStruct.PLL.PLLN = 20; + 8001940: 2314 movs r3, #20 + 8001942: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + 8001944: 2307 movs r3, #7 + 8001946: 64fb str r3, [r7, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + 8001948: 2302 movs r3, #2 + 800194a: 653b str r3, [r7, #80] ; 0x50 + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + 800194c: 2302 movs r3, #2 + 800194e: 657b str r3, [r7, #84] ; 0x54 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8001950: f107 0314 add.w r3, r7, #20 + 8001954: 4618 mov r0, r3 + 8001956: f007 ff37 bl 80097c8 + 800195a: 4603 mov r3, r0 + 800195c: 2b00 cmp r3, #0 + 800195e: d001 beq.n 8001964 + { + Error_Handler(); + 8001960: f000 f847 bl 80019f2 + } - ssd1306_WriteCommand(0xD5); //--set display clock divide ratio/oscillator frequency - 800206e: 20d5 movs r0, #213 ; 0xd5 - 8002070: f7ff ff94 bl 8001f9c - ssd1306_WriteCommand(0xF0); //--set divide ratio - 8002074: 20f0 movs r0, #240 ; 0xf0 - 8002076: f7ff ff91 bl 8001f9c + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8001964: 230f movs r3, #15 + 8001966: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8001968: 2303 movs r3, #3 + 800196a: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800196c: 2300 movs r3, #0 + 800196e: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 8001970: f44f 63a0 mov.w r3, #1280 ; 0x500 + 8001974: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8001976: 2300 movs r3, #0 + 8001978: 613b str r3, [r7, #16] - ssd1306_WriteCommand(0xD9); //--set pre-charge period - 800207a: 20d9 movs r0, #217 ; 0xd9 - 800207c: f7ff ff8e bl 8001f9c - ssd1306_WriteCommand(0x22); // - 8002080: 2022 movs r0, #34 ; 0x22 - 8002082: f7ff ff8b bl 8001f9c + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 800197a: 463b mov r3, r7 + 800197c: 2102 movs r1, #2 + 800197e: 4618 mov r0, r3 + 8001980: f008 fb36 bl 8009ff0 + 8001984: 4603 mov r3, r0 + 8001986: 2b00 cmp r3, #0 + 8001988: d001 beq.n 800198e + { + Error_Handler(); + 800198a: f000 f832 bl 80019f2 + } +} + 800198e: bf00 nop + 8001990: 3758 adds r7, #88 ; 0x58 + 8001992: 46bd mov sp, r7 + 8001994: bd80 pop {r7, pc} - ssd1306_WriteCommand(0xDA); //--set com pins hardware configuration - CHECK - 8002086: 20da movs r0, #218 ; 0xda - 8002088: f7ff ff88 bl 8001f9c -#if (SSD1306_HEIGHT == 32) - ssd1306_WriteCommand(0x02); -#elif (SSD1306_HEIGHT == 64) - ssd1306_WriteCommand(0x12); - 800208c: 2012 movs r0, #18 - 800208e: f7ff ff85 bl 8001f9c - ssd1306_WriteCommand(0x12); -#else -#error "Only 32, 64, or 128 lines of height are supported!" -#endif - - ssd1306_WriteCommand(0xDB); //--set vcomh - 8002092: 20db movs r0, #219 ; 0xdb - 8002094: f7ff ff82 bl 8001f9c - ssd1306_WriteCommand(0x20); //0x20,0.77xVcc - 8002098: 2020 movs r0, #32 - 800209a: f7ff ff7f bl 8001f9c +08001996 : +/** + * @brief Peripherals Common Clock Configuration + * @retval None + */ +void PeriphCommonClock_Config(void) +{ + 8001996: b580 push {r7, lr} + 8001998: b096 sub sp, #88 ; 0x58 + 800199a: af00 add r7, sp, #0 + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 800199c: 1d3b adds r3, r7, #4 + 800199e: 2254 movs r2, #84 ; 0x54 + 80019a0: 2100 movs r1, #0 + 80019a2: 4618 mov r0, r3 + 80019a4: f013 fab1 bl 8014f0a - ssd1306_WriteCommand(0x8D); //--set DC-DC enable - 800209e: 208d movs r0, #141 ; 0x8d - 80020a0: f7ff ff7c bl 8001f9c - ssd1306_WriteCommand(0x14); // - 80020a4: 2014 movs r0, #20 - 80020a6: f7ff ff79 bl 8001f9c - ssd1306_SetDisplayOn(1); //--turn on SSD1306 panel - 80020aa: 2001 movs r0, #1 - 80020ac: f000 fb52 bl 8002754 + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC; + 80019a8: f44f 43c0 mov.w r3, #24576 ; 0x6000 + 80019ac: 607b str r3, [r7, #4] + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; + 80019ae: f04f 5380 mov.w r3, #268435456 ; 0x10000000 + 80019b2: 64fb str r3, [r7, #76] ; 0x4c + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + 80019b4: f04f 6380 mov.w r3, #67108864 ; 0x4000000 + 80019b8: 647b str r3, [r7, #68] ; 0x44 + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; + 80019ba: 2301 movs r3, #1 + 80019bc: 60bb str r3, [r7, #8] + PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + 80019be: 2301 movs r3, #1 + 80019c0: 60fb str r3, [r7, #12] + PeriphClkInit.PLLSAI1.PLLSAI1N = 24; + 80019c2: 2318 movs r3, #24 + 80019c4: 613b str r3, [r7, #16] + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + 80019c6: 2307 movs r3, #7 + 80019c8: 617b str r3, [r7, #20] + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + 80019ca: 2302 movs r3, #2 + 80019cc: 61bb str r3, [r7, #24] + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + 80019ce: 2302 movs r3, #2 + 80019d0: 61fb str r3, [r7, #28] + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK; + 80019d2: f04f 7388 mov.w r3, #17825792 ; 0x1100000 + 80019d6: 623b str r3, [r7, #32] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 80019d8: 1d3b adds r3, r7, #4 + 80019da: 4618 mov r0, r3 + 80019dc: f008 fd2c bl 800a438 + 80019e0: 4603 mov r3, r0 + 80019e2: 2b00 cmp r3, #0 + 80019e4: d001 beq.n 80019ea + { + Error_Handler(); + 80019e6: f000 f804 bl 80019f2 + } +} + 80019ea: bf00 nop + 80019ec: 3758 adds r7, #88 ; 0x58 + 80019ee: 46bd mov sp, r7 + 80019f0: bd80 pop {r7, pc} - // Clear screen - ssd1306_Fill(Black); - 80020b0: 2000 movs r0, #0 - 80020b2: f000 f80f bl 80020d4 - - // Flush buffer to screen - ssd1306_UpdateScreen(); - 80020b6: f000 f825 bl 8002104 - - // Set default values for screen object - SSD1306.CurrentX = 0; - 80020ba: 4b05 ldr r3, [pc, #20] ; (80020d0 ) - 80020bc: 2200 movs r2, #0 - 80020be: 801a strh r2, [r3, #0] - SSD1306.CurrentY = 0; - 80020c0: 4b03 ldr r3, [pc, #12] ; (80020d0 ) - 80020c2: 2200 movs r2, #0 - 80020c4: 805a strh r2, [r3, #2] - - SSD1306.Initialized = 1; - 80020c6: 4b02 ldr r3, [pc, #8] ; (80020d0 ) - 80020c8: 2201 movs r2, #1 - 80020ca: 711a strb r2, [r3, #4] +080019f2 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 80019f2: b480 push {r7} + 80019f4: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80019f6: b672 cpsid i } - 80020cc: bf00 nop - 80020ce: bd80 pop {r7, pc} - 80020d0: 20000c78 .word 0x20000c78 + 80019f8: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80019fa: e7fe b.n 80019fa -080020d4 : +080019fc : +//on a une fonction de decodage par typme de trame interressante, puis une fonction nmea_parse servant à mettre à jour la structure de donnée avec lesdonnées presentes dans le databuffer, qui lui se met à jour tout seul. -/* Fill the whole screen with the given color */ -void ssd1306_Fill(SSD1306_COLOR color) { - 80020d4: b580 push {r7, lr} - 80020d6: b082 sub sp, #8 - 80020d8: af00 add r7, sp, #0 - 80020da: 4603 mov r3, r0 - 80020dc: 71fb strb r3, [r7, #7] - memset(SSD1306_Buffer, (color == Black) ? 0x00 : 0xFF, sizeof(SSD1306_Buffer)); - 80020de: 79fb ldrb r3, [r7, #7] - 80020e0: 2b00 cmp r3, #0 - 80020e2: d101 bne.n 80020e8 - 80020e4: 2300 movs r3, #0 - 80020e6: e000 b.n 80020ea - 80020e8: 23ff movs r3, #255 ; 0xff - 80020ea: f44f 6280 mov.w r2, #1024 ; 0x400 - 80020ee: 4619 mov r1, r3 - 80020f0: 4803 ldr r0, [pc, #12] ; (8002100 ) - 80020f2: f010 fcb2 bl 8012a5a -} - 80020f6: bf00 nop - 80020f8: 3708 adds r7, #8 - 80020fa: 46bd mov sp, r7 - 80020fc: bd80 pop {r7, pc} - 80020fe: bf00 nop - 8002100: 20000878 .word 0x20000878 - -08002104 : +char *data[15]; -/* Write the screenbuffer with changed to the screen */ -void ssd1306_UpdateScreen(void) { - 8002104: b580 push {r7, lr} - 8002106: b082 sub sp, #8 - 8002108: af00 add r7, sp, #0 - // depends on the screen height: - // - // * 32px == 4 pages - // * 64px == 8 pages - // * 128px == 16 pages - for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) { - 800210a: 2300 movs r3, #0 - 800210c: 71fb strb r3, [r7, #7] - 800210e: e016 b.n 800213e - ssd1306_WriteCommand(0xB0 + i); // Set the current RAM page address. - 8002110: 79fb ldrb r3, [r7, #7] - 8002112: 3b50 subs r3, #80 ; 0x50 - 8002114: b2db uxtb r3, r3 - 8002116: 4618 mov r0, r3 - 8002118: f7ff ff40 bl 8001f9c - ssd1306_WriteCommand(0x00 + SSD1306_X_OFFSET_LOWER); - 800211c: 2000 movs r0, #0 - 800211e: f7ff ff3d bl 8001f9c - ssd1306_WriteCommand(0x10 + SSD1306_X_OFFSET_UPPER); - 8002122: 2010 movs r0, #16 - 8002124: f7ff ff3a bl 8001f9c - ssd1306_WriteData(&SSD1306_Buffer[SSD1306_WIDTH*i],SSD1306_WIDTH); - 8002128: 79fb ldrb r3, [r7, #7] - 800212a: 01db lsls r3, r3, #7 - 800212c: 4a08 ldr r2, [pc, #32] ; (8002150 ) - 800212e: 4413 add r3, r2 - 8002130: 2180 movs r1, #128 ; 0x80 - 8002132: 4618 mov r0, r3 - 8002134: f7ff ff4a bl 8001fcc - for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) { - 8002138: 79fb ldrb r3, [r7, #7] - 800213a: 3301 adds r3, #1 - 800213c: 71fb strb r3, [r7, #7] - 800213e: 79fb ldrb r3, [r7, #7] - 8002140: 2b07 cmp r3, #7 - 8002142: d9e5 bls.n 8002110 - } -} - 8002144: bf00 nop - 8002146: bf00 nop - 8002148: 3708 adds r7, #8 - 800214a: 46bd mov sp, r7 - 800214c: bd80 pop {r7, pc} - 800214e: bf00 nop - 8002150: 20000878 .word 0x20000878 +int gps_checksum(char *nmea_data) +{ + 80019fc: b580 push {r7, lr} + 80019fe: b086 sub sp, #24 + 8001a00: af00 add r7, sp, #0 + 8001a02: 6078 str r0, [r7, #4] + //if you point a string with less than 5 characters the function will read outside of scope and crash the mcu. + if(strlen(nmea_data) < 5) return 0; + 8001a04: 6878 ldr r0, [r7, #4] + 8001a06: f7fe fc33 bl 8000270 + 8001a0a: 4603 mov r3, r0 + 8001a0c: 2b04 cmp r3, #4 + 8001a0e: d801 bhi.n 8001a14 + 8001a10: 2300 movs r3, #0 + 8001a12: e038 b.n 8001a86 + char recv_crc[2]; + recv_crc[0] = nmea_data[strlen(nmea_data) - 4]; + 8001a14: 6878 ldr r0, [r7, #4] + 8001a16: f7fe fc2b bl 8000270 + 8001a1a: 4603 mov r3, r0 + 8001a1c: 3b04 subs r3, #4 + 8001a1e: 687a ldr r2, [r7, #4] + 8001a20: 4413 add r3, r2 + 8001a22: 781b ldrb r3, [r3, #0] + 8001a24: 723b strb r3, [r7, #8] + recv_crc[1] = nmea_data[strlen(nmea_data) - 3]; + 8001a26: 6878 ldr r0, [r7, #4] + 8001a28: f7fe fc22 bl 8000270 + 8001a2c: 4603 mov r3, r0 + 8001a2e: 3b03 subs r3, #3 + 8001a30: 687a ldr r2, [r7, #4] + 8001a32: 4413 add r3, r2 + 8001a34: 781b ldrb r3, [r3, #0] + 8001a36: 727b strb r3, [r7, #9] + int crc = 0; + 8001a38: 2300 movs r3, #0 + 8001a3a: 617b str r3, [r7, #20] + int i; -08002154 : - * Draw one pixel in the screenbuffer - * X => X Coordinate - * Y => Y Coordinate - * color => Pixel color - */ -void ssd1306_DrawPixel(uint8_t x, uint8_t y, SSD1306_COLOR color) { - 8002154: b480 push {r7} - 8002156: b083 sub sp, #12 - 8002158: af00 add r7, sp, #0 - 800215a: 4603 mov r3, r0 - 800215c: 71fb strb r3, [r7, #7] - 800215e: 460b mov r3, r1 - 8002160: 71bb strb r3, [r7, #6] - 8002162: 4613 mov r3, r2 - 8002164: 717b strb r3, [r7, #5] - if(x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { - 8002166: f997 3007 ldrsb.w r3, [r7, #7] - 800216a: 2b00 cmp r3, #0 - 800216c: db3d blt.n 80021ea - 800216e: 79bb ldrb r3, [r7, #6] - 8002170: 2b3f cmp r3, #63 ; 0x3f - 8002172: d83a bhi.n 80021ea - // Don't write outside the buffer - return; + //exclude the CRLF plus CRC with an * from the end + for (i = 0; i < strlen(nmea_data) - 5; i ++) { + 8001a3c: 2300 movs r3, #0 + 8001a3e: 613b str r3, [r7, #16] + 8001a40: e00a b.n 8001a58 + crc ^= nmea_data[i]; + 8001a42: 693b ldr r3, [r7, #16] + 8001a44: 687a ldr r2, [r7, #4] + 8001a46: 4413 add r3, r2 + 8001a48: 781b ldrb r3, [r3, #0] + 8001a4a: 461a mov r2, r3 + 8001a4c: 697b ldr r3, [r7, #20] + 8001a4e: 4053 eors r3, r2 + 8001a50: 617b str r3, [r7, #20] + for (i = 0; i < strlen(nmea_data) - 5; i ++) { + 8001a52: 693b ldr r3, [r7, #16] + 8001a54: 3301 adds r3, #1 + 8001a56: 613b str r3, [r7, #16] + 8001a58: 6878 ldr r0, [r7, #4] + 8001a5a: f7fe fc09 bl 8000270 + 8001a5e: 4603 mov r3, r0 + 8001a60: 1f5a subs r2, r3, #5 + 8001a62: 693b ldr r3, [r7, #16] + 8001a64: 429a cmp r2, r3 + 8001a66: d8ec bhi.n 8001a42 } - - // Draw in the right color - if(color == White) { - 8002174: 797b ldrb r3, [r7, #5] - 8002176: 2b01 cmp r3, #1 - 8002178: d11a bne.n 80021b0 - SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] |= 1 << (y % 8); - 800217a: 79fa ldrb r2, [r7, #7] - 800217c: 79bb ldrb r3, [r7, #6] - 800217e: 08db lsrs r3, r3, #3 - 8002180: b2d8 uxtb r0, r3 - 8002182: 4603 mov r3, r0 - 8002184: 01db lsls r3, r3, #7 - 8002186: 4413 add r3, r2 - 8002188: 4a1b ldr r2, [pc, #108] ; (80021f8 ) - 800218a: 5cd3 ldrb r3, [r2, r3] - 800218c: b25a sxtb r2, r3 - 800218e: 79bb ldrb r3, [r7, #6] - 8002190: f003 0307 and.w r3, r3, #7 - 8002194: 2101 movs r1, #1 - 8002196: fa01 f303 lsl.w r3, r1, r3 - 800219a: b25b sxtb r3, r3 - 800219c: 4313 orrs r3, r2 - 800219e: b259 sxtb r1, r3 - 80021a0: 79fa ldrb r2, [r7, #7] - 80021a2: 4603 mov r3, r0 - 80021a4: 01db lsls r3, r3, #7 - 80021a6: 4413 add r3, r2 - 80021a8: b2c9 uxtb r1, r1 - 80021aa: 4a13 ldr r2, [pc, #76] ; (80021f8 ) - 80021ac: 54d1 strb r1, [r2, r3] - 80021ae: e01d b.n 80021ec - } else { - SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] &= ~(1 << (y % 8)); - 80021b0: 79fa ldrb r2, [r7, #7] - 80021b2: 79bb ldrb r3, [r7, #6] - 80021b4: 08db lsrs r3, r3, #3 - 80021b6: b2d8 uxtb r0, r3 - 80021b8: 4603 mov r3, r0 - 80021ba: 01db lsls r3, r3, #7 - 80021bc: 4413 add r3, r2 - 80021be: 4a0e ldr r2, [pc, #56] ; (80021f8 ) - 80021c0: 5cd3 ldrb r3, [r2, r3] - 80021c2: b25a sxtb r2, r3 - 80021c4: 79bb ldrb r3, [r7, #6] - 80021c6: f003 0307 and.w r3, r3, #7 - 80021ca: 2101 movs r1, #1 - 80021cc: fa01 f303 lsl.w r3, r1, r3 - 80021d0: b25b sxtb r3, r3 - 80021d2: 43db mvns r3, r3 - 80021d4: b25b sxtb r3, r3 - 80021d6: 4013 ands r3, r2 - 80021d8: b259 sxtb r1, r3 - 80021da: 79fa ldrb r2, [r7, #7] - 80021dc: 4603 mov r3, r0 - 80021de: 01db lsls r3, r3, #7 - 80021e0: 4413 add r3, r2 - 80021e2: b2c9 uxtb r1, r1 - 80021e4: 4a04 ldr r2, [pc, #16] ; (80021f8 ) - 80021e6: 54d1 strb r1, [r2, r3] - 80021e8: e000 b.n 80021ec - return; - 80021ea: bf00 nop + int receivedHash = strtol(recv_crc, NULL, 16); + 8001a68: f107 0308 add.w r3, r7, #8 + 8001a6c: 2210 movs r2, #16 + 8001a6e: 2100 movs r1, #0 + 8001a70: 4618 mov r0, r3 + 8001a72: f012 fa71 bl 8013f58 + 8001a76: 60f8 str r0, [r7, #12] + if (crc == receivedHash) { + 8001a78: 697a ldr r2, [r7, #20] + 8001a7a: 68fb ldr r3, [r7, #12] + 8001a7c: 429a cmp r2, r3 + 8001a7e: d101 bne.n 8001a84 + return 1; + 8001a80: 2301 movs r3, #1 + 8001a82: e000 b.n 8001a86 } -} - 80021ec: 370c adds r7, #12 - 80021ee: 46bd mov sp, r7 - 80021f0: f85d 7b04 ldr.w r7, [sp], #4 - 80021f4: 4770 bx lr - 80021f6: bf00 nop - 80021f8: 20000878 .word 0x20000878 - -080021fc : - * Draw 1 char to the screen buffer - * ch => char om weg te schrijven - * Font => Font waarmee we gaan schrijven - * color => Black or White - */ -char ssd1306_WriteChar(char ch, FontDef Font, SSD1306_COLOR color) { - 80021fc: b590 push {r4, r7, lr} - 80021fe: b089 sub sp, #36 ; 0x24 - 8002200: af00 add r7, sp, #0 - 8002202: 4604 mov r4, r0 - 8002204: 1d38 adds r0, r7, #4 - 8002206: e880 0006 stmia.w r0, {r1, r2} - 800220a: 461a mov r2, r3 - 800220c: 4623 mov r3, r4 - 800220e: 73fb strb r3, [r7, #15] - 8002210: 4613 mov r3, r2 - 8002212: 73bb strb r3, [r7, #14] - uint32_t i, b, j; - - // Check if character is valid - if (ch < 32 || ch > 126) - 8002214: 7bfb ldrb r3, [r7, #15] - 8002216: 2b1f cmp r3, #31 - 8002218: d902 bls.n 8002220 - 800221a: 7bfb ldrb r3, [r7, #15] - 800221c: 2b7e cmp r3, #126 ; 0x7e - 800221e: d901 bls.n 8002224 - return 0; - 8002220: 2300 movs r3, #0 - 8002222: e06d b.n 8002300 - - // Check remaining space on current line - if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) || - 8002224: 4b38 ldr r3, [pc, #224] ; (8002308 ) - 8002226: 881b ldrh r3, [r3, #0] - 8002228: 461a mov r2, r3 - 800222a: 793b ldrb r3, [r7, #4] - 800222c: 4413 add r3, r2 - 800222e: 2b80 cmp r3, #128 ; 0x80 - 8002230: dc06 bgt.n 8002240 - SSD1306_HEIGHT < (SSD1306.CurrentY + Font.FontHeight)) - 8002232: 4b35 ldr r3, [pc, #212] ; (8002308 ) - 8002234: 885b ldrh r3, [r3, #2] - 8002236: 461a mov r2, r3 - 8002238: 797b ldrb r3, [r7, #5] - 800223a: 4413 add r3, r2 - if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) || - 800223c: 2b40 cmp r3, #64 ; 0x40 - 800223e: dd01 ble.n 8002244 - { - // Not enough space on current line + else{ return 0; - 8002240: 2300 movs r3, #0 - 8002242: e05d b.n 8002300 - } - - // Use the font to write - for(i = 0; i < Font.FontHeight; i++) { - 8002244: 2300 movs r3, #0 - 8002246: 61fb str r3, [r7, #28] - 8002248: e04c b.n 80022e4 - b = Font.data[(ch - 32) * Font.FontHeight + i]; - 800224a: 68ba ldr r2, [r7, #8] - 800224c: 7bfb ldrb r3, [r7, #15] - 800224e: 3b20 subs r3, #32 - 8002250: 7979 ldrb r1, [r7, #5] - 8002252: fb01 f303 mul.w r3, r1, r3 - 8002256: 4619 mov r1, r3 - 8002258: 69fb ldr r3, [r7, #28] - 800225a: 440b add r3, r1 - 800225c: 005b lsls r3, r3, #1 - 800225e: 4413 add r3, r2 - 8002260: 881b ldrh r3, [r3, #0] - 8002262: 617b str r3, [r7, #20] - for(j = 0; j < Font.FontWidth; j++) { - 8002264: 2300 movs r3, #0 - 8002266: 61bb str r3, [r7, #24] - 8002268: e034 b.n 80022d4 - if((b << j) & 0x8000) { - 800226a: 697a ldr r2, [r7, #20] - 800226c: 69bb ldr r3, [r7, #24] - 800226e: fa02 f303 lsl.w r3, r2, r3 - 8002272: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8002276: 2b00 cmp r3, #0 - 8002278: d012 beq.n 80022a0 - ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR) color); - 800227a: 4b23 ldr r3, [pc, #140] ; (8002308 ) - 800227c: 881b ldrh r3, [r3, #0] - 800227e: b2da uxtb r2, r3 - 8002280: 69bb ldr r3, [r7, #24] - 8002282: b2db uxtb r3, r3 - 8002284: 4413 add r3, r2 - 8002286: b2d8 uxtb r0, r3 - 8002288: 4b1f ldr r3, [pc, #124] ; (8002308 ) - 800228a: 885b ldrh r3, [r3, #2] - 800228c: b2da uxtb r2, r3 - 800228e: 69fb ldr r3, [r7, #28] - 8002290: b2db uxtb r3, r3 - 8002292: 4413 add r3, r2 - 8002294: b2db uxtb r3, r3 - 8002296: 7bba ldrb r2, [r7, #14] - 8002298: 4619 mov r1, r3 - 800229a: f7ff ff5b bl 8002154 - 800229e: e016 b.n 80022ce - } else { - ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR)!color); - 80022a0: 4b19 ldr r3, [pc, #100] ; (8002308 ) - 80022a2: 881b ldrh r3, [r3, #0] - 80022a4: b2da uxtb r2, r3 - 80022a6: 69bb ldr r3, [r7, #24] - 80022a8: b2db uxtb r3, r3 - 80022aa: 4413 add r3, r2 - 80022ac: b2d8 uxtb r0, r3 - 80022ae: 4b16 ldr r3, [pc, #88] ; (8002308 ) - 80022b0: 885b ldrh r3, [r3, #2] - 80022b2: b2da uxtb r2, r3 - 80022b4: 69fb ldr r3, [r7, #28] - 80022b6: b2db uxtb r3, r3 - 80022b8: 4413 add r3, r2 - 80022ba: b2d9 uxtb r1, r3 - 80022bc: 7bbb ldrb r3, [r7, #14] - 80022be: 2b00 cmp r3, #0 - 80022c0: bf0c ite eq - 80022c2: 2301 moveq r3, #1 - 80022c4: 2300 movne r3, #0 - 80022c6: b2db uxtb r3, r3 - 80022c8: 461a mov r2, r3 - 80022ca: f7ff ff43 bl 8002154 - for(j = 0; j < Font.FontWidth; j++) { - 80022ce: 69bb ldr r3, [r7, #24] - 80022d0: 3301 adds r3, #1 - 80022d2: 61bb str r3, [r7, #24] - 80022d4: 793b ldrb r3, [r7, #4] - 80022d6: 461a mov r2, r3 - 80022d8: 69bb ldr r3, [r7, #24] - 80022da: 4293 cmp r3, r2 - 80022dc: d3c5 bcc.n 800226a - for(i = 0; i < Font.FontHeight; i++) { - 80022de: 69fb ldr r3, [r7, #28] - 80022e0: 3301 adds r3, #1 - 80022e2: 61fb str r3, [r7, #28] - 80022e4: 797b ldrb r3, [r7, #5] - 80022e6: 461a mov r2, r3 - 80022e8: 69fb ldr r3, [r7, #28] - 80022ea: 4293 cmp r3, r2 - 80022ec: d3ad bcc.n 800224a - } - } + 8001a84: 2300 movs r3, #0 } - - // The current space is now taken - SSD1306.CurrentX += Font.FontWidth; - 80022ee: 4b06 ldr r3, [pc, #24] ; (8002308 ) - 80022f0: 881a ldrh r2, [r3, #0] - 80022f2: 793b ldrb r3, [r7, #4] - 80022f4: b29b uxth r3, r3 - 80022f6: 4413 add r3, r2 - 80022f8: b29a uxth r2, r3 - 80022fa: 4b03 ldr r3, [pc, #12] ; (8002308 ) - 80022fc: 801a strh r2, [r3, #0] - - // Return written char for validation - return ch; - 80022fe: 7bfb ldrb r3, [r7, #15] } - 8002300: 4618 mov r0, r3 - 8002302: 3724 adds r7, #36 ; 0x24 - 8002304: 46bd mov sp, r7 - 8002306: bd90 pop {r4, r7, pc} - 8002308: 20000c78 .word 0x20000c78 + 8001a86: 4618 mov r0, r3 + 8001a88: 3718 adds r7, #24 + 8001a8a: 46bd mov sp, r7 + 8001a8c: bd80 pop {r7, pc} + ... -0800230c : +08001a90 : -/* Write full string to screenbuffer */ -char ssd1306_WriteString(char* str, FontDef Font, SSD1306_COLOR color) { - 800230c: b580 push {r7, lr} - 800230e: b084 sub sp, #16 - 8002310: af00 add r7, sp, #0 - 8002312: 60f8 str r0, [r7, #12] - 8002314: 1d38 adds r0, r7, #4 - 8002316: e880 0006 stmia.w r0, {r1, r2} - 800231a: 70fb strb r3, [r7, #3] - while (*str) { - 800231c: e012 b.n 8002344 - if (ssd1306_WriteChar(*str, Font, color) != *str) { - 800231e: 68fb ldr r3, [r7, #12] - 8002320: 7818 ldrb r0, [r3, #0] - 8002322: 78fb ldrb r3, [r7, #3] - 8002324: 1d3a adds r2, r7, #4 - 8002326: ca06 ldmia r2, {r1, r2} - 8002328: f7ff ff68 bl 80021fc - 800232c: 4603 mov r3, r0 - 800232e: 461a mov r2, r3 - 8002330: 68fb ldr r3, [r7, #12] - 8002332: 781b ldrb r3, [r3, #0] - 8002334: 429a cmp r2, r3 - 8002336: d002 beq.n 800233e - // Char could not be written - return *str; - 8002338: 68fb ldr r3, [r7, #12] - 800233a: 781b ldrb r3, [r3, #0] - 800233c: e008 b.n 8002350 - } - str++; - 800233e: 68fb ldr r3, [r7, #12] - 8002340: 3301 adds r3, #1 - 8002342: 60fb str r3, [r7, #12] - while (*str) { - 8002344: 68fb ldr r3, [r7, #12] - 8002346: 781b ldrb r3, [r3, #0] - 8002348: 2b00 cmp r3, #0 - 800234a: d1e8 bne.n 800231e +int nmea_GPGGA(GPS *gps_data, char*inputString){ + 8001a90: b590 push {r4, r7, lr} + 8001a92: b0b7 sub sp, #220 ; 0xdc + 8001a94: af00 add r7, sp, #0 + 8001a96: 6078 str r0, [r7, #4] + 8001a98: 6039 str r1, [r7, #0] + char *values[25]; + int counter = 0; + 8001a9a: 2300 movs r3, #0 + 8001a9c: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + memset(values, 0, sizeof(values)); + 8001aa0: f107 0320 add.w r3, r7, #32 + 8001aa4: 2264 movs r2, #100 ; 0x64 + 8001aa6: 2100 movs r1, #0 + 8001aa8: 4618 mov r0, r3 + 8001aaa: f013 fa2e bl 8014f0a + char *marker = strtok(inputString, ","); + 8001aae: 49c2 ldr r1, [pc, #776] ; (8001db8 ) + 8001ab0: 6838 ldr r0, [r7, #0] + 8001ab2: f013 fa45 bl 8014f40 + 8001ab6: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0 + while (marker != NULL) { + 8001aba: e027 b.n 8001b0c + values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! + 8001abc: f8d7 00d0 ldr.w r0, [r7, #208] ; 0xd0 + 8001ac0: f7fe fbd6 bl 8000270 + 8001ac4: 4603 mov r3, r0 + 8001ac6: 1c5a adds r2, r3, #1 + 8001ac8: f8d7 40d4 ldr.w r4, [r7, #212] ; 0xd4 + 8001acc: 1c63 adds r3, r4, #1 + 8001ace: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + 8001ad2: 4610 mov r0, r2 + 8001ad4: f011 fa86 bl 8012fe4 + 8001ad8: 4603 mov r3, r0 + 8001ada: 461a mov r2, r3 + 8001adc: 00a3 lsls r3, r4, #2 + 8001ade: 33d8 adds r3, #216 ; 0xd8 + 8001ae0: 443b add r3, r7 + 8001ae2: f843 2cb8 str.w r2, [r3, #-184] + strcpy(values[counter - 1], marker); + 8001ae6: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 8001aea: 3b01 subs r3, #1 + 8001aec: 009b lsls r3, r3, #2 + 8001aee: 33d8 adds r3, #216 ; 0xd8 + 8001af0: 443b add r3, r7 + 8001af2: f853 3cb8 ldr.w r3, [r3, #-184] + 8001af6: f8d7 10d0 ldr.w r1, [r7, #208] ; 0xd0 + 8001afa: 4618 mov r0, r3 + 8001afc: f013 fb19 bl 8015132 + marker = strtok(NULL, ","); + 8001b00: 49ad ldr r1, [pc, #692] ; (8001db8 ) + 8001b02: 2000 movs r0, #0 + 8001b04: f013 fa1c bl 8014f40 + 8001b08: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0 + while (marker != NULL) { + 8001b0c: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0 + 8001b10: 2b00 cmp r3, #0 + 8001b12: d1d3 bne.n 8001abc } - - // Everything ok - return *str; - 800234c: 68fb ldr r3, [r7, #12] - 800234e: 781b ldrb r3, [r3, #0] -} - 8002350: 4618 mov r0, r3 - 8002352: 3710 adds r7, #16 - 8002354: 46bd mov sp, r7 - 8002356: bd80 pop {r7, pc} + char lonSide = values[5][0]; + 8001b14: 6b7b ldr r3, [r7, #52] ; 0x34 + 8001b16: 781b ldrb r3, [r3, #0] + 8001b18: f887 30b7 strb.w r3, [r7, #183] ; 0xb7 + char latSide = values[3][0]; + 8001b1c: 6afb ldr r3, [r7, #44] ; 0x2c + 8001b1e: 781b ldrb r3, [r3, #0] + 8001b20: f887 30b6 strb.w r3, [r7, #182] ; 0xb6 + strcpy(gps_data->lastMeasure, values[1]); + 8001b24: 687b ldr r3, [r7, #4] + 8001b26: 332c adds r3, #44 ; 0x2c + 8001b28: 6a7a ldr r2, [r7, #36] ; 0x24 + 8001b2a: 4611 mov r1, r2 + 8001b2c: 4618 mov r0, r3 + 8001b2e: f013 fb00 bl 8015132 + if(latSide == 'S' || latSide == 'N'){ + 8001b32: f897 30b6 ldrb.w r3, [r7, #182] ; 0xb6 + 8001b36: 2b53 cmp r3, #83 ; 0x53 + 8001b38: d004 beq.n 8001b44 + 8001b3a: f897 30b6 ldrb.w r3, [r7, #182] ; 0xb6 + 8001b3e: 2b4e cmp r3, #78 ; 0x4e + 8001b40: f040 8159 bne.w 8001df6 + char lat_d[2]; + char lat_m[7]; + for (int z = 0; z < 2; z++) lat_d[z] = values[2][z]; + 8001b44: 2300 movs r3, #0 + 8001b46: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + 8001b4a: e010 b.n 8001b6e + 8001b4c: 6aba ldr r2, [r7, #40] ; 0x28 + 8001b4e: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 8001b52: 4413 add r3, r2 + 8001b54: 7819 ldrb r1, [r3, #0] + 8001b56: f107 021c add.w r2, r7, #28 + 8001b5a: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 8001b5e: 4413 add r3, r2 + 8001b60: 460a mov r2, r1 + 8001b62: 701a strb r2, [r3, #0] + 8001b64: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 8001b68: 3301 adds r3, #1 + 8001b6a: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + 8001b6e: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 8001b72: 2b01 cmp r3, #1 + 8001b74: ddea ble.n 8001b4c + for (int z = 0; z < 6; z++) lat_m[z] = values[2][z + 2]; + 8001b76: 2300 movs r3, #0 + 8001b78: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 8001b7c: e011 b.n 8001ba2 + 8001b7e: 6aba ldr r2, [r7, #40] ; 0x28 + 8001b80: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8001b84: 3302 adds r3, #2 + 8001b86: 4413 add r3, r2 + 8001b88: 7819 ldrb r1, [r3, #0] + 8001b8a: f107 0214 add.w r2, r7, #20 + 8001b8e: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8001b92: 4413 add r3, r2 + 8001b94: 460a mov r2, r1 + 8001b96: 701a strb r2, [r3, #0] + 8001b98: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8001b9c: 3301 adds r3, #1 + 8001b9e: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 8001ba2: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8001ba6: 2b05 cmp r3, #5 + 8001ba8: dde9 ble.n 8001b7e -08002358 : + int lat_deg_strtol = strtol(lat_d, NULL, 10); + 8001baa: f107 031c add.w r3, r7, #28 + 8001bae: 220a movs r2, #10 + 8001bb0: 2100 movs r1, #0 + 8001bb2: 4618 mov r0, r3 + 8001bb4: f012 f9d0 bl 8013f58 + 8001bb8: f8c7 00b0 str.w r0, [r7, #176] ; 0xb0 + float lat_min_strtof = strtof(lat_m, NULL); + 8001bbc: f107 0314 add.w r3, r7, #20 + 8001bc0: 2100 movs r1, #0 + 8001bc2: 4618 mov r0, r3 + 8001bc4: f012 f8de bl 8013d84 + 8001bc8: ed87 0a2b vstr s0, [r7, #172] ; 0xac + double lat_deg = lat_deg_strtol + lat_min_strtof / 60; + 8001bcc: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 + 8001bd0: ee07 3a90 vmov s15, r3 + 8001bd4: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 8001bd8: edd7 6a2b vldr s13, [r7, #172] ; 0xac + 8001bdc: ed9f 6a77 vldr s12, [pc, #476] ; 8001dbc + 8001be0: eec6 7a86 vdiv.f32 s15, s13, s12 + 8001be4: ee77 7a27 vadd.f32 s15, s14, s15 + 8001be8: ee17 0a90 vmov r0, s15 + 8001bec: f7fe fcac bl 8000548 <__aeabi_f2d> + 8001bf0: 4602 mov r2, r0 + 8001bf2: 460b mov r3, r1 + 8001bf4: e9c7 2328 strd r2, r3, [r7, #160] ; 0xa0 -/* Position the cursor */ -void ssd1306_SetCursor(uint8_t x, uint8_t y) { - 8002358: b480 push {r7} - 800235a: b083 sub sp, #12 - 800235c: af00 add r7, sp, #0 - 800235e: 4603 mov r3, r0 - 8002360: 460a mov r2, r1 - 8002362: 71fb strb r3, [r7, #7] - 8002364: 4613 mov r3, r2 - 8002366: 71bb strb r3, [r7, #6] - SSD1306.CurrentX = x; - 8002368: 79fb ldrb r3, [r7, #7] - 800236a: b29a uxth r2, r3 - 800236c: 4b05 ldr r3, [pc, #20] ; (8002384 ) - 800236e: 801a strh r2, [r3, #0] - SSD1306.CurrentY = y; - 8002370: 79bb ldrb r3, [r7, #6] - 8002372: b29a uxth r2, r3 - 8002374: 4b03 ldr r3, [pc, #12] ; (8002384 ) - 8002376: 805a strh r2, [r3, #2] -} - 8002378: bf00 nop - 800237a: 370c adds r7, #12 - 800237c: 46bd mov sp, r7 - 800237e: f85d 7b04 ldr.w r7, [sp], #4 - 8002382: 4770 bx lr - 8002384: 20000c78 .word 0x20000c78 + char lon_d[3]; + char lon_m[7]; -08002388 : + for (int z = 0; z < 3; z++) lon_d[z] = values[4][z]; + 8001bf8: 2300 movs r3, #0 + 8001bfa: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 8001bfe: e010 b.n 8001c22 + 8001c00: 6b3a ldr r2, [r7, #48] ; 0x30 + 8001c02: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 8001c06: 4413 add r3, r2 + 8001c08: 7819 ldrb r1, [r3, #0] + 8001c0a: f107 0210 add.w r2, r7, #16 + 8001c0e: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 8001c12: 4413 add r3, r2 + 8001c14: 460a mov r2, r1 + 8001c16: 701a strb r2, [r3, #0] + 8001c18: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 8001c1c: 3301 adds r3, #1 + 8001c1e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 8001c22: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 8001c26: 2b02 cmp r3, #2 + 8001c28: ddea ble.n 8001c00 + for (int z = 0; z < 6; z++) lon_m[z] = values[4][z + 3]; + 8001c2a: 2300 movs r3, #0 + 8001c2c: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 8001c30: e011 b.n 8001c56 + 8001c32: 6b3a ldr r2, [r7, #48] ; 0x30 + 8001c34: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8001c38: 3303 adds r3, #3 + 8001c3a: 4413 add r3, r2 + 8001c3c: 7819 ldrb r1, [r3, #0] + 8001c3e: f107 0208 add.w r2, r7, #8 + 8001c42: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8001c46: 4413 add r3, r2 + 8001c48: 460a mov r2, r1 + 8001c4a: 701a strb r2, [r3, #0] + 8001c4c: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8001c50: 3301 adds r3, #1 + 8001c52: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 8001c56: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8001c5a: 2b05 cmp r3, #5 + 8001c5c: dde9 ble.n 8001c32 -/* Draw line by Bresenhem's algorithm */ -void ssd1306_Line(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { - 8002388: b590 push {r4, r7, lr} - 800238a: b089 sub sp, #36 ; 0x24 - 800238c: af00 add r7, sp, #0 - 800238e: 4604 mov r4, r0 - 8002390: 4608 mov r0, r1 - 8002392: 4611 mov r1, r2 - 8002394: 461a mov r2, r3 - 8002396: 4623 mov r3, r4 - 8002398: 71fb strb r3, [r7, #7] - 800239a: 4603 mov r3, r0 - 800239c: 71bb strb r3, [r7, #6] - 800239e: 460b mov r3, r1 - 80023a0: 717b strb r3, [r7, #5] - 80023a2: 4613 mov r3, r2 - 80023a4: 713b strb r3, [r7, #4] - int32_t deltaX = abs(x2 - x1); - 80023a6: 797a ldrb r2, [r7, #5] - 80023a8: 79fb ldrb r3, [r7, #7] - 80023aa: 1ad3 subs r3, r2, r3 - 80023ac: 2b00 cmp r3, #0 - 80023ae: bfb8 it lt - 80023b0: 425b neglt r3, r3 - 80023b2: 61bb str r3, [r7, #24] - int32_t deltaY = abs(y2 - y1); - 80023b4: 793a ldrb r2, [r7, #4] - 80023b6: 79bb ldrb r3, [r7, #6] - 80023b8: 1ad3 subs r3, r2, r3 - 80023ba: 2b00 cmp r3, #0 - 80023bc: bfb8 it lt - 80023be: 425b neglt r3, r3 - 80023c0: 617b str r3, [r7, #20] - int32_t signX = ((x1 < x2) ? 1 : -1); - 80023c2: 79fa ldrb r2, [r7, #7] - 80023c4: 797b ldrb r3, [r7, #5] - 80023c6: 429a cmp r2, r3 - 80023c8: d201 bcs.n 80023ce - 80023ca: 2301 movs r3, #1 - 80023cc: e001 b.n 80023d2 - 80023ce: f04f 33ff mov.w r3, #4294967295 - 80023d2: 613b str r3, [r7, #16] - int32_t signY = ((y1 < y2) ? 1 : -1); - 80023d4: 79ba ldrb r2, [r7, #6] - 80023d6: 793b ldrb r3, [r7, #4] - 80023d8: 429a cmp r2, r3 - 80023da: d201 bcs.n 80023e0 - 80023dc: 2301 movs r3, #1 - 80023de: e001 b.n 80023e4 - 80023e0: f04f 33ff mov.w r3, #4294967295 - 80023e4: 60fb str r3, [r7, #12] - int32_t error = deltaX - deltaY; - 80023e6: 69ba ldr r2, [r7, #24] - 80023e8: 697b ldr r3, [r7, #20] - 80023ea: 1ad3 subs r3, r2, r3 - 80023ec: 61fb str r3, [r7, #28] - int32_t error2; - - ssd1306_DrawPixel(x2, y2, color); - 80023ee: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 - 80023f2: 7939 ldrb r1, [r7, #4] - 80023f4: 797b ldrb r3, [r7, #5] - 80023f6: 4618 mov r0, r3 - 80023f8: f7ff feac bl 8002154 + int lon_deg_strtol = strtol(lon_d, NULL, 10); + 8001c5e: f107 0310 add.w r3, r7, #16 + 8001c62: 220a movs r2, #10 + 8001c64: 2100 movs r1, #0 + 8001c66: 4618 mov r0, r3 + 8001c68: f012 f976 bl 8013f58 + 8001c6c: f8c7 009c str.w r0, [r7, #156] ; 0x9c + float lon_min_strtof = strtof(lon_m, NULL); + 8001c70: f107 0308 add.w r3, r7, #8 + 8001c74: 2100 movs r1, #0 + 8001c76: 4618 mov r0, r3 + 8001c78: f012 f884 bl 8013d84 + 8001c7c: ed87 0a26 vstr s0, [r7, #152] ; 0x98 + double lon_deg = lon_deg_strtol + lon_min_strtof / 60; + 8001c80: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 8001c84: ee07 3a90 vmov s15, r3 + 8001c88: eeb8 7ae7 vcvt.f32.s32 s14, s15 + 8001c8c: edd7 6a26 vldr s13, [r7, #152] ; 0x98 + 8001c90: ed9f 6a4a vldr s12, [pc, #296] ; 8001dbc + 8001c94: eec6 7a86 vdiv.f32 s15, s13, s12 + 8001c98: ee77 7a27 vadd.f32 s15, s14, s15 + 8001c9c: ee17 0a90 vmov r0, s15 + 8001ca0: f7fe fc52 bl 8000548 <__aeabi_f2d> + 8001ca4: 4602 mov r2, r0 + 8001ca6: 460b mov r3, r1 + 8001ca8: e9c7 2324 strd r2, r3, [r7, #144] ; 0x90 - while((x1 != x2) || (y1 != y2)) { - 80023fc: e024 b.n 8002448 - ssd1306_DrawPixel(x1, y1, color); - 80023fe: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 - 8002402: 79b9 ldrb r1, [r7, #6] - 8002404: 79fb ldrb r3, [r7, #7] - 8002406: 4618 mov r0, r3 - 8002408: f7ff fea4 bl 8002154 - error2 = error * 2; - 800240c: 69fb ldr r3, [r7, #28] - 800240e: 005b lsls r3, r3, #1 - 8002410: 60bb str r3, [r7, #8] - if(error2 > -deltaY) { - 8002412: 697b ldr r3, [r7, #20] - 8002414: 425b negs r3, r3 - 8002416: 68ba ldr r2, [r7, #8] - 8002418: 429a cmp r2, r3 - 800241a: dd08 ble.n 800242e - error -= deltaY; - 800241c: 69fa ldr r2, [r7, #28] - 800241e: 697b ldr r3, [r7, #20] - 8002420: 1ad3 subs r3, r2, r3 - 8002422: 61fb str r3, [r7, #28] - x1 += signX; - 8002424: 693b ldr r3, [r7, #16] - 8002426: b2da uxtb r2, r3 - 8002428: 79fb ldrb r3, [r7, #7] - 800242a: 4413 add r3, r2 - 800242c: 71fb strb r3, [r7, #7] + if(lat_deg!=0 && lon_deg!=0 && lat_deg<90 && lon_deg<180){ + 8001cac: f04f 0200 mov.w r2, #0 + 8001cb0: f04f 0300 mov.w r3, #0 + 8001cb4: e9d7 0128 ldrd r0, r1, [r7, #160] ; 0xa0 + 8001cb8: f7fe ff06 bl 8000ac8 <__aeabi_dcmpeq> + 8001cbc: 4603 mov r3, r0 + 8001cbe: 2b00 cmp r3, #0 + 8001cc0: d176 bne.n 8001db0 + 8001cc2: f04f 0200 mov.w r2, #0 + 8001cc6: f04f 0300 mov.w r3, #0 + 8001cca: e9d7 0124 ldrd r0, r1, [r7, #144] ; 0x90 + 8001cce: f7fe fefb bl 8000ac8 <__aeabi_dcmpeq> + 8001cd2: 4603 mov r3, r0 + 8001cd4: 2b00 cmp r3, #0 + 8001cd6: d16b bne.n 8001db0 + 8001cd8: f04f 0200 mov.w r2, #0 + 8001cdc: 4b38 ldr r3, [pc, #224] ; (8001dc0 ) + 8001cde: e9d7 0128 ldrd r0, r1, [r7, #160] ; 0xa0 + 8001ce2: f7fe fefb bl 8000adc <__aeabi_dcmplt> + 8001ce6: 4603 mov r3, r0 + 8001ce8: 2b00 cmp r3, #0 + 8001cea: d061 beq.n 8001db0 + 8001cec: f04f 0200 mov.w r2, #0 + 8001cf0: 4b34 ldr r3, [pc, #208] ; (8001dc4 ) + 8001cf2: e9d7 0124 ldrd r0, r1, [r7, #144] ; 0x90 + 8001cf6: f7fe fef1 bl 8000adc <__aeabi_dcmplt> + 8001cfa: 4603 mov r3, r0 + 8001cfc: 2b00 cmp r3, #0 + 8001cfe: d057 beq.n 8001db0 + gps_data->latitude = lat_deg; + 8001d00: 6879 ldr r1, [r7, #4] + 8001d02: e9d7 2328 ldrd r2, r3, [r7, #160] ; 0xa0 + 8001d06: e9c1 2300 strd r2, r3, [r1] + gps_data->latSide = latSide; + 8001d0a: 687b ldr r3, [r7, #4] + 8001d0c: f897 20b6 ldrb.w r2, [r7, #182] ; 0xb6 + 8001d10: 721a strb r2, [r3, #8] + gps_data->longitude = lon_deg; + 8001d12: 6879 ldr r1, [r7, #4] + 8001d14: e9d7 2324 ldrd r2, r3, [r7, #144] ; 0x90 + 8001d18: e9c1 2304 strd r2, r3, [r1, #16] + gps_data->lonSide = lonSide; + 8001d1c: 687b ldr r3, [r7, #4] + 8001d1e: f897 20b7 ldrb.w r2, [r7, #183] ; 0xb7 + 8001d22: 761a strb r2, [r3, #24] + float altitude = strtof(values[9], NULL); + 8001d24: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001d26: 2100 movs r1, #0 + 8001d28: 4618 mov r0, r3 + 8001d2a: f012 f82b bl 8013d84 + 8001d2e: ed87 0a23 vstr s0, [r7, #140] ; 0x8c + gps_data->altitude = altitude!=0 ? altitude : gps_data->altitude; + 8001d32: edd7 7a23 vldr s15, [r7, #140] ; 0x8c + 8001d36: eef5 7a40 vcmp.f32 s15, #0.0 + 8001d3a: eef1 fa10 vmrs APSR_nzcv, fpscr + 8001d3e: d102 bne.n 8001d46 + 8001d40: 687b ldr r3, [r7, #4] + 8001d42: 69db ldr r3, [r3, #28] + 8001d44: e001 b.n 8001d4a + 8001d46: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8001d4a: 687a ldr r2, [r7, #4] + 8001d4c: 61d3 str r3, [r2, #28] + gps_data->satelliteCount = strtol(values[7], NULL, 10); + 8001d4e: 6bfb ldr r3, [r7, #60] ; 0x3c + 8001d50: 220a movs r2, #10 + 8001d52: 2100 movs r1, #0 + 8001d54: 4618 mov r0, r3 + 8001d56: f012 f8ff bl 8013f58 + 8001d5a: 4602 mov r2, r0 + 8001d5c: 687b ldr r3, [r7, #4] + 8001d5e: 625a str r2, [r3, #36] ; 0x24 + + int fixQuality = strtol(values[6], NULL, 10); + 8001d60: 6bbb ldr r3, [r7, #56] ; 0x38 + 8001d62: 220a movs r2, #10 + 8001d64: 2100 movs r1, #0 + 8001d66: 4618 mov r0, r3 + 8001d68: f012 f8f6 bl 8013f58 + 8001d6c: f8c7 0088 str.w r0, [r7, #136] ; 0x88 + gps_data->fix = fixQuality > 0 ? 1 : 0; + 8001d70: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 + 8001d74: 2b00 cmp r3, #0 + 8001d76: bfcc ite gt + 8001d78: 2301 movgt r3, #1 + 8001d7a: 2300 movle r3, #0 + 8001d7c: b2db uxtb r3, r3 + 8001d7e: 461a mov r2, r3 + 8001d80: 687b ldr r3, [r7, #4] + 8001d82: 629a str r2, [r3, #40] ; 0x28 + + float hdop = strtof(values[8], NULL); + 8001d84: 6c3b ldr r3, [r7, #64] ; 0x40 + 8001d86: 2100 movs r1, #0 + 8001d88: 4618 mov r0, r3 + 8001d8a: f011 fffb bl 8013d84 + 8001d8e: ed87 0a21 vstr s0, [r7, #132] ; 0x84 + gps_data->hdop = hdop!=0 ? hdop : gps_data->hdop; + 8001d92: edd7 7a21 vldr s15, [r7, #132] ; 0x84 + 8001d96: eef5 7a40 vcmp.f32 s15, #0.0 + 8001d9a: eef1 fa10 vmrs APSR_nzcv, fpscr + 8001d9e: d102 bne.n 8001da6 + 8001da0: 687b ldr r3, [r7, #4] + 8001da2: 6a1b ldr r3, [r3, #32] + 8001da4: e001 b.n 8001daa + 8001da6: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 8001daa: 687a ldr r2, [r7, #4] + 8001dac: 6213 str r3, [r2, #32] + if(lat_deg!=0 && lon_deg!=0 && lat_deg<90 && lon_deg<180){ + 8001dae: e022 b.n 8001df6 } - - if(error2 < deltaX) { - 800242e: 68ba ldr r2, [r7, #8] - 8002430: 69bb ldr r3, [r7, #24] - 8002432: 429a cmp r2, r3 - 8002434: da08 bge.n 8002448 - error += deltaX; - 8002436: 69fa ldr r2, [r7, #28] - 8002438: 69bb ldr r3, [r7, #24] - 800243a: 4413 add r3, r2 - 800243c: 61fb str r3, [r7, #28] - y1 += signY; - 800243e: 68fb ldr r3, [r7, #12] - 8002440: b2da uxtb r2, r3 - 8002442: 79bb ldrb r3, [r7, #6] - 8002444: 4413 add r3, r2 - 8002446: 71bb strb r3, [r7, #6] - while((x1 != x2) || (y1 != y2)) { - 8002448: 79fa ldrb r2, [r7, #7] - 800244a: 797b ldrb r3, [r7, #5] - 800244c: 429a cmp r2, r3 - 800244e: d1d6 bne.n 80023fe - 8002450: 79ba ldrb r2, [r7, #6] - 8002452: 793b ldrb r3, [r7, #4] - 8002454: 429a cmp r2, r3 - 8002456: d1d2 bne.n 80023fe + else { + for(int i=0; i + 8001db8: 08018d98 .word 0x08018d98 + 8001dbc: 42700000 .word 0x42700000 + 8001dc0: 40568000 .word 0x40568000 + 8001dc4: 40668000 .word 0x40668000 + 8001dc8: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 8001dcc: 009b lsls r3, r3, #2 + 8001dce: 33d8 adds r3, #216 ; 0xd8 + 8001dd0: 443b add r3, r7 + 8001dd2: f853 3cb8 ldr.w r3, [r3, #-184] + 8001dd6: 4618 mov r0, r3 + 8001dd8: f011 f90c bl 8012ff4 + 8001ddc: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 8001de0: 3301 adds r3, #1 + 8001de2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 8001de6: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc + 8001dea: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 8001dee: 429a cmp r2, r3 + 8001df0: dbea blt.n 8001dc8 + return 0; + 8001df2: 2300 movs r3, #0 + 8001df4: e019 b.n 8001e2a } + } - return; - 8002458: bf00 nop + + for(int i=0; i + 8001dfe: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 8001e02: 009b lsls r3, r3, #2 + 8001e04: 33d8 adds r3, #216 ; 0xd8 + 8001e06: 443b add r3, r7 + 8001e08: f853 3cb8 ldr.w r3, [r3, #-184] + 8001e0c: 4618 mov r0, r3 + 8001e0e: f011 f8f1 bl 8012ff4 + 8001e12: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 8001e16: 3301 adds r3, #1 + 8001e18: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 8001e1c: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8 + 8001e20: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 8001e24: 429a cmp r2, r3 + 8001e26: dbea blt.n 8001dfe + return 1; + 8001e28: 2301 movs r3, #1 } - 800245a: 3724 adds r7, #36 ; 0x24 - 800245c: 46bd mov sp, r7 - 800245e: bd90 pop {r4, r7, pc} + 8001e2a: 4618 mov r0, r3 + 8001e2c: 37dc adds r7, #220 ; 0xdc + 8001e2e: 46bd mov sp, r7 + 8001e30: bd90 pop {r4, r7, pc} + 8001e32: bf00 nop -08002460 : - ssd1306_Line(x,y,xp2,yp2,color); - return; -} +08001e34 : -/* Draw circle by Bresenhem's algorithm */ -void ssd1306_DrawCircle(uint8_t par_x,uint8_t par_y,uint8_t par_r,SSD1306_COLOR par_color) { - 8002460: b590 push {r4, r7, lr} - 8002462: b087 sub sp, #28 - 8002464: af00 add r7, sp, #0 - 8002466: 4604 mov r4, r0 - 8002468: 4608 mov r0, r1 - 800246a: 4611 mov r1, r2 - 800246c: 461a mov r2, r3 - 800246e: 4623 mov r3, r4 - 8002470: 71fb strb r3, [r7, #7] - 8002472: 4603 mov r3, r0 - 8002474: 71bb strb r3, [r7, #6] - 8002476: 460b mov r3, r1 - 8002478: 717b strb r3, [r7, #5] - 800247a: 4613 mov r3, r2 - 800247c: 713b strb r3, [r7, #4] - int32_t x = -par_r; - 800247e: 797b ldrb r3, [r7, #5] - 8002480: 425b negs r3, r3 - 8002482: 617b str r3, [r7, #20] - int32_t y = 0; - 8002484: 2300 movs r3, #0 - 8002486: 613b str r3, [r7, #16] - int32_t err = 2 - 2 * par_r; - 8002488: 797b ldrb r3, [r7, #5] - 800248a: f1c3 0301 rsb r3, r3, #1 - 800248e: 005b lsls r3, r3, #1 - 8002490: 60fb str r3, [r7, #12] - int32_t e2; - if (par_x >= SSD1306_WIDTH || par_y >= SSD1306_HEIGHT) { - 8002492: f997 3007 ldrsb.w r3, [r7, #7] - 8002496: 2b00 cmp r3, #0 - 8002498: db65 blt.n 8002566 - 800249a: 79bb ldrb r3, [r7, #6] - 800249c: 2b3f cmp r3, #63 ; 0x3f - 800249e: d862 bhi.n 8002566 - return; +int nmea_GPGSA(GPS *gps_data, char*inputString){ + 8001e34: b590 push {r4, r7, lr} + 8001e36: b0a3 sub sp, #140 ; 0x8c + 8001e38: af00 add r7, sp, #0 + 8001e3a: 6078 str r0, [r7, #4] + 8001e3c: 6039 str r1, [r7, #0] + char *values[25]; + int counter = 0; + 8001e3e: 2300 movs r3, #0 + 8001e40: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + memset(values, 0, sizeof(values)); + 8001e44: f107 030c add.w r3, r7, #12 + 8001e48: 2264 movs r2, #100 ; 0x64 + 8001e4a: 2100 movs r1, #0 + 8001e4c: 4618 mov r0, r3 + 8001e4e: f013 f85c bl 8014f0a + char *marker = strtok(inputString, ","); + 8001e52: 493b ldr r1, [pc, #236] ; (8001f40 ) + 8001e54: 6838 ldr r0, [r7, #0] + 8001e56: f013 f873 bl 8014f40 + 8001e5a: f8c7 0080 str.w r0, [r7, #128] ; 0x80 + while (marker != NULL) { + 8001e5e: e027 b.n 8001eb0 + values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! + 8001e60: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 + 8001e64: f7fe fa04 bl 8000270 + 8001e68: 4603 mov r3, r0 + 8001e6a: 1c5a adds r2, r3, #1 + 8001e6c: f8d7 4084 ldr.w r4, [r7, #132] ; 0x84 + 8001e70: 1c63 adds r3, r4, #1 + 8001e72: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 8001e76: 4610 mov r0, r2 + 8001e78: f011 f8b4 bl 8012fe4 + 8001e7c: 4603 mov r3, r0 + 8001e7e: 461a mov r2, r3 + 8001e80: 00a3 lsls r3, r4, #2 + 8001e82: 3388 adds r3, #136 ; 0x88 + 8001e84: 443b add r3, r7 + 8001e86: f843 2c7c str.w r2, [r3, #-124] + strcpy(values[counter - 1], marker); + 8001e8a: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 8001e8e: 3b01 subs r3, #1 + 8001e90: 009b lsls r3, r3, #2 + 8001e92: 3388 adds r3, #136 ; 0x88 + 8001e94: 443b add r3, r7 + 8001e96: f853 3c7c ldr.w r3, [r3, #-124] + 8001e9a: f8d7 1080 ldr.w r1, [r7, #128] ; 0x80 + 8001e9e: 4618 mov r0, r3 + 8001ea0: f013 f947 bl 8015132 + marker = strtok(NULL, ","); + 8001ea4: 4926 ldr r1, [pc, #152] ; (8001f40 ) + 8001ea6: 2000 movs r0, #0 + 8001ea8: f013 f84a bl 8014f40 + 8001eac: f8c7 0080 str.w r0, [r7, #128] ; 0x80 + while (marker != NULL) { + 8001eb0: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 8001eb4: 2b00 cmp r3, #0 + 8001eb6: d1d3 bne.n 8001e60 + } + int fix = strtol(values[2], NULL, 10); + 8001eb8: 697b ldr r3, [r7, #20] + 8001eba: 220a movs r2, #10 + 8001ebc: 2100 movs r1, #0 + 8001ebe: 4618 mov r0, r3 + 8001ec0: f012 f84a bl 8013f58 + 8001ec4: 6738 str r0, [r7, #112] ; 0x70 + gps_data->fix = fix > 1 ? 1 : 0; + 8001ec6: 6f3b ldr r3, [r7, #112] ; 0x70 + 8001ec8: 2b01 cmp r3, #1 + 8001eca: bfcc ite gt + 8001ecc: 2301 movgt r3, #1 + 8001ece: 2300 movle r3, #0 + 8001ed0: b2db uxtb r3, r3 + 8001ed2: 461a mov r2, r3 + 8001ed4: 687b ldr r3, [r7, #4] + 8001ed6: 629a str r2, [r3, #40] ; 0x28 + int satelliteCount = 0; + 8001ed8: 2300 movs r3, #0 + 8001eda: 67fb str r3, [r7, #124] ; 0x7c + for(int i=3; i<15; i++){ + 8001edc: 2303 movs r3, #3 + 8001ede: 67bb str r3, [r7, #120] ; 0x78 + 8001ee0: e00e b.n 8001f00 + if(values[i][0] != '\0'){ + 8001ee2: 6fbb ldr r3, [r7, #120] ; 0x78 + 8001ee4: 009b lsls r3, r3, #2 + 8001ee6: 3388 adds r3, #136 ; 0x88 + 8001ee8: 443b add r3, r7 + 8001eea: f853 3c7c ldr.w r3, [r3, #-124] + 8001eee: 781b ldrb r3, [r3, #0] + 8001ef0: 2b00 cmp r3, #0 + 8001ef2: d002 beq.n 8001efa + satelliteCount++; + 8001ef4: 6ffb ldr r3, [r7, #124] ; 0x7c + 8001ef6: 3301 adds r3, #1 + 8001ef8: 67fb str r3, [r7, #124] ; 0x7c + for(int i=3; i<15; i++){ + 8001efa: 6fbb ldr r3, [r7, #120] ; 0x78 + 8001efc: 3301 adds r3, #1 + 8001efe: 67bb str r3, [r7, #120] ; 0x78 + 8001f00: 6fbb ldr r3, [r7, #120] ; 0x78 + 8001f02: 2b0e cmp r3, #14 + 8001f04: dded ble.n 8001ee2 + } } + gps_data->satelliteCount = satelliteCount; + 8001f06: 687b ldr r3, [r7, #4] + 8001f08: 6ffa ldr r2, [r7, #124] ; 0x7c + 8001f0a: 625a str r2, [r3, #36] ; 0x24 + for(int i=0; i + 8001f12: 6f7b ldr r3, [r7, #116] ; 0x74 + 8001f14: 009b lsls r3, r3, #2 + 8001f16: 3388 adds r3, #136 ; 0x88 + 8001f18: 443b add r3, r7 + 8001f1a: f853 3c7c ldr.w r3, [r3, #-124] + 8001f1e: 4618 mov r0, r3 + 8001f20: f011 f868 bl 8012ff4 + 8001f24: 6f7b ldr r3, [r7, #116] ; 0x74 + 8001f26: 3301 adds r3, #1 + 8001f28: 677b str r3, [r7, #116] ; 0x74 + 8001f2a: 6f7a ldr r2, [r7, #116] ; 0x74 + 8001f2c: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 8001f30: 429a cmp r2, r3 + 8001f32: dbee blt.n 8001f12 + return 1; + 8001f34: 2301 movs r3, #1 +} + 8001f36: 4618 mov r0, r3 + 8001f38: 378c adds r7, #140 ; 0x8c + 8001f3a: 46bd mov sp, r7 + 8001f3c: bd90 pop {r4, r7, pc} + 8001f3e: bf00 nop + 8001f40: 08018d98 .word 0x08018d98 + 8001f44: 00000000 .word 0x00000000 - do { - ssd1306_DrawPixel(par_x - x, par_y + y, par_color); - 80024a0: 697b ldr r3, [r7, #20] - 80024a2: b2db uxtb r3, r3 - 80024a4: 79fa ldrb r2, [r7, #7] - 80024a6: 1ad3 subs r3, r2, r3 - 80024a8: b2d8 uxtb r0, r3 - 80024aa: 693b ldr r3, [r7, #16] - 80024ac: b2da uxtb r2, r3 - 80024ae: 79bb ldrb r3, [r7, #6] - 80024b0: 4413 add r3, r2 - 80024b2: b2db uxtb r3, r3 - 80024b4: 793a ldrb r2, [r7, #4] - 80024b6: 4619 mov r1, r3 - 80024b8: f7ff fe4c bl 8002154 - ssd1306_DrawPixel(par_x + x, par_y + y, par_color); - 80024bc: 697b ldr r3, [r7, #20] - 80024be: b2da uxtb r2, r3 - 80024c0: 79fb ldrb r3, [r7, #7] - 80024c2: 4413 add r3, r2 - 80024c4: b2d8 uxtb r0, r3 - 80024c6: 693b ldr r3, [r7, #16] - 80024c8: b2da uxtb r2, r3 - 80024ca: 79bb ldrb r3, [r7, #6] - 80024cc: 4413 add r3, r2 - 80024ce: b2db uxtb r3, r3 - 80024d0: 793a ldrb r2, [r7, #4] - 80024d2: 4619 mov r1, r3 - 80024d4: f7ff fe3e bl 8002154 - ssd1306_DrawPixel(par_x + x, par_y - y, par_color); - 80024d8: 697b ldr r3, [r7, #20] - 80024da: b2da uxtb r2, r3 - 80024dc: 79fb ldrb r3, [r7, #7] - 80024de: 4413 add r3, r2 - 80024e0: b2d8 uxtb r0, r3 - 80024e2: 693b ldr r3, [r7, #16] - 80024e4: b2db uxtb r3, r3 - 80024e6: 79ba ldrb r2, [r7, #6] - 80024e8: 1ad3 subs r3, r2, r3 - 80024ea: b2db uxtb r3, r3 - 80024ec: 793a ldrb r2, [r7, #4] - 80024ee: 4619 mov r1, r3 - 80024f0: f7ff fe30 bl 8002154 - ssd1306_DrawPixel(par_x - x, par_y - y, par_color); - 80024f4: 697b ldr r3, [r7, #20] - 80024f6: b2db uxtb r3, r3 - 80024f8: 79fa ldrb r2, [r7, #7] - 80024fa: 1ad3 subs r3, r2, r3 - 80024fc: b2d8 uxtb r0, r3 - 80024fe: 693b ldr r3, [r7, #16] - 8002500: b2db uxtb r3, r3 - 8002502: 79ba ldrb r2, [r7, #6] - 8002504: 1ad3 subs r3, r2, r3 - 8002506: b2db uxtb r3, r3 - 8002508: 793a ldrb r2, [r7, #4] - 800250a: 4619 mov r1, r3 - 800250c: f7ff fe22 bl 8002154 - e2 = err; - 8002510: 68fb ldr r3, [r7, #12] - 8002512: 60bb str r3, [r7, #8] +08001f48 : - if (e2 <= y) { - 8002514: 68ba ldr r2, [r7, #8] - 8002516: 693b ldr r3, [r7, #16] - 8002518: 429a cmp r2, r3 - 800251a: dc13 bgt.n 8002544 - y++; - 800251c: 693b ldr r3, [r7, #16] - 800251e: 3301 adds r3, #1 - 8002520: 613b str r3, [r7, #16] - err = err + (y * 2 + 1); - 8002522: 693b ldr r3, [r7, #16] - 8002524: 005b lsls r3, r3, #1 - 8002526: 3301 adds r3, #1 - 8002528: 68fa ldr r2, [r7, #12] - 800252a: 4413 add r3, r2 - 800252c: 60fb str r3, [r7, #12] - if(-x == y && e2 <= x) { - 800252e: 697b ldr r3, [r7, #20] - 8002530: 425b negs r3, r3 - 8002532: 693a ldr r2, [r7, #16] - 8002534: 429a cmp r2, r3 - 8002536: d105 bne.n 8002544 - 8002538: 68ba ldr r2, [r7, #8] - 800253a: 697b ldr r3, [r7, #20] - 800253c: 429a cmp r2, r3 - 800253e: dc01 bgt.n 8002544 - e2 = 0; - 8002540: 2300 movs r3, #0 - 8002542: 60bb str r3, [r7, #8] - } - } - if (e2 > x) { - 8002544: 68ba ldr r2, [r7, #8] - 8002546: 697b ldr r3, [r7, #20] - 8002548: 429a cmp r2, r3 - 800254a: dd08 ble.n 800255e - x++; - 800254c: 697b ldr r3, [r7, #20] - 800254e: 3301 adds r3, #1 - 8002550: 617b str r3, [r7, #20] - err = err + (x * 2 + 1); - 8002552: 697b ldr r3, [r7, #20] - 8002554: 005b lsls r3, r3, #1 - 8002556: 3301 adds r3, #1 - 8002558: 68fa ldr r2, [r7, #12] - 800255a: 4413 add r3, r2 - 800255c: 60fb str r3, [r7, #12] - } - } while (x <= 0); - 800255e: 697b ldr r3, [r7, #20] - 8002560: 2b00 cmp r3, #0 - 8002562: dd9d ble.n 80024a0 - return; - 8002564: e000 b.n 8002568 - return; - 8002566: bf00 nop -} - 8002568: 371c adds r7, #28 - 800256a: 46bd mov sp, r7 - 800256c: bd90 pop {r4, r7, pc} +int nmea_GNRMC(GPS *gps_data, char*inputString){ + 8001f48: b590 push {r4, r7, lr} + 8001f4a: b0a1 sub sp, #132 ; 0x84 + 8001f4c: af00 add r7, sp, #0 + 8001f4e: 6078 str r0, [r7, #4] + 8001f50: 6039 str r1, [r7, #0] + char *values[25]; + int counter = 0; + 8001f52: 2300 movs r3, #0 + 8001f54: 67fb str r3, [r7, #124] ; 0x7c + memset(values, 0, sizeof(values)); + 8001f56: f107 030c add.w r3, r7, #12 + 8001f5a: 2264 movs r2, #100 ; 0x64 + 8001f5c: 2100 movs r1, #0 + 8001f5e: 4618 mov r0, r3 + 8001f60: f012 ffd3 bl 8014f0a + char *marker = strtok(inputString, ","); + 8001f64: 4930 ldr r1, [pc, #192] ; (8002028 ) + 8001f66: 6838 ldr r0, [r7, #0] + 8001f68: f012 ffea bl 8014f40 + 8001f6c: 67b8 str r0, [r7, #120] ; 0x78 + while (marker != NULL) { + 8001f6e: e021 b.n 8001fb4 + values[counter++] = malloc(strlen(marker) + 1); //free later!!!!!! + 8001f70: 6fb8 ldr r0, [r7, #120] ; 0x78 + 8001f72: f7fe f97d bl 8000270 + 8001f76: 4603 mov r3, r0 + 8001f78: 1c5a adds r2, r3, #1 + 8001f7a: 6ffc ldr r4, [r7, #124] ; 0x7c + 8001f7c: 1c63 adds r3, r4, #1 + 8001f7e: 67fb str r3, [r7, #124] ; 0x7c + 8001f80: 4610 mov r0, r2 + 8001f82: f011 f82f bl 8012fe4 + 8001f86: 4603 mov r3, r0 + 8001f88: 461a mov r2, r3 + 8001f8a: 00a3 lsls r3, r4, #2 + 8001f8c: 3380 adds r3, #128 ; 0x80 + 8001f8e: 443b add r3, r7 + 8001f90: f843 2c74 str.w r2, [r3, #-116] + strcpy(values[counter - 1], marker); + 8001f94: 6ffb ldr r3, [r7, #124] ; 0x7c + 8001f96: 3b01 subs r3, #1 + 8001f98: 009b lsls r3, r3, #2 + 8001f9a: 3380 adds r3, #128 ; 0x80 + 8001f9c: 443b add r3, r7 + 8001f9e: f853 3c74 ldr.w r3, [r3, #-116] + 8001fa2: 6fb9 ldr r1, [r7, #120] ; 0x78 + 8001fa4: 4618 mov r0, r3 + 8001fa6: f013 f8c4 bl 8015132 + marker = strtok(NULL, ","); + 8001faa: 491f ldr r1, [pc, #124] ; (8002028 ) + 8001fac: 2000 movs r0, #0 + 8001fae: f012 ffc7 bl 8014f40 + 8001fb2: 67b8 str r0, [r7, #120] ; 0x78 + while (marker != NULL) { + 8001fb4: 6fbb ldr r3, [r7, #120] ; 0x78 + 8001fb6: 2b00 cmp r3, #0 + 8001fb8: d1da bne.n 8001f70 + } + float speed = strtof(values[7], NULL); + 8001fba: 6abb ldr r3, [r7, #40] ; 0x28 + 8001fbc: 2100 movs r1, #0 + 8001fbe: 4618 mov r0, r3 + 8001fc0: f011 fee0 bl 8013d84 + 8001fc4: ed87 0a1c vstr s0, [r7, #112] ; 0x70 + gps_data->speed=speed/(1.944); + 8001fc8: 6f38 ldr r0, [r7, #112] ; 0x70 + 8001fca: f7fe fabd bl 8000548 <__aeabi_f2d> + 8001fce: a314 add r3, pc, #80 ; (adr r3, 8002020 ) + 8001fd0: e9d3 2300 ldrd r2, r3, [r3] + 8001fd4: f7fe fc3a bl 800084c <__aeabi_ddiv> + 8001fd8: 4602 mov r2, r0 + 8001fda: 460b mov r3, r1 + 8001fdc: 4610 mov r0, r2 + 8001fde: 4619 mov r1, r3 + 8001fe0: f7fe fe02 bl 8000be8 <__aeabi_d2f> + 8001fe4: 4602 mov r2, r0 + 8001fe6: 687b ldr r3, [r7, #4] + 8001fe8: 639a str r2, [r3, #56] ; 0x38 -0800256e : - return; + for(int i=0; i + 8001ff0: 6f7b ldr r3, [r7, #116] ; 0x74 + 8001ff2: 009b lsls r3, r3, #2 + 8001ff4: 3380 adds r3, #128 ; 0x80 + 8001ff6: 443b add r3, r7 + 8001ff8: f853 3c74 ldr.w r3, [r3, #-116] + 8001ffc: 4618 mov r0, r3 + 8001ffe: f010 fff9 bl 8012ff4 + 8002002: 6f7b ldr r3, [r7, #116] ; 0x74 + 8002004: 3301 adds r3, #1 + 8002006: 677b str r3, [r7, #116] ; 0x74 + 8002008: 6f7a ldr r2, [r7, #116] ; 0x74 + 800200a: 6ffb ldr r3, [r7, #124] ; 0x7c + 800200c: 429a cmp r2, r3 + 800200e: dbef blt.n 8001ff0 + return 1; + 8002010: 2301 movs r3, #1 } + 8002012: 4618 mov r0, r3 + 8002014: 3784 adds r7, #132 ; 0x84 + 8002016: 46bd mov sp, r7 + 8002018: bd90 pop {r4, r7, pc} + 800201a: bf00 nop + 800201c: f3af 8000 nop.w + 8002020: be76c8b4 .word 0xbe76c8b4 + 8002024: 3fff1a9f .word 0x3fff1a9f + 8002028: 08018d98 .word 0x08018d98 -/* Draw a rectangle */ -void ssd1306_DrawRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { - 800256e: b590 push {r4, r7, lr} - 8002570: b085 sub sp, #20 - 8002572: af02 add r7, sp, #8 - 8002574: 4604 mov r4, r0 - 8002576: 4608 mov r0, r1 - 8002578: 4611 mov r1, r2 - 800257a: 461a mov r2, r3 - 800257c: 4623 mov r3, r4 - 800257e: 71fb strb r3, [r7, #7] - 8002580: 4603 mov r3, r0 - 8002582: 71bb strb r3, [r7, #6] - 8002584: 460b mov r3, r1 - 8002586: 717b strb r3, [r7, #5] - 8002588: 4613 mov r3, r2 - 800258a: 713b strb r3, [r7, #4] - ssd1306_Line(x1,y1,x2,y1,color); - 800258c: 79bc ldrb r4, [r7, #6] - 800258e: 797a ldrb r2, [r7, #5] - 8002590: 79b9 ldrb r1, [r7, #6] - 8002592: 79f8 ldrb r0, [r7, #7] - 8002594: 7e3b ldrb r3, [r7, #24] - 8002596: 9300 str r3, [sp, #0] - 8002598: 4623 mov r3, r4 - 800259a: f7ff fef5 bl 8002388 - ssd1306_Line(x2,y1,x2,y2,color); - 800259e: 793c ldrb r4, [r7, #4] - 80025a0: 797a ldrb r2, [r7, #5] - 80025a2: 79b9 ldrb r1, [r7, #6] - 80025a4: 7978 ldrb r0, [r7, #5] - 80025a6: 7e3b ldrb r3, [r7, #24] - 80025a8: 9300 str r3, [sp, #0] - 80025aa: 4623 mov r3, r4 - 80025ac: f7ff feec bl 8002388 - ssd1306_Line(x2,y2,x1,y2,color); - 80025b0: 793c ldrb r4, [r7, #4] - 80025b2: 79fa ldrb r2, [r7, #7] - 80025b4: 7939 ldrb r1, [r7, #4] - 80025b6: 7978 ldrb r0, [r7, #5] - 80025b8: 7e3b ldrb r3, [r7, #24] - 80025ba: 9300 str r3, [sp, #0] - 80025bc: 4623 mov r3, r4 - 80025be: f7ff fee3 bl 8002388 - ssd1306_Line(x1,y2,x1,y1,color); - 80025c2: 79bc ldrb r4, [r7, #6] - 80025c4: 79fa ldrb r2, [r7, #7] - 80025c6: 7939 ldrb r1, [r7, #4] - 80025c8: 79f8 ldrb r0, [r7, #7] - 80025ca: 7e3b ldrb r3, [r7, #24] - 80025cc: 9300 str r3, [sp, #0] - 80025ce: 4623 mov r3, r4 - 80025d0: f7ff feda bl 8002388 +0800202c : - return; - 80025d4: bf00 nop -} - 80025d6: 370c adds r7, #12 - 80025d8: 46bd mov sp, r7 - 80025da: bd90 pop {r4, r7, pc} -080025dc : -/* Draw a filled rectangle */ -void ssd1306_FillRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { - 80025dc: b590 push {r4, r7, lr} - 80025de: b085 sub sp, #20 - 80025e0: af00 add r7, sp, #0 - 80025e2: 4604 mov r4, r0 - 80025e4: 4608 mov r0, r1 - 80025e6: 4611 mov r1, r2 - 80025e8: 461a mov r2, r3 - 80025ea: 4623 mov r3, r4 - 80025ec: 71fb strb r3, [r7, #7] - 80025ee: 4603 mov r3, r0 - 80025f0: 71bb strb r3, [r7, #6] - 80025f2: 460b mov r3, r1 - 80025f4: 717b strb r3, [r7, #5] - 80025f6: 4613 mov r3, r2 - 80025f8: 713b strb r3, [r7, #4] - uint8_t x_start = ((x1<=x2) ? x1 : x2); - 80025fa: 79fa ldrb r2, [r7, #7] - 80025fc: 797b ldrb r3, [r7, #5] - 80025fe: 4293 cmp r3, r2 - 8002600: bf28 it cs - 8002602: 4613 movcs r3, r2 - 8002604: 737b strb r3, [r7, #13] - uint8_t x_end = ((x1<=x2) ? x2 : x1); - 8002606: 797a ldrb r2, [r7, #5] - 8002608: 79fb ldrb r3, [r7, #7] - 800260a: 4293 cmp r3, r2 - 800260c: bf38 it cc - 800260e: 4613 movcc r3, r2 - 8002610: 733b strb r3, [r7, #12] - uint8_t y_start = ((y1<=y2) ? y1 : y2); - 8002612: 79ba ldrb r2, [r7, #6] - 8002614: 793b ldrb r3, [r7, #4] - 8002616: 4293 cmp r3, r2 - 8002618: bf28 it cs - 800261a: 4613 movcs r3, r2 - 800261c: 72fb strb r3, [r7, #11] - uint8_t y_end = ((y1<=y2) ? y2 : y1); - 800261e: 793a ldrb r2, [r7, #4] - 8002620: 79bb ldrb r3, [r7, #6] - 8002622: 4293 cmp r3, r2 - 8002624: bf38 it cc - 8002626: 4613 movcc r3, r2 - 8002628: 72bb strb r3, [r7, #10] +void nmea_parse(GPS *gps_data, uint8_t *buffer){ + 800202c: b590 push {r4, r7, lr} + 800202e: b087 sub sp, #28 + 8002030: af00 add r7, sp, #0 + 8002032: 6078 str r0, [r7, #4] + 8002034: 6039 str r1, [r7, #0] + memset(data, 0, sizeof(data)); + 8002036: 223c movs r2, #60 ; 0x3c + 8002038: 2100 movs r1, #0 + 800203a: 484e ldr r0, [pc, #312] ; (8002174 ) + 800203c: f012 ff65 bl 8014f0a + char * token = strtok(buffer, "$"); + 8002040: 494d ldr r1, [pc, #308] ; (8002178 ) + 8002042: 6838 ldr r0, [r7, #0] + 8002044: f012 ff7c bl 8014f40 + 8002048: 6178 str r0, [r7, #20] + int cnt = 0; + 800204a: 2300 movs r3, #0 + 800204c: 613b str r3, [r7, #16] + while(token !=NULL){ + 800204e: e01d b.n 800208c + data[cnt++] = malloc(strlen(token)+1); //free later!!!!! + 8002050: 6978 ldr r0, [r7, #20] + 8002052: f7fe f90d bl 8000270 + 8002056: 4603 mov r3, r0 + 8002058: 1c5a adds r2, r3, #1 + 800205a: 693c ldr r4, [r7, #16] + 800205c: 1c63 adds r3, r4, #1 + 800205e: 613b str r3, [r7, #16] + 8002060: 4610 mov r0, r2 + 8002062: f010 ffbf bl 8012fe4 + 8002066: 4603 mov r3, r0 + 8002068: 461a mov r2, r3 + 800206a: 4b42 ldr r3, [pc, #264] ; (8002174 ) + 800206c: f843 2024 str.w r2, [r3, r4, lsl #2] + strcpy(data[cnt-1], token); + 8002070: 693b ldr r3, [r7, #16] + 8002072: 3b01 subs r3, #1 + 8002074: 4a3f ldr r2, [pc, #252] ; (8002174 ) + 8002076: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800207a: 6979 ldr r1, [r7, #20] + 800207c: 4618 mov r0, r3 + 800207e: f013 f858 bl 8015132 + token = strtok(NULL, "$"); + 8002082: 493d ldr r1, [pc, #244] ; (8002178 ) + 8002084: 2000 movs r0, #0 + 8002086: f012 ff5b bl 8014f40 + 800208a: 6178 str r0, [r7, #20] + while(token !=NULL){ + 800208c: 697b ldr r3, [r7, #20] + 800208e: 2b00 cmp r3, #0 + 8002090: d1de bne.n 8002050 + } + for(int i = 0; i + if(strstr(data[i], "\r\n")!=NULL && gps_checksum(data[i])){ + 8002098: 4a36 ldr r2, [pc, #216] ; (8002174 ) + 800209a: 68fb ldr r3, [r7, #12] + 800209c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020a0: 4936 ldr r1, [pc, #216] ; (800217c ) + 80020a2: 4618 mov r0, r3 + 80020a4: f012 ffa8 bl 8014ff8 + 80020a8: 4603 mov r3, r0 + 80020aa: 2b00 cmp r3, #0 + 80020ac: d044 beq.n 8002138 + 80020ae: 4a31 ldr r2, [pc, #196] ; (8002174 ) + 80020b0: 68fb ldr r3, [r7, #12] + 80020b2: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020b6: 4618 mov r0, r3 + 80020b8: f7ff fca0 bl 80019fc + 80020bc: 4603 mov r3, r0 + 80020be: 2b00 cmp r3, #0 + 80020c0: d03a beq.n 8002138 + if(strstr(data[i], "GNRMC")!=NULL){ + 80020c2: 4a2c ldr r2, [pc, #176] ; (8002174 ) + 80020c4: 68fb ldr r3, [r7, #12] + 80020c6: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020ca: 492d ldr r1, [pc, #180] ; (8002180 ) + 80020cc: 4618 mov r0, r3 + 80020ce: f012 ff93 bl 8014ff8 + 80020d2: 4603 mov r3, r0 + 80020d4: 2b00 cmp r3, #0 + 80020d6: d008 beq.n 80020ea + nmea_GNRMC(gps_data, data[i]); + 80020d8: 4a26 ldr r2, [pc, #152] ; (8002174 ) + 80020da: 68fb ldr r3, [r7, #12] + 80020dc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020e0: 4619 mov r1, r3 + 80020e2: 6878 ldr r0, [r7, #4] + 80020e4: f7ff ff30 bl 8001f48 + 80020e8: e026 b.n 8002138 + } + else if(strstr(data[i], "GNGSA")!=NULL){ + 80020ea: 4a22 ldr r2, [pc, #136] ; (8002174 ) + 80020ec: 68fb ldr r3, [r7, #12] + 80020ee: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80020f2: 4924 ldr r1, [pc, #144] ; (8002184 ) + 80020f4: 4618 mov r0, r3 + 80020f6: f012 ff7f bl 8014ff8 + 80020fa: 4603 mov r3, r0 + 80020fc: 2b00 cmp r3, #0 + 80020fe: d008 beq.n 8002112 + nmea_GPGSA(gps_data, data[i]); + 8002100: 4a1c ldr r2, [pc, #112] ; (8002174 ) + 8002102: 68fb ldr r3, [r7, #12] + 8002104: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002108: 4619 mov r1, r3 + 800210a: 6878 ldr r0, [r7, #4] + 800210c: f7ff fe92 bl 8001e34 + 8002110: e012 b.n 8002138 + } + else if(strstr(data[i], "GNGGA")!=NULL){ + 8002112: 4a18 ldr r2, [pc, #96] ; (8002174 ) + 8002114: 68fb ldr r3, [r7, #12] + 8002116: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800211a: 491b ldr r1, [pc, #108] ; (8002188 ) + 800211c: 4618 mov r0, r3 + 800211e: f012 ff6b bl 8014ff8 + 8002122: 4603 mov r3, r0 + 8002124: 2b00 cmp r3, #0 + 8002126: d007 beq.n 8002138 + nmea_GPGGA(gps_data, data[i]); + 8002128: 4a12 ldr r2, [pc, #72] ; (8002174 ) + 800212a: 68fb ldr r3, [r7, #12] + 800212c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002130: 4619 mov r1, r3 + 8002132: 6878 ldr r0, [r7, #4] + 8002134: f7ff fcac bl 8001a90 + for(int i = 0; i + } + } - for (uint8_t y= y_start; (y<= y_end)&&(y - for (uint8_t x= x_start; (x<= x_end)&&(x - ssd1306_DrawPixel(x, y, color); - 8002636: f897 2020 ldrb.w r2, [r7, #32] - 800263a: 7bf9 ldrb r1, [r7, #15] - 800263c: 7bbb ldrb r3, [r7, #14] - 800263e: 4618 mov r0, r3 - 8002640: f7ff fd88 bl 8002154 - for (uint8_t x= x_start; (x<= x_end)&&(x - 8002652: f997 300e ldrsb.w r3, [r7, #14] - 8002656: 2b00 cmp r3, #0 - 8002658: daed bge.n 8002636 - for (uint8_t y= y_start; (y<= y_end)&&(y - 8002668: 7bfb ldrb r3, [r7, #15] - 800266a: 2b3f cmp r3, #63 ; 0x3f - 800266c: d9e0 bls.n 8002630 - } } - return; - 800266e: bf00 nop - 8002670: bf00 nop + for(int i = 0; i + 800214c: 4a09 ldr r2, [pc, #36] ; (8002174 ) + 800214e: 68bb ldr r3, [r7, #8] + 8002150: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002154: 4618 mov r0, r3 + 8002156: f010 ff4d bl 8012ff4 + 800215a: 68bb ldr r3, [r7, #8] + 800215c: 3301 adds r3, #1 + 800215e: 60bb str r3, [r7, #8] + 8002160: 68ba ldr r2, [r7, #8] + 8002162: 693b ldr r3, [r7, #16] + 8002164: 429a cmp r2, r3 + 8002166: dbf1 blt.n 800214c + + +} + 8002168: bf00 nop + 800216a: bf00 nop + 800216c: 371c adds r7, #28 + 800216e: 46bd mov sp, r7 + 8002170: bd90 pop {r4, r7, pc} + 8002172: bf00 nop + 8002174: 20000958 .word 0x20000958 + 8002178: 08018d9c .word 0x08018d9c + 800217c: 08018da0 .word 0x08018da0 + 8002180: 08018da4 .word 0x08018da4 + 8002184: 08018dac .word 0x08018dac + 8002188: 08018db4 .word 0x08018db4 + +0800218c : + +SPI_HandleTypeDef hspi1; + +/* SPI1 init function */ +void MX_SPI1_Init(void) +{ + 800218c: b580 push {r7, lr} + 800218e: af00 add r7, sp, #0 + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + hspi1.Instance = SPI1; + 8002190: 4b1b ldr r3, [pc, #108] ; (8002200 ) + 8002192: 4a1c ldr r2, [pc, #112] ; (8002204 ) + 8002194: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8002196: 4b1a ldr r3, [pc, #104] ; (8002200 ) + 8002198: f44f 7282 mov.w r2, #260 ; 0x104 + 800219c: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 800219e: 4b18 ldr r3, [pc, #96] ; (8002200 ) + 80021a0: 2200 movs r2, #0 + 80021a2: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80021a4: 4b16 ldr r3, [pc, #88] ; (8002200 ) + 80021a6: f44f 62e0 mov.w r2, #1792 ; 0x700 + 80021aa: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80021ac: 4b14 ldr r3, [pc, #80] ; (8002200 ) + 80021ae: 2200 movs r2, #0 + 80021b0: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 80021b2: 4b13 ldr r3, [pc, #76] ; (8002200 ) + 80021b4: 2200 movs r2, #0 + 80021b6: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 80021b8: 4b11 ldr r3, [pc, #68] ; (8002200 ) + 80021ba: f44f 7200 mov.w r2, #512 ; 0x200 + 80021be: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; + 80021c0: 4b0f ldr r3, [pc, #60] ; (8002200 ) + 80021c2: 2210 movs r2, #16 + 80021c4: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80021c6: 4b0e ldr r3, [pc, #56] ; (8002200 ) + 80021c8: 2200 movs r2, #0 + 80021ca: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 80021cc: 4b0c ldr r3, [pc, #48] ; (8002200 ) + 80021ce: 2200 movs r2, #0 + 80021d0: 625a str r2, [r3, #36] ; 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80021d2: 4b0b ldr r3, [pc, #44] ; (8002200 ) + 80021d4: 2200 movs r2, #0 + 80021d6: 629a str r2, [r3, #40] ; 0x28 + hspi1.Init.CRCPolynomial = 7; + 80021d8: 4b09 ldr r3, [pc, #36] ; (8002200 ) + 80021da: 2207 movs r2, #7 + 80021dc: 62da str r2, [r3, #44] ; 0x2c + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 80021de: 4b08 ldr r3, [pc, #32] ; (8002200 ) + 80021e0: 2200 movs r2, #0 + 80021e2: 631a str r2, [r3, #48] ; 0x30 + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 80021e4: 4b06 ldr r3, [pc, #24] ; (8002200 ) + 80021e6: 2208 movs r2, #8 + 80021e8: 635a str r2, [r3, #52] ; 0x34 + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 80021ea: 4805 ldr r0, [pc, #20] ; (8002200 ) + 80021ec: f008 fc0c bl 800aa08 + 80021f0: 4603 mov r3, r0 + 80021f2: 2b00 cmp r3, #0 + 80021f4: d001 beq.n 80021fa + { + Error_Handler(); + 80021f6: f7ff fbfc bl 80019f2 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + } - 8002672: 3714 adds r7, #20 - 8002674: 46bd mov sp, r7 - 8002676: bd90 pop {r4, r7, pc} + 80021fa: bf00 nop + 80021fc: bd80 pop {r7, pc} + 80021fe: bf00 nop + 8002200: 200009c8 .word 0x200009c8 + 8002204: 40013000 .word 0x40013000 -08002678 : +08002208 : -/* Draw a bitmap */ -void ssd1306_DrawBitmap(uint8_t x, uint8_t y, const unsigned char* bitmap, uint8_t w, uint8_t h, SSD1306_COLOR color) { - 8002678: b580 push {r7, lr} - 800267a: b084 sub sp, #16 - 800267c: af00 add r7, sp, #0 - 800267e: 603a str r2, [r7, #0] - 8002680: 461a mov r2, r3 - 8002682: 4603 mov r3, r0 - 8002684: 71fb strb r3, [r7, #7] - 8002686: 460b mov r3, r1 - 8002688: 71bb strb r3, [r7, #6] - 800268a: 4613 mov r3, r2 - 800268c: 717b strb r3, [r7, #5] - int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte - 800268e: 797b ldrb r3, [r7, #5] - 8002690: 3307 adds r3, #7 - 8002692: 2b00 cmp r3, #0 - 8002694: da00 bge.n 8002698 - 8002696: 3307 adds r3, #7 - 8002698: 10db asrs r3, r3, #3 - 800269a: 817b strh r3, [r7, #10] - uint8_t byte = 0; - 800269c: 2300 movs r3, #0 - 800269e: 73fb strb r3, [r7, #15] +void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) +{ + 8002208: b580 push {r7, lr} + 800220a: b08a sub sp, #40 ; 0x28 + 800220c: af00 add r7, sp, #0 + 800220e: 6078 str r0, [r7, #4] - if (x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { - 80026a0: f997 3007 ldrsb.w r3, [r7, #7] - 80026a4: 2b00 cmp r3, #0 - 80026a6: db3e blt.n 8002726 - 80026a8: 79bb ldrb r3, [r7, #6] - 80026aa: 2b3f cmp r3, #63 ; 0x3f - 80026ac: d83b bhi.n 8002726 - return; - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8002210: f107 0314 add.w r3, r7, #20 + 8002214: 2200 movs r2, #0 + 8002216: 601a str r2, [r3, #0] + 8002218: 605a str r2, [r3, #4] + 800221a: 609a str r2, [r3, #8] + 800221c: 60da str r2, [r3, #12] + 800221e: 611a str r2, [r3, #16] + if(spiHandle->Instance==SPI1) + 8002220: 687b ldr r3, [r7, #4] + 8002222: 681b ldr r3, [r3, #0] + 8002224: 4a25 ldr r2, [pc, #148] ; (80022bc ) + 8002226: 4293 cmp r3, r2 + 8002228: d144 bne.n 80022b4 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* SPI1 clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 800222a: 4b25 ldr r3, [pc, #148] ; (80022c0 ) + 800222c: 6e1b ldr r3, [r3, #96] ; 0x60 + 800222e: 4a24 ldr r2, [pc, #144] ; (80022c0 ) + 8002230: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8002234: 6613 str r3, [r2, #96] ; 0x60 + 8002236: 4b22 ldr r3, [pc, #136] ; (80022c0 ) + 8002238: 6e1b ldr r3, [r3, #96] ; 0x60 + 800223a: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 800223e: 613b str r3, [r7, #16] + 8002240: 693b ldr r3, [r7, #16] - for (uint8_t j = 0; j < h; j++, y++) { - 80026ae: 2300 movs r3, #0 - 80026b0: 73bb strb r3, [r7, #14] - 80026b2: e033 b.n 800271c - for (uint8_t i = 0; i < w; i++) { - 80026b4: 2300 movs r3, #0 - 80026b6: 737b strb r3, [r7, #13] - 80026b8: e026 b.n 8002708 - if (i & 7) { - 80026ba: 7b7b ldrb r3, [r7, #13] - 80026bc: f003 0307 and.w r3, r3, #7 - 80026c0: 2b00 cmp r3, #0 - 80026c2: d003 beq.n 80026cc - byte <<= 1; - 80026c4: 7bfb ldrb r3, [r7, #15] - 80026c6: 005b lsls r3, r3, #1 - 80026c8: 73fb strb r3, [r7, #15] - 80026ca: e00d b.n 80026e8 - } else { - byte = (*(const unsigned char *)(&bitmap[j * byteWidth + i / 8])); - 80026cc: 7bbb ldrb r3, [r7, #14] - 80026ce: f9b7 200a ldrsh.w r2, [r7, #10] - 80026d2: fb02 f303 mul.w r3, r2, r3 - 80026d6: 7b7a ldrb r2, [r7, #13] - 80026d8: 08d2 lsrs r2, r2, #3 - 80026da: b2d2 uxtb r2, r2 - 80026dc: 4413 add r3, r2 - 80026de: 461a mov r2, r3 - 80026e0: 683b ldr r3, [r7, #0] - 80026e2: 4413 add r3, r2 - 80026e4: 781b ldrb r3, [r3, #0] - 80026e6: 73fb strb r3, [r7, #15] - } + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8002242: 4b1f ldr r3, [pc, #124] ; (80022c0 ) + 8002244: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002246: 4a1e ldr r2, [pc, #120] ; (80022c0 ) + 8002248: f043 0301 orr.w r3, r3, #1 + 800224c: 64d3 str r3, [r2, #76] ; 0x4c + 800224e: 4b1c ldr r3, [pc, #112] ; (80022c0 ) + 8002250: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002252: f003 0301 and.w r3, r3, #1 + 8002256: 60fb str r3, [r7, #12] + 8002258: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800225a: 4b19 ldr r3, [pc, #100] ; (80022c0 ) + 800225c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800225e: 4a18 ldr r2, [pc, #96] ; (80022c0 ) + 8002260: f043 0302 orr.w r3, r3, #2 + 8002264: 64d3 str r3, [r2, #76] ; 0x4c + 8002266: 4b16 ldr r3, [pc, #88] ; (80022c0 ) + 8002268: 6cdb ldr r3, [r3, #76] ; 0x4c + 800226a: f003 0302 and.w r3, r3, #2 + 800226e: 60bb str r3, [r7, #8] + 8002270: 68bb ldr r3, [r7, #8] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PB5 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; + 8002272: 2360 movs r3, #96 ; 0x60 + 8002274: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002276: 2302 movs r3, #2 + 8002278: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800227a: 2300 movs r3, #0 + 800227c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800227e: 2303 movs r3, #3 + 8002280: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8002282: 2305 movs r3, #5 + 8002284: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8002286: f107 0314 add.w r3, r7, #20 + 800228a: 4619 mov r1, r3 + 800228c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8002290: f004 fe42 bl 8006f18 + + GPIO_InitStruct.Pin = GPIO_PIN_5; + 8002294: 2320 movs r3, #32 + 8002296: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8002298: 2302 movs r3, #2 + 800229a: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800229c: 2300 movs r3, #0 + 800229e: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80022a0: 2303 movs r3, #3 + 80022a2: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 80022a4: 2305 movs r3, #5 + 80022a6: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80022a8: f107 0314 add.w r3, r7, #20 + 80022ac: 4619 mov r1, r3 + 80022ae: 4805 ldr r0, [pc, #20] ; (80022c4 ) + 80022b0: f004 fe32 bl 8006f18 + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } +} + 80022b4: bf00 nop + 80022b6: 3728 adds r7, #40 ; 0x28 + 80022b8: 46bd mov sp, r7 + 80022ba: bd80 pop {r7, pc} + 80022bc: 40013000 .word 0x40013000 + 80022c0: 40021000 .word 0x40021000 + 80022c4: 48000400 .word 0x48000400 + +080022c8 : + /* USER CODE END SPI1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ +int csvframe(uint8_t* buffer,float temp,float vbat,GPS * gpsdata,int otherval1,float otherval2){ + 80022c8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 80022cc: b09e sub sp, #120 ; 0x78 + 80022ce: af10 add r7, sp, #64 ; 0x40 + 80022d0: 62f8 str r0, [r7, #44] ; 0x2c + 80022d2: ed87 0a0a vstr s0, [r7, #40] ; 0x28 + 80022d6: edc7 0a09 vstr s1, [r7, #36] ; 0x24 + 80022da: 6239 str r1, [r7, #32] + 80022dc: 61fa str r2, [r7, #28] + 80022de: ed87 1a06 vstr s2, [r7, #24] + int framesize=0; + 80022e2: 2300 movs r3, #0 + 80022e4: 637b str r3, [r7, #52] ; 0x34 + framesize=snprintf((uint8_t*)buffer,256, "%0.2f,%0.2f,%0.2f,%0.7f,%0.7f,%0.2f,%d,%0.2f;\n\r",temp,vbat,gpsdata->speed,gpsdata->latitude,gpsdata->longitude,gpsdata->altitude,otherval1,otherval2); + 80022e6: 6ab8 ldr r0, [r7, #40] ; 0x28 + 80022e8: f7fe f92e bl 8000548 <__aeabi_f2d> + 80022ec: e9c7 0104 strd r0, r1, [r7, #16] + 80022f0: 6a78 ldr r0, [r7, #36] ; 0x24 + 80022f2: f7fe f929 bl 8000548 <__aeabi_f2d> + 80022f6: e9c7 0102 strd r0, r1, [r7, #8] + 80022fa: 6a3b ldr r3, [r7, #32] + 80022fc: 6b9b ldr r3, [r3, #56] ; 0x38 + 80022fe: 4618 mov r0, r3 + 8002300: f7fe f922 bl 8000548 <__aeabi_f2d> + 8002304: e9c7 0100 strd r0, r1, [r7] + 8002308: 6a3b ldr r3, [r7, #32] + 800230a: e9d3 8900 ldrd r8, r9, [r3] + 800230e: 6a3b ldr r3, [r7, #32] + 8002310: e9d3 ab04 ldrd sl, fp, [r3, #16] + 8002314: 6a3b ldr r3, [r7, #32] + 8002316: 69db ldr r3, [r3, #28] + 8002318: 4618 mov r0, r3 + 800231a: f7fe f915 bl 8000548 <__aeabi_f2d> + 800231e: 4604 mov r4, r0 + 8002320: 460d mov r5, r1 + 8002322: 69b8 ldr r0, [r7, #24] + 8002324: f7fe f910 bl 8000548 <__aeabi_f2d> + 8002328: 4602 mov r2, r0 + 800232a: 460b mov r3, r1 + 800232c: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 + 8002330: 69fb ldr r3, [r7, #28] + 8002332: 930c str r3, [sp, #48] ; 0x30 + 8002334: e9cd 450a strd r4, r5, [sp, #40] ; 0x28 + 8002338: e9cd ab08 strd sl, fp, [sp, #32] + 800233c: e9cd 8906 strd r8, r9, [sp, #24] + 8002340: ed97 7b00 vldr d7, [r7] + 8002344: ed8d 7b04 vstr d7, [sp, #16] + 8002348: ed97 7b02 vldr d7, [r7, #8] + 800234c: ed8d 7b02 vstr d7, [sp, #8] + 8002350: ed97 7b04 vldr d7, [r7, #16] + 8002354: ed8d 7b00 vstr d7, [sp] + 8002358: 4a06 ldr r2, [pc, #24] ; (8002374 ) + 800235a: f44f 7180 mov.w r1, #256 ; 0x100 + 800235e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8002360: f012 fd3c bl 8014ddc + 8002364: 6378 str r0, [r7, #52] ; 0x34 + return framesize; + 8002366: 6b7b ldr r3, [r7, #52] ; 0x34 +} + 8002368: 4618 mov r0, r3 + 800236a: 3738 adds r7, #56 ; 0x38 + 800236c: 46bd mov sp, r7 + 800236e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8002372: bf00 nop + 8002374: 08018dbc .word 0x08018dbc + +08002378 : + + +void storeindex(void){ + 8002378: b580 push {r7, lr} + 800237a: b09c sub sp, #112 ; 0x70 + 800237c: af02 add r7, sp, #8 + int writepage=MAX_WRITE_PAGE+1; + 800237e: f44f 43c8 mov.w r3, #25600 ; 0x6400 + 8002382: 667b str r3, [r7, #100] ; 0x64 + uint8_t writebuffer[100]; + memset((uint8_t*)writebuffer,'\0',100); + 8002384: 463b mov r3, r7 + 8002386: 2264 movs r2, #100 ; 0x64 + 8002388: 2100 movs r1, #0 + 800238a: 4618 mov r0, r3 + 800238c: f012 fdbd bl 8014f0a + snprintf((uint8_t*)writebuffer,100, "%d$%d$",pageoffset,pagenumber); + 8002390: 4b14 ldr r3, [pc, #80] ; (80023e4 ) + 8002392: 681a ldr r2, [r3, #0] + 8002394: 4b14 ldr r3, [pc, #80] ; (80023e8 ) + 8002396: 681b ldr r3, [r3, #0] + 8002398: 4638 mov r0, r7 + 800239a: 9300 str r3, [sp, #0] + 800239c: 4613 mov r3, r2 + 800239e: 4a13 ldr r2, [pc, #76] ; (80023ec ) + 80023a0: 2164 movs r1, #100 ; 0x64 + 80023a2: f012 fd1b bl 8014ddc + SPIF_EraseSector(&hspif1, (int)floor((writepage)/16)); + 80023a6: 6e7b ldr r3, [r7, #100] ; 0x64 + 80023a8: 2b00 cmp r3, #0 + 80023aa: da00 bge.n 80023ae + 80023ac: 330f adds r3, #15 + 80023ae: 111b asrs r3, r3, #4 + 80023b0: 4618 mov r0, r3 + 80023b2: f7fe f8b7 bl 8000524 <__aeabi_i2d> + 80023b6: 4602 mov r2, r0 + 80023b8: 460b mov r3, r1 + 80023ba: 4610 mov r0, r2 + 80023bc: 4619 mov r1, r3 + 80023be: f7fe fbcb bl 8000b58 <__aeabi_d2iz> + 80023c2: 4603 mov r3, r0 + 80023c4: 4619 mov r1, r3 + 80023c6: 480a ldr r0, [pc, #40] ; (80023f0 ) + 80023c8: f00f ffa3 bl 8012312 + SPIF_WritePage(&hspif1,writepage, (uint8_t *)writebuffer, 100,0); + 80023cc: 6e79 ldr r1, [r7, #100] ; 0x64 + 80023ce: 463a mov r2, r7 + 80023d0: 2300 movs r3, #0 + 80023d2: 9300 str r3, [sp, #0] + 80023d4: 2364 movs r3, #100 ; 0x64 + 80023d6: 4806 ldr r0, [pc, #24] ; (80023f0 ) + 80023d8: f010 f81e bl 8012418 + +} + 80023dc: bf00 nop + 80023de: 3768 adds r7, #104 ; 0x68 + 80023e0: 46bd mov sp, r7 + 80023e2: bd80 pop {r7, pc} + 80023e4: 20000934 .word 0x20000934 + 80023e8: 20000938 .word 0x20000938 + 80023ec: 08018dec .word 0x08018dec + 80023f0: 20000700 .word 0x20000700 + +080023f4 : + +void getindex(void){ + 80023f4: b580 push {r7, lr} + 80023f6: b086 sub sp, #24 + 80023f8: af02 add r7, sp, #8 + int readpage=MAX_WRITE_PAGE+1; + 80023fa: f44f 43c8 mov.w r3, #25600 ; 0x6400 + 80023fe: 607b str r3, [r7, #4] + SPIF_ReadPage(&hspif1, readpage, (uint8_t *)indexbuffer, 50, 0); + 8002400: 6879 ldr r1, [r7, #4] + 8002402: 2300 movs r3, #0 + 8002404: 9300 str r3, [sp, #0] + 8002406: 2332 movs r3, #50 ; 0x32 + 8002408: 4a2b ldr r2, [pc, #172] ; (80024b8 ) + 800240a: 482c ldr r0, [pc, #176] ; (80024bc ) + 800240c: f010 f822 bl 8012454 + memset(numbuf1,'$',10); + 8002410: 220a movs r2, #10 + 8002412: 2124 movs r1, #36 ; 0x24 + 8002414: 482a ldr r0, [pc, #168] ; (80024c0 ) + 8002416: f012 fd78 bl 8014f0a + memset(numbuf2,'$',10); + 800241a: 220a movs r2, #10 + 800241c: 2124 movs r1, #36 ; 0x24 + 800241e: 4829 ldr r0, [pc, #164] ; (80024c4 ) + 8002420: f012 fd73 bl 8014f0a + int cnt=0; + 8002424: 2300 movs r3, #0 + 8002426: 60fb str r3, [r7, #12] + if((indexbuffer[0]&0x0F)<10 ){ + 8002428: 4b23 ldr r3, [pc, #140] ; (80024b8 ) + 800242a: 781b ldrb r3, [r3, #0] + 800242c: f003 030f and.w r3, r3, #15 + 8002430: 2b09 cmp r3, #9 + 8002432: dc3a bgt.n 80024aa + while(indexbuffer[cnt]!='$'){ + 8002434: e00b b.n 800244e + + numbuf1[cnt]=indexbuffer[cnt]; + 8002436: 4a20 ldr r2, [pc, #128] ; (80024b8 ) + 8002438: 68fb ldr r3, [r7, #12] + 800243a: 4413 add r3, r2 + 800243c: 7819 ldrb r1, [r3, #0] + 800243e: 4a20 ldr r2, [pc, #128] ; (80024c0 ) + 8002440: 68fb ldr r3, [r7, #12] + 8002442: 4413 add r3, r2 + 8002444: 460a mov r2, r1 + 8002446: 701a strb r2, [r3, #0] + cnt++; + 8002448: 68fb ldr r3, [r7, #12] + 800244a: 3301 adds r3, #1 + 800244c: 60fb str r3, [r7, #12] + while(indexbuffer[cnt]!='$'){ + 800244e: 4a1a ldr r2, [pc, #104] ; (80024b8 ) + 8002450: 68fb ldr r3, [r7, #12] + 8002452: 4413 add r3, r2 + 8002454: 781b ldrb r3, [r3, #0] + 8002456: 2b24 cmp r3, #36 ; 0x24 + 8002458: d1ed bne.n 8002436 + } + cnt++; + 800245a: 68fb ldr r3, [r7, #12] + 800245c: 3301 adds r3, #1 + 800245e: 60fb str r3, [r7, #12] + int cnt1=0; + 8002460: 2300 movs r3, #0 + 8002462: 60bb str r3, [r7, #8] + while(indexbuffer[cnt]!='$'){ + 8002464: e00e b.n 8002484 + + numbuf2[cnt1]=indexbuffer[cnt]; + 8002466: 4a14 ldr r2, [pc, #80] ; (80024b8 ) + 8002468: 68fb ldr r3, [r7, #12] + 800246a: 4413 add r3, r2 + 800246c: 7819 ldrb r1, [r3, #0] + 800246e: 4a15 ldr r2, [pc, #84] ; (80024c4 ) + 8002470: 68bb ldr r3, [r7, #8] + 8002472: 4413 add r3, r2 + 8002474: 460a mov r2, r1 + 8002476: 701a strb r2, [r3, #0] + cnt1++; + 8002478: 68bb ldr r3, [r7, #8] + 800247a: 3301 adds r3, #1 + 800247c: 60bb str r3, [r7, #8] + cnt++; + 800247e: 68fb ldr r3, [r7, #12] + 8002480: 3301 adds r3, #1 + 8002482: 60fb str r3, [r7, #12] + while(indexbuffer[cnt]!='$'){ + 8002484: 4a0c ldr r2, [pc, #48] ; (80024b8 ) + 8002486: 68fb ldr r3, [r7, #12] + 8002488: 4413 add r3, r2 + 800248a: 781b ldrb r3, [r3, #0] + 800248c: 2b24 cmp r3, #36 ; 0x24 + 800248e: d1ea bne.n 8002466 + } + + pageoffset=atoi((uint8_t*)numbuf1); + 8002490: 480b ldr r0, [pc, #44] ; (80024c0 ) + 8002492: f010 fda3 bl 8012fdc + 8002496: 4603 mov r3, r0 + 8002498: 4a0b ldr r2, [pc, #44] ; (80024c8 ) + 800249a: 6013 str r3, [r2, #0] + pagenumber=atoi((uint8_t*)numbuf2); + 800249c: 4809 ldr r0, [pc, #36] ; (80024c4 ) + 800249e: f010 fd9d bl 8012fdc + 80024a2: 4603 mov r3, r0 + 80024a4: 4a09 ldr r2, [pc, #36] ; (80024cc ) + 80024a6: 6013 str r3, [r2, #0] + } + else{ + storeindex(); + } - if (byte & 0x80) { - 80026e8: f997 300f ldrsb.w r3, [r7, #15] - 80026ec: 2b00 cmp r3, #0 - 80026ee: da08 bge.n 8002702 - ssd1306_DrawPixel(x + i, y, color); - 80026f0: 79fa ldrb r2, [r7, #7] - 80026f2: 7b7b ldrb r3, [r7, #13] - 80026f4: 4413 add r3, r2 - 80026f6: b2db uxtb r3, r3 - 80026f8: 7f3a ldrb r2, [r7, #28] - 80026fa: 79b9 ldrb r1, [r7, #6] - 80026fc: 4618 mov r0, r3 - 80026fe: f7ff fd29 bl 8002154 - for (uint8_t i = 0; i < w; i++) { - 8002702: 7b7b ldrb r3, [r7, #13] - 8002704: 3301 adds r3, #1 - 8002706: 737b strb r3, [r7, #13] - 8002708: 7b7a ldrb r2, [r7, #13] - 800270a: 797b ldrb r3, [r7, #5] - 800270c: 429a cmp r2, r3 - 800270e: d3d4 bcc.n 80026ba - for (uint8_t j = 0; j < h; j++, y++) { - 8002710: 7bbb ldrb r3, [r7, #14] - 8002712: 3301 adds r3, #1 - 8002714: 73bb strb r3, [r7, #14] - 8002716: 79bb ldrb r3, [r7, #6] - 8002718: 3301 adds r3, #1 - 800271a: 71bb strb r3, [r7, #6] - 800271c: 7bba ldrb r2, [r7, #14] - 800271e: 7e3b ldrb r3, [r7, #24] - 8002720: 429a cmp r2, r3 - 8002722: d3c7 bcc.n 80026b4 - } - } - } - return; - 8002724: e000 b.n 8002728 - return; - 8002726: bf00 nop } - 8002728: 3710 adds r7, #16 - 800272a: 46bd mov sp, r7 - 800272c: bd80 pop {r7, pc} + 80024a8: e001 b.n 80024ae + storeindex(); + 80024aa: f7ff ff65 bl 8002378 +} + 80024ae: bf00 nop + 80024b0: 3710 adds r7, #16 + 80024b2: 46bd mov sp, r7 + 80024b4: bd80 pop {r7, pc} + 80024b6: bf00 nop + 80024b8: 20000994 .word 0x20000994 + 80024bc: 20000700 .word 0x20000700 + 80024c0: 20000940 .word 0x20000940 + 80024c4: 2000094c .word 0x2000094c + 80024c8: 20000934 .word 0x20000934 + 80024cc: 20000938 .word 0x20000938 + +080024d0 : + +void writebuffertoflash(uint8_t * buffer,int bufferlenght){ + 80024d0: b580 push {r7, lr} + 80024d2: b084 sub sp, #16 + 80024d4: af02 add r7, sp, #8 + 80024d6: 6078 str r0, [r7, #4] + 80024d8: 6039 str r1, [r7, #0] + if((pagenumber+1)%16==0){ + 80024da: 4b3f ldr r3, [pc, #252] ; (80025d8 ) + 80024dc: 681b ldr r3, [r3, #0] + 80024de: 3301 adds r3, #1 + 80024e0: f003 030f and.w r3, r3, #15 + 80024e4: 2b00 cmp r3, #0 + 80024e6: d11b bne.n 8002520 + if(sectoreraseen==0){ + 80024e8: 4b3c ldr r3, [pc, #240] ; (80025dc ) + 80024ea: 681b ldr r3, [r3, #0] + 80024ec: 2b00 cmp r3, #0 + 80024ee: d117 bne.n 8002520 + SPIF_EraseSector(&hspif1, (int)floor((pagenumber+1)/16)); + 80024f0: 4b39 ldr r3, [pc, #228] ; (80025d8 ) + 80024f2: 681b ldr r3, [r3, #0] + 80024f4: 3301 adds r3, #1 + 80024f6: 2b00 cmp r3, #0 + 80024f8: da00 bge.n 80024fc + 80024fa: 330f adds r3, #15 + 80024fc: 111b asrs r3, r3, #4 + 80024fe: 4618 mov r0, r3 + 8002500: f7fe f810 bl 8000524 <__aeabi_i2d> + 8002504: 4602 mov r2, r0 + 8002506: 460b mov r3, r1 + 8002508: 4610 mov r0, r2 + 800250a: 4619 mov r1, r3 + 800250c: f7fe fb24 bl 8000b58 <__aeabi_d2iz> + 8002510: 4603 mov r3, r0 + 8002512: 4619 mov r1, r3 + 8002514: 4832 ldr r0, [pc, #200] ; (80025e0 ) + 8002516: f00f fefc bl 8012312 + sectoreraseen=1; + 800251a: 4b30 ldr r3, [pc, #192] ; (80025dc ) + 800251c: 2201 movs r2, #1 + 800251e: 601a str r2, [r3, #0] + } + + } + if(bufferlenght+pageoffset<256){ + 8002520: 4b30 ldr r3, [pc, #192] ; (80025e4 ) + 8002522: 681a ldr r2, [r3, #0] + 8002524: 683b ldr r3, [r7, #0] + 8002526: 4413 add r3, r2 + 8002528: 2bff cmp r3, #255 ; 0xff + 800252a: dc11 bgt.n 8002550 + SPIF_WritePage(&hspif1,pagenumber, (uint8_t *)buffer, bufferlenght,pageoffset); + 800252c: 4b2a ldr r3, [pc, #168] ; (80025d8 ) + 800252e: 681b ldr r3, [r3, #0] + 8002530: 4619 mov r1, r3 + 8002532: 683b ldr r3, [r7, #0] + 8002534: 4a2b ldr r2, [pc, #172] ; (80025e4 ) + 8002536: 6812 ldr r2, [r2, #0] + 8002538: 9200 str r2, [sp, #0] + 800253a: 687a ldr r2, [r7, #4] + 800253c: 4828 ldr r0, [pc, #160] ; (80025e0 ) + 800253e: f00f ff6b bl 8012418 + pageoffset=pageoffset+bufferlenght; + 8002542: 4b28 ldr r3, [pc, #160] ; (80025e4 ) + 8002544: 681a ldr r2, [r3, #0] + 8002546: 683b ldr r3, [r7, #0] + 8002548: 4413 add r3, r2 + 800254a: 4a26 ldr r2, [pc, #152] ; (80025e4 ) + 800254c: 6013 str r3, [r2, #0] + 800254e: e03c b.n 80025ca + } + else{ + SPIF_WritePage(&hspif1,pagenumber, (uint8_t *)buffer, 256-pageoffset,pageoffset); + 8002550: 4b21 ldr r3, [pc, #132] ; (80025d8 ) + 8002552: 681b ldr r3, [r3, #0] + 8002554: 4619 mov r1, r3 + 8002556: 4b23 ldr r3, [pc, #140] ; (80025e4 ) + 8002558: 681b ldr r3, [r3, #0] + 800255a: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 800255e: 461a mov r2, r3 + 8002560: 4b20 ldr r3, [pc, #128] ; (80025e4 ) + 8002562: 681b ldr r3, [r3, #0] + 8002564: 9300 str r3, [sp, #0] + 8002566: 4613 mov r3, r2 + 8002568: 687a ldr r2, [r7, #4] + 800256a: 481d ldr r0, [pc, #116] ; (80025e0 ) + 800256c: f00f ff54 bl 8012418 + HAL_Delay(100); + 8002570: 2064 movs r0, #100 ; 0x64 + 8002572: f002 fe79 bl 8005268 + SPIF_WritePage(&hspif1,pagenumber+1, (uint8_t *)buffer+(256-pageoffset), bufferlenght-(256-pageoffset),0); + 8002576: 4b18 ldr r3, [pc, #96] ; (80025d8 ) + 8002578: 681b ldr r3, [r3, #0] + 800257a: 3301 adds r3, #1 + 800257c: 4618 mov r0, r3 + 800257e: 4b19 ldr r3, [pc, #100] ; (80025e4 ) + 8002580: 681b ldr r3, [r3, #0] + 8002582: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 8002586: 461a mov r2, r3 + 8002588: 687b ldr r3, [r7, #4] + 800258a: 1899 adds r1, r3, r2 + 800258c: 4b15 ldr r3, [pc, #84] ; (80025e4 ) + 800258e: 681b ldr r3, [r3, #0] + 8002590: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 8002594: 683a ldr r2, [r7, #0] + 8002596: 1ad3 subs r3, r2, r3 + 8002598: 461a mov r2, r3 + 800259a: 2300 movs r3, #0 + 800259c: 9300 str r3, [sp, #0] + 800259e: 4613 mov r3, r2 + 80025a0: 460a mov r2, r1 + 80025a2: 4601 mov r1, r0 + 80025a4: 480e ldr r0, [pc, #56] ; (80025e0 ) + 80025a6: f00f ff37 bl 8012418 + pagenumber=pagenumber+1; + 80025aa: 4b0b ldr r3, [pc, #44] ; (80025d8 ) + 80025ac: 681b ldr r3, [r3, #0] + 80025ae: 3301 adds r3, #1 + 80025b0: 4a09 ldr r2, [pc, #36] ; (80025d8 ) + 80025b2: 6013 str r3, [r2, #0] + sectoreraseen=0; + 80025b4: 4b09 ldr r3, [pc, #36] ; (80025dc ) + 80025b6: 2200 movs r2, #0 + 80025b8: 601a str r2, [r3, #0] + pageoffset=(bufferlenght-(256-pageoffset)); + 80025ba: 4b0a ldr r3, [pc, #40] ; (80025e4 ) + 80025bc: 681b ldr r3, [r3, #0] + 80025be: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 80025c2: 683a ldr r2, [r7, #0] + 80025c4: 1ad3 subs r3, r2, r3 + 80025c6: 4a07 ldr r2, [pc, #28] ; (80025e4 ) + 80025c8: 6013 str r3, [r2, #0] + } + storeindex(); + 80025ca: f7ff fed5 bl 8002378 -0800272e : +} + 80025ce: bf00 nop + 80025d0: 3708 adds r7, #8 + 80025d2: 46bd mov sp, r7 + 80025d4: bd80 pop {r7, pc} + 80025d6: bf00 nop + 80025d8: 20000938 .word 0x20000938 + 80025dc: 2000093c .word 0x2000093c + 80025e0: 20000700 .word 0x20000700 + 80025e4: 20000934 .word 0x20000934 -void ssd1306_SetContrast(const uint8_t value) { - 800272e: b580 push {r7, lr} - 8002730: b084 sub sp, #16 - 8002732: af00 add r7, sp, #0 - 8002734: 4603 mov r3, r0 - 8002736: 71fb strb r3, [r7, #7] - const uint8_t kSetContrastControlRegister = 0x81; - 8002738: 2381 movs r3, #129 ; 0x81 - 800273a: 73fb strb r3, [r7, #15] - ssd1306_WriteCommand(kSetContrastControlRegister); - 800273c: 7bfb ldrb r3, [r7, #15] - 800273e: 4618 mov r0, r3 - 8002740: f7ff fc2c bl 8001f9c - ssd1306_WriteCommand(value); - 8002744: 79fb ldrb r3, [r7, #7] - 8002746: 4618 mov r0, r3 - 8002748: f7ff fc28 bl 8001f9c +080025e8 : +#include +#include +#include // For memcpy + + +void ssd1306_Reset(void) { + 80025e8: b480 push {r7} + 80025ea: af00 add r7, sp, #0 + /* for I2C - do nothing */ } - 800274c: bf00 nop - 800274e: 3710 adds r7, #16 - 8002750: 46bd mov sp, r7 - 8002752: bd80 pop {r7, pc} + 80025ec: bf00 nop + 80025ee: 46bd mov sp, r7 + 80025f0: f85d 7b04 ldr.w r7, [sp], #4 + 80025f4: 4770 bx lr + ... -08002754 : +080025f8 : -void ssd1306_SetDisplayOn(const uint8_t on) { - 8002754: b580 push {r7, lr} - 8002756: b084 sub sp, #16 - 8002758: af00 add r7, sp, #0 - 800275a: 4603 mov r3, r0 - 800275c: 71fb strb r3, [r7, #7] - uint8_t value; - if (on) { - 800275e: 79fb ldrb r3, [r7, #7] - 8002760: 2b00 cmp r3, #0 - 8002762: d005 beq.n 8002770 - value = 0xAF; // Display on - 8002764: 23af movs r3, #175 ; 0xaf - 8002766: 73fb strb r3, [r7, #15] - SSD1306.DisplayOn = 1; - 8002768: 4b08 ldr r3, [pc, #32] ; (800278c ) - 800276a: 2201 movs r2, #1 - 800276c: 715a strb r2, [r3, #5] - 800276e: e004 b.n 800277a - } else { - value = 0xAE; // Display off - 8002770: 23ae movs r3, #174 ; 0xae - 8002772: 73fb strb r3, [r7, #15] - SSD1306.DisplayOn = 0; - 8002774: 4b05 ldr r3, [pc, #20] ; (800278c ) - 8002776: 2200 movs r2, #0 - 8002778: 715a strb r2, [r3, #5] +// Send a byte to the command register +void ssd1306_WriteCommand(uint8_t byte) { + 80025f8: b580 push {r7, lr} + 80025fa: b086 sub sp, #24 + 80025fc: af04 add r7, sp, #16 + 80025fe: 4603 mov r3, r0 + 8002600: 71fb strb r3, [r7, #7] + HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x00, 1, &byte, 1, HAL_MAX_DELAY); + 8002602: f04f 33ff mov.w r3, #4294967295 + 8002606: 9302 str r3, [sp, #8] + 8002608: 2301 movs r3, #1 + 800260a: 9301 str r3, [sp, #4] + 800260c: 1dfb adds r3, r7, #7 + 800260e: 9300 str r3, [sp, #0] + 8002610: 2301 movs r3, #1 + 8002612: 2200 movs r2, #0 + 8002614: 2178 movs r1, #120 ; 0x78 + 8002616: 4803 ldr r0, [pc, #12] ; (8002624 ) + 8002618: f004 feb4 bl 8007384 +} + 800261c: bf00 nop + 800261e: 3708 adds r7, #8 + 8002620: 46bd mov sp, r7 + 8002622: bd80 pop {r7, pc} + 8002624: 20000414 .word 0x20000414 + +08002628 : + +// Send data +void ssd1306_WriteData(uint8_t* buffer, size_t buff_size) { + 8002628: b580 push {r7, lr} + 800262a: b086 sub sp, #24 + 800262c: af04 add r7, sp, #16 + 800262e: 6078 str r0, [r7, #4] + 8002630: 6039 str r1, [r7, #0] + HAL_I2C_Mem_Write(&SSD1306_I2C_PORT, SSD1306_I2C_ADDR, 0x40, 1, buffer, buff_size, HAL_MAX_DELAY); + 8002632: 683b ldr r3, [r7, #0] + 8002634: b29b uxth r3, r3 + 8002636: f04f 32ff mov.w r2, #4294967295 + 800263a: 9202 str r2, [sp, #8] + 800263c: 9301 str r3, [sp, #4] + 800263e: 687b ldr r3, [r7, #4] + 8002640: 9300 str r3, [sp, #0] + 8002642: 2301 movs r3, #1 + 8002644: 2240 movs r2, #64 ; 0x40 + 8002646: 2178 movs r1, #120 ; 0x78 + 8002648: 4803 ldr r0, [pc, #12] ; (8002658 ) + 800264a: f004 fe9b bl 8007384 +} + 800264e: bf00 nop + 8002650: 3708 adds r7, #8 + 8002652: 46bd mov sp, r7 + 8002654: bd80 pop {r7, pc} + 8002656: bf00 nop + 8002658: 20000414 .word 0x20000414 + +0800265c : } - ssd1306_WriteCommand(value); - 800277a: 7bfb ldrb r3, [r7, #15] - 800277c: 4618 mov r0, r3 - 800277e: f7ff fc0d bl 8001f9c + return ret; } - 8002782: bf00 nop - 8002784: 3710 adds r7, #16 - 8002786: 46bd mov sp, r7 - 8002788: bd80 pop {r7, pc} - 800278a: bf00 nop - 800278c: 20000c78 .word 0x20000c78 -08002790 : -extern DMA_HandleTypeDef hdma_lpuart_rx; +/* Initialize the oled screen */ +void ssd1306_Init(void) { + 800265c: b580 push {r7, lr} + 800265e: af00 add r7, sp, #0 + // Reset OLED + ssd1306_Reset(); + 8002660: f7ff ffc2 bl 80025e8 + // Wait for the screen to boot + HAL_Delay(100); + 8002664: 2064 movs r0, #100 ; 0x64 + 8002666: f002 fdff bl 8005268 + // Init OLED + ssd1306_SetDisplayOn(0); //display off + 800266a: 2000 movs r0, #0 + 800266c: f000 fba0 bl 8002db0 -//le code qui permet d'avoir les ecran de donnée que l'on souhaite, changeable a souhait on peut d'ailleur rajouter des état ou rajouter des fonctionnalité au sein de chaque état, pas encore décidé de la version définitive. -void statemachine(void){ - 8002790: b5f0 push {r4, r5, r6, r7, lr} - 8002792: ed2d 8b02 vpush {d8} - 8002796: b0b3 sub sp, #204 ; 0xcc - 8002798: af04 add r7, sp, #16 - switch(state){ - 800279a: 4bc7 ldr r3, [pc, #796] ; (8002ab8 ) - 800279c: 781b ldrb r3, [r3, #0] - 800279e: 2b05 cmp r3, #5 - 80027a0: f201 82df bhi.w 8003d62 - 80027a4: a201 add r2, pc, #4 ; (adr r2, 80027ac ) - 80027a6: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80027aa: bf00 nop - 80027ac: 080027c5 .word 0x080027c5 - 80027b0: 08002c43 .word 0x08002c43 - 80027b4: 08003195 .word 0x08003195 - 80027b8: 0800383b .word 0x0800383b - 80027bc: 080039d9 .word 0x080039d9 - 80027c0: 08003c75 .word 0x08003c75 - case STATE_SPEED: - ssd1306_Fill(Black); - 80027c4: 2000 movs r0, #0 - 80027c6: f7ff fc85 bl 80020d4 - ssd1306_SetCursor(32, 32); - 80027ca: 2120 movs r1, #32 - 80027cc: 2020 movs r0, #32 - 80027ce: f7ff fdc3 bl 8002358 - nmea_parse(&myData, DataBuffer); - 80027d2: 49ba ldr r1, [pc, #744] ; (8002abc ) - 80027d4: 48ba ldr r0, [pc, #744] ; (8002ac0 ) - 80027d6: f7ff fb29 bl 8001e2c - if(myData.speed>=vitmax){ - 80027da: 4bb9 ldr r3, [pc, #740] ; (8002ac0 ) - 80027dc: ed93 7a0e vldr s14, [r3, #56] ; 0x38 - 80027e0: 4bb8 ldr r3, [pc, #736] ; (8002ac4 ) - 80027e2: edd3 7a00 vldr s15, [r3] - 80027e6: eeb4 7ae7 vcmpe.f32 s14, s15 - 80027ea: eef1 fa10 vmrs APSR_nzcv, fpscr - 80027ee: db03 blt.n 80027f8 - vitmax=myData.speed; - 80027f0: 4bb3 ldr r3, [pc, #716] ; (8002ac0 ) - 80027f2: 6b9b ldr r3, [r3, #56] ; 0x38 - 80027f4: 4ab3 ldr r2, [pc, #716] ; (8002ac4 ) - 80027f6: 6013 str r3, [r2, #0] - } - float pace=0; - 80027f8: f04f 0300 mov.w r3, #0 - 80027fc: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - float sec=0; - 8002800: f04f 0300 mov.w r3, #0 - 8002804: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 - if (myData.speed!=0){ - 8002808: 4bad ldr r3, [pc, #692] ; (8002ac0 ) - 800280a: edd3 7a0e vldr s15, [r3, #56] ; 0x38 - 800280e: eef5 7a40 vcmp.f32 s15, #0.0 - 8002812: eef1 fa10 vmrs APSR_nzcv, fpscr - 8002816: d035 beq.n 8002884 - pace=1000/(60*myData.speed); - 8002818: 4ba9 ldr r3, [pc, #676] ; (8002ac0 ) - 800281a: edd3 7a0e vldr s15, [r3, #56] ; 0x38 - 800281e: ed9f 7aaa vldr s14, [pc, #680] ; 8002ac8 - 8002822: ee27 7a87 vmul.f32 s14, s15, s14 - 8002826: eddf 6aa9 vldr s13, [pc, #676] ; 8002acc - 800282a: eec6 7a87 vdiv.f32 s15, s13, s14 - 800282e: edc7 7a2d vstr s15, [r7, #180] ; 0xb4 - sec=(pace-floor(pace))*60; - 8002832: f8d7 00b4 ldr.w r0, [r7, #180] ; 0xb4 - 8002836: f7fd fe87 bl 8000548 <__aeabi_f2d> - 800283a: 4604 mov r4, r0 - 800283c: 460d mov r5, r1 - 800283e: f8d7 00b4 ldr.w r0, [r7, #180] ; 0xb4 - 8002842: f7fd fe81 bl 8000548 <__aeabi_f2d> - 8002846: 4602 mov r2, r0 - 8002848: 460b mov r3, r1 - 800284a: ec43 2b10 vmov d0, r2, r3 - 800284e: f012 ff5f bl 8015710 - 8002852: ec53 2b10 vmov r2, r3, d0 - 8002856: 4620 mov r0, r4 - 8002858: 4629 mov r1, r5 - 800285a: f7fd fd15 bl 8000288 <__aeabi_dsub> - 800285e: 4602 mov r2, r0 - 8002860: 460b mov r3, r1 - 8002862: 4610 mov r0, r2 - 8002864: 4619 mov r1, r3 - 8002866: f04f 0200 mov.w r2, #0 - 800286a: 4b99 ldr r3, [pc, #612] ; (8002ad0 ) - 800286c: f7fd fec4 bl 80005f8 <__aeabi_dmul> - 8002870: 4602 mov r2, r0 - 8002872: 460b mov r3, r1 - 8002874: 4610 mov r0, r2 - 8002876: 4619 mov r1, r3 - 8002878: f7fe f9b6 bl 8000be8 <__aeabi_d2f> - 800287c: 4603 mov r3, r0 - 800287e: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 - 8002882: e002 b.n 800288a - } - else { - pace=9999;//en cas de division par 0, techniquement le temps devient infini mais ce n'est pas intérréssant - 8002884: 4b93 ldr r3, [pc, #588] ; (8002ad4 ) - 8002886: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - } + ssd1306_WriteCommand(0x20); //Set Memory Addressing Mode + 8002670: 2020 movs r0, #32 + 8002672: f7ff ffc1 bl 80025f8 + ssd1306_WriteCommand(0x00); // 00b,Horizontal Addressing Mode; 01b,Vertical Addressing Mode; + 8002676: 2000 movs r0, #0 + 8002678: f7ff ffbe bl 80025f8 + // 10b,Page Addressing Mode (RESET); 11b,Invalid + ssd1306_WriteCommand(0xB0); //Set Page Start Address for Page Addressing Mode,0-7 + 800267c: 20b0 movs r0, #176 ; 0xb0 + 800267e: f7ff ffbb bl 80025f8 - switch(spdstate){ - 800288a: 4b93 ldr r3, [pc, #588] ; (8002ad8 ) - 800288c: 781b ldrb r3, [r3, #0] - 800288e: 2b02 cmp r3, #2 - 8002890: f000 815e beq.w 8002b50 - 8002894: 2b02 cmp r3, #2 - 8002896: f300 81c4 bgt.w 8002c22 - 800289a: 2b00 cmp r3, #0 - 800289c: d003 beq.n 80028a6 - 800289e: 2b01 cmp r3, #1 - 80028a0: f000 80a2 beq.w 80029e8 - 80028a4: e1bd b.n 8002c22 +#ifdef SSD1306_MIRROR_VERT + ssd1306_WriteCommand(0xC0); // Mirror vertically +#else + ssd1306_WriteCommand(0xC8); //Set COM Output Scan Direction + 8002682: 20c8 movs r0, #200 ; 0xc8 + 8002684: f7ff ffb8 bl 80025f8 +#endif + ssd1306_WriteCommand(0x00); //---set low column address + 8002688: 2000 movs r0, #0 + 800268a: f7ff ffb5 bl 80025f8 + ssd1306_WriteCommand(0x10); //---set high column address + 800268e: 2010 movs r0, #16 + 8002690: f7ff ffb2 bl 80025f8 - case STATE_SUMMARY: - if(myData.fix == 1){ //if the GPS has a fix, print the data - 80028a6: 4b86 ldr r3, [pc, #536] ; (8002ac0 ) - 80028a8: 6a9b ldr r3, [r3, #40] ; 0x28 - 80028aa: 2b01 cmp r3, #1 - 80028ac: d171 bne.n 8002992 - char * str = (char*)malloc(sizeof(char)*20); - 80028ae: 2014 movs r0, #20 - 80028b0: f00e f940 bl 8010b34 - 80028b4: 4603 mov r3, r0 - 80028b6: 65bb str r3, [r7, #88] ; 0x58 - snprintf(str,15, "MaxV=%.1f",vitmax*3.6);//amélioration possible la stocker en eeprom - 80028b8: 4b82 ldr r3, [pc, #520] ; (8002ac4 ) - 80028ba: 681b ldr r3, [r3, #0] - 80028bc: 4618 mov r0, r3 - 80028be: f7fd fe43 bl 8000548 <__aeabi_f2d> - 80028c2: a379 add r3, pc, #484 ; (adr r3, 8002aa8 ) - 80028c4: e9d3 2300 ldrd r2, r3, [r3] - 80028c8: f7fd fe96 bl 80005f8 <__aeabi_dmul> - 80028cc: 4602 mov r2, r0 - 80028ce: 460b mov r3, r1 - 80028d0: e9cd 2300 strd r2, r3, [sp] - 80028d4: 4a81 ldr r2, [pc, #516] ; (8002adc ) - 80028d6: 210f movs r1, #15 - 80028d8: 6db8 ldr r0, [r7, #88] ; 0x58 - 80028da: f010 f827 bl 801292c - ssd1306_SetCursor(32, 32); - 80028de: 2120 movs r1, #32 - 80028e0: 2020 movs r0, #32 - 80028e2: f7ff fd39 bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 80028e6: 4a7e ldr r2, [pc, #504] ; (8002ae0 ) - 80028e8: 2301 movs r3, #1 - 80028ea: ca06 ldmia r2, {r1, r2} - 80028ec: 6db8 ldr r0, [r7, #88] ; 0x58 - 80028ee: f7ff fd0d bl 800230c - snprintf(str,15, "V=%0.1f",(myData.speed)*3.6); - 80028f2: 4b73 ldr r3, [pc, #460] ; (8002ac0 ) - 80028f4: 6b9b ldr r3, [r3, #56] ; 0x38 - 80028f6: 4618 mov r0, r3 - 80028f8: f7fd fe26 bl 8000548 <__aeabi_f2d> - 80028fc: a36a add r3, pc, #424 ; (adr r3, 8002aa8 ) - 80028fe: e9d3 2300 ldrd r2, r3, [r3] - 8002902: f7fd fe79 bl 80005f8 <__aeabi_dmul> - 8002906: 4602 mov r2, r0 - 8002908: 460b mov r3, r1 - 800290a: e9cd 2300 strd r2, r3, [sp] - 800290e: 4a75 ldr r2, [pc, #468] ; (8002ae4 ) - 8002910: 210f movs r1, #15 - 8002912: 6db8 ldr r0, [r7, #88] ; 0x58 - 8002914: f010 f80a bl 801292c - ssd1306_SetCursor(32, 42); - 8002918: 212a movs r1, #42 ; 0x2a - 800291a: 2020 movs r0, #32 - 800291c: f7ff fd1c bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002920: 4a6f ldr r2, [pc, #444] ; (8002ae0 ) - 8002922: 2301 movs r3, #1 - 8002924: ca06 ldmia r2, {r1, r2} - 8002926: 6db8 ldr r0, [r7, #88] ; 0x58 - 8002928: f7ff fcf0 bl 800230c - snprintf(str,15, "p=%0.0fmin%0.0f s",floor(pace),floor(sec));//affichage au format minute puis seconde - 800292c: f8d7 00b4 ldr.w r0, [r7, #180] ; 0xb4 - 8002930: f7fd fe0a bl 8000548 <__aeabi_f2d> - 8002934: 4602 mov r2, r0 - 8002936: 460b mov r3, r1 - 8002938: ec43 2b10 vmov d0, r2, r3 - 800293c: f012 fee8 bl 8015710 - 8002940: eeb0 8a40 vmov.f32 s16, s0 - 8002944: eef0 8a60 vmov.f32 s17, s1 - 8002948: f8d7 00b0 ldr.w r0, [r7, #176] ; 0xb0 - 800294c: f7fd fdfc bl 8000548 <__aeabi_f2d> - 8002950: 4602 mov r2, r0 - 8002952: 460b mov r3, r1 - 8002954: ec43 2b10 vmov d0, r2, r3 - 8002958: f012 feda bl 8015710 - 800295c: eeb0 7a40 vmov.f32 s14, s0 - 8002960: eef0 7a60 vmov.f32 s15, s1 - 8002964: ed8d 7b02 vstr d7, [sp, #8] - 8002968: ed8d 8b00 vstr d8, [sp] - 800296c: 4a5e ldr r2, [pc, #376] ; (8002ae8 ) - 800296e: 210f movs r1, #15 - 8002970: 6db8 ldr r0, [r7, #88] ; 0x58 - 8002972: f00f ffdb bl 801292c - ssd1306_SetCursor(32, 52); - 8002976: 2134 movs r1, #52 ; 0x34 - 8002978: 2020 movs r0, #32 - 800297a: f7ff fced bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 800297e: 4a58 ldr r2, [pc, #352] ; (8002ae0 ) - 8002980: 2301 movs r3, #1 - 8002982: ca06 ldmia r2, {r1, r2} - 8002984: 6db8 ldr r0, [r7, #88] ; 0x58 - 8002986: f7ff fcc1 bl 800230c - free(str); - 800298a: 6db8 ldr r0, [r7, #88] ; 0x58 - 800298c: f00e f8da bl 8010b44 - 8002990: e01b b.n 80029ca - } - else{ //if the GPS doesn't have a fix, print a message - char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. - 8002992: 2014 movs r0, #20 - 8002994: f00e f8ce bl 8010b34 - 8002998: 4603 mov r3, r0 - 800299a: 65fb str r3, [r7, #92] ; 0x5c - ssd1306_SetCursor(32, 32); - 800299c: 2120 movs r1, #32 - 800299e: 2020 movs r0, #32 - 80029a0: f7ff fcda bl 8002358 - ssd1306_WriteString("Speed 1", Font_6x8, White); - 80029a4: 4a4e ldr r2, [pc, #312] ; (8002ae0 ) - 80029a6: 2301 movs r3, #1 - 80029a8: ca06 ldmia r2, {r1, r2} - 80029aa: 4850 ldr r0, [pc, #320] ; (8002aec ) - 80029ac: f7ff fcae bl 800230c - ssd1306_SetCursor(32, 44); - 80029b0: 212c movs r1, #44 ; 0x2c - 80029b2: 2020 movs r0, #32 - 80029b4: f7ff fcd0 bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 80029b8: 4a49 ldr r2, [pc, #292] ; (8002ae0 ) - 80029ba: 2301 movs r3, #1 - 80029bc: ca06 ldmia r2, {r1, r2} - 80029be: 484c ldr r0, [pc, #304] ; (8002af0 ) - 80029c0: f7ff fca4 bl 800230c - free(str); - 80029c4: 6df8 ldr r0, [r7, #92] ; 0x5c - 80029c6: f00e f8bd bl 8010b44 - } - if(BTN_B>=1){ - 80029ca: 4b4a ldr r3, [pc, #296] ; (8002af4 ) - 80029cc: 681b ldr r3, [r3, #0] - 80029ce: 2b00 cmp r3, #0 - 80029d0: f340 8122 ble.w 8002c18 - spdstate++; - 80029d4: 4b40 ldr r3, [pc, #256] ; (8002ad8 ) - 80029d6: 781b ldrb r3, [r3, #0] - 80029d8: 3301 adds r3, #1 - 80029da: b2da uxtb r2, r3 - 80029dc: 4b3e ldr r3, [pc, #248] ; (8002ad8 ) - 80029de: 701a strb r2, [r3, #0] - BTN_B=0; - 80029e0: 4b44 ldr r3, [pc, #272] ; (8002af4 ) - 80029e2: 2200 movs r2, #0 - 80029e4: 601a str r2, [r3, #0] - } + ssd1306_WriteCommand(0x40); //--set start line address - CHECK + 8002694: 2040 movs r0, #64 ; 0x40 + 8002696: f7ff ffaf bl 80025f8 + ssd1306_SetContrast(0xFF); + 800269a: 20ff movs r0, #255 ; 0xff + 800269c: f000 fb75 bl 8002d8a +#ifdef SSD1306_MIRROR_HORIZ + ssd1306_WriteCommand(0xA0); // Mirror horizontally +#else + ssd1306_WriteCommand(0xA1); //--set segment re-map 0 to 127 - CHECK + 80026a0: 20a1 movs r0, #161 ; 0xa1 + 80026a2: f7ff ffa9 bl 80025f8 +#endif - break; - 80029e6: e117 b.n 8002c18 - case STATE_COMPTEUR: - if(myData.fix == 1){ //if the GPS has a fix, print the data - 80029e8: 4b35 ldr r3, [pc, #212] ; (8002ac0 ) - 80029ea: 6a9b ldr r3, [r3, #40] ; 0x28 - 80029ec: 2b01 cmp r3, #1 - 80029ee: f040 8085 bne.w 8002afc - char * str = (char*)malloc(sizeof(char)*20); - 80029f2: 2014 movs r0, #20 - 80029f4: f00e f89e bl 8010b34 - 80029f8: 4603 mov r3, r0 - 80029fa: 663b str r3, [r7, #96] ; 0x60 - snprintf(str,15, "V=%0.1f",(myData.speed)*3.6); - 80029fc: 4b30 ldr r3, [pc, #192] ; (8002ac0 ) - 80029fe: 6b9b ldr r3, [r3, #56] ; 0x38 - 8002a00: 4618 mov r0, r3 - 8002a02: f7fd fda1 bl 8000548 <__aeabi_f2d> - 8002a06: a328 add r3, pc, #160 ; (adr r3, 8002aa8 ) - 8002a08: e9d3 2300 ldrd r2, r3, [r3] - 8002a0c: f7fd fdf4 bl 80005f8 <__aeabi_dmul> - 8002a10: 4602 mov r2, r0 - 8002a12: 460b mov r3, r1 - 8002a14: e9cd 2300 strd r2, r3, [sp] - 8002a18: 4a32 ldr r2, [pc, #200] ; (8002ae4 ) - 8002a1a: 210f movs r1, #15 - 8002a1c: 6e38 ldr r0, [r7, #96] ; 0x60 - 8002a1e: f00f ff85 bl 801292c - ssd1306_SetCursor(32, 54); - 8002a22: 2136 movs r1, #54 ; 0x36 - 8002a24: 2020 movs r0, #32 - 8002a26: f7ff fc97 bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002a2a: 4a2d ldr r2, [pc, #180] ; (8002ae0 ) - 8002a2c: 2301 movs r3, #1 - 8002a2e: ca06 ldmia r2, {r1, r2} - 8002a30: 6e38 ldr r0, [r7, #96] ; 0x60 - 8002a32: f7ff fc6b bl 800230c - ssd1306_DrawRectangle(32, 38, 95, 53, White); - 8002a36: 2301 movs r3, #1 - 8002a38: 9300 str r3, [sp, #0] - 8002a3a: 2335 movs r3, #53 ; 0x35 - 8002a3c: 225f movs r2, #95 ; 0x5f - 8002a3e: 2126 movs r1, #38 ; 0x26 - 8002a40: 2020 movs r0, #32 - 8002a42: f7ff fd94 bl 800256e - ssd1306_FillRectangle(32, 38,(int) floor(32+(myData.speed*0.63)), 53, White); - 8002a46: 4b1e ldr r3, [pc, #120] ; (8002ac0 ) - 8002a48: 6b9b ldr r3, [r3, #56] ; 0x38 - 8002a4a: 4618 mov r0, r3 - 8002a4c: f7fd fd7c bl 8000548 <__aeabi_f2d> - 8002a50: a317 add r3, pc, #92 ; (adr r3, 8002ab0 ) - 8002a52: e9d3 2300 ldrd r2, r3, [r3] - 8002a56: f7fd fdcf bl 80005f8 <__aeabi_dmul> - 8002a5a: 4602 mov r2, r0 - 8002a5c: 460b mov r3, r1 - 8002a5e: 4610 mov r0, r2 - 8002a60: 4619 mov r1, r3 - 8002a62: f04f 0200 mov.w r2, #0 - 8002a66: 4b24 ldr r3, [pc, #144] ; (8002af8 ) - 8002a68: f7fd fc10 bl 800028c <__adddf3> - 8002a6c: 4602 mov r2, r0 - 8002a6e: 460b mov r3, r1 - 8002a70: ec43 2b17 vmov d7, r2, r3 - 8002a74: eeb0 0a47 vmov.f32 s0, s14 - 8002a78: eef0 0a67 vmov.f32 s1, s15 - 8002a7c: f012 fe48 bl 8015710 - 8002a80: ec53 2b10 vmov r2, r3, d0 - 8002a84: 4610 mov r0, r2 - 8002a86: 4619 mov r1, r3 - 8002a88: f7fe f866 bl 8000b58 <__aeabi_d2iz> - 8002a8c: 4603 mov r3, r0 - 8002a8e: b2da uxtb r2, r3 - 8002a90: 2301 movs r3, #1 - 8002a92: 9300 str r3, [sp, #0] - 8002a94: 2335 movs r3, #53 ; 0x35 - 8002a96: 2126 movs r1, #38 ; 0x26 - 8002a98: 2020 movs r0, #32 - 8002a9a: f7ff fd9f bl 80025dc +#ifdef SSD1306_INVERSE_COLOR + ssd1306_WriteCommand(0xA7); //--set inverse color +#else + ssd1306_WriteCommand(0xA6); //--set normal color + 80026a6: 20a6 movs r0, #166 ; 0xa6 + 80026a8: f7ff ffa6 bl 80025f8 +// Set multiplex ratio. +#if (SSD1306_HEIGHT == 128) + // Found in the Luma Python lib for SH1106. + ssd1306_WriteCommand(0xFF); +#else + ssd1306_WriteCommand(0xA8); //--set multiplex ratio(1 to 64) - CHECK + 80026ac: 20a8 movs r0, #168 ; 0xa8 + 80026ae: f7ff ffa3 bl 80025f8 +#endif - free(str); - 8002a9e: 6e38 ldr r0, [r7, #96] ; 0x60 - 8002aa0: f00e f850 bl 8010b44 - 8002aa4: e046 b.n 8002b34 - 8002aa6: bf00 nop - 8002aa8: cccccccd .word 0xcccccccd - 8002aac: 400ccccc .word 0x400ccccc - 8002ab0: c28f5c29 .word 0xc28f5c29 - 8002ab4: 3fe428f5 .word 0x3fe428f5 - 8002ab8: 20000828 .word 0x20000828 - 8002abc: 200005e0 .word 0x200005e0 - 8002ac0: 200007e0 .word 0x200007e0 - 8002ac4: 20000c80 .word 0x20000c80 - 8002ac8: 42700000 .word 0x42700000 - 8002acc: 447a0000 .word 0x447a0000 - 8002ad0: 404e0000 .word 0x404e0000 - 8002ad4: 461c3c00 .word 0x461c3c00 - 8002ad8: 2000082a .word 0x2000082a - 8002adc: 080168fc .word 0x080168fc - 8002ae0: 20000008 .word 0x20000008 - 8002ae4: 08016908 .word 0x08016908 - 8002ae8: 08016910 .word 0x08016910 - 8002aec: 08016924 .word 0x08016924 - 8002af0: 0801692c .word 0x0801692c - 8002af4: 20000824 .word 0x20000824 - 8002af8: 40400000 .word 0x40400000 - } - else{ //if the GPS doesn't have a fix, print a message - char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. - 8002afc: 2014 movs r0, #20 - 8002afe: f00e f819 bl 8010b34 - 8002b02: 4603 mov r3, r0 - 8002b04: 667b str r3, [r7, #100] ; 0x64 - ssd1306_SetCursor(32, 32); - 8002b06: 2120 movs r1, #32 - 8002b08: 2020 movs r0, #32 - 8002b0a: f7ff fc25 bl 8002358 - ssd1306_WriteString("Speed 2", Font_6x8, White); - 8002b0e: 4a9a ldr r2, [pc, #616] ; (8002d78 ) - 8002b10: 2301 movs r3, #1 - 8002b12: ca06 ldmia r2, {r1, r2} - 8002b14: 4899 ldr r0, [pc, #612] ; (8002d7c ) - 8002b16: f7ff fbf9 bl 800230c - ssd1306_SetCursor(32, 44); - 8002b1a: 212c movs r1, #44 ; 0x2c - 8002b1c: 2020 movs r0, #32 - 8002b1e: f7ff fc1b bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 8002b22: 4a95 ldr r2, [pc, #596] ; (8002d78 ) - 8002b24: 2301 movs r3, #1 - 8002b26: ca06 ldmia r2, {r1, r2} - 8002b28: 4895 ldr r0, [pc, #596] ; (8002d80 ) - 8002b2a: f7ff fbef bl 800230c - free(str); - 8002b2e: 6e78 ldr r0, [r7, #100] ; 0x64 - 8002b30: f00e f808 bl 8010b44 - } - if(BTN_B>=1){ - 8002b34: 4b93 ldr r3, [pc, #588] ; (8002d84 ) - 8002b36: 681b ldr r3, [r3, #0] - 8002b38: 2b00 cmp r3, #0 - 8002b3a: dd6f ble.n 8002c1c - spdstate++; - 8002b3c: 4b92 ldr r3, [pc, #584] ; (8002d88 ) - 8002b3e: 781b ldrb r3, [r3, #0] - 8002b40: 3301 adds r3, #1 - 8002b42: b2da uxtb r2, r3 - 8002b44: 4b90 ldr r3, [pc, #576] ; (8002d88 ) - 8002b46: 701a strb r2, [r3, #0] - BTN_B=0; - 8002b48: 4b8e ldr r3, [pc, #568] ; (8002d84 ) - 8002b4a: 2200 movs r2, #0 - 8002b4c: 601a str r2, [r3, #0] - } - break; - 8002b4e: e065 b.n 8002c1c - case STATE_GRAPH: - if(myData.fix == 1){ - 8002b50: 4b8e ldr r3, [pc, #568] ; (8002d8c ) - 8002b52: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002b54: 2b01 cmp r3, #1 - 8002b56: d12f bne.n 8002bb8 - char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. - 8002b58: 2014 movs r0, #20 - 8002b5a: f00d ffeb bl 8010b34 - 8002b5e: 4603 mov r3, r0 - 8002b60: 66bb str r3, [r7, #104] ; 0x68 +#if (SSD1306_HEIGHT == 32) + ssd1306_WriteCommand(0x1F); // +#elif (SSD1306_HEIGHT == 64) + ssd1306_WriteCommand(0x3F); // + 80026b2: 203f movs r0, #63 ; 0x3f + 80026b4: f7ff ffa0 bl 80025f8 + ssd1306_WriteCommand(0x3F); // Seems to work for 128px high displays too. +#else +#error "Only 32, 64, or 128 lines of height are supported!" +#endif - ssd1306_SetCursor(32, 32); - 8002b62: 2120 movs r1, #32 - 8002b64: 2020 movs r0, #32 - 8002b66: f7ff fbf7 bl 8002358 - snprintf(str,15, "%0.1f",(myData.speed)*3.6); - 8002b6a: 4b88 ldr r3, [pc, #544] ; (8002d8c ) - 8002b6c: 6b9b ldr r3, [r3, #56] ; 0x38 - 8002b6e: 4618 mov r0, r3 - 8002b70: f7fd fcea bl 8000548 <__aeabi_f2d> - 8002b74: a37e add r3, pc, #504 ; (adr r3, 8002d70 ) - 8002b76: e9d3 2300 ldrd r2, r3, [r3] - 8002b7a: f7fd fd3d bl 80005f8 <__aeabi_dmul> - 8002b7e: 4602 mov r2, r0 - 8002b80: 460b mov r3, r1 - 8002b82: e9cd 2300 strd r2, r3, [sp] - 8002b86: 4a82 ldr r2, [pc, #520] ; (8002d90 ) - 8002b88: 210f movs r1, #15 - 8002b8a: 6eb8 ldr r0, [r7, #104] ; 0x68 - 8002b8c: f00f fece bl 801292c - ssd1306_WriteString(str, Font_11x18, White); - 8002b90: 4a80 ldr r2, [pc, #512] ; (8002d94 ) - 8002b92: 2301 movs r3, #1 - 8002b94: ca06 ldmia r2, {r1, r2} - 8002b96: 6eb8 ldr r0, [r7, #104] ; 0x68 - 8002b98: f7ff fbb8 bl 800230c - ssd1306_SetCursor(32, 54); - 8002b9c: 2136 movs r1, #54 ; 0x36 - 8002b9e: 2020 movs r0, #32 - 8002ba0: f7ff fbda bl 8002358 - ssd1306_WriteString("kmh", Font_6x8, White); - 8002ba4: 4a74 ldr r2, [pc, #464] ; (8002d78 ) - 8002ba6: 2301 movs r3, #1 - 8002ba8: ca06 ldmia r2, {r1, r2} - 8002baa: 487b ldr r0, [pc, #492] ; (8002d98 ) - 8002bac: f7ff fbae bl 800230c + ssd1306_WriteCommand(0xA4); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content + 80026b8: 20a4 movs r0, #164 ; 0xa4 + 80026ba: f7ff ff9d bl 80025f8 - free(str); - 8002bb0: 6eb8 ldr r0, [r7, #104] ; 0x68 - 8002bb2: f00d ffc7 bl 8010b44 - 8002bb6: e01b b.n 8002bf0 - } - else{ - char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. - 8002bb8: 2014 movs r0, #20 - 8002bba: f00d ffbb bl 8010b34 - 8002bbe: 4603 mov r3, r0 - 8002bc0: 66fb str r3, [r7, #108] ; 0x6c - ssd1306_SetCursor(32, 32); - 8002bc2: 2120 movs r1, #32 - 8002bc4: 2020 movs r0, #32 - 8002bc6: f7ff fbc7 bl 8002358 - ssd1306_WriteString("Speed 3", Font_6x8, White); - 8002bca: 4a6b ldr r2, [pc, #428] ; (8002d78 ) - 8002bcc: 2301 movs r3, #1 - 8002bce: ca06 ldmia r2, {r1, r2} - 8002bd0: 4872 ldr r0, [pc, #456] ; (8002d9c ) - 8002bd2: f7ff fb9b bl 800230c - ssd1306_SetCursor(32, 44); - 8002bd6: 212c movs r1, #44 ; 0x2c - 8002bd8: 2020 movs r0, #32 - 8002bda: f7ff fbbd bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 8002bde: 4a66 ldr r2, [pc, #408] ; (8002d78 ) - 8002be0: 2301 movs r3, #1 - 8002be2: ca06 ldmia r2, {r1, r2} - 8002be4: 4866 ldr r0, [pc, #408] ; (8002d80 ) - 8002be6: f7ff fb91 bl 800230c - free(str); - 8002bea: 6ef8 ldr r0, [r7, #108] ; 0x6c - 8002bec: f00d ffaa bl 8010b44 - } + ssd1306_WriteCommand(0xD3); //-set display offset - CHECK + 80026be: 20d3 movs r0, #211 ; 0xd3 + 80026c0: f7ff ff9a bl 80025f8 + ssd1306_WriteCommand(0x00); //-not offset + 80026c4: 2000 movs r0, #0 + 80026c6: f7ff ff97 bl 80025f8 - if(BTN_B>=1){ - 8002bf0: 4b64 ldr r3, [pc, #400] ; (8002d84 ) - 8002bf2: 681b ldr r3, [r3, #0] - 8002bf4: 2b00 cmp r3, #0 - 8002bf6: dd13 ble.n 8002c20 - spdstate--; - 8002bf8: 4b63 ldr r3, [pc, #396] ; (8002d88 ) - 8002bfa: 781b ldrb r3, [r3, #0] - 8002bfc: 3b01 subs r3, #1 - 8002bfe: b2da uxtb r2, r3 - 8002c00: 4b61 ldr r3, [pc, #388] ; (8002d88 ) - 8002c02: 701a strb r2, [r3, #0] - spdstate--; - 8002c04: 4b60 ldr r3, [pc, #384] ; (8002d88 ) - 8002c06: 781b ldrb r3, [r3, #0] - 8002c08: 3b01 subs r3, #1 - 8002c0a: b2da uxtb r2, r3 - 8002c0c: 4b5e ldr r3, [pc, #376] ; (8002d88 ) - 8002c0e: 701a strb r2, [r3, #0] - BTN_B=0; - 8002c10: 4b5c ldr r3, [pc, #368] ; (8002d84 ) - 8002c12: 2200 movs r2, #0 - 8002c14: 601a str r2, [r3, #0] + ssd1306_WriteCommand(0xD5); //--set display clock divide ratio/oscillator frequency + 80026ca: 20d5 movs r0, #213 ; 0xd5 + 80026cc: f7ff ff94 bl 80025f8 + ssd1306_WriteCommand(0xF0); //--set divide ratio + 80026d0: 20f0 movs r0, #240 ; 0xf0 + 80026d2: f7ff ff91 bl 80025f8 + ssd1306_WriteCommand(0xD9); //--set pre-charge period + 80026d6: 20d9 movs r0, #217 ; 0xd9 + 80026d8: f7ff ff8e bl 80025f8 + ssd1306_WriteCommand(0x22); // + 80026dc: 2022 movs r0, #34 ; 0x22 + 80026de: f7ff ff8b bl 80025f8 - } - break; - 8002c16: e003 b.n 8002c20 - break; - 8002c18: bf00 nop - 8002c1a: e002 b.n 8002c22 - break; - 8002c1c: bf00 nop - 8002c1e: e000 b.n 8002c22 - break; - 8002c20: bf00 nop + ssd1306_WriteCommand(0xDA); //--set com pins hardware configuration - CHECK + 80026e2: 20da movs r0, #218 ; 0xda + 80026e4: f7ff ff88 bl 80025f8 +#if (SSD1306_HEIGHT == 32) + ssd1306_WriteCommand(0x02); +#elif (SSD1306_HEIGHT == 64) + ssd1306_WriteCommand(0x12); + 80026e8: 2012 movs r0, #18 + 80026ea: f7ff ff85 bl 80025f8 + ssd1306_WriteCommand(0x12); +#else +#error "Only 32, 64, or 128 lines of height are supported!" +#endif + ssd1306_WriteCommand(0xDB); //--set vcomh + 80026ee: 20db movs r0, #219 ; 0xdb + 80026f0: f7ff ff82 bl 80025f8 + ssd1306_WriteCommand(0x20); //0x20,0.77xVcc + 80026f4: 2020 movs r0, #32 + 80026f6: f7ff ff7f bl 80025f8 - } - if(BTN_A>=1){ - 8002c22: 4b5f ldr r3, [pc, #380] ; (8002da0 ) - 8002c24: 681b ldr r3, [r3, #0] - 8002c26: 2b00 cmp r3, #0 - 8002c28: f341 808f ble.w 8003d4a - state++; - 8002c2c: 4b5d ldr r3, [pc, #372] ; (8002da4 ) - 8002c2e: 781b ldrb r3, [r3, #0] - 8002c30: 3301 adds r3, #1 - 8002c32: b2da uxtb r2, r3 - 8002c34: 4b5b ldr r3, [pc, #364] ; (8002da4 ) - 8002c36: 701a strb r2, [r3, #0] - BTN_A=0; - 8002c38: 4b59 ldr r3, [pc, #356] ; (8002da0 ) - 8002c3a: 2200 movs r2, #0 - 8002c3c: 601a str r2, [r3, #0] - } - break; - 8002c3e: f001 b884 b.w 8003d4a + ssd1306_WriteCommand(0x8D); //--set DC-DC enable + 80026fa: 208d movs r0, #141 ; 0x8d + 80026fc: f7ff ff7c bl 80025f8 + ssd1306_WriteCommand(0x14); // + 8002700: 2014 movs r0, #20 + 8002702: f7ff ff79 bl 80025f8 + ssd1306_SetDisplayOn(1); //--turn on SSD1306 panel + 8002706: 2001 movs r0, #1 + 8002708: f000 fb52 bl 8002db0 + // Clear screen + ssd1306_Fill(Black); + 800270c: 2000 movs r0, #0 + 800270e: f000 f80f bl 8002730 + + // Flush buffer to screen + ssd1306_UpdateScreen(); + 8002712: f000 f825 bl 8002760 + + // Set default values for screen object + SSD1306.CurrentX = 0; + 8002716: 4b05 ldr r3, [pc, #20] ; (800272c ) + 8002718: 2200 movs r2, #0 + 800271a: 801a strh r2, [r3, #0] + SSD1306.CurrentY = 0; + 800271c: 4b03 ldr r3, [pc, #12] ; (800272c ) + 800271e: 2200 movs r2, #0 + 8002720: 805a strh r2, [r3, #2] + + SSD1306.Initialized = 1; + 8002722: 4b02 ldr r3, [pc, #8] ; (800272c ) + 8002724: 2201 movs r2, #1 + 8002726: 711a strb r2, [r3, #4] +} + 8002728: bf00 nop + 800272a: bd80 pop {r7, pc} + 800272c: 20000e2c .word 0x20000e2c - case STATE_POS: - ssd1306_Fill(Black); - 8002c42: 2000 movs r0, #0 - 8002c44: f7ff fa46 bl 80020d4 - nmea_parse(&myData, DataBuffer); - 8002c48: 4957 ldr r1, [pc, #348] ; (8002da8 ) - 8002c4a: 4850 ldr r0, [pc, #320] ; (8002d8c ) - 8002c4c: f7ff f8ee bl 8001e2c - switch(posstate){ - 8002c50: 4b56 ldr r3, [pc, #344] ; (8002dac ) - 8002c52: 781b ldrb r3, [r3, #0] - 8002c54: 2b03 cmp r3, #3 - 8002c56: f200 828d bhi.w 8003174 - 8002c5a: a201 add r2, pc, #4 ; (adr r2, 8002c60 ) - 8002c5c: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8002c60: 08002c71 .word 0x08002c71 - 8002c64: 08002dc1 .word 0x08002dc1 - 8002c68: 08002eb7 .word 0x08002eb7 - 8002c6c: 08002ff9 .word 0x08002ff9 +08002730 : - case STATE_SUMMARY1: - if(myData.fix == 1){ - 8002c70: 4b46 ldr r3, [pc, #280] ; (8002d8c ) - 8002c72: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002c74: 2b01 cmp r3, #1 - 8002c76: d14e bne.n 8002d16 - char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages - 8002c78: 2014 movs r0, #20 - 8002c7a: f00d ff5b bl 8010b34 - 8002c7e: 4603 mov r3, r0 - 8002c80: 673b str r3, [r7, #112] ; 0x70 - ssd1306_SetCursor(32, 32); - 8002c82: 2120 movs r1, #32 - 8002c84: 2020 movs r0, #32 - 8002c86: f7ff fb67 bl 8002358 - snprintf(str,15, "Latitude:"); - 8002c8a: 4a49 ldr r2, [pc, #292] ; (8002db0 ) - 8002c8c: 210f movs r1, #15 - 8002c8e: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002c90: f00f fe4c bl 801292c - ssd1306_WriteString(str, Font_6x8, White); - 8002c94: 4a38 ldr r2, [pc, #224] ; (8002d78 ) - 8002c96: 2301 movs r3, #1 - 8002c98: ca06 ldmia r2, {r1, r2} - 8002c9a: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002c9c: f7ff fb36 bl 800230c - snprintf(str,15, "%0.7f",myData.latitude);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps - 8002ca0: 4b3a ldr r3, [pc, #232] ; (8002d8c ) - 8002ca2: e9d3 2300 ldrd r2, r3, [r3] - 8002ca6: e9cd 2300 strd r2, r3, [sp] - 8002caa: 4a42 ldr r2, [pc, #264] ; (8002db4 ) - 8002cac: 210f movs r1, #15 - 8002cae: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002cb0: f00f fe3c bl 801292c - ssd1306_SetCursor(32, 40); - 8002cb4: 2128 movs r1, #40 ; 0x28 - 8002cb6: 2020 movs r0, #32 - 8002cb8: f7ff fb4e bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002cbc: 4a2e ldr r2, [pc, #184] ; (8002d78 ) - 8002cbe: 2301 movs r3, #1 - 8002cc0: ca06 ldmia r2, {r1, r2} - 8002cc2: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002cc4: f7ff fb22 bl 800230c - snprintf(str,15, "Longitude:"); - 8002cc8: 4a3b ldr r2, [pc, #236] ; (8002db8 ) - 8002cca: 210f movs r1, #15 - 8002ccc: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002cce: f00f fe2d bl 801292c - ssd1306_SetCursor(32, 48); - 8002cd2: 2130 movs r1, #48 ; 0x30 - 8002cd4: 2020 movs r0, #32 - 8002cd6: f7ff fb3f bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002cda: 4a27 ldr r2, [pc, #156] ; (8002d78 ) - 8002cdc: 2301 movs r3, #1 - 8002cde: ca06 ldmia r2, {r1, r2} - 8002ce0: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002ce2: f7ff fb13 bl 800230c - snprintf(str,15, "%0.7f",myData.longitude); - 8002ce6: 4b29 ldr r3, [pc, #164] ; (8002d8c ) - 8002ce8: e9d3 2304 ldrd r2, r3, [r3, #16] - 8002cec: e9cd 2300 strd r2, r3, [sp] - 8002cf0: 4a30 ldr r2, [pc, #192] ; (8002db4 ) - 8002cf2: 210f movs r1, #15 - 8002cf4: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002cf6: f00f fe19 bl 801292c - ssd1306_SetCursor(32, 56); - 8002cfa: 2138 movs r1, #56 ; 0x38 - 8002cfc: 2020 movs r0, #32 - 8002cfe: f7ff fb2b bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002d02: 4a1d ldr r2, [pc, #116] ; (8002d78 ) - 8002d04: 2301 movs r3, #1 - 8002d06: ca06 ldmia r2, {r1, r2} - 8002d08: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002d0a: f7ff faff bl 800230c - free(str); - 8002d0e: 6f38 ldr r0, [r7, #112] ; 0x70 - 8002d10: f00d ff18 bl 8010b44 - 8002d14: e01b b.n 8002d4e - } - else{ //if the GPS doesn't have a fix, print a message - char *str = (char*)malloc(sizeof(char)*20); - 8002d16: 2014 movs r0, #20 - 8002d18: f00d ff0c bl 8010b34 - 8002d1c: 4603 mov r3, r0 - 8002d1e: 677b str r3, [r7, #116] ; 0x74 - ssd1306_SetCursor(32, 32); - 8002d20: 2120 movs r1, #32 - 8002d22: 2020 movs r0, #32 - 8002d24: f7ff fb18 bl 8002358 - ssd1306_WriteString("Pos1", Font_6x8, White); - 8002d28: 4a13 ldr r2, [pc, #76] ; (8002d78 ) - 8002d2a: 2301 movs r3, #1 - 8002d2c: ca06 ldmia r2, {r1, r2} - 8002d2e: 4823 ldr r0, [pc, #140] ; (8002dbc ) - 8002d30: f7ff faec bl 800230c - ssd1306_SetCursor(32, 44); - 8002d34: 212c movs r1, #44 ; 0x2c - 8002d36: 2020 movs r0, #32 - 8002d38: f7ff fb0e bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 8002d3c: 4a0e ldr r2, [pc, #56] ; (8002d78 ) - 8002d3e: 2301 movs r3, #1 - 8002d40: ca06 ldmia r2, {r1, r2} - 8002d42: 480f ldr r0, [pc, #60] ; (8002d80 ) - 8002d44: f7ff fae2 bl 800230c - free(str); - 8002d48: 6f78 ldr r0, [r7, #116] ; 0x74 - 8002d4a: f00d fefb bl 8010b44 - } - if(BTN_B>=1){ - 8002d4e: 4b0d ldr r3, [pc, #52] ; (8002d84 ) - 8002d50: 681b ldr r3, [r3, #0] - 8002d52: 2b00 cmp r3, #0 - 8002d54: f340 8207 ble.w 8003166 - posstate++; - 8002d58: 4b14 ldr r3, [pc, #80] ; (8002dac ) - 8002d5a: 781b ldrb r3, [r3, #0] - 8002d5c: 3301 adds r3, #1 - 8002d5e: b2da uxtb r2, r3 - 8002d60: 4b12 ldr r3, [pc, #72] ; (8002dac ) - 8002d62: 701a strb r2, [r3, #0] - BTN_B=0; - 8002d64: 4b07 ldr r3, [pc, #28] ; (8002d84 ) - 8002d66: 2200 movs r2, #0 - 8002d68: 601a str r2, [r3, #0] +/* Fill the whole screen with the given color */ +void ssd1306_Fill(SSD1306_COLOR color) { + 8002730: b580 push {r7, lr} + 8002732: b082 sub sp, #8 + 8002734: af00 add r7, sp, #0 + 8002736: 4603 mov r3, r0 + 8002738: 71fb strb r3, [r7, #7] + memset(SSD1306_Buffer, (color == Black) ? 0x00 : 0xFF, sizeof(SSD1306_Buffer)); + 800273a: 79fb ldrb r3, [r7, #7] + 800273c: 2b00 cmp r3, #0 + 800273e: d101 bne.n 8002744 + 8002740: 2300 movs r3, #0 + 8002742: e000 b.n 8002746 + 8002744: 23ff movs r3, #255 ; 0xff + 8002746: f44f 6280 mov.w r2, #1024 ; 0x400 + 800274a: 4619 mov r1, r3 + 800274c: 4803 ldr r0, [pc, #12] ; (800275c ) + 800274e: f012 fbdc bl 8014f0a +} + 8002752: bf00 nop + 8002754: 3708 adds r7, #8 + 8002756: 46bd mov sp, r7 + 8002758: bd80 pop {r7, pc} + 800275a: bf00 nop + 800275c: 20000a2c .word 0x20000a2c + +08002760 : +/* Write the screenbuffer with changed to the screen */ +void ssd1306_UpdateScreen(void) { + 8002760: b580 push {r7, lr} + 8002762: b082 sub sp, #8 + 8002764: af00 add r7, sp, #0 + // depends on the screen height: + // + // * 32px == 4 pages + // * 64px == 8 pages + // * 128px == 16 pages + for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) { + 8002766: 2300 movs r3, #0 + 8002768: 71fb strb r3, [r7, #7] + 800276a: e016 b.n 800279a + ssd1306_WriteCommand(0xB0 + i); // Set the current RAM page address. + 800276c: 79fb ldrb r3, [r7, #7] + 800276e: 3b50 subs r3, #80 ; 0x50 + 8002770: b2db uxtb r3, r3 + 8002772: 4618 mov r0, r3 + 8002774: f7ff ff40 bl 80025f8 + ssd1306_WriteCommand(0x00 + SSD1306_X_OFFSET_LOWER); + 8002778: 2000 movs r0, #0 + 800277a: f7ff ff3d bl 80025f8 + ssd1306_WriteCommand(0x10 + SSD1306_X_OFFSET_UPPER); + 800277e: 2010 movs r0, #16 + 8002780: f7ff ff3a bl 80025f8 + ssd1306_WriteData(&SSD1306_Buffer[SSD1306_WIDTH*i],SSD1306_WIDTH); + 8002784: 79fb ldrb r3, [r7, #7] + 8002786: 01db lsls r3, r3, #7 + 8002788: 4a08 ldr r2, [pc, #32] ; (80027ac ) + 800278a: 4413 add r3, r2 + 800278c: 2180 movs r1, #128 ; 0x80 + 800278e: 4618 mov r0, r3 + 8002790: f7ff ff4a bl 8002628 + for(uint8_t i = 0; i < SSD1306_HEIGHT/8; i++) { + 8002794: 79fb ldrb r3, [r7, #7] + 8002796: 3301 adds r3, #1 + 8002798: 71fb strb r3, [r7, #7] + 800279a: 79fb ldrb r3, [r7, #7] + 800279c: 2b07 cmp r3, #7 + 800279e: d9e5 bls.n 800276c + } +} + 80027a0: bf00 nop + 80027a2: bf00 nop + 80027a4: 3708 adds r7, #8 + 80027a6: 46bd mov sp, r7 + 80027a8: bd80 pop {r7, pc} + 80027aa: bf00 nop + 80027ac: 20000a2c .word 0x20000a2c +080027b0 : + * Draw one pixel in the screenbuffer + * X => X Coordinate + * Y => Y Coordinate + * color => Pixel color + */ +void ssd1306_DrawPixel(uint8_t x, uint8_t y, SSD1306_COLOR color) { + 80027b0: b480 push {r7} + 80027b2: b083 sub sp, #12 + 80027b4: af00 add r7, sp, #0 + 80027b6: 4603 mov r3, r0 + 80027b8: 71fb strb r3, [r7, #7] + 80027ba: 460b mov r3, r1 + 80027bc: 71bb strb r3, [r7, #6] + 80027be: 4613 mov r3, r2 + 80027c0: 717b strb r3, [r7, #5] + if(x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { + 80027c2: f997 3007 ldrsb.w r3, [r7, #7] + 80027c6: 2b00 cmp r3, #0 + 80027c8: db3d blt.n 8002846 + 80027ca: 79bb ldrb r3, [r7, #6] + 80027cc: 2b3f cmp r3, #63 ; 0x3f + 80027ce: d83a bhi.n 8002846 + // Don't write outside the buffer + return; + } + + // Draw in the right color + if(color == White) { + 80027d0: 797b ldrb r3, [r7, #5] + 80027d2: 2b01 cmp r3, #1 + 80027d4: d11a bne.n 800280c + SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] |= 1 << (y % 8); + 80027d6: 79fa ldrb r2, [r7, #7] + 80027d8: 79bb ldrb r3, [r7, #6] + 80027da: 08db lsrs r3, r3, #3 + 80027dc: b2d8 uxtb r0, r3 + 80027de: 4603 mov r3, r0 + 80027e0: 01db lsls r3, r3, #7 + 80027e2: 4413 add r3, r2 + 80027e4: 4a1b ldr r2, [pc, #108] ; (8002854 ) + 80027e6: 5cd3 ldrb r3, [r2, r3] + 80027e8: b25a sxtb r2, r3 + 80027ea: 79bb ldrb r3, [r7, #6] + 80027ec: f003 0307 and.w r3, r3, #7 + 80027f0: 2101 movs r1, #1 + 80027f2: fa01 f303 lsl.w r3, r1, r3 + 80027f6: b25b sxtb r3, r3 + 80027f8: 4313 orrs r3, r2 + 80027fa: b259 sxtb r1, r3 + 80027fc: 79fa ldrb r2, [r7, #7] + 80027fe: 4603 mov r3, r0 + 8002800: 01db lsls r3, r3, #7 + 8002802: 4413 add r3, r2 + 8002804: b2c9 uxtb r1, r1 + 8002806: 4a13 ldr r2, [pc, #76] ; (8002854 ) + 8002808: 54d1 strb r1, [r2, r3] + 800280a: e01d b.n 8002848 + } else { + SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] &= ~(1 << (y % 8)); + 800280c: 79fa ldrb r2, [r7, #7] + 800280e: 79bb ldrb r3, [r7, #6] + 8002810: 08db lsrs r3, r3, #3 + 8002812: b2d8 uxtb r0, r3 + 8002814: 4603 mov r3, r0 + 8002816: 01db lsls r3, r3, #7 + 8002818: 4413 add r3, r2 + 800281a: 4a0e ldr r2, [pc, #56] ; (8002854 ) + 800281c: 5cd3 ldrb r3, [r2, r3] + 800281e: b25a sxtb r2, r3 + 8002820: 79bb ldrb r3, [r7, #6] + 8002822: f003 0307 and.w r3, r3, #7 + 8002826: 2101 movs r1, #1 + 8002828: fa01 f303 lsl.w r3, r1, r3 + 800282c: b25b sxtb r3, r3 + 800282e: 43db mvns r3, r3 + 8002830: b25b sxtb r3, r3 + 8002832: 4013 ands r3, r2 + 8002834: b259 sxtb r1, r3 + 8002836: 79fa ldrb r2, [r7, #7] + 8002838: 4603 mov r3, r0 + 800283a: 01db lsls r3, r3, #7 + 800283c: 4413 add r3, r2 + 800283e: b2c9 uxtb r1, r1 + 8002840: 4a04 ldr r2, [pc, #16] ; (8002854 ) + 8002842: 54d1 strb r1, [r2, r3] + 8002844: e000 b.n 8002848 + return; + 8002846: bf00 nop + } +} + 8002848: 370c adds r7, #12 + 800284a: 46bd mov sp, r7 + 800284c: f85d 7b04 ldr.w r7, [sp], #4 + 8002850: 4770 bx lr + 8002852: bf00 nop + 8002854: 20000a2c .word 0x20000a2c +08002858 : + * Draw 1 char to the screen buffer + * ch => char om weg te schrijven + * Font => Font waarmee we gaan schrijven + * color => Black or White + */ +char ssd1306_WriteChar(char ch, FontDef Font, SSD1306_COLOR color) { + 8002858: b590 push {r4, r7, lr} + 800285a: b089 sub sp, #36 ; 0x24 + 800285c: af00 add r7, sp, #0 + 800285e: 4604 mov r4, r0 + 8002860: 1d38 adds r0, r7, #4 + 8002862: e880 0006 stmia.w r0, {r1, r2} + 8002866: 461a mov r2, r3 + 8002868: 4623 mov r3, r4 + 800286a: 73fb strb r3, [r7, #15] + 800286c: 4613 mov r3, r2 + 800286e: 73bb strb r3, [r7, #14] + uint32_t i, b, j; + + // Check if character is valid + if (ch < 32 || ch > 126) + 8002870: 7bfb ldrb r3, [r7, #15] + 8002872: 2b1f cmp r3, #31 + 8002874: d902 bls.n 800287c + 8002876: 7bfb ldrb r3, [r7, #15] + 8002878: 2b7e cmp r3, #126 ; 0x7e + 800287a: d901 bls.n 8002880 + return 0; + 800287c: 2300 movs r3, #0 + 800287e: e06d b.n 800295c + + // Check remaining space on current line + if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) || + 8002880: 4b38 ldr r3, [pc, #224] ; (8002964 ) + 8002882: 881b ldrh r3, [r3, #0] + 8002884: 461a mov r2, r3 + 8002886: 793b ldrb r3, [r7, #4] + 8002888: 4413 add r3, r2 + 800288a: 2b80 cmp r3, #128 ; 0x80 + 800288c: dc06 bgt.n 800289c + SSD1306_HEIGHT < (SSD1306.CurrentY + Font.FontHeight)) + 800288e: 4b35 ldr r3, [pc, #212] ; (8002964 ) + 8002890: 885b ldrh r3, [r3, #2] + 8002892: 461a mov r2, r3 + 8002894: 797b ldrb r3, [r7, #5] + 8002896: 4413 add r3, r2 + if (SSD1306_WIDTH < (SSD1306.CurrentX + Font.FontWidth) || + 8002898: 2b40 cmp r3, #64 ; 0x40 + 800289a: dd01 ble.n 80028a0 + { + // Not enough space on current line + return 0; + 800289c: 2300 movs r3, #0 + 800289e: e05d b.n 800295c + } + + // Use the font to write + for(i = 0; i < Font.FontHeight; i++) { + 80028a0: 2300 movs r3, #0 + 80028a2: 61fb str r3, [r7, #28] + 80028a4: e04c b.n 8002940 + b = Font.data[(ch - 32) * Font.FontHeight + i]; + 80028a6: 68ba ldr r2, [r7, #8] + 80028a8: 7bfb ldrb r3, [r7, #15] + 80028aa: 3b20 subs r3, #32 + 80028ac: 7979 ldrb r1, [r7, #5] + 80028ae: fb01 f303 mul.w r3, r1, r3 + 80028b2: 4619 mov r1, r3 + 80028b4: 69fb ldr r3, [r7, #28] + 80028b6: 440b add r3, r1 + 80028b8: 005b lsls r3, r3, #1 + 80028ba: 4413 add r3, r2 + 80028bc: 881b ldrh r3, [r3, #0] + 80028be: 617b str r3, [r7, #20] + for(j = 0; j < Font.FontWidth; j++) { + 80028c0: 2300 movs r3, #0 + 80028c2: 61bb str r3, [r7, #24] + 80028c4: e034 b.n 8002930 + if((b << j) & 0x8000) { + 80028c6: 697a ldr r2, [r7, #20] + 80028c8: 69bb ldr r3, [r7, #24] + 80028ca: fa02 f303 lsl.w r3, r2, r3 + 80028ce: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 80028d2: 2b00 cmp r3, #0 + 80028d4: d012 beq.n 80028fc + ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR) color); + 80028d6: 4b23 ldr r3, [pc, #140] ; (8002964 ) + 80028d8: 881b ldrh r3, [r3, #0] + 80028da: b2da uxtb r2, r3 + 80028dc: 69bb ldr r3, [r7, #24] + 80028de: b2db uxtb r3, r3 + 80028e0: 4413 add r3, r2 + 80028e2: b2d8 uxtb r0, r3 + 80028e4: 4b1f ldr r3, [pc, #124] ; (8002964 ) + 80028e6: 885b ldrh r3, [r3, #2] + 80028e8: b2da uxtb r2, r3 + 80028ea: 69fb ldr r3, [r7, #28] + 80028ec: b2db uxtb r3, r3 + 80028ee: 4413 add r3, r2 + 80028f0: b2db uxtb r3, r3 + 80028f2: 7bba ldrb r2, [r7, #14] + 80028f4: 4619 mov r1, r3 + 80028f6: f7ff ff5b bl 80027b0 + 80028fa: e016 b.n 800292a + } else { + ssd1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR)!color); + 80028fc: 4b19 ldr r3, [pc, #100] ; (8002964 ) + 80028fe: 881b ldrh r3, [r3, #0] + 8002900: b2da uxtb r2, r3 + 8002902: 69bb ldr r3, [r7, #24] + 8002904: b2db uxtb r3, r3 + 8002906: 4413 add r3, r2 + 8002908: b2d8 uxtb r0, r3 + 800290a: 4b16 ldr r3, [pc, #88] ; (8002964 ) + 800290c: 885b ldrh r3, [r3, #2] + 800290e: b2da uxtb r2, r3 + 8002910: 69fb ldr r3, [r7, #28] + 8002912: b2db uxtb r3, r3 + 8002914: 4413 add r3, r2 + 8002916: b2d9 uxtb r1, r3 + 8002918: 7bbb ldrb r3, [r7, #14] + 800291a: 2b00 cmp r3, #0 + 800291c: bf0c ite eq + 800291e: 2301 moveq r3, #1 + 8002920: 2300 movne r3, #0 + 8002922: b2db uxtb r3, r3 + 8002924: 461a mov r2, r3 + 8002926: f7ff ff43 bl 80027b0 + for(j = 0; j < Font.FontWidth; j++) { + 800292a: 69bb ldr r3, [r7, #24] + 800292c: 3301 adds r3, #1 + 800292e: 61bb str r3, [r7, #24] + 8002930: 793b ldrb r3, [r7, #4] + 8002932: 461a mov r2, r3 + 8002934: 69bb ldr r3, [r7, #24] + 8002936: 4293 cmp r3, r2 + 8002938: d3c5 bcc.n 80028c6 + for(i = 0; i < Font.FontHeight; i++) { + 800293a: 69fb ldr r3, [r7, #28] + 800293c: 3301 adds r3, #1 + 800293e: 61fb str r3, [r7, #28] + 8002940: 797b ldrb r3, [r7, #5] + 8002942: 461a mov r2, r3 + 8002944: 69fb ldr r3, [r7, #28] + 8002946: 4293 cmp r3, r2 + 8002948: d3ad bcc.n 80028a6 + } + } + } + + // The current space is now taken + SSD1306.CurrentX += Font.FontWidth; + 800294a: 4b06 ldr r3, [pc, #24] ; (8002964 ) + 800294c: 881a ldrh r2, [r3, #0] + 800294e: 793b ldrb r3, [r7, #4] + 8002950: b29b uxth r3, r3 + 8002952: 4413 add r3, r2 + 8002954: b29a uxth r2, r3 + 8002956: 4b03 ldr r3, [pc, #12] ; (8002964 ) + 8002958: 801a strh r2, [r3, #0] + + // Return written char for validation + return ch; + 800295a: 7bfb ldrb r3, [r7, #15] +} + 800295c: 4618 mov r0, r3 + 800295e: 3724 adds r7, #36 ; 0x24 + 8002960: 46bd mov sp, r7 + 8002962: bd90 pop {r4, r7, pc} + 8002964: 20000e2c .word 0x20000e2c +08002968 : - break; - 8002d6a: e1fc b.n 8003166 - 8002d6c: f3af 8000 nop.w - 8002d70: cccccccd .word 0xcccccccd - 8002d74: 400ccccc .word 0x400ccccc - 8002d78: 20000008 .word 0x20000008 - 8002d7c: 08016938 .word 0x08016938 - 8002d80: 0801692c .word 0x0801692c - 8002d84: 20000824 .word 0x20000824 - 8002d88: 2000082a .word 0x2000082a - 8002d8c: 200007e0 .word 0x200007e0 - 8002d90: 08016940 .word 0x08016940 - 8002d94: 20000018 .word 0x20000018 - 8002d98: 08016948 .word 0x08016948 - 8002d9c: 0801694c .word 0x0801694c - 8002da0: 20000820 .word 0x20000820 - 8002da4: 20000828 .word 0x20000828 - 8002da8: 200005e0 .word 0x200005e0 - 8002dac: 2000082b .word 0x2000082b - 8002db0: 08016954 .word 0x08016954 - 8002db4: 08016960 .word 0x08016960 - 8002db8: 08016968 .word 0x08016968 - 8002dbc: 08016974 .word 0x08016974 - case STATE_LAT: - if(myData.fix == 1){ - 8002dc0: 4b80 ldr r3, [pc, #512] ; (8002fc4 ) - 8002dc2: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002dc4: 2b01 cmp r3, #1 - 8002dc6: d14b bne.n 8002e60 - char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages - 8002dc8: 2014 movs r0, #20 - 8002dca: f00d feb3 bl 8010b34 - 8002dce: 4603 mov r3, r0 - 8002dd0: 67bb str r3, [r7, #120] ; 0x78 - ssd1306_SetCursor(32, 32); - 8002dd2: 2120 movs r1, #32 - 8002dd4: 2020 movs r0, #32 - 8002dd6: f7ff fabf bl 8002358 - snprintf(str,15, "LatSide:"); - 8002dda: 4a7b ldr r2, [pc, #492] ; (8002fc8 ) - 8002ddc: 210f movs r1, #15 - 8002dde: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002de0: f00f fda4 bl 801292c - ssd1306_WriteString(str, Font_6x8, White); - 8002de4: 4a79 ldr r2, [pc, #484] ; (8002fcc ) - 8002de6: 2301 movs r3, #1 - 8002de8: ca06 ldmia r2, {r1, r2} - 8002dea: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002dec: f7ff fa8e bl 800230c - snprintf(str,15, "%c",myData.latSide);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps - 8002df0: 4b74 ldr r3, [pc, #464] ; (8002fc4 ) - 8002df2: 7a1b ldrb r3, [r3, #8] - 8002df4: 4a76 ldr r2, [pc, #472] ; (8002fd0 ) - 8002df6: 210f movs r1, #15 - 8002df8: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002dfa: f00f fd97 bl 801292c - ssd1306_SetCursor(32, 40); - 8002dfe: 2128 movs r1, #40 ; 0x28 - 8002e00: 2020 movs r0, #32 - 8002e02: f7ff faa9 bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002e06: 4a71 ldr r2, [pc, #452] ; (8002fcc ) - 8002e08: 2301 movs r3, #1 - 8002e0a: ca06 ldmia r2, {r1, r2} - 8002e0c: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e0e: f7ff fa7d bl 800230c - snprintf(str,15, "Latitude:"); - 8002e12: 4a70 ldr r2, [pc, #448] ; (8002fd4 ) - 8002e14: 210f movs r1, #15 - 8002e16: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e18: f00f fd88 bl 801292c - ssd1306_SetCursor(32, 48); - 8002e1c: 2130 movs r1, #48 ; 0x30 - 8002e1e: 2020 movs r0, #32 - 8002e20: f7ff fa9a bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002e24: 4a69 ldr r2, [pc, #420] ; (8002fcc ) - 8002e26: 2301 movs r3, #1 - 8002e28: ca06 ldmia r2, {r1, r2} - 8002e2a: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e2c: f7ff fa6e bl 800230c - snprintf(str,15, "%0.7f",myData.latitude); - 8002e30: 4b64 ldr r3, [pc, #400] ; (8002fc4 ) - 8002e32: e9d3 2300 ldrd r2, r3, [r3] - 8002e36: e9cd 2300 strd r2, r3, [sp] - 8002e3a: 4a67 ldr r2, [pc, #412] ; (8002fd8 ) - 8002e3c: 210f movs r1, #15 - 8002e3e: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e40: f00f fd74 bl 801292c - ssd1306_SetCursor(32, 56); - 8002e44: 2138 movs r1, #56 ; 0x38 - 8002e46: 2020 movs r0, #32 - 8002e48: f7ff fa86 bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8002e4c: 4a5f ldr r2, [pc, #380] ; (8002fcc ) - 8002e4e: 2301 movs r3, #1 - 8002e50: ca06 ldmia r2, {r1, r2} - 8002e52: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e54: f7ff fa5a bl 800230c - free(str); - 8002e58: 6fb8 ldr r0, [r7, #120] ; 0x78 - 8002e5a: f00d fe73 bl 8010b44 - 8002e5e: e01b b.n 8002e98 - } - else{ //if the GPS doesn't have a fix, print a message - char *str = (char*)malloc(sizeof(char)*20); - 8002e60: 2014 movs r0, #20 - 8002e62: f00d fe67 bl 8010b34 - 8002e66: 4603 mov r3, r0 - 8002e68: 67fb str r3, [r7, #124] ; 0x7c - ssd1306_SetCursor(32, 32); - 8002e6a: 2120 movs r1, #32 - 8002e6c: 2020 movs r0, #32 - 8002e6e: f7ff fa73 bl 8002358 - ssd1306_WriteString("Pos2", Font_6x8, White); - 8002e72: 4a56 ldr r2, [pc, #344] ; (8002fcc ) - 8002e74: 2301 movs r3, #1 - 8002e76: ca06 ldmia r2, {r1, r2} - 8002e78: 4858 ldr r0, [pc, #352] ; (8002fdc ) - 8002e7a: f7ff fa47 bl 800230c - ssd1306_SetCursor(32, 44); - 8002e7e: 212c movs r1, #44 ; 0x2c - 8002e80: 2020 movs r0, #32 - 8002e82: f7ff fa69 bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 8002e86: 4a51 ldr r2, [pc, #324] ; (8002fcc ) - 8002e88: 2301 movs r3, #1 - 8002e8a: ca06 ldmia r2, {r1, r2} - 8002e8c: 4854 ldr r0, [pc, #336] ; (8002fe0 ) - 8002e8e: f7ff fa3d bl 800230c - free(str); - 8002e92: 6ff8 ldr r0, [r7, #124] ; 0x7c - 8002e94: f00d fe56 bl 8010b44 - } +/* Write full string to screenbuffer */ +char ssd1306_WriteString(char* str, FontDef Font, SSD1306_COLOR color) { + 8002968: b580 push {r7, lr} + 800296a: b084 sub sp, #16 + 800296c: af00 add r7, sp, #0 + 800296e: 60f8 str r0, [r7, #12] + 8002970: 1d38 adds r0, r7, #4 + 8002972: e880 0006 stmia.w r0, {r1, r2} + 8002976: 70fb strb r3, [r7, #3] + while (*str) { + 8002978: e012 b.n 80029a0 + if (ssd1306_WriteChar(*str, Font, color) != *str) { + 800297a: 68fb ldr r3, [r7, #12] + 800297c: 7818 ldrb r0, [r3, #0] + 800297e: 78fb ldrb r3, [r7, #3] + 8002980: 1d3a adds r2, r7, #4 + 8002982: ca06 ldmia r2, {r1, r2} + 8002984: f7ff ff68 bl 8002858 + 8002988: 4603 mov r3, r0 + 800298a: 461a mov r2, r3 + 800298c: 68fb ldr r3, [r7, #12] + 800298e: 781b ldrb r3, [r3, #0] + 8002990: 429a cmp r2, r3 + 8002992: d002 beq.n 800299a + // Char could not be written + return *str; + 8002994: 68fb ldr r3, [r7, #12] + 8002996: 781b ldrb r3, [r3, #0] + 8002998: e008 b.n 80029ac + } + str++; + 800299a: 68fb ldr r3, [r7, #12] + 800299c: 3301 adds r3, #1 + 800299e: 60fb str r3, [r7, #12] + while (*str) { + 80029a0: 68fb ldr r3, [r7, #12] + 80029a2: 781b ldrb r3, [r3, #0] + 80029a4: 2b00 cmp r3, #0 + 80029a6: d1e8 bne.n 800297a + } + + // Everything ok + return *str; + 80029a8: 68fb ldr r3, [r7, #12] + 80029aa: 781b ldrb r3, [r3, #0] +} + 80029ac: 4618 mov r0, r3 + 80029ae: 3710 adds r7, #16 + 80029b0: 46bd mov sp, r7 + 80029b2: bd80 pop {r7, pc} + +080029b4 : + +/* Position the cursor */ +void ssd1306_SetCursor(uint8_t x, uint8_t y) { + 80029b4: b480 push {r7} + 80029b6: b083 sub sp, #12 + 80029b8: af00 add r7, sp, #0 + 80029ba: 4603 mov r3, r0 + 80029bc: 460a mov r2, r1 + 80029be: 71fb strb r3, [r7, #7] + 80029c0: 4613 mov r3, r2 + 80029c2: 71bb strb r3, [r7, #6] + SSD1306.CurrentX = x; + 80029c4: 79fb ldrb r3, [r7, #7] + 80029c6: b29a uxth r2, r3 + 80029c8: 4b05 ldr r3, [pc, #20] ; (80029e0 ) + 80029ca: 801a strh r2, [r3, #0] + SSD1306.CurrentY = y; + 80029cc: 79bb ldrb r3, [r7, #6] + 80029ce: b29a uxth r2, r3 + 80029d0: 4b03 ldr r3, [pc, #12] ; (80029e0 ) + 80029d2: 805a strh r2, [r3, #2] +} + 80029d4: bf00 nop + 80029d6: 370c adds r7, #12 + 80029d8: 46bd mov sp, r7 + 80029da: f85d 7b04 ldr.w r7, [sp], #4 + 80029de: 4770 bx lr + 80029e0: 20000e2c .word 0x20000e2c + +080029e4 : + +/* Draw line by Bresenhem's algorithm */ +void ssd1306_Line(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { + 80029e4: b590 push {r4, r7, lr} + 80029e6: b089 sub sp, #36 ; 0x24 + 80029e8: af00 add r7, sp, #0 + 80029ea: 4604 mov r4, r0 + 80029ec: 4608 mov r0, r1 + 80029ee: 4611 mov r1, r2 + 80029f0: 461a mov r2, r3 + 80029f2: 4623 mov r3, r4 + 80029f4: 71fb strb r3, [r7, #7] + 80029f6: 4603 mov r3, r0 + 80029f8: 71bb strb r3, [r7, #6] + 80029fa: 460b mov r3, r1 + 80029fc: 717b strb r3, [r7, #5] + 80029fe: 4613 mov r3, r2 + 8002a00: 713b strb r3, [r7, #4] + int32_t deltaX = abs(x2 - x1); + 8002a02: 797a ldrb r2, [r7, #5] + 8002a04: 79fb ldrb r3, [r7, #7] + 8002a06: 1ad3 subs r3, r2, r3 + 8002a08: 2b00 cmp r3, #0 + 8002a0a: bfb8 it lt + 8002a0c: 425b neglt r3, r3 + 8002a0e: 61bb str r3, [r7, #24] + int32_t deltaY = abs(y2 - y1); + 8002a10: 793a ldrb r2, [r7, #4] + 8002a12: 79bb ldrb r3, [r7, #6] + 8002a14: 1ad3 subs r3, r2, r3 + 8002a16: 2b00 cmp r3, #0 + 8002a18: bfb8 it lt + 8002a1a: 425b neglt r3, r3 + 8002a1c: 617b str r3, [r7, #20] + int32_t signX = ((x1 < x2) ? 1 : -1); + 8002a1e: 79fa ldrb r2, [r7, #7] + 8002a20: 797b ldrb r3, [r7, #5] + 8002a22: 429a cmp r2, r3 + 8002a24: d201 bcs.n 8002a2a + 8002a26: 2301 movs r3, #1 + 8002a28: e001 b.n 8002a2e + 8002a2a: f04f 33ff mov.w r3, #4294967295 + 8002a2e: 613b str r3, [r7, #16] + int32_t signY = ((y1 < y2) ? 1 : -1); + 8002a30: 79ba ldrb r2, [r7, #6] + 8002a32: 793b ldrb r3, [r7, #4] + 8002a34: 429a cmp r2, r3 + 8002a36: d201 bcs.n 8002a3c + 8002a38: 2301 movs r3, #1 + 8002a3a: e001 b.n 8002a40 + 8002a3c: f04f 33ff mov.w r3, #4294967295 + 8002a40: 60fb str r3, [r7, #12] + int32_t error = deltaX - deltaY; + 8002a42: 69ba ldr r2, [r7, #24] + 8002a44: 697b ldr r3, [r7, #20] + 8002a46: 1ad3 subs r3, r2, r3 + 8002a48: 61fb str r3, [r7, #28] + int32_t error2; + + ssd1306_DrawPixel(x2, y2, color); + 8002a4a: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 + 8002a4e: 7939 ldrb r1, [r7, #4] + 8002a50: 797b ldrb r3, [r7, #5] + 8002a52: 4618 mov r0, r3 + 8002a54: f7ff feac bl 80027b0 + + while((x1 != x2) || (y1 != y2)) { + 8002a58: e024 b.n 8002aa4 + ssd1306_DrawPixel(x1, y1, color); + 8002a5a: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 + 8002a5e: 79b9 ldrb r1, [r7, #6] + 8002a60: 79fb ldrb r3, [r7, #7] + 8002a62: 4618 mov r0, r3 + 8002a64: f7ff fea4 bl 80027b0 + error2 = error * 2; + 8002a68: 69fb ldr r3, [r7, #28] + 8002a6a: 005b lsls r3, r3, #1 + 8002a6c: 60bb str r3, [r7, #8] + if(error2 > -deltaY) { + 8002a6e: 697b ldr r3, [r7, #20] + 8002a70: 425b negs r3, r3 + 8002a72: 68ba ldr r2, [r7, #8] + 8002a74: 429a cmp r2, r3 + 8002a76: dd08 ble.n 8002a8a + error -= deltaY; + 8002a78: 69fa ldr r2, [r7, #28] + 8002a7a: 697b ldr r3, [r7, #20] + 8002a7c: 1ad3 subs r3, r2, r3 + 8002a7e: 61fb str r3, [r7, #28] + x1 += signX; + 8002a80: 693b ldr r3, [r7, #16] + 8002a82: b2da uxtb r2, r3 + 8002a84: 79fb ldrb r3, [r7, #7] + 8002a86: 4413 add r3, r2 + 8002a88: 71fb strb r3, [r7, #7] + } + + if(error2 < deltaX) { + 8002a8a: 68ba ldr r2, [r7, #8] + 8002a8c: 69bb ldr r3, [r7, #24] + 8002a8e: 429a cmp r2, r3 + 8002a90: da08 bge.n 8002aa4 + error += deltaX; + 8002a92: 69fa ldr r2, [r7, #28] + 8002a94: 69bb ldr r3, [r7, #24] + 8002a96: 4413 add r3, r2 + 8002a98: 61fb str r3, [r7, #28] + y1 += signY; + 8002a9a: 68fb ldr r3, [r7, #12] + 8002a9c: b2da uxtb r2, r3 + 8002a9e: 79bb ldrb r3, [r7, #6] + 8002aa0: 4413 add r3, r2 + 8002aa2: 71bb strb r3, [r7, #6] + while((x1 != x2) || (y1 != y2)) { + 8002aa4: 79fa ldrb r2, [r7, #7] + 8002aa6: 797b ldrb r3, [r7, #5] + 8002aa8: 429a cmp r2, r3 + 8002aaa: d1d6 bne.n 8002a5a + 8002aac: 79ba ldrb r2, [r7, #6] + 8002aae: 793b ldrb r3, [r7, #4] + 8002ab0: 429a cmp r2, r3 + 8002ab2: d1d2 bne.n 8002a5a + } + } + return; + 8002ab4: bf00 nop +} + 8002ab6: 3724 adds r7, #36 ; 0x24 + 8002ab8: 46bd mov sp, r7 + 8002aba: bd90 pop {r4, r7, pc} + +08002abc : + ssd1306_Line(x,y,xp2,yp2,color); + return; +} + +/* Draw circle by Bresenhem's algorithm */ +void ssd1306_DrawCircle(uint8_t par_x,uint8_t par_y,uint8_t par_r,SSD1306_COLOR par_color) { + 8002abc: b590 push {r4, r7, lr} + 8002abe: b087 sub sp, #28 + 8002ac0: af00 add r7, sp, #0 + 8002ac2: 4604 mov r4, r0 + 8002ac4: 4608 mov r0, r1 + 8002ac6: 4611 mov r1, r2 + 8002ac8: 461a mov r2, r3 + 8002aca: 4623 mov r3, r4 + 8002acc: 71fb strb r3, [r7, #7] + 8002ace: 4603 mov r3, r0 + 8002ad0: 71bb strb r3, [r7, #6] + 8002ad2: 460b mov r3, r1 + 8002ad4: 717b strb r3, [r7, #5] + 8002ad6: 4613 mov r3, r2 + 8002ad8: 713b strb r3, [r7, #4] + int32_t x = -par_r; + 8002ada: 797b ldrb r3, [r7, #5] + 8002adc: 425b negs r3, r3 + 8002ade: 617b str r3, [r7, #20] + int32_t y = 0; + 8002ae0: 2300 movs r3, #0 + 8002ae2: 613b str r3, [r7, #16] + int32_t err = 2 - 2 * par_r; + 8002ae4: 797b ldrb r3, [r7, #5] + 8002ae6: f1c3 0301 rsb r3, r3, #1 + 8002aea: 005b lsls r3, r3, #1 + 8002aec: 60fb str r3, [r7, #12] + int32_t e2; + + if (par_x >= SSD1306_WIDTH || par_y >= SSD1306_HEIGHT) { + 8002aee: f997 3007 ldrsb.w r3, [r7, #7] + 8002af2: 2b00 cmp r3, #0 + 8002af4: db65 blt.n 8002bc2 + 8002af6: 79bb ldrb r3, [r7, #6] + 8002af8: 2b3f cmp r3, #63 ; 0x3f + 8002afa: d862 bhi.n 8002bc2 + return; + } + + do { + ssd1306_DrawPixel(par_x - x, par_y + y, par_color); + 8002afc: 697b ldr r3, [r7, #20] + 8002afe: b2db uxtb r3, r3 + 8002b00: 79fa ldrb r2, [r7, #7] + 8002b02: 1ad3 subs r3, r2, r3 + 8002b04: b2d8 uxtb r0, r3 + 8002b06: 693b ldr r3, [r7, #16] + 8002b08: b2da uxtb r2, r3 + 8002b0a: 79bb ldrb r3, [r7, #6] + 8002b0c: 4413 add r3, r2 + 8002b0e: b2db uxtb r3, r3 + 8002b10: 793a ldrb r2, [r7, #4] + 8002b12: 4619 mov r1, r3 + 8002b14: f7ff fe4c bl 80027b0 + ssd1306_DrawPixel(par_x + x, par_y + y, par_color); + 8002b18: 697b ldr r3, [r7, #20] + 8002b1a: b2da uxtb r2, r3 + 8002b1c: 79fb ldrb r3, [r7, #7] + 8002b1e: 4413 add r3, r2 + 8002b20: b2d8 uxtb r0, r3 + 8002b22: 693b ldr r3, [r7, #16] + 8002b24: b2da uxtb r2, r3 + 8002b26: 79bb ldrb r3, [r7, #6] + 8002b28: 4413 add r3, r2 + 8002b2a: b2db uxtb r3, r3 + 8002b2c: 793a ldrb r2, [r7, #4] + 8002b2e: 4619 mov r1, r3 + 8002b30: f7ff fe3e bl 80027b0 + ssd1306_DrawPixel(par_x + x, par_y - y, par_color); + 8002b34: 697b ldr r3, [r7, #20] + 8002b36: b2da uxtb r2, r3 + 8002b38: 79fb ldrb r3, [r7, #7] + 8002b3a: 4413 add r3, r2 + 8002b3c: b2d8 uxtb r0, r3 + 8002b3e: 693b ldr r3, [r7, #16] + 8002b40: b2db uxtb r3, r3 + 8002b42: 79ba ldrb r2, [r7, #6] + 8002b44: 1ad3 subs r3, r2, r3 + 8002b46: b2db uxtb r3, r3 + 8002b48: 793a ldrb r2, [r7, #4] + 8002b4a: 4619 mov r1, r3 + 8002b4c: f7ff fe30 bl 80027b0 + ssd1306_DrawPixel(par_x - x, par_y - y, par_color); + 8002b50: 697b ldr r3, [r7, #20] + 8002b52: b2db uxtb r3, r3 + 8002b54: 79fa ldrb r2, [r7, #7] + 8002b56: 1ad3 subs r3, r2, r3 + 8002b58: b2d8 uxtb r0, r3 + 8002b5a: 693b ldr r3, [r7, #16] + 8002b5c: b2db uxtb r3, r3 + 8002b5e: 79ba ldrb r2, [r7, #6] + 8002b60: 1ad3 subs r3, r2, r3 + 8002b62: b2db uxtb r3, r3 + 8002b64: 793a ldrb r2, [r7, #4] + 8002b66: 4619 mov r1, r3 + 8002b68: f7ff fe22 bl 80027b0 + e2 = err; + 8002b6c: 68fb ldr r3, [r7, #12] + 8002b6e: 60bb str r3, [r7, #8] + + if (e2 <= y) { + 8002b70: 68ba ldr r2, [r7, #8] + 8002b72: 693b ldr r3, [r7, #16] + 8002b74: 429a cmp r2, r3 + 8002b76: dc13 bgt.n 8002ba0 + y++; + 8002b78: 693b ldr r3, [r7, #16] + 8002b7a: 3301 adds r3, #1 + 8002b7c: 613b str r3, [r7, #16] + err = err + (y * 2 + 1); + 8002b7e: 693b ldr r3, [r7, #16] + 8002b80: 005b lsls r3, r3, #1 + 8002b82: 3301 adds r3, #1 + 8002b84: 68fa ldr r2, [r7, #12] + 8002b86: 4413 add r3, r2 + 8002b88: 60fb str r3, [r7, #12] + if(-x == y && e2 <= x) { + 8002b8a: 697b ldr r3, [r7, #20] + 8002b8c: 425b negs r3, r3 + 8002b8e: 693a ldr r2, [r7, #16] + 8002b90: 429a cmp r2, r3 + 8002b92: d105 bne.n 8002ba0 + 8002b94: 68ba ldr r2, [r7, #8] + 8002b96: 697b ldr r3, [r7, #20] + 8002b98: 429a cmp r2, r3 + 8002b9a: dc01 bgt.n 8002ba0 + e2 = 0; + 8002b9c: 2300 movs r3, #0 + 8002b9e: 60bb str r3, [r7, #8] + } + } + + if (e2 > x) { + 8002ba0: 68ba ldr r2, [r7, #8] + 8002ba2: 697b ldr r3, [r7, #20] + 8002ba4: 429a cmp r2, r3 + 8002ba6: dd08 ble.n 8002bba + x++; + 8002ba8: 697b ldr r3, [r7, #20] + 8002baa: 3301 adds r3, #1 + 8002bac: 617b str r3, [r7, #20] + err = err + (x * 2 + 1); + 8002bae: 697b ldr r3, [r7, #20] + 8002bb0: 005b lsls r3, r3, #1 + 8002bb2: 3301 adds r3, #1 + 8002bb4: 68fa ldr r2, [r7, #12] + 8002bb6: 4413 add r3, r2 + 8002bb8: 60fb str r3, [r7, #12] + } + } while (x <= 0); + 8002bba: 697b ldr r3, [r7, #20] + 8002bbc: 2b00 cmp r3, #0 + 8002bbe: dd9d ble.n 8002afc + + return; + 8002bc0: e000 b.n 8002bc4 + return; + 8002bc2: bf00 nop +} + 8002bc4: 371c adds r7, #28 + 8002bc6: 46bd mov sp, r7 + 8002bc8: bd90 pop {r4, r7, pc} + +08002bca : + + return; +} + +/* Draw a rectangle */ +void ssd1306_DrawRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { + 8002bca: b590 push {r4, r7, lr} + 8002bcc: b085 sub sp, #20 + 8002bce: af02 add r7, sp, #8 + 8002bd0: 4604 mov r4, r0 + 8002bd2: 4608 mov r0, r1 + 8002bd4: 4611 mov r1, r2 + 8002bd6: 461a mov r2, r3 + 8002bd8: 4623 mov r3, r4 + 8002bda: 71fb strb r3, [r7, #7] + 8002bdc: 4603 mov r3, r0 + 8002bde: 71bb strb r3, [r7, #6] + 8002be0: 460b mov r3, r1 + 8002be2: 717b strb r3, [r7, #5] + 8002be4: 4613 mov r3, r2 + 8002be6: 713b strb r3, [r7, #4] + ssd1306_Line(x1,y1,x2,y1,color); + 8002be8: 79bc ldrb r4, [r7, #6] + 8002bea: 797a ldrb r2, [r7, #5] + 8002bec: 79b9 ldrb r1, [r7, #6] + 8002bee: 79f8 ldrb r0, [r7, #7] + 8002bf0: 7e3b ldrb r3, [r7, #24] + 8002bf2: 9300 str r3, [sp, #0] + 8002bf4: 4623 mov r3, r4 + 8002bf6: f7ff fef5 bl 80029e4 + ssd1306_Line(x2,y1,x2,y2,color); + 8002bfa: 793c ldrb r4, [r7, #4] + 8002bfc: 797a ldrb r2, [r7, #5] + 8002bfe: 79b9 ldrb r1, [r7, #6] + 8002c00: 7978 ldrb r0, [r7, #5] + 8002c02: 7e3b ldrb r3, [r7, #24] + 8002c04: 9300 str r3, [sp, #0] + 8002c06: 4623 mov r3, r4 + 8002c08: f7ff feec bl 80029e4 + ssd1306_Line(x2,y2,x1,y2,color); + 8002c0c: 793c ldrb r4, [r7, #4] + 8002c0e: 79fa ldrb r2, [r7, #7] + 8002c10: 7939 ldrb r1, [r7, #4] + 8002c12: 7978 ldrb r0, [r7, #5] + 8002c14: 7e3b ldrb r3, [r7, #24] + 8002c16: 9300 str r3, [sp, #0] + 8002c18: 4623 mov r3, r4 + 8002c1a: f7ff fee3 bl 80029e4 + ssd1306_Line(x1,y2,x1,y1,color); + 8002c1e: 79bc ldrb r4, [r7, #6] + 8002c20: 79fa ldrb r2, [r7, #7] + 8002c22: 7939 ldrb r1, [r7, #4] + 8002c24: 79f8 ldrb r0, [r7, #7] + 8002c26: 7e3b ldrb r3, [r7, #24] + 8002c28: 9300 str r3, [sp, #0] + 8002c2a: 4623 mov r3, r4 + 8002c2c: f7ff feda bl 80029e4 + + return; + 8002c30: bf00 nop +} + 8002c32: 370c adds r7, #12 + 8002c34: 46bd mov sp, r7 + 8002c36: bd90 pop {r4, r7, pc} + +08002c38 : + +/* Draw a filled rectangle */ +void ssd1306_FillRectangle(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, SSD1306_COLOR color) { + 8002c38: b590 push {r4, r7, lr} + 8002c3a: b085 sub sp, #20 + 8002c3c: af00 add r7, sp, #0 + 8002c3e: 4604 mov r4, r0 + 8002c40: 4608 mov r0, r1 + 8002c42: 4611 mov r1, r2 + 8002c44: 461a mov r2, r3 + 8002c46: 4623 mov r3, r4 + 8002c48: 71fb strb r3, [r7, #7] + 8002c4a: 4603 mov r3, r0 + 8002c4c: 71bb strb r3, [r7, #6] + 8002c4e: 460b mov r3, r1 + 8002c50: 717b strb r3, [r7, #5] + 8002c52: 4613 mov r3, r2 + 8002c54: 713b strb r3, [r7, #4] + uint8_t x_start = ((x1<=x2) ? x1 : x2); + 8002c56: 79fa ldrb r2, [r7, #7] + 8002c58: 797b ldrb r3, [r7, #5] + 8002c5a: 4293 cmp r3, r2 + 8002c5c: bf28 it cs + 8002c5e: 4613 movcs r3, r2 + 8002c60: 737b strb r3, [r7, #13] + uint8_t x_end = ((x1<=x2) ? x2 : x1); + 8002c62: 797a ldrb r2, [r7, #5] + 8002c64: 79fb ldrb r3, [r7, #7] + 8002c66: 4293 cmp r3, r2 + 8002c68: bf38 it cc + 8002c6a: 4613 movcc r3, r2 + 8002c6c: 733b strb r3, [r7, #12] + uint8_t y_start = ((y1<=y2) ? y1 : y2); + 8002c6e: 79ba ldrb r2, [r7, #6] + 8002c70: 793b ldrb r3, [r7, #4] + 8002c72: 4293 cmp r3, r2 + 8002c74: bf28 it cs + 8002c76: 4613 movcs r3, r2 + 8002c78: 72fb strb r3, [r7, #11] + uint8_t y_end = ((y1<=y2) ? y2 : y1); + 8002c7a: 793a ldrb r2, [r7, #4] + 8002c7c: 79bb ldrb r3, [r7, #6] + 8002c7e: 4293 cmp r3, r2 + 8002c80: bf38 it cc + 8002c82: 4613 movcc r3, r2 + 8002c84: 72bb strb r3, [r7, #10] + + for (uint8_t y= y_start; (y<= y_end)&&(y + for (uint8_t x= x_start; (x<= x_end)&&(x + ssd1306_DrawPixel(x, y, color); + 8002c92: f897 2020 ldrb.w r2, [r7, #32] + 8002c96: 7bf9 ldrb r1, [r7, #15] + 8002c98: 7bbb ldrb r3, [r7, #14] + 8002c9a: 4618 mov r0, r3 + 8002c9c: f7ff fd88 bl 80027b0 + for (uint8_t x= x_start; (x<= x_end)&&(x + 8002cae: f997 300e ldrsb.w r3, [r7, #14] + 8002cb2: 2b00 cmp r3, #0 + 8002cb4: daed bge.n 8002c92 + for (uint8_t y= y_start; (y<= y_end)&&(y + 8002cc4: 7bfb ldrb r3, [r7, #15] + 8002cc6: 2b3f cmp r3, #63 ; 0x3f + 8002cc8: d9e0 bls.n 8002c8c + } + } + return; + 8002cca: bf00 nop + 8002ccc: bf00 nop +} + 8002cce: 3714 adds r7, #20 + 8002cd0: 46bd mov sp, r7 + 8002cd2: bd90 pop {r4, r7, pc} + +08002cd4 : + +/* Draw a bitmap */ +void ssd1306_DrawBitmap(uint8_t x, uint8_t y, const unsigned char* bitmap, uint8_t w, uint8_t h, SSD1306_COLOR color) { + 8002cd4: b580 push {r7, lr} + 8002cd6: b084 sub sp, #16 + 8002cd8: af00 add r7, sp, #0 + 8002cda: 603a str r2, [r7, #0] + 8002cdc: 461a mov r2, r3 + 8002cde: 4603 mov r3, r0 + 8002ce0: 71fb strb r3, [r7, #7] + 8002ce2: 460b mov r3, r1 + 8002ce4: 71bb strb r3, [r7, #6] + 8002ce6: 4613 mov r3, r2 + 8002ce8: 717b strb r3, [r7, #5] + int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte + 8002cea: 797b ldrb r3, [r7, #5] + 8002cec: 3307 adds r3, #7 + 8002cee: 2b00 cmp r3, #0 + 8002cf0: da00 bge.n 8002cf4 + 8002cf2: 3307 adds r3, #7 + 8002cf4: 10db asrs r3, r3, #3 + 8002cf6: 817b strh r3, [r7, #10] + uint8_t byte = 0; + 8002cf8: 2300 movs r3, #0 + 8002cfa: 73fb strb r3, [r7, #15] + + if (x >= SSD1306_WIDTH || y >= SSD1306_HEIGHT) { + 8002cfc: f997 3007 ldrsb.w r3, [r7, #7] + 8002d00: 2b00 cmp r3, #0 + 8002d02: db3e blt.n 8002d82 + 8002d04: 79bb ldrb r3, [r7, #6] + 8002d06: 2b3f cmp r3, #63 ; 0x3f + 8002d08: d83b bhi.n 8002d82 + return; + } + + for (uint8_t j = 0; j < h; j++, y++) { + 8002d0a: 2300 movs r3, #0 + 8002d0c: 73bb strb r3, [r7, #14] + 8002d0e: e033 b.n 8002d78 + for (uint8_t i = 0; i < w; i++) { + 8002d10: 2300 movs r3, #0 + 8002d12: 737b strb r3, [r7, #13] + 8002d14: e026 b.n 8002d64 + if (i & 7) { + 8002d16: 7b7b ldrb r3, [r7, #13] + 8002d18: f003 0307 and.w r3, r3, #7 + 8002d1c: 2b00 cmp r3, #0 + 8002d1e: d003 beq.n 8002d28 + byte <<= 1; + 8002d20: 7bfb ldrb r3, [r7, #15] + 8002d22: 005b lsls r3, r3, #1 + 8002d24: 73fb strb r3, [r7, #15] + 8002d26: e00d b.n 8002d44 + } else { + byte = (*(const unsigned char *)(&bitmap[j * byteWidth + i / 8])); + 8002d28: 7bbb ldrb r3, [r7, #14] + 8002d2a: f9b7 200a ldrsh.w r2, [r7, #10] + 8002d2e: fb02 f303 mul.w r3, r2, r3 + 8002d32: 7b7a ldrb r2, [r7, #13] + 8002d34: 08d2 lsrs r2, r2, #3 + 8002d36: b2d2 uxtb r2, r2 + 8002d38: 4413 add r3, r2 + 8002d3a: 461a mov r2, r3 + 8002d3c: 683b ldr r3, [r7, #0] + 8002d3e: 4413 add r3, r2 + 8002d40: 781b ldrb r3, [r3, #0] + 8002d42: 73fb strb r3, [r7, #15] + } + + if (byte & 0x80) { + 8002d44: f997 300f ldrsb.w r3, [r7, #15] + 8002d48: 2b00 cmp r3, #0 + 8002d4a: da08 bge.n 8002d5e + ssd1306_DrawPixel(x + i, y, color); + 8002d4c: 79fa ldrb r2, [r7, #7] + 8002d4e: 7b7b ldrb r3, [r7, #13] + 8002d50: 4413 add r3, r2 + 8002d52: b2db uxtb r3, r3 + 8002d54: 7f3a ldrb r2, [r7, #28] + 8002d56: 79b9 ldrb r1, [r7, #6] + 8002d58: 4618 mov r0, r3 + 8002d5a: f7ff fd29 bl 80027b0 + for (uint8_t i = 0; i < w; i++) { + 8002d5e: 7b7b ldrb r3, [r7, #13] + 8002d60: 3301 adds r3, #1 + 8002d62: 737b strb r3, [r7, #13] + 8002d64: 7b7a ldrb r2, [r7, #13] + 8002d66: 797b ldrb r3, [r7, #5] + 8002d68: 429a cmp r2, r3 + 8002d6a: d3d4 bcc.n 8002d16 + for (uint8_t j = 0; j < h; j++, y++) { + 8002d6c: 7bbb ldrb r3, [r7, #14] + 8002d6e: 3301 adds r3, #1 + 8002d70: 73bb strb r3, [r7, #14] + 8002d72: 79bb ldrb r3, [r7, #6] + 8002d74: 3301 adds r3, #1 + 8002d76: 71bb strb r3, [r7, #6] + 8002d78: 7bba ldrb r2, [r7, #14] + 8002d7a: 7e3b ldrb r3, [r7, #24] + 8002d7c: 429a cmp r2, r3 + 8002d7e: d3c7 bcc.n 8002d10 + } + } + } + return; + 8002d80: e000 b.n 8002d84 + return; + 8002d82: bf00 nop +} + 8002d84: 3710 adds r7, #16 + 8002d86: 46bd mov sp, r7 + 8002d88: bd80 pop {r7, pc} + +08002d8a : + +void ssd1306_SetContrast(const uint8_t value) { + 8002d8a: b580 push {r7, lr} + 8002d8c: b084 sub sp, #16 + 8002d8e: af00 add r7, sp, #0 + 8002d90: 4603 mov r3, r0 + 8002d92: 71fb strb r3, [r7, #7] + const uint8_t kSetContrastControlRegister = 0x81; + 8002d94: 2381 movs r3, #129 ; 0x81 + 8002d96: 73fb strb r3, [r7, #15] + ssd1306_WriteCommand(kSetContrastControlRegister); + 8002d98: 7bfb ldrb r3, [r7, #15] + 8002d9a: 4618 mov r0, r3 + 8002d9c: f7ff fc2c bl 80025f8 + ssd1306_WriteCommand(value); + 8002da0: 79fb ldrb r3, [r7, #7] + 8002da2: 4618 mov r0, r3 + 8002da4: f7ff fc28 bl 80025f8 +} + 8002da8: bf00 nop + 8002daa: 3710 adds r7, #16 + 8002dac: 46bd mov sp, r7 + 8002dae: bd80 pop {r7, pc} + +08002db0 : + +void ssd1306_SetDisplayOn(const uint8_t on) { + 8002db0: b580 push {r7, lr} + 8002db2: b084 sub sp, #16 + 8002db4: af00 add r7, sp, #0 + 8002db6: 4603 mov r3, r0 + 8002db8: 71fb strb r3, [r7, #7] + uint8_t value; + if (on) { + 8002dba: 79fb ldrb r3, [r7, #7] + 8002dbc: 2b00 cmp r3, #0 + 8002dbe: d005 beq.n 8002dcc + value = 0xAF; // Display on + 8002dc0: 23af movs r3, #175 ; 0xaf + 8002dc2: 73fb strb r3, [r7, #15] + SSD1306.DisplayOn = 1; + 8002dc4: 4b08 ldr r3, [pc, #32] ; (8002de8 ) + 8002dc6: 2201 movs r2, #1 + 8002dc8: 715a strb r2, [r3, #5] + 8002dca: e004 b.n 8002dd6 + } else { + value = 0xAE; // Display off + 8002dcc: 23ae movs r3, #174 ; 0xae + 8002dce: 73fb strb r3, [r7, #15] + SSD1306.DisplayOn = 0; + 8002dd0: 4b05 ldr r3, [pc, #20] ; (8002de8 ) + 8002dd2: 2200 movs r2, #0 + 8002dd4: 715a strb r2, [r3, #5] + } + ssd1306_WriteCommand(value); + 8002dd6: 7bfb ldrb r3, [r7, #15] + 8002dd8: 4618 mov r0, r3 + 8002dda: f7ff fc0d bl 80025f8 +} + 8002dde: bf00 nop + 8002de0: 3710 adds r7, #16 + 8002de2: 46bd mov sp, r7 + 8002de4: bd80 pop {r7, pc} + 8002de6: bf00 nop + 8002de8: 20000e2c .word 0x20000e2c + 8002dec: 00000000 .word 0x00000000 + +08002df0 : + + + +} + +void batterygauge(float vbat,int x, int y,int currentsquare){ + 8002df0: b590 push {r4, r7, lr} + 8002df2: b087 sub sp, #28 + 8002df4: af02 add r7, sp, #8 + 8002df6: ed87 0a03 vstr s0, [r7, #12] + 8002dfa: 60b8 str r0, [r7, #8] + 8002dfc: 6079 str r1, [r7, #4] + 8002dfe: 603a str r2, [r7, #0] + ssd1306_Line(x+15,y+1,x+15,y+5, White); + 8002e00: 68bb ldr r3, [r7, #8] + 8002e02: b2db uxtb r3, r3 + 8002e04: 330f adds r3, #15 + 8002e06: b2d8 uxtb r0, r3 + 8002e08: 687b ldr r3, [r7, #4] + 8002e0a: b2db uxtb r3, r3 + 8002e0c: 3301 adds r3, #1 + 8002e0e: b2d9 uxtb r1, r3 + 8002e10: 68bb ldr r3, [r7, #8] + 8002e12: b2db uxtb r3, r3 + 8002e14: 330f adds r3, #15 + 8002e16: b2da uxtb r2, r3 + 8002e18: 687b ldr r3, [r7, #4] + 8002e1a: b2db uxtb r3, r3 + 8002e1c: 3305 adds r3, #5 + 8002e1e: b2db uxtb r3, r3 + 8002e20: 2401 movs r4, #1 + 8002e22: 9400 str r4, [sp, #0] + 8002e24: f7ff fdde bl 80029e4 + ssd1306_Line(x+16,y+1,x+16,y+5, White); + 8002e28: 68bb ldr r3, [r7, #8] + 8002e2a: b2db uxtb r3, r3 + 8002e2c: 3310 adds r3, #16 + 8002e2e: b2d8 uxtb r0, r3 + 8002e30: 687b ldr r3, [r7, #4] + 8002e32: b2db uxtb r3, r3 + 8002e34: 3301 adds r3, #1 + 8002e36: b2d9 uxtb r1, r3 + 8002e38: 68bb ldr r3, [r7, #8] + 8002e3a: b2db uxtb r3, r3 + 8002e3c: 3310 adds r3, #16 + 8002e3e: b2da uxtb r2, r3 + 8002e40: 687b ldr r3, [r7, #4] + 8002e42: b2db uxtb r3, r3 + 8002e44: 3305 adds r3, #5 + 8002e46: b2db uxtb r3, r3 + 8002e48: 2401 movs r4, #1 + 8002e4a: 9400 str r4, [sp, #0] + 8002e4c: f7ff fdca bl 80029e4 + ssd1306_DrawRectangle(x, y, x+14, y+6, White); + 8002e50: 68bb ldr r3, [r7, #8] + 8002e52: b2d8 uxtb r0, r3 + 8002e54: 687b ldr r3, [r7, #4] + 8002e56: b2d9 uxtb r1, r3 + 8002e58: 68bb ldr r3, [r7, #8] + 8002e5a: b2db uxtb r3, r3 + 8002e5c: 330e adds r3, #14 + 8002e5e: b2da uxtb r2, r3 + 8002e60: 687b ldr r3, [r7, #4] + 8002e62: b2db uxtb r3, r3 + 8002e64: 3306 adds r3, #6 + 8002e66: b2db uxtb r3, r3 + 8002e68: 2401 movs r4, #1 + 8002e6a: 9400 str r4, [sp, #0] + 8002e6c: f7ff fead bl 8002bca + if(vbat<=3.7){ + 8002e70: 68f8 ldr r0, [r7, #12] + 8002e72: f7fd fb69 bl 8000548 <__aeabi_f2d> + 8002e76: a396 add r3, pc, #600 ; (adr r3, 80030d0 ) + 8002e78: e9d3 2300 ldrd r2, r3, [r3] + 8002e7c: f7fd fe38 bl 8000af0 <__aeabi_dcmple> + 8002e80: 4603 mov r3, r0 + 8002e82: 2b00 cmp r3, #0 + 8002e84: d02a beq.n 8002edc + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + 8002e86: 68bb ldr r3, [r7, #8] + 8002e88: b2db uxtb r3, r3 + 8002e8a: 3302 adds r3, #2 + 8002e8c: b2d8 uxtb r0, r3 + 8002e8e: 687b ldr r3, [r7, #4] + 8002e90: b2db uxtb r3, r3 + 8002e92: 3302 adds r3, #2 + 8002e94: b2d9 uxtb r1, r3 + 8002e96: 68bb ldr r3, [r7, #8] + 8002e98: b2db uxtb r3, r3 + 8002e9a: 3303 adds r3, #3 + 8002e9c: b2da uxtb r2, r3 + 8002e9e: 687b ldr r3, [r7, #4] + 8002ea0: b2db uxtb r3, r3 + 8002ea2: 3304 adds r3, #4 + 8002ea4: b2db uxtb r3, r3 + 8002ea6: 2401 movs r4, #1 + 8002ea8: 9400 str r4, [sp, #0] + 8002eaa: f7ff fe8e bl 8002bca + if(currentsquare==1){ + 8002eae: 683b ldr r3, [r7, #0] + 8002eb0: 2b01 cmp r3, #1 + 8002eb2: d113 bne.n 8002edc + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + 8002eb4: 68bb ldr r3, [r7, #8] + 8002eb6: b2db uxtb r3, r3 + 8002eb8: 3302 adds r3, #2 + 8002eba: b2d8 uxtb r0, r3 + 8002ebc: 687b ldr r3, [r7, #4] + 8002ebe: b2db uxtb r3, r3 + 8002ec0: 3302 adds r3, #2 + 8002ec2: b2d9 uxtb r1, r3 + 8002ec4: 68bb ldr r3, [r7, #8] + 8002ec6: b2db uxtb r3, r3 + 8002ec8: 3303 adds r3, #3 + 8002eca: b2da uxtb r2, r3 + 8002ecc: 687b ldr r3, [r7, #4] + 8002ece: b2db uxtb r3, r3 + 8002ed0: 3304 adds r3, #4 + 8002ed2: b2db uxtb r3, r3 + 8002ed4: 2401 movs r4, #1 + 8002ed6: 9400 str r4, [sp, #0] + 8002ed8: f7ff fe77 bl 8002bca + } + else{ + + } + } + if(vbat>3.7 && vbat<= 3.9){ + 8002edc: 68f8 ldr r0, [r7, #12] + 8002ede: f7fd fb33 bl 8000548 <__aeabi_f2d> + 8002ee2: a37b add r3, pc, #492 ; (adr r3, 80030d0 ) + 8002ee4: e9d3 2300 ldrd r2, r3, [r3] + 8002ee8: f7fd fe16 bl 8000b18 <__aeabi_dcmpgt> + 8002eec: 4603 mov r3, r0 + 8002eee: 2b00 cmp r3, #0 + 8002ef0: d035 beq.n 8002f5e + 8002ef2: 68f8 ldr r0, [r7, #12] + 8002ef4: f7fd fb28 bl 8000548 <__aeabi_f2d> + 8002ef8: a377 add r3, pc, #476 ; (adr r3, 80030d8 ) + 8002efa: e9d3 2300 ldrd r2, r3, [r3] + 8002efe: f7fd fdf7 bl 8000af0 <__aeabi_dcmple> + 8002f02: 4603 mov r3, r0 + 8002f04: 2b00 cmp r3, #0 + 8002f06: d02a beq.n 8002f5e + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + 8002f08: 68bb ldr r3, [r7, #8] + 8002f0a: b2db uxtb r3, r3 + 8002f0c: 3302 adds r3, #2 + 8002f0e: b2d8 uxtb r0, r3 + 8002f10: 687b ldr r3, [r7, #4] + 8002f12: b2db uxtb r3, r3 + 8002f14: 3302 adds r3, #2 + 8002f16: b2d9 uxtb r1, r3 + 8002f18: 68bb ldr r3, [r7, #8] + 8002f1a: b2db uxtb r3, r3 + 8002f1c: 3303 adds r3, #3 + 8002f1e: b2da uxtb r2, r3 + 8002f20: 687b ldr r3, [r7, #4] + 8002f22: b2db uxtb r3, r3 + 8002f24: 3304 adds r3, #4 + 8002f26: b2db uxtb r3, r3 + 8002f28: 2401 movs r4, #1 + 8002f2a: 9400 str r4, [sp, #0] + 8002f2c: f7ff fe4d bl 8002bca + if(currentsquare==1){ + 8002f30: 683b ldr r3, [r7, #0] + 8002f32: 2b01 cmp r3, #1 + 8002f34: d113 bne.n 8002f5e + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + 8002f36: 68bb ldr r3, [r7, #8] + 8002f38: b2db uxtb r3, r3 + 8002f3a: 3305 adds r3, #5 + 8002f3c: b2d8 uxtb r0, r3 + 8002f3e: 687b ldr r3, [r7, #4] + 8002f40: b2db uxtb r3, r3 + 8002f42: 3302 adds r3, #2 + 8002f44: b2d9 uxtb r1, r3 + 8002f46: 68bb ldr r3, [r7, #8] + 8002f48: b2db uxtb r3, r3 + 8002f4a: 3306 adds r3, #6 + 8002f4c: b2da uxtb r2, r3 + 8002f4e: 687b ldr r3, [r7, #4] + 8002f50: b2db uxtb r3, r3 + 8002f52: 3304 adds r3, #4 + 8002f54: b2db uxtb r3, r3 + 8002f56: 2401 movs r4, #1 + 8002f58: 9400 str r4, [sp, #0] + 8002f5a: f7ff fe36 bl 8002bca + else{ + + } + + } + if(vbat>3.9 && vbat<=4.1){ + 8002f5e: 68f8 ldr r0, [r7, #12] + 8002f60: f7fd faf2 bl 8000548 <__aeabi_f2d> + 8002f64: a35c add r3, pc, #368 ; (adr r3, 80030d8 ) + 8002f66: e9d3 2300 ldrd r2, r3, [r3] + 8002f6a: f7fd fdd5 bl 8000b18 <__aeabi_dcmpgt> + 8002f6e: 4603 mov r3, r0 + 8002f70: 2b00 cmp r3, #0 + 8002f72: d049 beq.n 8003008 + 8002f74: 68f8 ldr r0, [r7, #12] + 8002f76: f7fd fae7 bl 8000548 <__aeabi_f2d> + 8002f7a: a359 add r3, pc, #356 ; (adr r3, 80030e0 ) + 8002f7c: e9d3 2300 ldrd r2, r3, [r3] + 8002f80: f7fd fdb6 bl 8000af0 <__aeabi_dcmple> + 8002f84: 4603 mov r3, r0 + 8002f86: 2b00 cmp r3, #0 + 8002f88: d03e beq.n 8003008 + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + 8002f8a: 68bb ldr r3, [r7, #8] + 8002f8c: b2db uxtb r3, r3 + 8002f8e: 3302 adds r3, #2 + 8002f90: b2d8 uxtb r0, r3 + 8002f92: 687b ldr r3, [r7, #4] + 8002f94: b2db uxtb r3, r3 + 8002f96: 3302 adds r3, #2 + 8002f98: b2d9 uxtb r1, r3 + 8002f9a: 68bb ldr r3, [r7, #8] + 8002f9c: b2db uxtb r3, r3 + 8002f9e: 3303 adds r3, #3 + 8002fa0: b2da uxtb r2, r3 + 8002fa2: 687b ldr r3, [r7, #4] + 8002fa4: b2db uxtb r3, r3 + 8002fa6: 3304 adds r3, #4 + 8002fa8: b2db uxtb r3, r3 + 8002faa: 2401 movs r4, #1 + 8002fac: 9400 str r4, [sp, #0] + 8002fae: f7ff fe0c bl 8002bca + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + 8002fb2: 68bb ldr r3, [r7, #8] + 8002fb4: b2db uxtb r3, r3 + 8002fb6: 3305 adds r3, #5 + 8002fb8: b2d8 uxtb r0, r3 + 8002fba: 687b ldr r3, [r7, #4] + 8002fbc: b2db uxtb r3, r3 + 8002fbe: 3302 adds r3, #2 + 8002fc0: b2d9 uxtb r1, r3 + 8002fc2: 68bb ldr r3, [r7, #8] + 8002fc4: b2db uxtb r3, r3 + 8002fc6: 3306 adds r3, #6 + 8002fc8: b2da uxtb r2, r3 + 8002fca: 687b ldr r3, [r7, #4] + 8002fcc: b2db uxtb r3, r3 + 8002fce: 3304 adds r3, #4 + 8002fd0: b2db uxtb r3, r3 + 8002fd2: 2401 movs r4, #1 + 8002fd4: 9400 str r4, [sp, #0] + 8002fd6: f7ff fdf8 bl 8002bca + + if(currentsquare==1){ + 8002fda: 683b ldr r3, [r7, #0] + 8002fdc: 2b01 cmp r3, #1 + 8002fde: d113 bne.n 8003008 + ssd1306_DrawRectangle(x+8, y+2, x+9, y+4, White); + 8002fe0: 68bb ldr r3, [r7, #8] + 8002fe2: b2db uxtb r3, r3 + 8002fe4: 3308 adds r3, #8 + 8002fe6: b2d8 uxtb r0, r3 + 8002fe8: 687b ldr r3, [r7, #4] + 8002fea: b2db uxtb r3, r3 + 8002fec: 3302 adds r3, #2 + 8002fee: b2d9 uxtb r1, r3 + 8002ff0: 68bb ldr r3, [r7, #8] + 8002ff2: b2db uxtb r3, r3 + 8002ff4: 3309 adds r3, #9 + 8002ff6: b2da uxtb r2, r3 + 8002ff8: 687b ldr r3, [r7, #4] + 8002ffa: b2db uxtb r3, r3 + 8002ffc: 3304 adds r3, #4 + 8002ffe: b2db uxtb r3, r3 + 8003000: 2401 movs r4, #1 + 8003002: 9400 str r4, [sp, #0] + 8003004: f7ff fde1 bl 8002bca + else{ + + } + } + + if(vbat>4.1){ + 8003008: 68f8 ldr r0, [r7, #12] + 800300a: f7fd fa9d bl 8000548 <__aeabi_f2d> + 800300e: a334 add r3, pc, #208 ; (adr r3, 80030e0 ) + 8003010: e9d3 2300 ldrd r2, r3, [r3] + 8003014: f7fd fd80 bl 8000b18 <__aeabi_dcmpgt> + 8003018: 4603 mov r3, r0 + 800301a: 2b00 cmp r3, #0 + 800301c: d100 bne.n 8003020 + } + + + + +} + 800301e: e052 b.n 80030c6 + ssd1306_DrawRectangle(x+2, y+2, x+3, y+4, White); + 8003020: 68bb ldr r3, [r7, #8] + 8003022: b2db uxtb r3, r3 + 8003024: 3302 adds r3, #2 + 8003026: b2d8 uxtb r0, r3 + 8003028: 687b ldr r3, [r7, #4] + 800302a: b2db uxtb r3, r3 + 800302c: 3302 adds r3, #2 + 800302e: b2d9 uxtb r1, r3 + 8003030: 68bb ldr r3, [r7, #8] + 8003032: b2db uxtb r3, r3 + 8003034: 3303 adds r3, #3 + 8003036: b2da uxtb r2, r3 + 8003038: 687b ldr r3, [r7, #4] + 800303a: b2db uxtb r3, r3 + 800303c: 3304 adds r3, #4 + 800303e: b2db uxtb r3, r3 + 8003040: 2401 movs r4, #1 + 8003042: 9400 str r4, [sp, #0] + 8003044: f7ff fdc1 bl 8002bca + ssd1306_DrawRectangle(x+5, y+2, x+6, y+4, White); + 8003048: 68bb ldr r3, [r7, #8] + 800304a: b2db uxtb r3, r3 + 800304c: 3305 adds r3, #5 + 800304e: b2d8 uxtb r0, r3 + 8003050: 687b ldr r3, [r7, #4] + 8003052: b2db uxtb r3, r3 + 8003054: 3302 adds r3, #2 + 8003056: b2d9 uxtb r1, r3 + 8003058: 68bb ldr r3, [r7, #8] + 800305a: b2db uxtb r3, r3 + 800305c: 3306 adds r3, #6 + 800305e: b2da uxtb r2, r3 + 8003060: 687b ldr r3, [r7, #4] + 8003062: b2db uxtb r3, r3 + 8003064: 3304 adds r3, #4 + 8003066: b2db uxtb r3, r3 + 8003068: 2401 movs r4, #1 + 800306a: 9400 str r4, [sp, #0] + 800306c: f7ff fdad bl 8002bca + ssd1306_DrawRectangle(x+8, y+2, x+9, y+4, White); + 8003070: 68bb ldr r3, [r7, #8] + 8003072: b2db uxtb r3, r3 + 8003074: 3308 adds r3, #8 + 8003076: b2d8 uxtb r0, r3 + 8003078: 687b ldr r3, [r7, #4] + 800307a: b2db uxtb r3, r3 + 800307c: 3302 adds r3, #2 + 800307e: b2d9 uxtb r1, r3 + 8003080: 68bb ldr r3, [r7, #8] + 8003082: b2db uxtb r3, r3 + 8003084: 3309 adds r3, #9 + 8003086: b2da uxtb r2, r3 + 8003088: 687b ldr r3, [r7, #4] + 800308a: b2db uxtb r3, r3 + 800308c: 3304 adds r3, #4 + 800308e: b2db uxtb r3, r3 + 8003090: 2401 movs r4, #1 + 8003092: 9400 str r4, [sp, #0] + 8003094: f7ff fd99 bl 8002bca + if(currentsquare==1){ + 8003098: 683b ldr r3, [r7, #0] + 800309a: 2b01 cmp r3, #1 + 800309c: d113 bne.n 80030c6 + ssd1306_DrawRectangle(x+11, y+2, x+12, y+4, White); + 800309e: 68bb ldr r3, [r7, #8] + 80030a0: b2db uxtb r3, r3 + 80030a2: 330b adds r3, #11 + 80030a4: b2d8 uxtb r0, r3 + 80030a6: 687b ldr r3, [r7, #4] + 80030a8: b2db uxtb r3, r3 + 80030aa: 3302 adds r3, #2 + 80030ac: b2d9 uxtb r1, r3 + 80030ae: 68bb ldr r3, [r7, #8] + 80030b0: b2db uxtb r3, r3 + 80030b2: 330c adds r3, #12 + 80030b4: b2da uxtb r2, r3 + 80030b6: 687b ldr r3, [r7, #4] + 80030b8: b2db uxtb r3, r3 + 80030ba: 3304 adds r3, #4 + 80030bc: b2db uxtb r3, r3 + 80030be: 2401 movs r4, #1 + 80030c0: 9400 str r4, [sp, #0] + 80030c2: f7ff fd82 bl 8002bca +} + 80030c6: bf00 nop + 80030c8: 3714 adds r7, #20 + 80030ca: 46bd mov sp, r7 + 80030cc: bd90 pop {r4, r7, pc} + 80030ce: bf00 nop + 80030d0: 9999999a .word 0x9999999a + 80030d4: 400d9999 .word 0x400d9999 + 80030d8: 33333333 .word 0x33333333 + 80030dc: 400f3333 .word 0x400f3333 + 80030e0: 66666666 .word 0x66666666 + 80030e4: 40106666 .word 0x40106666 + +080030e8 : +extern uint8_t numbuf2[10]; +int erasetime=0; +int erasedisplay=0; +int usbtransmiten=0; + +void statemachine(void){ + 80030e8: b5f0 push {r4, r5, r6, r7, lr} + 80030ea: ed2d 8b02 vpush {d8} + 80030ee: b09f sub sp, #124 ; 0x7c + 80030f0: af04 add r7, sp, #16 + switch(state){ + 80030f2: 4b97 ldr r3, [pc, #604] ; (8003350 ) + 80030f4: 781b ldrb r3, [r3, #0] + 80030f6: 2b06 cmp r3, #6 + 80030f8: f201 8482 bhi.w 8004a00 + 80030fc: a201 add r2, pc, #4 ; (adr r2, 8003104 ) + 80030fe: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003102: bf00 nop + 8003104: 08003121 .word 0x08003121 + 8003108: 080035b1 .word 0x080035b1 + 800310c: 08003af9 .word 0x08003af9 + 8003110: 08004163 .word 0x08004163 + 8003114: 08004319 .word 0x08004319 + 8003118: 080044d9 .word 0x080044d9 + 800311c: 080046e5 .word 0x080046e5 + case STATE_SPEED: + ssd1306_Fill(Black); + 8003120: 2000 movs r0, #0 + 8003122: f7ff fb05 bl 8002730 + ssd1306_SetCursor(32, 32); + 8003126: 2120 movs r1, #32 + 8003128: 2020 movs r0, #32 + 800312a: f7ff fc43 bl 80029b4 + nmea_parse(&myData, DataBuffer); + 800312e: 4989 ldr r1, [pc, #548] ; (8003354 ) + 8003130: 4889 ldr r0, [pc, #548] ; (8003358 ) + 8003132: f7fe ff7b bl 800202c + if(myData.speed>=vitmax){ + 8003136: 4b88 ldr r3, [pc, #544] ; (8003358 ) + 8003138: ed93 7a0e vldr s14, [r3, #56] ; 0x38 + 800313c: 4b87 ldr r3, [pc, #540] ; (800335c ) + 800313e: edd3 7a00 vldr s15, [r3] + 8003142: eeb4 7ae7 vcmpe.f32 s14, s15 + 8003146: eef1 fa10 vmrs APSR_nzcv, fpscr + 800314a: db03 blt.n 8003154 + vitmax=myData.speed; + 800314c: 4b82 ldr r3, [pc, #520] ; (8003358 ) + 800314e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003150: 4a82 ldr r2, [pc, #520] ; (800335c ) + 8003152: 6013 str r3, [r2, #0] + } + float pace=0; + 8003154: f04f 0300 mov.w r3, #0 + 8003158: 667b str r3, [r7, #100] ; 0x64 + float sec=0; + 800315a: f04f 0300 mov.w r3, #0 + 800315e: 663b str r3, [r7, #96] ; 0x60 + if (myData.speed!=0){ + 8003160: 4b7d ldr r3, [pc, #500] ; (8003358 ) + 8003162: edd3 7a0e vldr s15, [r3, #56] ; 0x38 + 8003166: eef5 7a40 vcmp.f32 s15, #0.0 + 800316a: eef1 fa10 vmrs APSR_nzcv, fpscr + 800316e: d032 beq.n 80031d6 + pace=1000/(60*myData.speed); + 8003170: 4b79 ldr r3, [pc, #484] ; (8003358 ) + 8003172: edd3 7a0e vldr s15, [r3, #56] ; 0x38 + 8003176: ed9f 7a7a vldr s14, [pc, #488] ; 8003360 + 800317a: ee27 7a87 vmul.f32 s14, s15, s14 + 800317e: eddf 6a79 vldr s13, [pc, #484] ; 8003364 + 8003182: eec6 7a87 vdiv.f32 s15, s13, s14 + 8003186: edc7 7a19 vstr s15, [r7, #100] ; 0x64 + sec=(pace-floor(pace))*60; + 800318a: 6e78 ldr r0, [r7, #100] ; 0x64 + 800318c: f7fd f9dc bl 8000548 <__aeabi_f2d> + 8003190: 4604 mov r4, r0 + 8003192: 460d mov r5, r1 + 8003194: 6e78 ldr r0, [r7, #100] ; 0x64 + 8003196: f7fd f9d7 bl 8000548 <__aeabi_f2d> + 800319a: 4602 mov r2, r0 + 800319c: 460b mov r3, r1 + 800319e: ec43 2b10 vmov d0, r2, r3 + 80031a2: f014 fd0d bl 8017bc0 + 80031a6: ec53 2b10 vmov r2, r3, d0 + 80031aa: 4620 mov r0, r4 + 80031ac: 4629 mov r1, r5 + 80031ae: f7fd f86b bl 8000288 <__aeabi_dsub> + 80031b2: 4602 mov r2, r0 + 80031b4: 460b mov r3, r1 + 80031b6: 4610 mov r0, r2 + 80031b8: 4619 mov r1, r3 + 80031ba: f04f 0200 mov.w r2, #0 + 80031be: 4b6a ldr r3, [pc, #424] ; (8003368 ) + 80031c0: f7fd fa1a bl 80005f8 <__aeabi_dmul> + 80031c4: 4602 mov r2, r0 + 80031c6: 460b mov r3, r1 + 80031c8: 4610 mov r0, r2 + 80031ca: 4619 mov r1, r3 + 80031cc: f7fd fd0c bl 8000be8 <__aeabi_d2f> + 80031d0: 4603 mov r3, r0 + 80031d2: 663b str r3, [r7, #96] ; 0x60 + 80031d4: e001 b.n 80031da + } + else { + pace=9999;//en cas de division par 0, techniquement le temps devient infini mais ce n'est pas intérréssant + 80031d6: 4b65 ldr r3, [pc, #404] ; (800336c ) + 80031d8: 667b str r3, [r7, #100] ; 0x64 + } + + + switch(spdstate){ + 80031da: 4b65 ldr r3, [pc, #404] ; (8003370 ) + 80031dc: 781b ldrb r3, [r3, #0] + 80031de: 2b02 cmp r3, #2 + 80031e0: f000 8160 beq.w 80034a4 + 80031e4: 2b02 cmp r3, #2 + 80031e6: f300 81d0 bgt.w 800358a + 80031ea: 2b00 cmp r3, #0 + 80031ec: d003 beq.n 80031f6 + 80031ee: 2b01 cmp r3, #1 + 80031f0: f000 80d0 beq.w 8003394 + 80031f4: e1c9 b.n 800358a + + + case STATE_SUMMARY: + if(myData.fix == 1){ //if the GPS has a fix, print the data + 80031f6: 4b58 ldr r3, [pc, #352] ; (8003358 ) + 80031f8: 6a9b ldr r3, [r3, #40] ; 0x28 + 80031fa: 2b01 cmp r3, #1 + 80031fc: d16f bne.n 80032de + char * str = (char*)malloc(sizeof(char)*20); + 80031fe: 2014 movs r0, #20 + 8003200: f00f fef0 bl 8012fe4 + 8003204: 4603 mov r3, r0 + 8003206: 607b str r3, [r7, #4] + snprintf(str,15, "MaxV=%.1f",vitmax*3.6);//amélioration possible la stocker en eeprom + 8003208: 4b54 ldr r3, [pc, #336] ; (800335c ) + 800320a: 681b ldr r3, [r3, #0] + 800320c: 4618 mov r0, r3 + 800320e: f7fd f99b bl 8000548 <__aeabi_f2d> + 8003212: a34d add r3, pc, #308 ; (adr r3, 8003348 ) + 8003214: e9d3 2300 ldrd r2, r3, [r3] + 8003218: f7fd f9ee bl 80005f8 <__aeabi_dmul> + 800321c: 4602 mov r2, r0 + 800321e: 460b mov r3, r1 + 8003220: e9cd 2300 strd r2, r3, [sp] + 8003224: 4a53 ldr r2, [pc, #332] ; (8003374 ) + 8003226: 210f movs r1, #15 + 8003228: 6878 ldr r0, [r7, #4] + 800322a: f011 fdd7 bl 8014ddc + ssd1306_SetCursor(32, 32); + 800322e: 2120 movs r1, #32 + 8003230: 2020 movs r0, #32 + 8003232: f7ff fbbf bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 8003236: 4a50 ldr r2, [pc, #320] ; (8003378 ) + 8003238: 2301 movs r3, #1 + 800323a: ca06 ldmia r2, {r1, r2} + 800323c: 6878 ldr r0, [r7, #4] + 800323e: f7ff fb93 bl 8002968 + snprintf(str,15, "V=%0.1f",(myData.speed)*3.6); + 8003242: 4b45 ldr r3, [pc, #276] ; (8003358 ) + 8003244: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003246: 4618 mov r0, r3 + 8003248: f7fd f97e bl 8000548 <__aeabi_f2d> + 800324c: a33e add r3, pc, #248 ; (adr r3, 8003348 ) + 800324e: e9d3 2300 ldrd r2, r3, [r3] + 8003252: f7fd f9d1 bl 80005f8 <__aeabi_dmul> + 8003256: 4602 mov r2, r0 + 8003258: 460b mov r3, r1 + 800325a: e9cd 2300 strd r2, r3, [sp] + 800325e: 4a47 ldr r2, [pc, #284] ; (800337c ) + 8003260: 210f movs r1, #15 + 8003262: 6878 ldr r0, [r7, #4] + 8003264: f011 fdba bl 8014ddc + ssd1306_SetCursor(32, 42); + 8003268: 212a movs r1, #42 ; 0x2a + 800326a: 2020 movs r0, #32 + 800326c: f7ff fba2 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 8003270: 4a41 ldr r2, [pc, #260] ; (8003378 ) + 8003272: 2301 movs r3, #1 + 8003274: ca06 ldmia r2, {r1, r2} + 8003276: 6878 ldr r0, [r7, #4] + 8003278: f7ff fb76 bl 8002968 + snprintf(str,15, "p=%0.0fmin%0.0f s",floor(pace),floor(sec));//affichage au format minute puis seconde + 800327c: 6e78 ldr r0, [r7, #100] ; 0x64 + 800327e: f7fd f963 bl 8000548 <__aeabi_f2d> + 8003282: 4602 mov r2, r0 + 8003284: 460b mov r3, r1 + 8003286: ec43 2b10 vmov d0, r2, r3 + 800328a: f014 fc99 bl 8017bc0 + 800328e: eeb0 8a40 vmov.f32 s16, s0 + 8003292: eef0 8a60 vmov.f32 s17, s1 + 8003296: 6e38 ldr r0, [r7, #96] ; 0x60 + 8003298: f7fd f956 bl 8000548 <__aeabi_f2d> + 800329c: 4602 mov r2, r0 + 800329e: 460b mov r3, r1 + 80032a0: ec43 2b10 vmov d0, r2, r3 + 80032a4: f014 fc8c bl 8017bc0 + 80032a8: eeb0 7a40 vmov.f32 s14, s0 + 80032ac: eef0 7a60 vmov.f32 s15, s1 + 80032b0: ed8d 7b02 vstr d7, [sp, #8] + 80032b4: ed8d 8b00 vstr d8, [sp] + 80032b8: 4a31 ldr r2, [pc, #196] ; (8003380 ) + 80032ba: 210f movs r1, #15 + 80032bc: 6878 ldr r0, [r7, #4] + 80032be: f011 fd8d bl 8014ddc + ssd1306_SetCursor(32, 52); + 80032c2: 2134 movs r1, #52 ; 0x34 + 80032c4: 2020 movs r0, #32 + 80032c6: f7ff fb75 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 80032ca: 4a2b ldr r2, [pc, #172] ; (8003378 ) + 80032cc: 2301 movs r3, #1 + 80032ce: ca06 ldmia r2, {r1, r2} + 80032d0: 6878 ldr r0, [r7, #4] + 80032d2: f7ff fb49 bl 8002968 + free(str); + 80032d6: 6878 ldr r0, [r7, #4] + 80032d8: f00f fe8c bl 8012ff4 + 80032dc: e025 b.n 800332a + } + else{ //if the GPS doesn't have a fix, print a message + char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. + 80032de: 2014 movs r0, #20 + 80032e0: f00f fe80 bl 8012fe4 + 80032e4: 4603 mov r3, r0 + 80032e6: 60bb str r3, [r7, #8] + ssd1306_SetCursor(32, 32); + 80032e8: 2120 movs r1, #32 + 80032ea: 2020 movs r0, #32 + 80032ec: f7ff fb62 bl 80029b4 + ssd1306_WriteString("Speed 1", Font_6x8, White); + 80032f0: 4a21 ldr r2, [pc, #132] ; (8003378 ) + 80032f2: 2301 movs r3, #1 + 80032f4: ca06 ldmia r2, {r1, r2} + 80032f6: 4823 ldr r0, [pc, #140] ; (8003384 ) + 80032f8: f7ff fb36 bl 8002968 + ssd1306_SetCursor(32, 44); + 80032fc: 212c movs r1, #44 ; 0x2c + 80032fe: 2020 movs r0, #32 + 8003300: f7ff fb58 bl 80029b4 + ssd1306_WriteString("Wait GPS", Font_6x8, White); + 8003304: 4a1c ldr r2, [pc, #112] ; (8003378 ) + 8003306: 2301 movs r3, #1 + 8003308: ca06 ldmia r2, {r1, r2} + 800330a: 481f ldr r0, [pc, #124] ; (8003388 ) + 800330c: f7ff fb2c bl 8002968 + batterygauge(vbat,35, 54,1); + 8003310: 4b1e ldr r3, [pc, #120] ; (800338c ) + 8003312: edd3 7a00 vldr s15, [r3] + 8003316: 2201 movs r2, #1 + 8003318: 2136 movs r1, #54 ; 0x36 + 800331a: 2023 movs r0, #35 ; 0x23 + 800331c: eeb0 0a67 vmov.f32 s0, s15 + 8003320: f7ff fd66 bl 8002df0 + free(str); + 8003324: 68b8 ldr r0, [r7, #8] + 8003326: f00f fe65 bl 8012ff4 + } + if(BTN_B>=1){ + 800332a: 4b19 ldr r3, [pc, #100] ; (8003390 ) + 800332c: 681b ldr r3, [r3, #0] + 800332e: 2b00 cmp r3, #0 + 8003330: f340 8126 ble.w 8003580 + spdstate++; + 8003334: 4b0e ldr r3, [pc, #56] ; (8003370 ) + 8003336: 781b ldrb r3, [r3, #0] + 8003338: 3301 adds r3, #1 + 800333a: b2da uxtb r2, r3 + 800333c: 4b0c ldr r3, [pc, #48] ; (8003370 ) + 800333e: 701a strb r2, [r3, #0] + BTN_B=0; + 8003340: 4b13 ldr r3, [pc, #76] ; (8003390 ) + 8003342: 2200 movs r2, #0 + 8003344: 601a str r2, [r3, #0] + } + + + + break; + 8003346: e11b b.n 8003580 + 8003348: cccccccd .word 0xcccccccd + 800334c: 400ccccc .word 0x400ccccc + 8003350: 200006f8 .word 0x200006f8 + 8003354: 200004ac .word 0x200004ac + 8003358: 200006b0 .word 0x200006b0 + 800335c: 20000e34 .word 0x20000e34 + 8003360: 42700000 .word 0x42700000 + 8003364: 447a0000 .word 0x447a0000 + 8003368: 404e0000 .word 0x404e0000 + 800336c: 461c3c00 .word 0x461c3c00 + 8003370: 200006fa .word 0x200006fa + 8003374: 08018df4 .word 0x08018df4 + 8003378: 20000008 .word 0x20000008 + 800337c: 08018e00 .word 0x08018e00 + 8003380: 08018e08 .word 0x08018e08 + 8003384: 08018e1c .word 0x08018e1c + 8003388: 08018e24 .word 0x08018e24 + 800338c: 20000730 .word 0x20000730 + 8003390: 200006f4 .word 0x200006f4 + case STATE_COMPTEUR: + if(myData.fix == 1){ //if the GPS has a fix, print the data + 8003394: 4b96 ldr r3, [pc, #600] ; (80035f0 ) + 8003396: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003398: 2b01 cmp r3, #1 + 800339a: d159 bne.n 8003450 + char * str = (char*)malloc(sizeof(char)*20); + 800339c: 2014 movs r0, #20 + 800339e: f00f fe21 bl 8012fe4 + 80033a2: 4603 mov r3, r0 + 80033a4: 60fb str r3, [r7, #12] + snprintf(str,15, "V=%0.1f",(myData.speed)*3.6); + 80033a6: 4b92 ldr r3, [pc, #584] ; (80035f0 ) + 80033a8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80033aa: 4618 mov r0, r3 + 80033ac: f7fd f8cc bl 8000548 <__aeabi_f2d> + 80033b0: a38b add r3, pc, #556 ; (adr r3, 80035e0 ) + 80033b2: e9d3 2300 ldrd r2, r3, [r3] + 80033b6: f7fd f91f bl 80005f8 <__aeabi_dmul> + 80033ba: 4602 mov r2, r0 + 80033bc: 460b mov r3, r1 + 80033be: e9cd 2300 strd r2, r3, [sp] + 80033c2: 4a8c ldr r2, [pc, #560] ; (80035f4 ) + 80033c4: 210f movs r1, #15 + 80033c6: 68f8 ldr r0, [r7, #12] + 80033c8: f011 fd08 bl 8014ddc + ssd1306_SetCursor(32, 54); + 80033cc: 2136 movs r1, #54 ; 0x36 + 80033ce: 2020 movs r0, #32 + 80033d0: f7ff faf0 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 80033d4: 4a88 ldr r2, [pc, #544] ; (80035f8 ) + 80033d6: 2301 movs r3, #1 + 80033d8: ca06 ldmia r2, {r1, r2} + 80033da: 68f8 ldr r0, [r7, #12] + 80033dc: f7ff fac4 bl 8002968 + ssd1306_DrawRectangle(32, 38, 95, 53, White); + 80033e0: 2301 movs r3, #1 + 80033e2: 9300 str r3, [sp, #0] + 80033e4: 2335 movs r3, #53 ; 0x35 + 80033e6: 225f movs r2, #95 ; 0x5f + 80033e8: 2126 movs r1, #38 ; 0x26 + 80033ea: 2020 movs r0, #32 + 80033ec: f7ff fbed bl 8002bca + ssd1306_FillRectangle(32, 38,(int) floor(32+(myData.speed*0.63)), 53, White); + 80033f0: 4b7f ldr r3, [pc, #508] ; (80035f0 ) + 80033f2: 6b9b ldr r3, [r3, #56] ; 0x38 + 80033f4: 4618 mov r0, r3 + 80033f6: f7fd f8a7 bl 8000548 <__aeabi_f2d> + 80033fa: a37b add r3, pc, #492 ; (adr r3, 80035e8 ) + 80033fc: e9d3 2300 ldrd r2, r3, [r3] + 8003400: f7fd f8fa bl 80005f8 <__aeabi_dmul> + 8003404: 4602 mov r2, r0 + 8003406: 460b mov r3, r1 + 8003408: 4610 mov r0, r2 + 800340a: 4619 mov r1, r3 + 800340c: f04f 0200 mov.w r2, #0 + 8003410: 4b7a ldr r3, [pc, #488] ; (80035fc ) + 8003412: f7fc ff3b bl 800028c <__adddf3> + 8003416: 4602 mov r2, r0 + 8003418: 460b mov r3, r1 + 800341a: ec43 2b17 vmov d7, r2, r3 + 800341e: eeb0 0a47 vmov.f32 s0, s14 + 8003422: eef0 0a67 vmov.f32 s1, s15 + 8003426: f014 fbcb bl 8017bc0 + 800342a: ec53 2b10 vmov r2, r3, d0 + 800342e: 4610 mov r0, r2 + 8003430: 4619 mov r1, r3 + 8003432: f7fd fb91 bl 8000b58 <__aeabi_d2iz> + 8003436: 4603 mov r3, r0 + 8003438: b2da uxtb r2, r3 + 800343a: 2301 movs r3, #1 + 800343c: 9300 str r3, [sp, #0] + 800343e: 2335 movs r3, #53 ; 0x35 + 8003440: 2126 movs r1, #38 ; 0x26 + 8003442: 2020 movs r0, #32 + 8003444: f7ff fbf8 bl 8002c38 + + free(str); + 8003448: 68f8 ldr r0, [r7, #12] + 800344a: f00f fdd3 bl 8012ff4 + 800344e: e01b b.n 8003488 + } + else{ //if the GPS doesn't have a fix, print a message + char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. + 8003450: 2014 movs r0, #20 + 8003452: f00f fdc7 bl 8012fe4 + 8003456: 4603 mov r3, r0 + 8003458: 613b str r3, [r7, #16] + ssd1306_SetCursor(32, 32); + 800345a: 2120 movs r1, #32 + 800345c: 2020 movs r0, #32 + 800345e: f7ff faa9 bl 80029b4 + ssd1306_WriteString("Speed 2", Font_6x8, White); + 8003462: 4a65 ldr r2, [pc, #404] ; (80035f8 ) + 8003464: 2301 movs r3, #1 + 8003466: ca06 ldmia r2, {r1, r2} + 8003468: 4865 ldr r0, [pc, #404] ; (8003600 ) + 800346a: f7ff fa7d bl 8002968 + ssd1306_SetCursor(32, 44); + 800346e: 212c movs r1, #44 ; 0x2c + 8003470: 2020 movs r0, #32 + 8003472: f7ff fa9f bl 80029b4 + ssd1306_WriteString("Wait GPS", Font_6x8, White); + 8003476: 4a60 ldr r2, [pc, #384] ; (80035f8 ) + 8003478: 2301 movs r3, #1 + 800347a: ca06 ldmia r2, {r1, r2} + 800347c: 4861 ldr r0, [pc, #388] ; (8003604 ) + 800347e: f7ff fa73 bl 8002968 + free(str); + 8003482: 6938 ldr r0, [r7, #16] + 8003484: f00f fdb6 bl 8012ff4 + } + if(BTN_B>=1){ + 8003488: 4b5f ldr r3, [pc, #380] ; (8003608 ) + 800348a: 681b ldr r3, [r3, #0] + 800348c: 2b00 cmp r3, #0 + 800348e: dd79 ble.n 8003584 + spdstate++; + 8003490: 4b5e ldr r3, [pc, #376] ; (800360c ) + 8003492: 781b ldrb r3, [r3, #0] + 8003494: 3301 adds r3, #1 + 8003496: b2da uxtb r2, r3 + 8003498: 4b5c ldr r3, [pc, #368] ; (800360c ) + 800349a: 701a strb r2, [r3, #0] + BTN_B=0; + 800349c: 4b5a ldr r3, [pc, #360] ; (8003608 ) + 800349e: 2200 movs r2, #0 + 80034a0: 601a str r2, [r3, #0] + } + break; + 80034a2: e06f b.n 8003584 + case STATE_GRAPH: + if(myData.fix == 1){ + 80034a4: 4b52 ldr r3, [pc, #328] ; (80035f0 ) + 80034a6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80034a8: 2b01 cmp r3, #1 + 80034aa: d12f bne.n 800350c + char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. + 80034ac: 2014 movs r0, #20 + 80034ae: f00f fd99 bl 8012fe4 + 80034b2: 4603 mov r3, r0 + 80034b4: 617b str r3, [r7, #20] + + ssd1306_SetCursor(32, 32); + 80034b6: 2120 movs r1, #32 + 80034b8: 2020 movs r0, #32 + 80034ba: f7ff fa7b bl 80029b4 + snprintf(str,15, "%0.1f",(myData.speed)*3.6); + 80034be: 4b4c ldr r3, [pc, #304] ; (80035f0 ) + 80034c0: 6b9b ldr r3, [r3, #56] ; 0x38 + 80034c2: 4618 mov r0, r3 + 80034c4: f7fd f840 bl 8000548 <__aeabi_f2d> + 80034c8: a345 add r3, pc, #276 ; (adr r3, 80035e0 ) + 80034ca: e9d3 2300 ldrd r2, r3, [r3] + 80034ce: f7fd f893 bl 80005f8 <__aeabi_dmul> + 80034d2: 4602 mov r2, r0 + 80034d4: 460b mov r3, r1 + 80034d6: e9cd 2300 strd r2, r3, [sp] + 80034da: 4a4d ldr r2, [pc, #308] ; (8003610 ) + 80034dc: 210f movs r1, #15 + 80034de: 6978 ldr r0, [r7, #20] + 80034e0: f011 fc7c bl 8014ddc + ssd1306_WriteString(str, Font_11x18, White); + 80034e4: 4a4b ldr r2, [pc, #300] ; (8003614 ) + 80034e6: 2301 movs r3, #1 + 80034e8: ca06 ldmia r2, {r1, r2} + 80034ea: 6978 ldr r0, [r7, #20] + 80034ec: f7ff fa3c bl 8002968 + batterygauge(vbat,35, 54,1); + 80034f0: 4b49 ldr r3, [pc, #292] ; (8003618 ) + 80034f2: edd3 7a00 vldr s15, [r3] + 80034f6: 2201 movs r2, #1 + 80034f8: 2136 movs r1, #54 ; 0x36 + 80034fa: 2023 movs r0, #35 ; 0x23 + 80034fc: eeb0 0a67 vmov.f32 s0, s15 + 8003500: f7ff fc76 bl 8002df0 + + free(str); + 8003504: 6978 ldr r0, [r7, #20] + 8003506: f00f fd75 bl 8012ff4 + 800350a: e025 b.n 8003558 + } + else{ + char *str = (char*)malloc(sizeof(char)*20);// message qui sra dans tous les etat si l'on ne capte pas de sattelites. + 800350c: 2014 movs r0, #20 + 800350e: f00f fd69 bl 8012fe4 + 8003512: 4603 mov r3, r0 + 8003514: 61bb str r3, [r7, #24] + ssd1306_SetCursor(32, 32); + 8003516: 2120 movs r1, #32 + 8003518: 2020 movs r0, #32 + 800351a: f7ff fa4b bl 80029b4 + ssd1306_WriteString("Speed 3", Font_6x8, White); + 800351e: 4a36 ldr r2, [pc, #216] ; (80035f8 ) + 8003520: 2301 movs r3, #1 + 8003522: ca06 ldmia r2, {r1, r2} + 8003524: 483d ldr r0, [pc, #244] ; (800361c ) + 8003526: f7ff fa1f bl 8002968 + ssd1306_SetCursor(32, 44); + 800352a: 212c movs r1, #44 ; 0x2c + 800352c: 2020 movs r0, #32 + 800352e: f7ff fa41 bl 80029b4 + ssd1306_WriteString("Wait GPS", Font_6x8, White); + 8003532: 4a31 ldr r2, [pc, #196] ; (80035f8 ) + 8003534: 2301 movs r3, #1 + 8003536: ca06 ldmia r2, {r1, r2} + 8003538: 4832 ldr r0, [pc, #200] ; (8003604 ) + 800353a: f7ff fa15 bl 8002968 + batterygauge(vbat,35, 54,1); + 800353e: 4b36 ldr r3, [pc, #216] ; (8003618 ) + 8003540: edd3 7a00 vldr s15, [r3] + 8003544: 2201 movs r2, #1 + 8003546: 2136 movs r1, #54 ; 0x36 + 8003548: 2023 movs r0, #35 ; 0x23 + 800354a: eeb0 0a67 vmov.f32 s0, s15 + 800354e: f7ff fc4f bl 8002df0 + free(str); + 8003552: 69b8 ldr r0, [r7, #24] + 8003554: f00f fd4e bl 8012ff4 + } + + if(BTN_B>=1){ + 8003558: 4b2b ldr r3, [pc, #172] ; (8003608 ) + 800355a: 681b ldr r3, [r3, #0] + 800355c: 2b00 cmp r3, #0 + 800355e: dd13 ble.n 8003588 + spdstate--; + 8003560: 4b2a ldr r3, [pc, #168] ; (800360c ) + 8003562: 781b ldrb r3, [r3, #0] + 8003564: 3b01 subs r3, #1 + 8003566: b2da uxtb r2, r3 + 8003568: 4b28 ldr r3, [pc, #160] ; (800360c ) + 800356a: 701a strb r2, [r3, #0] + spdstate--; + 800356c: 4b27 ldr r3, [pc, #156] ; (800360c ) + 800356e: 781b ldrb r3, [r3, #0] + 8003570: 3b01 subs r3, #1 + 8003572: b2da uxtb r2, r3 + 8003574: 4b25 ldr r3, [pc, #148] ; (800360c ) + 8003576: 701a strb r2, [r3, #0] + BTN_B=0; + 8003578: 4b23 ldr r3, [pc, #140] ; (8003608 ) + 800357a: 2200 movs r2, #0 + 800357c: 601a str r2, [r3, #0] + + + } + break; + 800357e: e003 b.n 8003588 + break; + 8003580: bf00 nop + 8003582: e002 b.n 800358a + break; + 8003584: bf00 nop + 8003586: e000 b.n 800358a + break; + 8003588: bf00 nop + + + } + if(BTN_A>=1){ + 800358a: 4b25 ldr r3, [pc, #148] ; (8003620 ) + 800358c: 681b ldr r3, [r3, #0] + 800358e: 2b00 cmp r3, #0 + 8003590: f341 8228 ble.w 80049e4 + state++; + 8003594: 4b23 ldr r3, [pc, #140] ; (8003624 ) + 8003596: 781b ldrb r3, [r3, #0] + 8003598: 3301 adds r3, #1 + 800359a: b2da uxtb r2, r3 + 800359c: 4b21 ldr r3, [pc, #132] ; (8003624 ) + 800359e: 701a strb r2, [r3, #0] + BTN_A=0; + 80035a0: 4b1f ldr r3, [pc, #124] ; (8003620 ) + 80035a2: 2200 movs r2, #0 + 80035a4: 601a str r2, [r3, #0] + BTN_B=0; + 80035a6: 4b18 ldr r3, [pc, #96] ; (8003608 ) + 80035a8: 2200 movs r2, #0 + 80035aa: 601a str r2, [r3, #0] + } + break; + 80035ac: f001 ba1a b.w 80049e4 + + + case STATE_POS: + ssd1306_Fill(Black); + 80035b0: 2000 movs r0, #0 + 80035b2: f7ff f8bd bl 8002730 + nmea_parse(&myData, DataBuffer); + 80035b6: 491c ldr r1, [pc, #112] ; (8003628 ) + 80035b8: 480d ldr r0, [pc, #52] ; (80035f0 ) + 80035ba: f7fe fd37 bl 800202c + switch(posstate){ + 80035be: 4b1b ldr r3, [pc, #108] ; (800362c ) + 80035c0: 781b ldrb r3, [r3, #0] + 80035c2: 2b03 cmp r3, #3 + 80035c4: f200 8285 bhi.w 8003ad2 + 80035c8: a201 add r2, pc, #4 ; (adr r2, 80035d0 ) + 80035ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80035ce: bf00 nop + 80035d0: 08003631 .word 0x08003631 + 80035d4: 08003749 .word 0x08003749 + 80035d8: 0800383f .word 0x0800383f + 80035dc: 0800396f .word 0x0800396f + 80035e0: cccccccd .word 0xcccccccd + 80035e4: 400ccccc .word 0x400ccccc + 80035e8: c28f5c29 .word 0xc28f5c29 + 80035ec: 3fe428f5 .word 0x3fe428f5 + 80035f0: 200006b0 .word 0x200006b0 + 80035f4: 08018e00 .word 0x08018e00 + 80035f8: 20000008 .word 0x20000008 + 80035fc: 40400000 .word 0x40400000 + 8003600: 08018e30 .word 0x08018e30 + 8003604: 08018e24 .word 0x08018e24 + 8003608: 200006f4 .word 0x200006f4 + 800360c: 200006fa .word 0x200006fa + 8003610: 08018e38 .word 0x08018e38 + 8003614: 20000018 .word 0x20000018 + 8003618: 20000730 .word 0x20000730 + 800361c: 08018e40 .word 0x08018e40 + 8003620: 200006f0 .word 0x200006f0 + 8003624: 200006f8 .word 0x200006f8 + 8003628: 200004ac .word 0x200004ac + 800362c: 200006fb .word 0x200006fb + + case STATE_SUMMARY1: + if(myData.fix == 1){ + 8003630: 4bab ldr r3, [pc, #684] ; (80038e0 ) + 8003632: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003634: 2b01 cmp r3, #1 + 8003636: d14e bne.n 80036d6 + char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages + 8003638: 2014 movs r0, #20 + 800363a: f00f fcd3 bl 8012fe4 + 800363e: 4603 mov r3, r0 + 8003640: 61fb str r3, [r7, #28] + ssd1306_SetCursor(32, 32); + 8003642: 2120 movs r1, #32 + 8003644: 2020 movs r0, #32 + 8003646: f7ff f9b5 bl 80029b4 + snprintf(str,15, "Latitude:"); + 800364a: 4aa6 ldr r2, [pc, #664] ; (80038e4 ) + 800364c: 210f movs r1, #15 + 800364e: 69f8 ldr r0, [r7, #28] + 8003650: f011 fbc4 bl 8014ddc + ssd1306_WriteString(str, Font_6x8, White); + 8003654: 4aa4 ldr r2, [pc, #656] ; (80038e8 ) + 8003656: 2301 movs r3, #1 + 8003658: ca06 ldmia r2, {r1, r2} + 800365a: 69f8 ldr r0, [r7, #28] + 800365c: f7ff f984 bl 8002968 + snprintf(str,15, "%0.7f",myData.latitude);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps + 8003660: 4b9f ldr r3, [pc, #636] ; (80038e0 ) + 8003662: e9d3 2300 ldrd r2, r3, [r3] + 8003666: e9cd 2300 strd r2, r3, [sp] + 800366a: 4aa0 ldr r2, [pc, #640] ; (80038ec ) + 800366c: 210f movs r1, #15 + 800366e: 69f8 ldr r0, [r7, #28] + 8003670: f011 fbb4 bl 8014ddc + ssd1306_SetCursor(32, 40); + 8003674: 2128 movs r1, #40 ; 0x28 + 8003676: 2020 movs r0, #32 + 8003678: f7ff f99c bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 800367c: 4a9a ldr r2, [pc, #616] ; (80038e8 ) + 800367e: 2301 movs r3, #1 + 8003680: ca06 ldmia r2, {r1, r2} + 8003682: 69f8 ldr r0, [r7, #28] + 8003684: f7ff f970 bl 8002968 + snprintf(str,15, "Longitude:"); + 8003688: 4a99 ldr r2, [pc, #612] ; (80038f0 ) + 800368a: 210f movs r1, #15 + 800368c: 69f8 ldr r0, [r7, #28] + 800368e: f011 fba5 bl 8014ddc + ssd1306_SetCursor(32, 48); + 8003692: 2130 movs r1, #48 ; 0x30 + 8003694: 2020 movs r0, #32 + 8003696: f7ff f98d bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 800369a: 4a93 ldr r2, [pc, #588] ; (80038e8 ) + 800369c: 2301 movs r3, #1 + 800369e: ca06 ldmia r2, {r1, r2} + 80036a0: 69f8 ldr r0, [r7, #28] + 80036a2: f7ff f961 bl 8002968 + snprintf(str,15, "%0.7f",myData.longitude); + 80036a6: 4b8e ldr r3, [pc, #568] ; (80038e0 ) + 80036a8: e9d3 2304 ldrd r2, r3, [r3, #16] + 80036ac: e9cd 2300 strd r2, r3, [sp] + 80036b0: 4a8e ldr r2, [pc, #568] ; (80038ec ) + 80036b2: 210f movs r1, #15 + 80036b4: 69f8 ldr r0, [r7, #28] + 80036b6: f011 fb91 bl 8014ddc + ssd1306_SetCursor(32, 56); + 80036ba: 2138 movs r1, #56 ; 0x38 + 80036bc: 2020 movs r0, #32 + 80036be: f7ff f979 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 80036c2: 4a89 ldr r2, [pc, #548] ; (80038e8 ) + 80036c4: 2301 movs r3, #1 + 80036c6: ca06 ldmia r2, {r1, r2} + 80036c8: 69f8 ldr r0, [r7, #28] + 80036ca: f7ff f94d bl 8002968 + free(str); + 80036ce: 69f8 ldr r0, [r7, #28] + 80036d0: f00f fc90 bl 8012ff4 + 80036d4: e029 b.n 800372a + } + else{ //if the GPS doesn't have a fix, print a message + char *str = (char*)malloc(sizeof(char)*20); + 80036d6: 2014 movs r0, #20 + 80036d8: f00f fc84 bl 8012fe4 + 80036dc: 4603 mov r3, r0 + 80036de: 623b str r3, [r7, #32] + ssd1306_SetCursor(32, 32); + 80036e0: 2120 movs r1, #32 + 80036e2: 2020 movs r0, #32 + 80036e4: f7ff f966 bl 80029b4 + ssd1306_WriteString("Pos1", Font_6x8, White); + 80036e8: 4a7f ldr r2, [pc, #508] ; (80038e8 ) + 80036ea: 2301 movs r3, #1 + 80036ec: ca06 ldmia r2, {r1, r2} + 80036ee: 4881 ldr r0, [pc, #516] ; (80038f4 ) + 80036f0: f7ff f93a bl 8002968 + ssd1306_SetCursor(32, 44); + 80036f4: 212c movs r1, #44 ; 0x2c + 80036f6: 2020 movs r0, #32 + 80036f8: f7ff f95c bl 80029b4 + ssd1306_WriteString("Wait GPS", Font_6x8, White); + 80036fc: 4a7a ldr r2, [pc, #488] ; (80038e8 ) + 80036fe: 2301 movs r3, #1 + 8003700: ca06 ldmia r2, {r1, r2} + 8003702: 487d ldr r0, [pc, #500] ; (80038f8 ) + 8003704: f7ff f930 bl 8002968 + ssd1306_SetCursor(32, 54); + 8003708: 2136 movs r1, #54 ; 0x36 + 800370a: 2020 movs r0, #32 + 800370c: f7ff f952 bl 80029b4 + batterygauge(vbat,35, 54,1); + 8003710: 4b7a ldr r3, [pc, #488] ; (80038fc ) + 8003712: edd3 7a00 vldr s15, [r3] + 8003716: 2201 movs r2, #1 + 8003718: 2136 movs r1, #54 ; 0x36 + 800371a: 2023 movs r0, #35 ; 0x23 + 800371c: eeb0 0a67 vmov.f32 s0, s15 + 8003720: f7ff fb66 bl 8002df0 + free(str); + 8003724: 6a38 ldr r0, [r7, #32] + 8003726: f00f fc65 bl 8012ff4 + } if(BTN_B>=1){ - 8002e98: 4b52 ldr r3, [pc, #328] ; (8002fe4 ) - 8002e9a: 681b ldr r3, [r3, #0] - 8002e9c: 2b00 cmp r3, #0 - 8002e9e: f340 8164 ble.w 800316a + 800372a: 4b75 ldr r3, [pc, #468] ; (8003900 ) + 800372c: 681b ldr r3, [r3, #0] + 800372e: 2b00 cmp r3, #0 + 8003730: f340 81c8 ble.w 8003ac4 + posstate++; + 8003734: 4b73 ldr r3, [pc, #460] ; (8003904 ) + 8003736: 781b ldrb r3, [r3, #0] + 8003738: 3301 adds r3, #1 + 800373a: b2da uxtb r2, r3 + 800373c: 4b71 ldr r3, [pc, #452] ; (8003904 ) + 800373e: 701a strb r2, [r3, #0] + BTN_B=0; + 8003740: 4b6f ldr r3, [pc, #444] ; (8003900 ) + 8003742: 2200 movs r2, #0 + 8003744: 601a str r2, [r3, #0] + + + + + + break; + 8003746: e1bd b.n 8003ac4 + case STATE_LAT: + if(myData.fix == 1){ + 8003748: 4b65 ldr r3, [pc, #404] ; (80038e0 ) + 800374a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800374c: 2b01 cmp r3, #1 + 800374e: d14b bne.n 80037e8 + char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages + 8003750: 2014 movs r0, #20 + 8003752: f00f fc47 bl 8012fe4 + 8003756: 4603 mov r3, r0 + 8003758: 627b str r3, [r7, #36] ; 0x24 + ssd1306_SetCursor(32, 32); + 800375a: 2120 movs r1, #32 + 800375c: 2020 movs r0, #32 + 800375e: f7ff f929 bl 80029b4 + snprintf(str,15, "LatSide:"); + 8003762: 4a69 ldr r2, [pc, #420] ; (8003908 ) + 8003764: 210f movs r1, #15 + 8003766: 6a78 ldr r0, [r7, #36] ; 0x24 + 8003768: f011 fb38 bl 8014ddc + ssd1306_WriteString(str, Font_6x8, White); + 800376c: 4a5e ldr r2, [pc, #376] ; (80038e8 ) + 800376e: 2301 movs r3, #1 + 8003770: ca06 ldmia r2, {r1, r2} + 8003772: 6a78 ldr r0, [r7, #36] ; 0x24 + 8003774: f7ff f8f8 bl 8002968 + snprintf(str,15, "%c",myData.latSide);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps + 8003778: 4b59 ldr r3, [pc, #356] ; (80038e0 ) + 800377a: 7a1b ldrb r3, [r3, #8] + 800377c: 4a63 ldr r2, [pc, #396] ; (800390c ) + 800377e: 210f movs r1, #15 + 8003780: 6a78 ldr r0, [r7, #36] ; 0x24 + 8003782: f011 fb2b bl 8014ddc + ssd1306_SetCursor(32, 40); + 8003786: 2128 movs r1, #40 ; 0x28 + 8003788: 2020 movs r0, #32 + 800378a: f7ff f913 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 800378e: 4a56 ldr r2, [pc, #344] ; (80038e8 ) + 8003790: 2301 movs r3, #1 + 8003792: ca06 ldmia r2, {r1, r2} + 8003794: 6a78 ldr r0, [r7, #36] ; 0x24 + 8003796: f7ff f8e7 bl 8002968 + snprintf(str,15, "Latitude:"); + 800379a: 4a52 ldr r2, [pc, #328] ; (80038e4 ) + 800379c: 210f movs r1, #15 + 800379e: 6a78 ldr r0, [r7, #36] ; 0x24 + 80037a0: f011 fb1c bl 8014ddc + ssd1306_SetCursor(32, 48); + 80037a4: 2130 movs r1, #48 ; 0x30 + 80037a6: 2020 movs r0, #32 + 80037a8: f7ff f904 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 80037ac: 4a4e ldr r2, [pc, #312] ; (80038e8 ) + 80037ae: 2301 movs r3, #1 + 80037b0: ca06 ldmia r2, {r1, r2} + 80037b2: 6a78 ldr r0, [r7, #36] ; 0x24 + 80037b4: f7ff f8d8 bl 8002968 + snprintf(str,15, "%0.7f",myData.latitude); + 80037b8: 4b49 ldr r3, [pc, #292] ; (80038e0 ) + 80037ba: e9d3 2300 ldrd r2, r3, [r3] + 80037be: e9cd 2300 strd r2, r3, [sp] + 80037c2: 4a4a ldr r2, [pc, #296] ; (80038ec ) + 80037c4: 210f movs r1, #15 + 80037c6: 6a78 ldr r0, [r7, #36] ; 0x24 + 80037c8: f011 fb08 bl 8014ddc + ssd1306_SetCursor(32, 56); + 80037cc: 2138 movs r1, #56 ; 0x38 + 80037ce: 2020 movs r0, #32 + 80037d0: f7ff f8f0 bl 80029b4 + ssd1306_WriteString(str, Font_6x8, White); + 80037d4: 4a44 ldr r2, [pc, #272] ; (80038e8 ) + 80037d6: 2301 movs r3, #1 + 80037d8: ca06 ldmia r2, {r1, r2} + 80037da: 6a78 ldr r0, [r7, #36] ; 0x24 + 80037dc: f7ff f8c4 bl 8002968 + free(str); + 80037e0: 6a78 ldr r0, [r7, #36] ; 0x24 + 80037e2: f00f fc07 bl 8012ff4 + 80037e6: e01b b.n 8003820 + } + else{ //if the GPS doesn't have a fix, print a message + char *str = (char*)malloc(sizeof(char)*20); + 80037e8: 2014 movs r0, #20 + 80037ea: f00f fbfb bl 8012fe4 + 80037ee: 4603 mov r3, r0 + 80037f0: 62bb str r3, [r7, #40] ; 0x28 + ssd1306_SetCursor(32, 32); + 80037f2: 2120 movs r1, #32 + 80037f4: 2020 movs r0, #32 + 80037f6: f7ff f8dd bl 80029b4 + ssd1306_WriteString("Pos2", Font_6x8, White); + 80037fa: 4a3b ldr r2, [pc, #236] ; (80038e8 ) + 80037fc: 2301 movs r3, #1 + 80037fe: ca06 ldmia r2, {r1, r2} + 8003800: 4843 ldr r0, [pc, #268] ; (8003910 ) + 8003802: f7ff f8b1 bl 8002968 + ssd1306_SetCursor(32, 44); + 8003806: 212c movs r1, #44 ; 0x2c + 8003808: 2020 movs r0, #32 + 800380a: f7ff f8d3 bl 80029b4 + ssd1306_WriteString("Wait GPS", Font_6x8, White); + 800380e: 4a36 ldr r2, [pc, #216] ; (80038e8 ) + 8003810: 2301 movs r3, #1 + 8003812: ca06 ldmia r2, {r1, r2} + 8003814: 4838 ldr r0, [pc, #224] ; (80038f8 ) + 8003816: f7ff f8a7 bl 8002968 + free(str); + 800381a: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800381c: f00f fbea bl 8012ff4 + } + if(BTN_B>=1){ + 8003820: 4b37 ldr r3, [pc, #220] ; (8003900 ) + 8003822: 681b ldr r3, [r3, #0] + 8003824: 2b00 cmp r3, #0 + 8003826: f340 814f ble.w 8003ac8 posstate++; - 8002ea2: 4b51 ldr r3, [pc, #324] ; (8002fe8 ) - 8002ea4: 781b ldrb r3, [r3, #0] - 8002ea6: 3301 adds r3, #1 - 8002ea8: b2da uxtb r2, r3 - 8002eaa: 4b4f ldr r3, [pc, #316] ; (8002fe8 ) - 8002eac: 701a strb r2, [r3, #0] + 800382a: 4b36 ldr r3, [pc, #216] ; (8003904 ) + 800382c: 781b ldrb r3, [r3, #0] + 800382e: 3301 adds r3, #1 + 8003830: b2da uxtb r2, r3 + 8003832: 4b34 ldr r3, [pc, #208] ; (8003904 ) + 8003834: 701a strb r2, [r3, #0] BTN_B=0; - 8002eae: 4b4d ldr r3, [pc, #308] ; (8002fe4 ) - 8002eb0: 2200 movs r2, #0 - 8002eb2: 601a str r2, [r3, #0] + 8003836: 4b32 ldr r3, [pc, #200] ; (8003900 ) + 8003838: 2200 movs r2, #0 + 800383a: 601a str r2, [r3, #0] } break; - 8002eb4: e159 b.n 800316a + 800383c: e144 b.n 8003ac8 case STATE_LONG: if(myData.fix == 1){ - 8002eb6: 4b43 ldr r3, [pc, #268] ; (8002fc4 ) - 8002eb8: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002eba: 2b01 cmp r3, #1 - 8002ebc: d155 bne.n 8002f6a + 800383e: 4b28 ldr r3, [pc, #160] ; (80038e0 ) + 8003840: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003842: 2b01 cmp r3, #1 + 8003844: d168 bne.n 8003918 char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages - 8002ebe: 2014 movs r0, #20 - 8002ec0: f00d fe38 bl 8010b34 - 8002ec4: 4603 mov r3, r0 - 8002ec6: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 8003846: 2014 movs r0, #20 + 8003848: f00f fbcc bl 8012fe4 + 800384c: 4603 mov r3, r0 + 800384e: 62fb str r3, [r7, #44] ; 0x2c ssd1306_SetCursor(32, 32); - 8002eca: 2120 movs r1, #32 - 8002ecc: 2020 movs r0, #32 - 8002ece: f7ff fa43 bl 8002358 + 8003850: 2120 movs r1, #32 + 8003852: 2020 movs r0, #32 + 8003854: f7ff f8ae bl 80029b4 snprintf(str,15, "LonSide:"); - 8002ed2: 4a46 ldr r2, [pc, #280] ; (8002fec ) - 8002ed4: 210f movs r1, #15 - 8002ed6: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002eda: f00f fd27 bl 801292c + 8003858: 4a2e ldr r2, [pc, #184] ; (8003914 ) + 800385a: 210f movs r1, #15 + 800385c: 6af8 ldr r0, [r7, #44] ; 0x2c + 800385e: f011 fabd bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 8002ede: 4a3b ldr r2, [pc, #236] ; (8002fcc ) - 8002ee0: 2301 movs r3, #1 - 8002ee2: ca06 ldmia r2, {r1, r2} - 8002ee4: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002ee8: f7ff fa10 bl 800230c + 8003862: 4a21 ldr r2, [pc, #132] ; (80038e8 ) + 8003864: 2301 movs r3, #1 + 8003866: ca06 ldmia r2, {r1, r2} + 8003868: 6af8 ldr r0, [r7, #44] ; 0x2c + 800386a: f7ff f87d bl 8002968 snprintf(str,15, "%c",myData.lonSide);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps - 8002eec: 4b35 ldr r3, [pc, #212] ; (8002fc4 ) - 8002eee: 7e1b ldrb r3, [r3, #24] - 8002ef0: 4a37 ldr r2, [pc, #220] ; (8002fd0 ) - 8002ef2: 210f movs r1, #15 - 8002ef4: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002ef8: f00f fd18 bl 801292c + 800386e: 4b1c ldr r3, [pc, #112] ; (80038e0 ) + 8003870: 7e1b ldrb r3, [r3, #24] + 8003872: 4a26 ldr r2, [pc, #152] ; (800390c ) + 8003874: 210f movs r1, #15 + 8003876: 6af8 ldr r0, [r7, #44] ; 0x2c + 8003878: f011 fab0 bl 8014ddc ssd1306_SetCursor(32, 40); - 8002efc: 2128 movs r1, #40 ; 0x28 - 8002efe: 2020 movs r0, #32 - 8002f00: f7ff fa2a bl 8002358 + 800387c: 2128 movs r1, #40 ; 0x28 + 800387e: 2020 movs r0, #32 + 8003880: f7ff f898 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8002f04: 4a31 ldr r2, [pc, #196] ; (8002fcc ) - 8002f06: 2301 movs r3, #1 - 8002f08: ca06 ldmia r2, {r1, r2} - 8002f0a: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f0e: f7ff f9fd bl 800230c + 8003884: 4a18 ldr r2, [pc, #96] ; (80038e8 ) + 8003886: 2301 movs r3, #1 + 8003888: ca06 ldmia r2, {r1, r2} + 800388a: 6af8 ldr r0, [r7, #44] ; 0x2c + 800388c: f7ff f86c bl 8002968 snprintf(str,15, "Longitude:"); - 8002f12: 4a37 ldr r2, [pc, #220] ; (8002ff0 ) - 8002f14: 210f movs r1, #15 - 8002f16: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f1a: f00f fd07 bl 801292c + 8003890: 4a17 ldr r2, [pc, #92] ; (80038f0 ) + 8003892: 210f movs r1, #15 + 8003894: 6af8 ldr r0, [r7, #44] ; 0x2c + 8003896: f011 faa1 bl 8014ddc ssd1306_SetCursor(32, 48); - 8002f1e: 2130 movs r1, #48 ; 0x30 - 8002f20: 2020 movs r0, #32 - 8002f22: f7ff fa19 bl 8002358 + 800389a: 2130 movs r1, #48 ; 0x30 + 800389c: 2020 movs r0, #32 + 800389e: f7ff f889 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8002f26: 4a29 ldr r2, [pc, #164] ; (8002fcc ) - 8002f28: 2301 movs r3, #1 - 8002f2a: ca06 ldmia r2, {r1, r2} - 8002f2c: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f30: f7ff f9ec bl 800230c + 80038a2: 4a11 ldr r2, [pc, #68] ; (80038e8 ) + 80038a4: 2301 movs r3, #1 + 80038a6: ca06 ldmia r2, {r1, r2} + 80038a8: 6af8 ldr r0, [r7, #44] ; 0x2c + 80038aa: f7ff f85d bl 8002968 snprintf(str,15, "%0.7f",myData.longitude); - 8002f34: 4b23 ldr r3, [pc, #140] ; (8002fc4 ) - 8002f36: e9d3 2304 ldrd r2, r3, [r3, #16] - 8002f3a: e9cd 2300 strd r2, r3, [sp] - 8002f3e: 4a26 ldr r2, [pc, #152] ; (8002fd8 ) - 8002f40: 210f movs r1, #15 - 8002f42: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f46: f00f fcf1 bl 801292c + 80038ae: 4b0c ldr r3, [pc, #48] ; (80038e0 ) + 80038b0: e9d3 2304 ldrd r2, r3, [r3, #16] + 80038b4: e9cd 2300 strd r2, r3, [sp] + 80038b8: 4a0c ldr r2, [pc, #48] ; (80038ec ) + 80038ba: 210f movs r1, #15 + 80038bc: 6af8 ldr r0, [r7, #44] ; 0x2c + 80038be: f011 fa8d bl 8014ddc ssd1306_SetCursor(32, 56); - 8002f4a: 2138 movs r1, #56 ; 0x38 - 8002f4c: 2020 movs r0, #32 - 8002f4e: f7ff fa03 bl 8002358 + 80038c2: 2138 movs r1, #56 ; 0x38 + 80038c4: 2020 movs r0, #32 + 80038c6: f7ff f875 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8002f52: 4a1e ldr r2, [pc, #120] ; (8002fcc ) - 8002f54: 2301 movs r3, #1 - 8002f56: ca06 ldmia r2, {r1, r2} - 8002f58: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f5c: f7ff f9d6 bl 800230c + 80038ca: 4a07 ldr r2, [pc, #28] ; (80038e8 ) + 80038cc: 2301 movs r3, #1 + 80038ce: ca06 ldmia r2, {r1, r2} + 80038d0: 6af8 ldr r0, [r7, #44] ; 0x2c + 80038d2: f7ff f849 bl 8002968 free(str); - 8002f60: f8d7 0080 ldr.w r0, [r7, #128] ; 0x80 - 8002f64: f00d fdee bl 8010b44 - 8002f68: e01d b.n 8002fa6 + 80038d6: 6af8 ldr r0, [r7, #44] ; 0x2c + 80038d8: f00f fb8c bl 8012ff4 + 80038dc: e038 b.n 8003950 + 80038de: bf00 nop + 80038e0: 200006b0 .word 0x200006b0 + 80038e4: 08018e48 .word 0x08018e48 + 80038e8: 20000008 .word 0x20000008 + 80038ec: 08018e54 .word 0x08018e54 + 80038f0: 08018e5c .word 0x08018e5c + 80038f4: 08018e68 .word 0x08018e68 + 80038f8: 08018e24 .word 0x08018e24 + 80038fc: 20000730 .word 0x20000730 + 8003900: 200006f4 .word 0x200006f4 + 8003904: 200006fb .word 0x200006fb + 8003908: 08018e70 .word 0x08018e70 + 800390c: 08018e7c .word 0x08018e7c + 8003910: 08018e80 .word 0x08018e80 + 8003914: 08018e88 .word 0x08018e88 } else{ //if the GPS doesn't have a fix, print a message char *str = (char*)malloc(sizeof(char)*20); - 8002f6a: 2014 movs r0, #20 - 8002f6c: f00d fde2 bl 8010b34 - 8002f70: 4603 mov r3, r0 - 8002f72: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 8003918: 2014 movs r0, #20 + 800391a: f00f fb63 bl 8012fe4 + 800391e: 4603 mov r3, r0 + 8003920: 633b str r3, [r7, #48] ; 0x30 ssd1306_SetCursor(32, 32); - 8002f76: 2120 movs r1, #32 - 8002f78: 2020 movs r0, #32 - 8002f7a: f7ff f9ed bl 8002358 + 8003922: 2120 movs r1, #32 + 8003924: 2020 movs r0, #32 + 8003926: f7ff f845 bl 80029b4 ssd1306_WriteString("Pos3", Font_6x8, White); - 8002f7e: 4a13 ldr r2, [pc, #76] ; (8002fcc ) - 8002f80: 2301 movs r3, #1 - 8002f82: ca06 ldmia r2, {r1, r2} - 8002f84: 481b ldr r0, [pc, #108] ; (8002ff4 ) - 8002f86: f7ff f9c1 bl 800230c + 800392a: 4aa1 ldr r2, [pc, #644] ; (8003bb0 ) + 800392c: 2301 movs r3, #1 + 800392e: ca06 ldmia r2, {r1, r2} + 8003930: 48a0 ldr r0, [pc, #640] ; (8003bb4 ) + 8003932: f7ff f819 bl 8002968 ssd1306_SetCursor(32, 44); - 8002f8a: 212c movs r1, #44 ; 0x2c - 8002f8c: 2020 movs r0, #32 - 8002f8e: f7ff f9e3 bl 8002358 + 8003936: 212c movs r1, #44 ; 0x2c + 8003938: 2020 movs r0, #32 + 800393a: f7ff f83b bl 80029b4 ssd1306_WriteString("Wait GPS", Font_6x8, White); - 8002f92: 4a0e ldr r2, [pc, #56] ; (8002fcc ) - 8002f94: 2301 movs r3, #1 - 8002f96: ca06 ldmia r2, {r1, r2} - 8002f98: 4811 ldr r0, [pc, #68] ; (8002fe0 ) - 8002f9a: f7ff f9b7 bl 800230c + 800393e: 4a9c ldr r2, [pc, #624] ; (8003bb0 ) + 8003940: 2301 movs r3, #1 + 8003942: ca06 ldmia r2, {r1, r2} + 8003944: 489c ldr r0, [pc, #624] ; (8003bb8 ) + 8003946: f7ff f80f bl 8002968 free(str); - 8002f9e: f8d7 0084 ldr.w r0, [r7, #132] ; 0x84 - 8002fa2: f00d fdcf bl 8010b44 + 800394a: 6b38 ldr r0, [r7, #48] ; 0x30 + 800394c: f00f fb52 bl 8012ff4 } if(BTN_B>=1){ - 8002fa6: 4b0f ldr r3, [pc, #60] ; (8002fe4 ) - 8002fa8: 681b ldr r3, [r3, #0] - 8002faa: 2b00 cmp r3, #0 - 8002fac: f340 80df ble.w 800316e + 8003950: 4b9a ldr r3, [pc, #616] ; (8003bbc ) + 8003952: 681b ldr r3, [r3, #0] + 8003954: 2b00 cmp r3, #0 + 8003956: f340 80b9 ble.w 8003acc posstate++; - 8002fb0: 4b0d ldr r3, [pc, #52] ; (8002fe8 ) - 8002fb2: 781b ldrb r3, [r3, #0] - 8002fb4: 3301 adds r3, #1 - 8002fb6: b2da uxtb r2, r3 - 8002fb8: 4b0b ldr r3, [pc, #44] ; (8002fe8 ) - 8002fba: 701a strb r2, [r3, #0] + 800395a: 4b99 ldr r3, [pc, #612] ; (8003bc0 ) + 800395c: 781b ldrb r3, [r3, #0] + 800395e: 3301 adds r3, #1 + 8003960: b2da uxtb r2, r3 + 8003962: 4b97 ldr r3, [pc, #604] ; (8003bc0 ) + 8003964: 701a strb r2, [r3, #0] BTN_B=0; - 8002fbc: 4b09 ldr r3, [pc, #36] ; (8002fe4 ) - 8002fbe: 2200 movs r2, #0 - 8002fc0: 601a str r2, [r3, #0] + 8003966: 4b95 ldr r3, [pc, #596] ; (8003bbc ) + 8003968: 2200 movs r2, #0 + 800396a: 601a str r2, [r3, #0] } break; - 8002fc2: e0d4 b.n 800316e - 8002fc4: 200007e0 .word 0x200007e0 - 8002fc8: 0801697c .word 0x0801697c - 8002fcc: 20000008 .word 0x20000008 - 8002fd0: 08016988 .word 0x08016988 - 8002fd4: 08016954 .word 0x08016954 - 8002fd8: 08016960 .word 0x08016960 - 8002fdc: 0801698c .word 0x0801698c - 8002fe0: 0801692c .word 0x0801692c - 8002fe4: 20000824 .word 0x20000824 - 8002fe8: 2000082b .word 0x2000082b - 8002fec: 08016994 .word 0x08016994 - 8002ff0: 08016968 .word 0x08016968 - 8002ff4: 080169a0 .word 0x080169a0 + 800396c: e0ae b.n 8003acc case STATE_ALT: if(myData.fix == 1){ - 8002ff8: 4bbd ldr r3, [pc, #756] ; (80032f0 ) - 8002ffa: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002ffc: 2b01 cmp r3, #1 - 8002ffe: d17a bne.n 80030f6 + 800396e: 4b95 ldr r3, [pc, #596] ; (8003bc4 ) + 8003970: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003972: 2b01 cmp r3, #1 + 8003974: d170 bne.n 8003a58 char * str = (char*)malloc(sizeof(char)*20);//tout le long, on utilisera le meme buffer str pour tous les affichages - 8003000: 2014 movs r0, #20 - 8003002: f00d fd97 bl 8010b34 - 8003006: 4603 mov r3, r0 - 8003008: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + 8003976: 2014 movs r0, #20 + 8003978: f00f fb34 bl 8012fe4 + 800397c: 4603 mov r3, r0 + 800397e: 637b str r3, [r7, #52] ; 0x34 ssd1306_SetCursor(32, 32); - 800300c: 2120 movs r1, #32 - 800300e: 2020 movs r0, #32 - 8003010: f7ff f9a2 bl 8002358 + 8003980: 2120 movs r1, #32 + 8003982: 2020 movs r0, #32 + 8003984: f7ff f816 bl 80029b4 snprintf(str,15, "altitude:"); - 8003014: 4ab7 ldr r2, [pc, #732] ; (80032f4 ) - 8003016: 210f movs r1, #15 - 8003018: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 800301c: f00f fc86 bl 801292c + 8003988: 4a8f ldr r2, [pc, #572] ; (8003bc8 ) + 800398a: 210f movs r1, #15 + 800398c: 6b78 ldr r0, [r7, #52] ; 0x34 + 800398e: f011 fa25 bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 8003020: 4ab5 ldr r2, [pc, #724] ; (80032f8 ) - 8003022: 2301 movs r3, #1 - 8003024: ca06 ldmia r2, {r1, r2} - 8003026: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 800302a: f7ff f96f bl 800230c + 8003992: 4a87 ldr r2, [pc, #540] ; (8003bb0 ) + 8003994: 2301 movs r3, #1 + 8003996: ca06 ldmia r2, {r1, r2} + 8003998: 6b78 ldr r0, [r7, #52] ; 0x34 + 800399a: f7fe ffe5 bl 8002968 snprintf(str,15, "%0.1f m",myData.altitude);//pas forcement utile d'afficher 7 decimales apres la virgule, 6 donne une precision au metre ce qui est le max du gps - 800302e: 4bb0 ldr r3, [pc, #704] ; (80032f0 ) - 8003030: 69db ldr r3, [r3, #28] - 8003032: 4618 mov r0, r3 - 8003034: f7fd fa88 bl 8000548 <__aeabi_f2d> - 8003038: 4602 mov r2, r0 - 800303a: 460b mov r3, r1 - 800303c: e9cd 2300 strd r2, r3, [sp] - 8003040: 4aae ldr r2, [pc, #696] ; (80032fc ) - 8003042: 210f movs r1, #15 - 8003044: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 8003048: f00f fc70 bl 801292c + 800399e: 4b89 ldr r3, [pc, #548] ; (8003bc4 ) + 80039a0: 69db ldr r3, [r3, #28] + 80039a2: 4618 mov r0, r3 + 80039a4: f7fc fdd0 bl 8000548 <__aeabi_f2d> + 80039a8: 4602 mov r2, r0 + 80039aa: 460b mov r3, r1 + 80039ac: e9cd 2300 strd r2, r3, [sp] + 80039b0: 4a86 ldr r2, [pc, #536] ; (8003bcc ) + 80039b2: 210f movs r1, #15 + 80039b4: 6b78 ldr r0, [r7, #52] ; 0x34 + 80039b6: f011 fa11 bl 8014ddc ssd1306_SetCursor(32, 40); - 800304c: 2128 movs r1, #40 ; 0x28 - 800304e: 2020 movs r0, #32 - 8003050: f7ff f982 bl 8002358 + 80039ba: 2128 movs r1, #40 ; 0x28 + 80039bc: 2020 movs r0, #32 + 80039be: f7fe fff9 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8003054: 4aa8 ldr r2, [pc, #672] ; (80032f8 ) - 8003056: 2301 movs r3, #1 - 8003058: ca06 ldmia r2, {r1, r2} - 800305a: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 800305e: f7ff f955 bl 800230c + 80039c2: 4a7b ldr r2, [pc, #492] ; (8003bb0 ) + 80039c4: 2301 movs r3, #1 + 80039c6: ca06 ldmia r2, {r1, r2} + 80039c8: 6b78 ldr r0, [r7, #52] ; 0x34 + 80039ca: f7fe ffcd bl 8002968 snprintf(str,15, "Pressure:"); - 8003062: 4aa7 ldr r2, [pc, #668] ; (8003300 ) - 8003064: 210f movs r1, #15 - 8003066: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 800306a: f00f fc5f bl 801292c + 80039ce: 4a80 ldr r2, [pc, #512] ; (8003bd0 ) + 80039d0: 210f movs r1, #15 + 80039d2: 6b78 ldr r0, [r7, #52] ; 0x34 + 80039d4: f011 fa02 bl 8014ddc ssd1306_SetCursor(32, 48); - 800306e: 2130 movs r1, #48 ; 0x30 - 8003070: 2020 movs r0, #32 - 8003072: f7ff f971 bl 8002358 + 80039d8: 2130 movs r1, #48 ; 0x30 + 80039da: 2020 movs r0, #32 + 80039dc: f7fe ffea bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8003076: 4aa0 ldr r2, [pc, #640] ; (80032f8 ) - 8003078: 2301 movs r3, #1 - 800307a: ca06 ldmia r2, {r1, r2} - 800307c: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 8003080: f7ff f944 bl 800230c + 80039e0: 4a73 ldr r2, [pc, #460] ; (8003bb0 ) + 80039e2: 2301 movs r3, #1 + 80039e4: ca06 ldmia r2, {r1, r2} + 80039e6: 6b78 ldr r0, [r7, #52] ; 0x34 + 80039e8: f7fe ffbe bl 8002968 snprintf(str,15, "%0.1fhpa",1000*expf((-0.0001148)*(myData.altitude))); - 8003084: 4b9a ldr r3, [pc, #616] ; (80032f0 ) - 8003086: 69db ldr r3, [r3, #28] - 8003088: 4618 mov r0, r3 - 800308a: f7fd fa5d bl 8000548 <__aeabi_f2d> - 800308e: a396 add r3, pc, #600 ; (adr r3, 80032e8 ) - 8003090: e9d3 2300 ldrd r2, r3, [r3] - 8003094: f7fd fab0 bl 80005f8 <__aeabi_dmul> - 8003098: 4602 mov r2, r0 - 800309a: 460b mov r3, r1 - 800309c: 4610 mov r0, r2 - 800309e: 4619 mov r1, r3 - 80030a0: f7fd fda2 bl 8000be8 <__aeabi_d2f> - 80030a4: 4603 mov r3, r0 - 80030a6: ee00 3a10 vmov s0, r3 - 80030aa: f012 faed bl 8015688 - 80030ae: eef0 7a40 vmov.f32 s15, s0 - 80030b2: ed9f 7a94 vldr s14, [pc, #592] ; 8003304 - 80030b6: ee67 7a87 vmul.f32 s15, s15, s14 - 80030ba: ee17 0a90 vmov r0, s15 - 80030be: f7fd fa43 bl 8000548 <__aeabi_f2d> - 80030c2: 4602 mov r2, r0 - 80030c4: 460b mov r3, r1 - 80030c6: e9cd 2300 strd r2, r3, [sp] - 80030ca: 4a8f ldr r2, [pc, #572] ; (8003308 ) - 80030cc: 210f movs r1, #15 - 80030ce: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 80030d2: f00f fc2b bl 801292c + 80039ec: 4b75 ldr r3, [pc, #468] ; (8003bc4 ) + 80039ee: 69db ldr r3, [r3, #28] + 80039f0: 4618 mov r0, r3 + 80039f2: f7fc fda9 bl 8000548 <__aeabi_f2d> + 80039f6: a36c add r3, pc, #432 ; (adr r3, 8003ba8 ) + 80039f8: e9d3 2300 ldrd r2, r3, [r3] + 80039fc: f7fc fdfc bl 80005f8 <__aeabi_dmul> + 8003a00: 4602 mov r2, r0 + 8003a02: 460b mov r3, r1 + 8003a04: 4610 mov r0, r2 + 8003a06: 4619 mov r1, r3 + 8003a08: f7fd f8ee bl 8000be8 <__aeabi_d2f> + 8003a0c: 4603 mov r3, r0 + 8003a0e: ee00 3a10 vmov s0, r3 + 8003a12: f014 f891 bl 8017b38 + 8003a16: eef0 7a40 vmov.f32 s15, s0 + 8003a1a: ed9f 7a6e vldr s14, [pc, #440] ; 8003bd4 + 8003a1e: ee67 7a87 vmul.f32 s15, s15, s14 + 8003a22: ee17 0a90 vmov r0, s15 + 8003a26: f7fc fd8f bl 8000548 <__aeabi_f2d> + 8003a2a: 4602 mov r2, r0 + 8003a2c: 460b mov r3, r1 + 8003a2e: e9cd 2300 strd r2, r3, [sp] + 8003a32: 4a69 ldr r2, [pc, #420] ; (8003bd8 ) + 8003a34: 210f movs r1, #15 + 8003a36: 6b78 ldr r0, [r7, #52] ; 0x34 + 8003a38: f011 f9d0 bl 8014ddc ssd1306_SetCursor(32, 56); - 80030d6: 2138 movs r1, #56 ; 0x38 - 80030d8: 2020 movs r0, #32 - 80030da: f7ff f93d bl 8002358 + 8003a3c: 2138 movs r1, #56 ; 0x38 + 8003a3e: 2020 movs r0, #32 + 8003a40: f7fe ffb8 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 80030de: 4a86 ldr r2, [pc, #536] ; (80032f8 ) - 80030e0: 2301 movs r3, #1 - 80030e2: ca06 ldmia r2, {r1, r2} - 80030e4: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 80030e8: f7ff f910 bl 800230c + 8003a44: 4a5a ldr r2, [pc, #360] ; (8003bb0 ) + 8003a46: 2301 movs r3, #1 + 8003a48: ca06 ldmia r2, {r1, r2} + 8003a4a: 6b78 ldr r0, [r7, #52] ; 0x34 + 8003a4c: f7fe ff8c bl 8002968 free(str); - 80030ec: f8d7 0088 ldr.w r0, [r7, #136] ; 0x88 - 80030f0: f00d fd28 bl 8010b44 - 80030f4: e01d b.n 8003132 + 8003a50: 6b78 ldr r0, [r7, #52] ; 0x34 + 8003a52: f00f facf bl 8012ff4 + 8003a56: e01b b.n 8003a90 } else{ //if the GPS doesn't have a fix, print a message char *str = (char*)malloc(sizeof(char)*20); - 80030f6: 2014 movs r0, #20 - 80030f8: f00d fd1c bl 8010b34 - 80030fc: 4603 mov r3, r0 - 80030fe: f8c7 308c str.w r3, [r7, #140] ; 0x8c + 8003a58: 2014 movs r0, #20 + 8003a5a: f00f fac3 bl 8012fe4 + 8003a5e: 4603 mov r3, r0 + 8003a60: 63bb str r3, [r7, #56] ; 0x38 ssd1306_SetCursor(32, 32); - 8003102: 2120 movs r1, #32 - 8003104: 2020 movs r0, #32 - 8003106: f7ff f927 bl 8002358 + 8003a62: 2120 movs r1, #32 + 8003a64: 2020 movs r0, #32 + 8003a66: f7fe ffa5 bl 80029b4 ssd1306_WriteString("Pos4", Font_6x8, White); - 800310a: 4a7b ldr r2, [pc, #492] ; (80032f8 ) - 800310c: 2301 movs r3, #1 - 800310e: ca06 ldmia r2, {r1, r2} - 8003110: 487e ldr r0, [pc, #504] ; (800330c ) - 8003112: f7ff f8fb bl 800230c + 8003a6a: 4a51 ldr r2, [pc, #324] ; (8003bb0 ) + 8003a6c: 2301 movs r3, #1 + 8003a6e: ca06 ldmia r2, {r1, r2} + 8003a70: 485a ldr r0, [pc, #360] ; (8003bdc ) + 8003a72: f7fe ff79 bl 8002968 ssd1306_SetCursor(32, 44); - 8003116: 212c movs r1, #44 ; 0x2c - 8003118: 2020 movs r0, #32 - 800311a: f7ff f91d bl 8002358 + 8003a76: 212c movs r1, #44 ; 0x2c + 8003a78: 2020 movs r0, #32 + 8003a7a: f7fe ff9b bl 80029b4 ssd1306_WriteString("Wait GPS", Font_6x8, White); - 800311e: 4a76 ldr r2, [pc, #472] ; (80032f8 ) - 8003120: 2301 movs r3, #1 - 8003122: ca06 ldmia r2, {r1, r2} - 8003124: 487a ldr r0, [pc, #488] ; (8003310 ) - 8003126: f7ff f8f1 bl 800230c + 8003a7e: 4a4c ldr r2, [pc, #304] ; (8003bb0 ) + 8003a80: 2301 movs r3, #1 + 8003a82: ca06 ldmia r2, {r1, r2} + 8003a84: 484c ldr r0, [pc, #304] ; (8003bb8 ) + 8003a86: f7fe ff6f bl 8002968 free(str); - 800312a: f8d7 008c ldr.w r0, [r7, #140] ; 0x8c - 800312e: f00d fd09 bl 8010b44 + 8003a8a: 6bb8 ldr r0, [r7, #56] ; 0x38 + 8003a8c: f00f fab2 bl 8012ff4 } if(BTN_B>=1){ - 8003132: 4b78 ldr r3, [pc, #480] ; (8003314 ) - 8003134: 681b ldr r3, [r3, #0] - 8003136: 2b00 cmp r3, #0 - 8003138: dd1b ble.n 8003172 + 8003a90: 4b4a ldr r3, [pc, #296] ; (8003bbc ) + 8003a92: 681b ldr r3, [r3, #0] + 8003a94: 2b00 cmp r3, #0 + 8003a96: dd1b ble.n 8003ad0 posstate--; - 800313a: 4b77 ldr r3, [pc, #476] ; (8003318 ) - 800313c: 781b ldrb r3, [r3, #0] - 800313e: 3b01 subs r3, #1 - 8003140: b2da uxtb r2, r3 - 8003142: 4b75 ldr r3, [pc, #468] ; (8003318 ) - 8003144: 701a strb r2, [r3, #0] + 8003a98: 4b49 ldr r3, [pc, #292] ; (8003bc0 ) + 8003a9a: 781b ldrb r3, [r3, #0] + 8003a9c: 3b01 subs r3, #1 + 8003a9e: b2da uxtb r2, r3 + 8003aa0: 4b47 ldr r3, [pc, #284] ; (8003bc0 ) + 8003aa2: 701a strb r2, [r3, #0] posstate--; - 8003146: 4b74 ldr r3, [pc, #464] ; (8003318 ) - 8003148: 781b ldrb r3, [r3, #0] - 800314a: 3b01 subs r3, #1 - 800314c: b2da uxtb r2, r3 - 800314e: 4b72 ldr r3, [pc, #456] ; (8003318 ) - 8003150: 701a strb r2, [r3, #0] + 8003aa4: 4b46 ldr r3, [pc, #280] ; (8003bc0 ) + 8003aa6: 781b ldrb r3, [r3, #0] + 8003aa8: 3b01 subs r3, #1 + 8003aaa: b2da uxtb r2, r3 + 8003aac: 4b44 ldr r3, [pc, #272] ; (8003bc0 ) + 8003aae: 701a strb r2, [r3, #0] posstate--; - 8003152: 4b71 ldr r3, [pc, #452] ; (8003318 ) - 8003154: 781b ldrb r3, [r3, #0] - 8003156: 3b01 subs r3, #1 - 8003158: b2da uxtb r2, r3 - 800315a: 4b6f ldr r3, [pc, #444] ; (8003318 ) - 800315c: 701a strb r2, [r3, #0] + 8003ab0: 4b43 ldr r3, [pc, #268] ; (8003bc0 ) + 8003ab2: 781b ldrb r3, [r3, #0] + 8003ab4: 3b01 subs r3, #1 + 8003ab6: b2da uxtb r2, r3 + 8003ab8: 4b41 ldr r3, [pc, #260] ; (8003bc0 ) + 8003aba: 701a strb r2, [r3, #0] BTN_B=0; - 800315e: 4b6d ldr r3, [pc, #436] ; (8003314 ) - 8003160: 2200 movs r2, #0 - 8003162: 601a str r2, [r3, #0] + 8003abc: 4b3f ldr r3, [pc, #252] ; (8003bbc ) + 8003abe: 2200 movs r2, #0 + 8003ac0: 601a str r2, [r3, #0] } break; - 8003164: e005 b.n 8003172 + 8003ac2: e005 b.n 8003ad0 break; - 8003166: bf00 nop - 8003168: e004 b.n 8003174 + 8003ac4: bf00 nop + 8003ac6: e004 b.n 8003ad2 break; - 800316a: bf00 nop - 800316c: e002 b.n 8003174 + 8003ac8: bf00 nop + 8003aca: e002 b.n 8003ad2 break; - 800316e: bf00 nop - 8003170: e000 b.n 8003174 + 8003acc: bf00 nop + 8003ace: e000 b.n 8003ad2 break; - 8003172: bf00 nop + 8003ad0: bf00 nop } if(BTN_A>=1){ - 8003174: 4b69 ldr r3, [pc, #420] ; (800331c ) - 8003176: 681b ldr r3, [r3, #0] - 8003178: 2b00 cmp r3, #0 - 800317a: f340 85e8 ble.w 8003d4e + 8003ad2: 4b43 ldr r3, [pc, #268] ; (8003be0 ) + 8003ad4: 681b ldr r3, [r3, #0] + 8003ad6: 2b00 cmp r3, #0 + 8003ad8: f340 8786 ble.w 80049e8 state++; - 800317e: 4b68 ldr r3, [pc, #416] ; (8003320 ) - 8003180: 781b ldrb r3, [r3, #0] - 8003182: 3301 adds r3, #1 - 8003184: b2da uxtb r2, r3 - 8003186: 4b66 ldr r3, [pc, #408] ; (8003320 ) - 8003188: 701a strb r2, [r3, #0] + 8003adc: 4b41 ldr r3, [pc, #260] ; (8003be4 ) + 8003ade: 781b ldrb r3, [r3, #0] + 8003ae0: 3301 adds r3, #1 + 8003ae2: b2da uxtb r2, r3 + 8003ae4: 4b3f ldr r3, [pc, #252] ; (8003be4 ) + 8003ae6: 701a strb r2, [r3, #0] BTN_A=0; - 800318a: 4b64 ldr r3, [pc, #400] ; (800331c ) - 800318c: 2200 movs r2, #0 - 800318e: 601a str r2, [r3, #0] + 8003ae8: 4b3d ldr r3, [pc, #244] ; (8003be0 ) + 8003aea: 2200 movs r2, #0 + 8003aec: 601a str r2, [r3, #0] + BTN_B=0; + 8003aee: 4b33 ldr r3, [pc, #204] ; (8003bbc ) + 8003af0: 2200 movs r2, #0 + 8003af2: 601a str r2, [r3, #0] + + } break; - 8003190: f000 bddd b.w 8003d4e + 8003af4: f000 bf78 b.w 80049e8 case STATE_HEURE: ssd1306_Fill(Black); - 8003194: 2000 movs r0, #0 - 8003196: f7fe ff9d bl 80020d4 + 8003af8: 2000 movs r0, #0 + 8003afa: f7fe fe19 bl 8002730 nmea_parse(&myData, DataBuffer); - 800319a: 4962 ldr r1, [pc, #392] ; (8003324 ) - 800319c: 4854 ldr r0, [pc, #336] ; (80032f0 ) - 800319e: f7fe fe45 bl 8001e2c + 8003afe: 493a ldr r1, [pc, #232] ; (8003be8 ) + 8003b00: 4830 ldr r0, [pc, #192] ; (8003bc4 ) + 8003b02: f7fe fa93 bl 800202c int heure=0; - 80031a2: 2300 movs r3, #0 - 80031a4: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 8003b06: 2300 movs r3, #0 + 8003b08: 65fb str r3, [r7, #92] ; 0x5c heure=(myData.lastMeasure[0]&0x0f)*10+(myData.lastMeasure[1]&0x0f); - 80031a8: 4b51 ldr r3, [pc, #324] ; (80032f0 ) - 80031aa: f893 302c ldrb.w r3, [r3, #44] ; 0x2c - 80031ae: f003 020f and.w r2, r3, #15 - 80031b2: 4613 mov r3, r2 - 80031b4: 009b lsls r3, r3, #2 - 80031b6: 4413 add r3, r2 - 80031b8: 005b lsls r3, r3, #1 - 80031ba: 461a mov r2, r3 - 80031bc: 4b4c ldr r3, [pc, #304] ; (80032f0 ) - 80031be: f893 302d ldrb.w r3, [r3, #45] ; 0x2d - 80031c2: f003 030f and.w r3, r3, #15 - 80031c6: 4413 add r3, r2 - 80031c8: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 8003b0a: 4b2e ldr r3, [pc, #184] ; (8003bc4 ) + 8003b0c: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8003b10: f003 020f and.w r2, r3, #15 + 8003b14: 4613 mov r3, r2 + 8003b16: 009b lsls r3, r3, #2 + 8003b18: 4413 add r3, r2 + 8003b1a: 005b lsls r3, r3, #1 + 8003b1c: 461a mov r2, r3 + 8003b1e: 4b29 ldr r3, [pc, #164] ; (8003bc4 ) + 8003b20: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8003b24: f003 030f and.w r3, r3, #15 + 8003b28: 4413 add r3, r2 + 8003b2a: 65fb str r3, [r7, #92] ; 0x5c if((heure+2)>=24){ - 80031cc: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 80031d0: 2b15 cmp r3, #21 - 80031d2: dd05 ble.n 80031e0 + 8003b2c: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003b2e: 2b15 cmp r3, #21 + 8003b30: dd03 ble.n 8003b3a heure=heure-22; - 80031d4: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 80031d8: 3b16 subs r3, #22 - 80031da: f8c7 30ac str.w r3, [r7, #172] ; 0xac - 80031de: e004 b.n 80031ea + 8003b32: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003b34: 3b16 subs r3, #22 + 8003b36: 65fb str r3, [r7, #92] ; 0x5c + 8003b38: e002 b.n 8003b40 } else{ heure=heure+2; - 80031e0: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 80031e4: 3302 adds r3, #2 - 80031e6: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 8003b3a: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003b3c: 3302 adds r3, #2 + 8003b3e: 65fb str r3, [r7, #92] ; 0x5c } if(myData.fix == 1){ - 80031ea: 4b41 ldr r3, [pc, #260] ; (80032f0 ) - 80031ec: 6a9b ldr r3, [r3, #40] ; 0x28 - 80031ee: 2b01 cmp r3, #1 - 80031f0: f040 82f9 bne.w 80037e6 + 8003b40: 4b20 ldr r3, [pc, #128] ; (8003bc4 ) + 8003b42: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003b44: 2b01 cmp r3, #1 + 8003b46: f040 82e3 bne.w 8004110 switch(hrstate){ - 80031f4: 4b4c ldr r3, [pc, #304] ; (8003328 ) - 80031f6: 781b ldrb r3, [r3, #0] - 80031f8: 2b00 cmp r3, #0 - 80031fa: d003 beq.n 8003204 - 80031fc: 2b01 cmp r3, #1 - 80031fe: f000 809f beq.w 8003340 - 8003202: e308 b.n 8003816 + 8003b4a: 4b28 ldr r3, [pc, #160] ; (8003bec ) + 8003b4c: 781b ldrb r3, [r3, #0] + 8003b4e: 2b00 cmp r3, #0 + 8003b50: d003 beq.n 8003b5a + 8003b52: 2b01 cmp r3, #1 + 8003b54: f000 808f beq.w 8003c76 + 8003b58: e2f0 b.n 800413c case STATE_DIGIT: char * str = (char*)malloc(sizeof(char)*20); - 8003204: 2014 movs r0, #20 - 8003206: f00d fc95 bl 8010b34 - 800320a: 4603 mov r3, r0 - 800320c: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 8003b5a: 2014 movs r0, #20 + 8003b5c: f00f fa42 bl 8012fe4 + 8003b60: 4603 mov r3, r0 + 8003b62: 63fb str r3, [r7, #60] ; 0x3c ssd1306_SetCursor(32, 32); - 8003210: 2120 movs r1, #32 - 8003212: 2020 movs r0, #32 - 8003214: f7ff f8a0 bl 8002358 + 8003b64: 2120 movs r1, #32 + 8003b66: 2020 movs r0, #32 + 8003b68: f7fe ff24 bl 80029b4 ssd1306_WriteString("hr GMT+2:", Font_6x8, White); - 8003218: 4a37 ldr r2, [pc, #220] ; (80032f8 ) - 800321a: 2301 movs r3, #1 - 800321c: ca06 ldmia r2, {r1, r2} - 800321e: 4843 ldr r0, [pc, #268] ; (800332c ) - 8003220: f7ff f874 bl 800230c + 8003b6c: 4a10 ldr r2, [pc, #64] ; (8003bb0 ) + 8003b6e: 2301 movs r3, #1 + 8003b70: ca06 ldmia r2, {r1, r2} + 8003b72: 481f ldr r0, [pc, #124] ; (8003bf0 ) + 8003b74: f7fe fef8 bl 8002968 ssd1306_SetCursor(34, 42); - 8003224: 212a movs r1, #42 ; 0x2a - 8003226: 2022 movs r0, #34 ; 0x22 - 8003228: f7ff f896 bl 8002358 + 8003b78: 212a movs r1, #42 ; 0x2a + 8003b7a: 2022 movs r0, #34 ; 0x22 + 8003b7c: f7fe ff1a bl 80029b4 if(heure>=10){ - 800322c: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 8003230: 2b09 cmp r3, #9 - 8003232: dd11 ble.n 8003258 + 8003b80: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003b82: 2b09 cmp r3, #9 + 8003b84: dd38 ble.n 8003bf8 snprintf(str,15, "%d:%c%c",heure,myData.lastMeasure[2],myData.lastMeasure[3]); - 8003234: 4b2e ldr r3, [pc, #184] ; (80032f0 ) - 8003236: f893 302e ldrb.w r3, [r3, #46] ; 0x2e - 800323a: 461a mov r2, r3 - 800323c: 4b2c ldr r3, [pc, #176] ; (80032f0 ) - 800323e: f893 302f ldrb.w r3, [r3, #47] ; 0x2f - 8003242: 9301 str r3, [sp, #4] - 8003244: 9200 str r2, [sp, #0] - 8003246: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800324a: 4a39 ldr r2, [pc, #228] ; (8003330 ) - 800324c: 210f movs r1, #15 - 800324e: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 8003252: f00f fb6b bl 801292c - 8003256: e010 b.n 800327a + 8003b86: 4b0f ldr r3, [pc, #60] ; (8003bc4 ) + 8003b88: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 8003b8c: 461a mov r2, r3 + 8003b8e: 4b0d ldr r3, [pc, #52] ; (8003bc4 ) + 8003b90: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 8003b94: 9301 str r3, [sp, #4] + 8003b96: 9200 str r2, [sp, #0] + 8003b98: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003b9a: 4a16 ldr r2, [pc, #88] ; (8003bf4 ) + 8003b9c: 210f movs r1, #15 + 8003b9e: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003ba0: f011 f91c bl 8014ddc + 8003ba4: e037 b.n 8003c16 + 8003ba6: bf00 nop + 8003ba8: fb798882 .word 0xfb798882 + 8003bac: bf1e1818 .word 0xbf1e1818 + 8003bb0: 20000008 .word 0x20000008 + 8003bb4: 08018e94 .word 0x08018e94 + 8003bb8: 08018e24 .word 0x08018e24 + 8003bbc: 200006f4 .word 0x200006f4 + 8003bc0: 200006fb .word 0x200006fb + 8003bc4: 200006b0 .word 0x200006b0 + 8003bc8: 08018e9c .word 0x08018e9c + 8003bcc: 08018ea8 .word 0x08018ea8 + 8003bd0: 08018eb0 .word 0x08018eb0 + 8003bd4: 447a0000 .word 0x447a0000 + 8003bd8: 08018ebc .word 0x08018ebc + 8003bdc: 08018ec8 .word 0x08018ec8 + 8003be0: 200006f0 .word 0x200006f0 + 8003be4: 200006f8 .word 0x200006f8 + 8003be8: 200004ac .word 0x200004ac + 8003bec: 200006f9 .word 0x200006f9 + 8003bf0: 08018ed0 .word 0x08018ed0 + 8003bf4: 08018edc .word 0x08018edc } else{ snprintf(str,15, "0%d:%c%c",heure,myData.lastMeasure[2],myData.lastMeasure[3]); - 8003258: 4b25 ldr r3, [pc, #148] ; (80032f0 ) - 800325a: f893 302e ldrb.w r3, [r3, #46] ; 0x2e - 800325e: 461a mov r2, r3 - 8003260: 4b23 ldr r3, [pc, #140] ; (80032f0 ) - 8003262: f893 302f ldrb.w r3, [r3, #47] ; 0x2f - 8003266: 9301 str r3, [sp, #4] - 8003268: 9200 str r2, [sp, #0] - 800326a: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800326e: 4a31 ldr r2, [pc, #196] ; (8003334 ) - 8003270: 210f movs r1, #15 - 8003272: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 8003276: f00f fb59 bl 801292c + 8003bf8: 4bb5 ldr r3, [pc, #724] ; (8003ed0 ) + 8003bfa: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 8003bfe: 461a mov r2, r3 + 8003c00: 4bb3 ldr r3, [pc, #716] ; (8003ed0 ) + 8003c02: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 8003c06: 9301 str r3, [sp, #4] + 8003c08: 9200 str r2, [sp, #0] + 8003c0a: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003c0c: 4ab1 ldr r2, [pc, #708] ; (8003ed4 ) + 8003c0e: 210f movs r1, #15 + 8003c10: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003c12: f011 f8e3 bl 8014ddc } ssd1306_WriteString(str, Font_7x10, White); - 800327a: 4a2f ldr r2, [pc, #188] ; (8003338 ) - 800327c: 2301 movs r3, #1 - 800327e: ca06 ldmia r2, {r1, r2} - 8003280: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 8003284: f7ff f842 bl 800230c + 8003c16: 4ab0 ldr r2, [pc, #704] ; (8003ed8 ) + 8003c18: 2301 movs r3, #1 + 8003c1a: ca06 ldmia r2, {r1, r2} + 8003c1c: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003c1e: f7fe fea3 bl 8002968 ssd1306_SetCursor(34, 52); - 8003288: 2134 movs r1, #52 ; 0x34 - 800328a: 2022 movs r0, #34 ; 0x22 - 800328c: f7ff f864 bl 8002358 + 8003c22: 2134 movs r1, #52 ; 0x34 + 8003c24: 2022 movs r0, #34 ; 0x22 + 8003c26: f7fe fec5 bl 80029b4 snprintf(str,15, "%c%c sec",myData.lastMeasure[4],myData.lastMeasure[5]); - 8003290: 4b17 ldr r3, [pc, #92] ; (80032f0 ) - 8003292: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 - 8003296: 461a mov r2, r3 - 8003298: 4b15 ldr r3, [pc, #84] ; (80032f0 ) - 800329a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 - 800329e: 9300 str r3, [sp, #0] - 80032a0: 4613 mov r3, r2 - 80032a2: 4a26 ldr r2, [pc, #152] ; (800333c ) - 80032a4: 210f movs r1, #15 - 80032a6: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 80032aa: f00f fb3f bl 801292c + 8003c2a: 4ba9 ldr r3, [pc, #676] ; (8003ed0 ) + 8003c2c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8003c30: 461a mov r2, r3 + 8003c32: 4ba7 ldr r3, [pc, #668] ; (8003ed0 ) + 8003c34: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8003c38: 9300 str r3, [sp, #0] + 8003c3a: 4613 mov r3, r2 + 8003c3c: 4aa7 ldr r2, [pc, #668] ; (8003edc ) + 8003c3e: 210f movs r1, #15 + 8003c40: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003c42: f011 f8cb bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 80032ae: 4a12 ldr r2, [pc, #72] ; (80032f8 ) - 80032b0: 2301 movs r3, #1 - 80032b2: ca06 ldmia r2, {r1, r2} - 80032b4: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 80032b8: f7ff f828 bl 800230c + 8003c46: 4aa6 ldr r2, [pc, #664] ; (8003ee0 ) + 8003c48: 2301 movs r3, #1 + 8003c4a: ca06 ldmia r2, {r1, r2} + 8003c4c: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003c4e: f7fe fe8b bl 8002968 free(str); - 80032bc: f8d7 0090 ldr.w r0, [r7, #144] ; 0x90 - 80032c0: f00d fc40 bl 8010b44 + 8003c52: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8003c54: f00f f9ce bl 8012ff4 if(BTN_B>=1){ - 80032c4: 4b13 ldr r3, [pc, #76] ; (8003314 ) - 80032c6: 681b ldr r3, [r3, #0] - 80032c8: 2b00 cmp r3, #0 - 80032ca: f340 82a1 ble.w 8003810 + 8003c58: 4ba2 ldr r3, [pc, #648] ; (8003ee4 ) + 8003c5a: 681b ldr r3, [r3, #0] + 8003c5c: 2b00 cmp r3, #0 + 8003c5e: f340 826a ble.w 8004136 hrstate++; - 80032ce: 4b16 ldr r3, [pc, #88] ; (8003328 ) - 80032d0: 781b ldrb r3, [r3, #0] - 80032d2: 3301 adds r3, #1 - 80032d4: b2da uxtb r2, r3 - 80032d6: 4b14 ldr r3, [pc, #80] ; (8003328 ) - 80032d8: 701a strb r2, [r3, #0] + 8003c62: 4ba1 ldr r3, [pc, #644] ; (8003ee8 ) + 8003c64: 781b ldrb r3, [r3, #0] + 8003c66: 3301 adds r3, #1 + 8003c68: b2da uxtb r2, r3 + 8003c6a: 4b9f ldr r3, [pc, #636] ; (8003ee8 ) + 8003c6c: 701a strb r2, [r3, #0] BTN_B=0; - 80032da: 4b0e ldr r3, [pc, #56] ; (8003314 ) - 80032dc: 2200 movs r2, #0 - 80032de: 601a str r2, [r3, #0] + 8003c6e: 4b9d ldr r3, [pc, #628] ; (8003ee4 ) + 8003c70: 2200 movs r2, #0 + 8003c72: 601a str r2, [r3, #0] } break; - 80032e0: e296 b.n 8003810 - 80032e2: bf00 nop - 80032e4: f3af 8000 nop.w - 80032e8: fb798882 .word 0xfb798882 - 80032ec: bf1e1818 .word 0xbf1e1818 - 80032f0: 200007e0 .word 0x200007e0 - 80032f4: 080169a8 .word 0x080169a8 - 80032f8: 20000008 .word 0x20000008 - 80032fc: 080169b4 .word 0x080169b4 - 8003300: 080169bc .word 0x080169bc - 8003304: 447a0000 .word 0x447a0000 - 8003308: 080169c8 .word 0x080169c8 - 800330c: 080169d4 .word 0x080169d4 - 8003310: 0801692c .word 0x0801692c - 8003314: 20000824 .word 0x20000824 - 8003318: 2000082b .word 0x2000082b - 800331c: 20000820 .word 0x20000820 - 8003320: 20000828 .word 0x20000828 - 8003324: 200005e0 .word 0x200005e0 - 8003328: 20000829 .word 0x20000829 - 800332c: 080169dc .word 0x080169dc - 8003330: 080169e8 .word 0x080169e8 - 8003334: 080169f0 .word 0x080169f0 - 8003338: 20000010 .word 0x20000010 - 800333c: 080169fc .word 0x080169fc + 8003c74: e25f b.n 8004136 case STATE_OLD: if(heure>12){ - 8003340: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 8003344: 2b0c cmp r3, #12 - 8003346: dd04 ble.n 8003352 + 8003c76: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003c78: 2b0c cmp r3, #12 + 8003c7a: dd02 ble.n 8003c82 heure=heure-12; - 8003348: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800334c: 3b0c subs r3, #12 - 800334e: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 8003c7c: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003c7e: 3b0c subs r3, #12 + 8003c80: 65fb str r3, [r7, #92] ; 0x5c } int minute=0; - 8003352: 2300 movs r3, #0 - 8003354: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 8003c82: 2300 movs r3, #0 + 8003c84: 643b str r3, [r7, #64] ; 0x40 minute=(myData.lastMeasure[2]&0x0f)*10+(myData.lastMeasure[3]&0x0f); - 8003358: 4b95 ldr r3, [pc, #596] ; (80035b0 ) - 800335a: f893 302e ldrb.w r3, [r3, #46] ; 0x2e - 800335e: f003 020f and.w r2, r3, #15 - 8003362: 4613 mov r3, r2 - 8003364: 009b lsls r3, r3, #2 - 8003366: 4413 add r3, r2 - 8003368: 005b lsls r3, r3, #1 - 800336a: 461a mov r2, r3 - 800336c: 4b90 ldr r3, [pc, #576] ; (80035b0 ) - 800336e: f893 302f ldrb.w r3, [r3, #47] ; 0x2f - 8003372: f003 030f and.w r3, r3, #15 - 8003376: 4413 add r3, r2 - 8003378: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 8003c86: 4b92 ldr r3, [pc, #584] ; (8003ed0 ) + 8003c88: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 8003c8c: f003 020f and.w r2, r3, #15 + 8003c90: 4613 mov r3, r2 + 8003c92: 009b lsls r3, r3, #2 + 8003c94: 4413 add r3, r2 + 8003c96: 005b lsls r3, r3, #1 + 8003c98: 461a mov r2, r3 + 8003c9a: 4b8d ldr r3, [pc, #564] ; (8003ed0 ) + 8003c9c: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 8003ca0: f003 030f and.w r3, r3, #15 + 8003ca4: 4413 add r3, r2 + 8003ca6: 643b str r3, [r7, #64] ; 0x40 ssd1306_DrawCircle(64, 48, 12, White); - 800337c: 2301 movs r3, #1 - 800337e: 220c movs r2, #12 - 8003380: 2130 movs r1, #48 ; 0x30 - 8003382: 2040 movs r0, #64 ; 0x40 - 8003384: f7ff f86c bl 8002460 + 8003ca8: 2301 movs r3, #1 + 8003caa: 220c movs r2, #12 + 8003cac: 2130 movs r1, #48 ; 0x30 + 8003cae: 2040 movs r0, #64 ; 0x40 + 8003cb0: f7fe ff04 bl 8002abc ssd1306_Line(64,48,64+floor(6*cos((3-heure)*M_PI/6)),48-floor(6*sin((3-heure)*M_PI/6)),White); - 8003388: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800338c: f1c3 0303 rsb r3, r3, #3 - 8003390: 4618 mov r0, r3 - 8003392: f7fd f8c7 bl 8000524 <__aeabi_i2d> - 8003396: a384 add r3, pc, #528 ; (adr r3, 80035a8 ) - 8003398: e9d3 2300 ldrd r2, r3, [r3] - 800339c: f7fd f92c bl 80005f8 <__aeabi_dmul> - 80033a0: 4602 mov r2, r0 - 80033a2: 460b mov r3, r1 - 80033a4: 4610 mov r0, r2 - 80033a6: 4619 mov r1, r3 - 80033a8: f04f 0200 mov.w r2, #0 - 80033ac: 4b81 ldr r3, [pc, #516] ; (80035b4 ) - 80033ae: f7fd fa4d bl 800084c <__aeabi_ddiv> - 80033b2: 4602 mov r2, r0 - 80033b4: 460b mov r3, r1 - 80033b6: ec43 2b17 vmov d7, r2, r3 - 80033ba: eeb0 0a47 vmov.f32 s0, s14 - 80033be: eef0 0a67 vmov.f32 s1, s15 - 80033c2: f012 f8b5 bl 8015530 - 80033c6: ec51 0b10 vmov r0, r1, d0 - 80033ca: f04f 0200 mov.w r2, #0 - 80033ce: 4b79 ldr r3, [pc, #484] ; (80035b4 ) - 80033d0: f7fd f912 bl 80005f8 <__aeabi_dmul> - 80033d4: 4602 mov r2, r0 - 80033d6: 460b mov r3, r1 - 80033d8: ec43 2b17 vmov d7, r2, r3 - 80033dc: eeb0 0a47 vmov.f32 s0, s14 - 80033e0: eef0 0a67 vmov.f32 s1, s15 - 80033e4: f012 f994 bl 8015710 - 80033e8: ec51 0b10 vmov r0, r1, d0 - 80033ec: f04f 0200 mov.w r2, #0 - 80033f0: 4b71 ldr r3, [pc, #452] ; (80035b8 ) - 80033f2: f7fc ff4b bl 800028c <__adddf3> - 80033f6: 4602 mov r2, r0 - 80033f8: 460b mov r3, r1 - 80033fa: 4610 mov r0, r2 - 80033fc: 4619 mov r1, r3 - 80033fe: f7fd fbd3 bl 8000ba8 <__aeabi_d2uiz> - 8003402: 4603 mov r3, r0 - 8003404: b2dc uxtb r4, r3 - 8003406: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800340a: f1c3 0303 rsb r3, r3, #3 - 800340e: 4618 mov r0, r3 - 8003410: f7fd f888 bl 8000524 <__aeabi_i2d> - 8003414: a364 add r3, pc, #400 ; (adr r3, 80035a8 ) - 8003416: e9d3 2300 ldrd r2, r3, [r3] - 800341a: f7fd f8ed bl 80005f8 <__aeabi_dmul> - 800341e: 4602 mov r2, r0 - 8003420: 460b mov r3, r1 - 8003422: 4610 mov r0, r2 - 8003424: 4619 mov r1, r3 - 8003426: f04f 0200 mov.w r2, #0 - 800342a: 4b62 ldr r3, [pc, #392] ; (80035b4 ) - 800342c: f7fd fa0e bl 800084c <__aeabi_ddiv> - 8003430: 4602 mov r2, r0 - 8003432: 460b mov r3, r1 - 8003434: ec43 2b17 vmov d7, r2, r3 - 8003438: eeb0 0a47 vmov.f32 s0, s14 - 800343c: eef0 0a67 vmov.f32 s1, s15 - 8003440: f012 f8ca bl 80155d8 - 8003444: ec51 0b10 vmov r0, r1, d0 - 8003448: f04f 0200 mov.w r2, #0 - 800344c: 4b59 ldr r3, [pc, #356] ; (80035b4 ) - 800344e: f7fd f8d3 bl 80005f8 <__aeabi_dmul> - 8003452: 4602 mov r2, r0 - 8003454: 460b mov r3, r1 - 8003456: ec43 2b17 vmov d7, r2, r3 - 800345a: eeb0 0a47 vmov.f32 s0, s14 - 800345e: eef0 0a67 vmov.f32 s1, s15 - 8003462: f012 f955 bl 8015710 - 8003466: ec53 2b10 vmov r2, r3, d0 - 800346a: f04f 0000 mov.w r0, #0 - 800346e: 4953 ldr r1, [pc, #332] ; (80035bc ) - 8003470: f7fc ff0a bl 8000288 <__aeabi_dsub> - 8003474: 4602 mov r2, r0 - 8003476: 460b mov r3, r1 - 8003478: 4610 mov r0, r2 - 800347a: 4619 mov r1, r3 - 800347c: f7fd fb94 bl 8000ba8 <__aeabi_d2uiz> - 8003480: 4603 mov r3, r0 - 8003482: b2db uxtb r3, r3 - 8003484: 2201 movs r2, #1 - 8003486: 9200 str r2, [sp, #0] - 8003488: 4622 mov r2, r4 - 800348a: 2130 movs r1, #48 ; 0x30 - 800348c: 2040 movs r0, #64 ; 0x40 - 800348e: f7fe ff7b bl 8002388 + 8003cb4: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003cb6: f1c3 0303 rsb r3, r3, #3 + 8003cba: 4618 mov r0, r3 + 8003cbc: f7fc fc32 bl 8000524 <__aeabi_i2d> + 8003cc0: a381 add r3, pc, #516 ; (adr r3, 8003ec8 ) + 8003cc2: e9d3 2300 ldrd r2, r3, [r3] + 8003cc6: f7fc fc97 bl 80005f8 <__aeabi_dmul> + 8003cca: 4602 mov r2, r0 + 8003ccc: 460b mov r3, r1 + 8003cce: 4610 mov r0, r2 + 8003cd0: 4619 mov r1, r3 + 8003cd2: f04f 0200 mov.w r2, #0 + 8003cd6: 4b85 ldr r3, [pc, #532] ; (8003eec ) + 8003cd8: f7fc fdb8 bl 800084c <__aeabi_ddiv> + 8003cdc: 4602 mov r2, r0 + 8003cde: 460b mov r3, r1 + 8003ce0: ec43 2b17 vmov d7, r2, r3 + 8003ce4: eeb0 0a47 vmov.f32 s0, s14 + 8003ce8: eef0 0a67 vmov.f32 s1, s15 + 8003cec: f013 fe78 bl 80179e0 + 8003cf0: ec51 0b10 vmov r0, r1, d0 + 8003cf4: f04f 0200 mov.w r2, #0 + 8003cf8: 4b7c ldr r3, [pc, #496] ; (8003eec ) + 8003cfa: f7fc fc7d bl 80005f8 <__aeabi_dmul> + 8003cfe: 4602 mov r2, r0 + 8003d00: 460b mov r3, r1 + 8003d02: ec43 2b17 vmov d7, r2, r3 + 8003d06: eeb0 0a47 vmov.f32 s0, s14 + 8003d0a: eef0 0a67 vmov.f32 s1, s15 + 8003d0e: f013 ff57 bl 8017bc0 + 8003d12: ec51 0b10 vmov r0, r1, d0 + 8003d16: f04f 0200 mov.w r2, #0 + 8003d1a: 4b75 ldr r3, [pc, #468] ; (8003ef0 ) + 8003d1c: f7fc fab6 bl 800028c <__adddf3> + 8003d20: 4602 mov r2, r0 + 8003d22: 460b mov r3, r1 + 8003d24: 4610 mov r0, r2 + 8003d26: 4619 mov r1, r3 + 8003d28: f7fc ff3e bl 8000ba8 <__aeabi_d2uiz> + 8003d2c: 4603 mov r3, r0 + 8003d2e: b2dc uxtb r4, r3 + 8003d30: 6dfb ldr r3, [r7, #92] ; 0x5c + 8003d32: f1c3 0303 rsb r3, r3, #3 + 8003d36: 4618 mov r0, r3 + 8003d38: f7fc fbf4 bl 8000524 <__aeabi_i2d> + 8003d3c: a362 add r3, pc, #392 ; (adr r3, 8003ec8 ) + 8003d3e: e9d3 2300 ldrd r2, r3, [r3] + 8003d42: f7fc fc59 bl 80005f8 <__aeabi_dmul> + 8003d46: 4602 mov r2, r0 + 8003d48: 460b mov r3, r1 + 8003d4a: 4610 mov r0, r2 + 8003d4c: 4619 mov r1, r3 + 8003d4e: f04f 0200 mov.w r2, #0 + 8003d52: 4b66 ldr r3, [pc, #408] ; (8003eec ) + 8003d54: f7fc fd7a bl 800084c <__aeabi_ddiv> + 8003d58: 4602 mov r2, r0 + 8003d5a: 460b mov r3, r1 + 8003d5c: ec43 2b17 vmov d7, r2, r3 + 8003d60: eeb0 0a47 vmov.f32 s0, s14 + 8003d64: eef0 0a67 vmov.f32 s1, s15 + 8003d68: f013 fe8e bl 8017a88 + 8003d6c: ec51 0b10 vmov r0, r1, d0 + 8003d70: f04f 0200 mov.w r2, #0 + 8003d74: 4b5d ldr r3, [pc, #372] ; (8003eec ) + 8003d76: f7fc fc3f bl 80005f8 <__aeabi_dmul> + 8003d7a: 4602 mov r2, r0 + 8003d7c: 460b mov r3, r1 + 8003d7e: ec43 2b17 vmov d7, r2, r3 + 8003d82: eeb0 0a47 vmov.f32 s0, s14 + 8003d86: eef0 0a67 vmov.f32 s1, s15 + 8003d8a: f013 ff19 bl 8017bc0 + 8003d8e: ec53 2b10 vmov r2, r3, d0 + 8003d92: f04f 0000 mov.w r0, #0 + 8003d96: 4957 ldr r1, [pc, #348] ; (8003ef4 ) + 8003d98: f7fc fa76 bl 8000288 <__aeabi_dsub> + 8003d9c: 4602 mov r2, r0 + 8003d9e: 460b mov r3, r1 + 8003da0: 4610 mov r0, r2 + 8003da2: 4619 mov r1, r3 + 8003da4: f7fc ff00 bl 8000ba8 <__aeabi_d2uiz> + 8003da8: 4603 mov r3, r0 + 8003daa: b2db uxtb r3, r3 + 8003dac: 2201 movs r2, #1 + 8003dae: 9200 str r2, [sp, #0] + 8003db0: 4622 mov r2, r4 + 8003db2: 2130 movs r1, #48 ; 0x30 + 8003db4: 2040 movs r0, #64 ; 0x40 + 8003db6: f7fe fe15 bl 80029e4 ssd1306_Line(64,48,64+floor(12*cos((15-minute)*M_PI/30)),48-floor(12*sin((15-minute)*M_PI/30)),White); - 8003492: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 - 8003496: f1c3 030f rsb r3, r3, #15 - 800349a: 4618 mov r0, r3 - 800349c: f7fd f842 bl 8000524 <__aeabi_i2d> - 80034a0: a341 add r3, pc, #260 ; (adr r3, 80035a8 ) - 80034a2: e9d3 2300 ldrd r2, r3, [r3] - 80034a6: f7fd f8a7 bl 80005f8 <__aeabi_dmul> - 80034aa: 4602 mov r2, r0 - 80034ac: 460b mov r3, r1 - 80034ae: 4610 mov r0, r2 - 80034b0: 4619 mov r1, r3 - 80034b2: f04f 0200 mov.w r2, #0 - 80034b6: 4b42 ldr r3, [pc, #264] ; (80035c0 ) - 80034b8: f7fd f9c8 bl 800084c <__aeabi_ddiv> - 80034bc: 4602 mov r2, r0 - 80034be: 460b mov r3, r1 - 80034c0: ec43 2b17 vmov d7, r2, r3 - 80034c4: eeb0 0a47 vmov.f32 s0, s14 - 80034c8: eef0 0a67 vmov.f32 s1, s15 - 80034cc: f012 f830 bl 8015530 - 80034d0: ec51 0b10 vmov r0, r1, d0 - 80034d4: f04f 0200 mov.w r2, #0 - 80034d8: 4b3a ldr r3, [pc, #232] ; (80035c4 ) - 80034da: f7fd f88d bl 80005f8 <__aeabi_dmul> - 80034de: 4602 mov r2, r0 - 80034e0: 460b mov r3, r1 - 80034e2: ec43 2b17 vmov d7, r2, r3 - 80034e6: eeb0 0a47 vmov.f32 s0, s14 - 80034ea: eef0 0a67 vmov.f32 s1, s15 - 80034ee: f012 f90f bl 8015710 - 80034f2: ec51 0b10 vmov r0, r1, d0 - 80034f6: f04f 0200 mov.w r2, #0 - 80034fa: 4b2f ldr r3, [pc, #188] ; (80035b8 ) - 80034fc: f7fc fec6 bl 800028c <__adddf3> - 8003500: 4602 mov r2, r0 - 8003502: 460b mov r3, r1 - 8003504: 4610 mov r0, r2 - 8003506: 4619 mov r1, r3 - 8003508: f7fd fb4e bl 8000ba8 <__aeabi_d2uiz> - 800350c: 4603 mov r3, r0 - 800350e: b2dc uxtb r4, r3 - 8003510: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 - 8003514: f1c3 030f rsb r3, r3, #15 - 8003518: 4618 mov r0, r3 - 800351a: f7fd f803 bl 8000524 <__aeabi_i2d> - 800351e: a322 add r3, pc, #136 ; (adr r3, 80035a8 ) - 8003520: e9d3 2300 ldrd r2, r3, [r3] - 8003524: f7fd f868 bl 80005f8 <__aeabi_dmul> - 8003528: 4602 mov r2, r0 - 800352a: 460b mov r3, r1 - 800352c: 4610 mov r0, r2 - 800352e: 4619 mov r1, r3 - 8003530: f04f 0200 mov.w r2, #0 - 8003534: 4b22 ldr r3, [pc, #136] ; (80035c0 ) - 8003536: f7fd f989 bl 800084c <__aeabi_ddiv> - 800353a: 4602 mov r2, r0 - 800353c: 460b mov r3, r1 - 800353e: ec43 2b17 vmov d7, r2, r3 - 8003542: eeb0 0a47 vmov.f32 s0, s14 - 8003546: eef0 0a67 vmov.f32 s1, s15 - 800354a: f012 f845 bl 80155d8 - 800354e: ec51 0b10 vmov r0, r1, d0 - 8003552: f04f 0200 mov.w r2, #0 - 8003556: 4b1b ldr r3, [pc, #108] ; (80035c4 ) - 8003558: f7fd f84e bl 80005f8 <__aeabi_dmul> - 800355c: 4602 mov r2, r0 - 800355e: 460b mov r3, r1 - 8003560: ec43 2b17 vmov d7, r2, r3 - 8003564: eeb0 0a47 vmov.f32 s0, s14 - 8003568: eef0 0a67 vmov.f32 s1, s15 - 800356c: f012 f8d0 bl 8015710 - 8003570: ec53 2b10 vmov r2, r3, d0 - 8003574: f04f 0000 mov.w r0, #0 - 8003578: 4910 ldr r1, [pc, #64] ; (80035bc ) - 800357a: f7fc fe85 bl 8000288 <__aeabi_dsub> - 800357e: 4602 mov r2, r0 - 8003580: 460b mov r3, r1 - 8003582: 4610 mov r0, r2 - 8003584: 4619 mov r1, r3 - 8003586: f7fd fb0f bl 8000ba8 <__aeabi_d2uiz> - 800358a: 4603 mov r3, r0 - 800358c: b2db uxtb r3, r3 - 800358e: 2201 movs r2, #1 - 8003590: 9200 str r2, [sp, #0] - 8003592: 4622 mov r2, r4 - 8003594: 2130 movs r1, #48 ; 0x30 - 8003596: 2040 movs r0, #64 ; 0x40 - 8003598: f7fe fef6 bl 8002388 + 8003dba: 6c3b ldr r3, [r7, #64] ; 0x40 + 8003dbc: f1c3 030f rsb r3, r3, #15 + 8003dc0: 4618 mov r0, r3 + 8003dc2: f7fc fbaf bl 8000524 <__aeabi_i2d> + 8003dc6: a340 add r3, pc, #256 ; (adr r3, 8003ec8 ) + 8003dc8: e9d3 2300 ldrd r2, r3, [r3] + 8003dcc: f7fc fc14 bl 80005f8 <__aeabi_dmul> + 8003dd0: 4602 mov r2, r0 + 8003dd2: 460b mov r3, r1 + 8003dd4: 4610 mov r0, r2 + 8003dd6: 4619 mov r1, r3 + 8003dd8: f04f 0200 mov.w r2, #0 + 8003ddc: 4b46 ldr r3, [pc, #280] ; (8003ef8 ) + 8003dde: f7fc fd35 bl 800084c <__aeabi_ddiv> + 8003de2: 4602 mov r2, r0 + 8003de4: 460b mov r3, r1 + 8003de6: ec43 2b17 vmov d7, r2, r3 + 8003dea: eeb0 0a47 vmov.f32 s0, s14 + 8003dee: eef0 0a67 vmov.f32 s1, s15 + 8003df2: f013 fdf5 bl 80179e0 + 8003df6: ec51 0b10 vmov r0, r1, d0 + 8003dfa: f04f 0200 mov.w r2, #0 + 8003dfe: 4b3f ldr r3, [pc, #252] ; (8003efc ) + 8003e00: f7fc fbfa bl 80005f8 <__aeabi_dmul> + 8003e04: 4602 mov r2, r0 + 8003e06: 460b mov r3, r1 + 8003e08: ec43 2b17 vmov d7, r2, r3 + 8003e0c: eeb0 0a47 vmov.f32 s0, s14 + 8003e10: eef0 0a67 vmov.f32 s1, s15 + 8003e14: f013 fed4 bl 8017bc0 + 8003e18: ec51 0b10 vmov r0, r1, d0 + 8003e1c: f04f 0200 mov.w r2, #0 + 8003e20: 4b33 ldr r3, [pc, #204] ; (8003ef0 ) + 8003e22: f7fc fa33 bl 800028c <__adddf3> + 8003e26: 4602 mov r2, r0 + 8003e28: 460b mov r3, r1 + 8003e2a: 4610 mov r0, r2 + 8003e2c: 4619 mov r1, r3 + 8003e2e: f7fc febb bl 8000ba8 <__aeabi_d2uiz> + 8003e32: 4603 mov r3, r0 + 8003e34: b2dc uxtb r4, r3 + 8003e36: 6c3b ldr r3, [r7, #64] ; 0x40 + 8003e38: f1c3 030f rsb r3, r3, #15 + 8003e3c: 4618 mov r0, r3 + 8003e3e: f7fc fb71 bl 8000524 <__aeabi_i2d> + 8003e42: a321 add r3, pc, #132 ; (adr r3, 8003ec8 ) + 8003e44: e9d3 2300 ldrd r2, r3, [r3] + 8003e48: f7fc fbd6 bl 80005f8 <__aeabi_dmul> + 8003e4c: 4602 mov r2, r0 + 8003e4e: 460b mov r3, r1 + 8003e50: 4610 mov r0, r2 + 8003e52: 4619 mov r1, r3 + 8003e54: f04f 0200 mov.w r2, #0 + 8003e58: 4b27 ldr r3, [pc, #156] ; (8003ef8 ) + 8003e5a: f7fc fcf7 bl 800084c <__aeabi_ddiv> + 8003e5e: 4602 mov r2, r0 + 8003e60: 460b mov r3, r1 + 8003e62: ec43 2b17 vmov d7, r2, r3 + 8003e66: eeb0 0a47 vmov.f32 s0, s14 + 8003e6a: eef0 0a67 vmov.f32 s1, s15 + 8003e6e: f013 fe0b bl 8017a88 + 8003e72: ec51 0b10 vmov r0, r1, d0 + 8003e76: f04f 0200 mov.w r2, #0 + 8003e7a: 4b20 ldr r3, [pc, #128] ; (8003efc ) + 8003e7c: f7fc fbbc bl 80005f8 <__aeabi_dmul> + 8003e80: 4602 mov r2, r0 + 8003e82: 460b mov r3, r1 + 8003e84: ec43 2b17 vmov d7, r2, r3 + 8003e88: eeb0 0a47 vmov.f32 s0, s14 + 8003e8c: eef0 0a67 vmov.f32 s1, s15 + 8003e90: f013 fe96 bl 8017bc0 + 8003e94: ec53 2b10 vmov r2, r3, d0 + 8003e98: f04f 0000 mov.w r0, #0 + 8003e9c: 4915 ldr r1, [pc, #84] ; (8003ef4 ) + 8003e9e: f7fc f9f3 bl 8000288 <__aeabi_dsub> + 8003ea2: 4602 mov r2, r0 + 8003ea4: 460b mov r3, r1 + 8003ea6: 4610 mov r0, r2 + 8003ea8: 4619 mov r1, r3 + 8003eaa: f7fc fe7d bl 8000ba8 <__aeabi_d2uiz> + 8003eae: 4603 mov r3, r0 + 8003eb0: b2db uxtb r3, r3 + 8003eb2: 2201 movs r2, #1 + 8003eb4: 9200 str r2, [sp, #0] + 8003eb6: 4622 mov r2, r4 + 8003eb8: 2130 movs r1, #48 ; 0x30 + 8003eba: 2040 movs r0, #64 ; 0x40 + 8003ebc: f7fe fd92 bl 80029e4 for(int i=0;i<=12;i++){ - 800359c: 2300 movs r3, #0 - 800359e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 - 80035a2: e10d b.n 80037c0 - 80035a4: f3af 8000 nop.w - 80035a8: 54442d18 .word 0x54442d18 - 80035ac: 400921fb .word 0x400921fb - 80035b0: 200007e0 .word 0x200007e0 - 80035b4: 40180000 .word 0x40180000 - 80035b8: 40500000 .word 0x40500000 - 80035bc: 40480000 .word 0x40480000 - 80035c0: 403e0000 .word 0x403e0000 - 80035c4: 40280000 .word 0x40280000 + 8003ec0: 2300 movs r3, #0 + 8003ec2: 65bb str r3, [r7, #88] ; 0x58 + 8003ec4: e112 b.n 80040ec + 8003ec6: bf00 nop + 8003ec8: 54442d18 .word 0x54442d18 + 8003ecc: 400921fb .word 0x400921fb + 8003ed0: 200006b0 .word 0x200006b0 + 8003ed4: 08018ee4 .word 0x08018ee4 + 8003ed8: 20000010 .word 0x20000010 + 8003edc: 08018ef0 .word 0x08018ef0 + 8003ee0: 20000008 .word 0x20000008 + 8003ee4: 200006f4 .word 0x200006f4 + 8003ee8: 200006f9 .word 0x200006f9 + 8003eec: 40180000 .word 0x40180000 + 8003ef0: 40500000 .word 0x40500000 + 8003ef4: 40480000 .word 0x40480000 + 8003ef8: 403e0000 .word 0x403e0000 + 8003efc: 40280000 .word 0x40280000 ssd1306_Line(64+floor(10*cos((i)*M_PI/6)),48+floor(10*sin((i)*M_PI/6)),64+floor(12*cos((i)*M_PI/6)),48+floor(12*sin((i)*M_PI/6)),White); - 80035c8: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 - 80035cc: f7fc ffaa bl 8000524 <__aeabi_i2d> - 80035d0: a3c9 add r3, pc, #804 ; (adr r3, 80038f8 ) - 80035d2: e9d3 2300 ldrd r2, r3, [r3] - 80035d6: f7fd f80f bl 80005f8 <__aeabi_dmul> - 80035da: 4602 mov r2, r0 - 80035dc: 460b mov r3, r1 - 80035de: 4610 mov r0, r2 - 80035e0: 4619 mov r1, r3 - 80035e2: f04f 0200 mov.w r2, #0 - 80035e6: 4bc6 ldr r3, [pc, #792] ; (8003900 ) - 80035e8: f7fd f930 bl 800084c <__aeabi_ddiv> - 80035ec: 4602 mov r2, r0 - 80035ee: 460b mov r3, r1 - 80035f0: ec43 2b17 vmov d7, r2, r3 - 80035f4: eeb0 0a47 vmov.f32 s0, s14 - 80035f8: eef0 0a67 vmov.f32 s1, s15 - 80035fc: f011 ff98 bl 8015530 - 8003600: ec51 0b10 vmov r0, r1, d0 - 8003604: f04f 0200 mov.w r2, #0 - 8003608: 4bbe ldr r3, [pc, #760] ; (8003904 ) - 800360a: f7fc fff5 bl 80005f8 <__aeabi_dmul> - 800360e: 4602 mov r2, r0 - 8003610: 460b mov r3, r1 - 8003612: ec43 2b17 vmov d7, r2, r3 - 8003616: eeb0 0a47 vmov.f32 s0, s14 - 800361a: eef0 0a67 vmov.f32 s1, s15 - 800361e: f012 f877 bl 8015710 - 8003622: ec51 0b10 vmov r0, r1, d0 - 8003626: f04f 0200 mov.w r2, #0 - 800362a: 4bb7 ldr r3, [pc, #732] ; (8003908 ) - 800362c: f7fc fe2e bl 800028c <__adddf3> - 8003630: 4602 mov r2, r0 - 8003632: 460b mov r3, r1 - 8003634: 4610 mov r0, r2 - 8003636: 4619 mov r1, r3 - 8003638: f7fd fab6 bl 8000ba8 <__aeabi_d2uiz> - 800363c: 4603 mov r3, r0 - 800363e: b2dc uxtb r4, r3 - 8003640: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 - 8003644: f7fc ff6e bl 8000524 <__aeabi_i2d> - 8003648: a3ab add r3, pc, #684 ; (adr r3, 80038f8 ) - 800364a: e9d3 2300 ldrd r2, r3, [r3] - 800364e: f7fc ffd3 bl 80005f8 <__aeabi_dmul> - 8003652: 4602 mov r2, r0 - 8003654: 460b mov r3, r1 - 8003656: 4610 mov r0, r2 - 8003658: 4619 mov r1, r3 - 800365a: f04f 0200 mov.w r2, #0 - 800365e: 4ba8 ldr r3, [pc, #672] ; (8003900 ) - 8003660: f7fd f8f4 bl 800084c <__aeabi_ddiv> - 8003664: 4602 mov r2, r0 - 8003666: 460b mov r3, r1 - 8003668: ec43 2b17 vmov d7, r2, r3 - 800366c: eeb0 0a47 vmov.f32 s0, s14 - 8003670: eef0 0a67 vmov.f32 s1, s15 - 8003674: f011 ffb0 bl 80155d8 - 8003678: ec51 0b10 vmov r0, r1, d0 - 800367c: f04f 0200 mov.w r2, #0 - 8003680: 4ba0 ldr r3, [pc, #640] ; (8003904 ) - 8003682: f7fc ffb9 bl 80005f8 <__aeabi_dmul> - 8003686: 4602 mov r2, r0 - 8003688: 460b mov r3, r1 - 800368a: ec43 2b17 vmov d7, r2, r3 - 800368e: eeb0 0a47 vmov.f32 s0, s14 - 8003692: eef0 0a67 vmov.f32 s1, s15 - 8003696: f012 f83b bl 8015710 - 800369a: ec51 0b10 vmov r0, r1, d0 - 800369e: f04f 0200 mov.w r2, #0 - 80036a2: 4b9a ldr r3, [pc, #616] ; (800390c ) - 80036a4: f7fc fdf2 bl 800028c <__adddf3> - 80036a8: 4602 mov r2, r0 - 80036aa: 460b mov r3, r1 - 80036ac: 4610 mov r0, r2 - 80036ae: 4619 mov r1, r3 - 80036b0: f7fd fa7a bl 8000ba8 <__aeabi_d2uiz> - 80036b4: 4603 mov r3, r0 - 80036b6: b2dd uxtb r5, r3 - 80036b8: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 - 80036bc: f7fc ff32 bl 8000524 <__aeabi_i2d> - 80036c0: a38d add r3, pc, #564 ; (adr r3, 80038f8 ) - 80036c2: e9d3 2300 ldrd r2, r3, [r3] - 80036c6: f7fc ff97 bl 80005f8 <__aeabi_dmul> - 80036ca: 4602 mov r2, r0 - 80036cc: 460b mov r3, r1 - 80036ce: 4610 mov r0, r2 - 80036d0: 4619 mov r1, r3 - 80036d2: f04f 0200 mov.w r2, #0 - 80036d6: 4b8a ldr r3, [pc, #552] ; (8003900 ) - 80036d8: f7fd f8b8 bl 800084c <__aeabi_ddiv> - 80036dc: 4602 mov r2, r0 - 80036de: 460b mov r3, r1 - 80036e0: ec43 2b17 vmov d7, r2, r3 - 80036e4: eeb0 0a47 vmov.f32 s0, s14 - 80036e8: eef0 0a67 vmov.f32 s1, s15 - 80036ec: f011 ff20 bl 8015530 - 80036f0: ec51 0b10 vmov r0, r1, d0 - 80036f4: f04f 0200 mov.w r2, #0 - 80036f8: 4b85 ldr r3, [pc, #532] ; (8003910 ) - 80036fa: f7fc ff7d bl 80005f8 <__aeabi_dmul> - 80036fe: 4602 mov r2, r0 - 8003700: 460b mov r3, r1 - 8003702: ec43 2b17 vmov d7, r2, r3 - 8003706: eeb0 0a47 vmov.f32 s0, s14 - 800370a: eef0 0a67 vmov.f32 s1, s15 - 800370e: f011 ffff bl 8015710 - 8003712: ec51 0b10 vmov r0, r1, d0 - 8003716: f04f 0200 mov.w r2, #0 - 800371a: 4b7b ldr r3, [pc, #492] ; (8003908 ) - 800371c: f7fc fdb6 bl 800028c <__adddf3> - 8003720: 4602 mov r2, r0 - 8003722: 460b mov r3, r1 - 8003724: 4610 mov r0, r2 - 8003726: 4619 mov r1, r3 - 8003728: f7fd fa3e bl 8000ba8 <__aeabi_d2uiz> - 800372c: 4603 mov r3, r0 - 800372e: b2de uxtb r6, r3 - 8003730: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 - 8003734: f7fc fef6 bl 8000524 <__aeabi_i2d> - 8003738: a36f add r3, pc, #444 ; (adr r3, 80038f8 ) - 800373a: e9d3 2300 ldrd r2, r3, [r3] - 800373e: f7fc ff5b bl 80005f8 <__aeabi_dmul> - 8003742: 4602 mov r2, r0 - 8003744: 460b mov r3, r1 - 8003746: 4610 mov r0, r2 - 8003748: 4619 mov r1, r3 - 800374a: f04f 0200 mov.w r2, #0 - 800374e: 4b6c ldr r3, [pc, #432] ; (8003900 ) - 8003750: f7fd f87c bl 800084c <__aeabi_ddiv> - 8003754: 4602 mov r2, r0 - 8003756: 460b mov r3, r1 - 8003758: ec43 2b17 vmov d7, r2, r3 - 800375c: eeb0 0a47 vmov.f32 s0, s14 - 8003760: eef0 0a67 vmov.f32 s1, s15 - 8003764: f011 ff38 bl 80155d8 - 8003768: ec51 0b10 vmov r0, r1, d0 - 800376c: f04f 0200 mov.w r2, #0 - 8003770: 4b67 ldr r3, [pc, #412] ; (8003910 ) - 8003772: f7fc ff41 bl 80005f8 <__aeabi_dmul> - 8003776: 4602 mov r2, r0 - 8003778: 460b mov r3, r1 - 800377a: ec43 2b17 vmov d7, r2, r3 - 800377e: eeb0 0a47 vmov.f32 s0, s14 - 8003782: eef0 0a67 vmov.f32 s1, s15 - 8003786: f011 ffc3 bl 8015710 - 800378a: ec51 0b10 vmov r0, r1, d0 - 800378e: f04f 0200 mov.w r2, #0 - 8003792: 4b5e ldr r3, [pc, #376] ; (800390c ) - 8003794: f7fc fd7a bl 800028c <__adddf3> - 8003798: 4602 mov r2, r0 - 800379a: 460b mov r3, r1 - 800379c: 4610 mov r0, r2 - 800379e: 4619 mov r1, r3 - 80037a0: f7fd fa02 bl 8000ba8 <__aeabi_d2uiz> - 80037a4: 4603 mov r3, r0 - 80037a6: b2db uxtb r3, r3 - 80037a8: 2201 movs r2, #1 - 80037aa: 9200 str r2, [sp, #0] - 80037ac: 4632 mov r2, r6 - 80037ae: 4629 mov r1, r5 - 80037b0: 4620 mov r0, r4 - 80037b2: f7fe fde9 bl 8002388 + 8003f00: 6db8 ldr r0, [r7, #88] ; 0x58 + 8003f02: f7fc fb0f bl 8000524 <__aeabi_i2d> + 8003f06: a3c6 add r3, pc, #792 ; (adr r3, 8004220 ) + 8003f08: e9d3 2300 ldrd r2, r3, [r3] + 8003f0c: f7fc fb74 bl 80005f8 <__aeabi_dmul> + 8003f10: 4602 mov r2, r0 + 8003f12: 460b mov r3, r1 + 8003f14: 4610 mov r0, r2 + 8003f16: 4619 mov r1, r3 + 8003f18: f04f 0200 mov.w r2, #0 + 8003f1c: 4bc2 ldr r3, [pc, #776] ; (8004228 ) + 8003f1e: f7fc fc95 bl 800084c <__aeabi_ddiv> + 8003f22: 4602 mov r2, r0 + 8003f24: 460b mov r3, r1 + 8003f26: ec43 2b17 vmov d7, r2, r3 + 8003f2a: eeb0 0a47 vmov.f32 s0, s14 + 8003f2e: eef0 0a67 vmov.f32 s1, s15 + 8003f32: f013 fd55 bl 80179e0 + 8003f36: ec51 0b10 vmov r0, r1, d0 + 8003f3a: f04f 0200 mov.w r2, #0 + 8003f3e: 4bbb ldr r3, [pc, #748] ; (800422c ) + 8003f40: f7fc fb5a bl 80005f8 <__aeabi_dmul> + 8003f44: 4602 mov r2, r0 + 8003f46: 460b mov r3, r1 + 8003f48: ec43 2b17 vmov d7, r2, r3 + 8003f4c: eeb0 0a47 vmov.f32 s0, s14 + 8003f50: eef0 0a67 vmov.f32 s1, s15 + 8003f54: f013 fe34 bl 8017bc0 + 8003f58: ec51 0b10 vmov r0, r1, d0 + 8003f5c: f04f 0200 mov.w r2, #0 + 8003f60: 4bb3 ldr r3, [pc, #716] ; (8004230 ) + 8003f62: f7fc f993 bl 800028c <__adddf3> + 8003f66: 4602 mov r2, r0 + 8003f68: 460b mov r3, r1 + 8003f6a: 4610 mov r0, r2 + 8003f6c: 4619 mov r1, r3 + 8003f6e: f7fc fe1b bl 8000ba8 <__aeabi_d2uiz> + 8003f72: 4603 mov r3, r0 + 8003f74: b2dc uxtb r4, r3 + 8003f76: 6db8 ldr r0, [r7, #88] ; 0x58 + 8003f78: f7fc fad4 bl 8000524 <__aeabi_i2d> + 8003f7c: a3a8 add r3, pc, #672 ; (adr r3, 8004220 ) + 8003f7e: e9d3 2300 ldrd r2, r3, [r3] + 8003f82: f7fc fb39 bl 80005f8 <__aeabi_dmul> + 8003f86: 4602 mov r2, r0 + 8003f88: 460b mov r3, r1 + 8003f8a: 4610 mov r0, r2 + 8003f8c: 4619 mov r1, r3 + 8003f8e: f04f 0200 mov.w r2, #0 + 8003f92: 4ba5 ldr r3, [pc, #660] ; (8004228 ) + 8003f94: f7fc fc5a bl 800084c <__aeabi_ddiv> + 8003f98: 4602 mov r2, r0 + 8003f9a: 460b mov r3, r1 + 8003f9c: ec43 2b17 vmov d7, r2, r3 + 8003fa0: eeb0 0a47 vmov.f32 s0, s14 + 8003fa4: eef0 0a67 vmov.f32 s1, s15 + 8003fa8: f013 fd6e bl 8017a88 + 8003fac: ec51 0b10 vmov r0, r1, d0 + 8003fb0: f04f 0200 mov.w r2, #0 + 8003fb4: 4b9d ldr r3, [pc, #628] ; (800422c ) + 8003fb6: f7fc fb1f bl 80005f8 <__aeabi_dmul> + 8003fba: 4602 mov r2, r0 + 8003fbc: 460b mov r3, r1 + 8003fbe: ec43 2b17 vmov d7, r2, r3 + 8003fc2: eeb0 0a47 vmov.f32 s0, s14 + 8003fc6: eef0 0a67 vmov.f32 s1, s15 + 8003fca: f013 fdf9 bl 8017bc0 + 8003fce: ec51 0b10 vmov r0, r1, d0 + 8003fd2: f04f 0200 mov.w r2, #0 + 8003fd6: 4b97 ldr r3, [pc, #604] ; (8004234 ) + 8003fd8: f7fc f958 bl 800028c <__adddf3> + 8003fdc: 4602 mov r2, r0 + 8003fde: 460b mov r3, r1 + 8003fe0: 4610 mov r0, r2 + 8003fe2: 4619 mov r1, r3 + 8003fe4: f7fc fde0 bl 8000ba8 <__aeabi_d2uiz> + 8003fe8: 4603 mov r3, r0 + 8003fea: b2dd uxtb r5, r3 + 8003fec: 6db8 ldr r0, [r7, #88] ; 0x58 + 8003fee: f7fc fa99 bl 8000524 <__aeabi_i2d> + 8003ff2: a38b add r3, pc, #556 ; (adr r3, 8004220 ) + 8003ff4: e9d3 2300 ldrd r2, r3, [r3] + 8003ff8: f7fc fafe bl 80005f8 <__aeabi_dmul> + 8003ffc: 4602 mov r2, r0 + 8003ffe: 460b mov r3, r1 + 8004000: 4610 mov r0, r2 + 8004002: 4619 mov r1, r3 + 8004004: f04f 0200 mov.w r2, #0 + 8004008: 4b87 ldr r3, [pc, #540] ; (8004228 ) + 800400a: f7fc fc1f bl 800084c <__aeabi_ddiv> + 800400e: 4602 mov r2, r0 + 8004010: 460b mov r3, r1 + 8004012: ec43 2b17 vmov d7, r2, r3 + 8004016: eeb0 0a47 vmov.f32 s0, s14 + 800401a: eef0 0a67 vmov.f32 s1, s15 + 800401e: f013 fcdf bl 80179e0 + 8004022: ec51 0b10 vmov r0, r1, d0 + 8004026: f04f 0200 mov.w r2, #0 + 800402a: 4b83 ldr r3, [pc, #524] ; (8004238 ) + 800402c: f7fc fae4 bl 80005f8 <__aeabi_dmul> + 8004030: 4602 mov r2, r0 + 8004032: 460b mov r3, r1 + 8004034: ec43 2b17 vmov d7, r2, r3 + 8004038: eeb0 0a47 vmov.f32 s0, s14 + 800403c: eef0 0a67 vmov.f32 s1, s15 + 8004040: f013 fdbe bl 8017bc0 + 8004044: ec51 0b10 vmov r0, r1, d0 + 8004048: f04f 0200 mov.w r2, #0 + 800404c: 4b78 ldr r3, [pc, #480] ; (8004230 ) + 800404e: f7fc f91d bl 800028c <__adddf3> + 8004052: 4602 mov r2, r0 + 8004054: 460b mov r3, r1 + 8004056: 4610 mov r0, r2 + 8004058: 4619 mov r1, r3 + 800405a: f7fc fda5 bl 8000ba8 <__aeabi_d2uiz> + 800405e: 4603 mov r3, r0 + 8004060: b2de uxtb r6, r3 + 8004062: 6db8 ldr r0, [r7, #88] ; 0x58 + 8004064: f7fc fa5e bl 8000524 <__aeabi_i2d> + 8004068: a36d add r3, pc, #436 ; (adr r3, 8004220 ) + 800406a: e9d3 2300 ldrd r2, r3, [r3] + 800406e: f7fc fac3 bl 80005f8 <__aeabi_dmul> + 8004072: 4602 mov r2, r0 + 8004074: 460b mov r3, r1 + 8004076: 4610 mov r0, r2 + 8004078: 4619 mov r1, r3 + 800407a: f04f 0200 mov.w r2, #0 + 800407e: 4b6a ldr r3, [pc, #424] ; (8004228 ) + 8004080: f7fc fbe4 bl 800084c <__aeabi_ddiv> + 8004084: 4602 mov r2, r0 + 8004086: 460b mov r3, r1 + 8004088: ec43 2b17 vmov d7, r2, r3 + 800408c: eeb0 0a47 vmov.f32 s0, s14 + 8004090: eef0 0a67 vmov.f32 s1, s15 + 8004094: f013 fcf8 bl 8017a88 + 8004098: ec51 0b10 vmov r0, r1, d0 + 800409c: f04f 0200 mov.w r2, #0 + 80040a0: 4b65 ldr r3, [pc, #404] ; (8004238 ) + 80040a2: f7fc faa9 bl 80005f8 <__aeabi_dmul> + 80040a6: 4602 mov r2, r0 + 80040a8: 460b mov r3, r1 + 80040aa: ec43 2b17 vmov d7, r2, r3 + 80040ae: eeb0 0a47 vmov.f32 s0, s14 + 80040b2: eef0 0a67 vmov.f32 s1, s15 + 80040b6: f013 fd83 bl 8017bc0 + 80040ba: ec51 0b10 vmov r0, r1, d0 + 80040be: f04f 0200 mov.w r2, #0 + 80040c2: 4b5c ldr r3, [pc, #368] ; (8004234 ) + 80040c4: f7fc f8e2 bl 800028c <__adddf3> + 80040c8: 4602 mov r2, r0 + 80040ca: 460b mov r3, r1 + 80040cc: 4610 mov r0, r2 + 80040ce: 4619 mov r1, r3 + 80040d0: f7fc fd6a bl 8000ba8 <__aeabi_d2uiz> + 80040d4: 4603 mov r3, r0 + 80040d6: b2db uxtb r3, r3 + 80040d8: 2201 movs r2, #1 + 80040da: 9200 str r2, [sp, #0] + 80040dc: 4632 mov r2, r6 + 80040de: 4629 mov r1, r5 + 80040e0: 4620 mov r0, r4 + 80040e2: f7fe fc7f bl 80029e4 for(int i=0;i<=12;i++){ - 80037b6: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 80037ba: 3301 adds r3, #1 - 80037bc: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 - 80037c0: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 80037c4: 2b0c cmp r3, #12 - 80037c6: f77f aeff ble.w 80035c8 + 80040e6: 6dbb ldr r3, [r7, #88] ; 0x58 + 80040e8: 3301 adds r3, #1 + 80040ea: 65bb str r3, [r7, #88] ; 0x58 + 80040ec: 6dbb ldr r3, [r7, #88] ; 0x58 + 80040ee: 2b0c cmp r3, #12 + 80040f0: f77f af06 ble.w 8003f00 } if(BTN_B>=1){ - 80037ca: 4b52 ldr r3, [pc, #328] ; (8003914 ) - 80037cc: 681b ldr r3, [r3, #0] - 80037ce: 2b00 cmp r3, #0 - 80037d0: dd20 ble.n 8003814 + 80040f4: 4b51 ldr r3, [pc, #324] ; (800423c ) + 80040f6: 681b ldr r3, [r3, #0] + 80040f8: 2b00 cmp r3, #0 + 80040fa: dd1e ble.n 800413a hrstate--; - 80037d2: 4b51 ldr r3, [pc, #324] ; (8003918 ) - 80037d4: 781b ldrb r3, [r3, #0] - 80037d6: 3b01 subs r3, #1 - 80037d8: b2da uxtb r2, r3 - 80037da: 4b4f ldr r3, [pc, #316] ; (8003918 ) - 80037dc: 701a strb r2, [r3, #0] + 80040fc: 4b50 ldr r3, [pc, #320] ; (8004240 ) + 80040fe: 781b ldrb r3, [r3, #0] + 8004100: 3b01 subs r3, #1 + 8004102: b2da uxtb r2, r3 + 8004104: 4b4e ldr r3, [pc, #312] ; (8004240 ) + 8004106: 701a strb r2, [r3, #0] BTN_B=0; - 80037de: 4b4d ldr r3, [pc, #308] ; (8003914 ) - 80037e0: 2200 movs r2, #0 - 80037e2: 601a str r2, [r3, #0] + 8004108: 4b4c ldr r3, [pc, #304] ; (800423c ) + 800410a: 2200 movs r2, #0 + 800410c: 601a str r2, [r3, #0] } break; - 80037e4: e016 b.n 8003814 + 800410e: e014 b.n 800413a } } else{ //if the GPS doesn't have a fix, print a message char *str = (char*)malloc(sizeof(char)*20); - 80037e6: 2014 movs r0, #20 - 80037e8: f00d f9a4 bl 8010b34 - 80037ec: 4603 mov r3, r0 - 80037ee: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 8004110: 2014 movs r0, #20 + 8004112: f00e ff67 bl 8012fe4 + 8004116: 4603 mov r3, r0 + 8004118: 647b str r3, [r7, #68] ; 0x44 ssd1306_SetCursor(32, 44); - 80037f2: 212c movs r1, #44 ; 0x2c - 80037f4: 2020 movs r0, #32 - 80037f6: f7fe fdaf bl 8002358 + 800411a: 212c movs r1, #44 ; 0x2c + 800411c: 2020 movs r0, #32 + 800411e: f7fe fc49 bl 80029b4 ssd1306_WriteString("Wait GPS", Font_6x8, White); - 80037fa: 4a48 ldr r2, [pc, #288] ; (800391c ) - 80037fc: 2301 movs r3, #1 - 80037fe: ca06 ldmia r2, {r1, r2} - 8003800: 4847 ldr r0, [pc, #284] ; (8003920 ) - 8003802: f7fe fd83 bl 800230c + 8004122: 4a48 ldr r2, [pc, #288] ; (8004244 ) + 8004124: 2301 movs r3, #1 + 8004126: ca06 ldmia r2, {r1, r2} + 8004128: 4847 ldr r0, [pc, #284] ; (8004248 ) + 800412a: f7fe fc1d bl 8002968 free(str); - 8003806: f8d7 0098 ldr.w r0, [r7, #152] ; 0x98 - 800380a: f00d f99b bl 8010b44 - 800380e: e002 b.n 8003816 + 800412e: 6c78 ldr r0, [r7, #68] ; 0x44 + 8004130: f00e ff60 bl 8012ff4 + 8004134: e002 b.n 800413c break; - 8003810: bf00 nop - 8003812: e000 b.n 8003816 + 8004136: bf00 nop + 8004138: e000 b.n 800413c break; - 8003814: bf00 nop + 800413a: bf00 nop } if(BTN_A>=1){ - 8003816: 4b43 ldr r3, [pc, #268] ; (8003924 ) - 8003818: 681b ldr r3, [r3, #0] - 800381a: 2b00 cmp r3, #0 - 800381c: f340 8299 ble.w 8003d52 + 800413c: 4b43 ldr r3, [pc, #268] ; (800424c ) + 800413e: 681b ldr r3, [r3, #0] + 8004140: 2b00 cmp r3, #0 + 8004142: f340 8453 ble.w 80049ec state++; - 8003820: 4b41 ldr r3, [pc, #260] ; (8003928 ) - 8003822: 781b ldrb r3, [r3, #0] - 8003824: 3301 adds r3, #1 - 8003826: b2da uxtb r2, r3 - 8003828: 4b3f ldr r3, [pc, #252] ; (8003928 ) - 800382a: 701a strb r2, [r3, #0] + 8004146: 4b42 ldr r3, [pc, #264] ; (8004250 ) + 8004148: 781b ldrb r3, [r3, #0] + 800414a: 3301 adds r3, #1 + 800414c: b2da uxtb r2, r3 + 800414e: 4b40 ldr r3, [pc, #256] ; (8004250 ) + 8004150: 701a strb r2, [r3, #0] BTN_A=0; - 800382c: 4b3d ldr r3, [pc, #244] ; (8003924 ) - 800382e: 2200 movs r2, #0 - 8003830: 601a str r2, [r3, #0] + 8004152: 4b3e ldr r3, [pc, #248] ; (800424c ) + 8004154: 2200 movs r2, #0 + 8004156: 601a str r2, [r3, #0] BTN_B=0; - 8003832: 4b38 ldr r3, [pc, #224] ; (8003914 ) - 8003834: 2200 movs r2, #0 - 8003836: 601a str r2, [r3, #0] + 8004158: 4b38 ldr r3, [pc, #224] ; (800423c ) + 800415a: 2200 movs r2, #0 + 800415c: 601a str r2, [r3, #0] } break; - 8003838: e28b b.n 8003d52 + 800415e: f000 bc45 b.w 80049ec case STATE_INFO: ssd1306_Fill(Black); - 800383a: 2000 movs r0, #0 - 800383c: f7fe fc4a bl 80020d4 + 8004162: 2000 movs r0, #0 + 8004164: f7fe fae4 bl 8002730 nmea_parse(&myData, DataBuffer); - 8003840: 493a ldr r1, [pc, #232] ; (800392c ) - 8003842: 483b ldr r0, [pc, #236] ; (8003930 ) - 8003844: f7fe faf2 bl 8001e2c + 8004168: 493a ldr r1, [pc, #232] ; (8004254 ) + 800416a: 483b ldr r0, [pc, #236] ; (8004258 ) + 800416c: f7fd ff5e bl 800202c if(myData.fix == 1){ //if the GPS has a fix, print the data - 8003848: 4b39 ldr r3, [pc, #228] ; (8003930 ) - 800384a: 6a9b ldr r3, [r3, #40] ; 0x28 - 800384c: 2b01 cmp r3, #1 - 800384e: d179 bne.n 8003944 + 8004170: 4b39 ldr r3, [pc, #228] ; (8004258 ) + 8004172: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004174: 2b01 cmp r3, #1 + 8004176: d17b bne.n 8004270 char * str = (char*)malloc(sizeof(char)*20); - 8003850: 2014 movs r0, #20 - 8003852: f00d f96f bl 8010b34 - 8003856: 4603 mov r3, r0 - 8003858: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 8004178: 2014 movs r0, #20 + 800417a: f00e ff33 bl 8012fe4 + 800417e: 4603 mov r3, r0 + 8004180: 64bb str r3, [r7, #72] ; 0x48 snprintf(str,15, "hdop=%.1f",myData.hdop);//sert a connaitre la qualitée du fix si proche de 1 voir inférieur alors le fix est tres bon - 800385c: 4b34 ldr r3, [pc, #208] ; (8003930 ) - 800385e: 6a1b ldr r3, [r3, #32] - 8003860: 4618 mov r0, r3 - 8003862: f7fc fe71 bl 8000548 <__aeabi_f2d> - 8003866: 4602 mov r2, r0 - 8003868: 460b mov r3, r1 - 800386a: e9cd 2300 strd r2, r3, [sp] - 800386e: 4a31 ldr r2, [pc, #196] ; (8003934 ) - 8003870: 210f movs r1, #15 - 8003872: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 8003876: f00f f859 bl 801292c + 8004182: 4b35 ldr r3, [pc, #212] ; (8004258 ) + 8004184: 6a1b ldr r3, [r3, #32] + 8004186: 4618 mov r0, r3 + 8004188: f7fc f9de bl 8000548 <__aeabi_f2d> + 800418c: 4602 mov r2, r0 + 800418e: 460b mov r3, r1 + 8004190: e9cd 2300 strd r2, r3, [sp] + 8004194: 4a31 ldr r2, [pc, #196] ; (800425c ) + 8004196: 210f movs r1, #15 + 8004198: 6cb8 ldr r0, [r7, #72] ; 0x48 + 800419a: f010 fe1f bl 8014ddc ssd1306_SetCursor(32, 32); - 800387a: 2120 movs r1, #32 - 800387c: 2020 movs r0, #32 - 800387e: f7fe fd6b bl 8002358 + 800419e: 2120 movs r1, #32 + 80041a0: 2020 movs r0, #32 + 80041a2: f7fe fc07 bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 8003882: 4a26 ldr r2, [pc, #152] ; (800391c ) - 8003884: 2301 movs r3, #1 - 8003886: ca06 ldmia r2, {r1, r2} - 8003888: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 800388c: f7fe fd3e bl 800230c - snprintf(str,15, "SatNb :%d",myData.satelliteCount); - 8003890: 4b27 ldr r3, [pc, #156] ; (8003930 ) - 8003892: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003894: 4a28 ldr r2, [pc, #160] ; (8003938 ) - 8003896: 210f movs r1, #15 - 8003898: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 800389c: f00f f846 bl 801292c + 80041a6: 4a27 ldr r2, [pc, #156] ; (8004244 ) + 80041a8: 2301 movs r3, #1 + 80041aa: ca06 ldmia r2, {r1, r2} + 80041ac: 6cb8 ldr r0, [r7, #72] ; 0x48 + 80041ae: f7fe fbdb bl 8002968 + snprintf(str,20, "v=%0.2fV",vbat); + 80041b2: 4b2b ldr r3, [pc, #172] ; (8004260 ) + 80041b4: 681b ldr r3, [r3, #0] + 80041b6: 4618 mov r0, r3 + 80041b8: f7fc f9c6 bl 8000548 <__aeabi_f2d> + 80041bc: 4602 mov r2, r0 + 80041be: 460b mov r3, r1 + 80041c0: e9cd 2300 strd r2, r3, [sp] + 80041c4: 4a27 ldr r2, [pc, #156] ; (8004264 ) + 80041c6: 2114 movs r1, #20 + 80041c8: 6cb8 ldr r0, [r7, #72] ; 0x48 + 80041ca: f010 fe07 bl 8014ddc ssd1306_SetCursor(32, 42); - 80038a0: 212a movs r1, #42 ; 0x2a - 80038a2: 2020 movs r0, #32 - 80038a4: f7fe fd58 bl 8002358 + 80041ce: 212a movs r1, #42 ; 0x2a + 80041d0: 2020 movs r0, #32 + 80041d2: f7fe fbef bl 80029b4 ssd1306_WriteString(str, Font_6x8, White); - 80038a8: 4a1c ldr r2, [pc, #112] ; (800391c ) - 80038aa: 2301 movs r3, #1 - 80038ac: ca06 ldmia r2, {r1, r2} - 80038ae: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 80038b2: f7fe fd2b bl 800230c + 80041d6: 4a1b ldr r2, [pc, #108] ; (8004244 ) + 80041d8: 2301 movs r3, #1 + 80041da: ca06 ldmia r2, {r1, r2} + 80041dc: 6cb8 ldr r0, [r7, #72] ; 0x48 + 80041de: f7fe fbc3 bl 8002968 ssd1306_SetCursor(32, 50); - 80038b6: 2132 movs r1, #50 ; 0x32 - 80038b8: 2020 movs r0, #32 - 80038ba: f7fe fd4d bl 8002358 + 80041e2: 2132 movs r1, #50 ; 0x32 + 80041e4: 2020 movs r0, #32 + 80041e6: f7fe fbe5 bl 80029b4 snprintf(str,15, "T=%0.2fC",temp); - 80038be: 4b1f ldr r3, [pc, #124] ; (800393c ) - 80038c0: 681b ldr r3, [r3, #0] - 80038c2: 4618 mov r0, r3 - 80038c4: f7fc fe40 bl 8000548 <__aeabi_f2d> - 80038c8: 4602 mov r2, r0 - 80038ca: 460b mov r3, r1 - 80038cc: e9cd 2300 strd r2, r3, [sp] - 80038d0: 4a1b ldr r2, [pc, #108] ; (8003940 ) - 80038d2: 210f movs r1, #15 - 80038d4: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 80038d8: f00f f828 bl 801292c + 80041ea: 4b1f ldr r3, [pc, #124] ; (8004268 ) + 80041ec: 681b ldr r3, [r3, #0] + 80041ee: 4618 mov r0, r3 + 80041f0: f7fc f9aa bl 8000548 <__aeabi_f2d> + 80041f4: 4602 mov r2, r0 + 80041f6: 460b mov r3, r1 + 80041f8: e9cd 2300 strd r2, r3, [sp] + 80041fc: 4a1b ldr r2, [pc, #108] ; (800426c ) + 80041fe: 210f movs r1, #15 + 8004200: 6cb8 ldr r0, [r7, #72] ; 0x48 + 8004202: f010 fdeb bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 80038dc: 4a0f ldr r2, [pc, #60] ; (800391c ) - 80038de: 2301 movs r3, #1 - 80038e0: ca06 ldmia r2, {r1, r2} - 80038e2: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 80038e6: f7fe fd11 bl 800230c + 8004206: 4a0f ldr r2, [pc, #60] ; (8004244 ) + 8004208: 2301 movs r3, #1 + 800420a: ca06 ldmia r2, {r1, r2} + 800420c: 6cb8 ldr r0, [r7, #72] ; 0x48 + 800420e: f7fe fbab bl 8002968 free(str); - 80038ea: f8d7 009c ldr.w r0, [r7, #156] ; 0x9c - 80038ee: f00d f929 bl 8010b44 - 80038f2: e05f b.n 80039b4 - 80038f4: f3af 8000 nop.w - 80038f8: 54442d18 .word 0x54442d18 - 80038fc: 400921fb .word 0x400921fb - 8003900: 40180000 .word 0x40180000 - 8003904: 40240000 .word 0x40240000 - 8003908: 40500000 .word 0x40500000 - 800390c: 40480000 .word 0x40480000 - 8003910: 40280000 .word 0x40280000 - 8003914: 20000824 .word 0x20000824 - 8003918: 20000829 .word 0x20000829 - 800391c: 20000008 .word 0x20000008 - 8003920: 0801692c .word 0x0801692c - 8003924: 20000820 .word 0x20000820 - 8003928: 20000828 .word 0x20000828 - 800392c: 200005e0 .word 0x200005e0 - 8003930: 200007e0 .word 0x200007e0 - 8003934: 08016a08 .word 0x08016a08 - 8003938: 08016a14 .word 0x08016a14 - 800393c: 20000834 .word 0x20000834 - 8003940: 08016a20 .word 0x08016a20 + 8004212: 6cb8 ldr r0, [r7, #72] ; 0x48 + 8004214: f00e feee bl 8012ff4 + 8004218: e06c b.n 80042f4 + 800421a: bf00 nop + 800421c: f3af 8000 nop.w + 8004220: 54442d18 .word 0x54442d18 + 8004224: 400921fb .word 0x400921fb + 8004228: 40180000 .word 0x40180000 + 800422c: 40240000 .word 0x40240000 + 8004230: 40500000 .word 0x40500000 + 8004234: 40480000 .word 0x40480000 + 8004238: 40280000 .word 0x40280000 + 800423c: 200006f4 .word 0x200006f4 + 8004240: 200006f9 .word 0x200006f9 + 8004244: 20000008 .word 0x20000008 + 8004248: 08018e24 .word 0x08018e24 + 800424c: 200006f0 .word 0x200006f0 + 8004250: 200006f8 .word 0x200006f8 + 8004254: 200004ac .word 0x200004ac + 8004258: 200006b0 .word 0x200006b0 + 800425c: 08018efc .word 0x08018efc + 8004260: 20000730 .word 0x20000730 + 8004264: 08018f08 .word 0x08018f08 + 8004268: 20000728 .word 0x20000728 + 800426c: 08018f14 .word 0x08018f14 } else{ //if the GPS doesn't have a fix, print a message char *str = (char*)malloc(sizeof(char)*20); - 8003944: 2014 movs r0, #20 - 8003946: f00d f8f5 bl 8010b34 - 800394a: 4603 mov r3, r0 - 800394c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 8004270: 2014 movs r0, #20 + 8004272: f00e feb7 bl 8012fe4 + 8004276: 4603 mov r3, r0 + 8004278: 64fb str r3, [r7, #76] ; 0x4c ssd1306_SetCursor(32, 32); - 8003950: 2120 movs r1, #32 - 8003952: 2020 movs r0, #32 - 8003954: f7fe fd00 bl 8002358 + 800427a: 2120 movs r1, #32 + 800427c: 2020 movs r0, #32 + 800427e: f7fe fb99 bl 80029b4 ssd1306_WriteString("INFO", Font_6x8, White); - 8003958: 4a55 ldr r2, [pc, #340] ; (8003ab0 ) - 800395a: 2301 movs r3, #1 - 800395c: ca06 ldmia r2, {r1, r2} - 800395e: 4855 ldr r0, [pc, #340] ; (8003ab4 ) - 8003960: f7fe fcd4 bl 800230c + 8004282: 4aa2 ldr r2, [pc, #648] ; (800450c ) + 8004284: 2301 movs r3, #1 + 8004286: ca06 ldmia r2, {r1, r2} + 8004288: 48a1 ldr r0, [pc, #644] ; (8004510 ) + 800428a: f7fe fb6d bl 8002968 ssd1306_SetCursor(32, 41); - 8003964: 2129 movs r1, #41 ; 0x29 - 8003966: 2020 movs r0, #32 - 8003968: f7fe fcf6 bl 8002358 - ssd1306_WriteString("Wait GPS", Font_6x8, White); - 800396c: 4a50 ldr r2, [pc, #320] ; (8003ab0 ) - 800396e: 2301 movs r3, #1 - 8003970: ca06 ldmia r2, {r1, r2} - 8003972: 4851 ldr r0, [pc, #324] ; (8003ab8 ) - 8003974: f7fe fcca bl 800230c + 800428e: 2129 movs r1, #41 ; 0x29 + 8004290: 2020 movs r0, #32 + 8004292: f7fe fb8f bl 80029b4 + snprintf(str,15, "vbat=%0.2fV",vbat); + 8004296: 4b9f ldr r3, [pc, #636] ; (8004514 ) + 8004298: 681b ldr r3, [r3, #0] + 800429a: 4618 mov r0, r3 + 800429c: f7fc f954 bl 8000548 <__aeabi_f2d> + 80042a0: 4602 mov r2, r0 + 80042a2: 460b mov r3, r1 + 80042a4: e9cd 2300 strd r2, r3, [sp] + 80042a8: 4a9b ldr r2, [pc, #620] ; (8004518 ) + 80042aa: 210f movs r1, #15 + 80042ac: 6cf8 ldr r0, [r7, #76] ; 0x4c + 80042ae: f010 fd95 bl 8014ddc + ssd1306_WriteString(str, Font_6x8, White); + 80042b2: 4a96 ldr r2, [pc, #600] ; (800450c ) + 80042b4: 2301 movs r3, #1 + 80042b6: ca06 ldmia r2, {r1, r2} + 80042b8: 6cf8 ldr r0, [r7, #76] ; 0x4c + 80042ba: f7fe fb55 bl 8002968 ssd1306_SetCursor(32, 50); - 8003978: 2132 movs r1, #50 ; 0x32 - 800397a: 2020 movs r0, #32 - 800397c: f7fe fcec bl 8002358 + 80042be: 2132 movs r1, #50 ; 0x32 + 80042c0: 2020 movs r0, #32 + 80042c2: f7fe fb77 bl 80029b4 snprintf(str,15, "T=%0.2fC",temp); - 8003980: 4b4e ldr r3, [pc, #312] ; (8003abc ) - 8003982: 681b ldr r3, [r3, #0] - 8003984: 4618 mov r0, r3 - 8003986: f7fc fddf bl 8000548 <__aeabi_f2d> - 800398a: 4602 mov r2, r0 - 800398c: 460b mov r3, r1 - 800398e: e9cd 2300 strd r2, r3, [sp] - 8003992: 4a4b ldr r2, [pc, #300] ; (8003ac0 ) - 8003994: 210f movs r1, #15 - 8003996: f8d7 00a0 ldr.w r0, [r7, #160] ; 0xa0 - 800399a: f00e ffc7 bl 801292c + 80042c6: 4b95 ldr r3, [pc, #596] ; (800451c ) + 80042c8: 681b ldr r3, [r3, #0] + 80042ca: 4618 mov r0, r3 + 80042cc: f7fc f93c bl 8000548 <__aeabi_f2d> + 80042d0: 4602 mov r2, r0 + 80042d2: 460b mov r3, r1 + 80042d4: e9cd 2300 strd r2, r3, [sp] + 80042d8: 4a91 ldr r2, [pc, #580] ; (8004520 ) + 80042da: 210f movs r1, #15 + 80042dc: 6cf8 ldr r0, [r7, #76] ; 0x4c + 80042de: f010 fd7d bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 800399e: 4a44 ldr r2, [pc, #272] ; (8003ab0 ) - 80039a0: 2301 movs r3, #1 - 80039a2: ca06 ldmia r2, {r1, r2} - 80039a4: f8d7 00a0 ldr.w r0, [r7, #160] ; 0xa0 - 80039a8: f7fe fcb0 bl 800230c + 80042e2: 4a8a ldr r2, [pc, #552] ; (800450c ) + 80042e4: 2301 movs r3, #1 + 80042e6: ca06 ldmia r2, {r1, r2} + 80042e8: 6cf8 ldr r0, [r7, #76] ; 0x4c + 80042ea: f7fe fb3d bl 8002968 free(str); - 80039ac: f8d7 00a0 ldr.w r0, [r7, #160] ; 0xa0 - 80039b0: f00d f8c8 bl 8010b44 + 80042ee: 6cf8 ldr r0, [r7, #76] ; 0x4c + 80042f0: f00e fe80 bl 8012ff4 } if(BTN_A>=1){ - 80039b4: 4b43 ldr r3, [pc, #268] ; (8003ac4 ) - 80039b6: 681b ldr r3, [r3, #0] - 80039b8: 2b00 cmp r3, #0 - 80039ba: f340 81cc ble.w 8003d56 + 80042f4: 4b8b ldr r3, [pc, #556] ; (8004524 ) + 80042f6: 681b ldr r3, [r3, #0] + 80042f8: 2b00 cmp r3, #0 + 80042fa: f340 8379 ble.w 80049f0 state++; - 80039be: 4b42 ldr r3, [pc, #264] ; (8003ac8 ) - 80039c0: 781b ldrb r3, [r3, #0] - 80039c2: 3301 adds r3, #1 - 80039c4: b2da uxtb r2, r3 - 80039c6: 4b40 ldr r3, [pc, #256] ; (8003ac8 ) - 80039c8: 701a strb r2, [r3, #0] + 80042fe: 4b8a ldr r3, [pc, #552] ; (8004528 ) + 8004300: 781b ldrb r3, [r3, #0] + 8004302: 3301 adds r3, #1 + 8004304: b2da uxtb r2, r3 + 8004306: 4b88 ldr r3, [pc, #544] ; (8004528 ) + 8004308: 701a strb r2, [r3, #0] BTN_A=0; - 80039ca: 4b3e ldr r3, [pc, #248] ; (8003ac4 ) - 80039cc: 2200 movs r2, #0 - 80039ce: 601a str r2, [r3, #0] + 800430a: 4b86 ldr r3, [pc, #536] ; (8004524 ) + 800430c: 2200 movs r2, #0 + 800430e: 601a str r2, [r3, #0] BTN_B=0; - 80039d0: 4b3e ldr r3, [pc, #248] ; (8003acc ) - 80039d2: 2200 movs r2, #0 - 80039d4: 601a str r2, [r3, #0] + 8004310: 4b86 ldr r3, [pc, #536] ; (800452c ) + 8004312: 2200 movs r2, #0 + 8004314: 601a str r2, [r3, #0] } break; - 80039d6: e1be b.n 8003d56 + 8004316: e36b b.n 80049f0 case STATE_CHRONOMETER: ssd1306_Fill(Black); - 80039d8: 2000 movs r0, #0 - 80039da: f7fe fb7b bl 80020d4 + 8004318: 2000 movs r0, #0 + 800431a: f7fe fa09 bl 8002730 ssd1306_SetCursor(32, 32); - 80039de: 2120 movs r1, #32 - 80039e0: 2020 movs r0, #32 - 80039e2: f7fe fcb9 bl 8002358 + 800431e: 2120 movs r1, #32 + 8004320: 2020 movs r0, #32 + 8004322: f7fe fb47 bl 80029b4 char *str = (char*)malloc(sizeof(char)*20); - 80039e6: 2014 movs r0, #20 - 80039e8: f00d f8a4 bl 8010b34 - 80039ec: 4603 mov r3, r0 - 80039ee: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 8004326: 2014 movs r0, #20 + 8004328: f00e fe5c bl 8012fe4 + 800432c: 4603 mov r3, r0 + 800432e: 653b str r3, [r7, #80] ; 0x50 ssd1306_WriteString("chrono", Font_6x8, White); - 80039f2: 4a2f ldr r2, [pc, #188] ; (8003ab0 ) - 80039f4: 2301 movs r3, #1 - 80039f6: ca06 ldmia r2, {r1, r2} - 80039f8: 4835 ldr r0, [pc, #212] ; (8003ad0 ) - 80039fa: f7fe fc87 bl 800230c + 8004330: 4a76 ldr r2, [pc, #472] ; (800450c ) + 8004332: 2301 movs r3, #1 + 8004334: ca06 ldmia r2, {r1, r2} + 8004336: 487e ldr r0, [pc, #504] ; (8004530 ) + 8004338: f7fe fb16 bl 8002968 ssd1306_SetCursor(32, 40); - 80039fe: 2128 movs r1, #40 ; 0x28 - 8003a00: 2020 movs r0, #32 - 8003a02: f7fe fca9 bl 8002358 + 800433c: 2128 movs r1, #40 ; 0x28 + 800433e: 2020 movs r0, #32 + 8004340: f7fe fb38 bl 80029b4 switch(chronostate){ - 8003a06: 4b33 ldr r3, [pc, #204] ; (8003ad4 ) - 8003a08: 781b ldrb r3, [r3, #0] - 8003a0a: 2b02 cmp r3, #2 - 8003a0c: d038 beq.n 8003a80 - 8003a0e: 2b02 cmp r3, #2 - 8003a10: dc6d bgt.n 8003aee - 8003a12: 2b00 cmp r3, #0 - 8003a14: d002 beq.n 8003a1c - 8003a16: 2b01 cmp r3, #1 - 8003a18: d01d beq.n 8003a56 - 8003a1a: e068 b.n 8003aee + 8004344: 4b7b ldr r3, [pc, #492] ; (8004534 ) + 8004346: 781b ldrb r3, [r3, #0] + 8004348: 2b02 cmp r3, #2 + 800434a: d038 beq.n 80043be + 800434c: 2b02 cmp r3, #2 + 800434e: dc4f bgt.n 80043f0 + 8004350: 2b00 cmp r3, #0 + 8004352: d002 beq.n 800435a + 8004354: 2b01 cmp r3, #1 + 8004356: d01d beq.n 8004394 + 8004358: e04a b.n 80043f0 case STATE_RESET: min=0; - 8003a1c: 4b2e ldr r3, [pc, #184] ; (8003ad8 ) - 8003a1e: f04f 0200 mov.w r2, #0 - 8003a22: 601a str r2, [r3, #0] + 800435a: 4b77 ldr r3, [pc, #476] ; (8004538 ) + 800435c: f04f 0200 mov.w r2, #0 + 8004360: 601a str r2, [r3, #0] seconde=0; - 8003a24: 4b2d ldr r3, [pc, #180] ; (8003adc ) - 8003a26: f04f 0200 mov.w r2, #0 - 8003a2a: 601a str r2, [r3, #0] + 8004362: 4b76 ldr r3, [pc, #472] ; (800453c ) + 8004364: f04f 0200 mov.w r2, #0 + 8004368: 601a str r2, [r3, #0] calctime=0; - 8003a2c: 4b2c ldr r3, [pc, #176] ; (8003ae0 ) - 8003a2e: 2200 movs r2, #0 - 8003a30: 601a str r2, [r3, #0] + 800436a: 4b75 ldr r3, [pc, #468] ; (8004540 ) + 800436c: 2200 movs r2, #0 + 800436e: 601a str r2, [r3, #0] if(BTN_B>=1){ - 8003a32: 4b26 ldr r3, [pc, #152] ; (8003acc ) - 8003a34: 681b ldr r3, [r3, #0] - 8003a36: 2b00 cmp r3, #0 - 8003a38: dd36 ble.n 8003aa8 + 8004370: 4b6e ldr r3, [pc, #440] ; (800452c ) + 8004372: 681b ldr r3, [r3, #0] + 8004374: 2b00 cmp r3, #0 + 8004376: dd36 ble.n 80043e6 chronostate++; - 8003a3a: 4b26 ldr r3, [pc, #152] ; (8003ad4 ) - 8003a3c: 781b ldrb r3, [r3, #0] - 8003a3e: 3301 adds r3, #1 - 8003a40: b2da uxtb r2, r3 - 8003a42: 4b24 ldr r3, [pc, #144] ; (8003ad4 ) - 8003a44: 701a strb r2, [r3, #0] + 8004378: 4b6e ldr r3, [pc, #440] ; (8004534 ) + 800437a: 781b ldrb r3, [r3, #0] + 800437c: 3301 adds r3, #1 + 800437e: b2da uxtb r2, r3 + 8004380: 4b6c ldr r3, [pc, #432] ; (8004534 ) + 8004382: 701a strb r2, [r3, #0] BTN_B=0; - 8003a46: 4b21 ldr r3, [pc, #132] ; (8003acc ) - 8003a48: 2200 movs r2, #0 - 8003a4a: 601a str r2, [r3, #0] + 8004384: 4b69 ldr r3, [pc, #420] ; (800452c ) + 8004386: 2200 movs r2, #0 + 8004388: 601a str r2, [r3, #0] starttime=uwTick; - 8003a4c: 4b25 ldr r3, [pc, #148] ; (8003ae4 ) - 8003a4e: 681b ldr r3, [r3, #0] - 8003a50: 4a25 ldr r2, [pc, #148] ; (8003ae8 ) - 8003a52: 6013 str r3, [r2, #0] + 800438a: 4b6e ldr r3, [pc, #440] ; (8004544 ) + 800438c: 681b ldr r3, [r3, #0] + 800438e: 4a6e ldr r2, [pc, #440] ; (8004548 ) + 8004390: 6013 str r3, [r2, #0] } break; - 8003a54: e028 b.n 8003aa8 + 8004392: e028 b.n 80043e6 case STATE_RUN: calctime=uwTick-starttime; - 8003a56: 4b23 ldr r3, [pc, #140] ; (8003ae4 ) - 8003a58: 681a ldr r2, [r3, #0] - 8003a5a: 4b23 ldr r3, [pc, #140] ; (8003ae8 ) - 8003a5c: 681b ldr r3, [r3, #0] - 8003a5e: 1ad3 subs r3, r2, r3 - 8003a60: 4a1f ldr r2, [pc, #124] ; (8003ae0 ) - 8003a62: 6013 str r3, [r2, #0] + 8004394: 4b6b ldr r3, [pc, #428] ; (8004544 ) + 8004396: 681a ldr r2, [r3, #0] + 8004398: 4b6b ldr r3, [pc, #428] ; (8004548 ) + 800439a: 681b ldr r3, [r3, #0] + 800439c: 1ad3 subs r3, r2, r3 + 800439e: 4a68 ldr r2, [pc, #416] ; (8004540 ) + 80043a0: 6013 str r3, [r2, #0] if(BTN_B>=1){ - 8003a64: 4b19 ldr r3, [pc, #100] ; (8003acc ) - 8003a66: 681b ldr r3, [r3, #0] - 8003a68: 2b00 cmp r3, #0 - 8003a6a: dd1f ble.n 8003aac + 80043a2: 4b62 ldr r3, [pc, #392] ; (800452c ) + 80043a4: 681b ldr r3, [r3, #0] + 80043a6: 2b00 cmp r3, #0 + 80043a8: dd1f ble.n 80043ea chronostate++; - 8003a6c: 4b19 ldr r3, [pc, #100] ; (8003ad4 ) - 8003a6e: 781b ldrb r3, [r3, #0] - 8003a70: 3301 adds r3, #1 - 8003a72: b2da uxtb r2, r3 - 8003a74: 4b17 ldr r3, [pc, #92] ; (8003ad4 ) - 8003a76: 701a strb r2, [r3, #0] + 80043aa: 4b62 ldr r3, [pc, #392] ; (8004534 ) + 80043ac: 781b ldrb r3, [r3, #0] + 80043ae: 3301 adds r3, #1 + 80043b0: b2da uxtb r2, r3 + 80043b2: 4b60 ldr r3, [pc, #384] ; (8004534 ) + 80043b4: 701a strb r2, [r3, #0] BTN_B=0; - 8003a78: 4b14 ldr r3, [pc, #80] ; (8003acc ) - 8003a7a: 2200 movs r2, #0 - 8003a7c: 601a str r2, [r3, #0] + 80043b6: 4b5d ldr r3, [pc, #372] ; (800452c ) + 80043b8: 2200 movs r2, #0 + 80043ba: 601a str r2, [r3, #0] } break; - 8003a7e: e015 b.n 8003aac + 80043bc: e015 b.n 80043ea case STATE_PAUSE: if(BTN_B>=1){ - 8003a80: 4b12 ldr r3, [pc, #72] ; (8003acc ) - 8003a82: 681b ldr r3, [r3, #0] - 8003a84: 2b00 cmp r3, #0 - 8003a86: dd31 ble.n 8003aec + 80043be: 4b5b ldr r3, [pc, #364] ; (800452c ) + 80043c0: 681b ldr r3, [r3, #0] + 80043c2: 2b00 cmp r3, #0 + 80043c4: dd13 ble.n 80043ee chronostate--; - 8003a88: 4b12 ldr r3, [pc, #72] ; (8003ad4 ) - 8003a8a: 781b ldrb r3, [r3, #0] - 8003a8c: 3b01 subs r3, #1 - 8003a8e: b2da uxtb r2, r3 - 8003a90: 4b10 ldr r3, [pc, #64] ; (8003ad4 ) - 8003a92: 701a strb r2, [r3, #0] + 80043c6: 4b5b ldr r3, [pc, #364] ; (8004534 ) + 80043c8: 781b ldrb r3, [r3, #0] + 80043ca: 3b01 subs r3, #1 + 80043cc: b2da uxtb r2, r3 + 80043ce: 4b59 ldr r3, [pc, #356] ; (8004534 ) + 80043d0: 701a strb r2, [r3, #0] chronostate--; - 8003a94: 4b0f ldr r3, [pc, #60] ; (8003ad4 ) - 8003a96: 781b ldrb r3, [r3, #0] - 8003a98: 3b01 subs r3, #1 - 8003a9a: b2da uxtb r2, r3 - 8003a9c: 4b0d ldr r3, [pc, #52] ; (8003ad4 ) - 8003a9e: 701a strb r2, [r3, #0] + 80043d2: 4b58 ldr r3, [pc, #352] ; (8004534 ) + 80043d4: 781b ldrb r3, [r3, #0] + 80043d6: 3b01 subs r3, #1 + 80043d8: b2da uxtb r2, r3 + 80043da: 4b56 ldr r3, [pc, #344] ; (8004534 ) + 80043dc: 701a strb r2, [r3, #0] BTN_B=0; - 8003aa0: 4b0a ldr r3, [pc, #40] ; (8003acc ) - 8003aa2: 2200 movs r2, #0 - 8003aa4: 601a str r2, [r3, #0] + 80043de: 4b53 ldr r3, [pc, #332] ; (800452c ) + 80043e0: 2200 movs r2, #0 + 80043e2: 601a str r2, [r3, #0] } break; - 8003aa6: e021 b.n 8003aec + 80043e4: e003 b.n 80043ee break; - 8003aa8: bf00 nop - 8003aaa: e020 b.n 8003aee + 80043e6: bf00 nop + 80043e8: e002 b.n 80043f0 break; - 8003aac: bf00 nop - 8003aae: e01e b.n 8003aee - 8003ab0: 20000008 .word 0x20000008 - 8003ab4: 08016a2c .word 0x08016a2c - 8003ab8: 0801692c .word 0x0801692c - 8003abc: 20000834 .word 0x20000834 - 8003ac0: 08016a20 .word 0x08016a20 - 8003ac4: 20000820 .word 0x20000820 - 8003ac8: 20000828 .word 0x20000828 - 8003acc: 20000824 .word 0x20000824 - 8003ad0: 08016a34 .word 0x08016a34 - 8003ad4: 2000082c .word 0x2000082c - 8003ad8: 20000c88 .word 0x20000c88 - 8003adc: 20000c84 .word 0x20000c84 - 8003ae0: 20000c90 .word 0x20000c90 - 8003ae4: 20000c9c .word 0x20000c9c - 8003ae8: 20000c8c .word 0x20000c8c + 80043ea: bf00 nop + 80043ec: e000 b.n 80043f0 break; - 8003aec: bf00 nop + 80043ee: bf00 nop } min=floor((float) calctime/60000); - 8003aee: 4ba0 ldr r3, [pc, #640] ; (8003d70 ) - 8003af0: 681b ldr r3, [r3, #0] - 8003af2: ee07 3a90 vmov s15, r3 - 8003af6: eef8 7a67 vcvt.f32.u32 s15, s15 - 8003afa: ed9f 7a9e vldr s14, [pc, #632] ; 8003d74 - 8003afe: eec7 6a87 vdiv.f32 s13, s15, s14 - 8003b02: ee16 0a90 vmov r0, s13 - 8003b06: f7fc fd1f bl 8000548 <__aeabi_f2d> - 8003b0a: 4602 mov r2, r0 - 8003b0c: 460b mov r3, r1 - 8003b0e: ec43 2b10 vmov d0, r2, r3 - 8003b12: f011 fdfd bl 8015710 - 8003b16: ec53 2b10 vmov r2, r3, d0 - 8003b1a: 4610 mov r0, r2 - 8003b1c: 4619 mov r1, r3 - 8003b1e: f7fd f863 bl 8000be8 <__aeabi_d2f> - 8003b22: 4603 mov r3, r0 - 8003b24: 4a94 ldr r2, [pc, #592] ; (8003d78 ) - 8003b26: 6013 str r3, [r2, #0] + 80043f0: 4b53 ldr r3, [pc, #332] ; (8004540 ) + 80043f2: 681b ldr r3, [r3, #0] + 80043f4: ee07 3a90 vmov s15, r3 + 80043f8: eef8 7a67 vcvt.f32.u32 s15, s15 + 80043fc: ed9f 7a53 vldr s14, [pc, #332] ; 800454c + 8004400: eec7 6a87 vdiv.f32 s13, s15, s14 + 8004404: ee16 0a90 vmov r0, s13 + 8004408: f7fc f89e bl 8000548 <__aeabi_f2d> + 800440c: 4602 mov r2, r0 + 800440e: 460b mov r3, r1 + 8004410: ec43 2b10 vmov d0, r2, r3 + 8004414: f013 fbd4 bl 8017bc0 + 8004418: ec53 2b10 vmov r2, r3, d0 + 800441c: 4610 mov r0, r2 + 800441e: 4619 mov r1, r3 + 8004420: f7fc fbe2 bl 8000be8 <__aeabi_d2f> + 8004424: 4603 mov r3, r0 + 8004426: 4a44 ldr r2, [pc, #272] ; (8004538 ) + 8004428: 6013 str r3, [r2, #0] seconde=(float) ((calctime-(min*60000))/1000); - 8003b28: 4b91 ldr r3, [pc, #580] ; (8003d70 ) - 8003b2a: 681b ldr r3, [r3, #0] - 8003b2c: ee07 3a90 vmov s15, r3 - 8003b30: eeb8 7a67 vcvt.f32.u32 s14, s15 - 8003b34: 4b90 ldr r3, [pc, #576] ; (8003d78 ) - 8003b36: edd3 7a00 vldr s15, [r3] - 8003b3a: eddf 6a8e vldr s13, [pc, #568] ; 8003d74 - 8003b3e: ee67 7aa6 vmul.f32 s15, s15, s13 - 8003b42: ee37 7a67 vsub.f32 s14, s14, s15 - 8003b46: eddf 6a8d vldr s13, [pc, #564] ; 8003d7c - 8003b4a: eec7 7a26 vdiv.f32 s15, s14, s13 - 8003b4e: 4b8c ldr r3, [pc, #560] ; (8003d80 ) - 8003b50: edc3 7a00 vstr s15, [r3] + 800442a: 4b45 ldr r3, [pc, #276] ; (8004540 ) + 800442c: 681b ldr r3, [r3, #0] + 800442e: ee07 3a90 vmov s15, r3 + 8004432: eeb8 7a67 vcvt.f32.u32 s14, s15 + 8004436: 4b40 ldr r3, [pc, #256] ; (8004538 ) + 8004438: edd3 7a00 vldr s15, [r3] + 800443c: eddf 6a43 vldr s13, [pc, #268] ; 800454c + 8004440: ee67 7aa6 vmul.f32 s15, s15, s13 + 8004444: ee37 7a67 vsub.f32 s14, s14, s15 + 8004448: eddf 6a41 vldr s13, [pc, #260] ; 8004550 + 800444c: eec7 7a26 vdiv.f32 s15, s14, s13 + 8004450: 4b3a ldr r3, [pc, #232] ; (800453c ) + 8004452: edc3 7a00 vstr s15, [r3] snprintf(str,15, "%0.0fmin",min); - 8003b54: 4b88 ldr r3, [pc, #544] ; (8003d78 ) - 8003b56: 681b ldr r3, [r3, #0] - 8003b58: 4618 mov r0, r3 - 8003b5a: f7fc fcf5 bl 8000548 <__aeabi_f2d> - 8003b5e: 4602 mov r2, r0 - 8003b60: 460b mov r3, r1 - 8003b62: e9cd 2300 strd r2, r3, [sp] - 8003b66: 4a87 ldr r2, [pc, #540] ; (8003d84 ) - 8003b68: 210f movs r1, #15 - 8003b6a: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003b6e: f00e fedd bl 801292c + 8004456: 4b38 ldr r3, [pc, #224] ; (8004538 ) + 8004458: 681b ldr r3, [r3, #0] + 800445a: 4618 mov r0, r3 + 800445c: f7fc f874 bl 8000548 <__aeabi_f2d> + 8004460: 4602 mov r2, r0 + 8004462: 460b mov r3, r1 + 8004464: e9cd 2300 strd r2, r3, [sp] + 8004468: 4a3a ldr r2, [pc, #232] ; (8004554 ) + 800446a: 210f movs r1, #15 + 800446c: 6d38 ldr r0, [r7, #80] ; 0x50 + 800446e: f010 fcb5 bl 8014ddc ssd1306_WriteString(str, Font_7x10, White); - 8003b72: 4a85 ldr r2, [pc, #532] ; (8003d88 ) - 8003b74: 2301 movs r3, #1 - 8003b76: ca06 ldmia r2, {r1, r2} - 8003b78: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003b7c: f7fe fbc6 bl 800230c + 8004472: 4a39 ldr r2, [pc, #228] ; (8004558 ) + 8004474: 2301 movs r3, #1 + 8004476: ca06 ldmia r2, {r1, r2} + 8004478: 6d38 ldr r0, [r7, #80] ; 0x50 + 800447a: f7fe fa75 bl 8002968 ssd1306_SetCursor(32, 50); - 8003b80: 2132 movs r1, #50 ; 0x32 - 8003b82: 2020 movs r0, #32 - 8003b84: f7fe fbe8 bl 8002358 + 800447e: 2132 movs r1, #50 ; 0x32 + 8004480: 2020 movs r0, #32 + 8004482: f7fe fa97 bl 80029b4 snprintf(str,15, "%0.3fsec",seconde); - 8003b88: 4b7d ldr r3, [pc, #500] ; (8003d80 ) - 8003b8a: 681b ldr r3, [r3, #0] - 8003b8c: 4618 mov r0, r3 - 8003b8e: f7fc fcdb bl 8000548 <__aeabi_f2d> - 8003b92: 4602 mov r2, r0 - 8003b94: 460b mov r3, r1 - 8003b96: e9cd 2300 strd r2, r3, [sp] - 8003b9a: 4a7c ldr r2, [pc, #496] ; (8003d8c ) - 8003b9c: 210f movs r1, #15 - 8003b9e: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003ba2: f00e fec3 bl 801292c + 8004486: 4b2d ldr r3, [pc, #180] ; (800453c ) + 8004488: 681b ldr r3, [r3, #0] + 800448a: 4618 mov r0, r3 + 800448c: f7fc f85c bl 8000548 <__aeabi_f2d> + 8004490: 4602 mov r2, r0 + 8004492: 460b mov r3, r1 + 8004494: e9cd 2300 strd r2, r3, [sp] + 8004498: 4a30 ldr r2, [pc, #192] ; (800455c ) + 800449a: 210f movs r1, #15 + 800449c: 6d38 ldr r0, [r7, #80] ; 0x50 + 800449e: f010 fc9d bl 8014ddc ssd1306_WriteString(str, Font_6x8, White); - 8003ba6: 4a7a ldr r2, [pc, #488] ; (8003d90 ) - 8003ba8: 2301 movs r3, #1 - 8003baa: ca06 ldmia r2, {r1, r2} - 8003bac: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003bb0: f7fe fbac bl 800230c + 80044a2: 4a1a ldr r2, [pc, #104] ; (800450c ) + 80044a4: 2301 movs r3, #1 + 80044a6: ca06 ldmia r2, {r1, r2} + 80044a8: 6d38 ldr r0, [r7, #80] ; 0x50 + 80044aa: f7fe fa5d bl 8002968 free(str); - 8003bb4: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003bb8: f00c ffc4 bl 8010b44 + 80044ae: 6d38 ldr r0, [r7, #80] ; 0x50 + 80044b0: f00e fda0 bl 8012ff4 if(BTN_A>=1){ - 8003bbc: 4b75 ldr r3, [pc, #468] ; (8003d94 ) - 8003bbe: 681b ldr r3, [r3, #0] - 8003bc0: 2b00 cmp r3, #0 - 8003bc2: f340 80ca ble.w 8003d5a - state++; - 8003bc6: 4b74 ldr r3, [pc, #464] ; (8003d98 ) - 8003bc8: 781b ldrb r3, [r3, #0] - 8003bca: 3301 adds r3, #1 - 8003bcc: b2da uxtb r2, r3 - 8003bce: 4b72 ldr r3, [pc, #456] ; (8003d98 ) - 8003bd0: 701a strb r2, [r3, #0] - uint8_t baudchange[]={0x24, 0x50, 0x4D, 0x54,0x4B ,0x32, 0x35 ,0x31 ,0x2C ,0x33, 0x38, 0x34 ,0x30, 0x30 ,0x2A, 0x32 ,0x37, 0x0A}; - 8003bd2: 4b72 ldr r3, [pc, #456] ; (8003d9c ) - 8003bd4: f107 0444 add.w r4, r7, #68 ; 0x44 - 8003bd8: 461d mov r5, r3 - 8003bda: cd0f ldmia r5!, {r0, r1, r2, r3} - 8003bdc: c40f stmia r4!, {r0, r1, r2, r3} - 8003bde: 682b ldr r3, [r5, #0] - 8003be0: 8023 strh r3, [r4, #0] - __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT); - 8003be2: 4b6f ldr r3, [pc, #444] ; (8003da0 ) - 8003be4: 681b ldr r3, [r3, #0] - 8003be6: 681a ldr r2, [r3, #0] - 8003be8: 4b6d ldr r3, [pc, #436] ; (8003da0 ) - 8003bea: 681b ldr r3, [r3, #0] - 8003bec: f022 0204 bic.w r2, r2, #4 - 8003bf0: 601a str r2, [r3, #0] - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)baudchange,18); - 8003bf2: f107 0344 add.w r3, r7, #68 ; 0x44 - 8003bf6: 2212 movs r2, #18 - 8003bf8: 4619 mov r1, r3 - 8003bfa: 486a ldr r0, [pc, #424] ; (8003da4 ) - 8003bfc: f006 fee0 bl 800a9c0 - uint8_t disablenmea[]={0x24, 0x50, 0x4D, 0x54, 0x4B, 0x33, 0x31, 0x34, 0x2C, 0x30, 0x2C, 0x31, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, - 8003c00: 4b69 ldr r3, [pc, #420] ; (8003da8 ) - 8003c02: 463c mov r4, r7 - 8003c04: 461d mov r5, r3 - 8003c06: cd0f ldmia r5!, {r0, r1, r2, r3} - 8003c08: c40f stmia r4!, {r0, r1, r2, r3} - 8003c0a: cd0f ldmia r5!, {r0, r1, r2, r3} - 8003c0c: c40f stmia r4!, {r0, r1, r2, r3} - 8003c0e: cd0f ldmia r5!, {r0, r1, r2, r3} - 8003c10: c40f stmia r4!, {r0, r1, r2, r3} - 8003c12: 682b ldr r3, [r5, #0] - 8003c14: 7023 strb r3, [r4, #0] - 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2A, 0x32, 0x39};//$PMTK314,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0*29 - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)disablenmea,49); - 8003c16: 463b mov r3, r7 - 8003c18: 2231 movs r2, #49 ; 0x31 - 8003c1a: 4619 mov r1, r3 - 8003c1c: 4861 ldr r0, [pc, #388] ; (8003da4 ) - 8003c1e: f006 fecf bl 800a9c0 - uint8_t updaterate[]={0x24, 0x50, 0x4D, 0x54, 0x4B, 0x32, 0x32, 0x30, 0x2C, 0x20, 0x32, 0x30, 0x30, 0x2A, 0x32, 0x43};//$PMTK220, 200*2C - 8003c22: 4b62 ldr r3, [pc, #392] ; (8003dac ) - 8003c24: f107 0434 add.w r4, r7, #52 ; 0x34 - 8003c28: cb0f ldmia r3, {r0, r1, r2, r3} - 8003c2a: e884 000f stmia.w r4, {r0, r1, r2, r3} - HAL_UART_Transmit_IT(&hlpuart1,(uint8_t *)updaterate,16); - 8003c2e: f107 0334 add.w r3, r7, #52 ; 0x34 - 8003c32: 2210 movs r2, #16 - 8003c34: 4619 mov r1, r3 - 8003c36: 485b ldr r0, [pc, #364] ; (8003da4 ) - 8003c38: f006 fec2 bl 800a9c0 - HAL_UART_Abort(&hlpuart1); - 8003c3c: 4859 ldr r0, [pc, #356] ; (8003da4 ) - 8003c3e: f006 ff69 bl 800ab14 - HAL_UART_DeInit(&hlpuart1); - 8003c42: 4858 ldr r0, [pc, #352] ; (8003da4 ) - 8003c44: f006 fe7e bl 800a944 - hlpuart1.Init.BaudRate = 38400; - 8003c48: 4b56 ldr r3, [pc, #344] ; (8003da4 ) - 8003c4a: f44f 4216 mov.w r2, #38400 ; 0x9600 - 8003c4e: 605a str r2, [r3, #4] - HAL_UART_Init(&hlpuart1); - 8003c50: 4854 ldr r0, [pc, #336] ; (8003da4 ) - 8003c52: f006 fe29 bl 800a8a8 - HAL_UART_Abort(&hlpuart1); - 8003c56: 4853 ldr r0, [pc, #332] ; (8003da4 ) - 8003c58: f006 ff5c bl 800ab14 - HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE); - 8003c5c: 2240 movs r2, #64 ; 0x40 - 8003c5e: 4954 ldr r1, [pc, #336] ; (8003db0 ) - 8003c60: 4850 ldr r0, [pc, #320] ; (8003da4 ) - 8003c62: f006 ff0b bl 800aa7c + 80044b4: 4b1b ldr r3, [pc, #108] ; (8004524 ) + 80044b6: 681b ldr r3, [r3, #0] + 80044b8: 2b00 cmp r3, #0 + 80044ba: f340 829b ble.w 80049f4 + state++; + 80044be: 4b1a ldr r3, [pc, #104] ; (8004528 ) + 80044c0: 781b ldrb r3, [r3, #0] + 80044c2: 3301 adds r3, #1 + 80044c4: b2da uxtb r2, r3 + 80044c6: 4b18 ldr r3, [pc, #96] ; (8004528 ) + 80044c8: 701a strb r2, [r3, #0] BTN_A=0; - 8003c66: 4b4b ldr r3, [pc, #300] ; (8003d94 ) - 8003c68: 2200 movs r2, #0 - 8003c6a: 601a str r2, [r3, #0] + 80044ca: 4b16 ldr r3, [pc, #88] ; (8004524 ) + 80044cc: 2200 movs r2, #0 + 80044ce: 601a str r2, [r3, #0] BTN_B=0; - 8003c6c: 4b51 ldr r3, [pc, #324] ; (8003db4 ) - 8003c6e: 2200 movs r2, #0 - 8003c70: 601a str r2, [r3, #0] + 80044d0: 4b16 ldr r3, [pc, #88] ; (800452c ) + 80044d2: 2200 movs r2, #0 + 80044d4: 601a str r2, [r3, #0] } break; - 8003c72: e072 b.n 8003d5a - case STATE_MEMTEST: - ssd1306_Fill(Black); - 8003c74: 2000 movs r0, #0 - 8003c76: f7fe fa2d bl 80020d4 - ssd1306_SetCursor(32, 32); - 8003c7a: 2120 movs r1, #32 - 8003c7c: 2020 movs r0, #32 - 8003c7e: f7fe fb6b bl 8002358 - ssd1306_WriteString("test", Font_6x8, White); - 8003c82: 4a43 ldr r2, [pc, #268] ; (8003d90 ) - 8003c84: 2301 movs r3, #1 - 8003c86: ca06 ldmia r2, {r1, r2} - 8003c88: 484b ldr r0, [pc, #300] ; (8003db8 ) - 8003c8a: f7fe fb3f bl 800230c - nmea_parse(&myData, DataBuffer); - 8003c8e: 494b ldr r1, [pc, #300] ; (8003dbc ) - 8003c90: 484b ldr r0, [pc, #300] ; (8003dc0 ) - 8003c92: f7fe f8cb bl 8001e2c - - snprintf(str,15, "spd=%.1f",myData.speed);//sert a connaitre la qualitée du fix si proche de 1 voir inférieur alors le fix est tres bon - 8003c96: 4b4a ldr r3, [pc, #296] ; (8003dc0 ) - 8003c98: 6b9b ldr r3, [r3, #56] ; 0x38 - 8003c9a: 4618 mov r0, r3 - 8003c9c: f7fc fc54 bl 8000548 <__aeabi_f2d> - 8003ca0: 4602 mov r2, r0 - 8003ca2: 460b mov r3, r1 - 8003ca4: e9cd 2300 strd r2, r3, [sp] - 8003ca8: 4a46 ldr r2, [pc, #280] ; (8003dc4 ) - 8003caa: 210f movs r1, #15 - 8003cac: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003cb0: f00e fe3c bl 801292c - ssd1306_SetCursor(32, 40); - 8003cb4: 2128 movs r1, #40 ; 0x28 - 8003cb6: 2020 movs r0, #32 - 8003cb8: f7fe fb4e bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8003cbc: 4a34 ldr r2, [pc, #208] ; (8003d90 ) - 8003cbe: 2301 movs r3, #1 - 8003cc0: ca06 ldmia r2, {r1, r2} - 8003cc2: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003cc6: f7fe fb21 bl 800230c - snprintf(str,15, "SatNb :%d",myData.satelliteCount); - 8003cca: 4b3d ldr r3, [pc, #244] ; (8003dc0 ) - 8003ccc: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003cce: 4a3e ldr r2, [pc, #248] ; (8003dc8 ) - 8003cd0: 210f movs r1, #15 - 8003cd2: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003cd6: f00e fe29 bl 801292c - ssd1306_SetCursor(32, 48); - 8003cda: 2130 movs r1, #48 ; 0x30 - 8003cdc: 2020 movs r0, #32 - 8003cde: f7fe fb3b bl 8002358 - ssd1306_WriteString(str, Font_6x8, White); - 8003ce2: 4a2b ldr r2, [pc, #172] ; (8003d90 ) - 8003ce4: 2301 movs r3, #1 - 8003ce6: ca06 ldmia r2, {r1, r2} - 8003ce8: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003cec: f7fe fb0e bl 800230c - free(str); - 8003cf0: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 - 8003cf4: f00c ff26 bl 8010b44 - - - - if(BTN_A>=1){ - 8003cf8: 4b26 ldr r3, [pc, #152] ; (8003d94 ) - 8003cfa: 681b ldr r3, [r3, #0] - 8003cfc: 2b00 cmp r3, #0 - 8003cfe: dd2e ble.n 8003d5e - state--; - 8003d00: 4b25 ldr r3, [pc, #148] ; (8003d98 ) - 8003d02: 781b ldrb r3, [r3, #0] - 8003d04: 3b01 subs r3, #1 - 8003d06: b2da uxtb r2, r3 - 8003d08: 4b23 ldr r3, [pc, #140] ; (8003d98 ) - 8003d0a: 701a strb r2, [r3, #0] - state--; - 8003d0c: 4b22 ldr r3, [pc, #136] ; (8003d98 ) - 8003d0e: 781b ldrb r3, [r3, #0] - 8003d10: 3b01 subs r3, #1 - 8003d12: b2da uxtb r2, r3 - 8003d14: 4b20 ldr r3, [pc, #128] ; (8003d98 ) - 8003d16: 701a strb r2, [r3, #0] - state--; - 8003d18: 4b1f ldr r3, [pc, #124] ; (8003d98 ) - 8003d1a: 781b ldrb r3, [r3, #0] - 8003d1c: 3b01 subs r3, #1 - 8003d1e: b2da uxtb r2, r3 - 8003d20: 4b1d ldr r3, [pc, #116] ; (8003d98 ) - 8003d22: 701a strb r2, [r3, #0] - state--; - 8003d24: 4b1c ldr r3, [pc, #112] ; (8003d98 ) - 8003d26: 781b ldrb r3, [r3, #0] - 8003d28: 3b01 subs r3, #1 - 8003d2a: b2da uxtb r2, r3 - 8003d2c: 4b1a ldr r3, [pc, #104] ; (8003d98 ) - 8003d2e: 701a strb r2, [r3, #0] - state--; - 8003d30: 4b19 ldr r3, [pc, #100] ; (8003d98 ) - 8003d32: 781b ldrb r3, [r3, #0] - 8003d34: 3b01 subs r3, #1 - 8003d36: b2da uxtb r2, r3 - 8003d38: 4b17 ldr r3, [pc, #92] ; (8003d98 ) - 8003d3a: 701a strb r2, [r3, #0] - BTN_A=0; - 8003d3c: 4b15 ldr r3, [pc, #84] ; (8003d94 ) - 8003d3e: 2200 movs r2, #0 - 8003d40: 601a str r2, [r3, #0] - BTN_B=0; - 8003d42: 4b1c ldr r3, [pc, #112] ; (8003db4 ) - 8003d44: 2200 movs r2, #0 - 8003d46: 601a str r2, [r3, #0] - } - - - - - break; - 8003d48: e009 b.n 8003d5e - break; - 8003d4a: bf00 nop - 8003d4c: e008 b.n 8003d60 - break; - 8003d4e: bf00 nop - 8003d50: e006 b.n 8003d60 - break; - 8003d52: bf00 nop - 8003d54: e004 b.n 8003d60 - break; - 8003d56: bf00 nop - 8003d58: e002 b.n 8003d60 - break; - 8003d5a: bf00 nop - 8003d5c: e000 b.n 8003d60 - break; - 8003d5e: bf00 nop - - - } - -return ; - 8003d60: bf00 nop - 8003d62: bf00 nop -} - 8003d64: 37bc adds r7, #188 ; 0xbc - 8003d66: 46bd mov sp, r7 - 8003d68: ecbd 8b02 vpop {d8} - 8003d6c: bdf0 pop {r4, r5, r6, r7, pc} - 8003d6e: bf00 nop - 8003d70: 20000c90 .word 0x20000c90 - 8003d74: 476a6000 .word 0x476a6000 - 8003d78: 20000c88 .word 0x20000c88 - 8003d7c: 447a0000 .word 0x447a0000 - 8003d80: 20000c84 .word 0x20000c84 - 8003d84: 08016a3c .word 0x08016a3c - 8003d88: 20000010 .word 0x20000010 - 8003d8c: 08016a48 .word 0x08016a48 - 8003d90: 20000008 .word 0x20000008 - 8003d94: 20000820 .word 0x20000820 - 8003d98: 20000828 .word 0x20000828 - 8003d9c: 08016a68 .word 0x08016a68 - 8003da0: 200004bc .word 0x200004bc - 8003da4: 20000434 .word 0x20000434 - 8003da8: 08016a7c .word 0x08016a7c - 8003dac: 08016ab0 .word 0x08016ab0 - 8003db0: 200005a0 .word 0x200005a0 - 8003db4: 20000824 .word 0x20000824 - 8003db8: 08016a54 .word 0x08016a54 - 8003dbc: 200005e0 .word 0x200005e0 - 8003dc0: 200007e0 .word 0x200007e0 - 8003dc4: 08016a5c .word 0x08016a5c - 8003dc8: 08016a14 .word 0x08016a14 - -08003dcc : -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - 8003dcc: b480 push {r7} - 8003dce: b083 sub sp, #12 - 8003dd0: af00 add r7, sp, #0 - /* USER CODE BEGIN MspInit 0 */ + 80044d6: e28d b.n 80049f4 - /* USER CODE END MspInit 0 */ + case STATE_BALISE: + ssd1306_Fill(Black); + 80044d8: 2000 movs r0, #0 + 80044da: f7fe f929 bl 8002730 + ssd1306_SetCursor(32,32); + 80044de: 2120 movs r1, #32 + 80044e0: 2020 movs r0, #32 + 80044e2: f7fe fa67 bl 80029b4 + ssd1306_WriteString("balise",Font_6x8,White); + 80044e6: 4a09 ldr r2, [pc, #36] ; (800450c ) + 80044e8: 2301 movs r3, #1 + 80044ea: ca06 ldmia r2, {r1, r2} + 80044ec: 481c ldr r0, [pc, #112] ; (8004560 ) + 80044ee: f7fe fa3b bl 8002968 + switch(balisestate){ + 80044f2: 4b1c ldr r3, [pc, #112] ; (8004564 ) + 80044f4: 781b ldrb r3, [r3, #0] + 80044f6: 2b02 cmp r3, #2 + 80044f8: f000 80b5 beq.w 8004666 + 80044fc: 2b02 cmp r3, #2 + 80044fe: f300 80df bgt.w 80046c0 + 8004502: 2b00 cmp r3, #0 + 8004504: d030 beq.n 8004568 + 8004506: 2b01 cmp r3, #1 + 8004508: d04a beq.n 80045a0 + 800450a: e0d9 b.n 80046c0 + 800450c: 20000008 .word 0x20000008 + 8004510: 08018f20 .word 0x08018f20 + 8004514: 20000730 .word 0x20000730 + 8004518: 08018f28 .word 0x08018f28 + 800451c: 20000728 .word 0x20000728 + 8004520: 08018f14 .word 0x08018f14 + 8004524: 200006f0 .word 0x200006f0 + 8004528: 200006f8 .word 0x200006f8 + 800452c: 200006f4 .word 0x200006f4 + 8004530: 08018f34 .word 0x08018f34 + 8004534: 200006fc .word 0x200006fc + 8004538: 20000e3c .word 0x20000e3c + 800453c: 20000e38 .word 0x20000e38 + 8004540: 20000e44 .word 0x20000e44 + 8004544: 20001048 .word 0x20001048 + 8004548: 20000e40 .word 0x20000e40 + 800454c: 476a6000 .word 0x476a6000 + 8004550: 447a0000 .word 0x447a0000 + 8004554: 08018f3c .word 0x08018f3c + 8004558: 20000010 .word 0x20000010 + 800455c: 08018f48 .word 0x08018f48 + 8004560: 08018f54 .word 0x08018f54 + 8004564: 20000e33 .word 0x20000e33 + case BALISESTATE1: + ssd1306_SetCursor(32,40); + 8004568: 2128 movs r1, #40 ; 0x28 + 800456a: 2020 movs r0, #32 + 800456c: f7fe fa22 bl 80029b4 + ssd1306_WriteString("do nothing",Font_6x8,White); + 8004570: 4a90 ldr r2, [pc, #576] ; (80047b4 ) + 8004572: 2301 movs r3, #1 + 8004574: ca06 ldmia r2, {r1, r2} + 8004576: 4890 ldr r0, [pc, #576] ; (80047b8 ) + 8004578: f7fe f9f6 bl 8002968 - __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8003dd2: 4b0f ldr r3, [pc, #60] ; (8003e10 ) - 8003dd4: 6e1b ldr r3, [r3, #96] ; 0x60 - 8003dd6: 4a0e ldr r2, [pc, #56] ; (8003e10 ) - 8003dd8: f043 0301 orr.w r3, r3, #1 - 8003ddc: 6613 str r3, [r2, #96] ; 0x60 - 8003dde: 4b0c ldr r3, [pc, #48] ; (8003e10 ) - 8003de0: 6e1b ldr r3, [r3, #96] ; 0x60 - 8003de2: f003 0301 and.w r3, r3, #1 - 8003de6: 607b str r3, [r7, #4] - 8003de8: 687b ldr r3, [r7, #4] - __HAL_RCC_PWR_CLK_ENABLE(); - 8003dea: 4b09 ldr r3, [pc, #36] ; (8003e10 ) - 8003dec: 6d9b ldr r3, [r3, #88] ; 0x58 - 8003dee: 4a08 ldr r2, [pc, #32] ; (8003e10 ) - 8003df0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8003df4: 6593 str r3, [r2, #88] ; 0x58 - 8003df6: 4b06 ldr r3, [pc, #24] ; (8003e10 ) - 8003df8: 6d9b ldr r3, [r3, #88] ; 0x58 - 8003dfa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8003dfe: 603b str r3, [r7, #0] - 8003e00: 683b ldr r3, [r7, #0] - /* System interrupt init*/ + if(BTN_B>=1){ + 800457c: 4b8f ldr r3, [pc, #572] ; (80047bc ) + 800457e: 681b ldr r3, [r3, #0] + 8004580: 2b00 cmp r3, #0 + 8004582: f340 809a ble.w 80046ba + balisestate++; + 8004586: 4b8e ldr r3, [pc, #568] ; (80047c0 ) + 8004588: 781b ldrb r3, [r3, #0] + 800458a: 3301 adds r3, #1 + 800458c: b2da uxtb r2, r3 + 800458e: 4b8c ldr r3, [pc, #560] ; (80047c0 ) + 8004590: 701a strb r2, [r3, #0] + BTN_B=0; + 8004592: 4b8a ldr r3, [pc, #552] ; (80047bc ) + 8004594: 2200 movs r2, #0 + 8004596: 601a str r2, [r3, #0] + BTN_A=0; + 8004598: 4b8a ldr r3, [pc, #552] ; (80047c4 ) + 800459a: 2200 movs r2, #0 + 800459c: 601a str r2, [r3, #0] + } - /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END MspInit 1 */ -} - 8003e02: bf00 nop - 8003e04: 370c adds r7, #12 - 8003e06: 46bd mov sp, r7 - 8003e08: f85d 7b04 ldr.w r7, [sp], #4 - 8003e0c: 4770 bx lr - 8003e0e: bf00 nop - 8003e10: 40021000 .word 0x40021000 - -08003e14 : -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - 8003e14: b580 push {r7, lr} - 8003e16: b08a sub sp, #40 ; 0x28 - 8003e18: af00 add r7, sp, #0 - 8003e1a: 6078 str r0, [r7, #4] - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8003e1c: f107 0314 add.w r3, r7, #20 - 8003e20: 2200 movs r2, #0 - 8003e22: 601a str r2, [r3, #0] - 8003e24: 605a str r2, [r3, #4] - 8003e26: 609a str r2, [r3, #8] - 8003e28: 60da str r2, [r3, #12] - 8003e2a: 611a str r2, [r3, #16] - if(hadc->Instance==ADC1) - 8003e2c: 687b ldr r3, [r7, #4] - 8003e2e: 681b ldr r3, [r3, #0] - 8003e30: 4a2f ldr r2, [pc, #188] ; (8003ef0 ) - 8003e32: 4293 cmp r3, r2 - 8003e34: d157 bne.n 8003ee6 - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ADC_CLK_ENABLE(); - 8003e36: 4b2f ldr r3, [pc, #188] ; (8003ef4 ) - 8003e38: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003e3a: 4a2e ldr r2, [pc, #184] ; (8003ef4 ) - 8003e3c: f443 5300 orr.w r3, r3, #8192 ; 0x2000 - 8003e40: 64d3 str r3, [r2, #76] ; 0x4c - 8003e42: 4b2c ldr r3, [pc, #176] ; (8003ef4 ) - 8003e44: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003e46: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8003e4a: 613b str r3, [r7, #16] - 8003e4c: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOA_CLK_ENABLE(); - 8003e4e: 4b29 ldr r3, [pc, #164] ; (8003ef4 ) - 8003e50: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003e52: 4a28 ldr r2, [pc, #160] ; (8003ef4 ) - 8003e54: f043 0301 orr.w r3, r3, #1 - 8003e58: 64d3 str r3, [r2, #76] ; 0x4c - 8003e5a: 4b26 ldr r3, [pc, #152] ; (8003ef4 ) - 8003e5c: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003e5e: f003 0301 and.w r3, r3, #1 - 8003e62: 60fb str r3, [r7, #12] - 8003e64: 68fb ldr r3, [r7, #12] - /**ADC1 GPIO Configuration - PA4 ------> ADC1_IN9 - */ - GPIO_InitStruct.Pin = GPIO_PIN_4; - 8003e66: 2310 movs r3, #16 - 8003e68: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL; - 8003e6a: 230b movs r3, #11 - 8003e6c: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003e6e: 2300 movs r3, #0 - 8003e70: 61fb str r3, [r7, #28] - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8003e72: f107 0314 add.w r3, r7, #20 - 8003e76: 4619 mov r1, r3 - 8003e78: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 8003e7c: f002 fac6 bl 800640c + break; + 800459e: e08c b.n 80046ba + case BALISESTATE2: + + nmea_parse(&myData, DataBuffer); + 80045a0: 4989 ldr r1, [pc, #548] ; (80047c8 ) + 80045a2: 488a ldr r0, [pc, #552] ; (80047cc ) + 80045a4: f7fd fd42 bl 800202c + if(pagenumber+1) + 80045aa: 681b ldr r3, [r3, #0] + 80045ac: f246 32fd movw r2, #25597 ; 0x63fd + 80045b0: 4293 cmp r3, r2 + 80045b2: dc54 bgt.n 800465e + + flashbufferlen=csvframe((uint8_t *)flashwrite,temp,vbat,&myData,0,0.0); + 80045b4: 4b87 ldr r3, [pc, #540] ; (80047d4 ) + 80045b6: edd3 7a00 vldr s15, [r3] + 80045ba: 4b87 ldr r3, [pc, #540] ; (80047d8 ) + 80045bc: ed93 7a00 vldr s14, [r3] + 80045c0: ed9f 1a86 vldr s2, [pc, #536] ; 80047dc + 80045c4: 2200 movs r2, #0 + 80045c6: 4981 ldr r1, [pc, #516] ; (80047cc ) + 80045c8: eef0 0a47 vmov.f32 s1, s14 + 80045cc: eeb0 0a67 vmov.f32 s0, s15 + 80045d0: 4883 ldr r0, [pc, #524] ; (80047e0 ) + 80045d2: f7fd fe79 bl 80022c8 + 80045d6: 4603 mov r3, r0 + 80045d8: 4a82 ldr r2, [pc, #520] ; (80047e4 ) + 80045da: 6013 str r3, [r2, #0] + writebuffertoflash((uint8_t*)flashwrite,flashbufferlen); + 80045dc: 4b81 ldr r3, [pc, #516] ; (80047e4 ) + 80045de: 681b ldr r3, [r3, #0] + 80045e0: 4619 mov r1, r3 + 80045e2: 487f ldr r0, [pc, #508] ; (80047e0 ) + 80045e4: f7fd ff74 bl 80024d0 + ssd1306_SetCursor(32,40); + 80045e8: 2128 movs r1, #40 ; 0x28 + 80045ea: 2020 movs r0, #32 + 80045ec: f7fe f9e2 bl 80029b4 + snprintf((uint8_t *)str1,50,"%d,%d",pageoffset,pagenumber); + 80045f0: 4b7d ldr r3, [pc, #500] ; (80047e8 ) + 80045f2: 681a ldr r2, [r3, #0] + 80045f4: 4b76 ldr r3, [pc, #472] ; (80047d0 ) + 80045f6: 681b ldr r3, [r3, #0] + 80045f8: 9300 str r3, [sp, #0] + 80045fa: 4613 mov r3, r2 + 80045fc: 4a7b ldr r2, [pc, #492] ; (80047ec ) + 80045fe: 2132 movs r1, #50 ; 0x32 + 8004600: 487b ldr r0, [pc, #492] ; (80047f0 ) + 8004602: f010 fbeb bl 8014ddc + ssd1306_WriteString((uint8_t*)str1,Font_6x8,White); + 8004606: 4a6b ldr r2, [pc, #428] ; (80047b4 ) + 8004608: 2301 movs r3, #1 + 800460a: ca06 ldmia r2, {r1, r2} + 800460c: 4878 ldr r0, [pc, #480] ; (80047f0 ) + 800460e: f7fe f9ab bl 8002968 + ssd1306_SetCursor(32,48); + 8004612: 2130 movs r1, #48 ; 0x30 + 8004614: 2020 movs r0, #32 + 8004616: f7fe f9cd bl 80029b4 + snprintf((uint8_t *)str1,50, "len=%d",flashbufferlen); + 800461a: 4b72 ldr r3, [pc, #456] ; (80047e4 ) + 800461c: 681b ldr r3, [r3, #0] + 800461e: 4a75 ldr r2, [pc, #468] ; (80047f4 ) + 8004620: 2132 movs r1, #50 ; 0x32 + 8004622: 4873 ldr r0, [pc, #460] ; (80047f0 ) + 8004624: f010 fbda bl 8014ddc + ssd1306_WriteString((uint8_t*)str1,Font_6x8,White); + 8004628: 4a62 ldr r2, [pc, #392] ; (80047b4 ) + 800462a: 2301 movs r3, #1 + 800462c: ca06 ldmia r2, {r1, r2} + 800462e: 4870 ldr r0, [pc, #448] ; (80047f0 ) + 8004630: f7fe f99a bl 8002968 + HAL_Delay(1000); + 8004634: f44f 707a mov.w r0, #1000 ; 0x3e8 + 8004638: f000 fe16 bl 8005268 + if(BTN_B>=1){ + 800463c: 4b5f ldr r3, [pc, #380] ; (80047bc ) + 800463e: 681b ldr r3, [r3, #0] + 8004640: 2b00 cmp r3, #0 + 8004642: dd3c ble.n 80046be + balisestate--; + 8004644: 4b5e ldr r3, [pc, #376] ; (80047c0 ) + 8004646: 781b ldrb r3, [r3, #0] + 8004648: 3b01 subs r3, #1 + 800464a: b2da uxtb r2, r3 + 800464c: 4b5c ldr r3, [pc, #368] ; (80047c0 ) + 800464e: 701a strb r2, [r3, #0] + BTN_B=0; + 8004650: 4b5a ldr r3, [pc, #360] ; (80047bc ) + 8004652: 2200 movs r2, #0 + 8004654: 601a str r2, [r3, #0] + BTN_A=0; + 8004656: 4b5b ldr r3, [pc, #364] ; (80047c4 ) + 8004658: 2200 movs r2, #0 + 800465a: 601a str r2, [r3, #0] + balisestate=2; + } - /* ADC1 DMA Init */ - /* ADC1 Init */ - hdma_adc1.Instance = DMA1_Channel1; - 8003e80: 4b1d ldr r3, [pc, #116] ; (8003ef8 ) - 8003e82: 4a1e ldr r2, [pc, #120] ; (8003efc ) - 8003e84: 601a str r2, [r3, #0] - hdma_adc1.Init.Request = DMA_REQUEST_0; - 8003e86: 4b1c ldr r3, [pc, #112] ; (8003ef8 ) - 8003e88: 2200 movs r2, #0 - 8003e8a: 605a str r2, [r3, #4] - hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; - 8003e8c: 4b1a ldr r3, [pc, #104] ; (8003ef8 ) - 8003e8e: 2200 movs r2, #0 - 8003e90: 609a str r2, [r3, #8] - hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; - 8003e92: 4b19 ldr r3, [pc, #100] ; (8003ef8 ) - 8003e94: 2200 movs r2, #0 - 8003e96: 60da str r2, [r3, #12] - hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; - 8003e98: 4b17 ldr r3, [pc, #92] ; (8003ef8 ) - 8003e9a: 2280 movs r2, #128 ; 0x80 - 8003e9c: 611a str r2, [r3, #16] - hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - 8003e9e: 4b16 ldr r3, [pc, #88] ; (8003ef8 ) - 8003ea0: f44f 7280 mov.w r2, #256 ; 0x100 - 8003ea4: 615a str r2, [r3, #20] - hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - 8003ea6: 4b14 ldr r3, [pc, #80] ; (8003ef8 ) - 8003ea8: f44f 6280 mov.w r2, #1024 ; 0x400 - 8003eac: 619a str r2, [r3, #24] - hdma_adc1.Init.Mode = DMA_NORMAL; - 8003eae: 4b12 ldr r3, [pc, #72] ; (8003ef8 ) - 8003eb0: 2200 movs r2, #0 - 8003eb2: 61da str r2, [r3, #28] - hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; - 8003eb4: 4b10 ldr r3, [pc, #64] ; (8003ef8 ) - 8003eb6: 2200 movs r2, #0 - 8003eb8: 621a str r2, [r3, #32] - if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) - 8003eba: 480f ldr r0, [pc, #60] ; (8003ef8 ) - 8003ebc: f001 ff92 bl 8005de4 - 8003ec0: 4603 mov r3, r0 - 8003ec2: 2b00 cmp r3, #0 - 8003ec4: d001 beq.n 8003eca - { - Error_Handler(); - 8003ec6: f7fd fc97 bl 80017f8 - } - __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); - 8003eca: 687b ldr r3, [r7, #4] - 8003ecc: 4a0a ldr r2, [pc, #40] ; (8003ef8 ) - 8003ece: 64da str r2, [r3, #76] ; 0x4c - 8003ed0: 4a09 ldr r2, [pc, #36] ; (8003ef8 ) - 8003ed2: 687b ldr r3, [r7, #4] - 8003ed4: 6293 str r3, [r2, #40] ; 0x28 - /* ADC1 interrupt Init */ - HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); - 8003ed6: 2200 movs r2, #0 - 8003ed8: 2100 movs r1, #0 - 8003eda: 2012 movs r0, #18 - 8003edc: f001 ff3d bl 8005d5a - HAL_NVIC_EnableIRQ(ADC1_IRQn); - 8003ee0: 2012 movs r0, #18 - 8003ee2: f001 ff56 bl 8005d92 - /* USER CODE BEGIN ADC1_MspInit 1 */ + break; + 800465c: e02f b.n 80046be + balisestate=2; + 800465e: 4b58 ldr r3, [pc, #352] ; (80047c0 ) + 8004660: 2202 movs r2, #2 + 8004662: 701a strb r2, [r3, #0] + break; + 8004664: e02b b.n 80046be + + case BALISESTATE3: + ssd1306_SetCursor(32,32); + 8004666: 2120 movs r1, #32 + 8004668: 2020 movs r0, #32 + 800466a: f7fe f9a3 bl 80029b4 + ssd1306_WriteString("fin de",Font_6x8,White); + 800466e: 4a51 ldr r2, [pc, #324] ; (80047b4 ) + 8004670: 2301 movs r3, #1 + 8004672: ca06 ldmia r2, {r1, r2} + 8004674: 4860 ldr r0, [pc, #384] ; (80047f8 ) + 8004676: f7fe f977 bl 8002968 + ssd1306_SetCursor(32,40); + 800467a: 2128 movs r1, #40 ; 0x28 + 800467c: 2020 movs r0, #32 + 800467e: f7fe f999 bl 80029b4 + ssd1306_WriteString("memoire",Font_6x8,White); + 8004682: 4a4c ldr r2, [pc, #304] ; (80047b4 ) + 8004684: 2301 movs r3, #1 + 8004686: ca06 ldmia r2, {r1, r2} + 8004688: 485c ldr r0, [pc, #368] ; (80047fc ) + 800468a: f7fe f96d bl 8002968 + ssd1306_SetCursor(32,48); + 800468e: 2130 movs r1, #48 ; 0x30 + 8004690: 2020 movs r0, #32 + 8004692: f7fe f98f bl 80029b4 + snprintf((uint8_t *)str1,50,"%d,%d",pageoffset,pagenumber); + 8004696: 4b54 ldr r3, [pc, #336] ; (80047e8 ) + 8004698: 681a ldr r2, [r3, #0] + 800469a: 4b4d ldr r3, [pc, #308] ; (80047d0 ) + 800469c: 681b ldr r3, [r3, #0] + 800469e: 9300 str r3, [sp, #0] + 80046a0: 4613 mov r3, r2 + 80046a2: 4a52 ldr r2, [pc, #328] ; (80047ec ) + 80046a4: 2132 movs r1, #50 ; 0x32 + 80046a6: 4852 ldr r0, [pc, #328] ; (80047f0 ) + 80046a8: f010 fb98 bl 8014ddc + ssd1306_WriteString((uint8_t*)str1,Font_6x8,White); + 80046ac: 4a41 ldr r2, [pc, #260] ; (80047b4 ) + 80046ae: 2301 movs r3, #1 + 80046b0: ca06 ldmia r2, {r1, r2} + 80046b2: 484f ldr r0, [pc, #316] ; (80047f0 ) + 80046b4: f7fe f958 bl 8002968 + break; + 80046b8: e002 b.n 80046c0 + break; + 80046ba: bf00 nop + 80046bc: e000 b.n 80046c0 + break; + 80046be: bf00 nop - /* USER CODE END ADC1_MspInit 1 */ - } -} - 8003ee6: bf00 nop - 8003ee8: 3728 adds r7, #40 ; 0x28 - 8003eea: 46bd mov sp, r7 - 8003eec: bd80 pop {r7, pc} - 8003eee: bf00 nop - 8003ef0: 50040000 .word 0x50040000 - 8003ef4: 40021000 .word 0x40021000 - 8003ef8: 20000398 .word 0x20000398 - 8003efc: 40020008 .word 0x40020008 -08003f00 : -* This function configures the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) -{ - 8003f00: b580 push {r7, lr} - 8003f02: b0a0 sub sp, #128 ; 0x80 - 8003f04: af00 add r7, sp, #0 - 8003f06: 6078 str r0, [r7, #4] - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8003f08: f107 036c add.w r3, r7, #108 ; 0x6c - 8003f0c: 2200 movs r2, #0 - 8003f0e: 601a str r2, [r3, #0] - 8003f10: 605a str r2, [r3, #4] - 8003f12: 609a str r2, [r3, #8] - 8003f14: 60da str r2, [r3, #12] - 8003f16: 611a str r2, [r3, #16] - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8003f18: f107 0318 add.w r3, r7, #24 - 8003f1c: 2254 movs r2, #84 ; 0x54 - 8003f1e: 2100 movs r1, #0 - 8003f20: 4618 mov r0, r3 - 8003f22: f00e fd9a bl 8012a5a - if(hi2c->Instance==I2C3) - 8003f26: 687b ldr r3, [r7, #4] - 8003f28: 681b ldr r3, [r3, #0] - 8003f2a: 4a2e ldr r2, [pc, #184] ; (8003fe4 ) - 8003f2c: 4293 cmp r3, r2 - 8003f2e: d154 bne.n 8003fda - - /* USER CODE END I2C3_MspInit 0 */ + } - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C3; - 8003f30: f44f 7380 mov.w r3, #256 ; 0x100 - 8003f34: 61bb str r3, [r7, #24] - PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_SYSCLK; - 8003f36: f44f 3380 mov.w r3, #65536 ; 0x10000 - 8003f3a: 64bb str r3, [r7, #72] ; 0x48 - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8003f3c: f107 0318 add.w r3, r7, #24 - 8003f40: 4618 mov r0, r3 - 8003f42: f005 fda5 bl 8009a90 - 8003f46: 4603 mov r3, r0 - 8003f48: 2b00 cmp r3, #0 - 8003f4a: d001 beq.n 8003f50 - { - Error_Handler(); - 8003f4c: f7fd fc54 bl 80017f8 - } + if(BTN_A>=1){ + 80046c0: 4b40 ldr r3, [pc, #256] ; (80047c4 ) + 80046c2: 681b ldr r3, [r3, #0] + 80046c4: 2b00 cmp r3, #0 + 80046c6: f340 8197 ble.w 80049f8 + state++; + 80046ca: 4b4d ldr r3, [pc, #308] ; (8004800 ) + 80046cc: 781b ldrb r3, [r3, #0] + 80046ce: 3301 adds r3, #1 + 80046d0: b2da uxtb r2, r3 + 80046d2: 4b4b ldr r3, [pc, #300] ; (8004800 ) + 80046d4: 701a strb r2, [r3, #0] + BTN_A=0; + 80046d6: 4b3b ldr r3, [pc, #236] ; (80047c4 ) + 80046d8: 2200 movs r2, #0 + 80046da: 601a str r2, [r3, #0] + BTN_B=0; + 80046dc: 4b37 ldr r3, [pc, #220] ; (80047bc ) + 80046de: 2200 movs r2, #0 + 80046e0: 601a str r2, [r3, #0] - __HAL_RCC_GPIOA_CLK_ENABLE(); - 8003f50: 4b25 ldr r3, [pc, #148] ; (8003fe8 ) - 8003f52: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003f54: 4a24 ldr r2, [pc, #144] ; (8003fe8 ) - 8003f56: f043 0301 orr.w r3, r3, #1 - 8003f5a: 64d3 str r3, [r2, #76] ; 0x4c - 8003f5c: 4b22 ldr r3, [pc, #136] ; (8003fe8 ) - 8003f5e: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003f60: f003 0301 and.w r3, r3, #1 - 8003f64: 617b str r3, [r7, #20] - 8003f66: 697b ldr r3, [r7, #20] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 8003f68: 4b1f ldr r3, [pc, #124] ; (8003fe8 ) - 8003f6a: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003f6c: 4a1e ldr r2, [pc, #120] ; (8003fe8 ) - 8003f6e: f043 0302 orr.w r3, r3, #2 - 8003f72: 64d3 str r3, [r2, #76] ; 0x4c - 8003f74: 4b1c ldr r3, [pc, #112] ; (8003fe8 ) - 8003f76: 6cdb ldr r3, [r3, #76] ; 0x4c - 8003f78: f003 0302 and.w r3, r3, #2 - 8003f7c: 613b str r3, [r7, #16] - 8003f7e: 693b ldr r3, [r7, #16] - /**I2C3 GPIO Configuration - PA7 ------> I2C3_SCL - PB4 (NJTRST) ------> I2C3_SDA - */ - GPIO_InitStruct.Pin = GPIO_PIN_7; - 8003f80: 2380 movs r3, #128 ; 0x80 - 8003f82: 66fb str r3, [r7, #108] ; 0x6c - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - 8003f84: 2312 movs r3, #18 - 8003f86: 673b str r3, [r7, #112] ; 0x70 - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003f88: 2300 movs r3, #0 - 8003f8a: 677b str r3, [r7, #116] ; 0x74 - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8003f8c: 2303 movs r3, #3 - 8003f8e: 67bb str r3, [r7, #120] ; 0x78 - GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; - 8003f90: 2304 movs r3, #4 - 8003f92: 67fb str r3, [r7, #124] ; 0x7c - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8003f94: f107 036c add.w r3, r7, #108 ; 0x6c - 8003f98: 4619 mov r1, r3 - 8003f9a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 8003f9e: f002 fa35 bl 800640c - GPIO_InitStruct.Pin = GPIO_PIN_4; - 8003fa2: 2310 movs r3, #16 - 8003fa4: 66fb str r3, [r7, #108] ; 0x6c - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - 8003fa6: 2312 movs r3, #18 - 8003fa8: 673b str r3, [r7, #112] ; 0x70 - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8003faa: 2300 movs r3, #0 - 8003fac: 677b str r3, [r7, #116] ; 0x74 - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8003fae: 2303 movs r3, #3 - 8003fb0: 67bb str r3, [r7, #120] ; 0x78 - GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; - 8003fb2: 2304 movs r3, #4 - 8003fb4: 67fb str r3, [r7, #124] ; 0x7c - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8003fb6: f107 036c add.w r3, r7, #108 ; 0x6c - 8003fba: 4619 mov r1, r3 - 8003fbc: 480b ldr r0, [pc, #44] ; (8003fec ) - 8003fbe: f002 fa25 bl 800640c - /* Peripheral clock enable */ - __HAL_RCC_I2C3_CLK_ENABLE(); - 8003fc2: 4b09 ldr r3, [pc, #36] ; (8003fe8 ) - 8003fc4: 6d9b ldr r3, [r3, #88] ; 0x58 - 8003fc6: 4a08 ldr r2, [pc, #32] ; (8003fe8 ) - 8003fc8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 - 8003fcc: 6593 str r3, [r2, #88] ; 0x58 - 8003fce: 4b06 ldr r3, [pc, #24] ; (8003fe8 ) - 8003fd0: 6d9b ldr r3, [r3, #88] ; 0x58 - 8003fd2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 - 8003fd6: 60fb str r3, [r7, #12] - 8003fd8: 68fb ldr r3, [r7, #12] - /* USER CODE BEGIN I2C3_MspInit 1 */ - /* USER CODE END I2C3_MspInit 1 */ - } -} - 8003fda: bf00 nop - 8003fdc: 3780 adds r7, #128 ; 0x80 - 8003fde: 46bd mov sp, r7 - 8003fe0: bd80 pop {r7, pc} - 8003fe2: bf00 nop - 8003fe4: 40005c00 .word 0x40005c00 - 8003fe8: 40021000 .word 0x40021000 - 8003fec: 48000400 .word 0x48000400 + break; + 80046e2: e189 b.n 80049f8 -08003ff0 : -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - 8003ff0: b580 push {r7, lr} - 8003ff2: b09e sub sp, #120 ; 0x78 - 8003ff4: af00 add r7, sp, #0 - 8003ff6: 6078 str r0, [r7, #4] - GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8003ff8: f107 0364 add.w r3, r7, #100 ; 0x64 - 8003ffc: 2200 movs r2, #0 - 8003ffe: 601a str r2, [r3, #0] - 8004000: 605a str r2, [r3, #4] - 8004002: 609a str r2, [r3, #8] - 8004004: 60da str r2, [r3, #12] - 8004006: 611a str r2, [r3, #16] - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8004008: f107 0310 add.w r3, r7, #16 - 800400c: 2254 movs r2, #84 ; 0x54 - 800400e: 2100 movs r1, #0 - 8004010: 4618 mov r0, r3 - 8004012: f00e fd22 bl 8012a5a - if(huart->Instance==LPUART1) - 8004016: 687b ldr r3, [r7, #4] - 8004018: 681b ldr r3, [r3, #0] - 800401a: 4a37 ldr r2, [pc, #220] ; (80040f8 ) - 800401c: 4293 cmp r3, r2 - 800401e: d167 bne.n 80040f0 - /* USER CODE END LPUART1_MspInit 0 */ + case STATE_USB: + ssd1306_Fill(Black); + 80046e4: 2000 movs r0, #0 + 80046e6: f7fe f823 bl 8002730 + ssd1306_SetCursor(32,32); + 80046ea: 2120 movs r1, #32 + 80046ec: 2020 movs r0, #32 + 80046ee: f7fe f961 bl 80029b4 + ssd1306_WriteString("usb",Font_6x8,White); + 80046f2: 4a30 ldr r2, [pc, #192] ; (80047b4 ) + 80046f4: 2301 movs r3, #1 + 80046f6: ca06 ldmia r2, {r1, r2} + 80046f8: 4842 ldr r0, [pc, #264] ; (8004804 ) + 80046fa: f7fe f935 bl 8002968 + switch(usbstate){ + 80046fe: 4b42 ldr r3, [pc, #264] ; (8004808 ) + 8004700: 781b ldrb r3, [r3, #0] + 8004702: 2b02 cmp r3, #2 + 8004704: f000 80f6 beq.w 80048f4 + 8004708: 2b02 cmp r3, #2 + 800470a: f300 8177 bgt.w 80049fc + 800470e: 2b00 cmp r3, #0 + 8004710: d002 beq.n 8004718 + 8004712: 2b01 cmp r3, #1 + 8004714: d07c beq.n 8004810 - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - 8004020: 2320 movs r3, #32 - 8004022: 613b str r3, [r7, #16] - PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - 8004024: 2300 movs r3, #0 - 8004026: 63bb str r3, [r7, #56] ; 0x38 - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8004028: f107 0310 add.w r3, r7, #16 - 800402c: 4618 mov r0, r3 - 800402e: f005 fd2f bl 8009a90 - 8004032: 4603 mov r3, r0 - 8004034: 2b00 cmp r3, #0 - 8004036: d001 beq.n 800403c - { - Error_Handler(); - 8004038: f7fd fbde bl 80017f8 - } - /* Peripheral clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - 800403c: 4b2f ldr r3, [pc, #188] ; (80040fc ) - 800403e: 6ddb ldr r3, [r3, #92] ; 0x5c - 8004040: 4a2e ldr r2, [pc, #184] ; (80040fc ) - 8004042: f043 0301 orr.w r3, r3, #1 - 8004046: 65d3 str r3, [r2, #92] ; 0x5c - 8004048: 4b2c ldr r3, [pc, #176] ; (80040fc ) - 800404a: 6ddb ldr r3, [r3, #92] ; 0x5c - 800404c: f003 0301 and.w r3, r3, #1 - 8004050: 60fb str r3, [r7, #12] - 8004052: 68fb ldr r3, [r7, #12] - __HAL_RCC_GPIOA_CLK_ENABLE(); - 8004054: 4b29 ldr r3, [pc, #164] ; (80040fc ) - 8004056: 6cdb ldr r3, [r3, #76] ; 0x4c - 8004058: 4a28 ldr r2, [pc, #160] ; (80040fc ) - 800405a: f043 0301 orr.w r3, r3, #1 - 800405e: 64d3 str r3, [r2, #76] ; 0x4c - 8004060: 4b26 ldr r3, [pc, #152] ; (80040fc ) - 8004062: 6cdb ldr r3, [r3, #76] ; 0x4c - 8004064: f003 0301 and.w r3, r3, #1 - 8004068: 60bb str r3, [r7, #8] - 800406a: 68bb ldr r3, [r7, #8] - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - 800406c: 230c movs r3, #12 - 800406e: 667b str r3, [r7, #100] ; 0x64 - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8004070: 2302 movs r3, #2 - 8004072: 66bb str r3, [r7, #104] ; 0x68 - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8004074: 2300 movs r3, #0 - 8004076: 66fb str r3, [r7, #108] ; 0x6c - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8004078: 2303 movs r3, #3 - 800407a: 673b str r3, [r7, #112] ; 0x70 - GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; - 800407c: 2308 movs r3, #8 - 800407e: 677b str r3, [r7, #116] ; 0x74 - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8004080: f107 0364 add.w r3, r7, #100 ; 0x64 - 8004084: 4619 mov r1, r3 - 8004086: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 800408a: f002 f9bf bl 800640c - /* LPUART1 DMA Init */ - /* LPUART_RX Init */ - hdma_lpuart_rx.Instance = DMA2_Channel7; - 800408e: 4b1c ldr r3, [pc, #112] ; (8004100 ) - 8004090: 4a1c ldr r2, [pc, #112] ; (8004104 ) - 8004092: 601a str r2, [r3, #0] - hdma_lpuart_rx.Init.Request = DMA_REQUEST_4; - 8004094: 4b1a ldr r3, [pc, #104] ; (8004100 ) - 8004096: 2204 movs r2, #4 - 8004098: 605a str r2, [r3, #4] - hdma_lpuart_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - 800409a: 4b19 ldr r3, [pc, #100] ; (8004100 ) - 800409c: 2200 movs r2, #0 - 800409e: 609a str r2, [r3, #8] - hdma_lpuart_rx.Init.PeriphInc = DMA_PINC_DISABLE; - 80040a0: 4b17 ldr r3, [pc, #92] ; (8004100 ) - 80040a2: 2200 movs r2, #0 - 80040a4: 60da str r2, [r3, #12] - hdma_lpuart_rx.Init.MemInc = DMA_MINC_ENABLE; - 80040a6: 4b16 ldr r3, [pc, #88] ; (8004100 ) - 80040a8: 2280 movs r2, #128 ; 0x80 - 80040aa: 611a str r2, [r3, #16] - hdma_lpuart_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - 80040ac: 4b14 ldr r3, [pc, #80] ; (8004100 ) - 80040ae: 2200 movs r2, #0 - 80040b0: 615a str r2, [r3, #20] - hdma_lpuart_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - 80040b2: 4b13 ldr r3, [pc, #76] ; (8004100 ) - 80040b4: 2200 movs r2, #0 - 80040b6: 619a str r2, [r3, #24] - hdma_lpuart_rx.Init.Mode = DMA_NORMAL; - 80040b8: 4b11 ldr r3, [pc, #68] ; (8004100 ) - 80040ba: 2200 movs r2, #0 - 80040bc: 61da str r2, [r3, #28] - hdma_lpuart_rx.Init.Priority = DMA_PRIORITY_LOW; - 80040be: 4b10 ldr r3, [pc, #64] ; (8004100 ) - 80040c0: 2200 movs r2, #0 - 80040c2: 621a str r2, [r3, #32] - if (HAL_DMA_Init(&hdma_lpuart_rx) != HAL_OK) - 80040c4: 480e ldr r0, [pc, #56] ; (8004100 ) - 80040c6: f001 fe8d bl 8005de4 - 80040ca: 4603 mov r3, r0 - 80040cc: 2b00 cmp r3, #0 - 80040ce: d001 beq.n 80040d4 - { - Error_Handler(); - 80040d0: f7fd fb92 bl 80017f8 - } - __HAL_LINKDMA(huart,hdmarx,hdma_lpuart_rx); - 80040d4: 687b ldr r3, [r7, #4] - 80040d6: 4a0a ldr r2, [pc, #40] ; (8004100 ) - 80040d8: 675a str r2, [r3, #116] ; 0x74 - 80040da: 4a09 ldr r2, [pc, #36] ; (8004100 ) - 80040dc: 687b ldr r3, [r7, #4] - 80040de: 6293 str r3, [r2, #40] ; 0x28 + break; + 8004716: e171 b.n 80049fc + ssd1306_SetCursor(32,40); + 8004718: 2128 movs r1, #40 ; 0x28 + 800471a: 2020 movs r0, #32 + 800471c: f7fe f94a bl 80029b4 + ssd1306_WriteString("do nothing",Font_6x8,White); + 8004720: 4a24 ldr r2, [pc, #144] ; (80047b4 ) + 8004722: 2301 movs r3, #1 + 8004724: ca06 ldmia r2, {r1, r2} + 8004726: 4824 ldr r0, [pc, #144] ; (80047b8 ) + 8004728: f7fe f91e bl 8002968 + usbtransmiten=0; + 800472c: 4b37 ldr r3, [pc, #220] ; (800480c ) + 800472e: 2200 movs r2, #0 + 8004730: 601a str r2, [r3, #0] + if(BTN_B>=1){ + 8004732: 4b22 ldr r3, [pc, #136] ; (80047bc ) + 8004734: 681b ldr r3, [r3, #0] + 8004736: 2b00 cmp r3, #0 + 8004738: dd0b ble.n 8004752 + usbstate++; + 800473a: 4b33 ldr r3, [pc, #204] ; (8004808 ) + 800473c: 781b ldrb r3, [r3, #0] + 800473e: 3301 adds r3, #1 + 8004740: b2da uxtb r2, r3 + 8004742: 4b31 ldr r3, [pc, #196] ; (8004808 ) + 8004744: 701a strb r2, [r3, #0] + BTN_B=0; + 8004746: 4b1d ldr r3, [pc, #116] ; (80047bc ) + 8004748: 2200 movs r2, #0 + 800474a: 601a str r2, [r3, #0] + BTN_A=0; + 800474c: 4b1d ldr r3, [pc, #116] ; (80047c4 ) + 800474e: 2200 movs r2, #0 + 8004750: 601a str r2, [r3, #0] + if(BTN_A>=1){ + 8004752: 4b1c ldr r3, [pc, #112] ; (80047c4 ) + 8004754: 681b ldr r3, [r3, #0] + 8004756: 2b00 cmp r3, #0 + 8004758: f340 813e ble.w 80049d8 + state--; + 800475c: 4b28 ldr r3, [pc, #160] ; (8004800 ) + 800475e: 781b ldrb r3, [r3, #0] + 8004760: 3b01 subs r3, #1 + 8004762: b2da uxtb r2, r3 + 8004764: 4b26 ldr r3, [pc, #152] ; (8004800 ) + 8004766: 701a strb r2, [r3, #0] + state--; + 8004768: 4b25 ldr r3, [pc, #148] ; (8004800 ) + 800476a: 781b ldrb r3, [r3, #0] + 800476c: 3b01 subs r3, #1 + 800476e: b2da uxtb r2, r3 + 8004770: 4b23 ldr r3, [pc, #140] ; (8004800 ) + 8004772: 701a strb r2, [r3, #0] + state--; + 8004774: 4b22 ldr r3, [pc, #136] ; (8004800 ) + 8004776: 781b ldrb r3, [r3, #0] + 8004778: 3b01 subs r3, #1 + 800477a: b2da uxtb r2, r3 + 800477c: 4b20 ldr r3, [pc, #128] ; (8004800 ) + 800477e: 701a strb r2, [r3, #0] + state--; + 8004780: 4b1f ldr r3, [pc, #124] ; (8004800 ) + 8004782: 781b ldrb r3, [r3, #0] + 8004784: 3b01 subs r3, #1 + 8004786: b2da uxtb r2, r3 + 8004788: 4b1d ldr r3, [pc, #116] ; (8004800 ) + 800478a: 701a strb r2, [r3, #0] + state--; + 800478c: 4b1c ldr r3, [pc, #112] ; (8004800 ) + 800478e: 781b ldrb r3, [r3, #0] + 8004790: 3b01 subs r3, #1 + 8004792: b2da uxtb r2, r3 + 8004794: 4b1a ldr r3, [pc, #104] ; (8004800 ) + 8004796: 701a strb r2, [r3, #0] + state--; + 8004798: 4b19 ldr r3, [pc, #100] ; (8004800 ) + 800479a: 781b ldrb r3, [r3, #0] + 800479c: 3b01 subs r3, #1 + 800479e: b2da uxtb r2, r3 + 80047a0: 4b17 ldr r3, [pc, #92] ; (8004800 ) + 80047a2: 701a strb r2, [r3, #0] + BTN_A=0; + 80047a4: 4b07 ldr r3, [pc, #28] ; (80047c4 ) + 80047a6: 2200 movs r2, #0 + 80047a8: 601a str r2, [r3, #0] + BTN_B=0; + 80047aa: 4b04 ldr r3, [pc, #16] ; (80047bc ) + 80047ac: 2200 movs r2, #0 + 80047ae: 601a str r2, [r3, #0] + break; + 80047b0: e112 b.n 80049d8 + 80047b2: bf00 nop + 80047b4: 20000008 .word 0x20000008 + 80047b8: 08018f5c .word 0x08018f5c + 80047bc: 200006f4 .word 0x200006f4 + 80047c0: 20000e33 .word 0x20000e33 + 80047c4: 200006f0 .word 0x200006f0 + 80047c8: 200004ac .word 0x200004ac + 80047cc: 200006b0 .word 0x200006b0 + 80047d0: 20000938 .word 0x20000938 + 80047d4: 20000728 .word 0x20000728 + 80047d8: 20000730 .word 0x20000730 + 80047dc: 00000000 .word 0x00000000 + 80047e0: 20000734 .word 0x20000734 + 80047e4: 20000e90 .word 0x20000e90 + 80047e8: 20000934 .word 0x20000934 + 80047ec: 08018f68 .word 0x08018f68 + 80047f0: 20000e5c .word 0x20000e5c + 80047f4: 08018f70 .word 0x08018f70 + 80047f8: 08018f78 .word 0x08018f78 + 80047fc: 08018f80 .word 0x08018f80 + 8004800: 200006f8 .word 0x200006f8 + 8004804: 08018f88 .word 0x08018f88 + 8004808: 20000e32 .word 0x20000e32 + 800480c: 20000e9c .word 0x20000e9c + ssd1306_SetCursor(32,40); + 8004810: 2128 movs r1, #40 ; 0x28 + 8004812: 2020 movs r0, #32 + 8004814: f7fe f8ce bl 80029b4 + ssd1306_WriteString("Push A",Font_6x8,White); + 8004818: 4a7c ldr r2, [pc, #496] ; (8004a0c ) + 800481a: 2301 movs r3, #1 + 800481c: ca06 ldmia r2, {r1, r2} + 800481e: 487c ldr r0, [pc, #496] ; (8004a10 ) + 8004820: f7fe f8a2 bl 8002968 + ssd1306_SetCursor(32,48); + 8004824: 2130 movs r1, #48 ; 0x30 + 8004826: 2020 movs r0, #32 + 8004828: f7fe f8c4 bl 80029b4 + ssd1306_WriteString("to erase",Font_6x8,White); + 800482c: 4a77 ldr r2, [pc, #476] ; (8004a0c ) + 800482e: 2301 movs r3, #1 + 8004830: ca06 ldmia r2, {r1, r2} + 8004832: 4878 ldr r0, [pc, #480] ; (8004a14 ) + 8004834: f7fe f898 bl 8002968 + if(erasedisplay==1){ + 8004838: 4b77 ldr r3, [pc, #476] ; (8004a18 ) + 800483a: 681b ldr r3, [r3, #0] + 800483c: 2b01 cmp r3, #1 + 800483e: d120 bne.n 8004882 + snprintf((uint8_t *)str,50,"t=%0.2f",(float)erasetime/1000); + 8004840: 4b76 ldr r3, [pc, #472] ; (8004a1c ) + 8004842: 681b ldr r3, [r3, #0] + 8004844: ee07 3a90 vmov s15, r3 + 8004848: eef8 7ae7 vcvt.f32.s32 s15, s15 + 800484c: ed9f 7a74 vldr s14, [pc, #464] ; 8004a20 + 8004850: eec7 6a87 vdiv.f32 s13, s15, s14 + 8004854: ee16 0a90 vmov r0, s13 + 8004858: f7fb fe76 bl 8000548 <__aeabi_f2d> + 800485c: 4602 mov r2, r0 + 800485e: 460b mov r3, r1 + 8004860: e9cd 2300 strd r2, r3, [sp] + 8004864: 4a6f ldr r2, [pc, #444] ; (8004a24 ) + 8004866: 2132 movs r1, #50 ; 0x32 + 8004868: 6d38 ldr r0, [r7, #80] ; 0x50 + 800486a: f010 fab7 bl 8014ddc + ssd1306_SetCursor(32,56); + 800486e: 2138 movs r1, #56 ; 0x38 + 8004870: 2020 movs r0, #32 + 8004872: f7fe f89f bl 80029b4 + ssd1306_WriteString((uint8_t*)str,Font_6x8,White); + 8004876: 4a65 ldr r2, [pc, #404] ; (8004a0c ) + 8004878: 2301 movs r3, #1 + 800487a: ca06 ldmia r2, {r1, r2} + 800487c: 6d38 ldr r0, [r7, #80] ; 0x50 + 800487e: f7fe f873 bl 8002968 + if(BTN_A>=1){ + 8004882: 4b69 ldr r3, [pc, #420] ; (8004a28 ) + 8004884: 681b ldr r3, [r3, #0] + 8004886: 2b00 cmp r3, #0 + 8004888: dd22 ble.n 80048d0 + erasetime=HAL_GetTick(); + 800488a: f000 fce1 bl 8005250 + 800488e: 4603 mov r3, r0 + 8004890: 461a mov r2, r3 + 8004892: 4b62 ldr r3, [pc, #392] ; (8004a1c ) + 8004894: 601a str r2, [r3, #0] + SPIF_EraseChip(&hspif1); + 8004896: 4865 ldr r0, [pc, #404] ; (8004a2c ) + 8004898: f00d fcf1 bl 801227e + erasetime=HAL_GetTick()-erasetime; + 800489c: f000 fcd8 bl 8005250 + 80048a0: 4603 mov r3, r0 + 80048a2: 4a5e ldr r2, [pc, #376] ; (8004a1c ) + 80048a4: 6812 ldr r2, [r2, #0] + 80048a6: 1a9b subs r3, r3, r2 + 80048a8: 461a mov r2, r3 + 80048aa: 4b5c ldr r3, [pc, #368] ; (8004a1c ) + 80048ac: 601a str r2, [r3, #0] + erasedisplay=1; + 80048ae: 4b5a ldr r3, [pc, #360] ; (8004a18 ) + 80048b0: 2201 movs r2, #1 + 80048b2: 601a str r2, [r3, #0] + pageoffset=0; + 80048b4: 4b5e ldr r3, [pc, #376] ; (8004a30 ) + 80048b6: 2200 movs r2, #0 + 80048b8: 601a str r2, [r3, #0] + pagenumber=0; + 80048ba: 4b5e ldr r3, [pc, #376] ; (8004a34 ) + 80048bc: 2200 movs r2, #0 + 80048be: 601a str r2, [r3, #0] + storeindex(); + 80048c0: f7fd fd5a bl 8002378 + BTN_A=0; + 80048c4: 4b58 ldr r3, [pc, #352] ; (8004a28 ) + 80048c6: 2200 movs r2, #0 + 80048c8: 601a str r2, [r3, #0] + BTN_B=0; + 80048ca: 4b5b ldr r3, [pc, #364] ; (8004a38 ) + 80048cc: 2200 movs r2, #0 + 80048ce: 601a str r2, [r3, #0] + if(BTN_B>=1){ + 80048d0: 4b59 ldr r3, [pc, #356] ; (8004a38 ) + 80048d2: 681b ldr r3, [r3, #0] + 80048d4: 2b00 cmp r3, #0 + 80048d6: f340 8081 ble.w 80049dc + usbstate++; + 80048da: 4b58 ldr r3, [pc, #352] ; (8004a3c ) + 80048dc: 781b ldrb r3, [r3, #0] + 80048de: 3301 adds r3, #1 + 80048e0: b2da uxtb r2, r3 + 80048e2: 4b56 ldr r3, [pc, #344] ; (8004a3c ) + 80048e4: 701a strb r2, [r3, #0] + BTN_B=0; + 80048e6: 4b54 ldr r3, [pc, #336] ; (8004a38 ) + 80048e8: 2200 movs r2, #0 + 80048ea: 601a str r2, [r3, #0] + BTN_A=0; + 80048ec: 4b4e ldr r3, [pc, #312] ; (8004a28 ) + 80048ee: 2200 movs r2, #0 + 80048f0: 601a str r2, [r3, #0] + break; + 80048f2: e073 b.n 80049dc + ssd1306_SetCursor(32,40); + 80048f4: 2128 movs r1, #40 ; 0x28 + 80048f6: 2020 movs r0, #32 + 80048f8: f7fe f85c bl 80029b4 + ssd1306_WriteString("write",Font_6x8,White); + 80048fc: 4a43 ldr r2, [pc, #268] ; (8004a0c ) + 80048fe: 2301 movs r3, #1 + 8004900: ca06 ldmia r2, {r1, r2} + 8004902: 484f ldr r0, [pc, #316] ; (8004a40 ) + 8004904: f7fe f830 bl 8002968 + int i=0; + 8004908: 2300 movs r3, #0 + 800490a: 657b str r3, [r7, #84] ; 0x54 + if(usbtransmiten==0){ + 800490c: 4b4d ldr r3, [pc, #308] ; (8004a44 ) + 800490e: 681b ldr r3, [r3, #0] + 8004910: 2b00 cmp r3, #0 + 8004912: d11c bne.n 800494e + while(i<=pagenumber){ + 8004914: e013 b.n 800493e + SPIF_ReadPage(&hspif1,i, (uint8_t *)flashread, 256, 0); + 8004916: 6d79 ldr r1, [r7, #84] ; 0x54 + 8004918: 2300 movs r3, #0 + 800491a: 9300 str r3, [sp, #0] + 800491c: f44f 7380 mov.w r3, #256 ; 0x100 + 8004920: 4a49 ldr r2, [pc, #292] ; (8004a48 ) + 8004922: 4842 ldr r0, [pc, #264] ; (8004a2c ) + 8004924: f00d fd96 bl 8012454 + CDC_Transmit_FS((uint8_t * )flashread,256); + 8004928: f44f 7180 mov.w r1, #256 ; 0x100 + 800492c: 4846 ldr r0, [pc, #280] ; (8004a48 ) + 800492e: f00d fe7b bl 8012628 + HAL_Delay(100); + 8004932: 2064 movs r0, #100 ; 0x64 + 8004934: f000 fc98 bl 8005268 + i++; + 8004938: 6d7b ldr r3, [r7, #84] ; 0x54 + 800493a: 3301 adds r3, #1 + 800493c: 657b str r3, [r7, #84] ; 0x54 + while(i<=pagenumber){ + 800493e: 4b3d ldr r3, [pc, #244] ; (8004a34 ) + 8004940: 681b ldr r3, [r3, #0] + 8004942: 6d7a ldr r2, [r7, #84] ; 0x54 + 8004944: 429a cmp r2, r3 + 8004946: dde6 ble.n 8004916 + usbtransmiten=1; + 8004948: 4b3e ldr r3, [pc, #248] ; (8004a44 ) + 800494a: 2201 movs r2, #1 + 800494c: 601a str r2, [r3, #0] + if(BTN_B>=1){ + 800494e: 4b3a ldr r3, [pc, #232] ; (8004a38 ) + 8004950: 681b ldr r3, [r3, #0] + 8004952: 2b00 cmp r3, #0 + 8004954: dd11 ble.n 800497a + usbstate--; + 8004956: 4b39 ldr r3, [pc, #228] ; (8004a3c ) + 8004958: 781b ldrb r3, [r3, #0] + 800495a: 3b01 subs r3, #1 + 800495c: b2da uxtb r2, r3 + 800495e: 4b37 ldr r3, [pc, #220] ; (8004a3c ) + 8004960: 701a strb r2, [r3, #0] + usbstate--; + 8004962: 4b36 ldr r3, [pc, #216] ; (8004a3c ) + 8004964: 781b ldrb r3, [r3, #0] + 8004966: 3b01 subs r3, #1 + 8004968: b2da uxtb r2, r3 + 800496a: 4b34 ldr r3, [pc, #208] ; (8004a3c ) + 800496c: 701a strb r2, [r3, #0] + BTN_B=0; + 800496e: 4b32 ldr r3, [pc, #200] ; (8004a38 ) + 8004970: 2200 movs r2, #0 + 8004972: 601a str r2, [r3, #0] + BTN_A=0; + 8004974: 4b2c ldr r3, [pc, #176] ; (8004a28 ) + 8004976: 2200 movs r2, #0 + 8004978: 601a str r2, [r3, #0] + if(BTN_A>=1){ + 800497a: 4b2b ldr r3, [pc, #172] ; (8004a28 ) + 800497c: 681b ldr r3, [r3, #0] + 800497e: 2b00 cmp r3, #0 + 8004980: dd2e ble.n 80049e0 + state--; + 8004982: 4b32 ldr r3, [pc, #200] ; (8004a4c ) + 8004984: 781b ldrb r3, [r3, #0] + 8004986: 3b01 subs r3, #1 + 8004988: b2da uxtb r2, r3 + 800498a: 4b30 ldr r3, [pc, #192] ; (8004a4c ) + 800498c: 701a strb r2, [r3, #0] + state--; + 800498e: 4b2f ldr r3, [pc, #188] ; (8004a4c ) + 8004990: 781b ldrb r3, [r3, #0] + 8004992: 3b01 subs r3, #1 + 8004994: b2da uxtb r2, r3 + 8004996: 4b2d ldr r3, [pc, #180] ; (8004a4c ) + 8004998: 701a strb r2, [r3, #0] + state--; + 800499a: 4b2c ldr r3, [pc, #176] ; (8004a4c ) + 800499c: 781b ldrb r3, [r3, #0] + 800499e: 3b01 subs r3, #1 + 80049a0: b2da uxtb r2, r3 + 80049a2: 4b2a ldr r3, [pc, #168] ; (8004a4c ) + 80049a4: 701a strb r2, [r3, #0] + state--; + 80049a6: 4b29 ldr r3, [pc, #164] ; (8004a4c ) + 80049a8: 781b ldrb r3, [r3, #0] + 80049aa: 3b01 subs r3, #1 + 80049ac: b2da uxtb r2, r3 + 80049ae: 4b27 ldr r3, [pc, #156] ; (8004a4c ) + 80049b0: 701a strb r2, [r3, #0] + state--; + 80049b2: 4b26 ldr r3, [pc, #152] ; (8004a4c ) + 80049b4: 781b ldrb r3, [r3, #0] + 80049b6: 3b01 subs r3, #1 + 80049b8: b2da uxtb r2, r3 + 80049ba: 4b24 ldr r3, [pc, #144] ; (8004a4c ) + 80049bc: 701a strb r2, [r3, #0] + state--; + 80049be: 4b23 ldr r3, [pc, #140] ; (8004a4c ) + 80049c0: 781b ldrb r3, [r3, #0] + 80049c2: 3b01 subs r3, #1 + 80049c4: b2da uxtb r2, r3 + 80049c6: 4b21 ldr r3, [pc, #132] ; (8004a4c ) + 80049c8: 701a strb r2, [r3, #0] + BTN_A=0; + 80049ca: 4b17 ldr r3, [pc, #92] ; (8004a28 ) + 80049cc: 2200 movs r2, #0 + 80049ce: 601a str r2, [r3, #0] + BTN_B=0; + 80049d0: 4b19 ldr r3, [pc, #100] ; (8004a38 ) + 80049d2: 2200 movs r2, #0 + 80049d4: 601a str r2, [r3, #0] + break; + 80049d6: e003 b.n 80049e0 + break; + 80049d8: bf00 nop + 80049da: e00f b.n 80049fc + break; + 80049dc: bf00 nop + 80049de: e00d b.n 80049fc + break; + 80049e0: bf00 nop + break; + 80049e2: e00b b.n 80049fc + break; + 80049e4: bf00 nop + 80049e6: e00a b.n 80049fe + break; + 80049e8: bf00 nop + 80049ea: e008 b.n 80049fe + break; + 80049ec: bf00 nop + 80049ee: e006 b.n 80049fe + break; + 80049f0: bf00 nop + 80049f2: e004 b.n 80049fe + break; + 80049f4: bf00 nop + 80049f6: e002 b.n 80049fe + break; + 80049f8: bf00 nop + 80049fa: e000 b.n 80049fe + break; + 80049fc: bf00 nop - /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); - 80040e0: 2200 movs r2, #0 - 80040e2: 2100 movs r1, #0 - 80040e4: 2046 movs r0, #70 ; 0x46 - 80040e6: f001 fe38 bl 8005d5a - HAL_NVIC_EnableIRQ(LPUART1_IRQn); - 80040ea: 2046 movs r0, #70 ; 0x46 - 80040ec: f001 fe51 bl 8005d92 - /* USER CODE BEGIN LPUART1_MspInit 1 */ + } - /* USER CODE END LPUART1_MspInit 1 */ - } +return ; + 80049fe: bf00 nop + 8004a00: bf00 nop +} + 8004a02: 376c adds r7, #108 ; 0x6c + 8004a04: 46bd mov sp, r7 + 8004a06: ecbd 8b02 vpop {d8} + 8004a0a: bdf0 pop {r4, r5, r6, r7, pc} + 8004a0c: 20000008 .word 0x20000008 + 8004a10: 08018f8c .word 0x08018f8c + 8004a14: 08018f94 .word 0x08018f94 + 8004a18: 20000e98 .word 0x20000e98 + 8004a1c: 20000e94 .word 0x20000e94 + 8004a20: 447a0000 .word 0x447a0000 + 8004a24: 08018fa0 .word 0x08018fa0 + 8004a28: 200006f0 .word 0x200006f0 + 8004a2c: 20000700 .word 0x20000700 + 8004a30: 20000934 .word 0x20000934 + 8004a34: 20000938 .word 0x20000938 + 8004a38: 200006f4 .word 0x200006f4 + 8004a3c: 20000e32 .word 0x20000e32 + 8004a40: 08018fa8 .word 0x08018fa8 + 8004a44: 20000e9c .word 0x20000e9c + 8004a48: 20000834 .word 0x20000834 + 8004a4c: 200006f8 .word 0x200006f8 + +08004a50 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8004a50: b480 push {r7} + 8004a52: b083 sub sp, #12 + 8004a54: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ -} - 80040f0: bf00 nop - 80040f2: 3778 adds r7, #120 ; 0x78 - 80040f4: 46bd mov sp, r7 - 80040f6: bd80 pop {r7, pc} - 80040f8: 40008000 .word 0x40008000 - 80040fc: 40021000 .word 0x40021000 - 8004100: 200004bc .word 0x200004bc - 8004104: 40020480 .word 0x40020480 + /* USER CODE END MspInit 0 */ -08004108 : -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - 8004108: b580 push {r7, lr} - 800410a: b082 sub sp, #8 - 800410c: af00 add r7, sp, #0 - 800410e: 6078 str r0, [r7, #4] - if(huart->Instance==LPUART1) - 8004110: 687b ldr r3, [r7, #4] - 8004112: 681b ldr r3, [r3, #0] - 8004114: 4a0c ldr r2, [pc, #48] ; (8004148 ) - 8004116: 4293 cmp r3, r2 - 8004118: d112 bne.n 8004140 - { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); - 800411a: 4b0c ldr r3, [pc, #48] ; (800414c ) - 800411c: 6ddb ldr r3, [r3, #92] ; 0x5c - 800411e: 4a0b ldr r2, [pc, #44] ; (800414c ) - 8004120: f023 0301 bic.w r3, r3, #1 - 8004124: 65d3 str r3, [r2, #92] ; 0x5c + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8004a56: 4b0f ldr r3, [pc, #60] ; (8004a94 ) + 8004a58: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004a5a: 4a0e ldr r2, [pc, #56] ; (8004a94 ) + 8004a5c: f043 0301 orr.w r3, r3, #1 + 8004a60: 6613 str r3, [r2, #96] ; 0x60 + 8004a62: 4b0c ldr r3, [pc, #48] ; (8004a94 ) + 8004a64: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004a66: f003 0301 and.w r3, r3, #1 + 8004a6a: 607b str r3, [r7, #4] + 8004a6c: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 8004a6e: 4b09 ldr r3, [pc, #36] ; (8004a94 ) + 8004a70: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004a72: 4a08 ldr r2, [pc, #32] ; (8004a94 ) + 8004a74: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8004a78: 6593 str r3, [r2, #88] ; 0x58 + 8004a7a: 4b06 ldr r3, [pc, #24] ; (8004a94 ) + 8004a7c: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004a7e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8004a82: 603b str r3, [r7, #0] + 8004a84: 683b ldr r3, [r7, #0] + /* System interrupt init*/ - /**LPUART1 GPIO Configuration - PA2 ------> LPUART1_TX - PA3 ------> LPUART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - 8004126: 210c movs r1, #12 - 8004128: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 800412c: f002 fad8 bl 80066e0 - - /* LPUART1 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - 8004130: 687b ldr r3, [r7, #4] - 8004132: 6f5b ldr r3, [r3, #116] ; 0x74 - 8004134: 4618 mov r0, r3 - 8004136: f001 ff0d bl 8005f54 - - /* LPUART1 interrupt DeInit */ - HAL_NVIC_DisableIRQ(LPUART1_IRQn); - 800413a: 2046 movs r0, #70 ; 0x46 - 800413c: f001 fe37 bl 8005dae - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - - /* USER CODE END LPUART1_MspDeInit 1 */ - } - -} - 8004140: bf00 nop - 8004142: 3708 adds r7, #8 - 8004144: 46bd mov sp, r7 - 8004146: bd80 pop {r7, pc} - 8004148: 40008000 .word 0x40008000 - 800414c: 40021000 .word 0x40021000 - -08004150 : -* This function configures the hardware resources used in this example -* @param htim_base: TIM_Base handle pointer -* @retval None -*/ -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) -{ - 8004150: b580 push {r7, lr} - 8004152: b084 sub sp, #16 - 8004154: af00 add r7, sp, #0 - 8004156: 6078 str r0, [r7, #4] - if(htim_base->Instance==TIM2) - 8004158: 687b ldr r3, [r7, #4] - 800415a: 681b ldr r3, [r3, #0] - 800415c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 8004160: d10c bne.n 800417c - { - /* USER CODE BEGIN TIM2_MspInit 0 */ + /* USER CODE BEGIN MspInit 1 */ - /* USER CODE END TIM2_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_TIM2_CLK_ENABLE(); - 8004162: 4b15 ldr r3, [pc, #84] ; (80041b8 ) - 8004164: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004166: 4a14 ldr r2, [pc, #80] ; (80041b8 ) - 8004168: f043 0301 orr.w r3, r3, #1 - 800416c: 6593 str r3, [r2, #88] ; 0x58 - 800416e: 4b12 ldr r3, [pc, #72] ; (80041b8 ) - 8004170: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004172: f003 0301 and.w r3, r3, #1 - 8004176: 60fb str r3, [r7, #12] - 8004178: 68fb ldr r3, [r7, #12] - /* USER CODE BEGIN TIM7_MspInit 1 */ - - /* USER CODE END TIM7_MspInit 1 */ - } - -} - 800417a: e018 b.n 80041ae - else if(htim_base->Instance==TIM7) - 800417c: 687b ldr r3, [r7, #4] - 800417e: 681b ldr r3, [r3, #0] - 8004180: 4a0e ldr r2, [pc, #56] ; (80041bc ) - 8004182: 4293 cmp r3, r2 - 8004184: d113 bne.n 80041ae - __HAL_RCC_TIM7_CLK_ENABLE(); - 8004186: 4b0c ldr r3, [pc, #48] ; (80041b8 ) - 8004188: 6d9b ldr r3, [r3, #88] ; 0x58 - 800418a: 4a0b ldr r2, [pc, #44] ; (80041b8 ) - 800418c: f043 0320 orr.w r3, r3, #32 - 8004190: 6593 str r3, [r2, #88] ; 0x58 - 8004192: 4b09 ldr r3, [pc, #36] ; (80041b8 ) - 8004194: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004196: f003 0320 and.w r3, r3, #32 - 800419a: 60bb str r3, [r7, #8] - 800419c: 68bb ldr r3, [r7, #8] - HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0); - 800419e: 2200 movs r2, #0 - 80041a0: 2100 movs r1, #0 - 80041a2: 2037 movs r0, #55 ; 0x37 - 80041a4: f001 fdd9 bl 8005d5a - HAL_NVIC_EnableIRQ(TIM7_IRQn); - 80041a8: 2037 movs r0, #55 ; 0x37 - 80041aa: f001 fdf2 bl 8005d92 -} - 80041ae: bf00 nop - 80041b0: 3710 adds r7, #16 - 80041b2: 46bd mov sp, r7 - 80041b4: bd80 pop {r7, pc} - 80041b6: bf00 nop - 80041b8: 40021000 .word 0x40021000 - 80041bc: 40001400 .word 0x40001400 - -080041c0 : + /* USER CODE END MspInit 1 */ +} + 8004a86: bf00 nop + 8004a88: 370c adds r7, #12 + 8004a8a: 46bd mov sp, r7 + 8004a8c: f85d 7b04 ldr.w r7, [sp], #4 + 8004a90: 4770 bx lr + 8004a92: bf00 nop + 8004a94: 40021000 .word 0x40021000 + +08004a98 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 80041c0: b480 push {r7} - 80041c2: af00 add r7, sp, #0 + 8004a98: b480 push {r7} + 8004a9a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 80041c4: e7fe b.n 80041c4 - ... + 8004a9c: e7fe b.n 8004a9c -080041c8 : +08004a9e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 80041c8: b580 push {r7, lr} - 80041ca: af00 add r7, sp, #0 + 8004a9e: b480 push {r7} + 8004aa0: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - ssd1306_Fill(Black); - 80041cc: 2000 movs r0, #0 - 80041ce: f7fd ff81 bl 80020d4 - ssd1306_SetCursor(33, 36); - 80041d2: 2124 movs r1, #36 ; 0x24 - 80041d4: 2021 movs r0, #33 ; 0x21 - 80041d6: f7fe f8bf bl 8002358 - ssd1306_WriteString("hard_fault", Font_6x8, White); - 80041da: 4a04 ldr r2, [pc, #16] ; (80041ec ) - 80041dc: 2301 movs r3, #1 - 80041de: ca06 ldmia r2, {r1, r2} - 80041e0: 4803 ldr r0, [pc, #12] ; (80041f0 ) - 80041e2: f7fe f893 bl 800230c - ssd1306_UpdateScreen(); - 80041e6: f7fd ff8d bl 8002104 - ssd1306_Fill(Black); - 80041ea: e7ef b.n 80041cc - 80041ec: 20000008 .word 0x20000008 - 80041f0: 08016ac0 .word 0x08016ac0 - -080041f4 : + 8004aa2: e7fe b.n 8004aa2 + +08004aa4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 80041f4: b480 push {r7} - 80041f6: af00 add r7, sp, #0 + 8004aa4: b480 push {r7} + 8004aa6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 80041f8: e7fe b.n 80041f8 + 8004aa8: e7fe b.n 8004aa8 -080041fa : +08004aaa : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { - 80041fa: b480 push {r7} - 80041fc: af00 add r7, sp, #0 + 8004aaa: b480 push {r7} + 8004aac: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 80041fe: e7fe b.n 80041fe + 8004aae: e7fe b.n 8004aae -08004200 : +08004ab0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8004200: b480 push {r7} - 8004202: af00 add r7, sp, #0 + 8004ab0: b480 push {r7} + 8004ab2: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8004204: e7fe b.n 8004204 + 8004ab4: e7fe b.n 8004ab4 -08004206 : +08004ab6 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8004206: b480 push {r7} - 8004208: af00 add r7, sp, #0 + 8004ab6: b480 push {r7} + 8004ab8: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 800420a: bf00 nop - 800420c: 46bd mov sp, r7 - 800420e: f85d 7b04 ldr.w r7, [sp], #4 - 8004212: 4770 bx lr + 8004aba: bf00 nop + 8004abc: 46bd mov sp, r7 + 8004abe: f85d 7b04 ldr.w r7, [sp], #4 + 8004ac2: 4770 bx lr -08004214 : +08004ac4 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8004214: b480 push {r7} - 8004216: af00 add r7, sp, #0 + 8004ac4: b480 push {r7} + 8004ac6: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8004218: bf00 nop - 800421a: 46bd mov sp, r7 - 800421c: f85d 7b04 ldr.w r7, [sp], #4 - 8004220: 4770 bx lr + 8004ac8: bf00 nop + 8004aca: 46bd mov sp, r7 + 8004acc: f85d 7b04 ldr.w r7, [sp], #4 + 8004ad0: 4770 bx lr -08004222 : +08004ad2 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8004222: b480 push {r7} - 8004224: af00 add r7, sp, #0 + 8004ad2: b480 push {r7} + 8004ad4: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8004226: bf00 nop - 8004228: 46bd mov sp, r7 - 800422a: f85d 7b04 ldr.w r7, [sp], #4 - 800422e: 4770 bx lr + 8004ad6: bf00 nop + 8004ad8: 46bd mov sp, r7 + 8004ada: f85d 7b04 ldr.w r7, [sp], #4 + 8004ade: 4770 bx lr -08004230 : +08004ae0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8004230: b580 push {r7, lr} - 8004232: af00 add r7, sp, #0 + 8004ae0: b580 push {r7, lr} + 8004ae2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ - distanceparcouru+=1; - 8004234: 4b04 ldr r3, [pc, #16] ; (8004248 ) - 8004236: 681b ldr r3, [r3, #0] - 8004238: 3301 adds r3, #1 - 800423a: 4a03 ldr r2, [pc, #12] ; (8004248 ) - 800423c: 6013 str r3, [r2, #0] /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 800423e: f000 f9a9 bl 8004594 + 8004ae4: f000 fba0 bl 8005228 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8004242: bf00 nop - 8004244: bd80 pop {r7, pc} - 8004246: bf00 nop - 8004248: 20000c94 .word 0x20000c94 + 8004ae8: bf00 nop + 8004aea: bd80 pop {r7, pc} -0800424c : +08004aec : + +/** + * @brief This function handles EXTI line1 interrupt. + */ +void EXTI1_IRQHandler(void) +{ + 8004aec: b580 push {r7, lr} + 8004aee: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI1_IRQn 0 */ + + /* USER CODE END EXTI1_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + 8004af0: 2002 movs r0, #2 + 8004af2: f002 fb93 bl 800721c + /* USER CODE BEGIN EXTI1_IRQn 1 */ + + /* USER CODE END EXTI1_IRQn 1 */ +} + 8004af6: bf00 nop + 8004af8: bd80 pop {r7, pc} + ... + +08004afc : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { - 800424c: b580 push {r7, lr} - 800424e: af00 add r7, sp, #0 + 8004afc: b580 push {r7, lr} + 8004afe: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); - 8004250: 4802 ldr r0, [pc, #8] ; (800425c ) - 8004252: f001 fff0 bl 8006236 + 8004b00: 4802 ldr r0, [pc, #8] ; (8004b0c ) + 8004b02: f002 f91e bl 8006d42 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } - 8004256: bf00 nop - 8004258: bd80 pop {r7, pc} - 800425a: bf00 nop - 800425c: 20000398 .word 0x20000398 + 8004b06: bf00 nop + 8004b08: bd80 pop {r7, pc} + 8004b0a: bf00 nop + 8004b0c: 20000378 .word 0x20000378 -08004260 : +08004b10 : /** * @brief This function handles ADC1 global interrupt. */ void ADC1_IRQHandler(void) { - 8004260: b580 push {r7, lr} - 8004262: af00 add r7, sp, #0 + 8004b10: b580 push {r7, lr} + 8004b12: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_IRQn 0 */ /* USER CODE END ADC1_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); - 8004264: 4802 ldr r0, [pc, #8] ; (8004270 ) - 8004266: f000 fd79 bl 8004d5c + 8004b14: 4802 ldr r0, [pc, #8] ; (8004b20 ) + 8004b16: f000 ff6b bl 80059f0 /* USER CODE BEGIN ADC1_IRQn 1 */ /* USER CODE END ADC1_IRQn 1 */ } - 800426a: bf00 nop - 800426c: bd80 pop {r7, pc} - 800426e: bf00 nop - 8004270: 20000334 .word 0x20000334 - -08004274 : - -/** - * @brief This function handles EXTI line[15:10] interrupts. - */ -void EXTI15_10_IRQHandler(void) -{ - 8004274: b580 push {r7, lr} - 8004276: af00 add r7, sp, #0 - /* USER CODE BEGIN EXTI15_10_IRQn 0 */ - - /* USER CODE END EXTI15_10_IRQn 0 */ - HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); - 8004278: f44f 4080 mov.w r0, #16384 ; 0x4000 - 800427c: f002 fb12 bl 80068a4 - HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); - 8004280: f44f 4000 mov.w r0, #32768 ; 0x8000 - 8004284: f002 fb0e bl 80068a4 - /* USER CODE BEGIN EXTI15_10_IRQn 1 */ - - /* USER CODE END EXTI15_10_IRQn 1 */ -} - 8004288: bf00 nop - 800428a: bd80 pop {r7, pc} + 8004b1a: bf00 nop + 8004b1c: bd80 pop {r7, pc} + 8004b1e: bf00 nop + 8004b20: 20000314 .word 0x20000314 -0800428c : +08004b24 : /** - * @brief This function handles TIM7 global interrupt. + * @brief This function handles EXTI line[9:5] interrupts. */ -void TIM7_IRQHandler(void) +void EXTI9_5_IRQHandler(void) { - 800428c: b580 push {r7, lr} - 800428e: af00 add r7, sp, #0 - /* USER CODE BEGIN TIM7_IRQn 0 */ - distanceparcouru+=1; - 8004290: 4b04 ldr r3, [pc, #16] ; (80042a4 ) - 8004292: 681b ldr r3, [r3, #0] - 8004294: 3301 adds r3, #1 - 8004296: 4a03 ldr r2, [pc, #12] ; (80042a4 ) - 8004298: 6013 str r3, [r2, #0] + 8004b24: b580 push {r7, lr} + 8004b26: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ - /* USER CODE END TIM7_IRQn 0 */ - HAL_TIM_IRQHandler(&htim7); - 800429a: 4803 ldr r0, [pc, #12] ; (80042a8 ) - 800429c: f005 ff84 bl 800a1a8 - /* USER CODE BEGIN TIM7_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + 8004b28: f44f 7080 mov.w r0, #256 ; 0x100 + 8004b2c: f002 fb76 bl 800721c + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ - /* USER CODE END TIM7_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 1 */ } - 80042a0: bf00 nop - 80042a2: bd80 pop {r7, pc} - 80042a4: 20000c94 .word 0x20000c94 - 80042a8: 20000550 .word 0x20000550 + 8004b30: bf00 nop + 8004b32: bd80 pop {r7, pc} -080042ac : +08004b34 : /** * @brief This function handles USB event interrupt through EXTI line 17. */ void USB_IRQHandler(void) { - 80042ac: b580 push {r7, lr} - 80042ae: af00 add r7, sp, #0 + 8004b34: b580 push {r7, lr} + 8004b36: af00 add r7, sp, #0 /* USER CODE BEGIN USB_IRQn 0 */ /* USER CODE END USB_IRQn 0 */ HAL_PCD_IRQHandler(&hpcd_USB_FS); - 80042b0: 4802 ldr r0, [pc, #8] ; (80042bc ) - 80042b2: f003 f903 bl 80074bc + 8004b38: 4802 ldr r0, [pc, #8] ; (8004b44 ) + 8004b3a: f003 f97b bl 8007e34 /* USER CODE BEGIN USB_IRQn 1 */ /* USER CODE END USB_IRQn 1 */ } - 80042b6: bf00 nop - 80042b8: bd80 pop {r7, pc} - 80042ba: bf00 nop - 80042bc: 20001180 .word 0x20001180 + 8004b3e: bf00 nop + 8004b40: bd80 pop {r7, pc} + 8004b42: bf00 nop + 8004b44: 20001d2c .word 0x20001d2c -080042c0 : +08004b48 : /** * @brief This function handles DMA2 channel7 global interrupt. */ void DMA2_Channel7_IRQHandler(void) { - 80042c0: b580 push {r7, lr} - 80042c2: af00 add r7, sp, #0 + 8004b48: b580 push {r7, lr} + 8004b4a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Channel7_IRQn 0 */ /* USER CODE END DMA2_Channel7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_lpuart_rx); - 80042c4: 4802 ldr r0, [pc, #8] ; (80042d0 ) - 80042c6: f001 ffb6 bl 8006236 + 8004b4c: 4802 ldr r0, [pc, #8] ; (8004b58 ) + 8004b4e: f002 f8f8 bl 8006d42 /* USER CODE BEGIN DMA2_Channel7_IRQn 1 */ /* USER CODE END DMA2_Channel7_IRQn 1 */ } - 80042ca: bf00 nop - 80042cc: bd80 pop {r7, pc} - 80042ce: bf00 nop - 80042d0: 200004bc .word 0x200004bc + 8004b52: bf00 nop + 8004b54: bd80 pop {r7, pc} + 8004b56: bf00 nop + 8004b58: 20001000 .word 0x20001000 -080042d4 : +08004b5c : /** * @brief This function handles LPUART1 global interrupt. */ void LPUART1_IRQHandler(void) { - 80042d4: b580 push {r7, lr} - 80042d6: af00 add r7, sp, #0 + 8004b5c: b580 push {r7, lr} + 8004b5e: af00 add r7, sp, #0 /* USER CODE BEGIN LPUART1_IRQn 0 */ /* USER CODE END LPUART1_IRQn 0 */ HAL_UART_IRQHandler(&hlpuart1); - 80042d8: 4802 ldr r0, [pc, #8] ; (80042e4 ) - 80042da: f006 fd17 bl 800ad0c + 8004b60: 4802 ldr r0, [pc, #8] ; (8004b6c ) + 8004b62: f007 fae7 bl 800c134 /* USER CODE BEGIN LPUART1_IRQn 1 */ /* USER CODE END LPUART1_IRQn 1 */ } - 80042de: bf00 nop - 80042e0: bd80 pop {r7, pc} - 80042e2: bf00 nop - 80042e4: 20000434 .word 0x20000434 + 8004b66: bf00 nop + 8004b68: bd80 pop {r7, pc} + 8004b6a: bf00 nop + 8004b6c: 20000ef0 .word 0x20000ef0 -080042e8 <_getpid>: +08004b70 <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { - 80042e8: b480 push {r7} - 80042ea: af00 add r7, sp, #0 + 8004b70: b480 push {r7} + 8004b72: af00 add r7, sp, #0 return 1; - 80042ec: 2301 movs r3, #1 + 8004b74: 2301 movs r3, #1 } - 80042ee: 4618 mov r0, r3 - 80042f0: 46bd mov sp, r7 - 80042f2: f85d 7b04 ldr.w r7, [sp], #4 - 80042f6: 4770 bx lr + 8004b76: 4618 mov r0, r3 + 8004b78: 46bd mov sp, r7 + 8004b7a: f85d 7b04 ldr.w r7, [sp], #4 + 8004b7e: 4770 bx lr -080042f8 <_kill>: +08004b80 <_kill>: int _kill(int pid, int sig) { - 80042f8: b580 push {r7, lr} - 80042fa: b082 sub sp, #8 - 80042fc: af00 add r7, sp, #0 - 80042fe: 6078 str r0, [r7, #4] - 8004300: 6039 str r1, [r7, #0] + 8004b80: b580 push {r7, lr} + 8004b82: b082 sub sp, #8 + 8004b84: af00 add r7, sp, #0 + 8004b86: 6078 str r0, [r7, #4] + 8004b88: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; - 8004302: f00e fc91 bl 8012c28 <__errno> - 8004306: 4603 mov r3, r0 - 8004308: 2216 movs r2, #22 - 800430a: 601a str r2, [r3, #0] + 8004b8a: f010 faa5 bl 80150d8 <__errno> + 8004b8e: 4603 mov r3, r0 + 8004b90: 2216 movs r2, #22 + 8004b92: 601a str r2, [r3, #0] return -1; - 800430c: f04f 33ff mov.w r3, #4294967295 + 8004b94: f04f 33ff mov.w r3, #4294967295 } - 8004310: 4618 mov r0, r3 - 8004312: 3708 adds r7, #8 - 8004314: 46bd mov sp, r7 - 8004316: bd80 pop {r7, pc} + 8004b98: 4618 mov r0, r3 + 8004b9a: 3708 adds r7, #8 + 8004b9c: 46bd mov sp, r7 + 8004b9e: bd80 pop {r7, pc} -08004318 <_exit>: +08004ba0 <_exit>: void _exit (int status) { - 8004318: b580 push {r7, lr} - 800431a: b082 sub sp, #8 - 800431c: af00 add r7, sp, #0 - 800431e: 6078 str r0, [r7, #4] + 8004ba0: b580 push {r7, lr} + 8004ba2: b082 sub sp, #8 + 8004ba4: af00 add r7, sp, #0 + 8004ba6: 6078 str r0, [r7, #4] _kill(status, -1); - 8004320: f04f 31ff mov.w r1, #4294967295 - 8004324: 6878 ldr r0, [r7, #4] - 8004326: f7ff ffe7 bl 80042f8 <_kill> + 8004ba8: f04f 31ff mov.w r1, #4294967295 + 8004bac: 6878 ldr r0, [r7, #4] + 8004bae: f7ff ffe7 bl 8004b80 <_kill> while (1) {} /* Make sure we hang here */ - 800432a: e7fe b.n 800432a <_exit+0x12> + 8004bb2: e7fe b.n 8004bb2 <_exit+0x12> -0800432c <_read>: +08004bb4 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { - 800432c: b580 push {r7, lr} - 800432e: b086 sub sp, #24 - 8004330: af00 add r7, sp, #0 - 8004332: 60f8 str r0, [r7, #12] - 8004334: 60b9 str r1, [r7, #8] - 8004336: 607a str r2, [r7, #4] + 8004bb4: b580 push {r7, lr} + 8004bb6: b086 sub sp, #24 + 8004bb8: af00 add r7, sp, #0 + 8004bba: 60f8 str r0, [r7, #12] + 8004bbc: 60b9 str r1, [r7, #8] + 8004bbe: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8004338: 2300 movs r3, #0 - 800433a: 617b str r3, [r7, #20] - 800433c: e00a b.n 8004354 <_read+0x28> + 8004bc0: 2300 movs r3, #0 + 8004bc2: 617b str r3, [r7, #20] + 8004bc4: e00a b.n 8004bdc <_read+0x28> { *ptr++ = __io_getchar(); - 800433e: f3af 8000 nop.w - 8004342: 4601 mov r1, r0 - 8004344: 68bb ldr r3, [r7, #8] - 8004346: 1c5a adds r2, r3, #1 - 8004348: 60ba str r2, [r7, #8] - 800434a: b2ca uxtb r2, r1 - 800434c: 701a strb r2, [r3, #0] + 8004bc6: f3af 8000 nop.w + 8004bca: 4601 mov r1, r0 + 8004bcc: 68bb ldr r3, [r7, #8] + 8004bce: 1c5a adds r2, r3, #1 + 8004bd0: 60ba str r2, [r7, #8] + 8004bd2: b2ca uxtb r2, r1 + 8004bd4: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) - 800434e: 697b ldr r3, [r7, #20] - 8004350: 3301 adds r3, #1 - 8004352: 617b str r3, [r7, #20] - 8004354: 697a ldr r2, [r7, #20] - 8004356: 687b ldr r3, [r7, #4] - 8004358: 429a cmp r2, r3 - 800435a: dbf0 blt.n 800433e <_read+0x12> + 8004bd6: 697b ldr r3, [r7, #20] + 8004bd8: 3301 adds r3, #1 + 8004bda: 617b str r3, [r7, #20] + 8004bdc: 697a ldr r2, [r7, #20] + 8004bde: 687b ldr r3, [r7, #4] + 8004be0: 429a cmp r2, r3 + 8004be2: dbf0 blt.n 8004bc6 <_read+0x12> } return len; - 800435c: 687b ldr r3, [r7, #4] + 8004be4: 687b ldr r3, [r7, #4] } - 800435e: 4618 mov r0, r3 - 8004360: 3718 adds r7, #24 - 8004362: 46bd mov sp, r7 - 8004364: bd80 pop {r7, pc} + 8004be6: 4618 mov r0, r3 + 8004be8: 3718 adds r7, #24 + 8004bea: 46bd mov sp, r7 + 8004bec: bd80 pop {r7, pc} -08004366 <_write>: +08004bee <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { - 8004366: b580 push {r7, lr} - 8004368: b086 sub sp, #24 - 800436a: af00 add r7, sp, #0 - 800436c: 60f8 str r0, [r7, #12] - 800436e: 60b9 str r1, [r7, #8] - 8004370: 607a str r2, [r7, #4] + 8004bee: b580 push {r7, lr} + 8004bf0: b086 sub sp, #24 + 8004bf2: af00 add r7, sp, #0 + 8004bf4: 60f8 str r0, [r7, #12] + 8004bf6: 60b9 str r1, [r7, #8] + 8004bf8: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8004372: 2300 movs r3, #0 - 8004374: 617b str r3, [r7, #20] - 8004376: e009 b.n 800438c <_write+0x26> + 8004bfa: 2300 movs r3, #0 + 8004bfc: 617b str r3, [r7, #20] + 8004bfe: e009 b.n 8004c14 <_write+0x26> { __io_putchar(*ptr++); - 8004378: 68bb ldr r3, [r7, #8] - 800437a: 1c5a adds r2, r3, #1 - 800437c: 60ba str r2, [r7, #8] - 800437e: 781b ldrb r3, [r3, #0] - 8004380: 4618 mov r0, r3 - 8004382: f3af 8000 nop.w + 8004c00: 68bb ldr r3, [r7, #8] + 8004c02: 1c5a adds r2, r3, #1 + 8004c04: 60ba str r2, [r7, #8] + 8004c06: 781b ldrb r3, [r3, #0] + 8004c08: 4618 mov r0, r3 + 8004c0a: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) - 8004386: 697b ldr r3, [r7, #20] - 8004388: 3301 adds r3, #1 - 800438a: 617b str r3, [r7, #20] - 800438c: 697a ldr r2, [r7, #20] - 800438e: 687b ldr r3, [r7, #4] - 8004390: 429a cmp r2, r3 - 8004392: dbf1 blt.n 8004378 <_write+0x12> + 8004c0e: 697b ldr r3, [r7, #20] + 8004c10: 3301 adds r3, #1 + 8004c12: 617b str r3, [r7, #20] + 8004c14: 697a ldr r2, [r7, #20] + 8004c16: 687b ldr r3, [r7, #4] + 8004c18: 429a cmp r2, r3 + 8004c1a: dbf1 blt.n 8004c00 <_write+0x12> } return len; - 8004394: 687b ldr r3, [r7, #4] + 8004c1c: 687b ldr r3, [r7, #4] } - 8004396: 4618 mov r0, r3 - 8004398: 3718 adds r7, #24 - 800439a: 46bd mov sp, r7 - 800439c: bd80 pop {r7, pc} + 8004c1e: 4618 mov r0, r3 + 8004c20: 3718 adds r7, #24 + 8004c22: 46bd mov sp, r7 + 8004c24: bd80 pop {r7, pc} -0800439e <_close>: +08004c26 <_close>: int _close(int file) { - 800439e: b480 push {r7} - 80043a0: b083 sub sp, #12 - 80043a2: af00 add r7, sp, #0 - 80043a4: 6078 str r0, [r7, #4] + 8004c26: b480 push {r7} + 8004c28: b083 sub sp, #12 + 8004c2a: af00 add r7, sp, #0 + 8004c2c: 6078 str r0, [r7, #4] (void)file; return -1; - 80043a6: f04f 33ff mov.w r3, #4294967295 + 8004c2e: f04f 33ff mov.w r3, #4294967295 } - 80043aa: 4618 mov r0, r3 - 80043ac: 370c adds r7, #12 - 80043ae: 46bd mov sp, r7 - 80043b0: f85d 7b04 ldr.w r7, [sp], #4 - 80043b4: 4770 bx lr + 8004c32: 4618 mov r0, r3 + 8004c34: 370c adds r7, #12 + 8004c36: 46bd mov sp, r7 + 8004c38: f85d 7b04 ldr.w r7, [sp], #4 + 8004c3c: 4770 bx lr -080043b6 <_fstat>: +08004c3e <_fstat>: int _fstat(int file, struct stat *st) { - 80043b6: b480 push {r7} - 80043b8: b083 sub sp, #12 - 80043ba: af00 add r7, sp, #0 - 80043bc: 6078 str r0, [r7, #4] - 80043be: 6039 str r1, [r7, #0] + 8004c3e: b480 push {r7} + 8004c40: b083 sub sp, #12 + 8004c42: af00 add r7, sp, #0 + 8004c44: 6078 str r0, [r7, #4] + 8004c46: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; - 80043c0: 683b ldr r3, [r7, #0] - 80043c2: f44f 5200 mov.w r2, #8192 ; 0x2000 - 80043c6: 605a str r2, [r3, #4] + 8004c48: 683b ldr r3, [r7, #0] + 8004c4a: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8004c4e: 605a str r2, [r3, #4] return 0; - 80043c8: 2300 movs r3, #0 + 8004c50: 2300 movs r3, #0 } - 80043ca: 4618 mov r0, r3 - 80043cc: 370c adds r7, #12 - 80043ce: 46bd mov sp, r7 - 80043d0: f85d 7b04 ldr.w r7, [sp], #4 - 80043d4: 4770 bx lr + 8004c52: 4618 mov r0, r3 + 8004c54: 370c adds r7, #12 + 8004c56: 46bd mov sp, r7 + 8004c58: f85d 7b04 ldr.w r7, [sp], #4 + 8004c5c: 4770 bx lr -080043d6 <_isatty>: +08004c5e <_isatty>: int _isatty(int file) { - 80043d6: b480 push {r7} - 80043d8: b083 sub sp, #12 - 80043da: af00 add r7, sp, #0 - 80043dc: 6078 str r0, [r7, #4] + 8004c5e: b480 push {r7} + 8004c60: b083 sub sp, #12 + 8004c62: af00 add r7, sp, #0 + 8004c64: 6078 str r0, [r7, #4] (void)file; return 1; - 80043de: 2301 movs r3, #1 + 8004c66: 2301 movs r3, #1 } - 80043e0: 4618 mov r0, r3 - 80043e2: 370c adds r7, #12 - 80043e4: 46bd mov sp, r7 - 80043e6: f85d 7b04 ldr.w r7, [sp], #4 - 80043ea: 4770 bx lr + 8004c68: 4618 mov r0, r3 + 8004c6a: 370c adds r7, #12 + 8004c6c: 46bd mov sp, r7 + 8004c6e: f85d 7b04 ldr.w r7, [sp], #4 + 8004c72: 4770 bx lr -080043ec <_lseek>: +08004c74 <_lseek>: int _lseek(int file, int ptr, int dir) { - 80043ec: b480 push {r7} - 80043ee: b085 sub sp, #20 - 80043f0: af00 add r7, sp, #0 - 80043f2: 60f8 str r0, [r7, #12] - 80043f4: 60b9 str r1, [r7, #8] - 80043f6: 607a str r2, [r7, #4] + 8004c74: b480 push {r7} + 8004c76: b085 sub sp, #20 + 8004c78: af00 add r7, sp, #0 + 8004c7a: 60f8 str r0, [r7, #12] + 8004c7c: 60b9 str r1, [r7, #8] + 8004c7e: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; - 80043f8: 2300 movs r3, #0 + 8004c80: 2300 movs r3, #0 } - 80043fa: 4618 mov r0, r3 - 80043fc: 3714 adds r7, #20 - 80043fe: 46bd mov sp, r7 - 8004400: f85d 7b04 ldr.w r7, [sp], #4 - 8004404: 4770 bx lr + 8004c82: 4618 mov r0, r3 + 8004c84: 3714 adds r7, #20 + 8004c86: 46bd mov sp, r7 + 8004c88: f85d 7b04 ldr.w r7, [sp], #4 + 8004c8c: 4770 bx lr ... -08004408 <_sbrk>: +08004c90 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { - 8004408: b580 push {r7, lr} - 800440a: b086 sub sp, #24 - 800440c: af00 add r7, sp, #0 - 800440e: 6078 str r0, [r7, #4] + 8004c90: b580 push {r7, lr} + 8004c92: b086 sub sp, #24 + 8004c94: af00 add r7, sp, #0 + 8004c96: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - 8004410: 4a14 ldr r2, [pc, #80] ; (8004464 <_sbrk+0x5c>) - 8004412: 4b15 ldr r3, [pc, #84] ; (8004468 <_sbrk+0x60>) - 8004414: 1ad3 subs r3, r2, r3 - 8004416: 617b str r3, [r7, #20] + 8004c98: 4a14 ldr r2, [pc, #80] ; (8004cec <_sbrk+0x5c>) + 8004c9a: 4b15 ldr r3, [pc, #84] ; (8004cf0 <_sbrk+0x60>) + 8004c9c: 1ad3 subs r3, r2, r3 + 8004c9e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; - 8004418: 697b ldr r3, [r7, #20] - 800441a: 613b str r3, [r7, #16] + 8004ca0: 697b ldr r3, [r7, #20] + 8004ca2: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) - 800441c: 4b13 ldr r3, [pc, #76] ; (800446c <_sbrk+0x64>) - 800441e: 681b ldr r3, [r3, #0] - 8004420: 2b00 cmp r3, #0 - 8004422: d102 bne.n 800442a <_sbrk+0x22> + 8004ca4: 4b13 ldr r3, [pc, #76] ; (8004cf4 <_sbrk+0x64>) + 8004ca6: 681b ldr r3, [r3, #0] + 8004ca8: 2b00 cmp r3, #0 + 8004caa: d102 bne.n 8004cb2 <_sbrk+0x22> { __sbrk_heap_end = &_end; - 8004424: 4b11 ldr r3, [pc, #68] ; (800446c <_sbrk+0x64>) - 8004426: 4a12 ldr r2, [pc, #72] ; (8004470 <_sbrk+0x68>) - 8004428: 601a str r2, [r3, #0] + 8004cac: 4b11 ldr r3, [pc, #68] ; (8004cf4 <_sbrk+0x64>) + 8004cae: 4a12 ldr r2, [pc, #72] ; (8004cf8 <_sbrk+0x68>) + 8004cb0: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8004cb2: 4b10 ldr r3, [pc, #64] ; (8004cf4 <_sbrk+0x64>) + 8004cb4: 681a ldr r2, [r3, #0] + 8004cb6: 687b ldr r3, [r7, #4] + 8004cb8: 4413 add r3, r2 + 8004cba: 693a ldr r2, [r7, #16] + 8004cbc: 429a cmp r2, r3 + 8004cbe: d207 bcs.n 8004cd0 <_sbrk+0x40> + { + errno = ENOMEM; + 8004cc0: f010 fa0a bl 80150d8 <__errno> + 8004cc4: 4603 mov r3, r0 + 8004cc6: 220c movs r2, #12 + 8004cc8: 601a str r2, [r3, #0] + return (void *)-1; + 8004cca: f04f 33ff mov.w r3, #4294967295 + 8004cce: e009 b.n 8004ce4 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8004cd0: 4b08 ldr r3, [pc, #32] ; (8004cf4 <_sbrk+0x64>) + 8004cd2: 681b ldr r3, [r3, #0] + 8004cd4: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8004cd6: 4b07 ldr r3, [pc, #28] ; (8004cf4 <_sbrk+0x64>) + 8004cd8: 681a ldr r2, [r3, #0] + 8004cda: 687b ldr r3, [r7, #4] + 8004cdc: 4413 add r3, r2 + 8004cde: 4a05 ldr r2, [pc, #20] ; (8004cf4 <_sbrk+0x64>) + 8004ce0: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8004ce2: 68fb ldr r3, [r7, #12] +} + 8004ce4: 4618 mov r0, r3 + 8004ce6: 3718 adds r7, #24 + 8004ce8: 46bd mov sp, r7 + 8004cea: bd80 pop {r7, pc} + 8004cec: 20010000 .word 0x20010000 + 8004cf0: 00000400 .word 0x00000400 + 8004cf4: 20000ea0 .word 0x20000ea0 + 8004cf8: 20002390 .word 0x20002390 + +08004cfc : + * @brief Setup the microcontroller system. + * @retval None + */ + +void SystemInit(void) +{ + 8004cfc: b480 push {r7} + 8004cfe: af00 add r7, sp, #0 + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + 8004d00: 4b06 ldr r3, [pc, #24] ; (8004d1c ) + 8004d02: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8004d06: 4a05 ldr r2, [pc, #20] ; (8004d1c ) + 8004d08: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8004d0c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 +#endif +} + 8004d10: bf00 nop + 8004d12: 46bd mov sp, r7 + 8004d14: f85d 7b04 ldr.w r7, [sp], #4 + 8004d18: 4770 bx lr + 8004d1a: bf00 nop + 8004d1c: e000ed00 .word 0xe000ed00 + +08004d20 : + +TIM_HandleTypeDef htim2; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + 8004d20: b580 push {r7, lr} + 8004d22: b088 sub sp, #32 + 8004d24: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8004d26: f107 0310 add.w r3, r7, #16 + 8004d2a: 2200 movs r2, #0 + 8004d2c: 601a str r2, [r3, #0] + 8004d2e: 605a str r2, [r3, #4] + 8004d30: 609a str r2, [r3, #8] + 8004d32: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8004d34: 1d3b adds r3, r7, #4 + 8004d36: 2200 movs r2, #0 + 8004d38: 601a str r2, [r3, #0] + 8004d3a: 605a str r2, [r3, #4] + 8004d3c: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8004d3e: 4b1e ldr r3, [pc, #120] ; (8004db8 ) + 8004d40: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8004d44: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 400-1; + 8004d46: 4b1c ldr r3, [pc, #112] ; (8004db8 ) + 8004d48: f240 128f movw r2, #399 ; 0x18f + 8004d4c: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8004d4e: 4b1a ldr r3, [pc, #104] ; (8004db8 ) + 8004d50: 2200 movs r2, #0 + 8004d52: 609a str r2, [r3, #8] + htim2.Init.Period = 10000-1; + 8004d54: 4b18 ldr r3, [pc, #96] ; (8004db8 ) + 8004d56: f242 720f movw r2, #9999 ; 0x270f + 8004d5a: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8004d5c: 4b16 ldr r3, [pc, #88] ; (8004db8 ) + 8004d5e: 2200 movs r2, #0 + 8004d60: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8004d62: 4b15 ldr r3, [pc, #84] ; (8004db8 ) + 8004d64: 2200 movs r2, #0 + 8004d66: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 8004d68: 4813 ldr r0, [pc, #76] ; (8004db8 ) + 8004d6a: f006 fd7b bl 800b864 + 8004d6e: 4603 mov r3, r0 + 8004d70: 2b00 cmp r3, #0 + 8004d72: d001 beq.n 8004d78 + { + Error_Handler(); + 8004d74: f7fc fe3d bl 80019f2 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8004d78: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8004d7c: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 8004d7e: f107 0310 add.w r3, r7, #16 + 8004d82: 4619 mov r1, r3 + 8004d84: 480c ldr r0, [pc, #48] ; (8004db8 ) + 8004d86: f006 fe11 bl 800b9ac + 8004d8a: 4603 mov r3, r0 + 8004d8c: 2b00 cmp r3, #0 + 8004d8e: d001 beq.n 8004d94 + { + Error_Handler(); + 8004d90: f7fc fe2f bl 80019f2 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; + 8004d94: 2320 movs r3, #32 + 8004d96: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8004d98: 2300 movs r3, #0 + 8004d9a: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8004d9c: 1d3b adds r3, r7, #4 + 8004d9e: 4619 mov r1, r3 + 8004da0: 4805 ldr r0, [pc, #20] ; (8004db8 ) + 8004da2: f006 ffcb bl 800bd3c + 8004da6: 4603 mov r3, r0 + 8004da8: 2b00 cmp r3, #0 + 8004daa: d001 beq.n 8004db0 + { + Error_Handler(); + 8004dac: f7fc fe21 bl 80019f2 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8004db0: bf00 nop + 8004db2: 3720 adds r7, #32 + 8004db4: 46bd mov sp, r7 + 8004db6: bd80 pop {r7, pc} + 8004db8: 20000ea4 .word 0x20000ea4 + +08004dbc : + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + 8004dbc: b480 push {r7} + 8004dbe: b085 sub sp, #20 + 8004dc0: af00 add r7, sp, #0 + 8004dc2: 6078 str r0, [r7, #4] + + if(tim_baseHandle->Instance==TIM2) + 8004dc4: 687b ldr r3, [r7, #4] + 8004dc6: 681b ldr r3, [r3, #0] + 8004dc8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8004dcc: d10b bne.n 8004de6 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8004dce: 4b09 ldr r3, [pc, #36] ; (8004df4 ) + 8004dd0: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004dd2: 4a08 ldr r2, [pc, #32] ; (8004df4 ) + 8004dd4: f043 0301 orr.w r3, r3, #1 + 8004dd8: 6593 str r3, [r2, #88] ; 0x58 + 8004dda: 4b06 ldr r3, [pc, #24] ; (8004df4 ) + 8004ddc: 6d9b ldr r3, [r3, #88] ; 0x58 + 8004dde: f003 0301 and.w r3, r3, #1 + 8004de2: 60fb str r3, [r7, #12] + 8004de4: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } +} + 8004de6: bf00 nop + 8004de8: 3714 adds r7, #20 + 8004dea: 46bd mov sp, r7 + 8004dec: f85d 7b04 ldr.w r7, [sp], #4 + 8004df0: 4770 bx lr + 8004df2: bf00 nop + 8004df4: 40021000 .word 0x40021000 + +08004df8 : +DMA_HandleTypeDef hdma_lpuart_rx; + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + 8004df8: b580 push {r7, lr} + 8004dfa: af00 add r7, sp, #0 + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + 8004dfc: 4b12 ldr r3, [pc, #72] ; (8004e48 ) + 8004dfe: 4a13 ldr r2, [pc, #76] ; (8004e4c ) + 8004e00: 601a str r2, [r3, #0] + hlpuart1.Init.BaudRate = 9600; + 8004e02: 4b11 ldr r3, [pc, #68] ; (8004e48 ) + 8004e04: f44f 5216 mov.w r2, #9600 ; 0x2580 + 8004e08: 605a str r2, [r3, #4] + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + 8004e0a: 4b0f ldr r3, [pc, #60] ; (8004e48 ) + 8004e0c: 2200 movs r2, #0 + 8004e0e: 609a str r2, [r3, #8] + hlpuart1.Init.StopBits = UART_STOPBITS_1; + 8004e10: 4b0d ldr r3, [pc, #52] ; (8004e48 ) + 8004e12: 2200 movs r2, #0 + 8004e14: 60da str r2, [r3, #12] + hlpuart1.Init.Parity = UART_PARITY_NONE; + 8004e16: 4b0c ldr r3, [pc, #48] ; (8004e48 ) + 8004e18: 2200 movs r2, #0 + 8004e1a: 611a str r2, [r3, #16] + hlpuart1.Init.Mode = UART_MODE_TX_RX; + 8004e1c: 4b0a ldr r3, [pc, #40] ; (8004e48 ) + 8004e1e: 220c movs r2, #12 + 8004e20: 615a str r2, [r3, #20] + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8004e22: 4b09 ldr r3, [pc, #36] ; (8004e48 ) + 8004e24: 2200 movs r2, #0 + 8004e26: 619a str r2, [r3, #24] + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8004e28: 4b07 ldr r3, [pc, #28] ; (8004e48 ) + 8004e2a: 2200 movs r2, #0 + 8004e2c: 621a str r2, [r3, #32] + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8004e2e: 4b06 ldr r3, [pc, #24] ; (8004e48 ) + 8004e30: 2200 movs r2, #0 + 8004e32: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + 8004e34: 4804 ldr r0, [pc, #16] ; (8004e48 ) + 8004e36: f006 ffe7 bl 800be08 + 8004e3a: 4603 mov r3, r0 + 8004e3c: 2b00 cmp r3, #0 + 8004e3e: d001 beq.n 8004e44 + { + Error_Handler(); + 8004e40: f7fc fdd7 bl 80019f2 + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + +} + 8004e44: bf00 nop + 8004e46: bd80 pop {r7, pc} + 8004e48: 20000ef0 .word 0x20000ef0 + 8004e4c: 40008000 .word 0x40008000 + +08004e50 : +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + 8004e50: b580 push {r7, lr} + 8004e52: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 8004e54: 4b14 ldr r3, [pc, #80] ; (8004ea8 ) + 8004e56: 4a15 ldr r2, [pc, #84] ; (8004eac ) + 8004e58: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 8004e5a: 4b13 ldr r3, [pc, #76] ; (8004ea8 ) + 8004e5c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8004e60: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 8004e62: 4b11 ldr r3, [pc, #68] ; (8004ea8 ) + 8004e64: 2200 movs r2, #0 + 8004e66: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 8004e68: 4b0f ldr r3, [pc, #60] ; (8004ea8 ) + 8004e6a: 2200 movs r2, #0 + 8004e6c: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 8004e6e: 4b0e ldr r3, [pc, #56] ; (8004ea8 ) + 8004e70: 2200 movs r2, #0 + 8004e72: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8004e74: 4b0c ldr r3, [pc, #48] ; (8004ea8 ) + 8004e76: 220c movs r2, #12 + 8004e78: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8004e7a: 4b0b ldr r3, [pc, #44] ; (8004ea8 ) + 8004e7c: 2200 movs r2, #0 + 8004e7e: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 8004e80: 4b09 ldr r3, [pc, #36] ; (8004ea8 ) + 8004e82: 2200 movs r2, #0 + 8004e84: 61da str r2, [r3, #28] + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8004e86: 4b08 ldr r3, [pc, #32] ; (8004ea8 ) + 8004e88: 2200 movs r2, #0 + 8004e8a: 621a str r2, [r3, #32] + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8004e8c: 4b06 ldr r3, [pc, #24] ; (8004ea8 ) + 8004e8e: 2200 movs r2, #0 + 8004e90: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart1) != HAL_OK) + 8004e92: 4805 ldr r0, [pc, #20] ; (8004ea8 ) + 8004e94: f006 ffb8 bl 800be08 + 8004e98: 4603 mov r3, r0 + 8004e9a: 2b00 cmp r3, #0 + 8004e9c: d001 beq.n 8004ea2 + { + Error_Handler(); + 8004e9e: f7fc fda8 bl 80019f2 } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 8004ea2: bf00 nop + 8004ea4: bd80 pop {r7, pc} + 8004ea6: bf00 nop + 8004ea8: 20000f78 .word 0x20000f78 + 8004eac: 40013800 .word 0x40013800 + +08004eb0 : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 8004eb0: b580 push {r7, lr} + 8004eb2: b0a0 sub sp, #128 ; 0x80 + 8004eb4: af00 add r7, sp, #0 + 8004eb6: 6078 str r0, [r7, #4] - /* Protect heap from growing into the reserved MSP stack */ - if (__sbrk_heap_end + incr > max_heap) - 800442a: 4b10 ldr r3, [pc, #64] ; (800446c <_sbrk+0x64>) - 800442c: 681a ldr r2, [r3, #0] - 800442e: 687b ldr r3, [r7, #4] - 8004430: 4413 add r3, r2 - 8004432: 693a ldr r2, [r7, #16] - 8004434: 429a cmp r2, r3 - 8004436: d207 bcs.n 8004448 <_sbrk+0x40> - { - errno = ENOMEM; - 8004438: f00e fbf6 bl 8012c28 <__errno> - 800443c: 4603 mov r3, r0 - 800443e: 220c movs r2, #12 - 8004440: 601a str r2, [r3, #0] - return (void *)-1; - 8004442: f04f 33ff mov.w r3, #4294967295 - 8004446: e009 b.n 800445c <_sbrk+0x54> - } + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8004eb8: f107 036c add.w r3, r7, #108 ; 0x6c + 8004ebc: 2200 movs r2, #0 + 8004ebe: 601a str r2, [r3, #0] + 8004ec0: 605a str r2, [r3, #4] + 8004ec2: 609a str r2, [r3, #8] + 8004ec4: 60da str r2, [r3, #12] + 8004ec6: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 8004ec8: f107 0318 add.w r3, r7, #24 + 8004ecc: 2254 movs r2, #84 ; 0x54 + 8004ece: 2100 movs r1, #0 + 8004ed0: 4618 mov r0, r3 + 8004ed2: f010 f81a bl 8014f0a + if(uartHandle->Instance==LPUART1) + 8004ed6: 687b ldr r3, [r7, #4] + 8004ed8: 681b ldr r3, [r3, #0] + 8004eda: 4a55 ldr r2, [pc, #340] ; (8005030 ) + 8004edc: 4293 cmp r3, r2 + 8004ede: d168 bne.n 8004fb2 - prev_heap_end = __sbrk_heap_end; - 8004448: 4b08 ldr r3, [pc, #32] ; (800446c <_sbrk+0x64>) - 800444a: 681b ldr r3, [r3, #0] - 800444c: 60fb str r3, [r7, #12] - __sbrk_heap_end += incr; - 800444e: 4b07 ldr r3, [pc, #28] ; (800446c <_sbrk+0x64>) - 8004450: 681a ldr r2, [r3, #0] - 8004452: 687b ldr r3, [r7, #4] - 8004454: 4413 add r3, r2 - 8004456: 4a05 ldr r2, [pc, #20] ; (800446c <_sbrk+0x64>) - 8004458: 6013 str r3, [r2, #0] + /* USER CODE END LPUART1_MspInit 0 */ - return (void *)prev_heap_end; - 800445a: 68fb ldr r3, [r7, #12] -} - 800445c: 4618 mov r0, r3 - 800445e: 3718 adds r7, #24 - 8004460: 46bd mov sp, r7 - 8004462: bd80 pop {r7, pc} - 8004464: 20010000 .word 0x20010000 - 8004468: 00000400 .word 0x00000400 - 800446c: 20000c98 .word 0x20000c98 - 8004470: 200015d8 .word 0x200015d8 - -08004474 : - * @brief Setup the microcontroller system. - * @retval None + /** Initializes the peripherals clock */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + 8004ee0: 2320 movs r3, #32 + 8004ee2: 61bb str r3, [r7, #24] + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + 8004ee4: 2300 movs r3, #0 + 8004ee6: 643b str r3, [r7, #64] ; 0x40 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8004ee8: f107 0318 add.w r3, r7, #24 + 8004eec: 4618 mov r0, r3 + 8004eee: f005 faa3 bl 800a438 + 8004ef2: 4603 mov r3, r0 + 8004ef4: 2b00 cmp r3, #0 + 8004ef6: d001 beq.n 8004efc + { + Error_Handler(); + 8004ef8: f7fc fd7b bl 80019f2 + } -void SystemInit(void) -{ - 8004474: b480 push {r7} - 8004476: af00 add r7, sp, #0 - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; -#endif + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + 8004efc: 4b4d ldr r3, [pc, #308] ; (8005034 ) + 8004efe: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004f00: 4a4c ldr r2, [pc, #304] ; (8005034 ) + 8004f02: f043 0301 orr.w r3, r3, #1 + 8004f06: 65d3 str r3, [r2, #92] ; 0x5c + 8004f08: 4b4a ldr r3, [pc, #296] ; (8005034 ) + 8004f0a: 6ddb ldr r3, [r3, #92] ; 0x5c + 8004f0c: f003 0301 and.w r3, r3, #1 + 8004f10: 617b str r3, [r7, #20] + 8004f12: 697b ldr r3, [r7, #20] - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ - 8004478: 4b06 ldr r3, [pc, #24] ; (8004494 ) - 800447a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800447e: 4a05 ldr r2, [pc, #20] ; (8004494 ) - 8004480: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 8004484: f8c2 3088 str.w r3, [r2, #136] ; 0x88 -#endif -} - 8004488: bf00 nop - 800448a: 46bd mov sp, r7 - 800448c: f85d 7b04 ldr.w r7, [sp], #4 - 8004490: 4770 bx lr - 8004492: bf00 nop - 8004494: e000ed00 .word 0xe000ed00 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8004f14: 4b47 ldr r3, [pc, #284] ; (8005034 ) + 8004f16: 6cdb ldr r3, [r3, #76] ; 0x4c + 8004f18: 4a46 ldr r2, [pc, #280] ; (8005034 ) + 8004f1a: f043 0301 orr.w r3, r3, #1 + 8004f1e: 64d3 str r3, [r2, #76] ; 0x4c + 8004f20: 4b44 ldr r3, [pc, #272] ; (8005034 ) + 8004f22: 6cdb ldr r3, [r3, #76] ; 0x4c + 8004f24: f003 0301 and.w r3, r3, #1 + 8004f28: 613b str r3, [r7, #16] + 8004f2a: 693b ldr r3, [r7, #16] + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + 8004f2c: 230c movs r3, #12 + 8004f2e: 66fb str r3, [r7, #108] ; 0x6c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004f30: 2302 movs r3, #2 + 8004f32: 673b str r3, [r7, #112] ; 0x70 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004f34: 2300 movs r3, #0 + 8004f36: 677b str r3, [r7, #116] ; 0x74 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8004f38: 2303 movs r3, #3 + 8004f3a: 67bb str r3, [r7, #120] ; 0x78 + GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; + 8004f3c: 2308 movs r3, #8 + 8004f3e: 67fb str r3, [r7, #124] ; 0x7c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8004f40: f107 036c add.w r3, r7, #108 ; 0x6c + 8004f44: 4619 mov r1, r3 + 8004f46: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8004f4a: f001 ffe5 bl 8006f18 + + /* LPUART1 DMA Init */ + /* LPUART_RX Init */ + hdma_lpuart_rx.Instance = DMA2_Channel7; + 8004f4e: 4b3a ldr r3, [pc, #232] ; (8005038 ) + 8004f50: 4a3a ldr r2, [pc, #232] ; (800503c ) + 8004f52: 601a str r2, [r3, #0] + hdma_lpuart_rx.Init.Request = DMA_REQUEST_4; + 8004f54: 4b38 ldr r3, [pc, #224] ; (8005038 ) + 8004f56: 2204 movs r2, #4 + 8004f58: 605a str r2, [r3, #4] + hdma_lpuart_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + 8004f5a: 4b37 ldr r3, [pc, #220] ; (8005038 ) + 8004f5c: 2200 movs r2, #0 + 8004f5e: 609a str r2, [r3, #8] + hdma_lpuart_rx.Init.PeriphInc = DMA_PINC_DISABLE; + 8004f60: 4b35 ldr r3, [pc, #212] ; (8005038 ) + 8004f62: 2200 movs r2, #0 + 8004f64: 60da str r2, [r3, #12] + hdma_lpuart_rx.Init.MemInc = DMA_MINC_ENABLE; + 8004f66: 4b34 ldr r3, [pc, #208] ; (8005038 ) + 8004f68: 2280 movs r2, #128 ; 0x80 + 8004f6a: 611a str r2, [r3, #16] + hdma_lpuart_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 8004f6c: 4b32 ldr r3, [pc, #200] ; (8005038 ) + 8004f6e: 2200 movs r2, #0 + 8004f70: 615a str r2, [r3, #20] + hdma_lpuart_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 8004f72: 4b31 ldr r3, [pc, #196] ; (8005038 ) + 8004f74: 2200 movs r2, #0 + 8004f76: 619a str r2, [r3, #24] + hdma_lpuart_rx.Init.Mode = DMA_NORMAL; + 8004f78: 4b2f ldr r3, [pc, #188] ; (8005038 ) + 8004f7a: 2200 movs r2, #0 + 8004f7c: 61da str r2, [r3, #28] + hdma_lpuart_rx.Init.Priority = DMA_PRIORITY_LOW; + 8004f7e: 4b2e ldr r3, [pc, #184] ; (8005038 ) + 8004f80: 2200 movs r2, #0 + 8004f82: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_lpuart_rx) != HAL_OK) + 8004f84: 482c ldr r0, [pc, #176] ; (8005038 ) + 8004f86: f001 fd45 bl 8006a14 + 8004f8a: 4603 mov r3, r0 + 8004f8c: 2b00 cmp r3, #0 + 8004f8e: d001 beq.n 8004f94 + { + Error_Handler(); + 8004f90: f7fc fd2f bl 80019f2 + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_lpuart_rx); + 8004f94: 687b ldr r3, [r7, #4] + 8004f96: 4a28 ldr r2, [pc, #160] ; (8005038 ) + 8004f98: 675a str r2, [r3, #116] ; 0x74 + 8004f9a: 4a27 ldr r2, [pc, #156] ; (8005038 ) + 8004f9c: 687b ldr r3, [r7, #4] + 8004f9e: 6293 str r3, [r2, #40] ; 0x28 + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + 8004fa0: 2200 movs r2, #0 + 8004fa2: 2100 movs r1, #0 + 8004fa4: 2046 movs r0, #70 ; 0x46 + 8004fa6: f001 fcfe bl 80069a6 + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + 8004faa: 2046 movs r0, #70 ; 0x46 + 8004fac: f001 fd17 bl 80069de + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + 8004fb0: e03a b.n 8005028 + else if(uartHandle->Instance==USART1) + 8004fb2: 687b ldr r3, [r7, #4] + 8004fb4: 681b ldr r3, [r3, #0] + 8004fb6: 4a22 ldr r2, [pc, #136] ; (8005040 ) + 8004fb8: 4293 cmp r3, r2 + 8004fba: d135 bne.n 8005028 + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + 8004fbc: 2301 movs r3, #1 + 8004fbe: 61bb str r3, [r7, #24] + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 8004fc0: 2300 movs r3, #0 + 8004fc2: 63bb str r3, [r7, #56] ; 0x38 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8004fc4: f107 0318 add.w r3, r7, #24 + 8004fc8: 4618 mov r0, r3 + 8004fca: f005 fa35 bl 800a438 + 8004fce: 4603 mov r3, r0 + 8004fd0: 2b00 cmp r3, #0 + 8004fd2: d001 beq.n 8004fd8 + Error_Handler(); + 8004fd4: f7fc fd0d bl 80019f2 + __HAL_RCC_USART1_CLK_ENABLE(); + 8004fd8: 4b16 ldr r3, [pc, #88] ; (8005034 ) + 8004fda: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004fdc: 4a15 ldr r2, [pc, #84] ; (8005034 ) + 8004fde: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8004fe2: 6613 str r3, [r2, #96] ; 0x60 + 8004fe4: 4b13 ldr r3, [pc, #76] ; (8005034 ) + 8004fe6: 6e1b ldr r3, [r3, #96] ; 0x60 + 8004fe8: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8004fec: 60fb str r3, [r7, #12] + 8004fee: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8004ff0: 4b10 ldr r3, [pc, #64] ; (8005034 ) + 8004ff2: 6cdb ldr r3, [r3, #76] ; 0x4c + 8004ff4: 4a0f ldr r2, [pc, #60] ; (8005034 ) + 8004ff6: f043 0302 orr.w r3, r3, #2 + 8004ffa: 64d3 str r3, [r2, #76] ; 0x4c + 8004ffc: 4b0d ldr r3, [pc, #52] ; (8005034 ) + 8004ffe: 6cdb ldr r3, [r3, #76] ; 0x4c + 8005000: f003 0302 and.w r3, r3, #2 + 8005004: 60bb str r3, [r7, #8] + 8005006: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + 8005008: 23c0 movs r3, #192 ; 0xc0 + 800500a: 66fb str r3, [r7, #108] ; 0x6c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800500c: 2302 movs r3, #2 + 800500e: 673b str r3, [r7, #112] ; 0x70 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005010: 2300 movs r3, #0 + 8005012: 677b str r3, [r7, #116] ; 0x74 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8005014: 2303 movs r3, #3 + 8005016: 67bb str r3, [r7, #120] ; 0x78 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 8005018: 2307 movs r3, #7 + 800501a: 67fb str r3, [r7, #124] ; 0x7c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800501c: f107 036c add.w r3, r7, #108 ; 0x6c + 8005020: 4619 mov r1, r3 + 8005022: 4808 ldr r0, [pc, #32] ; (8005044 ) + 8005024: f001 ff78 bl 8006f18 +} + 8005028: bf00 nop + 800502a: 3780 adds r7, #128 ; 0x80 + 800502c: 46bd mov sp, r7 + 800502e: bd80 pop {r7, pc} + 8005030: 40008000 .word 0x40008000 + 8005034: 40021000 .word 0x40021000 + 8005038: 20001000 .word 0x20001000 + 800503c: 40020480 .word 0x40020480 + 8005040: 40013800 .word 0x40013800 + 8005044: 48000400 .word 0x48000400 + +08005048 : + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart){ + 8005048: b5f0 push {r4, r5, r6, r7, lr} + 800504a: b085 sub sp, #20 + 800504c: af00 add r7, sp, #0 + 800504e: 6078 str r0, [r7, #4] + oldPos = newPos; //keep track of the last position in the buffer + 8005050: 4b30 ldr r3, [pc, #192] ; (8005114 ) + 8005052: 881a ldrh r2, [r3, #0] + 8005054: 4b30 ldr r3, [pc, #192] ; (8005118 ) + 8005056: 801a strh r2, [r3, #0] + if(oldPos + 64 > DataBuffer_SIZE){ //if the buffer is full, parse it, then reset the buffer + 8005058: 4b2f ldr r3, [pc, #188] ; (8005118 ) + 800505a: 881b ldrh r3, [r3, #0] + 800505c: f5b3 7fe0 cmp.w r3, #448 ; 0x1c0 + 8005060: d922 bls.n 80050a8 + + uint16_t datatocopy = DataBuffer_SIZE-oldPos; // find out how much space is left in the main buffer + 8005062: 4b2d ldr r3, [pc, #180] ; (8005118 ) + 8005064: 881b ldrh r3, [r3, #0] + 8005066: f5c3 7300 rsb r3, r3, #512 ; 0x200 + 800506a: 81fb strh r3, [r7, #14] + memcpy ((uint8_t *)DataBuffer+oldPos, RxBuffer, datatocopy); // copy data in that remaining space + 800506c: 4b2a ldr r3, [pc, #168] ; (8005118 ) + 800506e: 881b ldrh r3, [r3, #0] + 8005070: 461a mov r2, r3 + 8005072: 4b2a ldr r3, [pc, #168] ; (800511c ) + 8005074: 4413 add r3, r2 + 8005076: 89fa ldrh r2, [r7, #14] + 8005078: 4929 ldr r1, [pc, #164] ; (8005120 ) + 800507a: 4618 mov r0, r3 + 800507c: f010 f861 bl 8015142 + + oldPos = 0; // point to the start of the buffer + 8005080: 4b25 ldr r3, [pc, #148] ; (8005118 ) + 8005082: 2200 movs r2, #0 + 8005084: 801a strh r2, [r3, #0] + memcpy ((uint8_t *)DataBuffer, (uint8_t *)RxBuffer+datatocopy, (64-datatocopy)); // copy the remaining data + 8005086: 89fb ldrh r3, [r7, #14] + 8005088: 4a25 ldr r2, [pc, #148] ; (8005120 ) + 800508a: 1899 adds r1, r3, r2 + 800508c: 89fb ldrh r3, [r7, #14] + 800508e: f1c3 0340 rsb r3, r3, #64 ; 0x40 + 8005092: 461a mov r2, r3 + 8005094: 4821 ldr r0, [pc, #132] ; (800511c ) + 8005096: f010 f854 bl 8015142 + newPos = (64-datatocopy); // update the position + 800509a: 89fb ldrh r3, [r7, #14] + 800509c: f1c3 0340 rsb r3, r3, #64 ; 0x40 + 80050a0: b29a uxth r2, r3 + 80050a2: 4b1c ldr r3, [pc, #112] ; (8005114 ) + 80050a4: 801a strh r2, [r3, #0] + 80050a6: e01e b.n 80050e6 + } + else{ + memcpy((uint8_t *)DataBuffer+oldPos, RxBuffer, 64); //copy received data to the buffer + 80050a8: 4b1b ldr r3, [pc, #108] ; (8005118 ) + 80050aa: 881b ldrh r3, [r3, #0] + 80050ac: 461a mov r2, r3 + 80050ae: 4b1b ldr r3, [pc, #108] ; (800511c ) + 80050b0: 441a add r2, r3 + 80050b2: 4b1b ldr r3, [pc, #108] ; (8005120 ) + 80050b4: 4610 mov r0, r2 + 80050b6: f103 0440 add.w r4, r3, #64 ; 0x40 + 80050ba: 4602 mov r2, r0 + 80050bc: 4619 mov r1, r3 + 80050be: f8d1 c000 ldr.w ip, [r1] + 80050c2: 684e ldr r6, [r1, #4] + 80050c4: 688d ldr r5, [r1, #8] + 80050c6: 68c9 ldr r1, [r1, #12] + 80050c8: f8c2 c000 str.w ip, [r2] + 80050cc: 6056 str r6, [r2, #4] + 80050ce: 6095 str r5, [r2, #8] + 80050d0: 60d1 str r1, [r2, #12] + 80050d2: 3310 adds r3, #16 + 80050d4: 3010 adds r0, #16 + 80050d6: 42a3 cmp r3, r4 + 80050d8: d1ef bne.n 80050ba + newPos = 64+oldPos; //update buffer position + 80050da: 4b0f ldr r3, [pc, #60] ; (8005118 ) + 80050dc: 881b ldrh r3, [r3, #0] + 80050de: 3340 adds r3, #64 ; 0x40 + 80050e0: b29a uxth r2, r3 + 80050e2: 4b0c ldr r3, [pc, #48] ; (8005114 ) + 80050e4: 801a strh r2, [r3, #0] + + } + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//on recoit par dma à nouveau 64 caractères + 80050e6: 2240 movs r2, #64 ; 0x40 + 80050e8: 490d ldr r1, [pc, #52] ; (8005120 ) + 80050ea: 480e ldr r0, [pc, #56] ; (8005124 ) + 80050ec: f006 feda bl 800bea4 + __HAL_DMA_DISABLE_IT(&hdma_lpuart_rx, DMA_IT_HT);//on desactive l'interruption afin de ne pas être interrompu tout le temps + 80050f0: 4b0d ldr r3, [pc, #52] ; (8005128 ) + 80050f2: 681b ldr r3, [r3, #0] + 80050f4: 681a ldr r2, [r3, #0] + 80050f6: 4b0c ldr r3, [pc, #48] ; (8005128 ) + 80050f8: 681b ldr r3, [r3, #0] + 80050fa: f022 0204 bic.w r2, r2, #4 + 80050fe: 601a str r2, [r3, #0] -08004498 : + HAL_UART_Receive_DMA(&hlpuart1, (uint8_t *)RxBuffer, RxBuffer_SIZE);//l'appel de cette fonction réactive l'intérruption. + 8005100: 2240 movs r2, #64 ; 0x40 + 8005102: 4907 ldr r1, [pc, #28] ; (8005120 ) + 8005104: 4807 ldr r0, [pc, #28] ; (8005124 ) + 8005106: f006 fecd bl 800bea4 +} + 800510a: bf00 nop + 800510c: 3714 adds r7, #20 + 800510e: 46bd mov sp, r7 + 8005110: bdf0 pop {r4, r5, r6, r7, pc} + 8005112: bf00 nop + 8005114: 2000046a .word 0x2000046a + 8005118: 20000468 .word 0x20000468 + 800511c: 200004ac .word 0x200004ac + 8005120: 2000046c .word 0x2000046c + 8005124: 20000ef0 .word 0x20000ef0 + 8005128: 20001000 .word 0x20001000 + +0800512c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Set stack pointer */ - 8004498: f8df d034 ldr.w sp, [pc, #52] ; 80044d0 + 800512c: f8df d034 ldr.w sp, [pc, #52] ; 8005164 /* Call the clock system initialization function.*/ bl SystemInit - 800449c: f7ff ffea bl 8004474 + 8005130: f7ff fde4 bl 8004cfc /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 80044a0: 480c ldr r0, [pc, #48] ; (80044d4 ) + 8005134: 480c ldr r0, [pc, #48] ; (8005168 ) ldr r1, =_edata - 80044a2: 490d ldr r1, [pc, #52] ; (80044d8 ) + 8005136: 490d ldr r1, [pc, #52] ; (800516c ) ldr r2, =_sidata - 80044a4: 4a0d ldr r2, [pc, #52] ; (80044dc ) + 8005138: 4a0d ldr r2, [pc, #52] ; (8005170 ) movs r3, #0 - 80044a6: 2300 movs r3, #0 + 800513a: 2300 movs r3, #0 b LoopCopyDataInit - 80044a8: e002 b.n 80044b0 + 800513c: e002 b.n 8005144 -080044aa : +0800513e : CopyDataInit: ldr r4, [r2, r3] - 80044aa: 58d4 ldr r4, [r2, r3] + 800513e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 80044ac: 50c4 str r4, [r0, r3] + 8005140: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 80044ae: 3304 adds r3, #4 + 8005142: 3304 adds r3, #4 -080044b0 : +08005144 : LoopCopyDataInit: adds r4, r0, r3 - 80044b0: 18c4 adds r4, r0, r3 + 8005144: 18c4 adds r4, r0, r3 cmp r4, r1 - 80044b2: 428c cmp r4, r1 + 8005146: 428c cmp r4, r1 bcc CopyDataInit - 80044b4: d3f9 bcc.n 80044aa + 8005148: d3f9 bcc.n 800513e /* Zero fill the bss segment. */ ldr r2, =_sbss - 80044b6: 4a0a ldr r2, [pc, #40] ; (80044e0 ) + 800514a: 4a0a ldr r2, [pc, #40] ; (8005174 ) ldr r4, =_ebss - 80044b8: 4c0a ldr r4, [pc, #40] ; (80044e4 ) + 800514c: 4c0a ldr r4, [pc, #40] ; (8005178 ) movs r3, #0 - 80044ba: 2300 movs r3, #0 + 800514e: 2300 movs r3, #0 b LoopFillZerobss - 80044bc: e001 b.n 80044c2 + 8005150: e001 b.n 8005156 -080044be : +08005152 : FillZerobss: str r3, [r2] - 80044be: 6013 str r3, [r2, #0] + 8005152: 6013 str r3, [r2, #0] adds r2, r2, #4 - 80044c0: 3204 adds r2, #4 + 8005154: 3204 adds r2, #4 -080044c2 : +08005156 : LoopFillZerobss: cmp r2, r4 - 80044c2: 42a2 cmp r2, r4 + 8005156: 42a2 cmp r2, r4 bcc FillZerobss - 80044c4: d3fb bcc.n 80044be + 8005158: d3fb bcc.n 8005152 /* Call static constructors */ bl __libc_init_array - 80044c6: f00e fbb5 bl 8012c34 <__libc_init_array> + 800515a: f00f ffc3 bl 80150e4 <__libc_init_array> /* Call the application's entry point.*/ bl main - 80044ca: f7fc feb3 bl 8001234
+ 800515e: f7fc fb1b bl 8001798
-080044ce : +08005162 : LoopForever: b LoopForever - 80044ce: e7fe b.n 80044ce + 8005162: e7fe b.n 8005162 ldr sp, =_estack /* Set stack pointer */ - 80044d0: 20010000 .word 0x20010000 + 8005164: 20010000 .word 0x20010000 ldr r0, =_sdata - 80044d4: 20000000 .word 0x20000000 + 8005168: 20000000 .word 0x20000000 ldr r1, =_edata - 80044d8: 20000314 .word 0x20000314 + 800516c: 200002f4 .word 0x200002f4 ldr r2, =_sidata - 80044dc: 08018d98 .word 0x08018d98 + 8005170: 0801b270 .word 0x0801b270 ldr r2, =_sbss - 80044e0: 20000318 .word 0x20000318 + 8005174: 200002f8 .word 0x200002f8 ldr r4, =_ebss - 80044e4: 200015d8 .word 0x200015d8 + 8005178: 20002390 .word 0x20002390 -080044e8 : +0800517c : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 80044e8: e7fe b.n 80044e8 + 800517c: e7fe b.n 800517c -080044ea : +0800517e : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 80044ea: b580 push {r7, lr} - 80044ec: b082 sub sp, #8 - 80044ee: af00 add r7, sp, #0 + 800517e: b580 push {r7, lr} + 8005180: b082 sub sp, #8 + 8005182: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 80044f0: 2300 movs r3, #0 - 80044f2: 71fb strb r3, [r7, #7] + 8005184: 2300 movs r3, #0 + 8005186: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 80044f4: 2003 movs r0, #3 - 80044f6: f001 fc25 bl 8005d44 + 8005188: 2003 movs r0, #3 + 800518a: f001 fc01 bl 8006990 /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 80044fa: 200f movs r0, #15 - 80044fc: f000 f80e bl 800451c - 8004500: 4603 mov r3, r0 - 8004502: 2b00 cmp r3, #0 - 8004504: d002 beq.n 800450c + 800518e: 200f movs r0, #15 + 8005190: f000 f80e bl 80051b0 + 8005194: 4603 mov r3, r0 + 8005196: 2b00 cmp r3, #0 + 8005198: d002 beq.n 80051a0 { status = HAL_ERROR; - 8004506: 2301 movs r3, #1 - 8004508: 71fb strb r3, [r7, #7] - 800450a: e001 b.n 8004510 + 800519a: 2301 movs r3, #1 + 800519c: 71fb strb r3, [r7, #7] + 800519e: e001 b.n 80051a4 } else { /* Init the low level hardware */ HAL_MspInit(); - 800450c: f7ff fc5e bl 8003dcc + 80051a0: f7ff fc56 bl 8004a50 } /* Return function status */ return status; - 8004510: 79fb ldrb r3, [r7, #7] + 80051a4: 79fb ldrb r3, [r7, #7] } - 8004512: 4618 mov r0, r3 - 8004514: 3708 adds r7, #8 - 8004516: 46bd mov sp, r7 - 8004518: bd80 pop {r7, pc} + 80051a6: 4618 mov r0, r3 + 80051a8: 3708 adds r7, #8 + 80051aa: 46bd mov sp, r7 + 80051ac: bd80 pop {r7, pc} ... -0800451c : +080051b0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 800451c: b580 push {r7, lr} - 800451e: b084 sub sp, #16 - 8004520: af00 add r7, sp, #0 - 8004522: 6078 str r0, [r7, #4] + 80051b0: b580 push {r7, lr} + 80051b2: b084 sub sp, #16 + 80051b4: af00 add r7, sp, #0 + 80051b6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8004524: 2300 movs r3, #0 - 8004526: 73fb strb r3, [r7, #15] + 80051b8: 2300 movs r3, #0 + 80051ba: 73fb strb r3, [r7, #15] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) - 8004528: 4b17 ldr r3, [pc, #92] ; (8004588 ) - 800452a: 781b ldrb r3, [r3, #0] - 800452c: 2b00 cmp r3, #0 - 800452e: d023 beq.n 8004578 + 80051bc: 4b17 ldr r3, [pc, #92] ; (800521c ) + 80051be: 781b ldrb r3, [r3, #0] + 80051c0: 2b00 cmp r3, #0 + 80051c2: d023 beq.n 800520c { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U) - 8004530: 4b16 ldr r3, [pc, #88] ; (800458c ) - 8004532: 681a ldr r2, [r3, #0] - 8004534: 4b14 ldr r3, [pc, #80] ; (8004588 ) - 8004536: 781b ldrb r3, [r3, #0] - 8004538: 4619 mov r1, r3 - 800453a: f44f 737a mov.w r3, #1000 ; 0x3e8 - 800453e: fbb3 f3f1 udiv r3, r3, r1 - 8004542: fbb2 f3f3 udiv r3, r2, r3 - 8004546: 4618 mov r0, r3 - 8004548: f001 fc3f bl 8005dca - 800454c: 4603 mov r3, r0 - 800454e: 2b00 cmp r3, #0 - 8004550: d10f bne.n 8004572 + 80051c4: 4b16 ldr r3, [pc, #88] ; (8005220 ) + 80051c6: 681a ldr r2, [r3, #0] + 80051c8: 4b14 ldr r3, [pc, #80] ; (800521c ) + 80051ca: 781b ldrb r3, [r3, #0] + 80051cc: 4619 mov r1, r3 + 80051ce: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80051d2: fbb3 f3f1 udiv r3, r3, r1 + 80051d6: fbb2 f3f3 udiv r3, r2, r3 + 80051da: 4618 mov r0, r3 + 80051dc: f001 fc0d bl 80069fa + 80051e0: 4603 mov r3, r0 + 80051e2: 2b00 cmp r3, #0 + 80051e4: d10f bne.n 8005206 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8004552: 687b ldr r3, [r7, #4] - 8004554: 2b0f cmp r3, #15 - 8004556: d809 bhi.n 800456c + 80051e6: 687b ldr r3, [r7, #4] + 80051e8: 2b0f cmp r3, #15 + 80051ea: d809 bhi.n 8005200 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8004558: 2200 movs r2, #0 - 800455a: 6879 ldr r1, [r7, #4] - 800455c: f04f 30ff mov.w r0, #4294967295 - 8004560: f001 fbfb bl 8005d5a + 80051ec: 2200 movs r2, #0 + 80051ee: 6879 ldr r1, [r7, #4] + 80051f0: f04f 30ff mov.w r0, #4294967295 + 80051f4: f001 fbd7 bl 80069a6 uwTickPrio = TickPriority; - 8004564: 4a0a ldr r2, [pc, #40] ; (8004590 ) - 8004566: 687b ldr r3, [r7, #4] - 8004568: 6013 str r3, [r2, #0] - 800456a: e007 b.n 800457c + 80051f8: 4a0a ldr r2, [pc, #40] ; (8005224 ) + 80051fa: 687b ldr r3, [r7, #4] + 80051fc: 6013 str r3, [r2, #0] + 80051fe: e007 b.n 8005210 } else { status = HAL_ERROR; - 800456c: 2301 movs r3, #1 - 800456e: 73fb strb r3, [r7, #15] - 8004570: e004 b.n 800457c + 8005200: 2301 movs r3, #1 + 8005202: 73fb strb r3, [r7, #15] + 8005204: e004 b.n 8005210 } } else { status = HAL_ERROR; - 8004572: 2301 movs r3, #1 - 8004574: 73fb strb r3, [r7, #15] - 8004576: e001 b.n 800457c + 8005206: 2301 movs r3, #1 + 8005208: 73fb strb r3, [r7, #15] + 800520a: e001 b.n 8005210 } } else { status = HAL_ERROR; - 8004578: 2301 movs r3, #1 - 800457a: 73fb strb r3, [r7, #15] + 800520c: 2301 movs r3, #1 + 800520e: 73fb strb r3, [r7, #15] } /* Return function status */ return status; - 800457c: 7bfb ldrb r3, [r7, #15] -} - 800457e: 4618 mov r0, r3 - 8004580: 3710 adds r7, #16 - 8004582: 46bd mov sp, r7 - 8004584: bd80 pop {r7, pc} - 8004586: bf00 nop - 8004588: 20000028 .word 0x20000028 - 800458c: 20000020 .word 0x20000020 - 8004590: 20000024 .word 0x20000024 - -08004594 : + 8005210: 7bfb ldrb r3, [r7, #15] +} + 8005212: 4618 mov r0, r3 + 8005214: 3710 adds r7, #16 + 8005216: 46bd mov sp, r7 + 8005218: bd80 pop {r7, pc} + 800521a: bf00 nop + 800521c: 20000028 .word 0x20000028 + 8005220: 20000020 .word 0x20000020 + 8005224: 20000024 .word 0x20000024 + +08005228 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8004594: b480 push {r7} - 8004596: af00 add r7, sp, #0 + 8005228: b480 push {r7} + 800522a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; - 8004598: 4b06 ldr r3, [pc, #24] ; (80045b4 ) - 800459a: 781b ldrb r3, [r3, #0] - 800459c: 461a mov r2, r3 - 800459e: 4b06 ldr r3, [pc, #24] ; (80045b8 ) - 80045a0: 681b ldr r3, [r3, #0] - 80045a2: 4413 add r3, r2 - 80045a4: 4a04 ldr r2, [pc, #16] ; (80045b8 ) - 80045a6: 6013 str r3, [r2, #0] -} - 80045a8: bf00 nop - 80045aa: 46bd mov sp, r7 - 80045ac: f85d 7b04 ldr.w r7, [sp], #4 - 80045b0: 4770 bx lr - 80045b2: bf00 nop - 80045b4: 20000028 .word 0x20000028 - 80045b8: 20000c9c .word 0x20000c9c - -080045bc : + 800522c: 4b06 ldr r3, [pc, #24] ; (8005248 ) + 800522e: 781b ldrb r3, [r3, #0] + 8005230: 461a mov r2, r3 + 8005232: 4b06 ldr r3, [pc, #24] ; (800524c ) + 8005234: 681b ldr r3, [r3, #0] + 8005236: 4413 add r3, r2 + 8005238: 4a04 ldr r2, [pc, #16] ; (800524c ) + 800523a: 6013 str r3, [r2, #0] +} + 800523c: bf00 nop + 800523e: 46bd mov sp, r7 + 8005240: f85d 7b04 ldr.w r7, [sp], #4 + 8005244: 4770 bx lr + 8005246: bf00 nop + 8005248: 20000028 .word 0x20000028 + 800524c: 20001048 .word 0x20001048 + +08005250 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 80045bc: b480 push {r7} - 80045be: af00 add r7, sp, #0 + 8005250: b480 push {r7} + 8005252: af00 add r7, sp, #0 return uwTick; - 80045c0: 4b03 ldr r3, [pc, #12] ; (80045d0 ) - 80045c2: 681b ldr r3, [r3, #0] + 8005254: 4b03 ldr r3, [pc, #12] ; (8005264 ) + 8005256: 681b ldr r3, [r3, #0] } - 80045c4: 4618 mov r0, r3 - 80045c6: 46bd mov sp, r7 - 80045c8: f85d 7b04 ldr.w r7, [sp], #4 - 80045cc: 4770 bx lr - 80045ce: bf00 nop - 80045d0: 20000c9c .word 0x20000c9c + 8005258: 4618 mov r0, r3 + 800525a: 46bd mov sp, r7 + 800525c: f85d 7b04 ldr.w r7, [sp], #4 + 8005260: 4770 bx lr + 8005262: bf00 nop + 8005264: 20001048 .word 0x20001048 -080045d4 : +08005268 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 80045d4: b580 push {r7, lr} - 80045d6: b084 sub sp, #16 - 80045d8: af00 add r7, sp, #0 - 80045da: 6078 str r0, [r7, #4] + 8005268: b580 push {r7, lr} + 800526a: b084 sub sp, #16 + 800526c: af00 add r7, sp, #0 + 800526e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 80045dc: f7ff ffee bl 80045bc - 80045e0: 60b8 str r0, [r7, #8] + 8005270: f7ff ffee bl 8005250 + 8005274: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 80045e2: 687b ldr r3, [r7, #4] - 80045e4: 60fb str r3, [r7, #12] + 8005276: 687b ldr r3, [r7, #4] + 8005278: 60fb str r3, [r7, #12] /* Add a period to guaranty minimum wait */ if (wait < HAL_MAX_DELAY) - 80045e6: 68fb ldr r3, [r7, #12] - 80045e8: f1b3 3fff cmp.w r3, #4294967295 - 80045ec: d005 beq.n 80045fa + 800527a: 68fb ldr r3, [r7, #12] + 800527c: f1b3 3fff cmp.w r3, #4294967295 + 8005280: d005 beq.n 800528e { wait += (uint32_t)uwTickFreq; - 80045ee: 4b0a ldr r3, [pc, #40] ; (8004618 ) - 80045f0: 781b ldrb r3, [r3, #0] - 80045f2: 461a mov r2, r3 - 80045f4: 68fb ldr r3, [r7, #12] - 80045f6: 4413 add r3, r2 - 80045f8: 60fb str r3, [r7, #12] + 8005282: 4b0a ldr r3, [pc, #40] ; (80052ac ) + 8005284: 781b ldrb r3, [r3, #0] + 8005286: 461a mov r2, r3 + 8005288: 68fb ldr r3, [r7, #12] + 800528a: 4413 add r3, r2 + 800528c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) - 80045fa: bf00 nop - 80045fc: f7ff ffde bl 80045bc - 8004600: 4602 mov r2, r0 - 8004602: 68bb ldr r3, [r7, #8] - 8004604: 1ad3 subs r3, r2, r3 - 8004606: 68fa ldr r2, [r7, #12] - 8004608: 429a cmp r2, r3 - 800460a: d8f7 bhi.n 80045fc - { - } -} - 800460c: bf00 nop - 800460e: bf00 nop - 8004610: 3710 adds r7, #16 - 8004612: 46bd mov sp, r7 - 8004614: bd80 pop {r7, pc} - 8004616: bf00 nop - 8004618: 20000028 .word 0x20000028 - -0800461c : + 800528e: bf00 nop + 8005290: f7ff ffde bl 8005250 + 8005294: 4602 mov r2, r0 + 8005296: 68bb ldr r3, [r7, #8] + 8005298: 1ad3 subs r3, r2, r3 + 800529a: 68fa ldr r2, [r7, #12] + 800529c: 429a cmp r2, r3 + 800529e: d8f7 bhi.n 8005290 + { + } +} + 80052a0: bf00 nop + 80052a2: bf00 nop + 80052a4: 3710 adds r7, #16 + 80052a6: 46bd mov sp, r7 + 80052a8: bd80 pop {r7, pc} + 80052aa: bf00 nop + 80052ac: 20000028 .word 0x20000028 + +080052b0 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { - 800461c: b480 push {r7} - 800461e: b083 sub sp, #12 - 8004620: af00 add r7, sp, #0 - 8004622: 6078 str r0, [r7, #4] - 8004624: 6039 str r1, [r7, #0] + 80052b0: b480 push {r7} + 80052b2: b083 sub sp, #12 + 80052b4: af00 add r7, sp, #0 + 80052b6: 6078 str r0, [r7, #4] + 80052b8: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); - 8004626: 687b ldr r3, [r7, #4] - 8004628: 689b ldr r3, [r3, #8] - 800462a: f423 127c bic.w r2, r3, #4128768 ; 0x3f0000 - 800462e: 683b ldr r3, [r7, #0] - 8004630: 431a orrs r2, r3 - 8004632: 687b ldr r3, [r7, #4] - 8004634: 609a str r2, [r3, #8] -} - 8004636: bf00 nop - 8004638: 370c adds r7, #12 - 800463a: 46bd mov sp, r7 - 800463c: f85d 7b04 ldr.w r7, [sp], #4 - 8004640: 4770 bx lr - -08004642 : + 80052ba: 687b ldr r3, [r7, #4] + 80052bc: 689b ldr r3, [r3, #8] + 80052be: f423 127c bic.w r2, r3, #4128768 ; 0x3f0000 + 80052c2: 683b ldr r3, [r7, #0] + 80052c4: 431a orrs r2, r3 + 80052c6: 687b ldr r3, [r7, #4] + 80052c8: 609a str r2, [r3, #8] +} + 80052ca: bf00 nop + 80052cc: 370c adds r7, #12 + 80052ce: 46bd mov sp, r7 + 80052d0: f85d 7b04 ldr.w r7, [sp], #4 + 80052d4: 4770 bx lr + +080052d6 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { - 8004642: b480 push {r7} - 8004644: b083 sub sp, #12 - 8004646: af00 add r7, sp, #0 - 8004648: 6078 str r0, [r7, #4] - 800464a: 6039 str r1, [r7, #0] + 80052d6: b480 push {r7} + 80052d8: b083 sub sp, #12 + 80052da: af00 add r7, sp, #0 + 80052dc: 6078 str r0, [r7, #4] + 80052de: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); - 800464c: 687b ldr r3, [r7, #4] - 800464e: 689b ldr r3, [r3, #8] - 8004650: f023 72e0 bic.w r2, r3, #29360128 ; 0x1c00000 - 8004654: 683b ldr r3, [r7, #0] - 8004656: 431a orrs r2, r3 - 8004658: 687b ldr r3, [r7, #4] - 800465a: 609a str r2, [r3, #8] -} - 800465c: bf00 nop - 800465e: 370c adds r7, #12 - 8004660: 46bd mov sp, r7 - 8004662: f85d 7b04 ldr.w r7, [sp], #4 - 8004666: 4770 bx lr - -08004668 : + 80052e0: 687b ldr r3, [r7, #4] + 80052e2: 689b ldr r3, [r3, #8] + 80052e4: f023 72e0 bic.w r2, r3, #29360128 ; 0x1c00000 + 80052e8: 683b ldr r3, [r7, #0] + 80052ea: 431a orrs r2, r3 + 80052ec: 687b ldr r3, [r7, #4] + 80052ee: 609a str r2, [r3, #8] +} + 80052f0: bf00 nop + 80052f2: 370c adds r7, #12 + 80052f4: 46bd mov sp, r7 + 80052f6: f85d 7b04 ldr.w r7, [sp], #4 + 80052fa: 4770 bx lr + +080052fc : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { - 8004668: b480 push {r7} - 800466a: b083 sub sp, #12 - 800466c: af00 add r7, sp, #0 - 800466e: 6078 str r0, [r7, #4] + 80052fc: b480 push {r7} + 80052fe: b083 sub sp, #12 + 8005300: af00 add r7, sp, #0 + 8005302: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); - 8004670: 687b ldr r3, [r7, #4] - 8004672: 689b ldr r3, [r3, #8] - 8004674: f003 73e0 and.w r3, r3, #29360128 ; 0x1c00000 + 8005304: 687b ldr r3, [r7, #4] + 8005306: 689b ldr r3, [r3, #8] + 8005308: f003 73e0 and.w r3, r3, #29360128 ; 0x1c00000 } - 8004678: 4618 mov r0, r3 - 800467a: 370c adds r7, #12 - 800467c: 46bd mov sp, r7 - 800467e: f85d 7b04 ldr.w r7, [sp], #4 - 8004682: 4770 bx lr + 800530c: 4618 mov r0, r3 + 800530e: 370c adds r7, #12 + 8005310: 46bd mov sp, r7 + 8005312: f85d 7b04 ldr.w r7, [sp], #4 + 8005316: 4770 bx lr -08004684 : +08005318 : * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - 8004684: b480 push {r7} - 8004686: b087 sub sp, #28 - 8004688: af00 add r7, sp, #0 - 800468a: 60f8 str r0, [r7, #12] - 800468c: 60b9 str r1, [r7, #8] - 800468e: 607a str r2, [r7, #4] - 8004690: 603b str r3, [r7, #0] + 8005318: b480 push {r7} + 800531a: b087 sub sp, #28 + 800531c: af00 add r7, sp, #0 + 800531e: 60f8 str r0, [r7, #12] + 8005320: 60b9 str r1, [r7, #8] + 8005322: 607a str r2, [r7, #4] + 8005324: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8004692: 68fb ldr r3, [r7, #12] - 8004694: 3360 adds r3, #96 ; 0x60 - 8004696: 461a mov r2, r3 - 8004698: 68bb ldr r3, [r7, #8] - 800469a: 009b lsls r3, r3, #2 - 800469c: 4413 add r3, r2 - 800469e: 617b str r3, [r7, #20] + 8005326: 68fb ldr r3, [r7, #12] + 8005328: 3360 adds r3, #96 ; 0x60 + 800532a: 461a mov r2, r3 + 800532c: 68bb ldr r3, [r7, #8] + 800532e: 009b lsls r3, r3, #2 + 8005330: 4413 add r3, r2 + 8005332: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 80046a0: 697b ldr r3, [r7, #20] - 80046a2: 681a ldr r2, [r3, #0] - 80046a4: 4b08 ldr r3, [pc, #32] ; (80046c8 ) - 80046a6: 4013 ands r3, r2 - 80046a8: 687a ldr r2, [r7, #4] - 80046aa: f002 41f8 and.w r1, r2, #2080374784 ; 0x7c000000 - 80046ae: 683a ldr r2, [r7, #0] - 80046b0: 430a orrs r2, r1 - 80046b2: 4313 orrs r3, r2 - 80046b4: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 - 80046b8: 697b ldr r3, [r7, #20] - 80046ba: 601a str r2, [r3, #0] + 8005334: 697b ldr r3, [r7, #20] + 8005336: 681a ldr r2, [r3, #0] + 8005338: 4b08 ldr r3, [pc, #32] ; (800535c ) + 800533a: 4013 ands r3, r2 + 800533c: 687a ldr r2, [r7, #4] + 800533e: f002 41f8 and.w r1, r2, #2080374784 ; 0x7c000000 + 8005342: 683a ldr r2, [r7, #0] + 8005344: 430a orrs r2, r1 + 8005346: 4313 orrs r3, r2 + 8005348: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 800534c: 697b ldr r3, [r7, #20] + 800534e: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } - 80046bc: bf00 nop - 80046be: 371c adds r7, #28 - 80046c0: 46bd mov sp, r7 - 80046c2: f85d 7b04 ldr.w r7, [sp], #4 - 80046c6: 4770 bx lr - 80046c8: 03fff000 .word 0x03fff000 + 8005350: bf00 nop + 8005352: 371c adds r7, #28 + 8005354: 46bd mov sp, r7 + 8005356: f85d 7b04 ldr.w r7, [sp], #4 + 800535a: 4770 bx lr + 800535c: 03fff000 .word 0x03fff000 -080046cc : +08005360 : * (1, 2, 3, 4) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { - 80046cc: b480 push {r7} - 80046ce: b085 sub sp, #20 - 80046d0: af00 add r7, sp, #0 - 80046d2: 6078 str r0, [r7, #4] - 80046d4: 6039 str r1, [r7, #0] + 8005360: b480 push {r7} + 8005362: b085 sub sp, #20 + 8005364: af00 add r7, sp, #0 + 8005366: 6078 str r0, [r7, #4] + 8005368: 6039 str r1, [r7, #0] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 80046d6: 687b ldr r3, [r7, #4] - 80046d8: 3360 adds r3, #96 ; 0x60 - 80046da: 461a mov r2, r3 - 80046dc: 683b ldr r3, [r7, #0] - 80046de: 009b lsls r3, r3, #2 - 80046e0: 4413 add r3, r2 - 80046e2: 60fb str r3, [r7, #12] + 800536a: 687b ldr r3, [r7, #4] + 800536c: 3360 adds r3, #96 ; 0x60 + 800536e: 461a mov r2, r3 + 8005370: 683b ldr r3, [r7, #0] + 8005372: 009b lsls r3, r3, #2 + 8005374: 4413 add r3, r2 + 8005376: 60fb str r3, [r7, #12] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); - 80046e4: 68fb ldr r3, [r7, #12] - 80046e6: 681b ldr r3, [r3, #0] - 80046e8: f003 43f8 and.w r3, r3, #2080374784 ; 0x7c000000 + 8005378: 68fb ldr r3, [r7, #12] + 800537a: 681b ldr r3, [r3, #0] + 800537c: f003 43f8 and.w r3, r3, #2080374784 ; 0x7c000000 } - 80046ec: 4618 mov r0, r3 - 80046ee: 3714 adds r7, #20 - 80046f0: 46bd mov sp, r7 - 80046f2: f85d 7b04 ldr.w r7, [sp], #4 - 80046f6: 4770 bx lr + 8005380: 4618 mov r0, r3 + 8005382: 3714 adds r7, #20 + 8005384: 46bd mov sp, r7 + 8005386: f85d 7b04 ldr.w r7, [sp], #4 + 800538a: 4770 bx lr -080046f8 : +0800538c : * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - 80046f8: b480 push {r7} - 80046fa: b087 sub sp, #28 - 80046fc: af00 add r7, sp, #0 - 80046fe: 60f8 str r0, [r7, #12] - 8004700: 60b9 str r1, [r7, #8] - 8004702: 607a str r2, [r7, #4] + 800538c: b480 push {r7} + 800538e: b087 sub sp, #28 + 8005390: af00 add r7, sp, #0 + 8005392: 60f8 str r0, [r7, #12] + 8005394: 60b9 str r1, [r7, #8] + 8005396: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8004704: 68fb ldr r3, [r7, #12] - 8004706: 3360 adds r3, #96 ; 0x60 - 8004708: 461a mov r2, r3 - 800470a: 68bb ldr r3, [r7, #8] - 800470c: 009b lsls r3, r3, #2 - 800470e: 4413 add r3, r2 - 8004710: 617b str r3, [r7, #20] + 8005398: 68fb ldr r3, [r7, #12] + 800539a: 3360 adds r3, #96 ; 0x60 + 800539c: 461a mov r2, r3 + 800539e: 68bb ldr r3, [r7, #8] + 80053a0: 009b lsls r3, r3, #2 + 80053a2: 4413 add r3, r2 + 80053a4: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 8004712: 697b ldr r3, [r7, #20] - 8004714: 681b ldr r3, [r3, #0] - 8004716: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 - 800471a: 687b ldr r3, [r7, #4] - 800471c: 431a orrs r2, r3 - 800471e: 697b ldr r3, [r7, #20] - 8004720: 601a str r2, [r3, #0] + 80053a6: 697b ldr r3, [r7, #20] + 80053a8: 681b ldr r3, [r3, #0] + 80053aa: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 80053ae: 687b ldr r3, [r7, #4] + 80053b0: 431a orrs r2, r3 + 80053b2: 697b ldr r3, [r7, #20] + 80053b4: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN, OffsetState); } - 8004722: bf00 nop - 8004724: 371c adds r7, #28 - 8004726: 46bd mov sp, r7 - 8004728: f85d 7b04 ldr.w r7, [sp], #4 - 800472c: 4770 bx lr + 80053b6: bf00 nop + 80053b8: 371c adds r7, #28 + 80053ba: 46bd mov sp, r7 + 80053bc: f85d 7b04 ldr.w r7, [sp], #4 + 80053c0: 4770 bx lr -0800472e : +080053c2 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { - 800472e: b480 push {r7} - 8004730: b083 sub sp, #12 - 8004732: af00 add r7, sp, #0 - 8004734: 6078 str r0, [r7, #4] + 80053c2: b480 push {r7} + 80053c4: b083 sub sp, #12 + 80053c6: af00 add r7, sp, #0 + 80053c8: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); - 8004736: 687b ldr r3, [r7, #4] - 8004738: 68db ldr r3, [r3, #12] - 800473a: f403 6340 and.w r3, r3, #3072 ; 0xc00 - 800473e: 2b00 cmp r3, #0 - 8004740: d101 bne.n 8004746 - 8004742: 2301 movs r3, #1 - 8004744: e000 b.n 8004748 - 8004746: 2300 movs r3, #0 -} - 8004748: 4618 mov r0, r3 - 800474a: 370c adds r7, #12 - 800474c: 46bd mov sp, r7 - 800474e: f85d 7b04 ldr.w r7, [sp], #4 - 8004752: 4770 bx lr - -08004754 : + 80053ca: 687b ldr r3, [r7, #4] + 80053cc: 68db ldr r3, [r3, #12] + 80053ce: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 80053d2: 2b00 cmp r3, #0 + 80053d4: d101 bne.n 80053da + 80053d6: 2301 movs r3, #1 + 80053d8: e000 b.n 80053dc + 80053da: 2300 movs r3, #0 +} + 80053dc: 4618 mov r0, r3 + 80053de: 370c adds r7, #12 + 80053e0: 46bd mov sp, r7 + 80053e2: f85d 7b04 ldr.w r7, [sp], #4 + 80053e6: 4770 bx lr + +080053e8 : * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { - 8004754: b480 push {r7} - 8004756: b087 sub sp, #28 - 8004758: af00 add r7, sp, #0 - 800475a: 60f8 str r0, [r7, #12] - 800475c: 60b9 str r1, [r7, #8] - 800475e: 607a str r2, [r7, #4] + 80053e8: b480 push {r7} + 80053ea: b087 sub sp, #28 + 80053ec: af00 add r7, sp, #0 + 80053ee: 60f8 str r0, [r7, #12] + 80053f0: 60b9 str r1, [r7, #8] + 80053f2: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, - 8004760: 68fb ldr r3, [r7, #12] - 8004762: 3330 adds r3, #48 ; 0x30 - 8004764: 461a mov r2, r3 - 8004766: 68bb ldr r3, [r7, #8] - 8004768: 0a1b lsrs r3, r3, #8 - 800476a: 009b lsls r3, r3, #2 - 800476c: f003 030c and.w r3, r3, #12 - 8004770: 4413 add r3, r2 - 8004772: 617b str r3, [r7, #20] + 80053f4: 68fb ldr r3, [r7, #12] + 80053f6: 3330 adds r3, #48 ; 0x30 + 80053f8: 461a mov r2, r3 + 80053fa: 68bb ldr r3, [r7, #8] + 80053fc: 0a1b lsrs r3, r3, #8 + 80053fe: 009b lsls r3, r3, #2 + 8005400: f003 030c and.w r3, r3, #12 + 8005404: 4413 add r3, r2 + 8005406: 617b str r3, [r7, #20] ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, - 8004774: 697b ldr r3, [r7, #20] - 8004776: 681a ldr r2, [r3, #0] - 8004778: 68bb ldr r3, [r7, #8] - 800477a: f003 031f and.w r3, r3, #31 - 800477e: 211f movs r1, #31 - 8004780: fa01 f303 lsl.w r3, r1, r3 - 8004784: 43db mvns r3, r3 - 8004786: 401a ands r2, r3 - 8004788: 687b ldr r3, [r7, #4] - 800478a: 0e9b lsrs r3, r3, #26 - 800478c: f003 011f and.w r1, r3, #31 - 8004790: 68bb ldr r3, [r7, #8] - 8004792: f003 031f and.w r3, r3, #31 - 8004796: fa01 f303 lsl.w r3, r1, r3 - 800479a: 431a orrs r2, r3 - 800479c: 697b ldr r3, [r7, #20] - 800479e: 601a str r2, [r3, #0] + 8005408: 697b ldr r3, [r7, #20] + 800540a: 681a ldr r2, [r3, #0] + 800540c: 68bb ldr r3, [r7, #8] + 800540e: f003 031f and.w r3, r3, #31 + 8005412: 211f movs r1, #31 + 8005414: fa01 f303 lsl.w r3, r1, r3 + 8005418: 43db mvns r3, r3 + 800541a: 401a ands r2, r3 + 800541c: 687b ldr r3, [r7, #4] + 800541e: 0e9b lsrs r3, r3, #26 + 8005420: f003 011f and.w r1, r3, #31 + 8005424: 68bb ldr r3, [r7, #8] + 8005426: f003 031f and.w r3, r3, #31 + 800542a: fa01 f303 lsl.w r3, r1, r3 + 800542e: 431a orrs r2, r3 + 8005430: 697b ldr r3, [r7, #20] + 8005432: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } - 80047a0: bf00 nop - 80047a2: 371c adds r7, #28 - 80047a4: 46bd mov sp, r7 - 80047a6: f85d 7b04 ldr.w r7, [sp], #4 - 80047aa: 4770 bx lr + 8005434: bf00 nop + 8005436: 371c adds r7, #28 + 8005438: 46bd mov sp, r7 + 800543a: f85d 7b04 ldr.w r7, [sp], #4 + 800543e: 4770 bx lr -080047ac : +08005440 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { - 80047ac: b480 push {r7} - 80047ae: b083 sub sp, #12 - 80047b0: af00 add r7, sp, #0 - 80047b2: 6078 str r0, [r7, #4] + 8005440: b480 push {r7} + 8005442: b083 sub sp, #12 + 8005444: af00 add r7, sp, #0 + 8005446: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); - 80047b4: 687b ldr r3, [r7, #4] - 80047b6: 6cdb ldr r3, [r3, #76] ; 0x4c - 80047b8: f003 03c0 and.w r3, r3, #192 ; 0xc0 - 80047bc: 2b00 cmp r3, #0 - 80047be: d101 bne.n 80047c4 - 80047c0: 2301 movs r3, #1 - 80047c2: e000 b.n 80047c6 - 80047c4: 2300 movs r3, #0 -} - 80047c6: 4618 mov r0, r3 - 80047c8: 370c adds r7, #12 - 80047ca: 46bd mov sp, r7 - 80047cc: f85d 7b04 ldr.w r7, [sp], #4 - 80047d0: 4770 bx lr - -080047d2 : + 8005448: 687b ldr r3, [r7, #4] + 800544a: 6cdb ldr r3, [r3, #76] ; 0x4c + 800544c: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8005450: 2b00 cmp r3, #0 + 8005452: d101 bne.n 8005458 + 8005454: 2301 movs r3, #1 + 8005456: e000 b.n 800545a + 8005458: 2300 movs r3, #0 +} + 800545a: 4618 mov r0, r3 + 800545c: 370c adds r7, #12 + 800545e: 46bd mov sp, r7 + 8005460: f85d 7b04 ldr.w r7, [sp], #4 + 8005464: 4770 bx lr + +08005466 : * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { - 80047d2: b480 push {r7} - 80047d4: b087 sub sp, #28 - 80047d6: af00 add r7, sp, #0 - 80047d8: 60f8 str r0, [r7, #12] - 80047da: 60b9 str r1, [r7, #8] - 80047dc: 607a str r2, [r7, #4] + 8005466: b480 push {r7} + 8005468: b087 sub sp, #28 + 800546a: af00 add r7, sp, #0 + 800546c: 60f8 str r0, [r7, #12] + 800546e: 60b9 str r1, [r7, #8] + 8005470: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, - 80047de: 68fb ldr r3, [r7, #12] - 80047e0: 3314 adds r3, #20 - 80047e2: 461a mov r2, r3 - 80047e4: 68bb ldr r3, [r7, #8] - 80047e6: 0e5b lsrs r3, r3, #25 - 80047e8: 009b lsls r3, r3, #2 - 80047ea: f003 0304 and.w r3, r3, #4 - 80047ee: 4413 add r3, r2 - 80047f0: 617b str r3, [r7, #20] + 8005472: 68fb ldr r3, [r7, #12] + 8005474: 3314 adds r3, #20 + 8005476: 461a mov r2, r3 + 8005478: 68bb ldr r3, [r7, #8] + 800547a: 0e5b lsrs r3, r3, #25 + 800547c: 009b lsls r3, r3, #2 + 800547e: f003 0304 and.w r3, r3, #4 + 8005482: 4413 add r3, r2 + 8005484: 617b str r3, [r7, #20] ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, - 80047f2: 697b ldr r3, [r7, #20] - 80047f4: 681a ldr r2, [r3, #0] - 80047f6: 68bb ldr r3, [r7, #8] - 80047f8: 0d1b lsrs r3, r3, #20 - 80047fa: f003 031f and.w r3, r3, #31 - 80047fe: 2107 movs r1, #7 - 8004800: fa01 f303 lsl.w r3, r1, r3 - 8004804: 43db mvns r3, r3 - 8004806: 401a ands r2, r3 - 8004808: 68bb ldr r3, [r7, #8] - 800480a: 0d1b lsrs r3, r3, #20 - 800480c: f003 031f and.w r3, r3, #31 - 8004810: 6879 ldr r1, [r7, #4] - 8004812: fa01 f303 lsl.w r3, r1, r3 - 8004816: 431a orrs r2, r3 - 8004818: 697b ldr r3, [r7, #20] - 800481a: 601a str r2, [r3, #0] + 8005486: 697b ldr r3, [r7, #20] + 8005488: 681a ldr r2, [r3, #0] + 800548a: 68bb ldr r3, [r7, #8] + 800548c: 0d1b lsrs r3, r3, #20 + 800548e: f003 031f and.w r3, r3, #31 + 8005492: 2107 movs r1, #7 + 8005494: fa01 f303 lsl.w r3, r1, r3 + 8005498: 43db mvns r3, r3 + 800549a: 401a ands r2, r3 + 800549c: 68bb ldr r3, [r7, #8] + 800549e: 0d1b lsrs r3, r3, #20 + 80054a0: f003 031f and.w r3, r3, #31 + 80054a4: 6879 ldr r1, [r7, #4] + 80054a6: fa01 f303 lsl.w r3, r1, r3 + 80054aa: 431a orrs r2, r3 + 80054ac: 697b ldr r3, [r7, #20] + 80054ae: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } - 800481c: bf00 nop - 800481e: 371c adds r7, #28 - 8004820: 46bd mov sp, r7 - 8004822: f85d 7b04 ldr.w r7, [sp], #4 - 8004826: 4770 bx lr + 80054b0: bf00 nop + 80054b2: 371c adds r7, #28 + 80054b4: 46bd mov sp, r7 + 80054b6: f85d 7b04 ldr.w r7, [sp], #4 + 80054ba: 4770 bx lr -08004828 : +080054bc : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { - 8004828: b480 push {r7} - 800482a: b085 sub sp, #20 - 800482c: af00 add r7, sp, #0 - 800482e: 60f8 str r0, [r7, #12] - 8004830: 60b9 str r1, [r7, #8] - 8004832: 607a str r2, [r7, #4] + 80054bc: b480 push {r7} + 80054be: b085 sub sp, #20 + 80054c0: af00 add r7, sp, #0 + 80054c2: 60f8 str r0, [r7, #12] + 80054c4: 60b9 str r1, [r7, #8] + 80054c6: 607a str r2, [r7, #4] /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, - 8004834: 68fb ldr r3, [r7, #12] - 8004836: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0 - 800483a: 68bb ldr r3, [r7, #8] - 800483c: f3c3 0312 ubfx r3, r3, #0, #19 - 8004840: 43db mvns r3, r3 - 8004842: 401a ands r2, r3 - 8004844: 687b ldr r3, [r7, #4] - 8004846: f003 0318 and.w r3, r3, #24 - 800484a: 4908 ldr r1, [pc, #32] ; (800486c ) - 800484c: 40d9 lsrs r1, r3 - 800484e: 68bb ldr r3, [r7, #8] - 8004850: 400b ands r3, r1 - 8004852: f3c3 0312 ubfx r3, r3, #0, #19 - 8004856: 431a orrs r2, r3 - 8004858: 68fb ldr r3, [r7, #12] - 800485a: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0 + 80054c8: 68fb ldr r3, [r7, #12] + 80054ca: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0 + 80054ce: 68bb ldr r3, [r7, #8] + 80054d0: f3c3 0312 ubfx r3, r3, #0, #19 + 80054d4: 43db mvns r3, r3 + 80054d6: 401a ands r2, r3 + 80054d8: 687b ldr r3, [r7, #4] + 80054da: f003 0318 and.w r3, r3, #24 + 80054de: 4908 ldr r1, [pc, #32] ; (8005500 ) + 80054e0: 40d9 lsrs r1, r3 + 80054e2: 68bb ldr r3, [r7, #8] + 80054e4: 400b ands r3, r1 + 80054e6: f3c3 0312 ubfx r3, r3, #0, #19 + 80054ea: 431a orrs r2, r3 + 80054ec: 68fb ldr r3, [r7, #12] + 80054ee: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } - 800485e: bf00 nop - 8004860: 3714 adds r7, #20 - 8004862: 46bd mov sp, r7 - 8004864: f85d 7b04 ldr.w r7, [sp], #4 - 8004868: 4770 bx lr - 800486a: bf00 nop - 800486c: 0007ffff .word 0x0007ffff + 80054f2: bf00 nop + 80054f4: 3714 adds r7, #20 + 80054f6: 46bd mov sp, r7 + 80054f8: f85d 7b04 ldr.w r7, [sp], #4 + 80054fc: 4770 bx lr + 80054fe: bf00 nop + 8005500: 0007ffff .word 0x0007ffff -08004870 : +08005504 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { - 8004870: b480 push {r7} - 8004872: b083 sub sp, #12 - 8004874: af00 add r7, sp, #0 - 8004876: 6078 str r0, [r7, #4] + 8005504: b480 push {r7} + 8005506: b083 sub sp, #12 + 8005508: af00 add r7, sp, #0 + 800550a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); - 8004878: 687b ldr r3, [r7, #4] - 800487a: 689b ldr r3, [r3, #8] - 800487c: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000 - 8004880: f023 033f bic.w r3, r3, #63 ; 0x3f - 8004884: 687a ldr r2, [r7, #4] - 8004886: 6093 str r3, [r2, #8] -} - 8004888: bf00 nop - 800488a: 370c adds r7, #12 - 800488c: 46bd mov sp, r7 - 800488e: f85d 7b04 ldr.w r7, [sp], #4 - 8004892: 4770 bx lr - -08004894 : + 800550c: 687b ldr r3, [r7, #4] + 800550e: 689b ldr r3, [r3, #8] + 8005510: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000 + 8005514: f023 033f bic.w r3, r3, #63 ; 0x3f + 8005518: 687a ldr r2, [r7, #4] + 800551a: 6093 str r3, [r2, #8] +} + 800551c: bf00 nop + 800551e: 370c adds r7, #12 + 8005520: 46bd mov sp, r7 + 8005522: f85d 7b04 ldr.w r7, [sp], #4 + 8005526: 4770 bx lr + +08005528 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { - 8004894: b480 push {r7} - 8004896: b083 sub sp, #12 - 8004898: af00 add r7, sp, #0 - 800489a: 6078 str r0, [r7, #4] + 8005528: b480 push {r7} + 800552a: b083 sub sp, #12 + 800552c: af00 add r7, sp, #0 + 800552e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); - 800489c: 687b ldr r3, [r7, #4] - 800489e: 689b ldr r3, [r3, #8] - 80048a0: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 - 80048a4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 80048a8: d101 bne.n 80048ae - 80048aa: 2301 movs r3, #1 - 80048ac: e000 b.n 80048b0 - 80048ae: 2300 movs r3, #0 -} - 80048b0: 4618 mov r0, r3 - 80048b2: 370c adds r7, #12 - 80048b4: 46bd mov sp, r7 - 80048b6: f85d 7b04 ldr.w r7, [sp], #4 - 80048ba: 4770 bx lr - -080048bc : + 8005530: 687b ldr r3, [r7, #4] + 8005532: 689b ldr r3, [r3, #8] + 8005534: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8005538: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 800553c: d101 bne.n 8005542 + 800553e: 2301 movs r3, #1 + 8005540: e000 b.n 8005544 + 8005542: 2300 movs r3, #0 +} + 8005544: 4618 mov r0, r3 + 8005546: 370c adds r7, #12 + 8005548: 46bd mov sp, r7 + 800554a: f85d 7b04 ldr.w r7, [sp], #4 + 800554e: 4770 bx lr + +08005550 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { - 80048bc: b480 push {r7} - 80048be: b083 sub sp, #12 - 80048c0: af00 add r7, sp, #0 - 80048c2: 6078 str r0, [r7, #4] + 8005550: b480 push {r7} + 8005552: b083 sub sp, #12 + 8005554: af00 add r7, sp, #0 + 8005556: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 80048c4: 687b ldr r3, [r7, #4] - 80048c6: 689b ldr r3, [r3, #8] - 80048c8: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000 - 80048cc: f023 033f bic.w r3, r3, #63 ; 0x3f - 80048d0: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 - 80048d4: 687b ldr r3, [r7, #4] - 80048d6: 609a str r2, [r3, #8] + 8005558: 687b ldr r3, [r7, #4] + 800555a: 689b ldr r3, [r3, #8] + 800555c: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000 + 8005560: f023 033f bic.w r3, r3, #63 ; 0x3f + 8005564: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 + 8005568: 687b ldr r3, [r7, #4] + 800556a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } - 80048d8: bf00 nop - 80048da: 370c adds r7, #12 - 80048dc: 46bd mov sp, r7 - 80048de: f85d 7b04 ldr.w r7, [sp], #4 - 80048e2: 4770 bx lr + 800556c: bf00 nop + 800556e: 370c adds r7, #12 + 8005570: 46bd mov sp, r7 + 8005572: f85d 7b04 ldr.w r7, [sp], #4 + 8005576: 4770 bx lr -080048e4 : +08005578 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { - 80048e4: b480 push {r7} - 80048e6: b083 sub sp, #12 - 80048e8: af00 add r7, sp, #0 - 80048ea: 6078 str r0, [r7, #4] + 8005578: b480 push {r7} + 800557a: b083 sub sp, #12 + 800557c: af00 add r7, sp, #0 + 800557e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); - 80048ec: 687b ldr r3, [r7, #4] - 80048ee: 689b ldr r3, [r3, #8] - 80048f0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80048f4: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 - 80048f8: d101 bne.n 80048fe - 80048fa: 2301 movs r3, #1 - 80048fc: e000 b.n 8004900 - 80048fe: 2300 movs r3, #0 -} - 8004900: 4618 mov r0, r3 - 8004902: 370c adds r7, #12 - 8004904: 46bd mov sp, r7 - 8004906: f85d 7b04 ldr.w r7, [sp], #4 - 800490a: 4770 bx lr - -0800490c : + 8005580: 687b ldr r3, [r7, #4] + 8005582: 689b ldr r3, [r3, #8] + 8005584: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005588: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 800558c: d101 bne.n 8005592 + 800558e: 2301 movs r3, #1 + 8005590: e000 b.n 8005594 + 8005592: 2300 movs r3, #0 +} + 8005594: 4618 mov r0, r3 + 8005596: 370c adds r7, #12 + 8005598: 46bd mov sp, r7 + 800559a: f85d 7b04 ldr.w r7, [sp], #4 + 800559e: 4770 bx lr + +080055a0 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { - 800490c: b480 push {r7} - 800490e: b083 sub sp, #12 - 8004910: af00 add r7, sp, #0 - 8004912: 6078 str r0, [r7, #4] + 80055a0: b480 push {r7} + 80055a2: b083 sub sp, #12 + 80055a4: af00 add r7, sp, #0 + 80055a6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8004914: 687b ldr r3, [r7, #4] - 8004916: 689b ldr r3, [r3, #8] - 8004918: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 - 800491c: f023 033f bic.w r3, r3, #63 ; 0x3f - 8004920: f043 0201 orr.w r2, r3, #1 - 8004924: 687b ldr r3, [r7, #4] - 8004926: 609a str r2, [r3, #8] + 80055a8: 687b ldr r3, [r7, #4] + 80055aa: 689b ldr r3, [r3, #8] + 80055ac: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 80055b0: f023 033f bic.w r3, r3, #63 ; 0x3f + 80055b4: f043 0201 orr.w r2, r3, #1 + 80055b8: 687b ldr r3, [r7, #4] + 80055ba: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } - 8004928: bf00 nop - 800492a: 370c adds r7, #12 - 800492c: 46bd mov sp, r7 - 800492e: f85d 7b04 ldr.w r7, [sp], #4 - 8004932: 4770 bx lr + 80055bc: bf00 nop + 80055be: 370c adds r7, #12 + 80055c0: 46bd mov sp, r7 + 80055c2: f85d 7b04 ldr.w r7, [sp], #4 + 80055c6: 4770 bx lr -08004934 : +080055c8 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { - 8004934: b480 push {r7} - 8004936: b083 sub sp, #12 - 8004938: af00 add r7, sp, #0 - 800493a: 6078 str r0, [r7, #4] + 80055c8: b480 push {r7} + 80055ca: b083 sub sp, #12 + 80055cc: af00 add r7, sp, #0 + 80055ce: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); - 800493c: 687b ldr r3, [r7, #4] - 800493e: 689b ldr r3, [r3, #8] - 8004940: f003 0301 and.w r3, r3, #1 - 8004944: 2b01 cmp r3, #1 - 8004946: d101 bne.n 800494c - 8004948: 2301 movs r3, #1 - 800494a: e000 b.n 800494e - 800494c: 2300 movs r3, #0 -} - 800494e: 4618 mov r0, r3 - 8004950: 370c adds r7, #12 - 8004952: 46bd mov sp, r7 - 8004954: f85d 7b04 ldr.w r7, [sp], #4 - 8004958: 4770 bx lr - -0800495a : + 80055d0: 687b ldr r3, [r7, #4] + 80055d2: 689b ldr r3, [r3, #8] + 80055d4: f003 0301 and.w r3, r3, #1 + 80055d8: 2b01 cmp r3, #1 + 80055da: d101 bne.n 80055e0 + 80055dc: 2301 movs r3, #1 + 80055de: e000 b.n 80055e2 + 80055e0: 2300 movs r3, #0 +} + 80055e2: 4618 mov r0, r3 + 80055e4: 370c adds r7, #12 + 80055e6: 46bd mov sp, r7 + 80055e8: f85d 7b04 ldr.w r7, [sp], #4 + 80055ec: 4770 bx lr + +080055ee : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { - 800495a: b480 push {r7} - 800495c: b083 sub sp, #12 - 800495e: af00 add r7, sp, #0 - 8004960: 6078 str r0, [r7, #4] + 80055ee: b480 push {r7} + 80055f0: b083 sub sp, #12 + 80055f2: af00 add r7, sp, #0 + 80055f4: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8004962: 687b ldr r3, [r7, #4] - 8004964: 689b ldr r3, [r3, #8] - 8004966: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 - 800496a: f023 033f bic.w r3, r3, #63 ; 0x3f - 800496e: f043 0204 orr.w r2, r3, #4 - 8004972: 687b ldr r3, [r7, #4] - 8004974: 609a str r2, [r3, #8] + 80055f6: 687b ldr r3, [r7, #4] + 80055f8: 689b ldr r3, [r3, #8] + 80055fa: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 80055fe: f023 033f bic.w r3, r3, #63 ; 0x3f + 8005602: f043 0204 orr.w r2, r3, #4 + 8005606: 687b ldr r3, [r7, #4] + 8005608: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } - 8004976: bf00 nop - 8004978: 370c adds r7, #12 - 800497a: 46bd mov sp, r7 - 800497c: f85d 7b04 ldr.w r7, [sp], #4 - 8004980: 4770 bx lr + 800560a: bf00 nop + 800560c: 370c adds r7, #12 + 800560e: 46bd mov sp, r7 + 8005610: f85d 7b04 ldr.w r7, [sp], #4 + 8005614: 4770 bx lr -08004982 : +08005616 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { - 8004982: b480 push {r7} - 8004984: b083 sub sp, #12 - 8004986: af00 add r7, sp, #0 - 8004988: 6078 str r0, [r7, #4] + 8005616: b480 push {r7} + 8005618: b083 sub sp, #12 + 800561a: af00 add r7, sp, #0 + 800561c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); - 800498a: 687b ldr r3, [r7, #4] - 800498c: 689b ldr r3, [r3, #8] - 800498e: f003 0304 and.w r3, r3, #4 - 8004992: 2b04 cmp r3, #4 - 8004994: d101 bne.n 800499a - 8004996: 2301 movs r3, #1 - 8004998: e000 b.n 800499c - 800499a: 2300 movs r3, #0 -} - 800499c: 4618 mov r0, r3 - 800499e: 370c adds r7, #12 - 80049a0: 46bd mov sp, r7 - 80049a2: f85d 7b04 ldr.w r7, [sp], #4 - 80049a6: 4770 bx lr - -080049a8 : + 800561e: 687b ldr r3, [r7, #4] + 8005620: 689b ldr r3, [r3, #8] + 8005622: f003 0304 and.w r3, r3, #4 + 8005626: 2b04 cmp r3, #4 + 8005628: d101 bne.n 800562e + 800562a: 2301 movs r3, #1 + 800562c: e000 b.n 8005630 + 800562e: 2300 movs r3, #0 +} + 8005630: 4618 mov r0, r3 + 8005632: 370c adds r7, #12 + 8005634: 46bd mov sp, r7 + 8005636: f85d 7b04 ldr.w r7, [sp], #4 + 800563a: 4770 bx lr + +0800563c : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { - 80049a8: b480 push {r7} - 80049aa: b083 sub sp, #12 - 80049ac: af00 add r7, sp, #0 - 80049ae: 6078 str r0, [r7, #4] + 800563c: b480 push {r7} + 800563e: b083 sub sp, #12 + 8005640: af00 add r7, sp, #0 + 8005642: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); - 80049b0: 687b ldr r3, [r7, #4] - 80049b2: 689b ldr r3, [r3, #8] - 80049b4: f003 0308 and.w r3, r3, #8 - 80049b8: 2b08 cmp r3, #8 - 80049ba: d101 bne.n 80049c0 - 80049bc: 2301 movs r3, #1 - 80049be: e000 b.n 80049c2 - 80049c0: 2300 movs r3, #0 -} - 80049c2: 4618 mov r0, r3 - 80049c4: 370c adds r7, #12 - 80049c6: 46bd mov sp, r7 - 80049c8: f85d 7b04 ldr.w r7, [sp], #4 - 80049cc: 4770 bx lr + 8005644: 687b ldr r3, [r7, #4] + 8005646: 689b ldr r3, [r3, #8] + 8005648: f003 0308 and.w r3, r3, #8 + 800564c: 2b08 cmp r3, #8 + 800564e: d101 bne.n 8005654 + 8005650: 2301 movs r3, #1 + 8005652: e000 b.n 8005656 + 8005654: 2300 movs r3, #0 +} + 8005656: 4618 mov r0, r3 + 8005658: 370c adds r7, #12 + 800565a: 46bd mov sp, r7 + 800565c: f85d 7b04 ldr.w r7, [sp], #4 + 8005660: 4770 bx lr ... -080049d0 : +08005664 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { - 80049d0: b580 push {r7, lr} - 80049d2: b088 sub sp, #32 - 80049d4: af00 add r7, sp, #0 - 80049d6: 6078 str r0, [r7, #4] + 8005664: b580 push {r7, lr} + 8005666: b088 sub sp, #32 + 8005668: af00 add r7, sp, #0 + 800566a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 80049d8: 2300 movs r3, #0 - 80049da: 77fb strb r3, [r7, #31] + 800566c: 2300 movs r3, #0 + 800566e: 77fb strb r3, [r7, #31] uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; - 80049dc: 2300 movs r3, #0 - 80049de: 60fb str r3, [r7, #12] + 8005670: 2300 movs r3, #0 + 8005672: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) - 80049e0: 687b ldr r3, [r7, #4] - 80049e2: 2b00 cmp r3, #0 - 80049e4: d101 bne.n 80049ea + 8005674: 687b ldr r3, [r7, #4] + 8005676: 2b00 cmp r3, #0 + 8005678: d101 bne.n 800567e { return HAL_ERROR; - 80049e6: 2301 movs r3, #1 - 80049e8: e126 b.n 8004c38 + 800567a: 2301 movs r3, #1 + 800567c: e126 b.n 80058cc assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 80049ea: 687b ldr r3, [r7, #4] - 80049ec: 691b ldr r3, [r3, #16] - 80049ee: 2b00 cmp r3, #0 + 800567e: 687b ldr r3, [r7, #4] + 8005680: 691b ldr r3, [r3, #16] + 8005682: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) - 80049f0: 687b ldr r3, [r7, #4] - 80049f2: 6d5b ldr r3, [r3, #84] ; 0x54 - 80049f4: 2b00 cmp r3, #0 - 80049f6: d109 bne.n 8004a0c + 8005684: 687b ldr r3, [r7, #4] + 8005686: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005688: 2b00 cmp r3, #0 + 800568a: d109 bne.n 80056a0 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - 80049f8: 6878 ldr r0, [r7, #4] - 80049fa: f7ff fa0b bl 8003e14 + 800568c: 6878 ldr r0, [r7, #4] + 800568e: f7fb fd35 bl 80010fc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 80049fe: 687b ldr r3, [r7, #4] - 8004a00: 2200 movs r2, #0 - 8004a02: 659a str r2, [r3, #88] ; 0x58 + 8005692: 687b ldr r3, [r7, #4] + 8005694: 2200 movs r2, #0 + 8005696: 659a str r2, [r3, #88] ; 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; - 8004a04: 687b ldr r3, [r7, #4] - 8004a06: 2200 movs r2, #0 - 8004a08: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 8005698: 687b ldr r3, [r7, #4] + 800569a: 2200 movs r2, #0 + 800569c: f883 2050 strb.w r2, [r3, #80] ; 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) - 8004a0c: 687b ldr r3, [r7, #4] - 8004a0e: 681b ldr r3, [r3, #0] - 8004a10: 4618 mov r0, r3 - 8004a12: f7ff ff3f bl 8004894 - 8004a16: 4603 mov r3, r0 - 8004a18: 2b00 cmp r3, #0 - 8004a1a: d004 beq.n 8004a26 + 80056a0: 687b ldr r3, [r7, #4] + 80056a2: 681b ldr r3, [r3, #0] + 80056a4: 4618 mov r0, r3 + 80056a6: f7ff ff3f bl 8005528 + 80056aa: 4603 mov r3, r0 + 80056ac: 2b00 cmp r3, #0 + 80056ae: d004 beq.n 80056ba { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); - 8004a1c: 687b ldr r3, [r7, #4] - 8004a1e: 681b ldr r3, [r3, #0] - 8004a20: 4618 mov r0, r3 - 8004a22: f7ff ff25 bl 8004870 + 80056b0: 687b ldr r3, [r7, #4] + 80056b2: 681b ldr r3, [r3, #0] + 80056b4: 4618 mov r0, r3 + 80056b6: f7ff ff25 bl 8005504 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 8004a26: 687b ldr r3, [r7, #4] - 8004a28: 681b ldr r3, [r3, #0] - 8004a2a: 4618 mov r0, r3 - 8004a2c: f7ff ff5a bl 80048e4 - 8004a30: 4603 mov r3, r0 - 8004a32: 2b00 cmp r3, #0 - 8004a34: d115 bne.n 8004a62 + 80056ba: 687b ldr r3, [r7, #4] + 80056bc: 681b ldr r3, [r3, #0] + 80056be: 4618 mov r0, r3 + 80056c0: f7ff ff5a bl 8005578 + 80056c4: 4603 mov r3, r0 + 80056c6: 2b00 cmp r3, #0 + 80056c8: d115 bne.n 80056f6 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - 8004a36: 687b ldr r3, [r7, #4] - 8004a38: 681b ldr r3, [r3, #0] - 8004a3a: 4618 mov r0, r3 - 8004a3c: f7ff ff3e bl 80048bc + 80056ca: 687b ldr r3, [r7, #4] + 80056cc: 681b ldr r3, [r3, #0] + 80056ce: 4618 mov r0, r3 + 80056d0: f7ff ff3e bl 8005550 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8004a40: 4b7f ldr r3, [pc, #508] ; (8004c40 ) - 8004a42: 681b ldr r3, [r3, #0] - 8004a44: 099b lsrs r3, r3, #6 - 8004a46: 4a7f ldr r2, [pc, #508] ; (8004c44 ) - 8004a48: fba2 2303 umull r2, r3, r2, r3 - 8004a4c: 099b lsrs r3, r3, #6 - 8004a4e: 3301 adds r3, #1 - 8004a50: 005b lsls r3, r3, #1 - 8004a52: 60fb str r3, [r7, #12] + 80056d4: 4b7f ldr r3, [pc, #508] ; (80058d4 ) + 80056d6: 681b ldr r3, [r3, #0] + 80056d8: 099b lsrs r3, r3, #6 + 80056da: 4a7f ldr r2, [pc, #508] ; (80058d8 ) + 80056dc: fba2 2303 umull r2, r3, r2, r3 + 80056e0: 099b lsrs r3, r3, #6 + 80056e2: 3301 adds r3, #1 + 80056e4: 005b lsls r3, r3, #1 + 80056e6: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8004a54: e002 b.n 8004a5c + 80056e8: e002 b.n 80056f0 { wait_loop_index--; - 8004a56: 68fb ldr r3, [r7, #12] - 8004a58: 3b01 subs r3, #1 - 8004a5a: 60fb str r3, [r7, #12] + 80056ea: 68fb ldr r3, [r7, #12] + 80056ec: 3b01 subs r3, #1 + 80056ee: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8004a5c: 68fb ldr r3, [r7, #12] - 8004a5e: 2b00 cmp r3, #0 - 8004a60: d1f9 bne.n 8004a56 + 80056f0: 68fb ldr r3, [r7, #12] + 80056f2: 2b00 cmp r3, #0 + 80056f4: d1f9 bne.n 80056ea } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 8004a62: 687b ldr r3, [r7, #4] - 8004a64: 681b ldr r3, [r3, #0] - 8004a66: 4618 mov r0, r3 - 8004a68: f7ff ff3c bl 80048e4 - 8004a6c: 4603 mov r3, r0 - 8004a6e: 2b00 cmp r3, #0 - 8004a70: d10d bne.n 8004a8e + 80056f6: 687b ldr r3, [r7, #4] + 80056f8: 681b ldr r3, [r3, #0] + 80056fa: 4618 mov r0, r3 + 80056fc: f7ff ff3c bl 8005578 + 8005700: 4603 mov r3, r0 + 8005702: 2b00 cmp r3, #0 + 8005704: d10d bne.n 8005722 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8004a72: 687b ldr r3, [r7, #4] - 8004a74: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004a76: f043 0210 orr.w r2, r3, #16 - 8004a7a: 687b ldr r3, [r7, #4] - 8004a7c: 655a str r2, [r3, #84] ; 0x54 + 8005706: 687b ldr r3, [r7, #4] + 8005708: 6d5b ldr r3, [r3, #84] ; 0x54 + 800570a: f043 0210 orr.w r2, r3, #16 + 800570e: 687b ldr r3, [r7, #4] + 8005710: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8004a7e: 687b ldr r3, [r7, #4] - 8004a80: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004a82: f043 0201 orr.w r2, r3, #1 - 8004a86: 687b ldr r3, [r7, #4] - 8004a88: 659a str r2, [r3, #88] ; 0x58 + 8005712: 687b ldr r3, [r7, #4] + 8005714: 6d9b ldr r3, [r3, #88] ; 0x58 + 8005716: f043 0201 orr.w r2, r3, #1 + 800571a: 687b ldr r3, [r7, #4] + 800571c: 659a str r2, [r3, #88] ; 0x58 tmp_hal_status = HAL_ERROR; - 8004a8a: 2301 movs r3, #1 - 8004a8c: 77fb strb r3, [r7, #31] + 800571e: 2301 movs r3, #1 + 8005720: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 8004a8e: 687b ldr r3, [r7, #4] - 8004a90: 681b ldr r3, [r3, #0] - 8004a92: 4618 mov r0, r3 - 8004a94: f7ff ff75 bl 8004982 - 8004a98: 6178 str r0, [r7, #20] + 8005722: 687b ldr r3, [r7, #4] + 8005724: 681b ldr r3, [r3, #0] + 8005726: 4618 mov r0, r3 + 8005728: f7ff ff75 bl 8005616 + 800572c: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 8004a9a: 687b ldr r3, [r7, #4] - 8004a9c: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004a9e: f003 0310 and.w r3, r3, #16 - 8004aa2: 2b00 cmp r3, #0 - 8004aa4: f040 80bf bne.w 8004c26 + 800572e: 687b ldr r3, [r7, #4] + 8005730: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005732: f003 0310 and.w r3, r3, #16 + 8005736: 2b00 cmp r3, #0 + 8005738: f040 80bf bne.w 80058ba && (tmp_adc_is_conversion_on_going_regular == 0UL) - 8004aa8: 697b ldr r3, [r7, #20] - 8004aaa: 2b00 cmp r3, #0 - 8004aac: f040 80bb bne.w 8004c26 + 800573c: 697b ldr r3, [r7, #20] + 800573e: 2b00 cmp r3, #0 + 8005740: f040 80bb bne.w 80058ba ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 8004ab0: 687b ldr r3, [r7, #4] - 8004ab2: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004ab4: f423 7381 bic.w r3, r3, #258 ; 0x102 - 8004ab8: f043 0202 orr.w r2, r3, #2 - 8004abc: 687b ldr r3, [r7, #4] - 8004abe: 655a str r2, [r3, #84] ; 0x54 + 8005744: 687b ldr r3, [r7, #4] + 8005746: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005748: f423 7381 bic.w r3, r3, #258 ; 0x102 + 800574c: f043 0202 orr.w r2, r3, #2 + 8005750: 687b ldr r3, [r7, #4] + 8005752: 655a str r2, [r3, #84] ; 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8004ac0: 687b ldr r3, [r7, #4] - 8004ac2: 681b ldr r3, [r3, #0] - 8004ac4: 4618 mov r0, r3 - 8004ac6: f7ff ff35 bl 8004934 - 8004aca: 4603 mov r3, r0 - 8004acc: 2b00 cmp r3, #0 - 8004ace: d10b bne.n 8004ae8 + 8005754: 687b ldr r3, [r7, #4] + 8005756: 681b ldr r3, [r3, #0] + 8005758: 4618 mov r0, r3 + 800575a: f7ff ff35 bl 80055c8 + 800575e: 4603 mov r3, r0 + 8005760: 2b00 cmp r3, #0 + 8005762: d10b bne.n 800577c { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - 8004ad0: 485d ldr r0, [pc, #372] ; (8004c48 ) - 8004ad2: f7ff ff2f bl 8004934 - 8004ad6: 4603 mov r3, r0 - 8004ad8: 2b00 cmp r3, #0 - 8004ada: d105 bne.n 8004ae8 + 8005764: 485d ldr r0, [pc, #372] ; (80058dc ) + 8005766: f7ff ff2f bl 80055c8 + 800576a: 4603 mov r3, r0 + 800576c: 2b00 cmp r3, #0 + 800576e: d105 bne.n 800577c /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); - 8004adc: 687b ldr r3, [r7, #4] - 8004ade: 685b ldr r3, [r3, #4] - 8004ae0: 4619 mov r1, r3 - 8004ae2: 485a ldr r0, [pc, #360] ; (8004c4c ) - 8004ae4: f7ff fd9a bl 800461c + 8005770: 687b ldr r3, [r7, #4] + 8005772: 685b ldr r3, [r3, #4] + 8005774: 4619 mov r1, r3 + 8005776: 485a ldr r0, [pc, #360] ; (80058e0 ) + 8005778: f7ff fd9a bl 80052b0 /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8004ae8: 687b ldr r3, [r7, #4] - 8004aea: 7e5b ldrb r3, [r3, #25] - 8004aec: 035a lsls r2, r3, #13 + 800577c: 687b ldr r3, [r7, #4] + 800577e: 7e5b ldrb r3, [r3, #25] + 8005780: 035a lsls r2, r3, #13 hadc->Init.Overrun | - 8004aee: 687b ldr r3, [r7, #4] - 8004af0: 6b5b ldr r3, [r3, #52] ; 0x34 + 8005782: 687b ldr r3, [r7, #4] + 8005784: 6b5b ldr r3, [r3, #52] ; 0x34 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8004af2: 431a orrs r2, r3 + 8005786: 431a orrs r2, r3 hadc->Init.DataAlign | - 8004af4: 687b ldr r3, [r7, #4] - 8004af6: 68db ldr r3, [r3, #12] + 8005788: 687b ldr r3, [r7, #4] + 800578a: 68db ldr r3, [r3, #12] hadc->Init.Overrun | - 8004af8: 431a orrs r2, r3 + 800578c: 431a orrs r2, r3 hadc->Init.Resolution | - 8004afa: 687b ldr r3, [r7, #4] - 8004afc: 689b ldr r3, [r3, #8] + 800578e: 687b ldr r3, [r7, #4] + 8005790: 689b ldr r3, [r3, #8] hadc->Init.DataAlign | - 8004afe: 431a orrs r2, r3 + 8005792: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); - 8004b00: 687b ldr r3, [r7, #4] - 8004b02: f893 3020 ldrb.w r3, [r3, #32] - 8004b06: 041b lsls r3, r3, #16 + 8005794: 687b ldr r3, [r7, #4] + 8005796: f893 3020 ldrb.w r3, [r3, #32] + 800579a: 041b lsls r3, r3, #16 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8004b08: 4313 orrs r3, r2 - 8004b0a: 61bb str r3, [r7, #24] + 800579c: 4313 orrs r3, r2 + 800579e: 61bb str r3, [r7, #24] if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8004b0c: 687b ldr r3, [r7, #4] - 8004b0e: f893 3020 ldrb.w r3, [r3, #32] - 8004b12: 2b01 cmp r3, #1 - 8004b14: d106 bne.n 8004b24 + 80057a0: 687b ldr r3, [r7, #4] + 80057a2: f893 3020 ldrb.w r3, [r3, #32] + 80057a6: 2b01 cmp r3, #1 + 80057a8: d106 bne.n 80057b8 { tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); - 8004b16: 687b ldr r3, [r7, #4] - 8004b18: 6a5b ldr r3, [r3, #36] ; 0x24 - 8004b1a: 3b01 subs r3, #1 - 8004b1c: 045b lsls r3, r3, #17 - 8004b1e: 69ba ldr r2, [r7, #24] - 8004b20: 4313 orrs r3, r2 - 8004b22: 61bb str r3, [r7, #24] + 80057aa: 687b ldr r3, [r7, #4] + 80057ac: 6a5b ldr r3, [r3, #36] ; 0x24 + 80057ae: 3b01 subs r3, #1 + 80057b0: 045b lsls r3, r3, #17 + 80057b2: 69ba ldr r2, [r7, #24] + 80057b4: 4313 orrs r3, r2 + 80057b6: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - 8004b24: 687b ldr r3, [r7, #4] - 8004b26: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004b28: 2b00 cmp r3, #0 - 8004b2a: d009 beq.n 8004b40 + 80057b8: 687b ldr r3, [r7, #4] + 80057ba: 6a9b ldr r3, [r3, #40] ; 0x28 + 80057bc: 2b00 cmp r3, #0 + 80057be: d009 beq.n 80057d4 { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - 8004b2c: 687b ldr r3, [r7, #4] - 8004b2e: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004b30: f403 7270 and.w r2, r3, #960 ; 0x3c0 + 80057c0: 687b ldr r3, [r7, #4] + 80057c2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80057c4: f403 7270 and.w r2, r3, #960 ; 0x3c0 | hadc->Init.ExternalTrigConvEdge - 8004b34: 687b ldr r3, [r7, #4] - 8004b36: 6adb ldr r3, [r3, #44] ; 0x2c - 8004b38: 4313 orrs r3, r2 + 80057c8: 687b ldr r3, [r7, #4] + 80057ca: 6adb ldr r3, [r3, #44] ; 0x2c + 80057cc: 4313 orrs r3, r2 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - 8004b3a: 69ba ldr r2, [r7, #24] - 8004b3c: 4313 orrs r3, r2 - 8004b3e: 61bb str r3, [r7, #24] + 80057ce: 69ba ldr r2, [r7, #24] + 80057d0: 4313 orrs r3, r2 + 80057d2: 61bb str r3, [r7, #24] ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); - 8004b40: 687b ldr r3, [r7, #4] - 8004b42: 681b ldr r3, [r3, #0] - 8004b44: 68da ldr r2, [r3, #12] - 8004b46: 4b42 ldr r3, [pc, #264] ; (8004c50 ) - 8004b48: 4013 ands r3, r2 - 8004b4a: 687a ldr r2, [r7, #4] - 8004b4c: 6812 ldr r2, [r2, #0] - 8004b4e: 69b9 ldr r1, [r7, #24] - 8004b50: 430b orrs r3, r1 - 8004b52: 60d3 str r3, [r2, #12] + 80057d4: 687b ldr r3, [r7, #4] + 80057d6: 681b ldr r3, [r3, #0] + 80057d8: 68da ldr r2, [r3, #12] + 80057da: 4b42 ldr r3, [pc, #264] ; (80058e4 ) + 80057dc: 4013 ands r3, r2 + 80057de: 687a ldr r2, [r7, #4] + 80057e0: 6812 ldr r2, [r2, #0] + 80057e2: 69b9 ldr r1, [r7, #24] + 80057e4: 430b orrs r3, r1 + 80057e6: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - 8004b54: 687b ldr r3, [r7, #4] - 8004b56: 681b ldr r3, [r3, #0] - 8004b58: 4618 mov r0, r3 - 8004b5a: f7ff ff25 bl 80049a8 - 8004b5e: 6138 str r0, [r7, #16] + 80057e8: 687b ldr r3, [r7, #4] + 80057ea: 681b ldr r3, [r3, #0] + 80057ec: 4618 mov r0, r3 + 80057ee: f7ff ff25 bl 800563c + 80057f2: 6138 str r0, [r7, #16] if ((tmp_adc_is_conversion_on_going_regular == 0UL) - 8004b60: 697b ldr r3, [r7, #20] - 8004b62: 2b00 cmp r3, #0 - 8004b64: d13d bne.n 8004be2 + 80057f4: 697b ldr r3, [r7, #20] + 80057f6: 2b00 cmp r3, #0 + 80057f8: d13d bne.n 8005876 && (tmp_adc_is_conversion_on_going_injected == 0UL) - 8004b66: 693b ldr r3, [r7, #16] - 8004b68: 2b00 cmp r3, #0 - 8004b6a: d13a bne.n 8004be2 + 80057fa: 693b ldr r3, [r7, #16] + 80057fc: 2b00 cmp r3, #0 + 80057fe: d13a bne.n 8005876 ) { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 8004b6c: 687b ldr r3, [r7, #4] - 8004b6e: 7e1b ldrb r3, [r3, #24] + 8005800: 687b ldr r3, [r7, #4] + 8005802: 7e1b ldrb r3, [r3, #24] tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | - 8004b70: 039a lsls r2, r3, #14 + 8005804: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - 8004b72: 687b ldr r3, [r7, #4] - 8004b74: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 - 8004b78: 005b lsls r3, r3, #1 + 8005806: 687b ldr r3, [r7, #4] + 8005808: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800580c: 005b lsls r3, r3, #1 tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | - 8004b7a: 4313 orrs r3, r2 - 8004b7c: 61bb str r3, [r7, #24] + 800580e: 4313 orrs r3, r2 + 8005810: 61bb str r3, [r7, #24] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); - 8004b7e: 687b ldr r3, [r7, #4] - 8004b80: 681b ldr r3, [r3, #0] - 8004b82: 68db ldr r3, [r3, #12] - 8004b84: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 8004b88: f023 0302 bic.w r3, r3, #2 - 8004b8c: 687a ldr r2, [r7, #4] - 8004b8e: 6812 ldr r2, [r2, #0] - 8004b90: 69b9 ldr r1, [r7, #24] - 8004b92: 430b orrs r3, r1 - 8004b94: 60d3 str r3, [r2, #12] + 8005812: 687b ldr r3, [r7, #4] + 8005814: 681b ldr r3, [r3, #0] + 8005816: 68db ldr r3, [r3, #12] + 8005818: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800581c: f023 0302 bic.w r3, r3, #2 + 8005820: 687a ldr r2, [r7, #4] + 8005822: 6812 ldr r2, [r2, #0] + 8005824: 69b9 ldr r1, [r7, #24] + 8005826: 430b orrs r3, r1 + 8005828: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) - 8004b96: 687b ldr r3, [r7, #4] - 8004b98: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 - 8004b9c: 2b01 cmp r3, #1 - 8004b9e: d118 bne.n 8004bd2 + 800582a: 687b ldr r3, [r7, #4] + 800582c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 8005830: 2b01 cmp r3, #1 + 8005832: d118 bne.n 8005866 /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, - 8004ba0: 687b ldr r3, [r7, #4] - 8004ba2: 681b ldr r3, [r3, #0] - 8004ba4: 691b ldr r3, [r3, #16] - 8004ba6: f423 63ff bic.w r3, r3, #2040 ; 0x7f8 - 8004baa: f023 0304 bic.w r3, r3, #4 - 8004bae: 687a ldr r2, [r7, #4] - 8004bb0: 6bd1 ldr r1, [r2, #60] ; 0x3c - 8004bb2: 687a ldr r2, [r7, #4] - 8004bb4: 6c12 ldr r2, [r2, #64] ; 0x40 - 8004bb6: 4311 orrs r1, r2 - 8004bb8: 687a ldr r2, [r7, #4] - 8004bba: 6c52 ldr r2, [r2, #68] ; 0x44 - 8004bbc: 4311 orrs r1, r2 - 8004bbe: 687a ldr r2, [r7, #4] - 8004bc0: 6c92 ldr r2, [r2, #72] ; 0x48 - 8004bc2: 430a orrs r2, r1 - 8004bc4: 431a orrs r2, r3 - 8004bc6: 687b ldr r3, [r7, #4] - 8004bc8: 681b ldr r3, [r3, #0] - 8004bca: f042 0201 orr.w r2, r2, #1 - 8004bce: 611a str r2, [r3, #16] - 8004bd0: e007 b.n 8004be2 + 8005834: 687b ldr r3, [r7, #4] + 8005836: 681b ldr r3, [r3, #0] + 8005838: 691b ldr r3, [r3, #16] + 800583a: f423 63ff bic.w r3, r3, #2040 ; 0x7f8 + 800583e: f023 0304 bic.w r3, r3, #4 + 8005842: 687a ldr r2, [r7, #4] + 8005844: 6bd1 ldr r1, [r2, #60] ; 0x3c + 8005846: 687a ldr r2, [r7, #4] + 8005848: 6c12 ldr r2, [r2, #64] ; 0x40 + 800584a: 4311 orrs r1, r2 + 800584c: 687a ldr r2, [r7, #4] + 800584e: 6c52 ldr r2, [r2, #68] ; 0x44 + 8005850: 4311 orrs r1, r2 + 8005852: 687a ldr r2, [r7, #4] + 8005854: 6c92 ldr r2, [r2, #72] ; 0x48 + 8005856: 430a orrs r2, r1 + 8005858: 431a orrs r2, r3 + 800585a: 687b ldr r3, [r7, #4] + 800585c: 681b ldr r3, [r3, #0] + 800585e: f042 0201 orr.w r2, r2, #1 + 8005862: 611a str r2, [r3, #16] + 8005864: e007 b.n 8005876 ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); - 8004bd2: 687b ldr r3, [r7, #4] - 8004bd4: 681b ldr r3, [r3, #0] - 8004bd6: 691a ldr r2, [r3, #16] - 8004bd8: 687b ldr r3, [r7, #4] - 8004bda: 681b ldr r3, [r3, #0] - 8004bdc: f022 0201 bic.w r2, r2, #1 - 8004be0: 611a str r2, [r3, #16] + 8005866: 687b ldr r3, [r7, #4] + 8005868: 681b ldr r3, [r3, #0] + 800586a: 691a ldr r2, [r3, #16] + 800586c: 687b ldr r3, [r7, #4] + 800586e: 681b ldr r3, [r3, #0] + 8005870: f022 0201 bic.w r2, r2, #1 + 8005874: 611a str r2, [r3, #16] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - 8004be2: 687b ldr r3, [r7, #4] - 8004be4: 691b ldr r3, [r3, #16] - 8004be6: 2b01 cmp r3, #1 - 8004be8: d10c bne.n 8004c04 + 8005876: 687b ldr r3, [r7, #4] + 8005878: 691b ldr r3, [r3, #16] + 800587a: 2b01 cmp r3, #1 + 800587c: d10c bne.n 8005898 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); - 8004bea: 687b ldr r3, [r7, #4] - 8004bec: 681b ldr r3, [r3, #0] - 8004bee: 6b1b ldr r3, [r3, #48] ; 0x30 - 8004bf0: f023 010f bic.w r1, r3, #15 - 8004bf4: 687b ldr r3, [r7, #4] - 8004bf6: 69db ldr r3, [r3, #28] - 8004bf8: 1e5a subs r2, r3, #1 - 8004bfa: 687b ldr r3, [r7, #4] - 8004bfc: 681b ldr r3, [r3, #0] - 8004bfe: 430a orrs r2, r1 - 8004c00: 631a str r2, [r3, #48] ; 0x30 - 8004c02: e007 b.n 8004c14 + 800587e: 687b ldr r3, [r7, #4] + 8005880: 681b ldr r3, [r3, #0] + 8005882: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005884: f023 010f bic.w r1, r3, #15 + 8005888: 687b ldr r3, [r7, #4] + 800588a: 69db ldr r3, [r3, #28] + 800588c: 1e5a subs r2, r3, #1 + 800588e: 687b ldr r3, [r7, #4] + 8005890: 681b ldr r3, [r3, #0] + 8005892: 430a orrs r2, r1 + 8005894: 631a str r2, [r3, #48] ; 0x30 + 8005896: e007 b.n 80058a8 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); - 8004c04: 687b ldr r3, [r7, #4] - 8004c06: 681b ldr r3, [r3, #0] - 8004c08: 6b1a ldr r2, [r3, #48] ; 0x30 - 8004c0a: 687b ldr r3, [r7, #4] - 8004c0c: 681b ldr r3, [r3, #0] - 8004c0e: f022 020f bic.w r2, r2, #15 - 8004c12: 631a str r2, [r3, #48] ; 0x30 + 8005898: 687b ldr r3, [r7, #4] + 800589a: 681b ldr r3, [r3, #0] + 800589c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800589e: 687b ldr r3, [r7, #4] + 80058a0: 681b ldr r3, [r3, #0] + 80058a2: f022 020f bic.w r2, r2, #15 + 80058a6: 631a str r2, [r3, #48] ; 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); - 8004c14: 687b ldr r3, [r7, #4] - 8004c16: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004c18: f023 0303 bic.w r3, r3, #3 - 8004c1c: f043 0201 orr.w r2, r3, #1 - 8004c20: 687b ldr r3, [r7, #4] - 8004c22: 655a str r2, [r3, #84] ; 0x54 - 8004c24: e007 b.n 8004c36 + 80058a8: 687b ldr r3, [r7, #4] + 80058aa: 6d5b ldr r3, [r3, #84] ; 0x54 + 80058ac: f023 0303 bic.w r3, r3, #3 + 80058b0: f043 0201 orr.w r2, r3, #1 + 80058b4: 687b ldr r3, [r7, #4] + 80058b6: 655a str r2, [r3, #84] ; 0x54 + 80058b8: e007 b.n 80058ca } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8004c26: 687b ldr r3, [r7, #4] - 8004c28: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004c2a: f043 0210 orr.w r2, r3, #16 - 8004c2e: 687b ldr r3, [r7, #4] - 8004c30: 655a str r2, [r3, #84] ; 0x54 + 80058ba: 687b ldr r3, [r7, #4] + 80058bc: 6d5b ldr r3, [r3, #84] ; 0x54 + 80058be: f043 0210 orr.w r2, r3, #16 + 80058c2: 687b ldr r3, [r7, #4] + 80058c4: 655a str r2, [r3, #84] ; 0x54 tmp_hal_status = HAL_ERROR; - 8004c32: 2301 movs r3, #1 - 8004c34: 77fb strb r3, [r7, #31] + 80058c6: 2301 movs r3, #1 + 80058c8: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; - 8004c36: 7ffb ldrb r3, [r7, #31] -} - 8004c38: 4618 mov r0, r3 - 8004c3a: 3720 adds r7, #32 - 8004c3c: 46bd mov sp, r7 - 8004c3e: bd80 pop {r7, pc} - 8004c40: 20000020 .word 0x20000020 - 8004c44: 053e2d63 .word 0x053e2d63 - 8004c48: 50040000 .word 0x50040000 - 8004c4c: 50040300 .word 0x50040300 - 8004c50: fff0c007 .word 0xfff0c007 - -08004c54 : + 80058ca: 7ffb ldrb r3, [r7, #31] +} + 80058cc: 4618 mov r0, r3 + 80058ce: 3720 adds r7, #32 + 80058d0: 46bd mov sp, r7 + 80058d2: bd80 pop {r7, pc} + 80058d4: 20000020 .word 0x20000020 + 80058d8: 053e2d63 .word 0x053e2d63 + 80058dc: 50040000 .word 0x50040000 + 80058e0: 50040300 .word 0x50040300 + 80058e4: fff0c007 .word 0xfff0c007 + +080058e8 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { - 8004c54: b580 push {r7, lr} - 8004c56: b086 sub sp, #24 - 8004c58: af00 add r7, sp, #0 - 8004c5a: 60f8 str r0, [r7, #12] - 8004c5c: 60b9 str r1, [r7, #8] - 8004c5e: 607a str r2, [r7, #4] + 80058e8: b580 push {r7, lr} + 80058ea: b086 sub sp, #24 + 80058ec: af00 add r7, sp, #0 + 80058ee: 60f8 str r0, [r7, #12] + 80058f0: 60b9 str r1, [r7, #8] + 80058f2: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 8004c60: 68fb ldr r3, [r7, #12] - 8004c62: 681b ldr r3, [r3, #0] - 8004c64: 4618 mov r0, r3 - 8004c66: f7ff fe8c bl 8004982 - 8004c6a: 4603 mov r3, r0 - 8004c6c: 2b00 cmp r3, #0 - 8004c6e: d167 bne.n 8004d40 + 80058f4: 68fb ldr r3, [r7, #12] + 80058f6: 681b ldr r3, [r3, #0] + 80058f8: 4618 mov r0, r3 + 80058fa: f7ff fe8c bl 8005616 + 80058fe: 4603 mov r3, r0 + 8005900: 2b00 cmp r3, #0 + 8005902: d167 bne.n 80059d4 { /* Process locked */ __HAL_LOCK(hadc); - 8004c70: 68fb ldr r3, [r7, #12] - 8004c72: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 - 8004c76: 2b01 cmp r3, #1 - 8004c78: d101 bne.n 8004c7e - 8004c7a: 2302 movs r3, #2 - 8004c7c: e063 b.n 8004d46 - 8004c7e: 68fb ldr r3, [r7, #12] - 8004c80: 2201 movs r2, #1 - 8004c82: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 8005904: 68fb ldr r3, [r7, #12] + 8005906: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 800590a: 2b01 cmp r3, #1 + 800590c: d101 bne.n 8005912 + 800590e: 2302 movs r3, #2 + 8005910: e063 b.n 80059da + 8005912: 68fb ldr r3, [r7, #12] + 8005914: 2201 movs r2, #1 + 8005916: f883 2050 strb.w r2, [r3, #80] ; 0x50 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) #endif /* ADC_MULTIMODE_SUPPORT */ { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - 8004c86: 68f8 ldr r0, [r7, #12] - 8004c88: f000 fe1c bl 80058c4 - 8004c8c: 4603 mov r3, r0 - 8004c8e: 75fb strb r3, [r7, #23] + 800591a: 68f8 ldr r0, [r7, #12] + 800591c: f000 fe1c bl 8006558 + 8005920: 4603 mov r3, r0 + 8005922: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) - 8004c90: 7dfb ldrb r3, [r7, #23] - 8004c92: 2b00 cmp r3, #0 - 8004c94: d14f bne.n 8004d36 + 8005924: 7dfb ldrb r3, [r7, #23] + 8005926: 2b00 cmp r3, #0 + 8005928: d14f bne.n 80059ca { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, - 8004c96: 68fb ldr r3, [r7, #12] - 8004c98: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004c9a: f423 6370 bic.w r3, r3, #3840 ; 0xf00 - 8004c9e: f023 0301 bic.w r3, r3, #1 - 8004ca2: f443 7280 orr.w r2, r3, #256 ; 0x100 - 8004ca6: 68fb ldr r3, [r7, #12] - 8004ca8: 655a str r2, [r3, #84] ; 0x54 + 800592a: 68fb ldr r3, [r7, #12] + 800592c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800592e: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 8005932: f023 0301 bic.w r3, r3, #1 + 8005936: f443 7280 orr.w r2, r3, #256 ; 0x100 + 800593a: 68fb ldr r3, [r7, #12] + 800593c: 655a str r2, [r3, #84] ; 0x54 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) - 8004caa: 68fb ldr r3, [r7, #12] - 8004cac: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004cae: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8004cb2: 2b00 cmp r3, #0 - 8004cb4: d006 beq.n 8004cc4 + 800593e: 68fb ldr r3, [r7, #12] + 8005940: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005942: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8005946: 2b00 cmp r3, #0 + 8005948: d006 beq.n 8005958 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - 8004cb6: 68fb ldr r3, [r7, #12] - 8004cb8: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004cba: f023 0206 bic.w r2, r3, #6 - 8004cbe: 68fb ldr r3, [r7, #12] - 8004cc0: 659a str r2, [r3, #88] ; 0x58 - 8004cc2: e002 b.n 8004cca + 800594a: 68fb ldr r3, [r7, #12] + 800594c: 6d9b ldr r3, [r3, #88] ; 0x58 + 800594e: f023 0206 bic.w r2, r3, #6 + 8005952: 68fb ldr r3, [r7, #12] + 8005954: 659a str r2, [r3, #88] ; 0x58 + 8005956: e002 b.n 800595e } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); - 8004cc4: 68fb ldr r3, [r7, #12] - 8004cc6: 2200 movs r2, #0 - 8004cc8: 659a str r2, [r3, #88] ; 0x58 + 8005958: 68fb ldr r3, [r7, #12] + 800595a: 2200 movs r2, #0 + 800595c: 659a str r2, [r3, #88] ; 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - 8004cca: 68fb ldr r3, [r7, #12] - 8004ccc: 6cdb ldr r3, [r3, #76] ; 0x4c - 8004cce: 4a20 ldr r2, [pc, #128] ; (8004d50 ) - 8004cd0: 62da str r2, [r3, #44] ; 0x2c + 800595e: 68fb ldr r3, [r7, #12] + 8005960: 6cdb ldr r3, [r3, #76] ; 0x4c + 8005962: 4a20 ldr r2, [pc, #128] ; (80059e4 ) + 8005964: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - 8004cd2: 68fb ldr r3, [r7, #12] - 8004cd4: 6cdb ldr r3, [r3, #76] ; 0x4c - 8004cd6: 4a1f ldr r2, [pc, #124] ; (8004d54 ) - 8004cd8: 631a str r2, [r3, #48] ; 0x30 + 8005966: 68fb ldr r3, [r7, #12] + 8005968: 6cdb ldr r3, [r3, #76] ; 0x4c + 800596a: 4a1f ldr r2, [pc, #124] ; (80059e8 ) + 800596c: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - 8004cda: 68fb ldr r3, [r7, #12] - 8004cdc: 6cdb ldr r3, [r3, #76] ; 0x4c - 8004cde: 4a1e ldr r2, [pc, #120] ; (8004d58 ) - 8004ce0: 635a str r2, [r3, #52] ; 0x34 + 800596e: 68fb ldr r3, [r7, #12] + 8005970: 6cdb ldr r3, [r3, #76] ; 0x4c + 8005972: 4a1e ldr r2, [pc, #120] ; (80059ec ) + 8005974: 635a str r2, [r3, #52] ; 0x34 /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - 8004ce2: 68fb ldr r3, [r7, #12] - 8004ce4: 681b ldr r3, [r3, #0] - 8004ce6: 221c movs r2, #28 - 8004ce8: 601a str r2, [r3, #0] + 8005976: 68fb ldr r3, [r7, #12] + 8005978: 681b ldr r3, [r3, #0] + 800597a: 221c movs r2, #28 + 800597c: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - 8004cea: 68fb ldr r3, [r7, #12] - 8004cec: 2200 movs r2, #0 - 8004cee: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 800597e: 68fb ldr r3, [r7, #12] + 8005980: 2200 movs r2, #0 + 8005982: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - 8004cf2: 68fb ldr r3, [r7, #12] - 8004cf4: 681b ldr r3, [r3, #0] - 8004cf6: 685a ldr r2, [r3, #4] - 8004cf8: 68fb ldr r3, [r7, #12] - 8004cfa: 681b ldr r3, [r3, #0] - 8004cfc: f042 0210 orr.w r2, r2, #16 - 8004d00: 605a str r2, [r3, #4] + 8005986: 68fb ldr r3, [r7, #12] + 8005988: 681b ldr r3, [r3, #0] + 800598a: 685a ldr r2, [r3, #4] + 800598c: 68fb ldr r3, [r7, #12] + 800598e: 681b ldr r3, [r3, #0] + 8005990: f042 0210 orr.w r2, r2, #16 + 8005994: 605a str r2, [r3, #4] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); - 8004d02: 68fb ldr r3, [r7, #12] - 8004d04: 681b ldr r3, [r3, #0] - 8004d06: 68da ldr r2, [r3, #12] - 8004d08: 68fb ldr r3, [r7, #12] - 8004d0a: 681b ldr r3, [r3, #0] - 8004d0c: f042 0201 orr.w r2, r2, #1 - 8004d10: 60da str r2, [r3, #12] + 8005996: 68fb ldr r3, [r7, #12] + 8005998: 681b ldr r3, [r3, #0] + 800599a: 68da ldr r2, [r3, #12] + 800599c: 68fb ldr r3, [r7, #12] + 800599e: 681b ldr r3, [r3, #0] + 80059a0: f042 0201 orr.w r2, r2, #1 + 80059a4: 60da str r2, [r3, #12] /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - 8004d12: 68fb ldr r3, [r7, #12] - 8004d14: 6cd8 ldr r0, [r3, #76] ; 0x4c - 8004d16: 68fb ldr r3, [r7, #12] - 8004d18: 681b ldr r3, [r3, #0] - 8004d1a: 3340 adds r3, #64 ; 0x40 - 8004d1c: 4619 mov r1, r3 - 8004d1e: 68ba ldr r2, [r7, #8] - 8004d20: 687b ldr r3, [r7, #4] - 8004d22: f001 f9a9 bl 8006078 - 8004d26: 4603 mov r3, r0 - 8004d28: 75fb strb r3, [r7, #23] + 80059a6: 68fb ldr r3, [r7, #12] + 80059a8: 6cd8 ldr r0, [r3, #76] ; 0x4c + 80059aa: 68fb ldr r3, [r7, #12] + 80059ac: 681b ldr r3, [r3, #0] + 80059ae: 3340 adds r3, #64 ; 0x40 + 80059b0: 4619 mov r1, r3 + 80059b2: 68ba ldr r2, [r7, #8] + 80059b4: 687b ldr r3, [r7, #4] + 80059b6: f001 f8e5 bl 8006b84 + 80059ba: 4603 mov r3, r0 + 80059bc: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); - 8004d2a: 68fb ldr r3, [r7, #12] - 8004d2c: 681b ldr r3, [r3, #0] - 8004d2e: 4618 mov r0, r3 - 8004d30: f7ff fe13 bl 800495a - 8004d34: e006 b.n 8004d44 + 80059be: 68fb ldr r3, [r7, #12] + 80059c0: 681b ldr r3, [r3, #0] + 80059c2: 4618 mov r0, r3 + 80059c4: f7ff fe13 bl 80055ee + 80059c8: e006 b.n 80059d8 } else { /* Process unlocked */ __HAL_UNLOCK(hadc); - 8004d36: 68fb ldr r3, [r7, #12] - 8004d38: 2200 movs r2, #0 - 8004d3a: f883 2050 strb.w r2, [r3, #80] ; 0x50 - 8004d3e: e001 b.n 8004d44 + 80059ca: 68fb ldr r3, [r7, #12] + 80059cc: 2200 movs r2, #0 + 80059ce: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 80059d2: e001 b.n 80059d8 } #endif /* ADC_MULTIMODE_SUPPORT */ } else { tmp_hal_status = HAL_BUSY; - 8004d40: 2302 movs r3, #2 - 8004d42: 75fb strb r3, [r7, #23] + 80059d4: 2302 movs r3, #2 + 80059d6: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; - 8004d44: 7dfb ldrb r3, [r7, #23] -} - 8004d46: 4618 mov r0, r3 - 8004d48: 3718 adds r7, #24 - 8004d4a: 46bd mov sp, r7 - 8004d4c: bd80 pop {r7, pc} - 8004d4e: bf00 nop - 8004d50: 080059d1 .word 0x080059d1 - 8004d54: 08005aa9 .word 0x08005aa9 - 8004d58: 08005ac5 .word 0x08005ac5 - -08004d5c : + 80059d8: 7dfb ldrb r3, [r7, #23] +} + 80059da: 4618 mov r0, r3 + 80059dc: 3718 adds r7, #24 + 80059de: 46bd mov sp, r7 + 80059e0: bd80 pop {r7, pc} + 80059e2: bf00 nop + 80059e4: 08006665 .word 0x08006665 + 80059e8: 0800673d .word 0x0800673d + 80059ec: 08006759 .word 0x08006759 + +080059f0 : * @brief Handle ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { - 8004d5c: b580 push {r7, lr} - 8004d5e: b088 sub sp, #32 - 8004d60: af00 add r7, sp, #0 - 8004d62: 6078 str r0, [r7, #4] + 80059f0: b580 push {r7, lr} + 80059f2: b088 sub sp, #32 + 80059f4: af00 add r7, sp, #0 + 80059f6: 6078 str r0, [r7, #4] uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ - 8004d64: 2300 movs r3, #0 - 8004d66: 61fb str r3, [r7, #28] + 80059f8: 2300 movs r3, #0 + 80059fa: 61fb str r3, [r7, #28] uint32_t tmp_isr = hadc->Instance->ISR; - 8004d68: 687b ldr r3, [r7, #4] - 8004d6a: 681b ldr r3, [r3, #0] - 8004d6c: 681b ldr r3, [r3, #0] - 8004d6e: 61bb str r3, [r7, #24] + 80059fc: 687b ldr r3, [r7, #4] + 80059fe: 681b ldr r3, [r3, #0] + 8005a00: 681b ldr r3, [r3, #0] + 8005a02: 61bb str r3, [r7, #24] uint32_t tmp_ier = hadc->Instance->IER; - 8004d70: 687b ldr r3, [r7, #4] - 8004d72: 681b ldr r3, [r3, #0] - 8004d74: 685b ldr r3, [r3, #4] - 8004d76: 617b str r3, [r7, #20] + 8005a04: 687b ldr r3, [r7, #4] + 8005a06: 681b ldr r3, [r3, #0] + 8005a08: 685b ldr r3, [r3, #4] + 8005a0a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Sampling flag for ADC group regular ========== */ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) - 8004d78: 69bb ldr r3, [r7, #24] - 8004d7a: f003 0302 and.w r3, r3, #2 - 8004d7e: 2b00 cmp r3, #0 - 8004d80: d017 beq.n 8004db2 - 8004d82: 697b ldr r3, [r7, #20] - 8004d84: f003 0302 and.w r3, r3, #2 - 8004d88: 2b00 cmp r3, #0 - 8004d8a: d012 beq.n 8004db2 + 8005a0c: 69bb ldr r3, [r7, #24] + 8005a0e: f003 0302 and.w r3, r3, #2 + 8005a12: 2b00 cmp r3, #0 + 8005a14: d017 beq.n 8005a46 + 8005a16: 697b ldr r3, [r7, #20] + 8005a18: f003 0302 and.w r3, r3, #2 + 8005a1c: 2b00 cmp r3, #0 + 8005a1e: d012 beq.n 8005a46 { /* Update state machine on end of sampling status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 8004d8c: 687b ldr r3, [r7, #4] - 8004d8e: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004d90: f003 0310 and.w r3, r3, #16 - 8004d94: 2b00 cmp r3, #0 - 8004d96: d105 bne.n 8004da4 + 8005a20: 687b ldr r3, [r7, #4] + 8005a22: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005a24: f003 0310 and.w r3, r3, #16 + 8005a28: 2b00 cmp r3, #0 + 8005a2a: d105 bne.n 8005a38 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - 8004d98: 687b ldr r3, [r7, #4] - 8004d9a: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004d9c: f443 6200 orr.w r2, r3, #2048 ; 0x800 - 8004da0: 687b ldr r3, [r7, #4] - 8004da2: 655a str r2, [r3, #84] ; 0x54 + 8005a2c: 687b ldr r3, [r7, #4] + 8005a2e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005a30: f443 6200 orr.w r2, r3, #2048 ; 0x800 + 8005a34: 687b ldr r3, [r7, #4] + 8005a36: 655a str r2, [r3, #84] ; 0x54 /* End Of Sampling callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->EndOfSamplingCallback(hadc); #else HAL_ADCEx_EndOfSamplingCallback(hadc); - 8004da4: 6878 ldr r0, [r7, #4] - 8004da6: f000 fecf bl 8005b48 + 8005a38: 6878 ldr r0, [r7, #4] + 8005a3a: f000 fecf bl 80067dc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - 8004daa: 687b ldr r3, [r7, #4] - 8004dac: 681b ldr r3, [r3, #0] - 8004dae: 2202 movs r2, #2 - 8004db0: 601a str r2, [r3, #0] + 8005a3e: 687b ldr r3, [r7, #4] + 8005a40: 681b ldr r3, [r3, #0] + 8005a42: 2202 movs r2, #2 + 8005a44: 601a str r2, [r3, #0] } /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 8004db2: 69bb ldr r3, [r7, #24] - 8004db4: f003 0304 and.w r3, r3, #4 - 8004db8: 2b00 cmp r3, #0 - 8004dba: d004 beq.n 8004dc6 - 8004dbc: 697b ldr r3, [r7, #20] - 8004dbe: f003 0304 and.w r3, r3, #4 - 8004dc2: 2b00 cmp r3, #0 - 8004dc4: d109 bne.n 8004dda + 8005a46: 69bb ldr r3, [r7, #24] + 8005a48: f003 0304 and.w r3, r3, #4 + 8005a4c: 2b00 cmp r3, #0 + 8005a4e: d004 beq.n 8005a5a + 8005a50: 697b ldr r3, [r7, #20] + 8005a52: f003 0304 and.w r3, r3, #4 + 8005a56: 2b00 cmp r3, #0 + 8005a58: d109 bne.n 8005a6e (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) - 8004dc6: 69bb ldr r3, [r7, #24] - 8004dc8: f003 0308 and.w r3, r3, #8 + 8005a5a: 69bb ldr r3, [r7, #24] + 8005a5c: f003 0308 and.w r3, r3, #8 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - 8004dcc: 2b00 cmp r3, #0 - 8004dce: d05e beq.n 8004e8e + 8005a60: 2b00 cmp r3, #0 + 8005a62: d05e beq.n 8005b22 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) - 8004dd0: 697b ldr r3, [r7, #20] - 8004dd2: f003 0308 and.w r3, r3, #8 - 8004dd6: 2b00 cmp r3, #0 - 8004dd8: d059 beq.n 8004e8e + 8005a64: 697b ldr r3, [r7, #20] + 8005a66: f003 0308 and.w r3, r3, #8 + 8005a6a: 2b00 cmp r3, #0 + 8005a6c: d059 beq.n 8005b22 { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 8004dda: 687b ldr r3, [r7, #4] - 8004ddc: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004dde: f003 0310 and.w r3, r3, #16 - 8004de2: 2b00 cmp r3, #0 - 8004de4: d105 bne.n 8004df2 + 8005a6e: 687b ldr r3, [r7, #4] + 8005a70: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005a72: f003 0310 and.w r3, r3, #16 + 8005a76: 2b00 cmp r3, #0 + 8005a78: d105 bne.n 8005a86 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 8004de6: 687b ldr r3, [r7, #4] - 8004de8: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004dea: f443 7200 orr.w r2, r3, #512 ; 0x200 - 8004dee: 687b ldr r3, [r7, #4] - 8004df0: 655a str r2, [r3, #84] ; 0x54 + 8005a7a: 687b ldr r3, [r7, #4] + 8005a7c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005a7e: f443 7200 orr.w r2, r3, #512 ; 0x200 + 8005a82: 687b ldr r3, [r7, #4] + 8005a84: 655a str r2, [r3, #84] ; 0x54 } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - 8004df2: 687b ldr r3, [r7, #4] - 8004df4: 681b ldr r3, [r3, #0] - 8004df6: 4618 mov r0, r3 - 8004df8: f7ff fc99 bl 800472e - 8004dfc: 4603 mov r3, r0 - 8004dfe: 2b00 cmp r3, #0 - 8004e00: d03e beq.n 8004e80 + 8005a86: 687b ldr r3, [r7, #4] + 8005a88: 681b ldr r3, [r3, #0] + 8005a8a: 4618 mov r0, r3 + 8005a8c: f7ff fc99 bl 80053c2 + 8005a90: 4603 mov r3, r0 + 8005a92: 2b00 cmp r3, #0 + 8005a94: d03e beq.n 8005b14 /* else need to check Master ADC CONT bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 8004e02: 687b ldr r3, [r7, #4] - 8004e04: 681b ldr r3, [r3, #0] - 8004e06: 68db ldr r3, [r3, #12] - 8004e08: 613b str r3, [r7, #16] + 8005a96: 687b ldr r3, [r7, #4] + 8005a98: 681b ldr r3, [r3, #0] + 8005a9a: 68db ldr r3, [r3, #12] + 8005a9c: 613b str r3, [r7, #16] #endif /* ADC_MULTIMODE_SUPPORT */ /* Carry on if continuous mode is disabled */ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) - 8004e0a: 693b ldr r3, [r7, #16] - 8004e0c: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8004e10: 2b00 cmp r3, #0 - 8004e12: d135 bne.n 8004e80 + 8005a9e: 693b ldr r3, [r7, #16] + 8005aa0: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8005aa4: 2b00 cmp r3, #0 + 8005aa6: d135 bne.n 8005b14 { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - 8004e14: 687b ldr r3, [r7, #4] - 8004e16: 681b ldr r3, [r3, #0] - 8004e18: 681b ldr r3, [r3, #0] - 8004e1a: f003 0308 and.w r3, r3, #8 - 8004e1e: 2b08 cmp r3, #8 - 8004e20: d12e bne.n 8004e80 + 8005aa8: 687b ldr r3, [r7, #4] + 8005aaa: 681b ldr r3, [r3, #0] + 8005aac: 681b ldr r3, [r3, #0] + 8005aae: f003 0308 and.w r3, r3, #8 + 8005ab2: 2b08 cmp r3, #8 + 8005ab4: d12e bne.n 8005b14 { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 8004e22: 687b ldr r3, [r7, #4] - 8004e24: 681b ldr r3, [r3, #0] - 8004e26: 4618 mov r0, r3 - 8004e28: f7ff fdab bl 8004982 - 8004e2c: 4603 mov r3, r0 - 8004e2e: 2b00 cmp r3, #0 - 8004e30: d11a bne.n 8004e68 + 8005ab6: 687b ldr r3, [r7, #4] + 8005ab8: 681b ldr r3, [r3, #0] + 8005aba: 4618 mov r0, r3 + 8005abc: f7ff fdab bl 8005616 + 8005ac0: 4603 mov r3, r0 + 8005ac2: 2b00 cmp r3, #0 + 8005ac4: d11a bne.n 8005afc { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - 8004e32: 687b ldr r3, [r7, #4] - 8004e34: 681b ldr r3, [r3, #0] - 8004e36: 685a ldr r2, [r3, #4] - 8004e38: 687b ldr r3, [r7, #4] - 8004e3a: 681b ldr r3, [r3, #0] - 8004e3c: f022 020c bic.w r2, r2, #12 - 8004e40: 605a str r2, [r3, #4] + 8005ac6: 687b ldr r3, [r7, #4] + 8005ac8: 681b ldr r3, [r3, #0] + 8005aca: 685a ldr r2, [r3, #4] + 8005acc: 687b ldr r3, [r7, #4] + 8005ace: 681b ldr r3, [r3, #0] + 8005ad0: f022 020c bic.w r2, r2, #12 + 8005ad4: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 8004e42: 687b ldr r3, [r7, #4] - 8004e44: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004e46: f423 7280 bic.w r2, r3, #256 ; 0x100 - 8004e4a: 687b ldr r3, [r7, #4] - 8004e4c: 655a str r2, [r3, #84] ; 0x54 + 8005ad6: 687b ldr r3, [r7, #4] + 8005ad8: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005ada: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8005ade: 687b ldr r3, [r7, #4] + 8005ae0: 655a str r2, [r3, #84] ; 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - 8004e4e: 687b ldr r3, [r7, #4] - 8004e50: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004e52: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8004e56: 2b00 cmp r3, #0 - 8004e58: d112 bne.n 8004e80 + 8005ae2: 687b ldr r3, [r7, #4] + 8005ae4: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005ae6: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8005aea: 2b00 cmp r3, #0 + 8005aec: d112 bne.n 8005b14 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8004e5a: 687b ldr r3, [r7, #4] - 8004e5c: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004e5e: f043 0201 orr.w r2, r3, #1 - 8004e62: 687b ldr r3, [r7, #4] - 8004e64: 655a str r2, [r3, #84] ; 0x54 - 8004e66: e00b b.n 8004e80 + 8005aee: 687b ldr r3, [r7, #4] + 8005af0: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005af2: f043 0201 orr.w r2, r3, #1 + 8005af6: 687b ldr r3, [r7, #4] + 8005af8: 655a str r2, [r3, #84] ; 0x54 + 8005afa: e00b b.n 8005b14 } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8004e68: 687b ldr r3, [r7, #4] - 8004e6a: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004e6c: f043 0210 orr.w r2, r3, #16 - 8004e70: 687b ldr r3, [r7, #4] - 8004e72: 655a str r2, [r3, #84] ; 0x54 + 8005afc: 687b ldr r3, [r7, #4] + 8005afe: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005b00: f043 0210 orr.w r2, r3, #16 + 8005b04: 687b ldr r3, [r7, #4] + 8005b06: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8004e74: 687b ldr r3, [r7, #4] - 8004e76: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004e78: f043 0201 orr.w r2, r3, #1 - 8004e7c: 687b ldr r3, [r7, #4] - 8004e7e: 659a str r2, [r3, #88] ; 0x58 + 8005b08: 687b ldr r3, [r7, #4] + 8005b0a: 6d9b ldr r3, [r3, #88] ; 0x58 + 8005b0c: f043 0201 orr.w r2, r3, #1 + 8005b10: 687b ldr r3, [r7, #4] + 8005b12: 659a str r2, [r3, #88] ; 0x58 /* possibility to use: */ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); - 8004e80: 6878 ldr r0, [r7, #4] - 8004e82: f7fc f945 bl 8001110 + 8005b14: 6878 ldr r0, [r7, #4] + 8005b16: f7fb fb67 bl 80011e8 /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - 8004e86: 687b ldr r3, [r7, #4] - 8004e88: 681b ldr r3, [r3, #0] - 8004e8a: 220c movs r2, #12 - 8004e8c: 601a str r2, [r3, #0] + 8005b1a: 687b ldr r3, [r7, #4] + 8005b1c: 681b ldr r3, [r3, #0] + 8005b1e: 220c movs r2, #12 + 8005b20: 601a str r2, [r3, #0] } /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 8004e8e: 69bb ldr r3, [r7, #24] - 8004e90: f003 0320 and.w r3, r3, #32 - 8004e94: 2b00 cmp r3, #0 - 8004e96: d004 beq.n 8004ea2 - 8004e98: 697b ldr r3, [r7, #20] - 8004e9a: f003 0320 and.w r3, r3, #32 - 8004e9e: 2b00 cmp r3, #0 - 8004ea0: d109 bne.n 8004eb6 + 8005b22: 69bb ldr r3, [r7, #24] + 8005b24: f003 0320 and.w r3, r3, #32 + 8005b28: 2b00 cmp r3, #0 + 8005b2a: d004 beq.n 8005b36 + 8005b2c: 697b ldr r3, [r7, #20] + 8005b2e: f003 0320 and.w r3, r3, #32 + 8005b32: 2b00 cmp r3, #0 + 8005b34: d109 bne.n 8005b4a (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) - 8004ea2: 69bb ldr r3, [r7, #24] - 8004ea4: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005b36: 69bb ldr r3, [r7, #24] + 8005b38: f003 0340 and.w r3, r3, #64 ; 0x40 if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - 8004ea8: 2b00 cmp r3, #0 - 8004eaa: d072 beq.n 8004f92 + 8005b3c: 2b00 cmp r3, #0 + 8005b3e: d072 beq.n 8005c26 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) - 8004eac: 697b ldr r3, [r7, #20] - 8004eae: f003 0340 and.w r3, r3, #64 ; 0x40 - 8004eb2: 2b00 cmp r3, #0 - 8004eb4: d06d beq.n 8004f92 + 8005b40: 697b ldr r3, [r7, #20] + 8005b42: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005b46: 2b00 cmp r3, #0 + 8005b48: d06d beq.n 8005c26 { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 8004eb6: 687b ldr r3, [r7, #4] - 8004eb8: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004eba: f003 0310 and.w r3, r3, #16 - 8004ebe: 2b00 cmp r3, #0 - 8004ec0: d105 bne.n 8004ece + 8005b4a: 687b ldr r3, [r7, #4] + 8005b4c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005b4e: f003 0310 and.w r3, r3, #16 + 8005b52: 2b00 cmp r3, #0 + 8005b54: d105 bne.n 8005b62 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - 8004ec2: 687b ldr r3, [r7, #4] - 8004ec4: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004ec6: f443 5200 orr.w r2, r3, #8192 ; 0x2000 - 8004eca: 687b ldr r3, [r7, #4] - 8004ecc: 655a str r2, [r3, #84] ; 0x54 + 8005b56: 687b ldr r3, [r7, #4] + 8005b58: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005b5a: f443 5200 orr.w r2, r3, #8192 ; 0x2000 + 8005b5e: 687b ldr r3, [r7, #4] + 8005b60: 655a str r2, [r3, #84] ; 0x54 } /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); - 8004ece: 687b ldr r3, [r7, #4] - 8004ed0: 681b ldr r3, [r3, #0] - 8004ed2: 4618 mov r0, r3 - 8004ed4: f7ff fc6a bl 80047ac - 8004ed8: 60f8 str r0, [r7, #12] + 8005b62: 687b ldr r3, [r7, #4] + 8005b64: 681b ldr r3, [r3, #0] + 8005b66: 4618 mov r0, r3 + 8005b68: f7ff fc6a bl 8005440 + 8005b6c: 60f8 str r0, [r7, #12] tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); - 8004eda: 687b ldr r3, [r7, #4] - 8004edc: 681b ldr r3, [r3, #0] - 8004ede: 4618 mov r0, r3 - 8004ee0: f7ff fc25 bl 800472e - 8004ee4: 60b8 str r0, [r7, #8] + 8005b6e: 687b ldr r3, [r7, #4] + 8005b70: 681b ldr r3, [r3, #0] + 8005b72: 4618 mov r0, r3 + 8005b74: f7ff fc25 bl 80053c2 + 8005b78: 60b8 str r0, [r7, #8] { tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 8004ee6: 687b ldr r3, [r7, #4] - 8004ee8: 681b ldr r3, [r3, #0] - 8004eea: 68db ldr r3, [r3, #12] - 8004eec: 613b str r3, [r7, #16] + 8005b7a: 687b ldr r3, [r7, #4] + 8005b7c: 681b ldr r3, [r3, #0] + 8005b7e: 68db ldr r3, [r3, #12] + 8005b80: 613b str r3, [r7, #16] /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) - 8004eee: 68fb ldr r3, [r7, #12] - 8004ef0: 2b00 cmp r3, #0 - 8004ef2: d047 beq.n 8004f84 + 8005b82: 68fb ldr r3, [r7, #12] + 8005b84: 2b00 cmp r3, #0 + 8005b86: d047 beq.n 8005c18 { if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || - 8004ef4: 693b ldr r3, [r7, #16] - 8004ef6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8004efa: 2b00 cmp r3, #0 - 8004efc: d007 beq.n 8004f0e - 8004efe: 68bb ldr r3, [r7, #8] - 8004f00: 2b00 cmp r3, #0 - 8004f02: d03f beq.n 8004f84 + 8005b88: 693b ldr r3, [r7, #16] + 8005b8a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8005b8e: 2b00 cmp r3, #0 + 8005b90: d007 beq.n 8005ba2 + 8005b92: 68bb ldr r3, [r7, #8] + 8005b94: 2b00 cmp r3, #0 + 8005b96: d03f beq.n 8005c18 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) - 8004f04: 693b ldr r3, [r7, #16] - 8004f06: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8005b98: 693b ldr r3, [r7, #16] + 8005b9a: f403 5300 and.w r3, r3, #8192 ; 0x2000 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - 8004f0a: 2b00 cmp r3, #0 - 8004f0c: d13a bne.n 8004f84 + 8005b9e: 2b00 cmp r3, #0 + 8005ba0: d13a bne.n 8005c18 { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) - 8004f0e: 687b ldr r3, [r7, #4] - 8004f10: 681b ldr r3, [r3, #0] - 8004f12: 681b ldr r3, [r3, #0] - 8004f14: f003 0340 and.w r3, r3, #64 ; 0x40 - 8004f18: 2b40 cmp r3, #64 ; 0x40 - 8004f1a: d133 bne.n 8004f84 + 8005ba2: 687b ldr r3, [r7, #4] + 8005ba4: 681b ldr r3, [r3, #0] + 8005ba6: 681b ldr r3, [r3, #0] + 8005ba8: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005bac: 2b40 cmp r3, #64 ; 0x40 + 8005bae: d133 bne.n 8005c18 /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) - 8004f1c: 693b ldr r3, [r7, #16] - 8004f1e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8004f22: 2b00 cmp r3, #0 - 8004f24: d12e bne.n 8004f84 + 8005bb0: 693b ldr r3, [r7, #16] + 8005bb2: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8005bb6: 2b00 cmp r3, #0 + 8005bb8: d12e bne.n 8005c18 { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - 8004f26: 687b ldr r3, [r7, #4] - 8004f28: 681b ldr r3, [r3, #0] - 8004f2a: 4618 mov r0, r3 - 8004f2c: f7ff fd3c bl 80049a8 - 8004f30: 4603 mov r3, r0 - 8004f32: 2b00 cmp r3, #0 - 8004f34: d11a bne.n 8004f6c + 8005bba: 687b ldr r3, [r7, #4] + 8005bbc: 681b ldr r3, [r3, #0] + 8005bbe: 4618 mov r0, r3 + 8005bc0: f7ff fd3c bl 800563c + 8005bc4: 4603 mov r3, r0 + 8005bc6: 2b00 cmp r3, #0 + 8005bc8: d11a bne.n 8005c00 { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - 8004f36: 687b ldr r3, [r7, #4] - 8004f38: 681b ldr r3, [r3, #0] - 8004f3a: 685a ldr r2, [r3, #4] - 8004f3c: 687b ldr r3, [r7, #4] - 8004f3e: 681b ldr r3, [r3, #0] - 8004f40: f022 0260 bic.w r2, r2, #96 ; 0x60 - 8004f44: 605a str r2, [r3, #4] + 8005bca: 687b ldr r3, [r7, #4] + 8005bcc: 681b ldr r3, [r3, #0] + 8005bce: 685a ldr r2, [r3, #4] + 8005bd0: 687b ldr r3, [r7, #4] + 8005bd2: 681b ldr r3, [r3, #0] + 8005bd4: f022 0260 bic.w r2, r2, #96 ; 0x60 + 8005bd8: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - 8004f46: 687b ldr r3, [r7, #4] - 8004f48: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004f4a: f423 5280 bic.w r2, r3, #4096 ; 0x1000 - 8004f4e: 687b ldr r3, [r7, #4] - 8004f50: 655a str r2, [r3, #84] ; 0x54 + 8005bda: 687b ldr r3, [r7, #4] + 8005bdc: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005bde: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 8005be2: 687b ldr r3, [r7, #4] + 8005be4: 655a str r2, [r3, #84] ; 0x54 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - 8004f52: 687b ldr r3, [r7, #4] - 8004f54: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004f56: f403 7380 and.w r3, r3, #256 ; 0x100 - 8004f5a: 2b00 cmp r3, #0 - 8004f5c: d112 bne.n 8004f84 + 8005be6: 687b ldr r3, [r7, #4] + 8005be8: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005bea: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005bee: 2b00 cmp r3, #0 + 8005bf0: d112 bne.n 8005c18 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8004f5e: 687b ldr r3, [r7, #4] - 8004f60: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004f62: f043 0201 orr.w r2, r3, #1 - 8004f66: 687b ldr r3, [r7, #4] - 8004f68: 655a str r2, [r3, #84] ; 0x54 - 8004f6a: e00b b.n 8004f84 + 8005bf2: 687b ldr r3, [r7, #4] + 8005bf4: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005bf6: f043 0201 orr.w r2, r3, #1 + 8005bfa: 687b ldr r3, [r7, #4] + 8005bfc: 655a str r2, [r3, #84] ; 0x54 + 8005bfe: e00b b.n 8005c18 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8004f6c: 687b ldr r3, [r7, #4] - 8004f6e: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004f70: f043 0210 orr.w r2, r3, #16 - 8004f74: 687b ldr r3, [r7, #4] - 8004f76: 655a str r2, [r3, #84] ; 0x54 + 8005c00: 687b ldr r3, [r7, #4] + 8005c02: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005c04: f043 0210 orr.w r2, r3, #16 + 8005c08: 687b ldr r3, [r7, #4] + 8005c0a: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8004f78: 687b ldr r3, [r7, #4] - 8004f7a: 6d9b ldr r3, [r3, #88] ; 0x58 - 8004f7c: f043 0201 orr.w r2, r3, #1 - 8004f80: 687b ldr r3, [r7, #4] - 8004f82: 659a str r2, [r3, #88] ; 0x58 + 8005c0c: 687b ldr r3, [r7, #4] + 8005c0e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8005c10: f043 0201 orr.w r2, r3, #1 + 8005c14: 687b ldr r3, [r7, #4] + 8005c16: 659a str r2, [r3, #88] ; 0x58 interruption has been triggered by end of conversion or end of sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); - 8004f84: 6878 ldr r0, [r7, #4] - 8004f86: f000 fdb7 bl 8005af8 + 8005c18: 6878 ldr r0, [r7, #4] + 8005c1a: f000 fdb7 bl 800678c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); - 8004f8a: 687b ldr r3, [r7, #4] - 8004f8c: 681b ldr r3, [r3, #0] - 8004f8e: 2260 movs r2, #96 ; 0x60 - 8004f90: 601a str r2, [r3, #0] + 8005c1e: 687b ldr r3, [r7, #4] + 8005c20: 681b ldr r3, [r3, #0] + 8005c22: 2260 movs r2, #96 ; 0x60 + 8005c24: 601a str r2, [r3, #0] } /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) - 8004f92: 69bb ldr r3, [r7, #24] - 8004f94: f003 0380 and.w r3, r3, #128 ; 0x80 - 8004f98: 2b00 cmp r3, #0 - 8004f9a: d011 beq.n 8004fc0 - 8004f9c: 697b ldr r3, [r7, #20] - 8004f9e: f003 0380 and.w r3, r3, #128 ; 0x80 - 8004fa2: 2b00 cmp r3, #0 - 8004fa4: d00c beq.n 8004fc0 + 8005c26: 69bb ldr r3, [r7, #24] + 8005c28: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005c2c: 2b00 cmp r3, #0 + 8005c2e: d011 beq.n 8005c54 + 8005c30: 697b ldr r3, [r7, #20] + 8005c32: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005c36: 2b00 cmp r3, #0 + 8005c38: d00c beq.n 8005c54 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - 8004fa6: 687b ldr r3, [r7, #4] - 8004fa8: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004faa: f443 3280 orr.w r2, r3, #65536 ; 0x10000 - 8004fae: 687b ldr r3, [r7, #4] - 8004fb0: 655a str r2, [r3, #84] ; 0x54 + 8005c3a: 687b ldr r3, [r7, #4] + 8005c3c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005c3e: f443 3280 orr.w r2, r3, #65536 ; 0x10000 + 8005c42: 687b ldr r3, [r7, #4] + 8005c44: 655a str r2, [r3, #84] ; 0x54 /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); - 8004fb2: 6878 ldr r0, [r7, #4] - 8004fb4: f000 f890 bl 80050d8 + 8005c46: 6878 ldr r0, [r7, #4] + 8005c48: f000 f890 bl 8005d6c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - 8004fb8: 687b ldr r3, [r7, #4] - 8004fba: 681b ldr r3, [r3, #0] - 8004fbc: 2280 movs r2, #128 ; 0x80 - 8004fbe: 601a str r2, [r3, #0] + 8005c4c: 687b ldr r3, [r7, #4] + 8005c4e: 681b ldr r3, [r3, #0] + 8005c50: 2280 movs r2, #128 ; 0x80 + 8005c52: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 2 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) - 8004fc0: 69bb ldr r3, [r7, #24] - 8004fc2: f403 7380 and.w r3, r3, #256 ; 0x100 - 8004fc6: 2b00 cmp r3, #0 - 8004fc8: d012 beq.n 8004ff0 - 8004fca: 697b ldr r3, [r7, #20] - 8004fcc: f403 7380 and.w r3, r3, #256 ; 0x100 - 8004fd0: 2b00 cmp r3, #0 - 8004fd2: d00d beq.n 8004ff0 + 8005c54: 69bb ldr r3, [r7, #24] + 8005c56: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005c5a: 2b00 cmp r3, #0 + 8005c5c: d012 beq.n 8005c84 + 8005c5e: 697b ldr r3, [r7, #20] + 8005c60: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005c64: 2b00 cmp r3, #0 + 8005c66: d00d beq.n 8005c84 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - 8004fd4: 687b ldr r3, [r7, #4] - 8004fd6: 6d5b ldr r3, [r3, #84] ; 0x54 - 8004fd8: f443 3200 orr.w r2, r3, #131072 ; 0x20000 - 8004fdc: 687b ldr r3, [r7, #4] - 8004fde: 655a str r2, [r3, #84] ; 0x54 + 8005c68: 687b ldr r3, [r7, #4] + 8005c6a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005c6c: f443 3200 orr.w r2, r3, #131072 ; 0x20000 + 8005c70: 687b ldr r3, [r7, #4] + 8005c72: 655a str r2, [r3, #84] ; 0x54 /* Level out of window 2 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow2Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); - 8004fe0: 6878 ldr r0, [r7, #4] - 8004fe2: f000 fd9d bl 8005b20 + 8005c74: 6878 ldr r0, [r7, #4] + 8005c76: f000 fd9d bl 80067b4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - 8004fe6: 687b ldr r3, [r7, #4] - 8004fe8: 681b ldr r3, [r3, #0] - 8004fea: f44f 7280 mov.w r2, #256 ; 0x100 - 8004fee: 601a str r2, [r3, #0] + 8005c7a: 687b ldr r3, [r7, #4] + 8005c7c: 681b ldr r3, [r3, #0] + 8005c7e: f44f 7280 mov.w r2, #256 ; 0x100 + 8005c82: 601a str r2, [r3, #0] } /* ========== Check analog watchdog 3 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) - 8004ff0: 69bb ldr r3, [r7, #24] - 8004ff2: f403 7300 and.w r3, r3, #512 ; 0x200 - 8004ff6: 2b00 cmp r3, #0 - 8004ff8: d012 beq.n 8005020 - 8004ffa: 697b ldr r3, [r7, #20] - 8004ffc: f403 7300 and.w r3, r3, #512 ; 0x200 - 8005000: 2b00 cmp r3, #0 - 8005002: d00d beq.n 8005020 + 8005c84: 69bb ldr r3, [r7, #24] + 8005c86: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005c8a: 2b00 cmp r3, #0 + 8005c8c: d012 beq.n 8005cb4 + 8005c8e: 697b ldr r3, [r7, #20] + 8005c90: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005c94: 2b00 cmp r3, #0 + 8005c96: d00d beq.n 8005cb4 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - 8005004: 687b ldr r3, [r7, #4] - 8005006: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005008: f443 2280 orr.w r2, r3, #262144 ; 0x40000 - 800500c: 687b ldr r3, [r7, #4] - 800500e: 655a str r2, [r3, #84] ; 0x54 + 8005c98: 687b ldr r3, [r7, #4] + 8005c9a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005c9c: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 8005ca0: 687b ldr r3, [r7, #4] + 8005ca2: 655a str r2, [r3, #84] ; 0x54 /* Level out of window 3 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow3Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); - 8005010: 6878 ldr r0, [r7, #4] - 8005012: f000 fd8f bl 8005b34 + 8005ca4: 6878 ldr r0, [r7, #4] + 8005ca6: f000 fd8f bl 80067c8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - 8005016: 687b ldr r3, [r7, #4] - 8005018: 681b ldr r3, [r3, #0] - 800501a: f44f 7200 mov.w r2, #512 ; 0x200 - 800501e: 601a str r2, [r3, #0] + 8005caa: 687b ldr r3, [r7, #4] + 8005cac: 681b ldr r3, [r3, #0] + 8005cae: f44f 7200 mov.w r2, #512 ; 0x200 + 8005cb2: 601a str r2, [r3, #0] } /* ========== Check Overrun flag ========== */ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) - 8005020: 69bb ldr r3, [r7, #24] - 8005022: f003 0310 and.w r3, r3, #16 - 8005026: 2b00 cmp r3, #0 - 8005028: d02a beq.n 8005080 - 800502a: 697b ldr r3, [r7, #20] - 800502c: f003 0310 and.w r3, r3, #16 - 8005030: 2b00 cmp r3, #0 - 8005032: d025 beq.n 8005080 + 8005cb4: 69bb ldr r3, [r7, #24] + 8005cb6: f003 0310 and.w r3, r3, #16 + 8005cba: 2b00 cmp r3, #0 + 8005cbc: d02a beq.n 8005d14 + 8005cbe: 697b ldr r3, [r7, #20] + 8005cc0: f003 0310 and.w r3, r3, #16 + 8005cc4: 2b00 cmp r3, #0 + 8005cc6: d025 beq.n 8005d14 /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - 8005034: 687b ldr r3, [r7, #4] - 8005036: 6b5b ldr r3, [r3, #52] ; 0x34 - 8005038: 2b00 cmp r3, #0 - 800503a: d102 bne.n 8005042 + 8005cc8: 687b ldr r3, [r7, #4] + 8005cca: 6b5b ldr r3, [r3, #52] ; 0x34 + 8005ccc: 2b00 cmp r3, #0 + 8005cce: d102 bne.n 8005cd6 { overrun_error = 1UL; - 800503c: 2301 movs r3, #1 - 800503e: 61fb str r3, [r7, #28] - 8005040: e008 b.n 8005054 + 8005cd0: 2301 movs r3, #1 + 8005cd2: 61fb str r3, [r7, #28] + 8005cd4: e008 b.n 8005ce8 } else #endif /* ADC_MULTIMODE_SUPPORT */ { /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) - 8005042: 687b ldr r3, [r7, #4] - 8005044: 681b ldr r3, [r3, #0] - 8005046: 68db ldr r3, [r3, #12] - 8005048: f003 0301 and.w r3, r3, #1 - 800504c: 2b00 cmp r3, #0 - 800504e: d001 beq.n 8005054 + 8005cd6: 687b ldr r3, [r7, #4] + 8005cd8: 681b ldr r3, [r3, #0] + 8005cda: 68db ldr r3, [r3, #12] + 8005cdc: f003 0301 and.w r3, r3, #1 + 8005ce0: 2b00 cmp r3, #0 + 8005ce2: d001 beq.n 8005ce8 { overrun_error = 1UL; - 8005050: 2301 movs r3, #1 - 8005052: 61fb str r3, [r7, #28] + 8005ce4: 2301 movs r3, #1 + 8005ce6: 61fb str r3, [r7, #28] } } } if (overrun_error == 1UL) - 8005054: 69fb ldr r3, [r7, #28] - 8005056: 2b01 cmp r3, #1 - 8005058: d10e bne.n 8005078 + 8005ce8: 69fb ldr r3, [r7, #28] + 8005cea: 2b01 cmp r3, #1 + 8005cec: d10e bne.n 8005d0c { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - 800505a: 687b ldr r3, [r7, #4] - 800505c: 6d5b ldr r3, [r3, #84] ; 0x54 - 800505e: f443 6280 orr.w r2, r3, #1024 ; 0x400 - 8005062: 687b ldr r3, [r7, #4] - 8005064: 655a str r2, [r3, #84] ; 0x54 + 8005cee: 687b ldr r3, [r7, #4] + 8005cf0: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005cf2: f443 6280 orr.w r2, r3, #1024 ; 0x400 + 8005cf6: 687b ldr r3, [r7, #4] + 8005cf8: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - 8005066: 687b ldr r3, [r7, #4] - 8005068: 6d9b ldr r3, [r3, #88] ; 0x58 - 800506a: f043 0202 orr.w r2, r3, #2 - 800506e: 687b ldr r3, [r7, #4] - 8005070: 659a str r2, [r3, #88] ; 0x58 + 8005cfa: 687b ldr r3, [r7, #4] + 8005cfc: 6d9b ldr r3, [r3, #88] ; 0x58 + 8005cfe: f043 0202 orr.w r2, r3, #2 + 8005d02: 687b ldr r3, [r7, #4] + 8005d04: 659a str r2, [r3, #88] ; 0x58 /* Therefore, old ADC conversion data can be retrieved in */ /* function "HAL_ADC_ErrorCallback()". */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); - 8005072: 6878 ldr r0, [r7, #4] - 8005074: f000 f83a bl 80050ec + 8005d06: 6878 ldr r0, [r7, #4] + 8005d08: f000 f83a bl 8005d80 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - 8005078: 687b ldr r3, [r7, #4] - 800507a: 681b ldr r3, [r3, #0] - 800507c: 2210 movs r2, #16 - 800507e: 601a str r2, [r3, #0] + 8005d0c: 687b ldr r3, [r7, #4] + 8005d0e: 681b ldr r3, [r3, #0] + 8005d10: 2210 movs r2, #16 + 8005d12: 601a str r2, [r3, #0] } /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) - 8005080: 69bb ldr r3, [r7, #24] - 8005082: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8005086: 2b00 cmp r3, #0 - 8005088: d018 beq.n 80050bc - 800508a: 697b ldr r3, [r7, #20] - 800508c: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8005090: 2b00 cmp r3, #0 - 8005092: d013 beq.n 80050bc + 8005d14: 69bb ldr r3, [r7, #24] + 8005d16: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8005d1a: 2b00 cmp r3, #0 + 8005d1c: d018 beq.n 8005d50 + 8005d1e: 697b ldr r3, [r7, #20] + 8005d20: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8005d24: 2b00 cmp r3, #0 + 8005d26: d013 beq.n 8005d50 { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - 8005094: 687b ldr r3, [r7, #4] - 8005096: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005098: f443 4280 orr.w r2, r3, #16384 ; 0x4000 - 800509c: 687b ldr r3, [r7, #4] - 800509e: 655a str r2, [r3, #84] ; 0x54 + 8005d28: 687b ldr r3, [r7, #4] + 8005d2a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005d2c: f443 4280 orr.w r2, r3, #16384 ; 0x4000 + 8005d30: 687b ldr r3, [r7, #4] + 8005d32: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - 80050a0: 687b ldr r3, [r7, #4] - 80050a2: 6d9b ldr r3, [r3, #88] ; 0x58 - 80050a4: f043 0208 orr.w r2, r3, #8 - 80050a8: 687b ldr r3, [r7, #4] - 80050aa: 659a str r2, [r3, #88] ; 0x58 + 8005d34: 687b ldr r3, [r7, #4] + 8005d36: 6d9b ldr r3, [r3, #88] ; 0x58 + 8005d38: f043 0208 orr.w r2, r3, #8 + 8005d3c: 687b ldr r3, [r7, #4] + 8005d3e: 659a str r2, [r3, #88] ; 0x58 /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - 80050ac: 687b ldr r3, [r7, #4] - 80050ae: 681b ldr r3, [r3, #0] - 80050b0: f44f 6280 mov.w r2, #1024 ; 0x400 - 80050b4: 601a str r2, [r3, #0] + 8005d40: 687b ldr r3, [r7, #4] + 8005d42: 681b ldr r3, [r3, #0] + 8005d44: f44f 6280 mov.w r2, #1024 ; 0x400 + 8005d48: 601a str r2, [r3, #0] /* Injected context queue overflow callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedQueueOverflowCallback(hadc); #else HAL_ADCEx_InjectedQueueOverflowCallback(hadc); - 80050b6: 6878 ldr r0, [r7, #4] - 80050b8: f000 fd28 bl 8005b0c + 8005d4a: 6878 ldr r0, [r7, #4] + 8005d4c: f000 fd28 bl 80067a0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } } - 80050bc: bf00 nop - 80050be: 3720 adds r7, #32 - 80050c0: 46bd mov sp, r7 - 80050c2: bd80 pop {r7, pc} + 8005d50: bf00 nop + 8005d52: 3720 adds r7, #32 + 8005d54: 46bd mov sp, r7 + 8005d56: bd80 pop {r7, pc} -080050c4 : +08005d58 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { - 80050c4: b480 push {r7} - 80050c6: b083 sub sp, #12 - 80050c8: af00 add r7, sp, #0 - 80050ca: 6078 str r0, [r7, #4] + 8005d58: b480 push {r7} + 8005d5a: b083 sub sp, #12 + 8005d5c: af00 add r7, sp, #0 + 8005d5e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } - 80050cc: bf00 nop - 80050ce: 370c adds r7, #12 - 80050d0: 46bd mov sp, r7 - 80050d2: f85d 7b04 ldr.w r7, [sp], #4 - 80050d6: 4770 bx lr + 8005d60: bf00 nop + 8005d62: 370c adds r7, #12 + 8005d64: 46bd mov sp, r7 + 8005d66: f85d 7b04 ldr.w r7, [sp], #4 + 8005d6a: 4770 bx lr -080050d8 : +08005d6c : * @brief Analog watchdog 1 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { - 80050d8: b480 push {r7} - 80050da: b083 sub sp, #12 - 80050dc: af00 add r7, sp, #0 - 80050de: 6078 str r0, [r7, #4] + 8005d6c: b480 push {r7} + 8005d6e: b083 sub sp, #12 + 8005d70: af00 add r7, sp, #0 + 8005d72: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } - 80050e0: bf00 nop - 80050e2: 370c adds r7, #12 - 80050e4: 46bd mov sp, r7 - 80050e6: f85d 7b04 ldr.w r7, [sp], #4 - 80050ea: 4770 bx lr + 8005d74: bf00 nop + 8005d76: 370c adds r7, #12 + 8005d78: 46bd mov sp, r7 + 8005d7a: f85d 7b04 ldr.w r7, [sp], #4 + 8005d7e: 4770 bx lr -080050ec : +08005d80 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { - 80050ec: b480 push {r7} - 80050ee: b083 sub sp, #12 - 80050f0: af00 add r7, sp, #0 - 80050f2: 6078 str r0, [r7, #4] + 8005d80: b480 push {r7} + 8005d82: b083 sub sp, #12 + 8005d84: af00 add r7, sp, #0 + 8005d86: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } - 80050f4: bf00 nop - 80050f6: 370c adds r7, #12 - 80050f8: 46bd mov sp, r7 - 80050fa: f85d 7b04 ldr.w r7, [sp], #4 - 80050fe: 4770 bx lr + 8005d88: bf00 nop + 8005d8a: 370c adds r7, #12 + 8005d8c: 46bd mov sp, r7 + 8005d8e: f85d 7b04 ldr.w r7, [sp], #4 + 8005d92: 4770 bx lr -08005100 : +08005d94 : * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { - 8005100: b580 push {r7, lr} - 8005102: b0b6 sub sp, #216 ; 0xd8 - 8005104: af00 add r7, sp, #0 - 8005106: 6078 str r0, [r7, #4] - 8005108: 6039 str r1, [r7, #0] + 8005d94: b580 push {r7, lr} + 8005d96: b0b6 sub sp, #216 ; 0xd8 + 8005d98: af00 add r7, sp, #0 + 8005d9a: 6078 str r0, [r7, #4] + 8005d9c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 800510a: 2300 movs r3, #0 - 800510c: f887 30d7 strb.w r3, [r7, #215] ; 0xd7 + 8005d9e: 2300 movs r3, #0 + 8005da0: f887 30d7 strb.w r3, [r7, #215] ; 0xd7 uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; - 8005110: 2300 movs r3, #0 - 8005112: 60bb str r3, [r7, #8] + 8005da4: 2300 movs r3, #0 + 8005da6: 60bb str r3, [r7, #8] { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); - 8005114: 687b ldr r3, [r7, #4] - 8005116: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 - 800511a: 2b01 cmp r3, #1 - 800511c: d101 bne.n 8005122 - 800511e: 2302 movs r3, #2 - 8005120: e3bb b.n 800589a - 8005122: 687b ldr r3, [r7, #4] - 8005124: 2201 movs r2, #1 - 8005126: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 8005da8: 687b ldr r3, [r7, #4] + 8005daa: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 8005dae: 2b01 cmp r3, #1 + 8005db0: d101 bne.n 8005db6 + 8005db2: 2302 movs r3, #2 + 8005db4: e3bb b.n 800652e + 8005db6: 687b ldr r3, [r7, #4] + 8005db8: 2201 movs r2, #1 + 8005dba: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 800512a: 687b ldr r3, [r7, #4] - 800512c: 681b ldr r3, [r3, #0] - 800512e: 4618 mov r0, r3 - 8005130: f7ff fc27 bl 8004982 - 8005134: 4603 mov r3, r0 - 8005136: 2b00 cmp r3, #0 - 8005138: f040 83a0 bne.w 800587c + 8005dbe: 687b ldr r3, [r7, #4] + 8005dc0: 681b ldr r3, [r3, #0] + 8005dc2: 4618 mov r0, r3 + 8005dc4: f7ff fc27 bl 8005616 + 8005dc8: 4603 mov r3, r0 + 8005dca: 2b00 cmp r3, #0 + 8005dcc: f040 83a0 bne.w 8006510 { #if !defined (USE_FULL_ASSERT) uint32_t config_rank = pConfig->Rank; - 800513c: 683b ldr r3, [r7, #0] - 800513e: 685b ldr r3, [r3, #4] - 8005140: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005dd0: 683b ldr r3, [r7, #0] + 8005dd2: 685b ldr r3, [r3, #4] + 8005dd4: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 /* Correspondence for compatibility with legacy definition of */ /* sequencer ranks in direct number format. This correspondence can */ /* be done only on ranks 1 to 5 due to literal values. */ /* Note: Sequencer ranks in direct number format are no more used */ /* and are detected by activating USE_FULL_ASSERT feature. */ if (pConfig->Rank <= 5U) - 8005144: 683b ldr r3, [r7, #0] - 8005146: 685b ldr r3, [r3, #4] - 8005148: 2b05 cmp r3, #5 - 800514a: d824 bhi.n 8005196 + 8005dd8: 683b ldr r3, [r7, #0] + 8005dda: 685b ldr r3, [r3, #4] + 8005ddc: 2b05 cmp r3, #5 + 8005dde: d824 bhi.n 8005e2a { switch (pConfig->Rank) - 800514c: 683b ldr r3, [r7, #0] - 800514e: 685b ldr r3, [r3, #4] - 8005150: 3b02 subs r3, #2 - 8005152: 2b03 cmp r3, #3 - 8005154: d81b bhi.n 800518e - 8005156: a201 add r2, pc, #4 ; (adr r2, 800515c ) - 8005158: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800515c: 0800516d .word 0x0800516d - 8005160: 08005175 .word 0x08005175 - 8005164: 0800517d .word 0x0800517d - 8005168: 08005185 .word 0x08005185 + 8005de0: 683b ldr r3, [r7, #0] + 8005de2: 685b ldr r3, [r3, #4] + 8005de4: 3b02 subs r3, #2 + 8005de6: 2b03 cmp r3, #3 + 8005de8: d81b bhi.n 8005e22 + 8005dea: a201 add r2, pc, #4 ; (adr r2, 8005df0 ) + 8005dec: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005df0: 08005e01 .word 0x08005e01 + 8005df4: 08005e09 .word 0x08005e09 + 8005df8: 08005e11 .word 0x08005e11 + 8005dfc: 08005e19 .word 0x08005e19 { case 2U: config_rank = ADC_REGULAR_RANK_2; - 800516c: 230c movs r3, #12 - 800516e: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005e00: 230c movs r3, #12 + 8005e02: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 break; - 8005172: e010 b.n 8005196 + 8005e06: e010 b.n 8005e2a case 3U: config_rank = ADC_REGULAR_RANK_3; - 8005174: 2312 movs r3, #18 - 8005176: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005e08: 2312 movs r3, #18 + 8005e0a: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 break; - 800517a: e00c b.n 8005196 + 8005e0e: e00c b.n 8005e2a case 4U: config_rank = ADC_REGULAR_RANK_4; - 800517c: 2318 movs r3, #24 - 800517e: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005e10: 2318 movs r3, #24 + 8005e12: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 break; - 8005182: e008 b.n 8005196 + 8005e16: e008 b.n 8005e2a case 5U: config_rank = ADC_REGULAR_RANK_5; - 8005184: f44f 7380 mov.w r3, #256 ; 0x100 - 8005188: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005e18: f44f 7380 mov.w r3, #256 ; 0x100 + 8005e1c: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 break; - 800518c: e003 b.n 8005196 + 8005e20: e003 b.n 8005e2a /* case 1U */ default: config_rank = ADC_REGULAR_RANK_1; - 800518e: 2306 movs r3, #6 - 8005190: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8005e22: 2306 movs r3, #6 + 8005e24: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 break; - 8005194: bf00 nop + 8005e28: bf00 nop } } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, config_rank, pConfig->Channel); - 8005196: 687b ldr r3, [r7, #4] - 8005198: 6818 ldr r0, [r3, #0] - 800519a: 683b ldr r3, [r7, #0] - 800519c: 681b ldr r3, [r3, #0] - 800519e: 461a mov r2, r3 - 80051a0: f8d7 10d0 ldr.w r1, [r7, #208] ; 0xd0 - 80051a4: f7ff fad6 bl 8004754 + 8005e2a: 687b ldr r3, [r7, #4] + 8005e2c: 6818 ldr r0, [r3, #0] + 8005e2e: 683b ldr r3, [r7, #0] + 8005e30: 681b ldr r3, [r3, #0] + 8005e32: 461a mov r2, r3 + 8005e34: f8d7 10d0 ldr.w r1, [r7, #208] ; 0xd0 + 8005e38: f7ff fad6 bl 80053e8 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 80051a8: 687b ldr r3, [r7, #4] - 80051aa: 681b ldr r3, [r3, #0] - 80051ac: 4618 mov r0, r3 - 80051ae: f7ff fbe8 bl 8004982 - 80051b2: f8c7 00cc str.w r0, [r7, #204] ; 0xcc + 8005e3c: 687b ldr r3, [r7, #4] + 8005e3e: 681b ldr r3, [r3, #0] + 8005e40: 4618 mov r0, r3 + 8005e42: f7ff fbe8 bl 8005616 + 8005e46: f8c7 00cc str.w r0, [r7, #204] ; 0xcc tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - 80051b6: 687b ldr r3, [r7, #4] - 80051b8: 681b ldr r3, [r3, #0] - 80051ba: 4618 mov r0, r3 - 80051bc: f7ff fbf4 bl 80049a8 - 80051c0: f8c7 00c8 str.w r0, [r7, #200] ; 0xc8 + 8005e4a: 687b ldr r3, [r7, #4] + 8005e4c: 681b ldr r3, [r3, #0] + 8005e4e: 4618 mov r0, r3 + 8005e50: f7ff fbf4 bl 800563c + 8005e54: f8c7 00c8 str.w r0, [r7, #200] ; 0xc8 if ((tmp_adc_is_conversion_on_going_regular == 0UL) - 80051c4: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 80051c8: 2b00 cmp r3, #0 - 80051ca: f040 81a4 bne.w 8005516 + 8005e58: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 8005e5c: 2b00 cmp r3, #0 + 8005e5e: f040 81a4 bne.w 80061aa && (tmp_adc_is_conversion_on_going_injected == 0UL) - 80051ce: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 80051d2: 2b00 cmp r3, #0 - 80051d4: f040 819f bne.w 8005516 + 8005e62: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8005e66: 2b00 cmp r3, #0 + 8005e68: f040 819f bne.w 80061aa /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } #else /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); - 80051d8: 687b ldr r3, [r7, #4] - 80051da: 6818 ldr r0, [r3, #0] - 80051dc: 683b ldr r3, [r7, #0] - 80051de: 6819 ldr r1, [r3, #0] - 80051e0: 683b ldr r3, [r7, #0] - 80051e2: 689b ldr r3, [r3, #8] - 80051e4: 461a mov r2, r3 - 80051e6: f7ff faf4 bl 80047d2 + 8005e6c: 687b ldr r3, [r7, #4] + 8005e6e: 6818 ldr r0, [r3, #0] + 8005e70: 683b ldr r3, [r7, #0] + 8005e72: 6819 ldr r1, [r3, #0] + 8005e74: 683b ldr r3, [r7, #0] + 8005e76: 689b ldr r3, [r3, #8] + 8005e78: 461a mov r2, r3 + 8005e7a: f7ff faf4 bl 8005466 /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); - 80051ea: 683b ldr r3, [r7, #0] - 80051ec: 695a ldr r2, [r3, #20] - 80051ee: 687b ldr r3, [r7, #4] - 80051f0: 681b ldr r3, [r3, #0] - 80051f2: 68db ldr r3, [r3, #12] - 80051f4: 08db lsrs r3, r3, #3 - 80051f6: f003 0303 and.w r3, r3, #3 - 80051fa: 005b lsls r3, r3, #1 - 80051fc: fa02 f303 lsl.w r3, r2, r3 - 8005200: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 8005e7e: 683b ldr r3, [r7, #0] + 8005e80: 695a ldr r2, [r3, #20] + 8005e82: 687b ldr r3, [r7, #4] + 8005e84: 681b ldr r3, [r3, #0] + 8005e86: 68db ldr r3, [r3, #12] + 8005e88: 08db lsrs r3, r3, #3 + 8005e8a: f003 0303 and.w r3, r3, #3 + 8005e8e: 005b lsls r3, r3, #1 + 8005e90: fa02 f303 lsl.w r3, r2, r3 + 8005e94: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 if (pConfig->OffsetNumber != ADC_OFFSET_NONE) - 8005204: 683b ldr r3, [r7, #0] - 8005206: 691b ldr r3, [r3, #16] - 8005208: 2b04 cmp r3, #4 - 800520a: d00a beq.n 8005222 + 8005e98: 683b ldr r3, [r7, #0] + 8005e9a: 691b ldr r3, [r3, #16] + 8005e9c: 2b04 cmp r3, #4 + 8005e9e: d00a beq.n 8005eb6 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); - 800520c: 687b ldr r3, [r7, #4] - 800520e: 6818 ldr r0, [r3, #0] - 8005210: 683b ldr r3, [r7, #0] - 8005212: 6919 ldr r1, [r3, #16] - 8005214: 683b ldr r3, [r7, #0] - 8005216: 681a ldr r2, [r3, #0] - 8005218: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 800521c: f7ff fa32 bl 8004684 - 8005220: e179 b.n 8005516 + 8005ea0: 687b ldr r3, [r7, #4] + 8005ea2: 6818 ldr r0, [r3, #0] + 8005ea4: 683b ldr r3, [r7, #0] + 8005ea6: 6919 ldr r1, [r3, #16] + 8005ea8: 683b ldr r3, [r7, #0] + 8005eaa: 681a ldr r2, [r3, #0] + 8005eac: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 8005eb0: f7ff fa32 bl 8005318 + 8005eb4: e179 b.n 80061aa } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - 8005222: 687b ldr r3, [r7, #4] - 8005224: 681b ldr r3, [r3, #0] - 8005226: 2100 movs r1, #0 - 8005228: 4618 mov r0, r3 - 800522a: f7ff fa4f bl 80046cc - 800522e: 4603 mov r3, r0 - 8005230: f3c3 0312 ubfx r3, r3, #0, #19 - 8005234: 2b00 cmp r3, #0 - 8005236: d10a bne.n 800524e - 8005238: 687b ldr r3, [r7, #4] - 800523a: 681b ldr r3, [r3, #0] - 800523c: 2100 movs r1, #0 - 800523e: 4618 mov r0, r3 - 8005240: f7ff fa44 bl 80046cc - 8005244: 4603 mov r3, r0 - 8005246: 0e9b lsrs r3, r3, #26 - 8005248: f003 021f and.w r2, r3, #31 - 800524c: e01e b.n 800528c - 800524e: 687b ldr r3, [r7, #4] - 8005250: 681b ldr r3, [r3, #0] - 8005252: 2100 movs r1, #0 - 8005254: 4618 mov r0, r3 - 8005256: f7ff fa39 bl 80046cc - 800525a: 4603 mov r3, r0 - 800525c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 8005eb6: 687b ldr r3, [r7, #4] + 8005eb8: 681b ldr r3, [r3, #0] + 8005eba: 2100 movs r1, #0 + 8005ebc: 4618 mov r0, r3 + 8005ebe: f7ff fa4f bl 8005360 + 8005ec2: 4603 mov r3, r0 + 8005ec4: f3c3 0312 ubfx r3, r3, #0, #19 + 8005ec8: 2b00 cmp r3, #0 + 8005eca: d10a bne.n 8005ee2 + 8005ecc: 687b ldr r3, [r7, #4] + 8005ece: 681b ldr r3, [r3, #0] + 8005ed0: 2100 movs r1, #0 + 8005ed2: 4618 mov r0, r3 + 8005ed4: f7ff fa44 bl 8005360 + 8005ed8: 4603 mov r3, r0 + 8005eda: 0e9b lsrs r3, r3, #26 + 8005edc: f003 021f and.w r2, r3, #31 + 8005ee0: e01e b.n 8005f20 + 8005ee2: 687b ldr r3, [r7, #4] + 8005ee4: 681b ldr r3, [r3, #0] + 8005ee6: 2100 movs r1, #0 + 8005ee8: 4618 mov r0, r3 + 8005eea: f7ff fa39 bl 8005360 + 8005eee: 4603 mov r3, r0 + 8005ef0: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005260: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 8005264: fa93 f3a3 rbit r3, r3 - 8005268: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 8005ef4: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 8005ef8: fa93 f3a3 rbit r3, r3 + 8005efc: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; - 800526c: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 - 8005270: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 8005f00: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8005f04: f8c7 30bc str.w r3, [r7, #188] ; 0xbc optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) - 8005274: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 8005278: 2b00 cmp r3, #0 - 800527a: d101 bne.n 8005280 + 8005f08: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 8005f0c: 2b00 cmp r3, #0 + 8005f0e: d101 bne.n 8005f14 { return 32U; - 800527c: 2320 movs r3, #32 - 800527e: e004 b.n 800528a + 8005f10: 2320 movs r3, #32 + 8005f12: e004 b.n 8005f1e } return __builtin_clz(value); - 8005280: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 8005284: fab3 f383 clz r3, r3 - 8005288: b2db uxtb r3, r3 - 800528a: 461a mov r2, r3 + 8005f14: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 8005f18: fab3 f383 clz r3, r3 + 8005f1c: b2db uxtb r3, r3 + 8005f1e: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 800528c: 683b ldr r3, [r7, #0] - 800528e: 681b ldr r3, [r3, #0] - 8005290: f3c3 0312 ubfx r3, r3, #0, #19 - 8005294: 2b00 cmp r3, #0 - 8005296: d105 bne.n 80052a4 - 8005298: 683b ldr r3, [r7, #0] - 800529a: 681b ldr r3, [r3, #0] - 800529c: 0e9b lsrs r3, r3, #26 - 800529e: f003 031f and.w r3, r3, #31 - 80052a2: e018 b.n 80052d6 - 80052a4: 683b ldr r3, [r7, #0] - 80052a6: 681b ldr r3, [r3, #0] - 80052a8: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 8005f20: 683b ldr r3, [r7, #0] + 8005f22: 681b ldr r3, [r3, #0] + 8005f24: f3c3 0312 ubfx r3, r3, #0, #19 + 8005f28: 2b00 cmp r3, #0 + 8005f2a: d105 bne.n 8005f38 + 8005f2c: 683b ldr r3, [r7, #0] + 8005f2e: 681b ldr r3, [r3, #0] + 8005f30: 0e9b lsrs r3, r3, #26 + 8005f32: f003 031f and.w r3, r3, #31 + 8005f36: e018 b.n 8005f6a + 8005f38: 683b ldr r3, [r7, #0] + 8005f3a: 681b ldr r3, [r3, #0] + 8005f3c: f8c7 30ac str.w r3, [r7, #172] ; 0xac __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80052ac: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 80052b0: fa93 f3a3 rbit r3, r3 - 80052b4: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + 8005f40: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 8005f44: fa93 f3a3 rbit r3, r3 + 8005f48: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 return result; - 80052b8: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 80052bc: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + 8005f4c: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 8005f50: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 if (value == 0U) - 80052c0: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 - 80052c4: 2b00 cmp r3, #0 - 80052c6: d101 bne.n 80052cc + 8005f54: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 + 8005f58: 2b00 cmp r3, #0 + 8005f5a: d101 bne.n 8005f60 return 32U; - 80052c8: 2320 movs r3, #32 - 80052ca: e004 b.n 80052d6 + 8005f5c: 2320 movs r3, #32 + 8005f5e: e004 b.n 8005f6a return __builtin_clz(value); - 80052cc: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 - 80052d0: fab3 f383 clz r3, r3 - 80052d4: b2db uxtb r3, r3 + 8005f60: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 + 8005f64: fab3 f383 clz r3, r3 + 8005f68: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - 80052d6: 429a cmp r2, r3 - 80052d8: d106 bne.n 80052e8 + 8005f6a: 429a cmp r2, r3 + 8005f6c: d106 bne.n 8005f7c { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); - 80052da: 687b ldr r3, [r7, #4] - 80052dc: 681b ldr r3, [r3, #0] - 80052de: 2200 movs r2, #0 - 80052e0: 2100 movs r1, #0 - 80052e2: 4618 mov r0, r3 - 80052e4: f7ff fa08 bl 80046f8 + 8005f6e: 687b ldr r3, [r7, #4] + 8005f70: 681b ldr r3, [r3, #0] + 8005f72: 2200 movs r2, #0 + 8005f74: 2100 movs r1, #0 + 8005f76: 4618 mov r0, r3 + 8005f78: f7ff fa08 bl 800538c } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - 80052e8: 687b ldr r3, [r7, #4] - 80052ea: 681b ldr r3, [r3, #0] - 80052ec: 2101 movs r1, #1 - 80052ee: 4618 mov r0, r3 - 80052f0: f7ff f9ec bl 80046cc - 80052f4: 4603 mov r3, r0 - 80052f6: f3c3 0312 ubfx r3, r3, #0, #19 - 80052fa: 2b00 cmp r3, #0 - 80052fc: d10a bne.n 8005314 - 80052fe: 687b ldr r3, [r7, #4] - 8005300: 681b ldr r3, [r3, #0] - 8005302: 2101 movs r1, #1 - 8005304: 4618 mov r0, r3 - 8005306: f7ff f9e1 bl 80046cc - 800530a: 4603 mov r3, r0 - 800530c: 0e9b lsrs r3, r3, #26 - 800530e: f003 021f and.w r2, r3, #31 - 8005312: e01e b.n 8005352 - 8005314: 687b ldr r3, [r7, #4] - 8005316: 681b ldr r3, [r3, #0] - 8005318: 2101 movs r1, #1 - 800531a: 4618 mov r0, r3 - 800531c: f7ff f9d6 bl 80046cc - 8005320: 4603 mov r3, r0 - 8005322: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 8005f7c: 687b ldr r3, [r7, #4] + 8005f7e: 681b ldr r3, [r3, #0] + 8005f80: 2101 movs r1, #1 + 8005f82: 4618 mov r0, r3 + 8005f84: f7ff f9ec bl 8005360 + 8005f88: 4603 mov r3, r0 + 8005f8a: f3c3 0312 ubfx r3, r3, #0, #19 + 8005f8e: 2b00 cmp r3, #0 + 8005f90: d10a bne.n 8005fa8 + 8005f92: 687b ldr r3, [r7, #4] + 8005f94: 681b ldr r3, [r3, #0] + 8005f96: 2101 movs r1, #1 + 8005f98: 4618 mov r0, r3 + 8005f9a: f7ff f9e1 bl 8005360 + 8005f9e: 4603 mov r3, r0 + 8005fa0: 0e9b lsrs r3, r3, #26 + 8005fa2: f003 021f and.w r2, r3, #31 + 8005fa6: e01e b.n 8005fe6 + 8005fa8: 687b ldr r3, [r7, #4] + 8005faa: 681b ldr r3, [r3, #0] + 8005fac: 2101 movs r1, #1 + 8005fae: 4618 mov r0, r3 + 8005fb0: f7ff f9d6 bl 8005360 + 8005fb4: 4603 mov r3, r0 + 8005fb6: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005326: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 - 800532a: fa93 f3a3 rbit r3, r3 - 800532e: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 8005fba: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 8005fbe: fa93 f3a3 rbit r3, r3 + 8005fc2: f8c7 309c str.w r3, [r7, #156] ; 0x9c return result; - 8005332: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c - 8005336: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 8005fc6: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 8005fca: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 if (value == 0U) - 800533a: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 - 800533e: 2b00 cmp r3, #0 - 8005340: d101 bne.n 8005346 + 8005fce: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 + 8005fd2: 2b00 cmp r3, #0 + 8005fd4: d101 bne.n 8005fda return 32U; - 8005342: 2320 movs r3, #32 - 8005344: e004 b.n 8005350 + 8005fd6: 2320 movs r3, #32 + 8005fd8: e004 b.n 8005fe4 return __builtin_clz(value); - 8005346: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 - 800534a: fab3 f383 clz r3, r3 - 800534e: b2db uxtb r3, r3 - 8005350: 461a mov r2, r3 + 8005fda: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 + 8005fde: fab3 f383 clz r3, r3 + 8005fe2: b2db uxtb r3, r3 + 8005fe4: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 8005352: 683b ldr r3, [r7, #0] - 8005354: 681b ldr r3, [r3, #0] - 8005356: f3c3 0312 ubfx r3, r3, #0, #19 - 800535a: 2b00 cmp r3, #0 - 800535c: d105 bne.n 800536a - 800535e: 683b ldr r3, [r7, #0] - 8005360: 681b ldr r3, [r3, #0] - 8005362: 0e9b lsrs r3, r3, #26 - 8005364: f003 031f and.w r3, r3, #31 - 8005368: e018 b.n 800539c - 800536a: 683b ldr r3, [r7, #0] - 800536c: 681b ldr r3, [r3, #0] - 800536e: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 8005fe6: 683b ldr r3, [r7, #0] + 8005fe8: 681b ldr r3, [r3, #0] + 8005fea: f3c3 0312 ubfx r3, r3, #0, #19 + 8005fee: 2b00 cmp r3, #0 + 8005ff0: d105 bne.n 8005ffe + 8005ff2: 683b ldr r3, [r7, #0] + 8005ff4: 681b ldr r3, [r3, #0] + 8005ff6: 0e9b lsrs r3, r3, #26 + 8005ff8: f003 031f and.w r3, r3, #31 + 8005ffc: e018 b.n 8006030 + 8005ffe: 683b ldr r3, [r7, #0] + 8006000: 681b ldr r3, [r3, #0] + 8006002: f8c7 3094 str.w r3, [r7, #148] ; 0x94 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005372: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 - 8005376: fa93 f3a3 rbit r3, r3 - 800537a: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 8006006: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 + 800600a: fa93 f3a3 rbit r3, r3 + 800600e: f8c7 3090 str.w r3, [r7, #144] ; 0x90 return result; - 800537e: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 - 8005382: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 8006012: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 8006016: f8c7 3098 str.w r3, [r7, #152] ; 0x98 if (value == 0U) - 8005386: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800538a: 2b00 cmp r3, #0 - 800538c: d101 bne.n 8005392 + 800601a: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800601e: 2b00 cmp r3, #0 + 8006020: d101 bne.n 8006026 return 32U; - 800538e: 2320 movs r3, #32 - 8005390: e004 b.n 800539c + 8006022: 2320 movs r3, #32 + 8006024: e004 b.n 8006030 return __builtin_clz(value); - 8005392: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 8005396: fab3 f383 clz r3, r3 - 800539a: b2db uxtb r3, r3 + 8006026: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800602a: fab3 f383 clz r3, r3 + 800602e: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - 800539c: 429a cmp r2, r3 - 800539e: d106 bne.n 80053ae + 8006030: 429a cmp r2, r3 + 8006032: d106 bne.n 8006042 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); - 80053a0: 687b ldr r3, [r7, #4] - 80053a2: 681b ldr r3, [r3, #0] - 80053a4: 2200 movs r2, #0 - 80053a6: 2101 movs r1, #1 - 80053a8: 4618 mov r0, r3 - 80053aa: f7ff f9a5 bl 80046f8 + 8006034: 687b ldr r3, [r7, #4] + 8006036: 681b ldr r3, [r3, #0] + 8006038: 2200 movs r2, #0 + 800603a: 2101 movs r1, #1 + 800603c: 4618 mov r0, r3 + 800603e: f7ff f9a5 bl 800538c } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - 80053ae: 687b ldr r3, [r7, #4] - 80053b0: 681b ldr r3, [r3, #0] - 80053b2: 2102 movs r1, #2 - 80053b4: 4618 mov r0, r3 - 80053b6: f7ff f989 bl 80046cc - 80053ba: 4603 mov r3, r0 - 80053bc: f3c3 0312 ubfx r3, r3, #0, #19 - 80053c0: 2b00 cmp r3, #0 - 80053c2: d10a bne.n 80053da - 80053c4: 687b ldr r3, [r7, #4] - 80053c6: 681b ldr r3, [r3, #0] - 80053c8: 2102 movs r1, #2 - 80053ca: 4618 mov r0, r3 - 80053cc: f7ff f97e bl 80046cc - 80053d0: 4603 mov r3, r0 - 80053d2: 0e9b lsrs r3, r3, #26 - 80053d4: f003 021f and.w r2, r3, #31 - 80053d8: e01e b.n 8005418 - 80053da: 687b ldr r3, [r7, #4] - 80053dc: 681b ldr r3, [r3, #0] - 80053de: 2102 movs r1, #2 - 80053e0: 4618 mov r0, r3 - 80053e2: f7ff f973 bl 80046cc - 80053e6: 4603 mov r3, r0 - 80053e8: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + 8006042: 687b ldr r3, [r7, #4] + 8006044: 681b ldr r3, [r3, #0] + 8006046: 2102 movs r1, #2 + 8006048: 4618 mov r0, r3 + 800604a: f7ff f989 bl 8005360 + 800604e: 4603 mov r3, r0 + 8006050: f3c3 0312 ubfx r3, r3, #0, #19 + 8006054: 2b00 cmp r3, #0 + 8006056: d10a bne.n 800606e + 8006058: 687b ldr r3, [r7, #4] + 800605a: 681b ldr r3, [r3, #0] + 800605c: 2102 movs r1, #2 + 800605e: 4618 mov r0, r3 + 8006060: f7ff f97e bl 8005360 + 8006064: 4603 mov r3, r0 + 8006066: 0e9b lsrs r3, r3, #26 + 8006068: f003 021f and.w r2, r3, #31 + 800606c: e01e b.n 80060ac + 800606e: 687b ldr r3, [r7, #4] + 8006070: 681b ldr r3, [r3, #0] + 8006072: 2102 movs r1, #2 + 8006074: 4618 mov r0, r3 + 8006076: f7ff f973 bl 8005360 + 800607a: 4603 mov r3, r0 + 800607c: f8c7 3088 str.w r3, [r7, #136] ; 0x88 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80053ec: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 - 80053f0: fa93 f3a3 rbit r3, r3 - 80053f4: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 8006080: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 + 8006084: fa93 f3a3 rbit r3, r3 + 8006088: f8c7 3084 str.w r3, [r7, #132] ; 0x84 return result; - 80053f8: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 80053fc: f8c7 308c str.w r3, [r7, #140] ; 0x8c + 800608c: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 8006090: f8c7 308c str.w r3, [r7, #140] ; 0x8c if (value == 0U) - 8005400: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8005404: 2b00 cmp r3, #0 - 8005406: d101 bne.n 800540c + 8006094: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8006098: 2b00 cmp r3, #0 + 800609a: d101 bne.n 80060a0 return 32U; - 8005408: 2320 movs r3, #32 - 800540a: e004 b.n 8005416 + 800609c: 2320 movs r3, #32 + 800609e: e004 b.n 80060aa return __builtin_clz(value); - 800540c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8005410: fab3 f383 clz r3, r3 - 8005414: b2db uxtb r3, r3 - 8005416: 461a mov r2, r3 + 80060a0: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80060a4: fab3 f383 clz r3, r3 + 80060a8: b2db uxtb r3, r3 + 80060aa: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 8005418: 683b ldr r3, [r7, #0] - 800541a: 681b ldr r3, [r3, #0] - 800541c: f3c3 0312 ubfx r3, r3, #0, #19 - 8005420: 2b00 cmp r3, #0 - 8005422: d105 bne.n 8005430 - 8005424: 683b ldr r3, [r7, #0] - 8005426: 681b ldr r3, [r3, #0] - 8005428: 0e9b lsrs r3, r3, #26 - 800542a: f003 031f and.w r3, r3, #31 - 800542e: e014 b.n 800545a - 8005430: 683b ldr r3, [r7, #0] - 8005432: 681b ldr r3, [r3, #0] - 8005434: 67fb str r3, [r7, #124] ; 0x7c + 80060ac: 683b ldr r3, [r7, #0] + 80060ae: 681b ldr r3, [r3, #0] + 80060b0: f3c3 0312 ubfx r3, r3, #0, #19 + 80060b4: 2b00 cmp r3, #0 + 80060b6: d105 bne.n 80060c4 + 80060b8: 683b ldr r3, [r7, #0] + 80060ba: 681b ldr r3, [r3, #0] + 80060bc: 0e9b lsrs r3, r3, #26 + 80060be: f003 031f and.w r3, r3, #31 + 80060c2: e014 b.n 80060ee + 80060c4: 683b ldr r3, [r7, #0] + 80060c6: 681b ldr r3, [r3, #0] + 80060c8: 67fb str r3, [r7, #124] ; 0x7c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005436: 6ffb ldr r3, [r7, #124] ; 0x7c - 8005438: fa93 f3a3 rbit r3, r3 - 800543c: 67bb str r3, [r7, #120] ; 0x78 + 80060ca: 6ffb ldr r3, [r7, #124] ; 0x7c + 80060cc: fa93 f3a3 rbit r3, r3 + 80060d0: 67bb str r3, [r7, #120] ; 0x78 return result; - 800543e: 6fbb ldr r3, [r7, #120] ; 0x78 - 8005440: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 80060d2: 6fbb ldr r3, [r7, #120] ; 0x78 + 80060d4: f8c7 3080 str.w r3, [r7, #128] ; 0x80 if (value == 0U) - 8005444: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 8005448: 2b00 cmp r3, #0 - 800544a: d101 bne.n 8005450 + 80060d8: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 80060dc: 2b00 cmp r3, #0 + 80060de: d101 bne.n 80060e4 return 32U; - 800544c: 2320 movs r3, #32 - 800544e: e004 b.n 800545a + 80060e0: 2320 movs r3, #32 + 80060e2: e004 b.n 80060ee return __builtin_clz(value); - 8005450: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 8005454: fab3 f383 clz r3, r3 - 8005458: b2db uxtb r3, r3 + 80060e4: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 80060e8: fab3 f383 clz r3, r3 + 80060ec: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - 800545a: 429a cmp r2, r3 - 800545c: d106 bne.n 800546c + 80060ee: 429a cmp r2, r3 + 80060f0: d106 bne.n 8006100 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); - 800545e: 687b ldr r3, [r7, #4] - 8005460: 681b ldr r3, [r3, #0] - 8005462: 2200 movs r2, #0 - 8005464: 2102 movs r1, #2 - 8005466: 4618 mov r0, r3 - 8005468: f7ff f946 bl 80046f8 + 80060f2: 687b ldr r3, [r7, #4] + 80060f4: 681b ldr r3, [r3, #0] + 80060f6: 2200 movs r2, #0 + 80060f8: 2102 movs r1, #2 + 80060fa: 4618 mov r0, r3 + 80060fc: f7ff f946 bl 800538c } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - 800546c: 687b ldr r3, [r7, #4] - 800546e: 681b ldr r3, [r3, #0] - 8005470: 2103 movs r1, #3 - 8005472: 4618 mov r0, r3 - 8005474: f7ff f92a bl 80046cc - 8005478: 4603 mov r3, r0 - 800547a: f3c3 0312 ubfx r3, r3, #0, #19 - 800547e: 2b00 cmp r3, #0 - 8005480: d10a bne.n 8005498 - 8005482: 687b ldr r3, [r7, #4] - 8005484: 681b ldr r3, [r3, #0] - 8005486: 2103 movs r1, #3 - 8005488: 4618 mov r0, r3 - 800548a: f7ff f91f bl 80046cc - 800548e: 4603 mov r3, r0 - 8005490: 0e9b lsrs r3, r3, #26 - 8005492: f003 021f and.w r2, r3, #31 - 8005496: e017 b.n 80054c8 - 8005498: 687b ldr r3, [r7, #4] - 800549a: 681b ldr r3, [r3, #0] - 800549c: 2103 movs r1, #3 - 800549e: 4618 mov r0, r3 - 80054a0: f7ff f914 bl 80046cc - 80054a4: 4603 mov r3, r0 - 80054a6: 673b str r3, [r7, #112] ; 0x70 + 8006100: 687b ldr r3, [r7, #4] + 8006102: 681b ldr r3, [r3, #0] + 8006104: 2103 movs r1, #3 + 8006106: 4618 mov r0, r3 + 8006108: f7ff f92a bl 8005360 + 800610c: 4603 mov r3, r0 + 800610e: f3c3 0312 ubfx r3, r3, #0, #19 + 8006112: 2b00 cmp r3, #0 + 8006114: d10a bne.n 800612c + 8006116: 687b ldr r3, [r7, #4] + 8006118: 681b ldr r3, [r3, #0] + 800611a: 2103 movs r1, #3 + 800611c: 4618 mov r0, r3 + 800611e: f7ff f91f bl 8005360 + 8006122: 4603 mov r3, r0 + 8006124: 0e9b lsrs r3, r3, #26 + 8006126: f003 021f and.w r2, r3, #31 + 800612a: e017 b.n 800615c + 800612c: 687b ldr r3, [r7, #4] + 800612e: 681b ldr r3, [r3, #0] + 8006130: 2103 movs r1, #3 + 8006132: 4618 mov r0, r3 + 8006134: f7ff f914 bl 8005360 + 8006138: 4603 mov r3, r0 + 800613a: 673b str r3, [r7, #112] ; 0x70 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80054a8: 6f3b ldr r3, [r7, #112] ; 0x70 - 80054aa: fa93 f3a3 rbit r3, r3 - 80054ae: 66fb str r3, [r7, #108] ; 0x6c + 800613c: 6f3b ldr r3, [r7, #112] ; 0x70 + 800613e: fa93 f3a3 rbit r3, r3 + 8006142: 66fb str r3, [r7, #108] ; 0x6c return result; - 80054b0: 6efb ldr r3, [r7, #108] ; 0x6c - 80054b2: 677b str r3, [r7, #116] ; 0x74 + 8006144: 6efb ldr r3, [r7, #108] ; 0x6c + 8006146: 677b str r3, [r7, #116] ; 0x74 if (value == 0U) - 80054b4: 6f7b ldr r3, [r7, #116] ; 0x74 - 80054b6: 2b00 cmp r3, #0 - 80054b8: d101 bne.n 80054be + 8006148: 6f7b ldr r3, [r7, #116] ; 0x74 + 800614a: 2b00 cmp r3, #0 + 800614c: d101 bne.n 8006152 return 32U; - 80054ba: 2320 movs r3, #32 - 80054bc: e003 b.n 80054c6 + 800614e: 2320 movs r3, #32 + 8006150: e003 b.n 800615a return __builtin_clz(value); - 80054be: 6f7b ldr r3, [r7, #116] ; 0x74 - 80054c0: fab3 f383 clz r3, r3 - 80054c4: b2db uxtb r3, r3 - 80054c6: 461a mov r2, r3 + 8006152: 6f7b ldr r3, [r7, #116] ; 0x74 + 8006154: fab3 f383 clz r3, r3 + 8006158: b2db uxtb r3, r3 + 800615a: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 80054c8: 683b ldr r3, [r7, #0] - 80054ca: 681b ldr r3, [r3, #0] - 80054cc: f3c3 0312 ubfx r3, r3, #0, #19 - 80054d0: 2b00 cmp r3, #0 - 80054d2: d105 bne.n 80054e0 - 80054d4: 683b ldr r3, [r7, #0] - 80054d6: 681b ldr r3, [r3, #0] - 80054d8: 0e9b lsrs r3, r3, #26 - 80054da: f003 031f and.w r3, r3, #31 - 80054de: e011 b.n 8005504 - 80054e0: 683b ldr r3, [r7, #0] - 80054e2: 681b ldr r3, [r3, #0] - 80054e4: 667b str r3, [r7, #100] ; 0x64 + 800615c: 683b ldr r3, [r7, #0] + 800615e: 681b ldr r3, [r3, #0] + 8006160: f3c3 0312 ubfx r3, r3, #0, #19 + 8006164: 2b00 cmp r3, #0 + 8006166: d105 bne.n 8006174 + 8006168: 683b ldr r3, [r7, #0] + 800616a: 681b ldr r3, [r3, #0] + 800616c: 0e9b lsrs r3, r3, #26 + 800616e: f003 031f and.w r3, r3, #31 + 8006172: e011 b.n 8006198 + 8006174: 683b ldr r3, [r7, #0] + 8006176: 681b ldr r3, [r3, #0] + 8006178: 667b str r3, [r7, #100] ; 0x64 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80054e6: 6e7b ldr r3, [r7, #100] ; 0x64 - 80054e8: fa93 f3a3 rbit r3, r3 - 80054ec: 663b str r3, [r7, #96] ; 0x60 + 800617a: 6e7b ldr r3, [r7, #100] ; 0x64 + 800617c: fa93 f3a3 rbit r3, r3 + 8006180: 663b str r3, [r7, #96] ; 0x60 return result; - 80054ee: 6e3b ldr r3, [r7, #96] ; 0x60 - 80054f0: 66bb str r3, [r7, #104] ; 0x68 + 8006182: 6e3b ldr r3, [r7, #96] ; 0x60 + 8006184: 66bb str r3, [r7, #104] ; 0x68 if (value == 0U) - 80054f2: 6ebb ldr r3, [r7, #104] ; 0x68 - 80054f4: 2b00 cmp r3, #0 - 80054f6: d101 bne.n 80054fc + 8006186: 6ebb ldr r3, [r7, #104] ; 0x68 + 8006188: 2b00 cmp r3, #0 + 800618a: d101 bne.n 8006190 return 32U; - 80054f8: 2320 movs r3, #32 - 80054fa: e003 b.n 8005504 + 800618c: 2320 movs r3, #32 + 800618e: e003 b.n 8006198 return __builtin_clz(value); - 80054fc: 6ebb ldr r3, [r7, #104] ; 0x68 - 80054fe: fab3 f383 clz r3, r3 - 8005502: b2db uxtb r3, r3 + 8006190: 6ebb ldr r3, [r7, #104] ; 0x68 + 8006192: fab3 f383 clz r3, r3 + 8006196: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - 8005504: 429a cmp r2, r3 - 8005506: d106 bne.n 8005516 + 8006198: 429a cmp r2, r3 + 800619a: d106 bne.n 80061aa { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); - 8005508: 687b ldr r3, [r7, #4] - 800550a: 681b ldr r3, [r3, #0] - 800550c: 2200 movs r2, #0 - 800550e: 2103 movs r1, #3 - 8005510: 4618 mov r0, r3 - 8005512: f7ff f8f1 bl 80046f8 + 800619c: 687b ldr r3, [r7, #4] + 800619e: 681b ldr r3, [r3, #0] + 80061a0: 2200 movs r2, #0 + 80061a2: 2103 movs r1, #3 + 80061a4: 4618 mov r0, r3 + 80061a6: f7ff f8f1 bl 800538c } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8005516: 687b ldr r3, [r7, #4] - 8005518: 681b ldr r3, [r3, #0] - 800551a: 4618 mov r0, r3 - 800551c: f7ff fa0a bl 8004934 - 8005520: 4603 mov r3, r0 - 8005522: 2b00 cmp r3, #0 - 8005524: f040 8140 bne.w 80057a8 + 80061aa: 687b ldr r3, [r7, #4] + 80061ac: 681b ldr r3, [r3, #0] + 80061ae: 4618 mov r0, r3 + 80061b0: f7ff fa0a bl 80055c8 + 80061b4: 4603 mov r3, r0 + 80061b6: 2b00 cmp r3, #0 + 80061b8: f040 8140 bne.w 800643c { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); - 8005528: 687b ldr r3, [r7, #4] - 800552a: 6818 ldr r0, [r3, #0] - 800552c: 683b ldr r3, [r7, #0] - 800552e: 6819 ldr r1, [r3, #0] - 8005530: 683b ldr r3, [r7, #0] - 8005532: 68db ldr r3, [r3, #12] - 8005534: 461a mov r2, r3 - 8005536: f7ff f977 bl 8004828 + 80061bc: 687b ldr r3, [r7, #4] + 80061be: 6818 ldr r0, [r3, #0] + 80061c0: 683b ldr r3, [r7, #0] + 80061c2: 6819 ldr r1, [r3, #0] + 80061c4: 683b ldr r3, [r7, #0] + 80061c6: 68db ldr r3, [r3, #12] + 80061c8: 461a mov r2, r3 + 80061ca: f7ff f977 bl 80054bc /* Configuration of differential mode */ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) - 800553a: 683b ldr r3, [r7, #0] - 800553c: 68db ldr r3, [r3, #12] - 800553e: 4a8f ldr r2, [pc, #572] ; (800577c ) - 8005540: 4293 cmp r3, r2 - 8005542: f040 8131 bne.w 80057a8 + 80061ce: 683b ldr r3, [r7, #0] + 80061d0: 68db ldr r3, [r3, #12] + 80061d2: 4a8f ldr r2, [pc, #572] ; (8006410 ) + 80061d4: 4293 cmp r3, r2 + 80061d6: f040 8131 bne.w 800643c { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8005546: 687b ldr r3, [r7, #4] - 8005548: 6818 ldr r0, [r3, #0] + 80061da: 687b ldr r3, [r7, #4] + 80061dc: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 800554a: 683b ldr r3, [r7, #0] - 800554c: 681b ldr r3, [r3, #0] - 800554e: f3c3 0312 ubfx r3, r3, #0, #19 - 8005552: 2b00 cmp r3, #0 - 8005554: d10b bne.n 800556e - 8005556: 683b ldr r3, [r7, #0] - 8005558: 681b ldr r3, [r3, #0] - 800555a: 0e9b lsrs r3, r3, #26 - 800555c: 3301 adds r3, #1 - 800555e: f003 031f and.w r3, r3, #31 - 8005562: 2b09 cmp r3, #9 - 8005564: bf94 ite ls - 8005566: 2301 movls r3, #1 - 8005568: 2300 movhi r3, #0 - 800556a: b2db uxtb r3, r3 - 800556c: e019 b.n 80055a2 - 800556e: 683b ldr r3, [r7, #0] - 8005570: 681b ldr r3, [r3, #0] - 8005572: 65bb str r3, [r7, #88] ; 0x58 + 80061de: 683b ldr r3, [r7, #0] + 80061e0: 681b ldr r3, [r3, #0] + 80061e2: f3c3 0312 ubfx r3, r3, #0, #19 + 80061e6: 2b00 cmp r3, #0 + 80061e8: d10b bne.n 8006202 + 80061ea: 683b ldr r3, [r7, #0] + 80061ec: 681b ldr r3, [r3, #0] + 80061ee: 0e9b lsrs r3, r3, #26 + 80061f0: 3301 adds r3, #1 + 80061f2: f003 031f and.w r3, r3, #31 + 80061f6: 2b09 cmp r3, #9 + 80061f8: bf94 ite ls + 80061fa: 2301 movls r3, #1 + 80061fc: 2300 movhi r3, #0 + 80061fe: b2db uxtb r3, r3 + 8006200: e019 b.n 8006236 + 8006202: 683b ldr r3, [r7, #0] + 8006204: 681b ldr r3, [r3, #0] + 8006206: 65bb str r3, [r7, #88] ; 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005574: 6dbb ldr r3, [r7, #88] ; 0x58 - 8005576: fa93 f3a3 rbit r3, r3 - 800557a: 657b str r3, [r7, #84] ; 0x54 + 8006208: 6dbb ldr r3, [r7, #88] ; 0x58 + 800620a: fa93 f3a3 rbit r3, r3 + 800620e: 657b str r3, [r7, #84] ; 0x54 return result; - 800557c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800557e: 65fb str r3, [r7, #92] ; 0x5c + 8006210: 6d7b ldr r3, [r7, #84] ; 0x54 + 8006212: 65fb str r3, [r7, #92] ; 0x5c if (value == 0U) - 8005580: 6dfb ldr r3, [r7, #92] ; 0x5c - 8005582: 2b00 cmp r3, #0 - 8005584: d101 bne.n 800558a + 8006214: 6dfb ldr r3, [r7, #92] ; 0x5c + 8006216: 2b00 cmp r3, #0 + 8006218: d101 bne.n 800621e return 32U; - 8005586: 2320 movs r3, #32 - 8005588: e003 b.n 8005592 + 800621a: 2320 movs r3, #32 + 800621c: e003 b.n 8006226 return __builtin_clz(value); - 800558a: 6dfb ldr r3, [r7, #92] ; 0x5c - 800558c: fab3 f383 clz r3, r3 - 8005590: b2db uxtb r3, r3 - 8005592: 3301 adds r3, #1 - 8005594: f003 031f and.w r3, r3, #31 - 8005598: 2b09 cmp r3, #9 - 800559a: bf94 ite ls - 800559c: 2301 movls r3, #1 - 800559e: 2300 movhi r3, #0 - 80055a0: b2db uxtb r3, r3 + 800621e: 6dfb ldr r3, [r7, #92] ; 0x5c + 8006220: fab3 f383 clz r3, r3 + 8006224: b2db uxtb r3, r3 + 8006226: 3301 adds r3, #1 + 8006228: f003 031f and.w r3, r3, #31 + 800622c: 2b09 cmp r3, #9 + 800622e: bf94 ite ls + 8006230: 2301 movls r3, #1 + 8006232: 2300 movhi r3, #0 + 8006234: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 80055a2: 2b00 cmp r3, #0 - 80055a4: d079 beq.n 800569a + 8006236: 2b00 cmp r3, #0 + 8006238: d079 beq.n 800632e (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 80055a6: 683b ldr r3, [r7, #0] - 80055a8: 681b ldr r3, [r3, #0] - 80055aa: f3c3 0312 ubfx r3, r3, #0, #19 - 80055ae: 2b00 cmp r3, #0 - 80055b0: d107 bne.n 80055c2 - 80055b2: 683b ldr r3, [r7, #0] - 80055b4: 681b ldr r3, [r3, #0] - 80055b6: 0e9b lsrs r3, r3, #26 - 80055b8: 3301 adds r3, #1 - 80055ba: 069b lsls r3, r3, #26 - 80055bc: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 - 80055c0: e015 b.n 80055ee - 80055c2: 683b ldr r3, [r7, #0] - 80055c4: 681b ldr r3, [r3, #0] - 80055c6: 64fb str r3, [r7, #76] ; 0x4c + 800623a: 683b ldr r3, [r7, #0] + 800623c: 681b ldr r3, [r3, #0] + 800623e: f3c3 0312 ubfx r3, r3, #0, #19 + 8006242: 2b00 cmp r3, #0 + 8006244: d107 bne.n 8006256 + 8006246: 683b ldr r3, [r7, #0] + 8006248: 681b ldr r3, [r3, #0] + 800624a: 0e9b lsrs r3, r3, #26 + 800624c: 3301 adds r3, #1 + 800624e: 069b lsls r3, r3, #26 + 8006250: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 + 8006254: e015 b.n 8006282 + 8006256: 683b ldr r3, [r7, #0] + 8006258: 681b ldr r3, [r3, #0] + 800625a: 64fb str r3, [r7, #76] ; 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80055c8: 6cfb ldr r3, [r7, #76] ; 0x4c - 80055ca: fa93 f3a3 rbit r3, r3 - 80055ce: 64bb str r3, [r7, #72] ; 0x48 + 800625c: 6cfb ldr r3, [r7, #76] ; 0x4c + 800625e: fa93 f3a3 rbit r3, r3 + 8006262: 64bb str r3, [r7, #72] ; 0x48 return result; - 80055d0: 6cbb ldr r3, [r7, #72] ; 0x48 - 80055d2: 653b str r3, [r7, #80] ; 0x50 + 8006264: 6cbb ldr r3, [r7, #72] ; 0x48 + 8006266: 653b str r3, [r7, #80] ; 0x50 if (value == 0U) - 80055d4: 6d3b ldr r3, [r7, #80] ; 0x50 - 80055d6: 2b00 cmp r3, #0 - 80055d8: d101 bne.n 80055de + 8006268: 6d3b ldr r3, [r7, #80] ; 0x50 + 800626a: 2b00 cmp r3, #0 + 800626c: d101 bne.n 8006272 return 32U; - 80055da: 2320 movs r3, #32 - 80055dc: e003 b.n 80055e6 + 800626e: 2320 movs r3, #32 + 8006270: e003 b.n 800627a return __builtin_clz(value); - 80055de: 6d3b ldr r3, [r7, #80] ; 0x50 - 80055e0: fab3 f383 clz r3, r3 - 80055e4: b2db uxtb r3, r3 - 80055e6: 3301 adds r3, #1 - 80055e8: 069b lsls r3, r3, #26 - 80055ea: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 - 80055ee: 683b ldr r3, [r7, #0] - 80055f0: 681b ldr r3, [r3, #0] - 80055f2: f3c3 0312 ubfx r3, r3, #0, #19 - 80055f6: 2b00 cmp r3, #0 - 80055f8: d109 bne.n 800560e - 80055fa: 683b ldr r3, [r7, #0] - 80055fc: 681b ldr r3, [r3, #0] - 80055fe: 0e9b lsrs r3, r3, #26 - 8005600: 3301 adds r3, #1 - 8005602: f003 031f and.w r3, r3, #31 - 8005606: 2101 movs r1, #1 - 8005608: fa01 f303 lsl.w r3, r1, r3 - 800560c: e017 b.n 800563e - 800560e: 683b ldr r3, [r7, #0] - 8005610: 681b ldr r3, [r3, #0] - 8005612: 643b str r3, [r7, #64] ; 0x40 + 8006272: 6d3b ldr r3, [r7, #80] ; 0x50 + 8006274: fab3 f383 clz r3, r3 + 8006278: b2db uxtb r3, r3 + 800627a: 3301 adds r3, #1 + 800627c: 069b lsls r3, r3, #26 + 800627e: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 + 8006282: 683b ldr r3, [r7, #0] + 8006284: 681b ldr r3, [r3, #0] + 8006286: f3c3 0312 ubfx r3, r3, #0, #19 + 800628a: 2b00 cmp r3, #0 + 800628c: d109 bne.n 80062a2 + 800628e: 683b ldr r3, [r7, #0] + 8006290: 681b ldr r3, [r3, #0] + 8006292: 0e9b lsrs r3, r3, #26 + 8006294: 3301 adds r3, #1 + 8006296: f003 031f and.w r3, r3, #31 + 800629a: 2101 movs r1, #1 + 800629c: fa01 f303 lsl.w r3, r1, r3 + 80062a0: e017 b.n 80062d2 + 80062a2: 683b ldr r3, [r7, #0] + 80062a4: 681b ldr r3, [r3, #0] + 80062a6: 643b str r3, [r7, #64] ; 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005614: 6c3b ldr r3, [r7, #64] ; 0x40 - 8005616: fa93 f3a3 rbit r3, r3 - 800561a: 63fb str r3, [r7, #60] ; 0x3c + 80062a8: 6c3b ldr r3, [r7, #64] ; 0x40 + 80062aa: fa93 f3a3 rbit r3, r3 + 80062ae: 63fb str r3, [r7, #60] ; 0x3c return result; - 800561c: 6bfb ldr r3, [r7, #60] ; 0x3c - 800561e: 647b str r3, [r7, #68] ; 0x44 + 80062b0: 6bfb ldr r3, [r7, #60] ; 0x3c + 80062b2: 647b str r3, [r7, #68] ; 0x44 if (value == 0U) - 8005620: 6c7b ldr r3, [r7, #68] ; 0x44 - 8005622: 2b00 cmp r3, #0 - 8005624: d101 bne.n 800562a + 80062b4: 6c7b ldr r3, [r7, #68] ; 0x44 + 80062b6: 2b00 cmp r3, #0 + 80062b8: d101 bne.n 80062be return 32U; - 8005626: 2320 movs r3, #32 - 8005628: e003 b.n 8005632 + 80062ba: 2320 movs r3, #32 + 80062bc: e003 b.n 80062c6 return __builtin_clz(value); - 800562a: 6c7b ldr r3, [r7, #68] ; 0x44 - 800562c: fab3 f383 clz r3, r3 - 8005630: b2db uxtb r3, r3 - 8005632: 3301 adds r3, #1 - 8005634: f003 031f and.w r3, r3, #31 - 8005638: 2101 movs r1, #1 - 800563a: fa01 f303 lsl.w r3, r1, r3 - 800563e: ea42 0103 orr.w r1, r2, r3 - 8005642: 683b ldr r3, [r7, #0] - 8005644: 681b ldr r3, [r3, #0] - 8005646: f3c3 0312 ubfx r3, r3, #0, #19 - 800564a: 2b00 cmp r3, #0 - 800564c: d10a bne.n 8005664 - 800564e: 683b ldr r3, [r7, #0] - 8005650: 681b ldr r3, [r3, #0] - 8005652: 0e9b lsrs r3, r3, #26 - 8005654: 3301 adds r3, #1 - 8005656: f003 021f and.w r2, r3, #31 - 800565a: 4613 mov r3, r2 - 800565c: 005b lsls r3, r3, #1 - 800565e: 4413 add r3, r2 - 8005660: 051b lsls r3, r3, #20 - 8005662: e018 b.n 8005696 - 8005664: 683b ldr r3, [r7, #0] - 8005666: 681b ldr r3, [r3, #0] - 8005668: 637b str r3, [r7, #52] ; 0x34 + 80062be: 6c7b ldr r3, [r7, #68] ; 0x44 + 80062c0: fab3 f383 clz r3, r3 + 80062c4: b2db uxtb r3, r3 + 80062c6: 3301 adds r3, #1 + 80062c8: f003 031f and.w r3, r3, #31 + 80062cc: 2101 movs r1, #1 + 80062ce: fa01 f303 lsl.w r3, r1, r3 + 80062d2: ea42 0103 orr.w r1, r2, r3 + 80062d6: 683b ldr r3, [r7, #0] + 80062d8: 681b ldr r3, [r3, #0] + 80062da: f3c3 0312 ubfx r3, r3, #0, #19 + 80062de: 2b00 cmp r3, #0 + 80062e0: d10a bne.n 80062f8 + 80062e2: 683b ldr r3, [r7, #0] + 80062e4: 681b ldr r3, [r3, #0] + 80062e6: 0e9b lsrs r3, r3, #26 + 80062e8: 3301 adds r3, #1 + 80062ea: f003 021f and.w r2, r3, #31 + 80062ee: 4613 mov r3, r2 + 80062f0: 005b lsls r3, r3, #1 + 80062f2: 4413 add r3, r2 + 80062f4: 051b lsls r3, r3, #20 + 80062f6: e018 b.n 800632a + 80062f8: 683b ldr r3, [r7, #0] + 80062fa: 681b ldr r3, [r3, #0] + 80062fc: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800566a: 6b7b ldr r3, [r7, #52] ; 0x34 - 800566c: fa93 f3a3 rbit r3, r3 - 8005670: 633b str r3, [r7, #48] ; 0x30 + 80062fe: 6b7b ldr r3, [r7, #52] ; 0x34 + 8006300: fa93 f3a3 rbit r3, r3 + 8006304: 633b str r3, [r7, #48] ; 0x30 return result; - 8005672: 6b3b ldr r3, [r7, #48] ; 0x30 - 8005674: 63bb str r3, [r7, #56] ; 0x38 + 8006306: 6b3b ldr r3, [r7, #48] ; 0x30 + 8006308: 63bb str r3, [r7, #56] ; 0x38 if (value == 0U) - 8005676: 6bbb ldr r3, [r7, #56] ; 0x38 - 8005678: 2b00 cmp r3, #0 - 800567a: d101 bne.n 8005680 + 800630a: 6bbb ldr r3, [r7, #56] ; 0x38 + 800630c: 2b00 cmp r3, #0 + 800630e: d101 bne.n 8006314 return 32U; - 800567c: 2320 movs r3, #32 - 800567e: e003 b.n 8005688 + 8006310: 2320 movs r3, #32 + 8006312: e003 b.n 800631c return __builtin_clz(value); - 8005680: 6bbb ldr r3, [r7, #56] ; 0x38 - 8005682: fab3 f383 clz r3, r3 - 8005686: b2db uxtb r3, r3 - 8005688: 3301 adds r3, #1 - 800568a: f003 021f and.w r2, r3, #31 - 800568e: 4613 mov r3, r2 - 8005690: 005b lsls r3, r3, #1 - 8005692: 4413 add r3, r2 - 8005694: 051b lsls r3, r3, #20 + 8006314: 6bbb ldr r3, [r7, #56] ; 0x38 + 8006316: fab3 f383 clz r3, r3 + 800631a: b2db uxtb r3, r3 + 800631c: 3301 adds r3, #1 + 800631e: f003 021f and.w r2, r3, #31 + 8006322: 4613 mov r3, r2 + 8006324: 005b lsls r3, r3, #1 + 8006326: 4413 add r3, r2 + 8006328: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8005696: 430b orrs r3, r1 - 8005698: e081 b.n 800579e + 800632a: 430b orrs r3, r1 + 800632c: e081 b.n 8006432 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 800569a: 683b ldr r3, [r7, #0] - 800569c: 681b ldr r3, [r3, #0] - 800569e: f3c3 0312 ubfx r3, r3, #0, #19 - 80056a2: 2b00 cmp r3, #0 - 80056a4: d107 bne.n 80056b6 - 80056a6: 683b ldr r3, [r7, #0] - 80056a8: 681b ldr r3, [r3, #0] - 80056aa: 0e9b lsrs r3, r3, #26 - 80056ac: 3301 adds r3, #1 - 80056ae: 069b lsls r3, r3, #26 - 80056b0: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 - 80056b4: e015 b.n 80056e2 - 80056b6: 683b ldr r3, [r7, #0] - 80056b8: 681b ldr r3, [r3, #0] - 80056ba: 62bb str r3, [r7, #40] ; 0x28 + 800632e: 683b ldr r3, [r7, #0] + 8006330: 681b ldr r3, [r3, #0] + 8006332: f3c3 0312 ubfx r3, r3, #0, #19 + 8006336: 2b00 cmp r3, #0 + 8006338: d107 bne.n 800634a + 800633a: 683b ldr r3, [r7, #0] + 800633c: 681b ldr r3, [r3, #0] + 800633e: 0e9b lsrs r3, r3, #26 + 8006340: 3301 adds r3, #1 + 8006342: 069b lsls r3, r3, #26 + 8006344: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 + 8006348: e015 b.n 8006376 + 800634a: 683b ldr r3, [r7, #0] + 800634c: 681b ldr r3, [r3, #0] + 800634e: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80056bc: 6abb ldr r3, [r7, #40] ; 0x28 - 80056be: fa93 f3a3 rbit r3, r3 - 80056c2: 627b str r3, [r7, #36] ; 0x24 + 8006350: 6abb ldr r3, [r7, #40] ; 0x28 + 8006352: fa93 f3a3 rbit r3, r3 + 8006356: 627b str r3, [r7, #36] ; 0x24 return result; - 80056c4: 6a7b ldr r3, [r7, #36] ; 0x24 - 80056c6: 62fb str r3, [r7, #44] ; 0x2c + 8006358: 6a7b ldr r3, [r7, #36] ; 0x24 + 800635a: 62fb str r3, [r7, #44] ; 0x2c if (value == 0U) - 80056c8: 6afb ldr r3, [r7, #44] ; 0x2c - 80056ca: 2b00 cmp r3, #0 - 80056cc: d101 bne.n 80056d2 + 800635c: 6afb ldr r3, [r7, #44] ; 0x2c + 800635e: 2b00 cmp r3, #0 + 8006360: d101 bne.n 8006366 return 32U; - 80056ce: 2320 movs r3, #32 - 80056d0: e003 b.n 80056da + 8006362: 2320 movs r3, #32 + 8006364: e003 b.n 800636e return __builtin_clz(value); - 80056d2: 6afb ldr r3, [r7, #44] ; 0x2c - 80056d4: fab3 f383 clz r3, r3 - 80056d8: b2db uxtb r3, r3 - 80056da: 3301 adds r3, #1 - 80056dc: 069b lsls r3, r3, #26 - 80056de: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 - 80056e2: 683b ldr r3, [r7, #0] - 80056e4: 681b ldr r3, [r3, #0] - 80056e6: f3c3 0312 ubfx r3, r3, #0, #19 - 80056ea: 2b00 cmp r3, #0 - 80056ec: d109 bne.n 8005702 - 80056ee: 683b ldr r3, [r7, #0] - 80056f0: 681b ldr r3, [r3, #0] - 80056f2: 0e9b lsrs r3, r3, #26 - 80056f4: 3301 adds r3, #1 - 80056f6: f003 031f and.w r3, r3, #31 - 80056fa: 2101 movs r1, #1 - 80056fc: fa01 f303 lsl.w r3, r1, r3 - 8005700: e017 b.n 8005732 - 8005702: 683b ldr r3, [r7, #0] - 8005704: 681b ldr r3, [r3, #0] - 8005706: 61fb str r3, [r7, #28] + 8006366: 6afb ldr r3, [r7, #44] ; 0x2c + 8006368: fab3 f383 clz r3, r3 + 800636c: b2db uxtb r3, r3 + 800636e: 3301 adds r3, #1 + 8006370: 069b lsls r3, r3, #26 + 8006372: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000 + 8006376: 683b ldr r3, [r7, #0] + 8006378: 681b ldr r3, [r3, #0] + 800637a: f3c3 0312 ubfx r3, r3, #0, #19 + 800637e: 2b00 cmp r3, #0 + 8006380: d109 bne.n 8006396 + 8006382: 683b ldr r3, [r7, #0] + 8006384: 681b ldr r3, [r3, #0] + 8006386: 0e9b lsrs r3, r3, #26 + 8006388: 3301 adds r3, #1 + 800638a: f003 031f and.w r3, r3, #31 + 800638e: 2101 movs r1, #1 + 8006390: fa01 f303 lsl.w r3, r1, r3 + 8006394: e017 b.n 80063c6 + 8006396: 683b ldr r3, [r7, #0] + 8006398: 681b ldr r3, [r3, #0] + 800639a: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005708: 69fb ldr r3, [r7, #28] - 800570a: fa93 f3a3 rbit r3, r3 - 800570e: 61bb str r3, [r7, #24] + 800639c: 69fb ldr r3, [r7, #28] + 800639e: fa93 f3a3 rbit r3, r3 + 80063a2: 61bb str r3, [r7, #24] return result; - 8005710: 69bb ldr r3, [r7, #24] - 8005712: 623b str r3, [r7, #32] + 80063a4: 69bb ldr r3, [r7, #24] + 80063a6: 623b str r3, [r7, #32] if (value == 0U) - 8005714: 6a3b ldr r3, [r7, #32] - 8005716: 2b00 cmp r3, #0 - 8005718: d101 bne.n 800571e + 80063a8: 6a3b ldr r3, [r7, #32] + 80063aa: 2b00 cmp r3, #0 + 80063ac: d101 bne.n 80063b2 return 32U; - 800571a: 2320 movs r3, #32 - 800571c: e003 b.n 8005726 + 80063ae: 2320 movs r3, #32 + 80063b0: e003 b.n 80063ba return __builtin_clz(value); - 800571e: 6a3b ldr r3, [r7, #32] - 8005720: fab3 f383 clz r3, r3 - 8005724: b2db uxtb r3, r3 - 8005726: 3301 adds r3, #1 - 8005728: f003 031f and.w r3, r3, #31 - 800572c: 2101 movs r1, #1 - 800572e: fa01 f303 lsl.w r3, r1, r3 - 8005732: ea42 0103 orr.w r1, r2, r3 - 8005736: 683b ldr r3, [r7, #0] - 8005738: 681b ldr r3, [r3, #0] - 800573a: f3c3 0312 ubfx r3, r3, #0, #19 - 800573e: 2b00 cmp r3, #0 - 8005740: d10d bne.n 800575e - 8005742: 683b ldr r3, [r7, #0] - 8005744: 681b ldr r3, [r3, #0] - 8005746: 0e9b lsrs r3, r3, #26 - 8005748: 3301 adds r3, #1 - 800574a: f003 021f and.w r2, r3, #31 - 800574e: 4613 mov r3, r2 - 8005750: 005b lsls r3, r3, #1 - 8005752: 4413 add r3, r2 - 8005754: 3b1e subs r3, #30 - 8005756: 051b lsls r3, r3, #20 - 8005758: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 - 800575c: e01e b.n 800579c - 800575e: 683b ldr r3, [r7, #0] - 8005760: 681b ldr r3, [r3, #0] - 8005762: 613b str r3, [r7, #16] + 80063b2: 6a3b ldr r3, [r7, #32] + 80063b4: fab3 f383 clz r3, r3 + 80063b8: b2db uxtb r3, r3 + 80063ba: 3301 adds r3, #1 + 80063bc: f003 031f and.w r3, r3, #31 + 80063c0: 2101 movs r1, #1 + 80063c2: fa01 f303 lsl.w r3, r1, r3 + 80063c6: ea42 0103 orr.w r1, r2, r3 + 80063ca: 683b ldr r3, [r7, #0] + 80063cc: 681b ldr r3, [r3, #0] + 80063ce: f3c3 0312 ubfx r3, r3, #0, #19 + 80063d2: 2b00 cmp r3, #0 + 80063d4: d10d bne.n 80063f2 + 80063d6: 683b ldr r3, [r7, #0] + 80063d8: 681b ldr r3, [r3, #0] + 80063da: 0e9b lsrs r3, r3, #26 + 80063dc: 3301 adds r3, #1 + 80063de: f003 021f and.w r2, r3, #31 + 80063e2: 4613 mov r3, r2 + 80063e4: 005b lsls r3, r3, #1 + 80063e6: 4413 add r3, r2 + 80063e8: 3b1e subs r3, #30 + 80063ea: 051b lsls r3, r3, #20 + 80063ec: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 80063f0: e01e b.n 8006430 + 80063f2: 683b ldr r3, [r7, #0] + 80063f4: 681b ldr r3, [r3, #0] + 80063f6: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8005764: 693b ldr r3, [r7, #16] - 8005766: fa93 f3a3 rbit r3, r3 - 800576a: 60fb str r3, [r7, #12] + 80063f8: 693b ldr r3, [r7, #16] + 80063fa: fa93 f3a3 rbit r3, r3 + 80063fe: 60fb str r3, [r7, #12] return result; - 800576c: 68fb ldr r3, [r7, #12] - 800576e: 617b str r3, [r7, #20] + 8006400: 68fb ldr r3, [r7, #12] + 8006402: 617b str r3, [r7, #20] if (value == 0U) - 8005770: 697b ldr r3, [r7, #20] - 8005772: 2b00 cmp r3, #0 - 8005774: d104 bne.n 8005780 + 8006404: 697b ldr r3, [r7, #20] + 8006406: 2b00 cmp r3, #0 + 8006408: d104 bne.n 8006414 return 32U; - 8005776: 2320 movs r3, #32 - 8005778: e006 b.n 8005788 - 800577a: bf00 nop - 800577c: 407f0000 .word 0x407f0000 + 800640a: 2320 movs r3, #32 + 800640c: e006 b.n 800641c + 800640e: bf00 nop + 8006410: 407f0000 .word 0x407f0000 return __builtin_clz(value); - 8005780: 697b ldr r3, [r7, #20] - 8005782: fab3 f383 clz r3, r3 - 8005786: b2db uxtb r3, r3 - 8005788: 3301 adds r3, #1 - 800578a: f003 021f and.w r2, r3, #31 - 800578e: 4613 mov r3, r2 - 8005790: 005b lsls r3, r3, #1 - 8005792: 4413 add r3, r2 - 8005794: 3b1e subs r3, #30 - 8005796: 051b lsls r3, r3, #20 - 8005798: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 8006414: 697b ldr r3, [r7, #20] + 8006416: fab3 f383 clz r3, r3 + 800641a: b2db uxtb r3, r3 + 800641c: 3301 adds r3, #1 + 800641e: f003 021f and.w r2, r3, #31 + 8006422: 4613 mov r3, r2 + 8006424: 005b lsls r3, r3, #1 + 8006426: 4413 add r3, r2 + 8006428: 3b1e subs r3, #30 + 800642a: 051b lsls r3, r3, #20 + 800642c: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 800579c: 430b orrs r3, r1 + 8006430: 430b orrs r3, r1 (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), pConfig->SamplingTime); - 800579e: 683a ldr r2, [r7, #0] - 80057a0: 6892 ldr r2, [r2, #8] + 8006432: 683a ldr r2, [r7, #0] + 8006434: 6892 ldr r2, [r2, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, - 80057a2: 4619 mov r1, r3 - 80057a4: f7ff f815 bl 80047d2 + 8006436: 4619 mov r1, r3 + 8006438: f7ff f815 bl 8005466 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) - 80057a8: 683b ldr r3, [r7, #0] - 80057aa: 681a ldr r2, [r3, #0] - 80057ac: 4b3d ldr r3, [pc, #244] ; (80058a4 ) - 80057ae: 4013 ands r3, r2 - 80057b0: 2b00 cmp r3, #0 - 80057b2: d06c beq.n 800588e + 800643c: 683b ldr r3, [r7, #0] + 800643e: 681a ldr r2, [r3, #0] + 8006440: 4b3d ldr r3, [pc, #244] ; (8006538 ) + 8006442: 4013 ands r3, r2 + 8006444: 2b00 cmp r3, #0 + 8006446: d06c beq.n 8006522 { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - 80057b4: 483c ldr r0, [pc, #240] ; (80058a8 ) - 80057b6: f7fe ff57 bl 8004668 - 80057ba: f8c7 00c0 str.w r0, [r7, #192] ; 0xc0 + 8006448: 483c ldr r0, [pc, #240] ; (800653c ) + 800644a: f7fe ff57 bl 80052fc + 800644e: f8c7 00c0 str.w r0, [r7, #192] ; 0xc0 /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - 80057be: 683b ldr r3, [r7, #0] - 80057c0: 681b ldr r3, [r3, #0] - 80057c2: 4a3a ldr r2, [pc, #232] ; (80058ac ) - 80057c4: 4293 cmp r3, r2 - 80057c6: d127 bne.n 8005818 + 8006452: 683b ldr r3, [r7, #0] + 8006454: 681b ldr r3, [r3, #0] + 8006456: 4a3a ldr r2, [pc, #232] ; (8006540 ) + 8006458: 4293 cmp r3, r2 + 800645a: d127 bne.n 80064ac && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) - 80057c8: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 80057cc: f403 0300 and.w r3, r3, #8388608 ; 0x800000 - 80057d0: 2b00 cmp r3, #0 - 80057d2: d121 bne.n 8005818 + 800645c: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8006460: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8006464: 2b00 cmp r3, #0 + 8006466: d121 bne.n 80064ac { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - 80057d4: 687b ldr r3, [r7, #4] - 80057d6: 681b ldr r3, [r3, #0] - 80057d8: 4a35 ldr r2, [pc, #212] ; (80058b0 ) - 80057da: 4293 cmp r3, r2 - 80057dc: d157 bne.n 800588e + 8006468: 687b ldr r3, [r7, #4] + 800646a: 681b ldr r3, [r3, #0] + 800646c: 4a35 ldr r2, [pc, #212] ; (8006544 ) + 800646e: 4293 cmp r3, r2 + 8006470: d157 bne.n 8006522 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 80057de: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 80057e2: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 - 80057e6: 4619 mov r1, r3 - 80057e8: 482f ldr r0, [pc, #188] ; (80058a8 ) - 80057ea: f7fe ff2a bl 8004642 + 8006472: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8006476: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 800647a: 4619 mov r1, r3 + 800647c: 482f ldr r0, [pc, #188] ; (800653c ) + 800647e: f7fe ff2a bl 80052d6 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 80057ee: 4b31 ldr r3, [pc, #196] ; (80058b4 ) - 80057f0: 681b ldr r3, [r3, #0] - 80057f2: 099b lsrs r3, r3, #6 - 80057f4: 4a30 ldr r2, [pc, #192] ; (80058b8 ) - 80057f6: fba2 2303 umull r2, r3, r2, r3 - 80057fa: 099b lsrs r3, r3, #6 - 80057fc: 1c5a adds r2, r3, #1 - 80057fe: 4613 mov r3, r2 - 8005800: 005b lsls r3, r3, #1 - 8005802: 4413 add r3, r2 - 8005804: 009b lsls r3, r3, #2 - 8005806: 60bb str r3, [r7, #8] + 8006482: 4b31 ldr r3, [pc, #196] ; (8006548 ) + 8006484: 681b ldr r3, [r3, #0] + 8006486: 099b lsrs r3, r3, #6 + 8006488: 4a30 ldr r2, [pc, #192] ; (800654c ) + 800648a: fba2 2303 umull r2, r3, r2, r3 + 800648e: 099b lsrs r3, r3, #6 + 8006490: 1c5a adds r2, r3, #1 + 8006492: 4613 mov r3, r2 + 8006494: 005b lsls r3, r3, #1 + 8006496: 4413 add r3, r2 + 8006498: 009b lsls r3, r3, #2 + 800649a: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 8005808: e002 b.n 8005810 + 800649c: e002 b.n 80064a4 { wait_loop_index--; - 800580a: 68bb ldr r3, [r7, #8] - 800580c: 3b01 subs r3, #1 - 800580e: 60bb str r3, [r7, #8] + 800649e: 68bb ldr r3, [r7, #8] + 80064a0: 3b01 subs r3, #1 + 80064a2: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 8005810: 68bb ldr r3, [r7, #8] - 8005812: 2b00 cmp r3, #0 - 8005814: d1f9 bne.n 800580a + 80064a4: 68bb ldr r3, [r7, #8] + 80064a6: 2b00 cmp r3, #0 + 80064a8: d1f9 bne.n 800649e if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - 8005816: e03a b.n 800588e + 80064aa: e03a b.n 8006522 } } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) - 8005818: 683b ldr r3, [r7, #0] - 800581a: 681b ldr r3, [r3, #0] - 800581c: 4a27 ldr r2, [pc, #156] ; (80058bc ) - 800581e: 4293 cmp r3, r2 - 8005820: d113 bne.n 800584a + 80064ac: 683b ldr r3, [r7, #0] + 80064ae: 681b ldr r3, [r3, #0] + 80064b0: 4a27 ldr r2, [pc, #156] ; (8006550 ) + 80064b2: 4293 cmp r3, r2 + 80064b4: d113 bne.n 80064de && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - 8005822: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8005826: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 - 800582a: 2b00 cmp r3, #0 - 800582c: d10d bne.n 800584a + 80064b6: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 80064ba: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 80064be: 2b00 cmp r3, #0 + 80064c0: d10d bne.n 80064de { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - 800582e: 687b ldr r3, [r7, #4] - 8005830: 681b ldr r3, [r3, #0] - 8005832: 4a1f ldr r2, [pc, #124] ; (80058b0 ) - 8005834: 4293 cmp r3, r2 - 8005836: d12a bne.n 800588e + 80064c2: 687b ldr r3, [r7, #4] + 80064c4: 681b ldr r3, [r3, #0] + 80064c6: 4a1f ldr r2, [pc, #124] ; (8006544 ) + 80064c8: 4293 cmp r3, r2 + 80064ca: d12a bne.n 8006522 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 8005838: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 800583c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 8005840: 4619 mov r1, r3 - 8005842: 4819 ldr r0, [pc, #100] ; (80058a8 ) - 8005844: f7fe fefd bl 8004642 + 80064cc: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 80064d0: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80064d4: 4619 mov r1, r3 + 80064d6: 4819 ldr r0, [pc, #100] ; (800653c ) + 80064d8: f7fe fefd bl 80052d6 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - 8005848: e021 b.n 800588e + 80064dc: e021 b.n 8006522 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) - 800584a: 683b ldr r3, [r7, #0] - 800584c: 681b ldr r3, [r3, #0] - 800584e: 4a1c ldr r2, [pc, #112] ; (80058c0 ) - 8005850: 4293 cmp r3, r2 - 8005852: d11c bne.n 800588e + 80064de: 683b ldr r3, [r7, #0] + 80064e0: 681b ldr r3, [r3, #0] + 80064e2: 4a1c ldr r2, [pc, #112] ; (8006554 ) + 80064e4: 4293 cmp r3, r2 + 80064e6: d11c bne.n 8006522 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - 8005854: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 8005858: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 800585c: 2b00 cmp r3, #0 - 800585e: d116 bne.n 800588e + 80064e8: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 80064ec: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80064f0: 2b00 cmp r3, #0 + 80064f2: d116 bne.n 8006522 { if (ADC_VREFINT_INSTANCE(hadc)) - 8005860: 687b ldr r3, [r7, #4] - 8005862: 681b ldr r3, [r3, #0] - 8005864: 4a12 ldr r2, [pc, #72] ; (80058b0 ) - 8005866: 4293 cmp r3, r2 - 8005868: d111 bne.n 800588e + 80064f4: 687b ldr r3, [r7, #4] + 80064f6: 681b ldr r3, [r3, #0] + 80064f8: 4a12 ldr r2, [pc, #72] ; (8006544 ) + 80064fa: 4293 cmp r3, r2 + 80064fc: d111 bne.n 8006522 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 800586a: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 800586e: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 - 8005872: 4619 mov r1, r3 - 8005874: 480c ldr r0, [pc, #48] ; (80058a8 ) - 8005876: f7fe fee4 bl 8004642 - 800587a: e008 b.n 800588e + 80064fe: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 8006502: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 8006506: 4619 mov r1, r3 + 8006508: 480c ldr r0, [pc, #48] ; (800653c ) + 800650a: f7fe fee4 bl 80052d6 + 800650e: e008 b.n 8006522 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 800587c: 687b ldr r3, [r7, #4] - 800587e: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005880: f043 0220 orr.w r2, r3, #32 - 8005884: 687b ldr r3, [r7, #4] - 8005886: 655a str r2, [r3, #84] ; 0x54 + 8006510: 687b ldr r3, [r7, #4] + 8006512: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006514: f043 0220 orr.w r2, r3, #32 + 8006518: 687b ldr r3, [r7, #4] + 800651a: 655a str r2, [r3, #84] ; 0x54 tmp_hal_status = HAL_ERROR; - 8005888: 2301 movs r3, #1 - 800588a: f887 30d7 strb.w r3, [r7, #215] ; 0xd7 + 800651c: 2301 movs r3, #1 + 800651e: f887 30d7 strb.w r3, [r7, #215] ; 0xd7 } /* Process unlocked */ __HAL_UNLOCK(hadc); - 800588e: 687b ldr r3, [r7, #4] - 8005890: 2200 movs r2, #0 - 8005892: f883 2050 strb.w r2, [r3, #80] ; 0x50 + 8006522: 687b ldr r3, [r7, #4] + 8006524: 2200 movs r2, #0 + 8006526: f883 2050 strb.w r2, [r3, #80] ; 0x50 /* Return function status */ return tmp_hal_status; - 8005896: f897 30d7 ldrb.w r3, [r7, #215] ; 0xd7 -} - 800589a: 4618 mov r0, r3 - 800589c: 37d8 adds r7, #216 ; 0xd8 - 800589e: 46bd mov sp, r7 - 80058a0: bd80 pop {r7, pc} - 80058a2: bf00 nop - 80058a4: 80080000 .word 0x80080000 - 80058a8: 50040300 .word 0x50040300 - 80058ac: c7520000 .word 0xc7520000 - 80058b0: 50040000 .word 0x50040000 - 80058b4: 20000020 .word 0x20000020 - 80058b8: 053e2d63 .word 0x053e2d63 - 80058bc: cb840000 .word 0xcb840000 - 80058c0: 80000001 .word 0x80000001 - -080058c4 : + 800652a: f897 30d7 ldrb.w r3, [r7, #215] ; 0xd7 +} + 800652e: 4618 mov r0, r3 + 8006530: 37d8 adds r7, #216 ; 0xd8 + 8006532: 46bd mov sp, r7 + 8006534: bd80 pop {r7, pc} + 8006536: bf00 nop + 8006538: 80080000 .word 0x80080000 + 800653c: 50040300 .word 0x50040300 + 8006540: c7520000 .word 0xc7520000 + 8006544: 50040000 .word 0x50040000 + 8006548: 20000020 .word 0x20000020 + 800654c: 053e2d63 .word 0x053e2d63 + 8006550: cb840000 .word 0xcb840000 + 8006554: 80000001 .word 0x80000001 + +08006558 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { - 80058c4: b580 push {r7, lr} - 80058c6: b084 sub sp, #16 - 80058c8: af00 add r7, sp, #0 - 80058ca: 6078 str r0, [r7, #4] + 8006558: b580 push {r7, lr} + 800655a: b084 sub sp, #16 + 800655c: af00 add r7, sp, #0 + 800655e: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t wait_loop_index = 0UL; - 80058cc: 2300 movs r3, #0 - 80058ce: 60bb str r3, [r7, #8] + 8006560: 2300 movs r3, #0 + 8006562: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 80058d0: 687b ldr r3, [r7, #4] - 80058d2: 681b ldr r3, [r3, #0] - 80058d4: 4618 mov r0, r3 - 80058d6: f7ff f82d bl 8004934 - 80058da: 4603 mov r3, r0 - 80058dc: 2b00 cmp r3, #0 - 80058de: d169 bne.n 80059b4 + 8006564: 687b ldr r3, [r7, #4] + 8006566: 681b ldr r3, [r3, #0] + 8006568: 4618 mov r0, r3 + 800656a: f7ff f82d bl 80055c8 + 800656e: 4603 mov r3, r0 + 8006570: 2b00 cmp r3, #0 + 8006572: d169 bne.n 8006648 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - 80058e0: 687b ldr r3, [r7, #4] - 80058e2: 681b ldr r3, [r3, #0] - 80058e4: 689a ldr r2, [r3, #8] - 80058e6: 4b36 ldr r3, [pc, #216] ; (80059c0 ) - 80058e8: 4013 ands r3, r2 - 80058ea: 2b00 cmp r3, #0 - 80058ec: d00d beq.n 800590a + 8006574: 687b ldr r3, [r7, #4] + 8006576: 681b ldr r3, [r3, #0] + 8006578: 689a ldr r2, [r3, #8] + 800657a: 4b36 ldr r3, [pc, #216] ; (8006654 ) + 800657c: 4013 ands r3, r2 + 800657e: 2b00 cmp r3, #0 + 8006580: d00d beq.n 800659e | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 80058ee: 687b ldr r3, [r7, #4] - 80058f0: 6d5b ldr r3, [r3, #84] ; 0x54 - 80058f2: f043 0210 orr.w r2, r3, #16 - 80058f6: 687b ldr r3, [r7, #4] - 80058f8: 655a str r2, [r3, #84] ; 0x54 + 8006582: 687b ldr r3, [r7, #4] + 8006584: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006586: f043 0210 orr.w r2, r3, #16 + 800658a: 687b ldr r3, [r7, #4] + 800658c: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80058fa: 687b ldr r3, [r7, #4] - 80058fc: 6d9b ldr r3, [r3, #88] ; 0x58 - 80058fe: f043 0201 orr.w r2, r3, #1 - 8005902: 687b ldr r3, [r7, #4] - 8005904: 659a str r2, [r3, #88] ; 0x58 + 800658e: 687b ldr r3, [r7, #4] + 8006590: 6d9b ldr r3, [r3, #88] ; 0x58 + 8006592: f043 0201 orr.w r2, r3, #1 + 8006596: 687b ldr r3, [r7, #4] + 8006598: 659a str r2, [r3, #88] ; 0x58 return HAL_ERROR; - 8005906: 2301 movs r3, #1 - 8005908: e055 b.n 80059b6 + 800659a: 2301 movs r3, #1 + 800659c: e055 b.n 800664a } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - 800590a: 687b ldr r3, [r7, #4] - 800590c: 681b ldr r3, [r3, #0] - 800590e: 4618 mov r0, r3 - 8005910: f7fe fffc bl 800490c + 800659e: 687b ldr r3, [r7, #4] + 80065a0: 681b ldr r3, [r3, #0] + 80065a2: 4618 mov r0, r3 + 80065a4: f7fe fffc bl 80055a0 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) - 8005914: 482b ldr r0, [pc, #172] ; (80059c4 ) - 8005916: f7fe fea7 bl 8004668 - 800591a: 4603 mov r3, r0 + 80065a8: 482b ldr r0, [pc, #172] ; (8006658 ) + 80065aa: f7fe fea7 bl 80052fc + 80065ae: 4603 mov r3, r0 & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) - 800591c: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80065b0: f403 0300 and.w r3, r3, #8388608 ; 0x800000 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) - 8005920: 2b00 cmp r3, #0 - 8005922: d013 beq.n 800594c + 80065b4: 2b00 cmp r3, #0 + 80065b6: d013 beq.n 80065e0 /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8005924: 4b28 ldr r3, [pc, #160] ; (80059c8 ) - 8005926: 681b ldr r3, [r3, #0] - 8005928: 099b lsrs r3, r3, #6 - 800592a: 4a28 ldr r2, [pc, #160] ; (80059cc ) - 800592c: fba2 2303 umull r2, r3, r2, r3 - 8005930: 099b lsrs r3, r3, #6 - 8005932: 1c5a adds r2, r3, #1 - 8005934: 4613 mov r3, r2 - 8005936: 005b lsls r3, r3, #1 - 8005938: 4413 add r3, r2 - 800593a: 009b lsls r3, r3, #2 - 800593c: 60bb str r3, [r7, #8] + 80065b8: 4b28 ldr r3, [pc, #160] ; (800665c ) + 80065ba: 681b ldr r3, [r3, #0] + 80065bc: 099b lsrs r3, r3, #6 + 80065be: 4a28 ldr r2, [pc, #160] ; (8006660 ) + 80065c0: fba2 2303 umull r2, r3, r2, r3 + 80065c4: 099b lsrs r3, r3, #6 + 80065c6: 1c5a adds r2, r3, #1 + 80065c8: 4613 mov r3, r2 + 80065ca: 005b lsls r3, r3, #1 + 80065cc: 4413 add r3, r2 + 80065ce: 009b lsls r3, r3, #2 + 80065d0: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 800593e: e002 b.n 8005946 + 80065d2: e002 b.n 80065da { wait_loop_index--; - 8005940: 68bb ldr r3, [r7, #8] - 8005942: 3b01 subs r3, #1 - 8005944: 60bb str r3, [r7, #8] + 80065d4: 68bb ldr r3, [r7, #8] + 80065d6: 3b01 subs r3, #1 + 80065d8: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 8005946: 68bb ldr r3, [r7, #8] - 8005948: 2b00 cmp r3, #0 - 800594a: d1f9 bne.n 8005940 + 80065da: 68bb ldr r3, [r7, #8] + 80065dc: 2b00 cmp r3, #0 + 80065de: d1f9 bne.n 80065d4 } } /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - 800594c: f7fe fe36 bl 80045bc - 8005950: 60f8 str r0, [r7, #12] + 80065e0: f7fe fe36 bl 8005250 + 80065e4: 60f8 str r0, [r7, #12] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 8005952: e028 b.n 80059a6 + 80065e6: e028 b.n 800663a The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8005954: 687b ldr r3, [r7, #4] - 8005956: 681b ldr r3, [r3, #0] - 8005958: 4618 mov r0, r3 - 800595a: f7fe ffeb bl 8004934 - 800595e: 4603 mov r3, r0 - 8005960: 2b00 cmp r3, #0 - 8005962: d104 bne.n 800596e + 80065e8: 687b ldr r3, [r7, #4] + 80065ea: 681b ldr r3, [r3, #0] + 80065ec: 4618 mov r0, r3 + 80065ee: f7fe ffeb bl 80055c8 + 80065f2: 4603 mov r3, r0 + 80065f4: 2b00 cmp r3, #0 + 80065f6: d104 bne.n 8006602 { LL_ADC_Enable(hadc->Instance); - 8005964: 687b ldr r3, [r7, #4] - 8005966: 681b ldr r3, [r3, #0] - 8005968: 4618 mov r0, r3 - 800596a: f7fe ffcf bl 800490c + 80065f8: 687b ldr r3, [r7, #4] + 80065fa: 681b ldr r3, [r3, #0] + 80065fc: 4618 mov r0, r3 + 80065fe: f7fe ffcf bl 80055a0 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - 800596e: f7fe fe25 bl 80045bc - 8005972: 4602 mov r2, r0 - 8005974: 68fb ldr r3, [r7, #12] - 8005976: 1ad3 subs r3, r2, r3 - 8005978: 2b02 cmp r3, #2 - 800597a: d914 bls.n 80059a6 + 8006602: f7fe fe25 bl 8005250 + 8006606: 4602 mov r2, r0 + 8006608: 68fb ldr r3, [r7, #12] + 800660a: 1ad3 subs r3, r2, r3 + 800660c: 2b02 cmp r3, #2 + 800660e: d914 bls.n 800663a { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 800597c: 687b ldr r3, [r7, #4] - 800597e: 681b ldr r3, [r3, #0] - 8005980: 681b ldr r3, [r3, #0] - 8005982: f003 0301 and.w r3, r3, #1 - 8005986: 2b01 cmp r3, #1 - 8005988: d00d beq.n 80059a6 + 8006610: 687b ldr r3, [r7, #4] + 8006612: 681b ldr r3, [r3, #0] + 8006614: 681b ldr r3, [r3, #0] + 8006616: f003 0301 and.w r3, r3, #1 + 800661a: 2b01 cmp r3, #1 + 800661c: d00d beq.n 800663a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800598a: 687b ldr r3, [r7, #4] - 800598c: 6d5b ldr r3, [r3, #84] ; 0x54 - 800598e: f043 0210 orr.w r2, r3, #16 - 8005992: 687b ldr r3, [r7, #4] - 8005994: 655a str r2, [r3, #84] ; 0x54 + 800661e: 687b ldr r3, [r7, #4] + 8006620: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006622: f043 0210 orr.w r2, r3, #16 + 8006626: 687b ldr r3, [r7, #4] + 8006628: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8005996: 687b ldr r3, [r7, #4] - 8005998: 6d9b ldr r3, [r3, #88] ; 0x58 - 800599a: f043 0201 orr.w r2, r3, #1 - 800599e: 687b ldr r3, [r7, #4] - 80059a0: 659a str r2, [r3, #88] ; 0x58 + 800662a: 687b ldr r3, [r7, #4] + 800662c: 6d9b ldr r3, [r3, #88] ; 0x58 + 800662e: f043 0201 orr.w r2, r3, #1 + 8006632: 687b ldr r3, [r7, #4] + 8006634: 659a str r2, [r3, #88] ; 0x58 return HAL_ERROR; - 80059a2: 2301 movs r3, #1 - 80059a4: e007 b.n 80059b6 + 8006636: 2301 movs r3, #1 + 8006638: e007 b.n 800664a while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 80059a6: 687b ldr r3, [r7, #4] - 80059a8: 681b ldr r3, [r3, #0] - 80059aa: 681b ldr r3, [r3, #0] - 80059ac: f003 0301 and.w r3, r3, #1 - 80059b0: 2b01 cmp r3, #1 - 80059b2: d1cf bne.n 8005954 + 800663a: 687b ldr r3, [r7, #4] + 800663c: 681b ldr r3, [r3, #0] + 800663e: 681b ldr r3, [r3, #0] + 8006640: f003 0301 and.w r3, r3, #1 + 8006644: 2b01 cmp r3, #1 + 8006646: d1cf bne.n 80065e8 } } } /* Return HAL status */ return HAL_OK; - 80059b4: 2300 movs r3, #0 -} - 80059b6: 4618 mov r0, r3 - 80059b8: 3710 adds r7, #16 - 80059ba: 46bd mov sp, r7 - 80059bc: bd80 pop {r7, pc} - 80059be: bf00 nop - 80059c0: 8000003f .word 0x8000003f - 80059c4: 50040300 .word 0x50040300 - 80059c8: 20000020 .word 0x20000020 - 80059cc: 053e2d63 .word 0x053e2d63 - -080059d0 : + 8006648: 2300 movs r3, #0 +} + 800664a: 4618 mov r0, r3 + 800664c: 3710 adds r7, #16 + 800664e: 46bd mov sp, r7 + 8006650: bd80 pop {r7, pc} + 8006652: bf00 nop + 8006654: 8000003f .word 0x8000003f + 8006658: 50040300 .word 0x50040300 + 800665c: 20000020 .word 0x20000020 + 8006660: 053e2d63 .word 0x053e2d63 + +08006664 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { - 80059d0: b580 push {r7, lr} - 80059d2: b084 sub sp, #16 - 80059d4: af00 add r7, sp, #0 - 80059d6: 6078 str r0, [r7, #4] + 8006664: b580 push {r7, lr} + 8006666: b084 sub sp, #16 + 8006668: af00 add r7, sp, #0 + 800666a: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - 80059d8: 687b ldr r3, [r7, #4] - 80059da: 6a9b ldr r3, [r3, #40] ; 0x28 - 80059dc: 60fb str r3, [r7, #12] + 800666c: 687b ldr r3, [r7, #4] + 800666e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006670: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) - 80059de: 68fb ldr r3, [r7, #12] - 80059e0: 6d5b ldr r3, [r3, #84] ; 0x54 - 80059e2: f003 0350 and.w r3, r3, #80 ; 0x50 - 80059e6: 2b00 cmp r3, #0 - 80059e8: d14b bne.n 8005a82 + 8006672: 68fb ldr r3, [r7, #12] + 8006674: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006676: f003 0350 and.w r3, r3, #80 ; 0x50 + 800667a: 2b00 cmp r3, #0 + 800667c: d14b bne.n 8006716 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 80059ea: 68fb ldr r3, [r7, #12] - 80059ec: 6d5b ldr r3, [r3, #84] ; 0x54 - 80059ee: f443 7200 orr.w r2, r3, #512 ; 0x200 - 80059f2: 68fb ldr r3, [r7, #12] - 80059f4: 655a str r2, [r3, #84] ; 0x54 + 800667e: 68fb ldr r3, [r7, #12] + 8006680: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006682: f443 7200 orr.w r2, r3, #512 ; 0x200 + 8006686: 68fb ldr r3, [r7, #12] + 8006688: 655a str r2, [r3, #84] ; 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) - 80059f6: 68fb ldr r3, [r7, #12] - 80059f8: 681b ldr r3, [r3, #0] - 80059fa: 681b ldr r3, [r3, #0] - 80059fc: f003 0308 and.w r3, r3, #8 - 8005a00: 2b00 cmp r3, #0 - 8005a02: d021 beq.n 8005a48 + 800668a: 68fb ldr r3, [r7, #12] + 800668c: 681b ldr r3, [r3, #0] + 800668e: 681b ldr r3, [r3, #0] + 8006690: f003 0308 and.w r3, r3, #8 + 8006694: 2b00 cmp r3, #0 + 8006696: d021 beq.n 80066dc { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - 8005a04: 68fb ldr r3, [r7, #12] - 8005a06: 681b ldr r3, [r3, #0] - 8005a08: 4618 mov r0, r3 - 8005a0a: f7fe fe90 bl 800472e - 8005a0e: 4603 mov r3, r0 - 8005a10: 2b00 cmp r3, #0 - 8005a12: d032 beq.n 8005a7a + 8006698: 68fb ldr r3, [r7, #12] + 800669a: 681b ldr r3, [r3, #0] + 800669c: 4618 mov r0, r3 + 800669e: f7fe fe90 bl 80053c2 + 80066a2: 4603 mov r3, r0 + 80066a4: 2b00 cmp r3, #0 + 80066a6: d032 beq.n 800670e { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) - 8005a14: 68fb ldr r3, [r7, #12] - 8005a16: 681b ldr r3, [r3, #0] - 8005a18: 68db ldr r3, [r3, #12] - 8005a1a: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8005a1e: 2b00 cmp r3, #0 - 8005a20: d12b bne.n 8005a7a + 80066a8: 68fb ldr r3, [r7, #12] + 80066aa: 681b ldr r3, [r3, #0] + 80066ac: 68db ldr r3, [r3, #12] + 80066ae: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 80066b2: 2b00 cmp r3, #0 + 80066b4: d12b bne.n 800670e { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 8005a22: 68fb ldr r3, [r7, #12] - 8005a24: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a26: f423 7280 bic.w r2, r3, #256 ; 0x100 - 8005a2a: 68fb ldr r3, [r7, #12] - 8005a2c: 655a str r2, [r3, #84] ; 0x54 + 80066b6: 68fb ldr r3, [r7, #12] + 80066b8: 6d5b ldr r3, [r3, #84] ; 0x54 + 80066ba: f423 7280 bic.w r2, r3, #256 ; 0x100 + 80066be: 68fb ldr r3, [r7, #12] + 80066c0: 655a str r2, [r3, #84] ; 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - 8005a2e: 68fb ldr r3, [r7, #12] - 8005a30: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a32: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8005a36: 2b00 cmp r3, #0 - 8005a38: d11f bne.n 8005a7a + 80066c2: 68fb ldr r3, [r7, #12] + 80066c4: 6d5b ldr r3, [r3, #84] ; 0x54 + 80066c6: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 80066ca: 2b00 cmp r3, #0 + 80066cc: d11f bne.n 800670e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8005a3a: 68fb ldr r3, [r7, #12] - 8005a3c: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a3e: f043 0201 orr.w r2, r3, #1 - 8005a42: 68fb ldr r3, [r7, #12] - 8005a44: 655a str r2, [r3, #84] ; 0x54 - 8005a46: e018 b.n 8005a7a + 80066ce: 68fb ldr r3, [r7, #12] + 80066d0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80066d2: f043 0201 orr.w r2, r3, #1 + 80066d6: 68fb ldr r3, [r7, #12] + 80066d8: 655a str r2, [r3, #84] ; 0x54 + 80066da: e018 b.n 800670e } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) - 8005a48: 68fb ldr r3, [r7, #12] - 8005a4a: 681b ldr r3, [r3, #0] - 8005a4c: 68db ldr r3, [r3, #12] - 8005a4e: f003 0302 and.w r3, r3, #2 - 8005a52: 2b00 cmp r3, #0 - 8005a54: d111 bne.n 8005a7a + 80066dc: 68fb ldr r3, [r7, #12] + 80066de: 681b ldr r3, [r3, #0] + 80066e0: 68db ldr r3, [r3, #12] + 80066e2: f003 0302 and.w r3, r3, #2 + 80066e6: 2b00 cmp r3, #0 + 80066e8: d111 bne.n 800670e { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 8005a56: 68fb ldr r3, [r7, #12] - 8005a58: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a5a: f423 7280 bic.w r2, r3, #256 ; 0x100 - 8005a5e: 68fb ldr r3, [r7, #12] - 8005a60: 655a str r2, [r3, #84] ; 0x54 + 80066ea: 68fb ldr r3, [r7, #12] + 80066ec: 6d5b ldr r3, [r3, #84] ; 0x54 + 80066ee: f423 7280 bic.w r2, r3, #256 ; 0x100 + 80066f2: 68fb ldr r3, [r7, #12] + 80066f4: 655a str r2, [r3, #84] ; 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - 8005a62: 68fb ldr r3, [r7, #12] - 8005a64: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a66: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8005a6a: 2b00 cmp r3, #0 - 8005a6c: d105 bne.n 8005a7a + 80066f6: 68fb ldr r3, [r7, #12] + 80066f8: 6d5b ldr r3, [r3, #84] ; 0x54 + 80066fa: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 80066fe: 2b00 cmp r3, #0 + 8006700: d105 bne.n 800670e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 8005a6e: 68fb ldr r3, [r7, #12] - 8005a70: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a72: f043 0201 orr.w r2, r3, #1 - 8005a76: 68fb ldr r3, [r7, #12] - 8005a78: 655a str r2, [r3, #84] ; 0x54 + 8006702: 68fb ldr r3, [r7, #12] + 8006704: 6d5b ldr r3, [r3, #84] ; 0x54 + 8006706: f043 0201 orr.w r2, r3, #1 + 800670a: 68fb ldr r3, [r7, #12] + 800670c: 655a str r2, [r3, #84] ; 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); - 8005a7a: 68f8 ldr r0, [r7, #12] - 8005a7c: f7fb fb48 bl 8001110 + 800670e: 68f8 ldr r0, [r7, #12] + 8006710: f7fa fd6a bl 80011e8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } - 8005a80: e00e b.n 8005aa0 + 8006714: e00e b.n 8006734 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) - 8005a82: 68fb ldr r3, [r7, #12] - 8005a84: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005a86: f003 0310 and.w r3, r3, #16 - 8005a8a: 2b00 cmp r3, #0 - 8005a8c: d003 beq.n 8005a96 + 8006716: 68fb ldr r3, [r7, #12] + 8006718: 6d5b ldr r3, [r3, #84] ; 0x54 + 800671a: f003 0310 and.w r3, r3, #16 + 800671e: 2b00 cmp r3, #0 + 8006720: d003 beq.n 800672a HAL_ADC_ErrorCallback(hadc); - 8005a8e: 68f8 ldr r0, [r7, #12] - 8005a90: f7ff fb2c bl 80050ec + 8006722: 68f8 ldr r0, [r7, #12] + 8006724: f7ff fb2c bl 8005d80 } - 8005a94: e004 b.n 8005aa0 + 8006728: e004 b.n 8006734 hadc->DMA_Handle->XferErrorCallback(hdma); - 8005a96: 68fb ldr r3, [r7, #12] - 8005a98: 6cdb ldr r3, [r3, #76] ; 0x4c - 8005a9a: 6b5b ldr r3, [r3, #52] ; 0x34 - 8005a9c: 6878 ldr r0, [r7, #4] - 8005a9e: 4798 blx r3 -} - 8005aa0: bf00 nop - 8005aa2: 3710 adds r7, #16 - 8005aa4: 46bd mov sp, r7 - 8005aa6: bd80 pop {r7, pc} - -08005aa8 : + 800672a: 68fb ldr r3, [r7, #12] + 800672c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800672e: 6b5b ldr r3, [r3, #52] ; 0x34 + 8006730: 6878 ldr r0, [r7, #4] + 8006732: 4798 blx r3 +} + 8006734: bf00 nop + 8006736: 3710 adds r7, #16 + 8006738: 46bd mov sp, r7 + 800673a: bd80 pop {r7, pc} + +0800673c : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - 8005aa8: b580 push {r7, lr} - 8005aaa: b084 sub sp, #16 - 8005aac: af00 add r7, sp, #0 - 8005aae: 6078 str r0, [r7, #4] + 800673c: b580 push {r7, lr} + 800673e: b084 sub sp, #16 + 8006740: af00 add r7, sp, #0 + 8006742: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - 8005ab0: 687b ldr r3, [r7, #4] - 8005ab2: 6a9b ldr r3, [r3, #40] ; 0x28 - 8005ab4: 60fb str r3, [r7, #12] + 8006744: 687b ldr r3, [r7, #4] + 8006746: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006748: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); - 8005ab6: 68f8 ldr r0, [r7, #12] - 8005ab8: f7ff fb04 bl 80050c4 + 800674a: 68f8 ldr r0, [r7, #12] + 800674c: f7ff fb04 bl 8005d58 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - 8005abc: bf00 nop - 8005abe: 3710 adds r7, #16 - 8005ac0: 46bd mov sp, r7 - 8005ac2: bd80 pop {r7, pc} + 8006750: bf00 nop + 8006752: 3710 adds r7, #16 + 8006754: 46bd mov sp, r7 + 8006756: bd80 pop {r7, pc} -08005ac4 : +08006758 : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { - 8005ac4: b580 push {r7, lr} - 8005ac6: b084 sub sp, #16 - 8005ac8: af00 add r7, sp, #0 - 8005aca: 6078 str r0, [r7, #4] + 8006758: b580 push {r7, lr} + 800675a: b084 sub sp, #16 + 800675c: af00 add r7, sp, #0 + 800675e: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - 8005acc: 687b ldr r3, [r7, #4] - 8005ace: 6a9b ldr r3, [r3, #40] ; 0x28 - 8005ad0: 60fb str r3, [r7, #12] + 8006760: 687b ldr r3, [r7, #4] + 8006762: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006764: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - 8005ad2: 68fb ldr r3, [r7, #12] - 8005ad4: 6d5b ldr r3, [r3, #84] ; 0x54 - 8005ad6: f043 0240 orr.w r2, r3, #64 ; 0x40 - 8005ada: 68fb ldr r3, [r7, #12] - 8005adc: 655a str r2, [r3, #84] ; 0x54 + 8006766: 68fb ldr r3, [r7, #12] + 8006768: 6d5b ldr r3, [r3, #84] ; 0x54 + 800676a: f043 0240 orr.w r2, r3, #64 ; 0x40 + 800676e: 68fb ldr r3, [r7, #12] + 8006770: 655a str r2, [r3, #84] ; 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - 8005ade: 68fb ldr r3, [r7, #12] - 8005ae0: 6d9b ldr r3, [r3, #88] ; 0x58 - 8005ae2: f043 0204 orr.w r2, r3, #4 - 8005ae6: 68fb ldr r3, [r7, #12] - 8005ae8: 659a str r2, [r3, #88] ; 0x58 + 8006772: 68fb ldr r3, [r7, #12] + 8006774: 6d9b ldr r3, [r3, #88] ; 0x58 + 8006776: f043 0204 orr.w r2, r3, #4 + 800677a: 68fb ldr r3, [r7, #12] + 800677c: 659a str r2, [r3, #88] ; 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); - 8005aea: 68f8 ldr r0, [r7, #12] - 8005aec: f7ff fafe bl 80050ec + 800677e: 68f8 ldr r0, [r7, #12] + 8006780: f7ff fafe bl 8005d80 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - 8005af0: bf00 nop - 8005af2: 3710 adds r7, #16 - 8005af4: 46bd mov sp, r7 - 8005af6: bd80 pop {r7, pc} + 8006784: bf00 nop + 8006786: 3710 adds r7, #16 + 8006788: 46bd mov sp, r7 + 800678a: bd80 pop {r7, pc} -08005af8 : +0800678c : * @brief Injected conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { - 8005af8: b480 push {r7} - 8005afa: b083 sub sp, #12 - 8005afc: af00 add r7, sp, #0 - 8005afe: 6078 str r0, [r7, #4] + 800678c: b480 push {r7} + 800678e: b083 sub sp, #12 + 8006790: af00 add r7, sp, #0 + 8006792: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ } - 8005b00: bf00 nop - 8005b02: 370c adds r7, #12 - 8005b04: 46bd mov sp, r7 - 8005b06: f85d 7b04 ldr.w r7, [sp], #4 - 8005b0a: 4770 bx lr + 8006794: bf00 nop + 8006796: 370c adds r7, #12 + 8006798: 46bd mov sp, r7 + 800679a: f85d 7b04 ldr.w r7, [sp], #4 + 800679e: 4770 bx lr -08005b0c : +080067a0 : contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { - 8005b0c: b480 push {r7} - 8005b0e: b083 sub sp, #12 - 8005b10: af00 add r7, sp, #0 - 8005b12: 6078 str r0, [r7, #4] + 80067a0: b480 push {r7} + 80067a2: b083 sub sp, #12 + 80067a4: af00 add r7, sp, #0 + 80067a6: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } - 8005b14: bf00 nop - 8005b16: 370c adds r7, #12 - 8005b18: 46bd mov sp, r7 - 8005b1a: f85d 7b04 ldr.w r7, [sp], #4 - 8005b1e: 4770 bx lr + 80067a8: bf00 nop + 80067aa: 370c adds r7, #12 + 80067ac: 46bd mov sp, r7 + 80067ae: f85d 7b04 ldr.w r7, [sp], #4 + 80067b2: 4770 bx lr -08005b20 : +080067b4 : * @brief Analog watchdog 2 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { - 8005b20: b480 push {r7} - 8005b22: b083 sub sp, #12 - 8005b24: af00 add r7, sp, #0 - 8005b26: 6078 str r0, [r7, #4] + 80067b4: b480 push {r7} + 80067b6: b083 sub sp, #12 + 80067b8: af00 add r7, sp, #0 + 80067ba: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ } - 8005b28: bf00 nop - 8005b2a: 370c adds r7, #12 - 8005b2c: 46bd mov sp, r7 - 8005b2e: f85d 7b04 ldr.w r7, [sp], #4 - 8005b32: 4770 bx lr + 80067bc: bf00 nop + 80067be: 370c adds r7, #12 + 80067c0: 46bd mov sp, r7 + 80067c2: f85d 7b04 ldr.w r7, [sp], #4 + 80067c6: 4770 bx lr -08005b34 : +080067c8 : * @brief Analog watchdog 3 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { - 8005b34: b480 push {r7} - 8005b36: b083 sub sp, #12 - 8005b38: af00 add r7, sp, #0 - 8005b3a: 6078 str r0, [r7, #4] + 80067c8: b480 push {r7} + 80067ca: b083 sub sp, #12 + 80067cc: af00 add r7, sp, #0 + 80067ce: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ } - 8005b3c: bf00 nop - 8005b3e: 370c adds r7, #12 - 8005b40: 46bd mov sp, r7 - 8005b42: f85d 7b04 ldr.w r7, [sp], #4 - 8005b46: 4770 bx lr + 80067d0: bf00 nop + 80067d2: 370c adds r7, #12 + 80067d4: 46bd mov sp, r7 + 80067d6: f85d 7b04 ldr.w r7, [sp], #4 + 80067da: 4770 bx lr -08005b48 : +080067dc : * @brief End Of Sampling callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { - 8005b48: b480 push {r7} - 8005b4a: b083 sub sp, #12 - 8005b4c: af00 add r7, sp, #0 - 8005b4e: 6078 str r0, [r7, #4] + 80067dc: b480 push {r7} + 80067de: b083 sub sp, #12 + 80067e0: af00 add r7, sp, #0 + 80067e2: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } - 8005b50: bf00 nop - 8005b52: 370c adds r7, #12 - 8005b54: 46bd mov sp, r7 - 8005b56: f85d 7b04 ldr.w r7, [sp], #4 - 8005b5a: 4770 bx lr + 80067e4: bf00 nop + 80067e6: 370c adds r7, #12 + 80067e8: 46bd mov sp, r7 + 80067ea: f85d 7b04 ldr.w r7, [sp], #4 + 80067ee: 4770 bx lr -08005b5c <__NVIC_SetPriorityGrouping>: +080067f0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8005b5c: b480 push {r7} - 8005b5e: b085 sub sp, #20 - 8005b60: af00 add r7, sp, #0 - 8005b62: 6078 str r0, [r7, #4] + 80067f0: b480 push {r7} + 80067f2: b085 sub sp, #20 + 80067f4: af00 add r7, sp, #0 + 80067f6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8005b64: 687b ldr r3, [r7, #4] - 8005b66: f003 0307 and.w r3, r3, #7 - 8005b6a: 60fb str r3, [r7, #12] + 80067f8: 687b ldr r3, [r7, #4] + 80067fa: f003 0307 and.w r3, r3, #7 + 80067fe: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8005b6c: 4b0c ldr r3, [pc, #48] ; (8005ba0 <__NVIC_SetPriorityGrouping+0x44>) - 8005b6e: 68db ldr r3, [r3, #12] - 8005b70: 60bb str r3, [r7, #8] + 8006800: 4b0c ldr r3, [pc, #48] ; (8006834 <__NVIC_SetPriorityGrouping+0x44>) + 8006802: 68db ldr r3, [r3, #12] + 8006804: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8005b72: 68ba ldr r2, [r7, #8] - 8005b74: f64f 03ff movw r3, #63743 ; 0xf8ff - 8005b78: 4013 ands r3, r2 - 8005b7a: 60bb str r3, [r7, #8] + 8006806: 68ba ldr r2, [r7, #8] + 8006808: f64f 03ff movw r3, #63743 ; 0xf8ff + 800680c: 4013 ands r3, r2 + 800680e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8005b7c: 68fb ldr r3, [r7, #12] - 8005b7e: 021a lsls r2, r3, #8 + 8006810: 68fb ldr r3, [r7, #12] + 8006812: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8005b80: 68bb ldr r3, [r7, #8] - 8005b82: 4313 orrs r3, r2 + 8006814: 68bb ldr r3, [r7, #8] + 8006816: 4313 orrs r3, r2 reg_value = (reg_value | - 8005b84: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 - 8005b88: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8005b8c: 60bb str r3, [r7, #8] + 8006818: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 800681c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8006820: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8005b8e: 4a04 ldr r2, [pc, #16] ; (8005ba0 <__NVIC_SetPriorityGrouping+0x44>) - 8005b90: 68bb ldr r3, [r7, #8] - 8005b92: 60d3 str r3, [r2, #12] -} - 8005b94: bf00 nop - 8005b96: 3714 adds r7, #20 - 8005b98: 46bd mov sp, r7 - 8005b9a: f85d 7b04 ldr.w r7, [sp], #4 - 8005b9e: 4770 bx lr - 8005ba0: e000ed00 .word 0xe000ed00 - -08005ba4 <__NVIC_GetPriorityGrouping>: + 8006822: 4a04 ldr r2, [pc, #16] ; (8006834 <__NVIC_SetPriorityGrouping+0x44>) + 8006824: 68bb ldr r3, [r7, #8] + 8006826: 60d3 str r3, [r2, #12] +} + 8006828: bf00 nop + 800682a: 3714 adds r7, #20 + 800682c: 46bd mov sp, r7 + 800682e: f85d 7b04 ldr.w r7, [sp], #4 + 8006832: 4770 bx lr + 8006834: e000ed00 .word 0xe000ed00 + +08006838 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8005ba4: b480 push {r7} - 8005ba6: af00 add r7, sp, #0 + 8006838: b480 push {r7} + 800683a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8005ba8: 4b04 ldr r3, [pc, #16] ; (8005bbc <__NVIC_GetPriorityGrouping+0x18>) - 8005baa: 68db ldr r3, [r3, #12] - 8005bac: 0a1b lsrs r3, r3, #8 - 8005bae: f003 0307 and.w r3, r3, #7 -} - 8005bb2: 4618 mov r0, r3 - 8005bb4: 46bd mov sp, r7 - 8005bb6: f85d 7b04 ldr.w r7, [sp], #4 - 8005bba: 4770 bx lr - 8005bbc: e000ed00 .word 0xe000ed00 - -08005bc0 <__NVIC_EnableIRQ>: + 800683c: 4b04 ldr r3, [pc, #16] ; (8006850 <__NVIC_GetPriorityGrouping+0x18>) + 800683e: 68db ldr r3, [r3, #12] + 8006840: 0a1b lsrs r3, r3, #8 + 8006842: f003 0307 and.w r3, r3, #7 +} + 8006846: 4618 mov r0, r3 + 8006848: 46bd mov sp, r7 + 800684a: f85d 7b04 ldr.w r7, [sp], #4 + 800684e: 4770 bx lr + 8006850: e000ed00 .word 0xe000ed00 + +08006854 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 8005bc0: b480 push {r7} - 8005bc2: b083 sub sp, #12 - 8005bc4: af00 add r7, sp, #0 - 8005bc6: 4603 mov r3, r0 - 8005bc8: 71fb strb r3, [r7, #7] + 8006854: b480 push {r7} + 8006856: b083 sub sp, #12 + 8006858: af00 add r7, sp, #0 + 800685a: 4603 mov r3, r0 + 800685c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8005bca: f997 3007 ldrsb.w r3, [r7, #7] - 8005bce: 2b00 cmp r3, #0 - 8005bd0: db0b blt.n 8005bea <__NVIC_EnableIRQ+0x2a> + 800685e: f997 3007 ldrsb.w r3, [r7, #7] + 8006862: 2b00 cmp r3, #0 + 8006864: db0b blt.n 800687e <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8005bd2: 79fb ldrb r3, [r7, #7] - 8005bd4: f003 021f and.w r2, r3, #31 - 8005bd8: 4907 ldr r1, [pc, #28] ; (8005bf8 <__NVIC_EnableIRQ+0x38>) - 8005bda: f997 3007 ldrsb.w r3, [r7, #7] - 8005bde: 095b lsrs r3, r3, #5 - 8005be0: 2001 movs r0, #1 - 8005be2: fa00 f202 lsl.w r2, r0, r2 - 8005be6: f841 2023 str.w r2, [r1, r3, lsl #2] + 8006866: 79fb ldrb r3, [r7, #7] + 8006868: f003 021f and.w r2, r3, #31 + 800686c: 4907 ldr r1, [pc, #28] ; (800688c <__NVIC_EnableIRQ+0x38>) + 800686e: f997 3007 ldrsb.w r3, [r7, #7] + 8006872: 095b lsrs r3, r3, #5 + 8006874: 2001 movs r0, #1 + 8006876: fa00 f202 lsl.w r2, r0, r2 + 800687a: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } - 8005bea: bf00 nop - 8005bec: 370c adds r7, #12 - 8005bee: 46bd mov sp, r7 - 8005bf0: f85d 7b04 ldr.w r7, [sp], #4 - 8005bf4: 4770 bx lr - 8005bf6: bf00 nop - 8005bf8: e000e100 .word 0xe000e100 + 800687e: bf00 nop + 8006880: 370c adds r7, #12 + 8006882: 46bd mov sp, r7 + 8006884: f85d 7b04 ldr.w r7, [sp], #4 + 8006888: 4770 bx lr + 800688a: bf00 nop + 800688c: e000e100 .word 0xe000e100 -08005bfc <__NVIC_DisableIRQ>: - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - 8005bfc: b480 push {r7} - 8005bfe: b083 sub sp, #12 - 8005c00: af00 add r7, sp, #0 - 8005c02: 4603 mov r3, r0 - 8005c04: 71fb strb r3, [r7, #7] - if ((int32_t)(IRQn) >= 0) - 8005c06: f997 3007 ldrsb.w r3, [r7, #7] - 8005c0a: 2b00 cmp r3, #0 - 8005c0c: db12 blt.n 8005c34 <__NVIC_DisableIRQ+0x38> - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8005c0e: 79fb ldrb r3, [r7, #7] - 8005c10: f003 021f and.w r2, r3, #31 - 8005c14: 490a ldr r1, [pc, #40] ; (8005c40 <__NVIC_DisableIRQ+0x44>) - 8005c16: f997 3007 ldrsb.w r3, [r7, #7] - 8005c1a: 095b lsrs r3, r3, #5 - 8005c1c: 2001 movs r0, #1 - 8005c1e: fa00 f202 lsl.w r2, r0, r2 - 8005c22: 3320 adds r3, #32 - 8005c24: f841 2023 str.w r2, [r1, r3, lsl #2] - __ASM volatile ("dsb 0xF":::"memory"); - 8005c28: f3bf 8f4f dsb sy -} - 8005c2c: bf00 nop - __ASM volatile ("isb 0xF":::"memory"); - 8005c2e: f3bf 8f6f isb sy -} - 8005c32: bf00 nop - __DSB(); - __ISB(); - } -} - 8005c34: bf00 nop - 8005c36: 370c adds r7, #12 - 8005c38: 46bd mov sp, r7 - 8005c3a: f85d 7b04 ldr.w r7, [sp], #4 - 8005c3e: 4770 bx lr - 8005c40: e000e100 .word 0xe000e100 - -08005c44 <__NVIC_SetPriority>: +08006890 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8005c44: b480 push {r7} - 8005c46: b083 sub sp, #12 - 8005c48: af00 add r7, sp, #0 - 8005c4a: 4603 mov r3, r0 - 8005c4c: 6039 str r1, [r7, #0] - 8005c4e: 71fb strb r3, [r7, #7] + 8006890: b480 push {r7} + 8006892: b083 sub sp, #12 + 8006894: af00 add r7, sp, #0 + 8006896: 4603 mov r3, r0 + 8006898: 6039 str r1, [r7, #0] + 800689a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8005c50: f997 3007 ldrsb.w r3, [r7, #7] - 8005c54: 2b00 cmp r3, #0 - 8005c56: db0a blt.n 8005c6e <__NVIC_SetPriority+0x2a> + 800689c: f997 3007 ldrsb.w r3, [r7, #7] + 80068a0: 2b00 cmp r3, #0 + 80068a2: db0a blt.n 80068ba <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8005c58: 683b ldr r3, [r7, #0] - 8005c5a: b2da uxtb r2, r3 - 8005c5c: 490c ldr r1, [pc, #48] ; (8005c90 <__NVIC_SetPriority+0x4c>) - 8005c5e: f997 3007 ldrsb.w r3, [r7, #7] - 8005c62: 0112 lsls r2, r2, #4 - 8005c64: b2d2 uxtb r2, r2 - 8005c66: 440b add r3, r1 - 8005c68: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 80068a4: 683b ldr r3, [r7, #0] + 80068a6: b2da uxtb r2, r3 + 80068a8: 490c ldr r1, [pc, #48] ; (80068dc <__NVIC_SetPriority+0x4c>) + 80068aa: f997 3007 ldrsb.w r3, [r7, #7] + 80068ae: 0112 lsls r2, r2, #4 + 80068b0: b2d2 uxtb r2, r2 + 80068b2: 440b add r3, r1 + 80068b4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8005c6c: e00a b.n 8005c84 <__NVIC_SetPriority+0x40> + 80068b8: e00a b.n 80068d0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8005c6e: 683b ldr r3, [r7, #0] - 8005c70: b2da uxtb r2, r3 - 8005c72: 4908 ldr r1, [pc, #32] ; (8005c94 <__NVIC_SetPriority+0x50>) - 8005c74: 79fb ldrb r3, [r7, #7] - 8005c76: f003 030f and.w r3, r3, #15 - 8005c7a: 3b04 subs r3, #4 - 8005c7c: 0112 lsls r2, r2, #4 - 8005c7e: b2d2 uxtb r2, r2 - 8005c80: 440b add r3, r1 - 8005c82: 761a strb r2, [r3, #24] -} - 8005c84: bf00 nop - 8005c86: 370c adds r7, #12 - 8005c88: 46bd mov sp, r7 - 8005c8a: f85d 7b04 ldr.w r7, [sp], #4 - 8005c8e: 4770 bx lr - 8005c90: e000e100 .word 0xe000e100 - 8005c94: e000ed00 .word 0xe000ed00 - -08005c98 : + 80068ba: 683b ldr r3, [r7, #0] + 80068bc: b2da uxtb r2, r3 + 80068be: 4908 ldr r1, [pc, #32] ; (80068e0 <__NVIC_SetPriority+0x50>) + 80068c0: 79fb ldrb r3, [r7, #7] + 80068c2: f003 030f and.w r3, r3, #15 + 80068c6: 3b04 subs r3, #4 + 80068c8: 0112 lsls r2, r2, #4 + 80068ca: b2d2 uxtb r2, r2 + 80068cc: 440b add r3, r1 + 80068ce: 761a strb r2, [r3, #24] +} + 80068d0: bf00 nop + 80068d2: 370c adds r7, #12 + 80068d4: 46bd mov sp, r7 + 80068d6: f85d 7b04 ldr.w r7, [sp], #4 + 80068da: 4770 bx lr + 80068dc: e000e100 .word 0xe000e100 + 80068e0: e000ed00 .word 0xe000ed00 + +080068e4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8005c98: b480 push {r7} - 8005c9a: b089 sub sp, #36 ; 0x24 - 8005c9c: af00 add r7, sp, #0 - 8005c9e: 60f8 str r0, [r7, #12] - 8005ca0: 60b9 str r1, [r7, #8] - 8005ca2: 607a str r2, [r7, #4] + 80068e4: b480 push {r7} + 80068e6: b089 sub sp, #36 ; 0x24 + 80068e8: af00 add r7, sp, #0 + 80068ea: 60f8 str r0, [r7, #12] + 80068ec: 60b9 str r1, [r7, #8] + 80068ee: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8005ca4: 68fb ldr r3, [r7, #12] - 8005ca6: f003 0307 and.w r3, r3, #7 - 8005caa: 61fb str r3, [r7, #28] + 80068f0: 68fb ldr r3, [r7, #12] + 80068f2: f003 0307 and.w r3, r3, #7 + 80068f6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8005cac: 69fb ldr r3, [r7, #28] - 8005cae: f1c3 0307 rsb r3, r3, #7 - 8005cb2: 2b04 cmp r3, #4 - 8005cb4: bf28 it cs - 8005cb6: 2304 movcs r3, #4 - 8005cb8: 61bb str r3, [r7, #24] + 80068f8: 69fb ldr r3, [r7, #28] + 80068fa: f1c3 0307 rsb r3, r3, #7 + 80068fe: 2b04 cmp r3, #4 + 8006900: bf28 it cs + 8006902: 2304 movcs r3, #4 + 8006904: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8005cba: 69fb ldr r3, [r7, #28] - 8005cbc: 3304 adds r3, #4 - 8005cbe: 2b06 cmp r3, #6 - 8005cc0: d902 bls.n 8005cc8 - 8005cc2: 69fb ldr r3, [r7, #28] - 8005cc4: 3b03 subs r3, #3 - 8005cc6: e000 b.n 8005cca - 8005cc8: 2300 movs r3, #0 - 8005cca: 617b str r3, [r7, #20] + 8006906: 69fb ldr r3, [r7, #28] + 8006908: 3304 adds r3, #4 + 800690a: 2b06 cmp r3, #6 + 800690c: d902 bls.n 8006914 + 800690e: 69fb ldr r3, [r7, #28] + 8006910: 3b03 subs r3, #3 + 8006912: e000 b.n 8006916 + 8006914: 2300 movs r3, #0 + 8006916: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8005ccc: f04f 32ff mov.w r2, #4294967295 - 8005cd0: 69bb ldr r3, [r7, #24] - 8005cd2: fa02 f303 lsl.w r3, r2, r3 - 8005cd6: 43da mvns r2, r3 - 8005cd8: 68bb ldr r3, [r7, #8] - 8005cda: 401a ands r2, r3 - 8005cdc: 697b ldr r3, [r7, #20] - 8005cde: 409a lsls r2, r3 + 8006918: f04f 32ff mov.w r2, #4294967295 + 800691c: 69bb ldr r3, [r7, #24] + 800691e: fa02 f303 lsl.w r3, r2, r3 + 8006922: 43da mvns r2, r3 + 8006924: 68bb ldr r3, [r7, #8] + 8006926: 401a ands r2, r3 + 8006928: 697b ldr r3, [r7, #20] + 800692a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8005ce0: f04f 31ff mov.w r1, #4294967295 - 8005ce4: 697b ldr r3, [r7, #20] - 8005ce6: fa01 f303 lsl.w r3, r1, r3 - 8005cea: 43d9 mvns r1, r3 - 8005cec: 687b ldr r3, [r7, #4] - 8005cee: 400b ands r3, r1 + 800692c: f04f 31ff mov.w r1, #4294967295 + 8006930: 697b ldr r3, [r7, #20] + 8006932: fa01 f303 lsl.w r3, r1, r3 + 8006936: 43d9 mvns r1, r3 + 8006938: 687b ldr r3, [r7, #4] + 800693a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8005cf0: 4313 orrs r3, r2 + 800693c: 4313 orrs r3, r2 ); } - 8005cf2: 4618 mov r0, r3 - 8005cf4: 3724 adds r7, #36 ; 0x24 - 8005cf6: 46bd mov sp, r7 - 8005cf8: f85d 7b04 ldr.w r7, [sp], #4 - 8005cfc: 4770 bx lr + 800693e: 4618 mov r0, r3 + 8006940: 3724 adds r7, #36 ; 0x24 + 8006942: 46bd mov sp, r7 + 8006944: f85d 7b04 ldr.w r7, [sp], #4 + 8006948: 4770 bx lr ... -08005d00 : +0800694c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8005d00: b580 push {r7, lr} - 8005d02: b082 sub sp, #8 - 8005d04: af00 add r7, sp, #0 - 8005d06: 6078 str r0, [r7, #4] + 800694c: b580 push {r7, lr} + 800694e: b082 sub sp, #8 + 8006950: af00 add r7, sp, #0 + 8006952: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 8005d08: 687b ldr r3, [r7, #4] - 8005d0a: 3b01 subs r3, #1 - 8005d0c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 8005d10: d301 bcc.n 8005d16 + 8006954: 687b ldr r3, [r7, #4] + 8006956: 3b01 subs r3, #1 + 8006958: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 800695c: d301 bcc.n 8006962 { return (1UL); /* Reload value impossible */ - 8005d12: 2301 movs r3, #1 - 8005d14: e00f b.n 8005d36 + 800695e: 2301 movs r3, #1 + 8006960: e00f b.n 8006982 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 8005d16: 4a0a ldr r2, [pc, #40] ; (8005d40 ) - 8005d18: 687b ldr r3, [r7, #4] - 8005d1a: 3b01 subs r3, #1 - 8005d1c: 6053 str r3, [r2, #4] + 8006962: 4a0a ldr r2, [pc, #40] ; (800698c ) + 8006964: 687b ldr r3, [r7, #4] + 8006966: 3b01 subs r3, #1 + 8006968: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8005d1e: 210f movs r1, #15 - 8005d20: f04f 30ff mov.w r0, #4294967295 - 8005d24: f7ff ff8e bl 8005c44 <__NVIC_SetPriority> + 800696a: 210f movs r1, #15 + 800696c: f04f 30ff mov.w r0, #4294967295 + 8006970: f7ff ff8e bl 8006890 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8005d28: 4b05 ldr r3, [pc, #20] ; (8005d40 ) - 8005d2a: 2200 movs r2, #0 - 8005d2c: 609a str r2, [r3, #8] + 8006974: 4b05 ldr r3, [pc, #20] ; (800698c ) + 8006976: 2200 movs r2, #0 + 8006978: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8005d2e: 4b04 ldr r3, [pc, #16] ; (8005d40 ) - 8005d30: 2207 movs r2, #7 - 8005d32: 601a str r2, [r3, #0] + 800697a: 4b04 ldr r3, [pc, #16] ; (800698c ) + 800697c: 2207 movs r2, #7 + 800697e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8005d34: 2300 movs r3, #0 + 8006980: 2300 movs r3, #0 } - 8005d36: 4618 mov r0, r3 - 8005d38: 3708 adds r7, #8 - 8005d3a: 46bd mov sp, r7 - 8005d3c: bd80 pop {r7, pc} - 8005d3e: bf00 nop - 8005d40: e000e010 .word 0xe000e010 + 8006982: 4618 mov r0, r3 + 8006984: 3708 adds r7, #8 + 8006986: 46bd mov sp, r7 + 8006988: bd80 pop {r7, pc} + 800698a: bf00 nop + 800698c: e000e010 .word 0xe000e010 -08005d44 : +08006990 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8005d44: b580 push {r7, lr} - 8005d46: b082 sub sp, #8 - 8005d48: af00 add r7, sp, #0 - 8005d4a: 6078 str r0, [r7, #4] + 8006990: b580 push {r7, lr} + 8006992: b082 sub sp, #8 + 8006994: af00 add r7, sp, #0 + 8006996: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8005d4c: 6878 ldr r0, [r7, #4] - 8005d4e: f7ff ff05 bl 8005b5c <__NVIC_SetPriorityGrouping> + 8006998: 6878 ldr r0, [r7, #4] + 800699a: f7ff ff29 bl 80067f0 <__NVIC_SetPriorityGrouping> } - 8005d52: bf00 nop - 8005d54: 3708 adds r7, #8 - 8005d56: 46bd mov sp, r7 - 8005d58: bd80 pop {r7, pc} + 800699e: bf00 nop + 80069a0: 3708 adds r7, #8 + 80069a2: 46bd mov sp, r7 + 80069a4: bd80 pop {r7, pc} -08005d5a : +080069a6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8005d5a: b580 push {r7, lr} - 8005d5c: b086 sub sp, #24 - 8005d5e: af00 add r7, sp, #0 - 8005d60: 4603 mov r3, r0 - 8005d62: 60b9 str r1, [r7, #8] - 8005d64: 607a str r2, [r7, #4] - 8005d66: 73fb strb r3, [r7, #15] + 80069a6: b580 push {r7, lr} + 80069a8: b086 sub sp, #24 + 80069aa: af00 add r7, sp, #0 + 80069ac: 4603 mov r3, r0 + 80069ae: 60b9 str r1, [r7, #8] + 80069b0: 607a str r2, [r7, #4] + 80069b2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; - 8005d68: 2300 movs r3, #0 - 8005d6a: 617b str r3, [r7, #20] + 80069b4: 2300 movs r3, #0 + 80069b6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8005d6c: f7ff ff1a bl 8005ba4 <__NVIC_GetPriorityGrouping> - 8005d70: 6178 str r0, [r7, #20] + 80069b8: f7ff ff3e bl 8006838 <__NVIC_GetPriorityGrouping> + 80069bc: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8005d72: 687a ldr r2, [r7, #4] - 8005d74: 68b9 ldr r1, [r7, #8] - 8005d76: 6978 ldr r0, [r7, #20] - 8005d78: f7ff ff8e bl 8005c98 - 8005d7c: 4602 mov r2, r0 - 8005d7e: f997 300f ldrsb.w r3, [r7, #15] - 8005d82: 4611 mov r1, r2 - 8005d84: 4618 mov r0, r3 - 8005d86: f7ff ff5d bl 8005c44 <__NVIC_SetPriority> -} - 8005d8a: bf00 nop - 8005d8c: 3718 adds r7, #24 - 8005d8e: 46bd mov sp, r7 - 8005d90: bd80 pop {r7, pc} - -08005d92 : + 80069be: 687a ldr r2, [r7, #4] + 80069c0: 68b9 ldr r1, [r7, #8] + 80069c2: 6978 ldr r0, [r7, #20] + 80069c4: f7ff ff8e bl 80068e4 + 80069c8: 4602 mov r2, r0 + 80069ca: f997 300f ldrsb.w r3, [r7, #15] + 80069ce: 4611 mov r1, r2 + 80069d0: 4618 mov r0, r3 + 80069d2: f7ff ff5d bl 8006890 <__NVIC_SetPriority> +} + 80069d6: bf00 nop + 80069d8: 3718 adds r7, #24 + 80069da: 46bd mov sp, r7 + 80069dc: bd80 pop {r7, pc} + +080069de : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 8005d92: b580 push {r7, lr} - 8005d94: b082 sub sp, #8 - 8005d96: af00 add r7, sp, #0 - 8005d98: 4603 mov r3, r0 - 8005d9a: 71fb strb r3, [r7, #7] + 80069de: b580 push {r7, lr} + 80069e0: b082 sub sp, #8 + 80069e2: af00 add r7, sp, #0 + 80069e4: 4603 mov r3, r0 + 80069e6: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8005d9c: f997 3007 ldrsb.w r3, [r7, #7] - 8005da0: 4618 mov r0, r3 - 8005da2: f7ff ff0d bl 8005bc0 <__NVIC_EnableIRQ> + 80069e8: f997 3007 ldrsb.w r3, [r7, #7] + 80069ec: 4618 mov r0, r3 + 80069ee: f7ff ff31 bl 8006854 <__NVIC_EnableIRQ> } - 8005da6: bf00 nop - 8005da8: 3708 adds r7, #8 - 8005daa: 46bd mov sp, r7 - 8005dac: bd80 pop {r7, pc} + 80069f2: bf00 nop + 80069f4: 3708 adds r7, #8 + 80069f6: 46bd mov sp, r7 + 80069f8: bd80 pop {r7, pc} -08005dae : - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - 8005dae: b580 push {r7, lr} - 8005db0: b082 sub sp, #8 - 8005db2: af00 add r7, sp, #0 - 8005db4: 4603 mov r3, r0 - 8005db6: 71fb strb r3, [r7, #7] - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); - 8005db8: f997 3007 ldrsb.w r3, [r7, #7] - 8005dbc: 4618 mov r0, r3 - 8005dbe: f7ff ff1d bl 8005bfc <__NVIC_DisableIRQ> -} - 8005dc2: bf00 nop - 8005dc4: 3708 adds r7, #8 - 8005dc6: 46bd mov sp, r7 - 8005dc8: bd80 pop {r7, pc} - -08005dca : +080069fa : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8005dca: b580 push {r7, lr} - 8005dcc: b082 sub sp, #8 - 8005dce: af00 add r7, sp, #0 - 8005dd0: 6078 str r0, [r7, #4] + 80069fa: b580 push {r7, lr} + 80069fc: b082 sub sp, #8 + 80069fe: af00 add r7, sp, #0 + 8006a00: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8005dd2: 6878 ldr r0, [r7, #4] - 8005dd4: f7ff ff94 bl 8005d00 - 8005dd8: 4603 mov r3, r0 -} - 8005dda: 4618 mov r0, r3 - 8005ddc: 3708 adds r7, #8 - 8005dde: 46bd mov sp, r7 - 8005de0: bd80 pop {r7, pc} + 8006a02: 6878 ldr r0, [r7, #4] + 8006a04: f7ff ffa2 bl 800694c + 8006a08: 4603 mov r3, r0 +} + 8006a0a: 4618 mov r0, r3 + 8006a0c: 3708 adds r7, #8 + 8006a0e: 46bd mov sp, r7 + 8006a10: bd80 pop {r7, pc} ... -08005de4 : +08006a14 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - 8005de4: b480 push {r7} - 8005de6: b085 sub sp, #20 - 8005de8: af00 add r7, sp, #0 - 8005dea: 6078 str r0, [r7, #4] + 8006a14: b480 push {r7} + 8006a16: b085 sub sp, #20 + 8006a18: af00 add r7, sp, #0 + 8006a1a: 6078 str r0, [r7, #4] uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) - 8005dec: 687b ldr r3, [r7, #4] - 8005dee: 2b00 cmp r3, #0 - 8005df0: d101 bne.n 8005df6 + 8006a1c: 687b ldr r3, [r7, #4] + 8006a1e: 2b00 cmp r3, #0 + 8006a20: d101 bne.n 8006a26 { return HAL_ERROR; - 8005df2: 2301 movs r3, #1 - 8005df4: e098 b.n 8005f28 + 8006a22: 2301 movs r3, #1 + 8006a24: e098 b.n 8006b58 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - 8005df6: 687b ldr r3, [r7, #4] - 8005df8: 681b ldr r3, [r3, #0] - 8005dfa: 461a mov r2, r3 - 8005dfc: 4b4d ldr r3, [pc, #308] ; (8005f34 ) - 8005dfe: 429a cmp r2, r3 - 8005e00: d80f bhi.n 8005e22 + 8006a26: 687b ldr r3, [r7, #4] + 8006a28: 681b ldr r3, [r3, #0] + 8006a2a: 461a mov r2, r3 + 8006a2c: 4b4d ldr r3, [pc, #308] ; (8006b64 ) + 8006a2e: 429a cmp r2, r3 + 8006a30: d80f bhi.n 8006a52 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - 8005e02: 687b ldr r3, [r7, #4] - 8005e04: 681b ldr r3, [r3, #0] - 8005e06: 461a mov r2, r3 - 8005e08: 4b4b ldr r3, [pc, #300] ; (8005f38 ) - 8005e0a: 4413 add r3, r2 - 8005e0c: 4a4b ldr r2, [pc, #300] ; (8005f3c ) - 8005e0e: fba2 2303 umull r2, r3, r2, r3 - 8005e12: 091b lsrs r3, r3, #4 - 8005e14: 009a lsls r2, r3, #2 - 8005e16: 687b ldr r3, [r7, #4] - 8005e18: 645a str r2, [r3, #68] ; 0x44 + 8006a32: 687b ldr r3, [r7, #4] + 8006a34: 681b ldr r3, [r3, #0] + 8006a36: 461a mov r2, r3 + 8006a38: 4b4b ldr r3, [pc, #300] ; (8006b68 ) + 8006a3a: 4413 add r3, r2 + 8006a3c: 4a4b ldr r2, [pc, #300] ; (8006b6c ) + 8006a3e: fba2 2303 umull r2, r3, r2, r3 + 8006a42: 091b lsrs r3, r3, #4 + 8006a44: 009a lsls r2, r3, #2 + 8006a46: 687b ldr r3, [r7, #4] + 8006a48: 645a str r2, [r3, #68] ; 0x44 hdma->DmaBaseAddress = DMA1; - 8005e1a: 687b ldr r3, [r7, #4] - 8005e1c: 4a48 ldr r2, [pc, #288] ; (8005f40 ) - 8005e1e: 641a str r2, [r3, #64] ; 0x40 - 8005e20: e00e b.n 8005e40 + 8006a4a: 687b ldr r3, [r7, #4] + 8006a4c: 4a48 ldr r2, [pc, #288] ; (8006b70 ) + 8006a4e: 641a str r2, [r3, #64] ; 0x40 + 8006a50: e00e b.n 8006a70 } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - 8005e22: 687b ldr r3, [r7, #4] - 8005e24: 681b ldr r3, [r3, #0] - 8005e26: 461a mov r2, r3 - 8005e28: 4b46 ldr r3, [pc, #280] ; (8005f44 ) - 8005e2a: 4413 add r3, r2 - 8005e2c: 4a43 ldr r2, [pc, #268] ; (8005f3c ) - 8005e2e: fba2 2303 umull r2, r3, r2, r3 - 8005e32: 091b lsrs r3, r3, #4 - 8005e34: 009a lsls r2, r3, #2 - 8005e36: 687b ldr r3, [r7, #4] - 8005e38: 645a str r2, [r3, #68] ; 0x44 + 8006a52: 687b ldr r3, [r7, #4] + 8006a54: 681b ldr r3, [r3, #0] + 8006a56: 461a mov r2, r3 + 8006a58: 4b46 ldr r3, [pc, #280] ; (8006b74 ) + 8006a5a: 4413 add r3, r2 + 8006a5c: 4a43 ldr r2, [pc, #268] ; (8006b6c ) + 8006a5e: fba2 2303 umull r2, r3, r2, r3 + 8006a62: 091b lsrs r3, r3, #4 + 8006a64: 009a lsls r2, r3, #2 + 8006a66: 687b ldr r3, [r7, #4] + 8006a68: 645a str r2, [r3, #68] ; 0x44 hdma->DmaBaseAddress = DMA2; - 8005e3a: 687b ldr r3, [r7, #4] - 8005e3c: 4a42 ldr r2, [pc, #264] ; (8005f48 ) - 8005e3e: 641a str r2, [r3, #64] ; 0x40 + 8006a6a: 687b ldr r3, [r7, #4] + 8006a6c: 4a42 ldr r2, [pc, #264] ; (8006b78 ) + 8006a6e: 641a str r2, [r3, #64] ; 0x40 } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 8005e40: 687b ldr r3, [r7, #4] - 8005e42: 2202 movs r2, #2 - 8005e44: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006a70: 687b ldr r3, [r7, #4] + 8006a72: 2202 movs r2, #2 + 8006a74: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Get the CR register value */ tmp = hdma->Instance->CCR; - 8005e48: 687b ldr r3, [r7, #4] - 8005e4a: 681b ldr r3, [r3, #0] - 8005e4c: 681b ldr r3, [r3, #0] - 8005e4e: 60fb str r3, [r7, #12] + 8006a78: 687b ldr r3, [r7, #4] + 8006a7a: 681b ldr r3, [r3, #0] + 8006a7c: 681b ldr r3, [r3, #0] + 8006a7e: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | - 8005e50: 68fb ldr r3, [r7, #12] - 8005e52: f423 43ff bic.w r3, r3, #32640 ; 0x7f80 - 8005e56: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8005e5a: 60fb str r3, [r7, #12] + 8006a80: 68fb ldr r3, [r7, #12] + 8006a82: f423 43ff bic.w r3, r3, #32640 ; 0x7f80 + 8006a86: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8006a8a: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | - 8005e5c: 687b ldr r3, [r7, #4] - 8005e5e: 689a ldr r2, [r3, #8] + 8006a8c: 687b ldr r3, [r7, #4] + 8006a8e: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | - 8005e60: 687b ldr r3, [r7, #4] - 8005e62: 68db ldr r3, [r3, #12] + 8006a90: 687b ldr r3, [r7, #4] + 8006a92: 68db ldr r3, [r3, #12] tmp |= hdma->Init.Direction | - 8005e64: 431a orrs r2, r3 + 8006a94: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | - 8005e66: 687b ldr r3, [r7, #4] - 8005e68: 691b ldr r3, [r3, #16] - 8005e6a: 431a orrs r2, r3 + 8006a96: 687b ldr r3, [r7, #4] + 8006a98: 691b ldr r3, [r3, #16] + 8006a9a: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 8005e6c: 687b ldr r3, [r7, #4] - 8005e6e: 695b ldr r3, [r3, #20] + 8006a9c: 687b ldr r3, [r7, #4] + 8006a9e: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | - 8005e70: 431a orrs r2, r3 + 8006aa0: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 8005e72: 687b ldr r3, [r7, #4] - 8005e74: 699b ldr r3, [r3, #24] - 8005e76: 431a orrs r2, r3 + 8006aa2: 687b ldr r3, [r7, #4] + 8006aa4: 699b ldr r3, [r3, #24] + 8006aa6: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 8005e78: 687b ldr r3, [r7, #4] - 8005e7a: 69db ldr r3, [r3, #28] + 8006aa8: 687b ldr r3, [r7, #4] + 8006aaa: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - 8005e7c: 431a orrs r2, r3 + 8006aac: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; - 8005e7e: 687b ldr r3, [r7, #4] - 8005e80: 6a1b ldr r3, [r3, #32] - 8005e82: 4313 orrs r3, r2 + 8006aae: 687b ldr r3, [r7, #4] + 8006ab0: 6a1b ldr r3, [r3, #32] + 8006ab2: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | - 8005e84: 68fa ldr r2, [r7, #12] - 8005e86: 4313 orrs r3, r2 - 8005e88: 60fb str r3, [r7, #12] + 8006ab4: 68fa ldr r2, [r7, #12] + 8006ab6: 4313 orrs r3, r2 + 8006ab8: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; - 8005e8a: 687b ldr r3, [r7, #4] - 8005e8c: 681b ldr r3, [r3, #0] - 8005e8e: 68fa ldr r2, [r7, #12] - 8005e90: 601a str r2, [r3, #0] + 8006aba: 687b ldr r3, [r7, #4] + 8006abc: 681b ldr r3, [r3, #0] + 8006abe: 68fa ldr r2, [r7, #12] + 8006ac0: 601a str r2, [r3, #0] #endif /* DMAMUX1 */ #if !defined (DMAMUX1) /* Set request selection */ if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - 8005e92: 687b ldr r3, [r7, #4] - 8005e94: 689b ldr r3, [r3, #8] - 8005e96: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 8005e9a: d039 beq.n 8005f10 + 8006ac2: 687b ldr r3, [r7, #4] + 8006ac4: 689b ldr r3, [r3, #8] + 8006ac6: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8006aca: d039 beq.n 8006b40 { /* Write to DMA channel selection register */ if (DMA1 == hdma->DmaBaseAddress) - 8005e9c: 687b ldr r3, [r7, #4] - 8005e9e: 6c1b ldr r3, [r3, #64] ; 0x40 - 8005ea0: 4a27 ldr r2, [pc, #156] ; (8005f40 ) - 8005ea2: 4293 cmp r3, r2 - 8005ea4: d11a bne.n 8005edc + 8006acc: 687b ldr r3, [r7, #4] + 8006ace: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006ad0: 4a27 ldr r2, [pc, #156] ; (8006b70 ) + 8006ad2: 4293 cmp r3, r2 + 8006ad4: d11a bne.n 8006b0c { /* Reset request selection for DMA1 Channelx */ DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); - 8005ea6: 4b29 ldr r3, [pc, #164] ; (8005f4c ) - 8005ea8: 681a ldr r2, [r3, #0] - 8005eaa: 687b ldr r3, [r7, #4] - 8005eac: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005eae: f003 031c and.w r3, r3, #28 - 8005eb2: 210f movs r1, #15 - 8005eb4: fa01 f303 lsl.w r3, r1, r3 - 8005eb8: 43db mvns r3, r3 - 8005eba: 4924 ldr r1, [pc, #144] ; (8005f4c ) - 8005ebc: 4013 ands r3, r2 - 8005ebe: 600b str r3, [r1, #0] + 8006ad6: 4b29 ldr r3, [pc, #164] ; (8006b7c ) + 8006ad8: 681a ldr r2, [r3, #0] + 8006ada: 687b ldr r3, [r7, #4] + 8006adc: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006ade: f003 031c and.w r3, r3, #28 + 8006ae2: 210f movs r1, #15 + 8006ae4: fa01 f303 lsl.w r3, r1, r3 + 8006ae8: 43db mvns r3, r3 + 8006aea: 4924 ldr r1, [pc, #144] ; (8006b7c ) + 8006aec: 4013 ands r3, r2 + 8006aee: 600b str r3, [r1, #0] /* Configure request selection for DMA1 Channelx */ DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); - 8005ec0: 4b22 ldr r3, [pc, #136] ; (8005f4c ) - 8005ec2: 681a ldr r2, [r3, #0] - 8005ec4: 687b ldr r3, [r7, #4] - 8005ec6: 6859 ldr r1, [r3, #4] - 8005ec8: 687b ldr r3, [r7, #4] - 8005eca: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005ecc: f003 031c and.w r3, r3, #28 - 8005ed0: fa01 f303 lsl.w r3, r1, r3 - 8005ed4: 491d ldr r1, [pc, #116] ; (8005f4c ) - 8005ed6: 4313 orrs r3, r2 - 8005ed8: 600b str r3, [r1, #0] - 8005eda: e019 b.n 8005f10 + 8006af0: 4b22 ldr r3, [pc, #136] ; (8006b7c ) + 8006af2: 681a ldr r2, [r3, #0] + 8006af4: 687b ldr r3, [r7, #4] + 8006af6: 6859 ldr r1, [r3, #4] + 8006af8: 687b ldr r3, [r7, #4] + 8006afa: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006afc: f003 031c and.w r3, r3, #28 + 8006b00: fa01 f303 lsl.w r3, r1, r3 + 8006b04: 491d ldr r1, [pc, #116] ; (8006b7c ) + 8006b06: 4313 orrs r3, r2 + 8006b08: 600b str r3, [r1, #0] + 8006b0a: e019 b.n 8006b40 } else /* DMA2 */ { /* Reset request selection for DMA2 Channelx */ DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); - 8005edc: 4b1c ldr r3, [pc, #112] ; (8005f50 ) - 8005ede: 681a ldr r2, [r3, #0] - 8005ee0: 687b ldr r3, [r7, #4] - 8005ee2: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005ee4: f003 031c and.w r3, r3, #28 - 8005ee8: 210f movs r1, #15 - 8005eea: fa01 f303 lsl.w r3, r1, r3 - 8005eee: 43db mvns r3, r3 - 8005ef0: 4917 ldr r1, [pc, #92] ; (8005f50 ) - 8005ef2: 4013 ands r3, r2 - 8005ef4: 600b str r3, [r1, #0] + 8006b0c: 4b1c ldr r3, [pc, #112] ; (8006b80 ) + 8006b0e: 681a ldr r2, [r3, #0] + 8006b10: 687b ldr r3, [r7, #4] + 8006b12: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006b14: f003 031c and.w r3, r3, #28 + 8006b18: 210f movs r1, #15 + 8006b1a: fa01 f303 lsl.w r3, r1, r3 + 8006b1e: 43db mvns r3, r3 + 8006b20: 4917 ldr r1, [pc, #92] ; (8006b80 ) + 8006b22: 4013 ands r3, r2 + 8006b24: 600b str r3, [r1, #0] /* Configure request selection for DMA2 Channelx */ DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); - 8005ef6: 4b16 ldr r3, [pc, #88] ; (8005f50 ) - 8005ef8: 681a ldr r2, [r3, #0] - 8005efa: 687b ldr r3, [r7, #4] - 8005efc: 6859 ldr r1, [r3, #4] - 8005efe: 687b ldr r3, [r7, #4] - 8005f00: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005f02: f003 031c and.w r3, r3, #28 - 8005f06: fa01 f303 lsl.w r3, r1, r3 - 8005f0a: 4911 ldr r1, [pc, #68] ; (8005f50 ) - 8005f0c: 4313 orrs r3, r2 - 8005f0e: 600b str r3, [r1, #0] + 8006b26: 4b16 ldr r3, [pc, #88] ; (8006b80 ) + 8006b28: 681a ldr r2, [r3, #0] + 8006b2a: 687b ldr r3, [r7, #4] + 8006b2c: 6859 ldr r1, [r3, #4] + 8006b2e: 687b ldr r3, [r7, #4] + 8006b30: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006b32: f003 031c and.w r3, r3, #28 + 8006b36: fa01 f303 lsl.w r3, r1, r3 + 8006b3a: 4911 ldr r1, [pc, #68] ; (8006b80 ) + 8006b3c: 4313 orrs r3, r2 + 8006b3e: 600b str r3, [r1, #0] #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ /* STM32L496xx || STM32L4A6xx */ /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8005f10: 687b ldr r3, [r7, #4] - 8005f12: 2200 movs r2, #0 - 8005f14: 63da str r2, [r3, #60] ; 0x3c + 8006b40: 687b ldr r3, [r7, #4] + 8006b42: 2200 movs r2, #0 + 8006b44: 63da str r2, [r3, #60] ; 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - 8005f16: 687b ldr r3, [r7, #4] - 8005f18: 2201 movs r2, #1 - 8005f1a: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006b46: 687b ldr r3, [r7, #4] + 8006b48: 2201 movs r2, #1 + 8006b4a: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; - 8005f1e: 687b ldr r3, [r7, #4] - 8005f20: 2200 movs r2, #0 - 8005f22: f883 2024 strb.w r2, [r3, #36] ; 0x24 - - return HAL_OK; - 8005f26: 2300 movs r3, #0 -} - 8005f28: 4618 mov r0, r3 - 8005f2a: 3714 adds r7, #20 - 8005f2c: 46bd mov sp, r7 - 8005f2e: f85d 7b04 ldr.w r7, [sp], #4 - 8005f32: 4770 bx lr - 8005f34: 40020407 .word 0x40020407 - 8005f38: bffdfff8 .word 0xbffdfff8 - 8005f3c: cccccccd .word 0xcccccccd - 8005f40: 40020000 .word 0x40020000 - 8005f44: bffdfbf8 .word 0xbffdfbf8 - 8005f48: 40020400 .word 0x40020400 - 8005f4c: 400200a8 .word 0x400200a8 - 8005f50: 400204a8 .word 0x400204a8 - -08005f54 : - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - 8005f54: b480 push {r7} - 8005f56: b083 sub sp, #12 - 8005f58: af00 add r7, sp, #0 - 8005f5a: 6078 str r0, [r7, #4] - - /* Check the DMA handle allocation */ - if (NULL == hdma) - 8005f5c: 687b ldr r3, [r7, #4] - 8005f5e: 2b00 cmp r3, #0 - 8005f60: d101 bne.n 8005f66 - { - return HAL_ERROR; - 8005f62: 2301 movs r3, #1 - 8005f64: e072 b.n 800604c - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - 8005f66: 687b ldr r3, [r7, #4] - 8005f68: 681b ldr r3, [r3, #0] - 8005f6a: 681a ldr r2, [r3, #0] - 8005f6c: 687b ldr r3, [r7, #4] - 8005f6e: 681b ldr r3, [r3, #0] - 8005f70: f022 0201 bic.w r2, r2, #1 - 8005f74: 601a str r2, [r3, #0] - - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - 8005f76: 687b ldr r3, [r7, #4] - 8005f78: 681b ldr r3, [r3, #0] - 8005f7a: 461a mov r2, r3 - 8005f7c: 4b36 ldr r3, [pc, #216] ; (8006058 ) - 8005f7e: 429a cmp r2, r3 - 8005f80: d80f bhi.n 8005fa2 - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - 8005f82: 687b ldr r3, [r7, #4] - 8005f84: 681b ldr r3, [r3, #0] - 8005f86: 461a mov r2, r3 - 8005f88: 4b34 ldr r3, [pc, #208] ; (800605c ) - 8005f8a: 4413 add r3, r2 - 8005f8c: 4a34 ldr r2, [pc, #208] ; (8006060 ) - 8005f8e: fba2 2303 umull r2, r3, r2, r3 - 8005f92: 091b lsrs r3, r3, #4 - 8005f94: 009a lsls r2, r3, #2 - 8005f96: 687b ldr r3, [r7, #4] - 8005f98: 645a str r2, [r3, #68] ; 0x44 - hdma->DmaBaseAddress = DMA1; - 8005f9a: 687b ldr r3, [r7, #4] - 8005f9c: 4a31 ldr r2, [pc, #196] ; (8006064 ) - 8005f9e: 641a str r2, [r3, #64] ; 0x40 - 8005fa0: e00e b.n 8005fc0 - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - 8005fa2: 687b ldr r3, [r7, #4] - 8005fa4: 681b ldr r3, [r3, #0] - 8005fa6: 461a mov r2, r3 - 8005fa8: 4b2f ldr r3, [pc, #188] ; (8006068 ) - 8005faa: 4413 add r3, r2 - 8005fac: 4a2c ldr r2, [pc, #176] ; (8006060 ) - 8005fae: fba2 2303 umull r2, r3, r2, r3 - 8005fb2: 091b lsrs r3, r3, #4 - 8005fb4: 009a lsls r2, r3, #2 - 8005fb6: 687b ldr r3, [r7, #4] - 8005fb8: 645a str r2, [r3, #68] ; 0x44 - hdma->DmaBaseAddress = DMA2; - 8005fba: 687b ldr r3, [r7, #4] - 8005fbc: 4a2b ldr r2, [pc, #172] ; (800606c ) - 8005fbe: 641a str r2, [r3, #64] ; 0x40 - } - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0U; - 8005fc0: 687b ldr r3, [r7, #4] - 8005fc2: 681b ldr r3, [r3, #0] - 8005fc4: 2200 movs r2, #0 - 8005fc6: 601a str r2, [r3, #0] - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - 8005fc8: 687b ldr r3, [r7, #4] - 8005fca: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005fcc: f003 021c and.w r2, r3, #28 - 8005fd0: 687b ldr r3, [r7, #4] - 8005fd2: 6c1b ldr r3, [r3, #64] ; 0x40 - 8005fd4: 2101 movs r1, #1 - 8005fd6: fa01 f202 lsl.w r2, r1, r2 - 8005fda: 605a str r2, [r3, #4] - -#if !defined (DMAMUX1) - - /* Reset DMA channel selection register */ - if (DMA1 == hdma->DmaBaseAddress) - 8005fdc: 687b ldr r3, [r7, #4] - 8005fde: 6c1b ldr r3, [r3, #64] ; 0x40 - 8005fe0: 4a20 ldr r2, [pc, #128] ; (8006064 ) - 8005fe2: 4293 cmp r3, r2 - 8005fe4: d10d bne.n 8006002 - { - /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); - 8005fe6: 4b22 ldr r3, [pc, #136] ; (8006070 ) - 8005fe8: 681a ldr r2, [r3, #0] - 8005fea: 687b ldr r3, [r7, #4] - 8005fec: 6c5b ldr r3, [r3, #68] ; 0x44 - 8005fee: f003 031c and.w r3, r3, #28 - 8005ff2: 210f movs r1, #15 - 8005ff4: fa01 f303 lsl.w r3, r1, r3 - 8005ff8: 43db mvns r3, r3 - 8005ffa: 491d ldr r1, [pc, #116] ; (8006070 ) - 8005ffc: 4013 ands r3, r2 - 8005ffe: 600b str r3, [r1, #0] - 8006000: e00c b.n 800601c - } - else - { - /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); - 8006002: 4b1c ldr r3, [pc, #112] ; (8006074 ) - 8006004: 681a ldr r2, [r3, #0] - 8006006: 687b ldr r3, [r7, #4] - 8006008: 6c5b ldr r3, [r3, #68] ; 0x44 - 800600a: f003 031c and.w r3, r3, #28 - 800600e: 210f movs r1, #15 - 8006010: fa01 f303 lsl.w r3, r1, r3 - 8006014: 43db mvns r3, r3 - 8006016: 4917 ldr r1, [pc, #92] ; (8006074 ) - 8006018: 4013 ands r3, r2 - 800601a: 600b str r3, [r1, #0] - hdma->DMAmuxRequestGenStatusMask = 0U; - -#endif /* DMAMUX1 */ - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - 800601c: 687b ldr r3, [r7, #4] - 800601e: 2200 movs r2, #0 - 8006020: 62da str r2, [r3, #44] ; 0x2c - hdma->XferHalfCpltCallback = NULL; - 8006022: 687b ldr r3, [r7, #4] - 8006024: 2200 movs r2, #0 - 8006026: 631a str r2, [r3, #48] ; 0x30 - hdma->XferErrorCallback = NULL; - 8006028: 687b ldr r3, [r7, #4] - 800602a: 2200 movs r2, #0 - 800602c: 635a str r2, [r3, #52] ; 0x34 - hdma->XferAbortCallback = NULL; - 800602e: 687b ldr r3, [r7, #4] - 8006030: 2200 movs r2, #0 - 8006032: 639a str r2, [r3, #56] ; 0x38 - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 8006034: 687b ldr r3, [r7, #4] - 8006036: 2200 movs r2, #0 - 8006038: 63da str r2, [r3, #60] ; 0x3c - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - 800603a: 687b ldr r3, [r7, #4] - 800603c: 2200 movs r2, #0 - 800603e: f883 2025 strb.w r2, [r3, #37] ; 0x25 - - /* Release Lock */ - __HAL_UNLOCK(hdma); - 8006042: 687b ldr r3, [r7, #4] - 8006044: 2200 movs r2, #0 - 8006046: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006b4e: 687b ldr r3, [r7, #4] + 8006b50: 2200 movs r2, #0 + 8006b52: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_OK; - 800604a: 2300 movs r3, #0 -} - 800604c: 4618 mov r0, r3 - 800604e: 370c adds r7, #12 - 8006050: 46bd mov sp, r7 - 8006052: f85d 7b04 ldr.w r7, [sp], #4 - 8006056: 4770 bx lr - 8006058: 40020407 .word 0x40020407 - 800605c: bffdfff8 .word 0xbffdfff8 - 8006060: cccccccd .word 0xcccccccd - 8006064: 40020000 .word 0x40020000 - 8006068: bffdfbf8 .word 0xbffdfbf8 - 800606c: 40020400 .word 0x40020400 - 8006070: 400200a8 .word 0x400200a8 - 8006074: 400204a8 .word 0x400204a8 - -08006078 : + 8006b56: 2300 movs r3, #0 +} + 8006b58: 4618 mov r0, r3 + 8006b5a: 3714 adds r7, #20 + 8006b5c: 46bd mov sp, r7 + 8006b5e: f85d 7b04 ldr.w r7, [sp], #4 + 8006b62: 4770 bx lr + 8006b64: 40020407 .word 0x40020407 + 8006b68: bffdfff8 .word 0xbffdfff8 + 8006b6c: cccccccd .word 0xcccccccd + 8006b70: 40020000 .word 0x40020000 + 8006b74: bffdfbf8 .word 0xbffdfbf8 + 8006b78: 40020400 .word 0x40020400 + 8006b7c: 400200a8 .word 0x400200a8 + 8006b80: 400204a8 .word 0x400204a8 + +08006b84 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 8006078: b580 push {r7, lr} - 800607a: b086 sub sp, #24 - 800607c: af00 add r7, sp, #0 - 800607e: 60f8 str r0, [r7, #12] - 8006080: 60b9 str r1, [r7, #8] - 8006082: 607a str r2, [r7, #4] - 8006084: 603b str r3, [r7, #0] + 8006b84: b580 push {r7, lr} + 8006b86: b086 sub sp, #24 + 8006b88: af00 add r7, sp, #0 + 8006b8a: 60f8 str r0, [r7, #12] + 8006b8c: 60b9 str r1, [r7, #8] + 8006b8e: 607a str r2, [r7, #4] + 8006b90: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 8006086: 2300 movs r3, #0 - 8006088: 75fb strb r3, [r7, #23] + 8006b92: 2300 movs r3, #0 + 8006b94: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); - 800608a: 68fb ldr r3, [r7, #12] - 800608c: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 - 8006090: 2b01 cmp r3, #1 - 8006092: d101 bne.n 8006098 - 8006094: 2302 movs r3, #2 - 8006096: e04b b.n 8006130 - 8006098: 68fb ldr r3, [r7, #12] - 800609a: 2201 movs r2, #1 - 800609c: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006b96: 68fb ldr r3, [r7, #12] + 8006b98: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8006b9c: 2b01 cmp r3, #1 + 8006b9e: d101 bne.n 8006ba4 + 8006ba0: 2302 movs r3, #2 + 8006ba2: e04b b.n 8006c3c + 8006ba4: 68fb ldr r3, [r7, #12] + 8006ba6: 2201 movs r2, #1 + 8006ba8: f883 2024 strb.w r2, [r3, #36] ; 0x24 if (HAL_DMA_STATE_READY == hdma->State) - 80060a0: 68fb ldr r3, [r7, #12] - 80060a2: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 - 80060a6: b2db uxtb r3, r3 - 80060a8: 2b01 cmp r3, #1 - 80060aa: d13a bne.n 8006122 + 8006bac: 68fb ldr r3, [r7, #12] + 8006bae: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8006bb2: b2db uxtb r3, r3 + 8006bb4: 2b01 cmp r3, #1 + 8006bb6: d13a bne.n 8006c2e { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - 80060ac: 68fb ldr r3, [r7, #12] - 80060ae: 2202 movs r2, #2 - 80060b0: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006bb8: 68fb ldr r3, [r7, #12] + 8006bba: 2202 movs r2, #2 + 8006bbc: f883 2025 strb.w r2, [r3, #37] ; 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; - 80060b4: 68fb ldr r3, [r7, #12] - 80060b6: 2200 movs r2, #0 - 80060b8: 63da str r2, [r3, #60] ; 0x3c + 8006bc0: 68fb ldr r3, [r7, #12] + 8006bc2: 2200 movs r2, #0 + 8006bc4: 63da str r2, [r3, #60] ; 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - 80060ba: 68fb ldr r3, [r7, #12] - 80060bc: 681b ldr r3, [r3, #0] - 80060be: 681a ldr r2, [r3, #0] - 80060c0: 68fb ldr r3, [r7, #12] - 80060c2: 681b ldr r3, [r3, #0] - 80060c4: f022 0201 bic.w r2, r2, #1 - 80060c8: 601a str r2, [r3, #0] + 8006bc6: 68fb ldr r3, [r7, #12] + 8006bc8: 681b ldr r3, [r3, #0] + 8006bca: 681a ldr r2, [r3, #0] + 8006bcc: 68fb ldr r3, [r7, #12] + 8006bce: 681b ldr r3, [r3, #0] + 8006bd0: f022 0201 bic.w r2, r2, #1 + 8006bd4: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - 80060ca: 683b ldr r3, [r7, #0] - 80060cc: 687a ldr r2, [r7, #4] - 80060ce: 68b9 ldr r1, [r7, #8] - 80060d0: 68f8 ldr r0, [r7, #12] - 80060d2: f000 f96b bl 80063ac + 8006bd6: 683b ldr r3, [r7, #0] + 8006bd8: 687a ldr r2, [r7, #4] + 8006bda: 68b9 ldr r1, [r7, #8] + 8006bdc: 68f8 ldr r0, [r7, #12] + 8006bde: f000 f96b bl 8006eb8 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) - 80060d6: 68fb ldr r3, [r7, #12] - 80060d8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80060da: 2b00 cmp r3, #0 - 80060dc: d008 beq.n 80060f0 + 8006be2: 68fb ldr r3, [r7, #12] + 8006be4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8006be6: 2b00 cmp r3, #0 + 8006be8: d008 beq.n 8006bfc { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 80060de: 68fb ldr r3, [r7, #12] - 80060e0: 681b ldr r3, [r3, #0] - 80060e2: 681a ldr r2, [r3, #0] - 80060e4: 68fb ldr r3, [r7, #12] - 80060e6: 681b ldr r3, [r3, #0] - 80060e8: f042 020e orr.w r2, r2, #14 - 80060ec: 601a str r2, [r3, #0] - 80060ee: e00f b.n 8006110 + 8006bea: 68fb ldr r3, [r7, #12] + 8006bec: 681b ldr r3, [r3, #0] + 8006bee: 681a ldr r2, [r3, #0] + 8006bf0: 68fb ldr r3, [r7, #12] + 8006bf2: 681b ldr r3, [r3, #0] + 8006bf4: f042 020e orr.w r2, r2, #14 + 8006bf8: 601a str r2, [r3, #0] + 8006bfa: e00f b.n 8006c1c } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - 80060f0: 68fb ldr r3, [r7, #12] - 80060f2: 681b ldr r3, [r3, #0] - 80060f4: 681a ldr r2, [r3, #0] - 80060f6: 68fb ldr r3, [r7, #12] - 80060f8: 681b ldr r3, [r3, #0] - 80060fa: f022 0204 bic.w r2, r2, #4 - 80060fe: 601a str r2, [r3, #0] + 8006bfc: 68fb ldr r3, [r7, #12] + 8006bfe: 681b ldr r3, [r3, #0] + 8006c00: 681a ldr r2, [r3, #0] + 8006c02: 68fb ldr r3, [r7, #12] + 8006c04: 681b ldr r3, [r3, #0] + 8006c06: f022 0204 bic.w r2, r2, #4 + 8006c0a: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - 8006100: 68fb ldr r3, [r7, #12] - 8006102: 681b ldr r3, [r3, #0] - 8006104: 681a ldr r2, [r3, #0] - 8006106: 68fb ldr r3, [r7, #12] - 8006108: 681b ldr r3, [r3, #0] - 800610a: f042 020a orr.w r2, r2, #10 - 800610e: 601a str r2, [r3, #0] + 8006c0c: 68fb ldr r3, [r7, #12] + 8006c0e: 681b ldr r3, [r3, #0] + 8006c10: 681a ldr r2, [r3, #0] + 8006c12: 68fb ldr r3, [r7, #12] + 8006c14: 681b ldr r3, [r3, #0] + 8006c16: f042 020a orr.w r2, r2, #10 + 8006c1a: 601a str r2, [r3, #0] } #endif /* DMAMUX1 */ /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); - 8006110: 68fb ldr r3, [r7, #12] - 8006112: 681b ldr r3, [r3, #0] - 8006114: 681a ldr r2, [r3, #0] - 8006116: 68fb ldr r3, [r7, #12] - 8006118: 681b ldr r3, [r3, #0] - 800611a: f042 0201 orr.w r2, r2, #1 - 800611e: 601a str r2, [r3, #0] - 8006120: e005 b.n 800612e + 8006c1c: 68fb ldr r3, [r7, #12] + 8006c1e: 681b ldr r3, [r3, #0] + 8006c20: 681a ldr r2, [r3, #0] + 8006c22: 68fb ldr r3, [r7, #12] + 8006c24: 681b ldr r3, [r3, #0] + 8006c26: f042 0201 orr.w r2, r2, #1 + 8006c2a: 601a str r2, [r3, #0] + 8006c2c: e005 b.n 8006c3a } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8006122: 68fb ldr r3, [r7, #12] - 8006124: 2200 movs r2, #0 - 8006126: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006c2e: 68fb ldr r3, [r7, #12] + 8006c30: 2200 movs r2, #0 + 8006c32: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Remain BUSY */ status = HAL_BUSY; - 800612a: 2302 movs r3, #2 - 800612c: 75fb strb r3, [r7, #23] + 8006c36: 2302 movs r3, #2 + 8006c38: 75fb strb r3, [r7, #23] } return status; - 800612e: 7dfb ldrb r3, [r7, #23] + 8006c3a: 7dfb ldrb r3, [r7, #23] } - 8006130: 4618 mov r0, r3 - 8006132: 3718 adds r7, #24 - 8006134: 46bd mov sp, r7 - 8006136: bd80 pop {r7, pc} + 8006c3c: 4618 mov r0, r3 + 8006c3e: 3718 adds r7, #24 + 8006c40: 46bd mov sp, r7 + 8006c42: bd80 pop {r7, pc} -08006138 : +08006c44 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - 8006138: b480 push {r7} - 800613a: b085 sub sp, #20 - 800613c: af00 add r7, sp, #0 - 800613e: 6078 str r0, [r7, #4] + 8006c44: b480 push {r7} + 8006c46: b085 sub sp, #20 + 8006c48: af00 add r7, sp, #0 + 8006c4a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8006140: 2300 movs r3, #0 - 8006142: 73fb strb r3, [r7, #15] + 8006c4c: 2300 movs r3, #0 + 8006c4e: 73fb strb r3, [r7, #15] /* Check the DMA peripheral state */ if (hdma->State != HAL_DMA_STATE_BUSY) - 8006144: 687b ldr r3, [r7, #4] - 8006146: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 - 800614a: b2db uxtb r3, r3 - 800614c: 2b02 cmp r3, #2 - 800614e: d008 beq.n 8006162 + 8006c50: 687b ldr r3, [r7, #4] + 8006c52: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8006c56: b2db uxtb r3, r3 + 8006c58: 2b02 cmp r3, #2 + 8006c5a: d008 beq.n 8006c6e { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 8006150: 687b ldr r3, [r7, #4] - 8006152: 2204 movs r2, #4 - 8006154: 63da str r2, [r3, #60] ; 0x3c + 8006c5c: 687b ldr r3, [r7, #4] + 8006c5e: 2204 movs r2, #4 + 8006c60: 63da str r2, [r3, #60] ; 0x3c /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8006156: 687b ldr r3, [r7, #4] - 8006158: 2200 movs r2, #0 - 800615a: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006c62: 687b ldr r3, [r7, #4] + 8006c64: 2200 movs r2, #0 + 8006c66: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; - 800615e: 2301 movs r3, #1 - 8006160: e022 b.n 80061a8 + 8006c6a: 2301 movs r3, #1 + 8006c6c: e022 b.n 8006cb4 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8006162: 687b ldr r3, [r7, #4] - 8006164: 681b ldr r3, [r3, #0] - 8006166: 681a ldr r2, [r3, #0] - 8006168: 687b ldr r3, [r7, #4] - 800616a: 681b ldr r3, [r3, #0] - 800616c: f022 020e bic.w r2, r2, #14 - 8006170: 601a str r2, [r3, #0] + 8006c6e: 687b ldr r3, [r7, #4] + 8006c70: 681b ldr r3, [r3, #0] + 8006c72: 681a ldr r2, [r3, #0] + 8006c74: 687b ldr r3, [r7, #4] + 8006c76: 681b ldr r3, [r3, #0] + 8006c78: f022 020e bic.w r2, r2, #14 + 8006c7c: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; #endif /* DMAMUX1 */ /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - 8006172: 687b ldr r3, [r7, #4] - 8006174: 681b ldr r3, [r3, #0] - 8006176: 681a ldr r2, [r3, #0] - 8006178: 687b ldr r3, [r7, #4] - 800617a: 681b ldr r3, [r3, #0] - 800617c: f022 0201 bic.w r2, r2, #1 - 8006180: 601a str r2, [r3, #0] + 8006c7e: 687b ldr r3, [r7, #4] + 8006c80: 681b ldr r3, [r3, #0] + 8006c82: 681a ldr r2, [r3, #0] + 8006c84: 687b ldr r3, [r7, #4] + 8006c86: 681b ldr r3, [r3, #0] + 8006c88: f022 0201 bic.w r2, r2, #1 + 8006c8c: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - 8006182: 687b ldr r3, [r7, #4] - 8006184: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006186: f003 021c and.w r2, r3, #28 - 800618a: 687b ldr r3, [r7, #4] - 800618c: 6c1b ldr r3, [r3, #64] ; 0x40 - 800618e: 2101 movs r1, #1 - 8006190: fa01 f202 lsl.w r2, r1, r2 - 8006194: 605a str r2, [r3, #4] + 8006c8e: 687b ldr r3, [r7, #4] + 8006c90: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006c92: f003 021c and.w r2, r3, #28 + 8006c96: 687b ldr r3, [r7, #4] + 8006c98: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006c9a: 2101 movs r1, #1 + 8006c9c: fa01 f202 lsl.w r2, r1, r2 + 8006ca0: 605a str r2, [r3, #4] } #endif /* DMAMUX1 */ /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 8006196: 687b ldr r3, [r7, #4] - 8006198: 2201 movs r2, #1 - 800619a: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006ca2: 687b ldr r3, [r7, #4] + 8006ca4: 2201 movs r2, #1 + 8006ca6: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 800619e: 687b ldr r3, [r7, #4] - 80061a0: 2200 movs r2, #0 - 80061a2: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006caa: 687b ldr r3, [r7, #4] + 8006cac: 2200 movs r2, #0 + 8006cae: f883 2024 strb.w r2, [r3, #36] ; 0x24 return status; - 80061a6: 7bfb ldrb r3, [r7, #15] + 8006cb2: 7bfb ldrb r3, [r7, #15] } } - 80061a8: 4618 mov r0, r3 - 80061aa: 3714 adds r7, #20 - 80061ac: 46bd mov sp, r7 - 80061ae: f85d 7b04 ldr.w r7, [sp], #4 - 80061b2: 4770 bx lr + 8006cb4: 4618 mov r0, r3 + 8006cb6: 3714 adds r7, #20 + 8006cb8: 46bd mov sp, r7 + 8006cba: f85d 7b04 ldr.w r7, [sp], #4 + 8006cbe: 4770 bx lr -080061b4 : +08006cc0 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { - 80061b4: b580 push {r7, lr} - 80061b6: b084 sub sp, #16 - 80061b8: af00 add r7, sp, #0 - 80061ba: 6078 str r0, [r7, #4] + 8006cc0: b580 push {r7, lr} + 8006cc2: b084 sub sp, #16 + 8006cc4: af00 add r7, sp, #0 + 8006cc6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 80061bc: 2300 movs r3, #0 - 80061be: 73fb strb r3, [r7, #15] + 8006cc8: 2300 movs r3, #0 + 8006cca: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) - 80061c0: 687b ldr r3, [r7, #4] - 80061c2: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 - 80061c6: b2db uxtb r3, r3 - 80061c8: 2b02 cmp r3, #2 - 80061ca: d005 beq.n 80061d8 + 8006ccc: 687b ldr r3, [r7, #4] + 8006cce: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8006cd2: b2db uxtb r3, r3 + 8006cd4: 2b02 cmp r3, #2 + 8006cd6: d005 beq.n 8006ce4 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 80061cc: 687b ldr r3, [r7, #4] - 80061ce: 2204 movs r2, #4 - 80061d0: 63da str r2, [r3, #60] ; 0x3c + 8006cd8: 687b ldr r3, [r7, #4] + 8006cda: 2204 movs r2, #4 + 8006cdc: 63da str r2, [r3, #60] ; 0x3c status = HAL_ERROR; - 80061d2: 2301 movs r3, #1 - 80061d4: 73fb strb r3, [r7, #15] - 80061d6: e029 b.n 800622c + 8006cde: 2301 movs r3, #1 + 8006ce0: 73fb strb r3, [r7, #15] + 8006ce2: e029 b.n 8006d38 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 80061d8: 687b ldr r3, [r7, #4] - 80061da: 681b ldr r3, [r3, #0] - 80061dc: 681a ldr r2, [r3, #0] - 80061de: 687b ldr r3, [r7, #4] - 80061e0: 681b ldr r3, [r3, #0] - 80061e2: f022 020e bic.w r2, r2, #14 - 80061e6: 601a str r2, [r3, #0] + 8006ce4: 687b ldr r3, [r7, #4] + 8006ce6: 681b ldr r3, [r3, #0] + 8006ce8: 681a ldr r2, [r3, #0] + 8006cea: 687b ldr r3, [r7, #4] + 8006cec: 681b ldr r3, [r3, #0] + 8006cee: f022 020e bic.w r2, r2, #14 + 8006cf2: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - 80061e8: 687b ldr r3, [r7, #4] - 80061ea: 681b ldr r3, [r3, #0] - 80061ec: 681a ldr r2, [r3, #0] - 80061ee: 687b ldr r3, [r7, #4] - 80061f0: 681b ldr r3, [r3, #0] - 80061f2: f022 0201 bic.w r2, r2, #1 - 80061f6: 601a str r2, [r3, #0] + 8006cf4: 687b ldr r3, [r7, #4] + 8006cf6: 681b ldr r3, [r3, #0] + 8006cf8: 681a ldr r2, [r3, #0] + 8006cfa: 687b ldr r3, [r7, #4] + 8006cfc: 681b ldr r3, [r3, #0] + 8006cfe: f022 0201 bic.w r2, r2, #1 + 8006d02: 601a str r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } #else /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - 80061f8: 687b ldr r3, [r7, #4] - 80061fa: 6c5b ldr r3, [r3, #68] ; 0x44 - 80061fc: f003 021c and.w r2, r3, #28 - 8006200: 687b ldr r3, [r7, #4] - 8006202: 6c1b ldr r3, [r3, #64] ; 0x40 - 8006204: 2101 movs r1, #1 - 8006206: fa01 f202 lsl.w r2, r1, r2 - 800620a: 605a str r2, [r3, #4] + 8006d04: 687b ldr r3, [r7, #4] + 8006d06: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006d08: f003 021c and.w r2, r3, #28 + 8006d0c: 687b ldr r3, [r7, #4] + 8006d0e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006d10: 2101 movs r1, #1 + 8006d12: fa01 f202 lsl.w r2, r1, r2 + 8006d16: 605a str r2, [r3, #4] #endif /* DMAMUX1 */ /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800620c: 687b ldr r3, [r7, #4] - 800620e: 2201 movs r2, #1 - 8006210: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006d18: 687b ldr r3, [r7, #4] + 8006d1a: 2201 movs r2, #1 + 8006d1c: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8006214: 687b ldr r3, [r7, #4] - 8006216: 2200 movs r2, #0 - 8006218: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006d20: 687b ldr r3, [r7, #4] + 8006d22: 2200 movs r2, #0 + 8006d24: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) - 800621c: 687b ldr r3, [r7, #4] - 800621e: 6b9b ldr r3, [r3, #56] ; 0x38 - 8006220: 2b00 cmp r3, #0 - 8006222: d003 beq.n 800622c + 8006d28: 687b ldr r3, [r7, #4] + 8006d2a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006d2c: 2b00 cmp r3, #0 + 8006d2e: d003 beq.n 8006d38 { hdma->XferAbortCallback(hdma); - 8006224: 687b ldr r3, [r7, #4] - 8006226: 6b9b ldr r3, [r3, #56] ; 0x38 - 8006228: 6878 ldr r0, [r7, #4] - 800622a: 4798 blx r3 + 8006d30: 687b ldr r3, [r7, #4] + 8006d32: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006d34: 6878 ldr r0, [r7, #4] + 8006d36: 4798 blx r3 } } return status; - 800622c: 7bfb ldrb r3, [r7, #15] + 8006d38: 7bfb ldrb r3, [r7, #15] } - 800622e: 4618 mov r0, r3 - 8006230: 3710 adds r7, #16 - 8006232: 46bd mov sp, r7 - 8006234: bd80 pop {r7, pc} + 8006d3a: 4618 mov r0, r3 + 8006d3c: 3710 adds r7, #16 + 8006d3e: 46bd mov sp, r7 + 8006d40: bd80 pop {r7, pc} -08006236 : +08006d42 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - 8006236: b580 push {r7, lr} - 8006238: b084 sub sp, #16 - 800623a: af00 add r7, sp, #0 - 800623c: 6078 str r0, [r7, #4] + 8006d42: b580 push {r7, lr} + 8006d44: b084 sub sp, #16 + 8006d46: af00 add r7, sp, #0 + 8006d48: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; - 800623e: 687b ldr r3, [r7, #4] - 8006240: 6c1b ldr r3, [r3, #64] ; 0x40 - 8006242: 681b ldr r3, [r3, #0] - 8006244: 60fb str r3, [r7, #12] + 8006d4a: 687b ldr r3, [r7, #4] + 8006d4c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006d4e: 681b ldr r3, [r3, #0] + 8006d50: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; - 8006246: 687b ldr r3, [r7, #4] - 8006248: 681b ldr r3, [r3, #0] - 800624a: 681b ldr r3, [r3, #0] - 800624c: 60bb str r3, [r7, #8] + 8006d52: 687b ldr r3, [r7, #4] + 8006d54: 681b ldr r3, [r3, #0] + 8006d56: 681b ldr r3, [r3, #0] + 8006d58: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) - 800624e: 687b ldr r3, [r7, #4] - 8006250: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006252: f003 031c and.w r3, r3, #28 - 8006256: 2204 movs r2, #4 - 8006258: 409a lsls r2, r3 - 800625a: 68fb ldr r3, [r7, #12] - 800625c: 4013 ands r3, r2 - 800625e: 2b00 cmp r3, #0 - 8006260: d026 beq.n 80062b0 - 8006262: 68bb ldr r3, [r7, #8] - 8006264: f003 0304 and.w r3, r3, #4 - 8006268: 2b00 cmp r3, #0 - 800626a: d021 beq.n 80062b0 + 8006d5a: 687b ldr r3, [r7, #4] + 8006d5c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006d5e: f003 031c and.w r3, r3, #28 + 8006d62: 2204 movs r2, #4 + 8006d64: 409a lsls r2, r3 + 8006d66: 68fb ldr r3, [r7, #12] + 8006d68: 4013 ands r3, r2 + 8006d6a: 2b00 cmp r3, #0 + 8006d6c: d026 beq.n 8006dbc + 8006d6e: 68bb ldr r3, [r7, #8] + 8006d70: f003 0304 and.w r3, r3, #4 + 8006d74: 2b00 cmp r3, #0 + 8006d76: d021 beq.n 8006dbc { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 800626c: 687b ldr r3, [r7, #4] - 800626e: 681b ldr r3, [r3, #0] - 8006270: 681b ldr r3, [r3, #0] - 8006272: f003 0320 and.w r3, r3, #32 - 8006276: 2b00 cmp r3, #0 - 8006278: d107 bne.n 800628a + 8006d78: 687b ldr r3, [r7, #4] + 8006d7a: 681b ldr r3, [r3, #0] + 8006d7c: 681b ldr r3, [r3, #0] + 8006d7e: f003 0320 and.w r3, r3, #32 + 8006d82: 2b00 cmp r3, #0 + 8006d84: d107 bne.n 8006d96 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - 800627a: 687b ldr r3, [r7, #4] - 800627c: 681b ldr r3, [r3, #0] - 800627e: 681a ldr r2, [r3, #0] - 8006280: 687b ldr r3, [r7, #4] - 8006282: 681b ldr r3, [r3, #0] - 8006284: f022 0204 bic.w r2, r2, #4 - 8006288: 601a str r2, [r3, #0] + 8006d86: 687b ldr r3, [r7, #4] + 8006d88: 681b ldr r3, [r3, #0] + 8006d8a: 681a ldr r2, [r3, #0] + 8006d8c: 687b ldr r3, [r7, #4] + 8006d8e: 681b ldr r3, [r3, #0] + 8006d90: f022 0204 bic.w r2, r2, #4 + 8006d94: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); - 800628a: 687b ldr r3, [r7, #4] - 800628c: 6c5b ldr r3, [r3, #68] ; 0x44 - 800628e: f003 021c and.w r2, r3, #28 - 8006292: 687b ldr r3, [r7, #4] - 8006294: 6c1b ldr r3, [r3, #64] ; 0x40 - 8006296: 2104 movs r1, #4 - 8006298: fa01 f202 lsl.w r2, r1, r2 - 800629c: 605a str r2, [r3, #4] + 8006d96: 687b ldr r3, [r7, #4] + 8006d98: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006d9a: f003 021c and.w r2, r3, #28 + 8006d9e: 687b ldr r3, [r7, #4] + 8006da0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006da2: 2104 movs r1, #4 + 8006da4: fa01 f202 lsl.w r2, r1, r2 + 8006da8: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) - 800629e: 687b ldr r3, [r7, #4] - 80062a0: 6b1b ldr r3, [r3, #48] ; 0x30 - 80062a2: 2b00 cmp r3, #0 - 80062a4: d071 beq.n 800638a + 8006daa: 687b ldr r3, [r7, #4] + 8006dac: 6b1b ldr r3, [r3, #48] ; 0x30 + 8006dae: 2b00 cmp r3, #0 + 8006db0: d071 beq.n 8006e96 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); - 80062a6: 687b ldr r3, [r7, #4] - 80062a8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80062aa: 6878 ldr r0, [r7, #4] - 80062ac: 4798 blx r3 + 8006db2: 687b ldr r3, [r7, #4] + 8006db4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8006db6: 6878 ldr r0, [r7, #4] + 8006db8: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) - 80062ae: e06c b.n 800638a + 8006dba: e06c b.n 8006e96 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) - 80062b0: 687b ldr r3, [r7, #4] - 80062b2: 6c5b ldr r3, [r3, #68] ; 0x44 - 80062b4: f003 031c and.w r3, r3, #28 - 80062b8: 2202 movs r2, #2 - 80062ba: 409a lsls r2, r3 - 80062bc: 68fb ldr r3, [r7, #12] - 80062be: 4013 ands r3, r2 - 80062c0: 2b00 cmp r3, #0 - 80062c2: d02e beq.n 8006322 - 80062c4: 68bb ldr r3, [r7, #8] - 80062c6: f003 0302 and.w r3, r3, #2 - 80062ca: 2b00 cmp r3, #0 - 80062cc: d029 beq.n 8006322 + 8006dbc: 687b ldr r3, [r7, #4] + 8006dbe: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006dc0: f003 031c and.w r3, r3, #28 + 8006dc4: 2202 movs r2, #2 + 8006dc6: 409a lsls r2, r3 + 8006dc8: 68fb ldr r3, [r7, #12] + 8006dca: 4013 ands r3, r2 + 8006dcc: 2b00 cmp r3, #0 + 8006dce: d02e beq.n 8006e2e + 8006dd0: 68bb ldr r3, [r7, #8] + 8006dd2: f003 0302 and.w r3, r3, #2 + 8006dd6: 2b00 cmp r3, #0 + 8006dd8: d029 beq.n 8006e2e { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - 80062ce: 687b ldr r3, [r7, #4] - 80062d0: 681b ldr r3, [r3, #0] - 80062d2: 681b ldr r3, [r3, #0] - 80062d4: f003 0320 and.w r3, r3, #32 - 80062d8: 2b00 cmp r3, #0 - 80062da: d10b bne.n 80062f4 + 8006dda: 687b ldr r3, [r7, #4] + 8006ddc: 681b ldr r3, [r3, #0] + 8006dde: 681b ldr r3, [r3, #0] + 8006de0: f003 0320 and.w r3, r3, #32 + 8006de4: 2b00 cmp r3, #0 + 8006de6: d10b bne.n 8006e00 { /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ /* Disable the transfer complete and error interrupt */ /* if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - 80062dc: 687b ldr r3, [r7, #4] - 80062de: 681b ldr r3, [r3, #0] - 80062e0: 681a ldr r2, [r3, #0] - 80062e2: 687b ldr r3, [r7, #4] - 80062e4: 681b ldr r3, [r3, #0] - 80062e6: f022 020a bic.w r2, r2, #10 - 80062ea: 601a str r2, [r3, #0] + 8006de8: 687b ldr r3, [r7, #4] + 8006dea: 681b ldr r3, [r3, #0] + 8006dec: 681a ldr r2, [r3, #0] + 8006dee: 687b ldr r3, [r7, #4] + 8006df0: 681b ldr r3, [r3, #0] + 8006df2: f022 020a bic.w r2, r2, #10 + 8006df6: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 80062ec: 687b ldr r3, [r7, #4] - 80062ee: 2201 movs r2, #1 - 80062f0: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006df8: 687b ldr r3, [r7, #4] + 8006dfa: 2201 movs r2, #1 + 8006dfc: f883 2025 strb.w r2, [r3, #37] ; 0x25 } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU)); - 80062f4: 687b ldr r3, [r7, #4] - 80062f6: 6c5b ldr r3, [r3, #68] ; 0x44 - 80062f8: f003 021c and.w r2, r3, #28 - 80062fc: 687b ldr r3, [r7, #4] - 80062fe: 6c1b ldr r3, [r3, #64] ; 0x40 - 8006300: 2102 movs r1, #2 - 8006302: fa01 f202 lsl.w r2, r1, r2 - 8006306: 605a str r2, [r3, #4] + 8006e00: 687b ldr r3, [r7, #4] + 8006e02: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006e04: f003 021c and.w r2, r3, #28 + 8006e08: 687b ldr r3, [r7, #4] + 8006e0a: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006e0c: 2102 movs r1, #2 + 8006e0e: fa01 f202 lsl.w r2, r1, r2 + 8006e12: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8006308: 687b ldr r3, [r7, #4] - 800630a: 2200 movs r2, #0 - 800630c: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006e14: 687b ldr r3, [r7, #4] + 8006e16: 2200 movs r2, #0 + 8006e18: f883 2024 strb.w r2, [r3, #36] ; 0x24 if (hdma->XferCpltCallback != NULL) - 8006310: 687b ldr r3, [r7, #4] - 8006312: 6adb ldr r3, [r3, #44] ; 0x2c - 8006314: 2b00 cmp r3, #0 - 8006316: d038 beq.n 800638a + 8006e1c: 687b ldr r3, [r7, #4] + 8006e1e: 6adb ldr r3, [r3, #44] ; 0x2c + 8006e20: 2b00 cmp r3, #0 + 8006e22: d038 beq.n 8006e96 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); - 8006318: 687b ldr r3, [r7, #4] - 800631a: 6adb ldr r3, [r3, #44] ; 0x2c - 800631c: 6878 ldr r0, [r7, #4] - 800631e: 4798 blx r3 + 8006e24: 687b ldr r3, [r7, #4] + 8006e26: 6adb ldr r3, [r3, #44] ; 0x2c + 8006e28: 6878 ldr r0, [r7, #4] + 8006e2a: 4798 blx r3 if (hdma->XferCpltCallback != NULL) - 8006320: e033 b.n 800638a + 8006e2c: e033 b.n 8006e96 } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) - 8006322: 687b ldr r3, [r7, #4] - 8006324: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006326: f003 031c and.w r3, r3, #28 - 800632a: 2208 movs r2, #8 - 800632c: 409a lsls r2, r3 - 800632e: 68fb ldr r3, [r7, #12] - 8006330: 4013 ands r3, r2 - 8006332: 2b00 cmp r3, #0 - 8006334: d02a beq.n 800638c - 8006336: 68bb ldr r3, [r7, #8] - 8006338: f003 0308 and.w r3, r3, #8 - 800633c: 2b00 cmp r3, #0 - 800633e: d025 beq.n 800638c + 8006e2e: 687b ldr r3, [r7, #4] + 8006e30: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006e32: f003 031c and.w r3, r3, #28 + 8006e36: 2208 movs r2, #8 + 8006e38: 409a lsls r2, r3 + 8006e3a: 68fb ldr r3, [r7, #12] + 8006e3c: 4013 ands r3, r2 + 8006e3e: 2b00 cmp r3, #0 + 8006e40: d02a beq.n 8006e98 + 8006e42: 68bb ldr r3, [r7, #8] + 8006e44: f003 0308 and.w r3, r3, #8 + 8006e48: 2b00 cmp r3, #0 + 8006e4a: d025 beq.n 8006e98 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8006340: 687b ldr r3, [r7, #4] - 8006342: 681b ldr r3, [r3, #0] - 8006344: 681a ldr r2, [r3, #0] - 8006346: 687b ldr r3, [r7, #4] - 8006348: 681b ldr r3, [r3, #0] - 800634a: f022 020e bic.w r2, r2, #14 - 800634e: 601a str r2, [r3, #0] + 8006e4c: 687b ldr r3, [r7, #4] + 8006e4e: 681b ldr r3, [r3, #0] + 8006e50: 681a ldr r2, [r3, #0] + 8006e52: 687b ldr r3, [r7, #4] + 8006e54: 681b ldr r3, [r3, #0] + 8006e56: f022 020e bic.w r2, r2, #14 + 8006e5a: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - 8006350: 687b ldr r3, [r7, #4] - 8006352: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006354: f003 021c and.w r2, r3, #28 - 8006358: 687b ldr r3, [r7, #4] - 800635a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800635c: 2101 movs r1, #1 - 800635e: fa01 f202 lsl.w r2, r1, r2 - 8006362: 605a str r2, [r3, #4] + 8006e5c: 687b ldr r3, [r7, #4] + 8006e5e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006e60: f003 021c and.w r2, r3, #28 + 8006e64: 687b ldr r3, [r7, #4] + 8006e66: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006e68: 2101 movs r1, #1 + 8006e6a: fa01 f202 lsl.w r2, r1, r2 + 8006e6e: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - 8006364: 687b ldr r3, [r7, #4] - 8006366: 2201 movs r2, #1 - 8006368: 63da str r2, [r3, #60] ; 0x3c + 8006e70: 687b ldr r3, [r7, #4] + 8006e72: 2201 movs r2, #1 + 8006e74: 63da str r2, [r3, #60] ; 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800636a: 687b ldr r3, [r7, #4] - 800636c: 2201 movs r2, #1 - 800636e: f883 2025 strb.w r2, [r3, #37] ; 0x25 + 8006e76: 687b ldr r3, [r7, #4] + 8006e78: 2201 movs r2, #1 + 8006e7a: f883 2025 strb.w r2, [r3, #37] ; 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8006372: 687b ldr r3, [r7, #4] - 8006374: 2200 movs r2, #0 - 8006376: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8006e7e: 687b ldr r3, [r7, #4] + 8006e80: 2200 movs r2, #0 + 8006e82: f883 2024 strb.w r2, [r3, #36] ; 0x24 if (hdma->XferErrorCallback != NULL) - 800637a: 687b ldr r3, [r7, #4] - 800637c: 6b5b ldr r3, [r3, #52] ; 0x34 - 800637e: 2b00 cmp r3, #0 - 8006380: d004 beq.n 800638c + 8006e86: 687b ldr r3, [r7, #4] + 8006e88: 6b5b ldr r3, [r3, #52] ; 0x34 + 8006e8a: 2b00 cmp r3, #0 + 8006e8c: d004 beq.n 8006e98 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); - 8006382: 687b ldr r3, [r7, #4] - 8006384: 6b5b ldr r3, [r3, #52] ; 0x34 - 8006386: 6878 ldr r0, [r7, #4] - 8006388: 4798 blx r3 + 8006e8e: 687b ldr r3, [r7, #4] + 8006e90: 6b5b ldr r3, [r3, #52] ; 0x34 + 8006e92: 6878 ldr r0, [r7, #4] + 8006e94: 4798 blx r3 } else { /* Nothing To Do */ } return; - 800638a: bf00 nop - 800638c: bf00 nop + 8006e96: bf00 nop + 8006e98: bf00 nop } - 800638e: 3710 adds r7, #16 - 8006390: 46bd mov sp, r7 - 8006392: bd80 pop {r7, pc} + 8006e9a: 3710 adds r7, #16 + 8006e9c: 46bd mov sp, r7 + 8006e9e: bd80 pop {r7, pc} -08006394 : +08006ea0 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { - 8006394: b480 push {r7} - 8006396: b083 sub sp, #12 - 8006398: af00 add r7, sp, #0 - 800639a: 6078 str r0, [r7, #4] + 8006ea0: b480 push {r7} + 8006ea2: b083 sub sp, #12 + 8006ea4: af00 add r7, sp, #0 + 8006ea6: 6078 str r0, [r7, #4] return hdma->ErrorCode; - 800639c: 687b ldr r3, [r7, #4] - 800639e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8006ea8: 687b ldr r3, [r7, #4] + 8006eaa: 6bdb ldr r3, [r3, #60] ; 0x3c } - 80063a0: 4618 mov r0, r3 - 80063a2: 370c adds r7, #12 - 80063a4: 46bd mov sp, r7 - 80063a6: f85d 7b04 ldr.w r7, [sp], #4 - 80063aa: 4770 bx lr + 8006eac: 4618 mov r0, r3 + 8006eae: 370c adds r7, #12 + 8006eb0: 46bd mov sp, r7 + 8006eb2: f85d 7b04 ldr.w r7, [sp], #4 + 8006eb6: 4770 bx lr -080063ac : +08006eb8 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - 80063ac: b480 push {r7} - 80063ae: b085 sub sp, #20 - 80063b0: af00 add r7, sp, #0 - 80063b2: 60f8 str r0, [r7, #12] - 80063b4: 60b9 str r1, [r7, #8] - 80063b6: 607a str r2, [r7, #4] - 80063b8: 603b str r3, [r7, #0] + 8006eb8: b480 push {r7} + 8006eba: b085 sub sp, #20 + 8006ebc: af00 add r7, sp, #0 + 8006ebe: 60f8 str r0, [r7, #12] + 8006ec0: 60b9 str r1, [r7, #8] + 8006ec2: 607a str r2, [r7, #4] + 8006ec4: 603b str r3, [r7, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } #endif /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - 80063ba: 68fb ldr r3, [r7, #12] - 80063bc: 6c5b ldr r3, [r3, #68] ; 0x44 - 80063be: f003 021c and.w r2, r3, #28 - 80063c2: 68fb ldr r3, [r7, #12] - 80063c4: 6c1b ldr r3, [r3, #64] ; 0x40 - 80063c6: 2101 movs r1, #1 - 80063c8: fa01 f202 lsl.w r2, r1, r2 - 80063cc: 605a str r2, [r3, #4] + 8006ec6: 68fb ldr r3, [r7, #12] + 8006ec8: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006eca: f003 021c and.w r2, r3, #28 + 8006ece: 68fb ldr r3, [r7, #12] + 8006ed0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006ed2: 2101 movs r1, #1 + 8006ed4: fa01 f202 lsl.w r2, r1, r2 + 8006ed8: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - 80063ce: 68fb ldr r3, [r7, #12] - 80063d0: 681b ldr r3, [r3, #0] - 80063d2: 683a ldr r2, [r7, #0] - 80063d4: 605a str r2, [r3, #4] + 8006eda: 68fb ldr r3, [r7, #12] + 8006edc: 681b ldr r3, [r3, #0] + 8006ede: 683a ldr r2, [r7, #0] + 8006ee0: 605a str r2, [r3, #4] /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - 80063d6: 68fb ldr r3, [r7, #12] - 80063d8: 689b ldr r3, [r3, #8] - 80063da: 2b10 cmp r3, #16 - 80063dc: d108 bne.n 80063f0 + 8006ee2: 68fb ldr r3, [r7, #12] + 8006ee4: 689b ldr r3, [r3, #8] + 8006ee6: 2b10 cmp r3, #16 + 8006ee8: d108 bne.n 8006efc { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - 80063de: 68fb ldr r3, [r7, #12] - 80063e0: 681b ldr r3, [r3, #0] - 80063e2: 687a ldr r2, [r7, #4] - 80063e4: 609a str r2, [r3, #8] + 8006eea: 68fb ldr r3, [r7, #12] + 8006eec: 681b ldr r3, [r3, #0] + 8006eee: 687a ldr r2, [r7, #4] + 8006ef0: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; - 80063e6: 68fb ldr r3, [r7, #12] - 80063e8: 681b ldr r3, [r3, #0] - 80063ea: 68ba ldr r2, [r7, #8] - 80063ec: 60da str r2, [r3, #12] + 8006ef2: 68fb ldr r3, [r7, #12] + 8006ef4: 681b ldr r3, [r3, #0] + 8006ef6: 68ba ldr r2, [r7, #8] + 8006ef8: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } - 80063ee: e007 b.n 8006400 + 8006efa: e007 b.n 8006f0c hdma->Instance->CPAR = SrcAddress; - 80063f0: 68fb ldr r3, [r7, #12] - 80063f2: 681b ldr r3, [r3, #0] - 80063f4: 68ba ldr r2, [r7, #8] - 80063f6: 609a str r2, [r3, #8] + 8006efc: 68fb ldr r3, [r7, #12] + 8006efe: 681b ldr r3, [r3, #0] + 8006f00: 68ba ldr r2, [r7, #8] + 8006f02: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; - 80063f8: 68fb ldr r3, [r7, #12] - 80063fa: 681b ldr r3, [r3, #0] - 80063fc: 687a ldr r2, [r7, #4] - 80063fe: 60da str r2, [r3, #12] -} - 8006400: bf00 nop - 8006402: 3714 adds r7, #20 - 8006404: 46bd mov sp, r7 - 8006406: f85d 7b04 ldr.w r7, [sp], #4 - 800640a: 4770 bx lr - -0800640c : + 8006f04: 68fb ldr r3, [r7, #12] + 8006f06: 681b ldr r3, [r3, #0] + 8006f08: 687a ldr r2, [r7, #4] + 8006f0a: 60da str r2, [r3, #12] +} + 8006f0c: bf00 nop + 8006f0e: 3714 adds r7, #20 + 8006f10: 46bd mov sp, r7 + 8006f12: f85d 7b04 ldr.w r7, [sp], #4 + 8006f16: 4770 bx lr + +08006f18 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 800640c: b480 push {r7} - 800640e: b087 sub sp, #28 - 8006410: af00 add r7, sp, #0 - 8006412: 6078 str r0, [r7, #4] - 8006414: 6039 str r1, [r7, #0] + 8006f18: b480 push {r7} + 8006f1a: b087 sub sp, #28 + 8006f1c: af00 add r7, sp, #0 + 8006f1e: 6078 str r0, [r7, #4] + 8006f20: 6039 str r1, [r7, #0] uint32_t position = 0x00u; - 8006416: 2300 movs r3, #0 - 8006418: 617b str r3, [r7, #20] + 8006f22: 2300 movs r3, #0 + 8006f24: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) - 800641a: e148 b.n 80066ae + 8006f26: e148 b.n 80071ba { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); - 800641c: 683b ldr r3, [r7, #0] - 800641e: 681a ldr r2, [r3, #0] - 8006420: 2101 movs r1, #1 - 8006422: 697b ldr r3, [r7, #20] - 8006424: fa01 f303 lsl.w r3, r1, r3 - 8006428: 4013 ands r3, r2 - 800642a: 60fb str r3, [r7, #12] + 8006f28: 683b ldr r3, [r7, #0] + 8006f2a: 681a ldr r2, [r3, #0] + 8006f2c: 2101 movs r1, #1 + 8006f2e: 697b ldr r3, [r7, #20] + 8006f30: fa01 f303 lsl.w r3, r1, r3 + 8006f34: 4013 ands r3, r2 + 8006f36: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) - 800642c: 68fb ldr r3, [r7, #12] - 800642e: 2b00 cmp r3, #0 - 8006430: f000 813a beq.w 80066a8 + 8006f38: 68fb ldr r3, [r7, #12] + 8006f3a: 2b00 cmp r3, #0 + 8006f3c: f000 813a beq.w 80071b4 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 8006434: 683b ldr r3, [r7, #0] - 8006436: 685b ldr r3, [r3, #4] - 8006438: f003 0303 and.w r3, r3, #3 - 800643c: 2b01 cmp r3, #1 - 800643e: d005 beq.n 800644c - 8006440: 683b ldr r3, [r7, #0] - 8006442: 685b ldr r3, [r3, #4] - 8006444: f003 0303 and.w r3, r3, #3 - 8006448: 2b02 cmp r3, #2 - 800644a: d130 bne.n 80064ae + 8006f40: 683b ldr r3, [r7, #0] + 8006f42: 685b ldr r3, [r3, #4] + 8006f44: f003 0303 and.w r3, r3, #3 + 8006f48: 2b01 cmp r3, #1 + 8006f4a: d005 beq.n 8006f58 + 8006f4c: 683b ldr r3, [r7, #0] + 8006f4e: 685b ldr r3, [r3, #4] + 8006f50: f003 0303 and.w r3, r3, #3 + 8006f54: 2b02 cmp r3, #2 + 8006f56: d130 bne.n 8006fba { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 800644c: 687b ldr r3, [r7, #4] - 800644e: 689b ldr r3, [r3, #8] - 8006450: 613b str r3, [r7, #16] + 8006f58: 687b ldr r3, [r7, #4] + 8006f5a: 689b ldr r3, [r3, #8] + 8006f5c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); - 8006452: 697b ldr r3, [r7, #20] - 8006454: 005b lsls r3, r3, #1 - 8006456: 2203 movs r2, #3 - 8006458: fa02 f303 lsl.w r3, r2, r3 - 800645c: 43db mvns r3, r3 - 800645e: 693a ldr r2, [r7, #16] - 8006460: 4013 ands r3, r2 - 8006462: 613b str r3, [r7, #16] + 8006f5e: 697b ldr r3, [r7, #20] + 8006f60: 005b lsls r3, r3, #1 + 8006f62: 2203 movs r2, #3 + 8006f64: fa02 f303 lsl.w r3, r2, r3 + 8006f68: 43db mvns r3, r3 + 8006f6a: 693a ldr r2, [r7, #16] + 8006f6c: 4013 ands r3, r2 + 8006f6e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); - 8006464: 683b ldr r3, [r7, #0] - 8006466: 68da ldr r2, [r3, #12] - 8006468: 697b ldr r3, [r7, #20] - 800646a: 005b lsls r3, r3, #1 - 800646c: fa02 f303 lsl.w r3, r2, r3 - 8006470: 693a ldr r2, [r7, #16] - 8006472: 4313 orrs r3, r2 - 8006474: 613b str r3, [r7, #16] + 8006f70: 683b ldr r3, [r7, #0] + 8006f72: 68da ldr r2, [r3, #12] + 8006f74: 697b ldr r3, [r7, #20] + 8006f76: 005b lsls r3, r3, #1 + 8006f78: fa02 f303 lsl.w r3, r2, r3 + 8006f7c: 693a ldr r2, [r7, #16] + 8006f7e: 4313 orrs r3, r2 + 8006f80: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 8006476: 687b ldr r3, [r7, #4] - 8006478: 693a ldr r2, [r7, #16] - 800647a: 609a str r2, [r3, #8] + 8006f82: 687b ldr r3, [r7, #4] + 8006f84: 693a ldr r2, [r7, #16] + 8006f86: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 800647c: 687b ldr r3, [r7, #4] - 800647e: 685b ldr r3, [r3, #4] - 8006480: 613b str r3, [r7, #16] + 8006f88: 687b ldr r3, [r7, #4] + 8006f8a: 685b ldr r3, [r3, #4] + 8006f8c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; - 8006482: 2201 movs r2, #1 - 8006484: 697b ldr r3, [r7, #20] - 8006486: fa02 f303 lsl.w r3, r2, r3 - 800648a: 43db mvns r3, r3 - 800648c: 693a ldr r2, [r7, #16] - 800648e: 4013 ands r3, r2 - 8006490: 613b str r3, [r7, #16] + 8006f8e: 2201 movs r2, #1 + 8006f90: 697b ldr r3, [r7, #20] + 8006f92: fa02 f303 lsl.w r3, r2, r3 + 8006f96: 43db mvns r3, r3 + 8006f98: 693a ldr r2, [r7, #16] + 8006f9a: 4013 ands r3, r2 + 8006f9c: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8006492: 683b ldr r3, [r7, #0] - 8006494: 685b ldr r3, [r3, #4] - 8006496: 091b lsrs r3, r3, #4 - 8006498: f003 0201 and.w r2, r3, #1 - 800649c: 697b ldr r3, [r7, #20] - 800649e: fa02 f303 lsl.w r3, r2, r3 - 80064a2: 693a ldr r2, [r7, #16] - 80064a4: 4313 orrs r3, r2 - 80064a6: 613b str r3, [r7, #16] + 8006f9e: 683b ldr r3, [r7, #0] + 8006fa0: 685b ldr r3, [r3, #4] + 8006fa2: 091b lsrs r3, r3, #4 + 8006fa4: f003 0201 and.w r2, r3, #1 + 8006fa8: 697b ldr r3, [r7, #20] + 8006faa: fa02 f303 lsl.w r3, r2, r3 + 8006fae: 693a ldr r2, [r7, #16] + 8006fb0: 4313 orrs r3, r2 + 8006fb2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 80064a8: 687b ldr r3, [r7, #4] - 80064aa: 693a ldr r2, [r7, #16] - 80064ac: 605a str r2, [r3, #4] + 8006fb4: 687b ldr r3, [r7, #4] + 8006fb6: 693a ldr r2, [r7, #16] + 8006fb8: 605a str r2, [r3, #4] } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 80064ae: 683b ldr r3, [r7, #0] - 80064b0: 685b ldr r3, [r3, #4] - 80064b2: f003 0303 and.w r3, r3, #3 - 80064b6: 2b03 cmp r3, #3 - 80064b8: d017 beq.n 80064ea + 8006fba: 683b ldr r3, [r7, #0] + 8006fbc: 685b ldr r3, [r3, #4] + 8006fbe: f003 0303 and.w r3, r3, #3 + 8006fc2: 2b03 cmp r3, #3 + 8006fc4: d017 beq.n 8006ff6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); temp = GPIOx->PUPDR; - 80064ba: 687b ldr r3, [r7, #4] - 80064bc: 68db ldr r3, [r3, #12] - 80064be: 613b str r3, [r7, #16] + 8006fc6: 687b ldr r3, [r7, #4] + 8006fc8: 68db ldr r3, [r3, #12] + 8006fca: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - 80064c0: 697b ldr r3, [r7, #20] - 80064c2: 005b lsls r3, r3, #1 - 80064c4: 2203 movs r2, #3 - 80064c6: fa02 f303 lsl.w r3, r2, r3 - 80064ca: 43db mvns r3, r3 - 80064cc: 693a ldr r2, [r7, #16] - 80064ce: 4013 ands r3, r2 - 80064d0: 613b str r3, [r7, #16] + 8006fcc: 697b ldr r3, [r7, #20] + 8006fce: 005b lsls r3, r3, #1 + 8006fd0: 2203 movs r2, #3 + 8006fd2: fa02 f303 lsl.w r3, r2, r3 + 8006fd6: 43db mvns r3, r3 + 8006fd8: 693a ldr r2, [r7, #16] + 8006fda: 4013 ands r3, r2 + 8006fdc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); - 80064d2: 683b ldr r3, [r7, #0] - 80064d4: 689a ldr r2, [r3, #8] - 80064d6: 697b ldr r3, [r7, #20] - 80064d8: 005b lsls r3, r3, #1 - 80064da: fa02 f303 lsl.w r3, r2, r3 - 80064de: 693a ldr r2, [r7, #16] - 80064e0: 4313 orrs r3, r2 - 80064e2: 613b str r3, [r7, #16] + 8006fde: 683b ldr r3, [r7, #0] + 8006fe0: 689a ldr r2, [r3, #8] + 8006fe2: 697b ldr r3, [r7, #20] + 8006fe4: 005b lsls r3, r3, #1 + 8006fe6: fa02 f303 lsl.w r3, r2, r3 + 8006fea: 693a ldr r2, [r7, #16] + 8006fec: 4313 orrs r3, r2 + 8006fee: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 80064e4: 687b ldr r3, [r7, #4] - 80064e6: 693a ldr r2, [r7, #16] - 80064e8: 60da str r2, [r3, #12] + 8006ff0: 687b ldr r3, [r7, #4] + 8006ff2: 693a ldr r2, [r7, #16] + 8006ff4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 80064ea: 683b ldr r3, [r7, #0] - 80064ec: 685b ldr r3, [r3, #4] - 80064ee: f003 0303 and.w r3, r3, #3 - 80064f2: 2b02 cmp r3, #2 - 80064f4: d123 bne.n 800653e + 8006ff6: 683b ldr r3, [r7, #0] + 8006ff8: 685b ldr r3, [r3, #4] + 8006ffa: f003 0303 and.w r3, r3, #3 + 8006ffe: 2b02 cmp r3, #2 + 8007000: d123 bne.n 800704a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; - 80064f6: 697b ldr r3, [r7, #20] - 80064f8: 08da lsrs r2, r3, #3 - 80064fa: 687b ldr r3, [r7, #4] - 80064fc: 3208 adds r2, #8 - 80064fe: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8006502: 613b str r3, [r7, #16] + 8007002: 697b ldr r3, [r7, #20] + 8007004: 08da lsrs r2, r3, #3 + 8007006: 687b ldr r3, [r7, #4] + 8007008: 3208 adds r2, #8 + 800700a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800700e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); - 8006504: 697b ldr r3, [r7, #20] - 8006506: f003 0307 and.w r3, r3, #7 - 800650a: 009b lsls r3, r3, #2 - 800650c: 220f movs r2, #15 - 800650e: fa02 f303 lsl.w r3, r2, r3 - 8006512: 43db mvns r3, r3 - 8006514: 693a ldr r2, [r7, #16] - 8006516: 4013 ands r3, r2 - 8006518: 613b str r3, [r7, #16] + 8007010: 697b ldr r3, [r7, #20] + 8007012: f003 0307 and.w r3, r3, #7 + 8007016: 009b lsls r3, r3, #2 + 8007018: 220f movs r2, #15 + 800701a: fa02 f303 lsl.w r3, r2, r3 + 800701e: 43db mvns r3, r3 + 8007020: 693a ldr r2, [r7, #16] + 8007022: 4013 ands r3, r2 + 8007024: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - 800651a: 683b ldr r3, [r7, #0] - 800651c: 691a ldr r2, [r3, #16] - 800651e: 697b ldr r3, [r7, #20] - 8006520: f003 0307 and.w r3, r3, #7 - 8006524: 009b lsls r3, r3, #2 - 8006526: fa02 f303 lsl.w r3, r2, r3 - 800652a: 693a ldr r2, [r7, #16] - 800652c: 4313 orrs r3, r2 - 800652e: 613b str r3, [r7, #16] + 8007026: 683b ldr r3, [r7, #0] + 8007028: 691a ldr r2, [r3, #16] + 800702a: 697b ldr r3, [r7, #20] + 800702c: f003 0307 and.w r3, r3, #7 + 8007030: 009b lsls r3, r3, #2 + 8007032: fa02 f303 lsl.w r3, r2, r3 + 8007036: 693a ldr r2, [r7, #16] + 8007038: 4313 orrs r3, r2 + 800703a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; - 8006530: 697b ldr r3, [r7, #20] - 8006532: 08da lsrs r2, r3, #3 - 8006534: 687b ldr r3, [r7, #4] - 8006536: 3208 adds r2, #8 - 8006538: 6939 ldr r1, [r7, #16] - 800653a: f843 1022 str.w r1, [r3, r2, lsl #2] + 800703c: 697b ldr r3, [r7, #20] + 800703e: 08da lsrs r2, r3, #3 + 8007040: 687b ldr r3, [r7, #4] + 8007042: 3208 adds r2, #8 + 8007044: 6939 ldr r1, [r7, #16] + 8007046: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 800653e: 687b ldr r3, [r7, #4] - 8006540: 681b ldr r3, [r3, #0] - 8006542: 613b str r3, [r7, #16] + 800704a: 687b ldr r3, [r7, #4] + 800704c: 681b ldr r3, [r3, #0] + 800704e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - 8006544: 697b ldr r3, [r7, #20] - 8006546: 005b lsls r3, r3, #1 - 8006548: 2203 movs r2, #3 - 800654a: fa02 f303 lsl.w r3, r2, r3 - 800654e: 43db mvns r3, r3 - 8006550: 693a ldr r2, [r7, #16] - 8006552: 4013 ands r3, r2 - 8006554: 613b str r3, [r7, #16] + 8007050: 697b ldr r3, [r7, #20] + 8007052: 005b lsls r3, r3, #1 + 8007054: 2203 movs r2, #3 + 8007056: fa02 f303 lsl.w r3, r2, r3 + 800705a: 43db mvns r3, r3 + 800705c: 693a ldr r2, [r7, #16] + 800705e: 4013 ands r3, r2 + 8007060: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - 8006556: 683b ldr r3, [r7, #0] - 8006558: 685b ldr r3, [r3, #4] - 800655a: f003 0203 and.w r2, r3, #3 - 800655e: 697b ldr r3, [r7, #20] - 8006560: 005b lsls r3, r3, #1 - 8006562: fa02 f303 lsl.w r3, r2, r3 - 8006566: 693a ldr r2, [r7, #16] - 8006568: 4313 orrs r3, r2 - 800656a: 613b str r3, [r7, #16] + 8007062: 683b ldr r3, [r7, #0] + 8007064: 685b ldr r3, [r3, #4] + 8007066: f003 0203 and.w r2, r3, #3 + 800706a: 697b ldr r3, [r7, #20] + 800706c: 005b lsls r3, r3, #1 + 800706e: fa02 f303 lsl.w r3, r2, r3 + 8007072: 693a ldr r2, [r7, #16] + 8007074: 4313 orrs r3, r2 + 8007076: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 800656c: 687b ldr r3, [r7, #4] - 800656e: 693a ldr r2, [r7, #16] - 8006570: 601a str r2, [r3, #0] + 8007078: 687b ldr r3, [r7, #4] + 800707a: 693a ldr r2, [r7, #16] + 800707c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - 8006572: 683b ldr r3, [r7, #0] - 8006574: 685b ldr r3, [r3, #4] - 8006576: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 800657a: 2b00 cmp r3, #0 - 800657c: f000 8094 beq.w 80066a8 + 800707e: 683b ldr r3, [r7, #0] + 8007080: 685b ldr r3, [r3, #4] + 8007082: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8007086: 2b00 cmp r3, #0 + 8007088: f000 8094 beq.w 80071b4 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8006580: 4b52 ldr r3, [pc, #328] ; (80066cc ) - 8006582: 6e1b ldr r3, [r3, #96] ; 0x60 - 8006584: 4a51 ldr r2, [pc, #324] ; (80066cc ) - 8006586: f043 0301 orr.w r3, r3, #1 - 800658a: 6613 str r3, [r2, #96] ; 0x60 - 800658c: 4b4f ldr r3, [pc, #316] ; (80066cc ) - 800658e: 6e1b ldr r3, [r3, #96] ; 0x60 - 8006590: f003 0301 and.w r3, r3, #1 - 8006594: 60bb str r3, [r7, #8] - 8006596: 68bb ldr r3, [r7, #8] + 800708c: 4b52 ldr r3, [pc, #328] ; (80071d8 ) + 800708e: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007090: 4a51 ldr r2, [pc, #324] ; (80071d8 ) + 8007092: f043 0301 orr.w r3, r3, #1 + 8007096: 6613 str r3, [r2, #96] ; 0x60 + 8007098: 4b4f ldr r3, [pc, #316] ; (80071d8 ) + 800709a: 6e1b ldr r3, [r3, #96] ; 0x60 + 800709c: f003 0301 and.w r3, r3, #1 + 80070a0: 60bb str r3, [r7, #8] + 80070a2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2u]; - 8006598: 4a4d ldr r2, [pc, #308] ; (80066d0 ) - 800659a: 697b ldr r3, [r7, #20] - 800659c: 089b lsrs r3, r3, #2 - 800659e: 3302 adds r3, #2 - 80065a0: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80065a4: 613b str r3, [r7, #16] + 80070a4: 4a4d ldr r2, [pc, #308] ; (80071dc ) + 80070a6: 697b ldr r3, [r7, #20] + 80070a8: 089b lsrs r3, r3, #2 + 80070aa: 3302 adds r3, #2 + 80070ac: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80070b0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (4u * (position & 0x03u))); - 80065a6: 697b ldr r3, [r7, #20] - 80065a8: f003 0303 and.w r3, r3, #3 - 80065ac: 009b lsls r3, r3, #2 - 80065ae: 220f movs r2, #15 - 80065b0: fa02 f303 lsl.w r3, r2, r3 - 80065b4: 43db mvns r3, r3 - 80065b6: 693a ldr r2, [r7, #16] - 80065b8: 4013 ands r3, r2 - 80065ba: 613b str r3, [r7, #16] + 80070b2: 697b ldr r3, [r7, #20] + 80070b4: f003 0303 and.w r3, r3, #3 + 80070b8: 009b lsls r3, r3, #2 + 80070ba: 220f movs r2, #15 + 80070bc: fa02 f303 lsl.w r3, r2, r3 + 80070c0: 43db mvns r3, r3 + 80070c2: 693a ldr r2, [r7, #16] + 80070c4: 4013 ands r3, r2 + 80070c6: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); - 80065bc: 687b ldr r3, [r7, #4] - 80065be: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 - 80065c2: d00d beq.n 80065e0 - 80065c4: 687b ldr r3, [r7, #4] - 80065c6: 4a43 ldr r2, [pc, #268] ; (80066d4 ) - 80065c8: 4293 cmp r3, r2 - 80065ca: d007 beq.n 80065dc - 80065cc: 687b ldr r3, [r7, #4] - 80065ce: 4a42 ldr r2, [pc, #264] ; (80066d8 ) - 80065d0: 4293 cmp r3, r2 - 80065d2: d101 bne.n 80065d8 - 80065d4: 2302 movs r3, #2 - 80065d6: e004 b.n 80065e2 - 80065d8: 2307 movs r3, #7 - 80065da: e002 b.n 80065e2 - 80065dc: 2301 movs r3, #1 - 80065de: e000 b.n 80065e2 - 80065e0: 2300 movs r3, #0 - 80065e2: 697a ldr r2, [r7, #20] - 80065e4: f002 0203 and.w r2, r2, #3 - 80065e8: 0092 lsls r2, r2, #2 - 80065ea: 4093 lsls r3, r2 - 80065ec: 693a ldr r2, [r7, #16] - 80065ee: 4313 orrs r3, r2 - 80065f0: 613b str r3, [r7, #16] + 80070c8: 687b ldr r3, [r7, #4] + 80070ca: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 + 80070ce: d00d beq.n 80070ec + 80070d0: 687b ldr r3, [r7, #4] + 80070d2: 4a43 ldr r2, [pc, #268] ; (80071e0 ) + 80070d4: 4293 cmp r3, r2 + 80070d6: d007 beq.n 80070e8 + 80070d8: 687b ldr r3, [r7, #4] + 80070da: 4a42 ldr r2, [pc, #264] ; (80071e4 ) + 80070dc: 4293 cmp r3, r2 + 80070de: d101 bne.n 80070e4 + 80070e0: 2302 movs r3, #2 + 80070e2: e004 b.n 80070ee + 80070e4: 2307 movs r3, #7 + 80070e6: e002 b.n 80070ee + 80070e8: 2301 movs r3, #1 + 80070ea: e000 b.n 80070ee + 80070ec: 2300 movs r3, #0 + 80070ee: 697a ldr r2, [r7, #20] + 80070f0: f002 0203 and.w r2, r2, #3 + 80070f4: 0092 lsls r2, r2, #2 + 80070f6: 4093 lsls r3, r2 + 80070f8: 693a ldr r2, [r7, #16] + 80070fa: 4313 orrs r3, r2 + 80070fc: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; - 80065f2: 4937 ldr r1, [pc, #220] ; (80066d0 ) - 80065f4: 697b ldr r3, [r7, #20] - 80065f6: 089b lsrs r3, r3, #2 - 80065f8: 3302 adds r3, #2 - 80065fa: 693a ldr r2, [r7, #16] - 80065fc: f841 2023 str.w r2, [r1, r3, lsl #2] + 80070fe: 4937 ldr r1, [pc, #220] ; (80071dc ) + 8007100: 697b ldr r3, [r7, #20] + 8007102: 089b lsrs r3, r3, #2 + 8007104: 3302 adds r3, #2 + 8007106: 693a ldr r2, [r7, #16] + 8007108: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; - 8006600: 4b36 ldr r3, [pc, #216] ; (80066dc ) - 8006602: 689b ldr r3, [r3, #8] - 8006604: 613b str r3, [r7, #16] + 800710c: 4b36 ldr r3, [pc, #216] ; (80071e8 ) + 800710e: 689b ldr r3, [r3, #8] + 8007110: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8006606: 68fb ldr r3, [r7, #12] - 8006608: 43db mvns r3, r3 - 800660a: 693a ldr r2, [r7, #16] - 800660c: 4013 ands r3, r2 - 800660e: 613b str r3, [r7, #16] + 8007112: 68fb ldr r3, [r7, #12] + 8007114: 43db mvns r3, r3 + 8007116: 693a ldr r2, [r7, #16] + 8007118: 4013 ands r3, r2 + 800711a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - 8006610: 683b ldr r3, [r7, #0] - 8006612: 685b ldr r3, [r3, #4] - 8006614: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8006618: 2b00 cmp r3, #0 - 800661a: d003 beq.n 8006624 + 800711c: 683b ldr r3, [r7, #0] + 800711e: 685b ldr r3, [r3, #4] + 8007120: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8007124: 2b00 cmp r3, #0 + 8007126: d003 beq.n 8007130 { temp |= iocurrent; - 800661c: 693a ldr r2, [r7, #16] - 800661e: 68fb ldr r3, [r7, #12] - 8006620: 4313 orrs r3, r2 - 8006622: 613b str r3, [r7, #16] + 8007128: 693a ldr r2, [r7, #16] + 800712a: 68fb ldr r3, [r7, #12] + 800712c: 4313 orrs r3, r2 + 800712e: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; - 8006624: 4a2d ldr r2, [pc, #180] ; (80066dc ) - 8006626: 693b ldr r3, [r7, #16] - 8006628: 6093 str r3, [r2, #8] + 8007130: 4a2d ldr r2, [pc, #180] ; (80071e8 ) + 8007132: 693b ldr r3, [r7, #16] + 8007134: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; - 800662a: 4b2c ldr r3, [pc, #176] ; (80066dc ) - 800662c: 68db ldr r3, [r3, #12] - 800662e: 613b str r3, [r7, #16] + 8007136: 4b2c ldr r3, [pc, #176] ; (80071e8 ) + 8007138: 68db ldr r3, [r3, #12] + 800713a: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8006630: 68fb ldr r3, [r7, #12] - 8006632: 43db mvns r3, r3 - 8006634: 693a ldr r2, [r7, #16] - 8006636: 4013 ands r3, r2 - 8006638: 613b str r3, [r7, #16] + 800713c: 68fb ldr r3, [r7, #12] + 800713e: 43db mvns r3, r3 + 8007140: 693a ldr r2, [r7, #16] + 8007142: 4013 ands r3, r2 + 8007144: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - 800663a: 683b ldr r3, [r7, #0] - 800663c: 685b ldr r3, [r3, #4] - 800663e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8006642: 2b00 cmp r3, #0 - 8006644: d003 beq.n 800664e + 8007146: 683b ldr r3, [r7, #0] + 8007148: 685b ldr r3, [r3, #4] + 800714a: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800714e: 2b00 cmp r3, #0 + 8007150: d003 beq.n 800715a { temp |= iocurrent; - 8006646: 693a ldr r2, [r7, #16] - 8006648: 68fb ldr r3, [r7, #12] - 800664a: 4313 orrs r3, r2 - 800664c: 613b str r3, [r7, #16] + 8007152: 693a ldr r2, [r7, #16] + 8007154: 68fb ldr r3, [r7, #12] + 8007156: 4313 orrs r3, r2 + 8007158: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; - 800664e: 4a23 ldr r2, [pc, #140] ; (80066dc ) - 8006650: 693b ldr r3, [r7, #16] - 8006652: 60d3 str r3, [r2, #12] + 800715a: 4a23 ldr r2, [pc, #140] ; (80071e8 ) + 800715c: 693b ldr r3, [r7, #16] + 800715e: 60d3 str r3, [r2, #12] /* Clear EXTI line configuration */ temp = EXTI->EMR1; - 8006654: 4b21 ldr r3, [pc, #132] ; (80066dc ) - 8006656: 685b ldr r3, [r3, #4] - 8006658: 613b str r3, [r7, #16] + 8007160: 4b21 ldr r3, [pc, #132] ; (80071e8 ) + 8007162: 685b ldr r3, [r3, #4] + 8007164: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 800665a: 68fb ldr r3, [r7, #12] - 800665c: 43db mvns r3, r3 - 800665e: 693a ldr r2, [r7, #16] - 8006660: 4013 ands r3, r2 - 8006662: 613b str r3, [r7, #16] + 8007166: 68fb ldr r3, [r7, #12] + 8007168: 43db mvns r3, r3 + 800716a: 693a ldr r2, [r7, #16] + 800716c: 4013 ands r3, r2 + 800716e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) - 8006664: 683b ldr r3, [r7, #0] - 8006666: 685b ldr r3, [r3, #4] - 8006668: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800666c: 2b00 cmp r3, #0 - 800666e: d003 beq.n 8006678 + 8007170: 683b ldr r3, [r7, #0] + 8007172: 685b ldr r3, [r3, #4] + 8007174: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007178: 2b00 cmp r3, #0 + 800717a: d003 beq.n 8007184 { temp |= iocurrent; - 8006670: 693a ldr r2, [r7, #16] - 8006672: 68fb ldr r3, [r7, #12] - 8006674: 4313 orrs r3, r2 - 8006676: 613b str r3, [r7, #16] + 800717c: 693a ldr r2, [r7, #16] + 800717e: 68fb ldr r3, [r7, #12] + 8007180: 4313 orrs r3, r2 + 8007182: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; - 8006678: 4a18 ldr r2, [pc, #96] ; (80066dc ) - 800667a: 693b ldr r3, [r7, #16] - 800667c: 6053 str r3, [r2, #4] + 8007184: 4a18 ldr r2, [pc, #96] ; (80071e8 ) + 8007186: 693b ldr r3, [r7, #16] + 8007188: 6053 str r3, [r2, #4] temp = EXTI->IMR1; - 800667e: 4b17 ldr r3, [pc, #92] ; (80066dc ) - 8006680: 681b ldr r3, [r3, #0] - 8006682: 613b str r3, [r7, #16] + 800718a: 4b17 ldr r3, [pc, #92] ; (80071e8 ) + 800718c: 681b ldr r3, [r3, #0] + 800718e: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8006684: 68fb ldr r3, [r7, #12] - 8006686: 43db mvns r3, r3 - 8006688: 693a ldr r2, [r7, #16] - 800668a: 4013 ands r3, r2 - 800668c: 613b str r3, [r7, #16] + 8007190: 68fb ldr r3, [r7, #12] + 8007192: 43db mvns r3, r3 + 8007194: 693a ldr r2, [r7, #16] + 8007196: 4013 ands r3, r2 + 8007198: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) - 800668e: 683b ldr r3, [r7, #0] - 8006690: 685b ldr r3, [r3, #4] - 8006692: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8006696: 2b00 cmp r3, #0 - 8006698: d003 beq.n 80066a2 + 800719a: 683b ldr r3, [r7, #0] + 800719c: 685b ldr r3, [r3, #4] + 800719e: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80071a2: 2b00 cmp r3, #0 + 80071a4: d003 beq.n 80071ae { temp |= iocurrent; - 800669a: 693a ldr r2, [r7, #16] - 800669c: 68fb ldr r3, [r7, #12] - 800669e: 4313 orrs r3, r2 - 80066a0: 613b str r3, [r7, #16] + 80071a6: 693a ldr r2, [r7, #16] + 80071a8: 68fb ldr r3, [r7, #12] + 80071aa: 4313 orrs r3, r2 + 80071ac: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; - 80066a2: 4a0e ldr r2, [pc, #56] ; (80066dc ) - 80066a4: 693b ldr r3, [r7, #16] - 80066a6: 6013 str r3, [r2, #0] + 80071ae: 4a0e ldr r2, [pc, #56] ; (80071e8 ) + 80071b0: 693b ldr r3, [r7, #16] + 80071b2: 6013 str r3, [r2, #0] } } position++; - 80066a8: 697b ldr r3, [r7, #20] - 80066aa: 3301 adds r3, #1 - 80066ac: 617b str r3, [r7, #20] + 80071b4: 697b ldr r3, [r7, #20] + 80071b6: 3301 adds r3, #1 + 80071b8: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) - 80066ae: 683b ldr r3, [r7, #0] - 80066b0: 681a ldr r2, [r3, #0] - 80066b2: 697b ldr r3, [r7, #20] - 80066b4: fa22 f303 lsr.w r3, r2, r3 - 80066b8: 2b00 cmp r3, #0 - 80066ba: f47f aeaf bne.w 800641c - } -} - 80066be: bf00 nop - 80066c0: bf00 nop - 80066c2: 371c adds r7, #28 - 80066c4: 46bd mov sp, r7 - 80066c6: f85d 7b04 ldr.w r7, [sp], #4 - 80066ca: 4770 bx lr - 80066cc: 40021000 .word 0x40021000 - 80066d0: 40010000 .word 0x40010000 - 80066d4: 48000400 .word 0x48000400 - 80066d8: 48000800 .word 0x48000800 - 80066dc: 40010400 .word 0x40010400 - -080066e0 : - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - 80066e0: b480 push {r7} - 80066e2: b087 sub sp, #28 - 80066e4: af00 add r7, sp, #0 - 80066e6: 6078 str r0, [r7, #4] - 80066e8: 6039 str r1, [r7, #0] - uint32_t position = 0x00u; - 80066ea: 2300 movs r3, #0 - 80066ec: 617b str r3, [r7, #20] - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0x00u) - 80066ee: e0ab b.n 8006848 - { - /* Get current io position */ - iocurrent = (GPIO_Pin) & (1uL << position); - 80066f0: 2201 movs r2, #1 - 80066f2: 697b ldr r3, [r7, #20] - 80066f4: fa02 f303 lsl.w r3, r2, r3 - 80066f8: 683a ldr r2, [r7, #0] - 80066fa: 4013 ands r3, r2 - 80066fc: 613b str r3, [r7, #16] - - if (iocurrent != 0x00u) - 80066fe: 693b ldr r3, [r7, #16] - 8006700: 2b00 cmp r3, #0 - 8006702: f000 809e beq.w 8006842 - { - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2u]; - 8006706: 4a57 ldr r2, [pc, #348] ; (8006864 ) - 8006708: 697b ldr r3, [r7, #20] - 800670a: 089b lsrs r3, r3, #2 - 800670c: 3302 adds r3, #2 - 800670e: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8006712: 60fb str r3, [r7, #12] - tmp &= (0x0FuL << (4u * (position & 0x03u))); - 8006714: 697b ldr r3, [r7, #20] - 8006716: f003 0303 and.w r3, r3, #3 - 800671a: 009b lsls r3, r3, #2 - 800671c: 220f movs r2, #15 - 800671e: fa02 f303 lsl.w r3, r2, r3 - 8006722: 68fa ldr r2, [r7, #12] - 8006724: 4013 ands r3, r2 - 8006726: 60fb str r3, [r7, #12] - if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) - 8006728: 687b ldr r3, [r7, #4] - 800672a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 - 800672e: d00d beq.n 800674c - 8006730: 687b ldr r3, [r7, #4] - 8006732: 4a4d ldr r2, [pc, #308] ; (8006868 ) - 8006734: 4293 cmp r3, r2 - 8006736: d007 beq.n 8006748 - 8006738: 687b ldr r3, [r7, #4] - 800673a: 4a4c ldr r2, [pc, #304] ; (800686c ) - 800673c: 4293 cmp r3, r2 - 800673e: d101 bne.n 8006744 - 8006740: 2302 movs r3, #2 - 8006742: e004 b.n 800674e - 8006744: 2307 movs r3, #7 - 8006746: e002 b.n 800674e - 8006748: 2301 movs r3, #1 - 800674a: e000 b.n 800674e - 800674c: 2300 movs r3, #0 - 800674e: 697a ldr r2, [r7, #20] - 8006750: f002 0203 and.w r2, r2, #3 - 8006754: 0092 lsls r2, r2, #2 - 8006756: 4093 lsls r3, r2 - 8006758: 68fa ldr r2, [r7, #12] - 800675a: 429a cmp r2, r3 - 800675c: d132 bne.n 80067c4 - { - /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~(iocurrent); - 800675e: 4b44 ldr r3, [pc, #272] ; (8006870 ) - 8006760: 681a ldr r2, [r3, #0] - 8006762: 693b ldr r3, [r7, #16] - 8006764: 43db mvns r3, r3 - 8006766: 4942 ldr r1, [pc, #264] ; (8006870 ) - 8006768: 4013 ands r3, r2 - 800676a: 600b str r3, [r1, #0] - EXTI->EMR1 &= ~(iocurrent); - 800676c: 4b40 ldr r3, [pc, #256] ; (8006870 ) - 800676e: 685a ldr r2, [r3, #4] - 8006770: 693b ldr r3, [r7, #16] - 8006772: 43db mvns r3, r3 - 8006774: 493e ldr r1, [pc, #248] ; (8006870 ) - 8006776: 4013 ands r3, r2 - 8006778: 604b str r3, [r1, #4] - - /* Clear Rising Falling edge configuration */ - EXTI->FTSR1 &= ~(iocurrent); - 800677a: 4b3d ldr r3, [pc, #244] ; (8006870 ) - 800677c: 68da ldr r2, [r3, #12] - 800677e: 693b ldr r3, [r7, #16] - 8006780: 43db mvns r3, r3 - 8006782: 493b ldr r1, [pc, #236] ; (8006870 ) - 8006784: 4013 ands r3, r2 - 8006786: 60cb str r3, [r1, #12] - EXTI->RTSR1 &= ~(iocurrent); - 8006788: 4b39 ldr r3, [pc, #228] ; (8006870 ) - 800678a: 689a ldr r2, [r3, #8] - 800678c: 693b ldr r3, [r7, #16] - 800678e: 43db mvns r3, r3 - 8006790: 4937 ldr r1, [pc, #220] ; (8006870 ) - 8006792: 4013 ands r3, r2 - 8006794: 608b str r3, [r1, #8] - - tmp = 0x0FuL << (4u * (position & 0x03u)); - 8006796: 697b ldr r3, [r7, #20] - 8006798: f003 0303 and.w r3, r3, #3 - 800679c: 009b lsls r3, r3, #2 - 800679e: 220f movs r2, #15 - 80067a0: fa02 f303 lsl.w r3, r2, r3 - 80067a4: 60fb str r3, [r7, #12] - SYSCFG->EXTICR[position >> 2u] &= ~tmp; - 80067a6: 4a2f ldr r2, [pc, #188] ; (8006864 ) - 80067a8: 697b ldr r3, [r7, #20] - 80067aa: 089b lsrs r3, r3, #2 - 80067ac: 3302 adds r3, #2 - 80067ae: f852 1023 ldr.w r1, [r2, r3, lsl #2] - 80067b2: 68fb ldr r3, [r7, #12] - 80067b4: 43da mvns r2, r3 - 80067b6: 482b ldr r0, [pc, #172] ; (8006864 ) - 80067b8: 697b ldr r3, [r7, #20] - 80067ba: 089b lsrs r3, r3, #2 - 80067bc: 400a ands r2, r1 - 80067be: 3302 adds r3, #2 - 80067c0: f840 2023 str.w r2, [r0, r3, lsl #2] - } - - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); - 80067c4: 687b ldr r3, [r7, #4] - 80067c6: 681a ldr r2, [r3, #0] - 80067c8: 697b ldr r3, [r7, #20] - 80067ca: 005b lsls r3, r3, #1 - 80067cc: 2103 movs r1, #3 - 80067ce: fa01 f303 lsl.w r3, r1, r3 - 80067d2: 431a orrs r2, r3 - 80067d4: 687b ldr r3, [r7, #4] - 80067d6: 601a str r2, [r3, #0] - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; - 80067d8: 697b ldr r3, [r7, #20] - 80067da: 08da lsrs r2, r3, #3 - 80067dc: 687b ldr r3, [r7, #4] - 80067de: 3208 adds r2, #8 - 80067e0: f853 1022 ldr.w r1, [r3, r2, lsl #2] - 80067e4: 697b ldr r3, [r7, #20] - 80067e6: f003 0307 and.w r3, r3, #7 - 80067ea: 009b lsls r3, r3, #2 - 80067ec: 220f movs r2, #15 - 80067ee: fa02 f303 lsl.w r3, r2, r3 - 80067f2: 43db mvns r3, r3 - 80067f4: 697a ldr r2, [r7, #20] - 80067f6: 08d2 lsrs r2, r2, #3 - 80067f8: 4019 ands r1, r3 - 80067fa: 687b ldr r3, [r7, #4] - 80067fc: 3208 adds r2, #8 - 80067fe: f843 1022 str.w r1, [r3, r2, lsl #2] - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); - 8006802: 687b ldr r3, [r7, #4] - 8006804: 689a ldr r2, [r3, #8] - 8006806: 697b ldr r3, [r7, #20] - 8006808: 005b lsls r3, r3, #1 - 800680a: 2103 movs r1, #3 - 800680c: fa01 f303 lsl.w r3, r1, r3 - 8006810: 43db mvns r3, r3 - 8006812: 401a ands r2, r3 - 8006814: 687b ldr r3, [r7, #4] - 8006816: 609a str r2, [r3, #8] - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - 8006818: 687b ldr r3, [r7, #4] - 800681a: 685a ldr r2, [r3, #4] - 800681c: 2101 movs r1, #1 - 800681e: 697b ldr r3, [r7, #20] - 8006820: fa01 f303 lsl.w r3, r1, r3 - 8006824: 43db mvns r3, r3 - 8006826: 401a ands r2, r3 - 8006828: 687b ldr r3, [r7, #4] - 800682a: 605a str r2, [r3, #4] - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); - 800682c: 687b ldr r3, [r7, #4] - 800682e: 68da ldr r2, [r3, #12] - 8006830: 697b ldr r3, [r7, #20] - 8006832: 005b lsls r3, r3, #1 - 8006834: 2103 movs r1, #3 - 8006836: fa01 f303 lsl.w r3, r1, r3 - 800683a: 43db mvns r3, r3 - 800683c: 401a ands r2, r3 - 800683e: 687b ldr r3, [r7, #4] - 8006840: 60da str r2, [r3, #12] - /* Deactivate the Control bit of Analog mode for the current IO */ - GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position); -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - } - - position++; - 8006842: 697b ldr r3, [r7, #20] - 8006844: 3301 adds r3, #1 - 8006846: 617b str r3, [r7, #20] - while ((GPIO_Pin >> position) != 0x00u) - 8006848: 683a ldr r2, [r7, #0] - 800684a: 697b ldr r3, [r7, #20] - 800684c: fa22 f303 lsr.w r3, r2, r3 - 8006850: 2b00 cmp r3, #0 - 8006852: f47f af4d bne.w 80066f0 - } -} - 8006856: bf00 nop - 8006858: bf00 nop - 800685a: 371c adds r7, #28 - 800685c: 46bd mov sp, r7 - 800685e: f85d 7b04 ldr.w r7, [sp], #4 - 8006862: 4770 bx lr - 8006864: 40010000 .word 0x40010000 - 8006868: 48000400 .word 0x48000400 - 800686c: 48000800 .word 0x48000800 - 8006870: 40010400 .word 0x40010400 - -08006874 : + 80071ba: 683b ldr r3, [r7, #0] + 80071bc: 681a ldr r2, [r3, #0] + 80071be: 697b ldr r3, [r7, #20] + 80071c0: fa22 f303 lsr.w r3, r2, r3 + 80071c4: 2b00 cmp r3, #0 + 80071c6: f47f aeaf bne.w 8006f28 + } +} + 80071ca: bf00 nop + 80071cc: bf00 nop + 80071ce: 371c adds r7, #28 + 80071d0: 46bd mov sp, r7 + 80071d2: f85d 7b04 ldr.w r7, [sp], #4 + 80071d6: 4770 bx lr + 80071d8: 40021000 .word 0x40021000 + 80071dc: 40010000 .word 0x40010000 + 80071e0: 48000400 .word 0x48000400 + 80071e4: 48000800 .word 0x48000800 + 80071e8: 40010400 .word 0x40010400 + +080071ec : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8006874: b480 push {r7} - 8006876: b083 sub sp, #12 - 8006878: af00 add r7, sp, #0 - 800687a: 6078 str r0, [r7, #4] - 800687c: 460b mov r3, r1 - 800687e: 807b strh r3, [r7, #2] - 8006880: 4613 mov r3, r2 - 8006882: 707b strb r3, [r7, #1] + 80071ec: b480 push {r7} + 80071ee: b083 sub sp, #12 + 80071f0: af00 add r7, sp, #0 + 80071f2: 6078 str r0, [r7, #4] + 80071f4: 460b mov r3, r1 + 80071f6: 807b strh r3, [r7, #2] + 80071f8: 4613 mov r3, r2 + 80071fa: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 8006884: 787b ldrb r3, [r7, #1] - 8006886: 2b00 cmp r3, #0 - 8006888: d003 beq.n 8006892 + 80071fc: 787b ldrb r3, [r7, #1] + 80071fe: 2b00 cmp r3, #0 + 8007200: d003 beq.n 800720a { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 800688a: 887a ldrh r2, [r7, #2] - 800688c: 687b ldr r3, [r7, #4] - 800688e: 619a str r2, [r3, #24] + 8007202: 887a ldrh r2, [r7, #2] + 8007204: 687b ldr r3, [r7, #4] + 8007206: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 8006890: e002 b.n 8006898 + 8007208: e002 b.n 8007210 GPIOx->BRR = (uint32_t)GPIO_Pin; - 8006892: 887a ldrh r2, [r7, #2] - 8006894: 687b ldr r3, [r7, #4] - 8006896: 629a str r2, [r3, #40] ; 0x28 + 800720a: 887a ldrh r2, [r7, #2] + 800720c: 687b ldr r3, [r7, #4] + 800720e: 629a str r2, [r3, #40] ; 0x28 } - 8006898: bf00 nop - 800689a: 370c adds r7, #12 - 800689c: 46bd mov sp, r7 - 800689e: f85d 7b04 ldr.w r7, [sp], #4 - 80068a2: 4770 bx lr + 8007210: bf00 nop + 8007212: 370c adds r7, #12 + 8007214: 46bd mov sp, r7 + 8007216: f85d 7b04 ldr.w r7, [sp], #4 + 800721a: 4770 bx lr -080068a4 : +0800721c : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { - 80068a4: b580 push {r7, lr} - 80068a6: b082 sub sp, #8 - 80068a8: af00 add r7, sp, #0 - 80068aa: 4603 mov r3, r0 - 80068ac: 80fb strh r3, [r7, #6] + 800721c: b580 push {r7, lr} + 800721e: b082 sub sp, #8 + 8007220: af00 add r7, sp, #0 + 8007222: 4603 mov r3, r0 + 8007224: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) - 80068ae: 4b08 ldr r3, [pc, #32] ; (80068d0 ) - 80068b0: 695a ldr r2, [r3, #20] - 80068b2: 88fb ldrh r3, [r7, #6] - 80068b4: 4013 ands r3, r2 - 80068b6: 2b00 cmp r3, #0 - 80068b8: d006 beq.n 80068c8 + 8007226: 4b08 ldr r3, [pc, #32] ; (8007248 ) + 8007228: 695a ldr r2, [r3, #20] + 800722a: 88fb ldrh r3, [r7, #6] + 800722c: 4013 ands r3, r2 + 800722e: 2b00 cmp r3, #0 + 8007230: d006 beq.n 8007240 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - 80068ba: 4a05 ldr r2, [pc, #20] ; (80068d0 ) - 80068bc: 88fb ldrh r3, [r7, #6] - 80068be: 6153 str r3, [r2, #20] + 8007232: 4a05 ldr r2, [pc, #20] ; (8007248 ) + 8007234: 88fb ldrh r3, [r7, #6] + 8007236: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); - 80068c0: 88fb ldrh r3, [r7, #6] - 80068c2: 4618 mov r0, r3 - 80068c4: f7fa fb94 bl 8000ff0 + 8007238: 88fb ldrh r3, [r7, #6] + 800723a: 4618 mov r0, r3 + 800723c: f7fa fa8c bl 8001758 } } - 80068c8: bf00 nop - 80068ca: 3708 adds r7, #8 - 80068cc: 46bd mov sp, r7 - 80068ce: bd80 pop {r7, pc} - 80068d0: 40010400 .word 0x40010400 + 8007240: bf00 nop + 8007242: 3708 adds r7, #8 + 8007244: 46bd mov sp, r7 + 8007246: bd80 pop {r7, pc} + 8007248: 40010400 .word 0x40010400 -080068d4 : +0800724c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { - 80068d4: b580 push {r7, lr} - 80068d6: b082 sub sp, #8 - 80068d8: af00 add r7, sp, #0 - 80068da: 6078 str r0, [r7, #4] + 800724c: b580 push {r7, lr} + 800724e: b082 sub sp, #8 + 8007250: af00 add r7, sp, #0 + 8007252: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) - 80068dc: 687b ldr r3, [r7, #4] - 80068de: 2b00 cmp r3, #0 - 80068e0: d101 bne.n 80068e6 + 8007254: 687b ldr r3, [r7, #4] + 8007256: 2b00 cmp r3, #0 + 8007258: d101 bne.n 800725e { return HAL_ERROR; - 80068e2: 2301 movs r3, #1 - 80068e4: e08d b.n 8006a02 + 800725a: 2301 movs r3, #1 + 800725c: e08d b.n 800737a assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) - 80068e6: 687b ldr r3, [r7, #4] - 80068e8: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 - 80068ec: b2db uxtb r3, r3 - 80068ee: 2b00 cmp r3, #0 - 80068f0: d106 bne.n 8006900 + 800725e: 687b ldr r3, [r7, #4] + 8007260: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8007264: b2db uxtb r3, r3 + 8007266: 2b00 cmp r3, #0 + 8007268: d106 bne.n 8007278 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; - 80068f2: 687b ldr r3, [r7, #4] - 80068f4: 2200 movs r2, #0 - 80068f6: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 800726a: 687b ldr r3, [r7, #4] + 800726c: 2200 movs r2, #0 + 800726e: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); - 80068fa: 6878 ldr r0, [r7, #4] - 80068fc: f7fd fb00 bl 8003f00 + 8007272: 6878 ldr r0, [r7, #4] + 8007274: f7fa f9b2 bl 80015dc #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; - 8006900: 687b ldr r3, [r7, #4] - 8006902: 2224 movs r2, #36 ; 0x24 - 8006904: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007278: 687b ldr r3, [r7, #4] + 800727a: 2224 movs r2, #36 ; 0x24 + 800727c: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - 8006908: 687b ldr r3, [r7, #4] - 800690a: 681b ldr r3, [r3, #0] - 800690c: 681a ldr r2, [r3, #0] - 800690e: 687b ldr r3, [r7, #4] - 8006910: 681b ldr r3, [r3, #0] - 8006912: f022 0201 bic.w r2, r2, #1 - 8006916: 601a str r2, [r3, #0] + 8007280: 687b ldr r3, [r7, #4] + 8007282: 681b ldr r3, [r3, #0] + 8007284: 681a ldr r2, [r3, #0] + 8007286: 687b ldr r3, [r7, #4] + 8007288: 681b ldr r3, [r3, #0] + 800728a: f022 0201 bic.w r2, r2, #1 + 800728e: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - 8006918: 687b ldr r3, [r7, #4] - 800691a: 685a ldr r2, [r3, #4] - 800691c: 687b ldr r3, [r7, #4] - 800691e: 681b ldr r3, [r3, #0] - 8006920: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 - 8006924: 611a str r2, [r3, #16] + 8007290: 687b ldr r3, [r7, #4] + 8007292: 685a ldr r2, [r3, #4] + 8007294: 687b ldr r3, [r7, #4] + 8007296: 681b ldr r3, [r3, #0] + 8007298: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 800729c: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - 8006926: 687b ldr r3, [r7, #4] - 8006928: 681b ldr r3, [r3, #0] - 800692a: 689a ldr r2, [r3, #8] - 800692c: 687b ldr r3, [r7, #4] - 800692e: 681b ldr r3, [r3, #0] - 8006930: f422 4200 bic.w r2, r2, #32768 ; 0x8000 - 8006934: 609a str r2, [r3, #8] + 800729e: 687b ldr r3, [r7, #4] + 80072a0: 681b ldr r3, [r3, #0] + 80072a2: 689a ldr r2, [r3, #8] + 80072a4: 687b ldr r3, [r7, #4] + 80072a6: 681b ldr r3, [r3, #0] + 80072a8: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 80072ac: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - 8006936: 687b ldr r3, [r7, #4] - 8006938: 68db ldr r3, [r3, #12] - 800693a: 2b01 cmp r3, #1 - 800693c: d107 bne.n 800694e + 80072ae: 687b ldr r3, [r7, #4] + 80072b0: 68db ldr r3, [r3, #12] + 80072b2: 2b01 cmp r3, #1 + 80072b4: d107 bne.n 80072c6 { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - 800693e: 687b ldr r3, [r7, #4] - 8006940: 689a ldr r2, [r3, #8] - 8006942: 687b ldr r3, [r7, #4] - 8006944: 681b ldr r3, [r3, #0] - 8006946: f442 4200 orr.w r2, r2, #32768 ; 0x8000 - 800694a: 609a str r2, [r3, #8] - 800694c: e006 b.n 800695c + 80072b6: 687b ldr r3, [r7, #4] + 80072b8: 689a ldr r2, [r3, #8] + 80072ba: 687b ldr r3, [r7, #4] + 80072bc: 681b ldr r3, [r3, #0] + 80072be: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 80072c2: 609a str r2, [r3, #8] + 80072c4: e006 b.n 80072d4 } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - 800694e: 687b ldr r3, [r7, #4] - 8006950: 689a ldr r2, [r3, #8] - 8006952: 687b ldr r3, [r7, #4] - 8006954: 681b ldr r3, [r3, #0] - 8006956: f442 4204 orr.w r2, r2, #33792 ; 0x8400 - 800695a: 609a str r2, [r3, #8] + 80072c6: 687b ldr r3, [r7, #4] + 80072c8: 689a ldr r2, [r3, #8] + 80072ca: 687b ldr r3, [r7, #4] + 80072cc: 681b ldr r3, [r3, #0] + 80072ce: f442 4204 orr.w r2, r2, #33792 ; 0x8400 + 80072d2: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - 800695c: 687b ldr r3, [r7, #4] - 800695e: 68db ldr r3, [r3, #12] - 8006960: 2b02 cmp r3, #2 - 8006962: d108 bne.n 8006976 + 80072d4: 687b ldr r3, [r7, #4] + 80072d6: 68db ldr r3, [r3, #12] + 80072d8: 2b02 cmp r3, #2 + 80072da: d108 bne.n 80072ee { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - 8006964: 687b ldr r3, [r7, #4] - 8006966: 681b ldr r3, [r3, #0] - 8006968: 685a ldr r2, [r3, #4] - 800696a: 687b ldr r3, [r7, #4] - 800696c: 681b ldr r3, [r3, #0] - 800696e: f442 6200 orr.w r2, r2, #2048 ; 0x800 - 8006972: 605a str r2, [r3, #4] - 8006974: e007 b.n 8006986 + 80072dc: 687b ldr r3, [r7, #4] + 80072de: 681b ldr r3, [r3, #0] + 80072e0: 685a ldr r2, [r3, #4] + 80072e2: 687b ldr r3, [r7, #4] + 80072e4: 681b ldr r3, [r3, #0] + 80072e6: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 80072ea: 605a str r2, [r3, #4] + 80072ec: e007 b.n 80072fe } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - 8006976: 687b ldr r3, [r7, #4] - 8006978: 681b ldr r3, [r3, #0] - 800697a: 685a ldr r2, [r3, #4] - 800697c: 687b ldr r3, [r7, #4] - 800697e: 681b ldr r3, [r3, #0] - 8006980: f422 6200 bic.w r2, r2, #2048 ; 0x800 - 8006984: 605a str r2, [r3, #4] + 80072ee: 687b ldr r3, [r7, #4] + 80072f0: 681b ldr r3, [r3, #0] + 80072f2: 685a ldr r2, [r3, #4] + 80072f4: 687b ldr r3, [r7, #4] + 80072f6: 681b ldr r3, [r3, #0] + 80072f8: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 80072fc: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - 8006986: 687b ldr r3, [r7, #4] - 8006988: 681b ldr r3, [r3, #0] - 800698a: 685b ldr r3, [r3, #4] - 800698c: 687a ldr r2, [r7, #4] - 800698e: 6812 ldr r2, [r2, #0] - 8006990: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 - 8006994: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8006998: 6053 str r3, [r2, #4] + 80072fe: 687b ldr r3, [r7, #4] + 8007300: 681b ldr r3, [r3, #0] + 8007302: 685b ldr r3, [r3, #4] + 8007304: 687a ldr r2, [r7, #4] + 8007306: 6812 ldr r2, [r2, #0] + 8007308: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 800730c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8007310: 6053 str r3, [r2, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - 800699a: 687b ldr r3, [r7, #4] - 800699c: 681b ldr r3, [r3, #0] - 800699e: 68da ldr r2, [r3, #12] - 80069a0: 687b ldr r3, [r7, #4] - 80069a2: 681b ldr r3, [r3, #0] - 80069a4: f422 4200 bic.w r2, r2, #32768 ; 0x8000 - 80069a8: 60da str r2, [r3, #12] + 8007312: 687b ldr r3, [r7, #4] + 8007314: 681b ldr r3, [r3, #0] + 8007316: 68da ldr r2, [r3, #12] + 8007318: 687b ldr r3, [r7, #4] + 800731a: 681b ldr r3, [r3, #0] + 800731c: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8007320: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ - 80069aa: 687b ldr r3, [r7, #4] - 80069ac: 691a ldr r2, [r3, #16] - 80069ae: 687b ldr r3, [r7, #4] - 80069b0: 695b ldr r3, [r3, #20] - 80069b2: ea42 0103 orr.w r1, r2, r3 + 8007322: 687b ldr r3, [r7, #4] + 8007324: 691a ldr r2, [r3, #16] + 8007326: 687b ldr r3, [r7, #4] + 8007328: 695b ldr r3, [r3, #20] + 800732a: ea42 0103 orr.w r1, r2, r3 (hi2c->Init.OwnAddress2Masks << 8)); - 80069b6: 687b ldr r3, [r7, #4] - 80069b8: 699b ldr r3, [r3, #24] - 80069ba: 021a lsls r2, r3, #8 + 800732e: 687b ldr r3, [r7, #4] + 8007330: 699b ldr r3, [r3, #24] + 8007332: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ - 80069bc: 687b ldr r3, [r7, #4] - 80069be: 681b ldr r3, [r3, #0] - 80069c0: 430a orrs r2, r1 - 80069c2: 60da str r2, [r3, #12] + 8007334: 687b ldr r3, [r7, #4] + 8007336: 681b ldr r3, [r3, #0] + 8007338: 430a orrs r2, r1 + 800733a: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - 80069c4: 687b ldr r3, [r7, #4] - 80069c6: 69d9 ldr r1, [r3, #28] - 80069c8: 687b ldr r3, [r7, #4] - 80069ca: 6a1a ldr r2, [r3, #32] - 80069cc: 687b ldr r3, [r7, #4] - 80069ce: 681b ldr r3, [r3, #0] - 80069d0: 430a orrs r2, r1 - 80069d2: 601a str r2, [r3, #0] + 800733c: 687b ldr r3, [r7, #4] + 800733e: 69d9 ldr r1, [r3, #28] + 8007340: 687b ldr r3, [r7, #4] + 8007342: 6a1a ldr r2, [r3, #32] + 8007344: 687b ldr r3, [r7, #4] + 8007346: 681b ldr r3, [r3, #0] + 8007348: 430a orrs r2, r1 + 800734a: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); - 80069d4: 687b ldr r3, [r7, #4] - 80069d6: 681b ldr r3, [r3, #0] - 80069d8: 681a ldr r2, [r3, #0] - 80069da: 687b ldr r3, [r7, #4] - 80069dc: 681b ldr r3, [r3, #0] - 80069de: f042 0201 orr.w r2, r2, #1 - 80069e2: 601a str r2, [r3, #0] + 800734c: 687b ldr r3, [r7, #4] + 800734e: 681b ldr r3, [r3, #0] + 8007350: 681a ldr r2, [r3, #0] + 8007352: 687b ldr r3, [r7, #4] + 8007354: 681b ldr r3, [r3, #0] + 8007356: f042 0201 orr.w r2, r2, #1 + 800735a: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - 80069e4: 687b ldr r3, [r7, #4] - 80069e6: 2200 movs r2, #0 - 80069e8: 645a str r2, [r3, #68] ; 0x44 + 800735c: 687b ldr r3, [r7, #4] + 800735e: 2200 movs r2, #0 + 8007360: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; - 80069ea: 687b ldr r3, [r7, #4] - 80069ec: 2220 movs r2, #32 - 80069ee: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007362: 687b ldr r3, [r7, #4] + 8007364: 2220 movs r2, #32 + 8007366: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->PreviousState = I2C_STATE_NONE; - 80069f2: 687b ldr r3, [r7, #4] - 80069f4: 2200 movs r2, #0 - 80069f6: 631a str r2, [r3, #48] ; 0x30 + 800736a: 687b ldr r3, [r7, #4] + 800736c: 2200 movs r2, #0 + 800736e: 631a str r2, [r3, #48] ; 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; - 80069f8: 687b ldr r3, [r7, #4] - 80069fa: 2200 movs r2, #0 - 80069fc: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 8007370: 687b ldr r3, [r7, #4] + 8007372: 2200 movs r2, #0 + 8007374: f883 2042 strb.w r2, [r3, #66] ; 0x42 return HAL_OK; - 8006a00: 2300 movs r3, #0 + 8007378: 2300 movs r3, #0 } - 8006a02: 4618 mov r0, r3 - 8006a04: 3708 adds r7, #8 - 8006a06: 46bd mov sp, r7 - 8006a08: bd80 pop {r7, pc} + 800737a: 4618 mov r0, r3 + 800737c: 3708 adds r7, #8 + 800737e: 46bd mov sp, r7 + 8007380: bd80 pop {r7, pc} ... -08006a0c : +08007384 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 8006a0c: b580 push {r7, lr} - 8006a0e: b088 sub sp, #32 - 8006a10: af02 add r7, sp, #8 - 8006a12: 60f8 str r0, [r7, #12] - 8006a14: 4608 mov r0, r1 - 8006a16: 4611 mov r1, r2 - 8006a18: 461a mov r2, r3 - 8006a1a: 4603 mov r3, r0 - 8006a1c: 817b strh r3, [r7, #10] - 8006a1e: 460b mov r3, r1 - 8006a20: 813b strh r3, [r7, #8] - 8006a22: 4613 mov r3, r2 - 8006a24: 80fb strh r3, [r7, #6] + 8007384: b580 push {r7, lr} + 8007386: b088 sub sp, #32 + 8007388: af02 add r7, sp, #8 + 800738a: 60f8 str r0, [r7, #12] + 800738c: 4608 mov r0, r1 + 800738e: 4611 mov r1, r2 + 8007390: 461a mov r2, r3 + 8007392: 4603 mov r3, r0 + 8007394: 817b strh r3, [r7, #10] + 8007396: 460b mov r3, r1 + 8007398: 813b strh r3, [r7, #8] + 800739a: 4613 mov r3, r2 + 800739c: 80fb strh r3, [r7, #6] uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) - 8006a26: 68fb ldr r3, [r7, #12] - 8006a28: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 - 8006a2c: b2db uxtb r3, r3 - 8006a2e: 2b20 cmp r3, #32 - 8006a30: f040 80f9 bne.w 8006c26 + 800739e: 68fb ldr r3, [r7, #12] + 80073a0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 80073a4: b2db uxtb r3, r3 + 80073a6: 2b20 cmp r3, #32 + 80073a8: f040 80f9 bne.w 800759e { if ((pData == NULL) || (Size == 0U)) - 8006a34: 6a3b ldr r3, [r7, #32] - 8006a36: 2b00 cmp r3, #0 - 8006a38: d002 beq.n 8006a40 - 8006a3a: 8cbb ldrh r3, [r7, #36] ; 0x24 - 8006a3c: 2b00 cmp r3, #0 - 8006a3e: d105 bne.n 8006a4c + 80073ac: 6a3b ldr r3, [r7, #32] + 80073ae: 2b00 cmp r3, #0 + 80073b0: d002 beq.n 80073b8 + 80073b2: 8cbb ldrh r3, [r7, #36] ; 0x24 + 80073b4: 2b00 cmp r3, #0 + 80073b6: d105 bne.n 80073c4 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - 8006a40: 68fb ldr r3, [r7, #12] - 8006a42: f44f 7200 mov.w r2, #512 ; 0x200 - 8006a46: 645a str r2, [r3, #68] ; 0x44 + 80073b8: 68fb ldr r3, [r7, #12] + 80073ba: f44f 7200 mov.w r2, #512 ; 0x200 + 80073be: 645a str r2, [r3, #68] ; 0x44 return HAL_ERROR; - 8006a48: 2301 movs r3, #1 - 8006a4a: e0ed b.n 8006c28 + 80073c0: 2301 movs r3, #1 + 80073c2: e0ed b.n 80075a0 } /* Process Locked */ __HAL_LOCK(hi2c); - 8006a4c: 68fb ldr r3, [r7, #12] - 8006a4e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 - 8006a52: 2b01 cmp r3, #1 - 8006a54: d101 bne.n 8006a5a - 8006a56: 2302 movs r3, #2 - 8006a58: e0e6 b.n 8006c28 - 8006a5a: 68fb ldr r3, [r7, #12] - 8006a5c: 2201 movs r2, #1 - 8006a5e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 80073c4: 68fb ldr r3, [r7, #12] + 80073c6: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 80073ca: 2b01 cmp r3, #1 + 80073cc: d101 bne.n 80073d2 + 80073ce: 2302 movs r3, #2 + 80073d0: e0e6 b.n 80075a0 + 80073d2: 68fb ldr r3, [r7, #12] + 80073d4: 2201 movs r2, #1 + 80073d6: f883 2040 strb.w r2, [r3, #64] ; 0x40 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - 8006a62: f7fd fdab bl 80045bc - 8006a66: 6178 str r0, [r7, #20] + 80073da: f7fd ff39 bl 8005250 + 80073de: 6178 str r0, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - 8006a68: 697b ldr r3, [r7, #20] - 8006a6a: 9300 str r3, [sp, #0] - 8006a6c: 2319 movs r3, #25 - 8006a6e: 2201 movs r2, #1 - 8006a70: f44f 4100 mov.w r1, #32768 ; 0x8000 - 8006a74: 68f8 ldr r0, [r7, #12] - 8006a76: f000 f955 bl 8006d24 - 8006a7a: 4603 mov r3, r0 - 8006a7c: 2b00 cmp r3, #0 - 8006a7e: d001 beq.n 8006a84 + 80073e0: 697b ldr r3, [r7, #20] + 80073e2: 9300 str r3, [sp, #0] + 80073e4: 2319 movs r3, #25 + 80073e6: 2201 movs r2, #1 + 80073e8: f44f 4100 mov.w r1, #32768 ; 0x8000 + 80073ec: 68f8 ldr r0, [r7, #12] + 80073ee: f000 f955 bl 800769c + 80073f2: 4603 mov r3, r0 + 80073f4: 2b00 cmp r3, #0 + 80073f6: d001 beq.n 80073fc { return HAL_ERROR; - 8006a80: 2301 movs r3, #1 - 8006a82: e0d1 b.n 8006c28 + 80073f8: 2301 movs r3, #1 + 80073fa: e0d1 b.n 80075a0 } hi2c->State = HAL_I2C_STATE_BUSY_TX; - 8006a84: 68fb ldr r3, [r7, #12] - 8006a86: 2221 movs r2, #33 ; 0x21 - 8006a88: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 80073fc: 68fb ldr r3, [r7, #12] + 80073fe: 2221 movs r2, #33 ; 0x21 + 8007400: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_MEM; - 8006a8c: 68fb ldr r3, [r7, #12] - 8006a8e: 2240 movs r2, #64 ; 0x40 - 8006a90: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 8007404: 68fb ldr r3, [r7, #12] + 8007406: 2240 movs r2, #64 ; 0x40 + 8007408: f883 2042 strb.w r2, [r3, #66] ; 0x42 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - 8006a94: 68fb ldr r3, [r7, #12] - 8006a96: 2200 movs r2, #0 - 8006a98: 645a str r2, [r3, #68] ; 0x44 + 800740c: 68fb ldr r3, [r7, #12] + 800740e: 2200 movs r2, #0 + 8007410: 645a str r2, [r3, #68] ; 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; - 8006a9a: 68fb ldr r3, [r7, #12] - 8006a9c: 6a3a ldr r2, [r7, #32] - 8006a9e: 625a str r2, [r3, #36] ; 0x24 + 8007412: 68fb ldr r3, [r7, #12] + 8007414: 6a3a ldr r2, [r7, #32] + 8007416: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount = Size; - 8006aa0: 68fb ldr r3, [r7, #12] - 8006aa2: 8cba ldrh r2, [r7, #36] ; 0x24 - 8006aa4: 855a strh r2, [r3, #42] ; 0x2a + 8007418: 68fb ldr r3, [r7, #12] + 800741a: 8cba ldrh r2, [r7, #36] ; 0x24 + 800741c: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferISR = NULL; - 8006aa6: 68fb ldr r3, [r7, #12] - 8006aa8: 2200 movs r2, #0 - 8006aaa: 635a str r2, [r3, #52] ; 0x34 + 800741e: 68fb ldr r3, [r7, #12] + 8007420: 2200 movs r2, #0 + 8007422: 635a str r2, [r3, #52] ; 0x34 /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - 8006aac: 88f8 ldrh r0, [r7, #6] - 8006aae: 893a ldrh r2, [r7, #8] - 8006ab0: 8979 ldrh r1, [r7, #10] - 8006ab2: 697b ldr r3, [r7, #20] - 8006ab4: 9301 str r3, [sp, #4] - 8006ab6: 6abb ldr r3, [r7, #40] ; 0x28 - 8006ab8: 9300 str r3, [sp, #0] - 8006aba: 4603 mov r3, r0 - 8006abc: 68f8 ldr r0, [r7, #12] - 8006abe: f000 f8b9 bl 8006c34 - 8006ac2: 4603 mov r3, r0 - 8006ac4: 2b00 cmp r3, #0 - 8006ac6: d005 beq.n 8006ad4 + 8007424: 88f8 ldrh r0, [r7, #6] + 8007426: 893a ldrh r2, [r7, #8] + 8007428: 8979 ldrh r1, [r7, #10] + 800742a: 697b ldr r3, [r7, #20] + 800742c: 9301 str r3, [sp, #4] + 800742e: 6abb ldr r3, [r7, #40] ; 0x28 + 8007430: 9300 str r3, [sp, #0] + 8007432: 4603 mov r3, r0 + 8007434: 68f8 ldr r0, [r7, #12] + 8007436: f000 f8b9 bl 80075ac + 800743a: 4603 mov r3, r0 + 800743c: 2b00 cmp r3, #0 + 800743e: d005 beq.n 800744c { /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8006ac8: 68fb ldr r3, [r7, #12] - 8006aca: 2200 movs r2, #0 - 8006acc: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007440: 68fb ldr r3, [r7, #12] + 8007442: 2200 movs r2, #0 + 8007444: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; - 8006ad0: 2301 movs r3, #1 - 8006ad2: e0a9 b.n 8006c28 + 8007448: 2301 movs r3, #1 + 800744a: e0a9 b.n 80075a0 } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if (hi2c->XferCount > MAX_NBYTE_SIZE) - 8006ad4: 68fb ldr r3, [r7, #12] - 8006ad6: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006ad8: b29b uxth r3, r3 - 8006ada: 2bff cmp r3, #255 ; 0xff - 8006adc: d90e bls.n 8006afc + 800744c: 68fb ldr r3, [r7, #12] + 800744e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8007450: b29b uxth r3, r3 + 8007452: 2bff cmp r3, #255 ; 0xff + 8007454: d90e bls.n 8007474 { hi2c->XferSize = MAX_NBYTE_SIZE; - 8006ade: 68fb ldr r3, [r7, #12] - 8006ae0: 22ff movs r2, #255 ; 0xff - 8006ae2: 851a strh r2, [r3, #40] ; 0x28 + 8007456: 68fb ldr r3, [r7, #12] + 8007458: 22ff movs r2, #255 ; 0xff + 800745a: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - 8006ae4: 68fb ldr r3, [r7, #12] - 8006ae6: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006ae8: b2da uxtb r2, r3 - 8006aea: 8979 ldrh r1, [r7, #10] - 8006aec: 2300 movs r3, #0 - 8006aee: 9300 str r3, [sp, #0] - 8006af0: f04f 7380 mov.w r3, #16777216 ; 0x1000000 - 8006af4: 68f8 ldr r0, [r7, #12] - 8006af6: f000 facf bl 8007098 - 8006afa: e00f b.n 8006b1c + 800745c: 68fb ldr r3, [r7, #12] + 800745e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8007460: b2da uxtb r2, r3 + 8007462: 8979 ldrh r1, [r7, #10] + 8007464: 2300 movs r3, #0 + 8007466: 9300 str r3, [sp, #0] + 8007468: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 800746c: 68f8 ldr r0, [r7, #12] + 800746e: f000 facf bl 8007a10 + 8007472: e00f b.n 8007494 } else { hi2c->XferSize = hi2c->XferCount; - 8006afc: 68fb ldr r3, [r7, #12] - 8006afe: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006b00: b29a uxth r2, r3 - 8006b02: 68fb ldr r3, [r7, #12] - 8006b04: 851a strh r2, [r3, #40] ; 0x28 + 8007474: 68fb ldr r3, [r7, #12] + 8007476: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8007478: b29a uxth r2, r3 + 800747a: 68fb ldr r3, [r7, #12] + 800747c: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - 8006b06: 68fb ldr r3, [r7, #12] - 8006b08: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006b0a: b2da uxtb r2, r3 - 8006b0c: 8979 ldrh r1, [r7, #10] - 8006b0e: 2300 movs r3, #0 - 8006b10: 9300 str r3, [sp, #0] - 8006b12: f04f 7300 mov.w r3, #33554432 ; 0x2000000 - 8006b16: 68f8 ldr r0, [r7, #12] - 8006b18: f000 fabe bl 8007098 + 800747e: 68fb ldr r3, [r7, #12] + 8007480: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8007482: b2da uxtb r2, r3 + 8007484: 8979 ldrh r1, [r7, #10] + 8007486: 2300 movs r3, #0 + 8007488: 9300 str r3, [sp, #0] + 800748a: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 800748e: 68f8 ldr r0, [r7, #12] + 8007490: f000 fabe bl 8007a10 } do { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - 8006b1c: 697a ldr r2, [r7, #20] - 8006b1e: 6ab9 ldr r1, [r7, #40] ; 0x28 - 8006b20: 68f8 ldr r0, [r7, #12] - 8006b22: f000 f94e bl 8006dc2 - 8006b26: 4603 mov r3, r0 - 8006b28: 2b00 cmp r3, #0 - 8006b2a: d001 beq.n 8006b30 + 8007494: 697a ldr r2, [r7, #20] + 8007496: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8007498: 68f8 ldr r0, [r7, #12] + 800749a: f000 f94e bl 800773a + 800749e: 4603 mov r3, r0 + 80074a0: 2b00 cmp r3, #0 + 80074a2: d001 beq.n 80074a8 { return HAL_ERROR; - 8006b2c: 2301 movs r3, #1 - 8006b2e: e07b b.n 8006c28 + 80074a4: 2301 movs r3, #1 + 80074a6: e07b b.n 80075a0 } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; - 8006b30: 68fb ldr r3, [r7, #12] - 8006b32: 6a5b ldr r3, [r3, #36] ; 0x24 - 8006b34: 781a ldrb r2, [r3, #0] - 8006b36: 68fb ldr r3, [r7, #12] - 8006b38: 681b ldr r3, [r3, #0] - 8006b3a: 629a str r2, [r3, #40] ; 0x28 + 80074a8: 68fb ldr r3, [r7, #12] + 80074aa: 6a5b ldr r3, [r3, #36] ; 0x24 + 80074ac: 781a ldrb r2, [r3, #0] + 80074ae: 68fb ldr r3, [r7, #12] + 80074b0: 681b ldr r3, [r3, #0] + 80074b2: 629a str r2, [r3, #40] ; 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; - 8006b3c: 68fb ldr r3, [r7, #12] - 8006b3e: 6a5b ldr r3, [r3, #36] ; 0x24 - 8006b40: 1c5a adds r2, r3, #1 - 8006b42: 68fb ldr r3, [r7, #12] - 8006b44: 625a str r2, [r3, #36] ; 0x24 + 80074b4: 68fb ldr r3, [r7, #12] + 80074b6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80074b8: 1c5a adds r2, r3, #1 + 80074ba: 68fb ldr r3, [r7, #12] + 80074bc: 625a str r2, [r3, #36] ; 0x24 hi2c->XferCount--; - 8006b46: 68fb ldr r3, [r7, #12] - 8006b48: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006b4a: b29b uxth r3, r3 - 8006b4c: 3b01 subs r3, #1 - 8006b4e: b29a uxth r2, r3 - 8006b50: 68fb ldr r3, [r7, #12] - 8006b52: 855a strh r2, [r3, #42] ; 0x2a + 80074be: 68fb ldr r3, [r7, #12] + 80074c0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80074c2: b29b uxth r3, r3 + 80074c4: 3b01 subs r3, #1 + 80074c6: b29a uxth r2, r3 + 80074c8: 68fb ldr r3, [r7, #12] + 80074ca: 855a strh r2, [r3, #42] ; 0x2a hi2c->XferSize--; - 8006b54: 68fb ldr r3, [r7, #12] - 8006b56: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006b58: 3b01 subs r3, #1 - 8006b5a: b29a uxth r2, r3 - 8006b5c: 68fb ldr r3, [r7, #12] - 8006b5e: 851a strh r2, [r3, #40] ; 0x28 + 80074cc: 68fb ldr r3, [r7, #12] + 80074ce: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80074d0: 3b01 subs r3, #1 + 80074d2: b29a uxth r2, r3 + 80074d4: 68fb ldr r3, [r7, #12] + 80074d6: 851a strh r2, [r3, #40] ; 0x28 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - 8006b60: 68fb ldr r3, [r7, #12] - 8006b62: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006b64: b29b uxth r3, r3 - 8006b66: 2b00 cmp r3, #0 - 8006b68: d034 beq.n 8006bd4 - 8006b6a: 68fb ldr r3, [r7, #12] - 8006b6c: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006b6e: 2b00 cmp r3, #0 - 8006b70: d130 bne.n 8006bd4 + 80074d8: 68fb ldr r3, [r7, #12] + 80074da: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80074dc: b29b uxth r3, r3 + 80074de: 2b00 cmp r3, #0 + 80074e0: d034 beq.n 800754c + 80074e2: 68fb ldr r3, [r7, #12] + 80074e4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80074e6: 2b00 cmp r3, #0 + 80074e8: d130 bne.n 800754c { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - 8006b72: 697b ldr r3, [r7, #20] - 8006b74: 9300 str r3, [sp, #0] - 8006b76: 6abb ldr r3, [r7, #40] ; 0x28 - 8006b78: 2200 movs r2, #0 - 8006b7a: 2180 movs r1, #128 ; 0x80 - 8006b7c: 68f8 ldr r0, [r7, #12] - 8006b7e: f000 f8d1 bl 8006d24 - 8006b82: 4603 mov r3, r0 - 8006b84: 2b00 cmp r3, #0 - 8006b86: d001 beq.n 8006b8c + 80074ea: 697b ldr r3, [r7, #20] + 80074ec: 9300 str r3, [sp, #0] + 80074ee: 6abb ldr r3, [r7, #40] ; 0x28 + 80074f0: 2200 movs r2, #0 + 80074f2: 2180 movs r1, #128 ; 0x80 + 80074f4: 68f8 ldr r0, [r7, #12] + 80074f6: f000 f8d1 bl 800769c + 80074fa: 4603 mov r3, r0 + 80074fc: 2b00 cmp r3, #0 + 80074fe: d001 beq.n 8007504 { return HAL_ERROR; - 8006b88: 2301 movs r3, #1 - 8006b8a: e04d b.n 8006c28 + 8007500: 2301 movs r3, #1 + 8007502: e04d b.n 80075a0 } if (hi2c->XferCount > MAX_NBYTE_SIZE) - 8006b8c: 68fb ldr r3, [r7, #12] - 8006b8e: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006b90: b29b uxth r3, r3 - 8006b92: 2bff cmp r3, #255 ; 0xff - 8006b94: d90e bls.n 8006bb4 + 8007504: 68fb ldr r3, [r7, #12] + 8007506: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8007508: b29b uxth r3, r3 + 800750a: 2bff cmp r3, #255 ; 0xff + 800750c: d90e bls.n 800752c { hi2c->XferSize = MAX_NBYTE_SIZE; - 8006b96: 68fb ldr r3, [r7, #12] - 8006b98: 22ff movs r2, #255 ; 0xff - 8006b9a: 851a strh r2, [r3, #40] ; 0x28 + 800750e: 68fb ldr r3, [r7, #12] + 8007510: 22ff movs r2, #255 ; 0xff + 8007512: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - 8006b9c: 68fb ldr r3, [r7, #12] - 8006b9e: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006ba0: b2da uxtb r2, r3 - 8006ba2: 8979 ldrh r1, [r7, #10] - 8006ba4: 2300 movs r3, #0 - 8006ba6: 9300 str r3, [sp, #0] - 8006ba8: f04f 7380 mov.w r3, #16777216 ; 0x1000000 - 8006bac: 68f8 ldr r0, [r7, #12] - 8006bae: f000 fa73 bl 8007098 - 8006bb2: e00f b.n 8006bd4 + 8007514: 68fb ldr r3, [r7, #12] + 8007516: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8007518: b2da uxtb r2, r3 + 800751a: 8979 ldrh r1, [r7, #10] + 800751c: 2300 movs r3, #0 + 800751e: 9300 str r3, [sp, #0] + 8007520: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8007524: 68f8 ldr r0, [r7, #12] + 8007526: f000 fa73 bl 8007a10 + 800752a: e00f b.n 800754c I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - 8006bb4: 68fb ldr r3, [r7, #12] - 8006bb6: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006bb8: b29a uxth r2, r3 - 8006bba: 68fb ldr r3, [r7, #12] - 8006bbc: 851a strh r2, [r3, #40] ; 0x28 + 800752c: 68fb ldr r3, [r7, #12] + 800752e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8007530: b29a uxth r2, r3 + 8007532: 68fb ldr r3, [r7, #12] + 8007534: 851a strh r2, [r3, #40] ; 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - 8006bbe: 68fb ldr r3, [r7, #12] - 8006bc0: 8d1b ldrh r3, [r3, #40] ; 0x28 - 8006bc2: b2da uxtb r2, r3 - 8006bc4: 8979 ldrh r1, [r7, #10] - 8006bc6: 2300 movs r3, #0 - 8006bc8: 9300 str r3, [sp, #0] - 8006bca: f04f 7300 mov.w r3, #33554432 ; 0x2000000 - 8006bce: 68f8 ldr r0, [r7, #12] - 8006bd0: f000 fa62 bl 8007098 + 8007536: 68fb ldr r3, [r7, #12] + 8007538: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800753a: b2da uxtb r2, r3 + 800753c: 8979 ldrh r1, [r7, #10] + 800753e: 2300 movs r3, #0 + 8007540: 9300 str r3, [sp, #0] + 8007542: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8007546: 68f8 ldr r0, [r7, #12] + 8007548: f000 fa62 bl 8007a10 I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); - 8006bd4: 68fb ldr r3, [r7, #12] - 8006bd6: 8d5b ldrh r3, [r3, #42] ; 0x2a - 8006bd8: b29b uxth r3, r3 - 8006bda: 2b00 cmp r3, #0 - 8006bdc: d19e bne.n 8006b1c + 800754c: 68fb ldr r3, [r7, #12] + 800754e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8007550: b29b uxth r3, r3 + 8007552: 2b00 cmp r3, #0 + 8007554: d19e bne.n 8007494 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - 8006bde: 697a ldr r2, [r7, #20] - 8006be0: 6ab9 ldr r1, [r7, #40] ; 0x28 - 8006be2: 68f8 ldr r0, [r7, #12] - 8006be4: f000 f934 bl 8006e50 - 8006be8: 4603 mov r3, r0 - 8006bea: 2b00 cmp r3, #0 - 8006bec: d001 beq.n 8006bf2 + 8007556: 697a ldr r2, [r7, #20] + 8007558: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800755a: 68f8 ldr r0, [r7, #12] + 800755c: f000 f934 bl 80077c8 + 8007560: 4603 mov r3, r0 + 8007562: 2b00 cmp r3, #0 + 8007564: d001 beq.n 800756a { return HAL_ERROR; - 8006bee: 2301 movs r3, #1 - 8006bf0: e01a b.n 8006c28 + 8007566: 2301 movs r3, #1 + 8007568: e01a b.n 80075a0 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - 8006bf2: 68fb ldr r3, [r7, #12] - 8006bf4: 681b ldr r3, [r3, #0] - 8006bf6: 2220 movs r2, #32 - 8006bf8: 61da str r2, [r3, #28] + 800756a: 68fb ldr r3, [r7, #12] + 800756c: 681b ldr r3, [r3, #0] + 800756e: 2220 movs r2, #32 + 8007570: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - 8006bfa: 68fb ldr r3, [r7, #12] - 8006bfc: 681b ldr r3, [r3, #0] - 8006bfe: 6859 ldr r1, [r3, #4] - 8006c00: 68fb ldr r3, [r7, #12] - 8006c02: 681a ldr r2, [r3, #0] - 8006c04: 4b0a ldr r3, [pc, #40] ; (8006c30 ) - 8006c06: 400b ands r3, r1 - 8006c08: 6053 str r3, [r2, #4] + 8007572: 68fb ldr r3, [r7, #12] + 8007574: 681b ldr r3, [r3, #0] + 8007576: 6859 ldr r1, [r3, #4] + 8007578: 68fb ldr r3, [r7, #12] + 800757a: 681a ldr r2, [r3, #0] + 800757c: 4b0a ldr r3, [pc, #40] ; (80075a8 ) + 800757e: 400b ands r3, r1 + 8007580: 6053 str r3, [r2, #4] hi2c->State = HAL_I2C_STATE_READY; - 8006c0a: 68fb ldr r3, [r7, #12] - 8006c0c: 2220 movs r2, #32 - 8006c0e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007582: 68fb ldr r3, [r7, #12] + 8007584: 2220 movs r2, #32 + 8007586: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; - 8006c12: 68fb ldr r3, [r7, #12] - 8006c14: 2200 movs r2, #0 - 8006c16: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 800758a: 68fb ldr r3, [r7, #12] + 800758c: 2200 movs r2, #0 + 800758e: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8006c1a: 68fb ldr r3, [r7, #12] - 8006c1c: 2200 movs r2, #0 - 8006c1e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007592: 68fb ldr r3, [r7, #12] + 8007594: 2200 movs r2, #0 + 8007596: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; - 8006c22: 2300 movs r3, #0 - 8006c24: e000 b.n 8006c28 + 800759a: 2300 movs r3, #0 + 800759c: e000 b.n 80075a0 } else { return HAL_BUSY; - 8006c26: 2302 movs r3, #2 + 800759e: 2302 movs r3, #2 } } - 8006c28: 4618 mov r0, r3 - 8006c2a: 3718 adds r7, #24 - 8006c2c: 46bd mov sp, r7 - 8006c2e: bd80 pop {r7, pc} - 8006c30: fe00e800 .word 0xfe00e800 + 80075a0: 4618 mov r0, r3 + 80075a2: 3718 adds r7, #24 + 80075a4: 46bd mov sp, r7 + 80075a6: bd80 pop {r7, pc} + 80075a8: fe00e800 .word 0xfe00e800 -08006c34 : +080075ac : * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - 8006c34: b580 push {r7, lr} - 8006c36: b086 sub sp, #24 - 8006c38: af02 add r7, sp, #8 - 8006c3a: 60f8 str r0, [r7, #12] - 8006c3c: 4608 mov r0, r1 - 8006c3e: 4611 mov r1, r2 - 8006c40: 461a mov r2, r3 - 8006c42: 4603 mov r3, r0 - 8006c44: 817b strh r3, [r7, #10] - 8006c46: 460b mov r3, r1 - 8006c48: 813b strh r3, [r7, #8] - 8006c4a: 4613 mov r3, r2 - 8006c4c: 80fb strh r3, [r7, #6] + 80075ac: b580 push {r7, lr} + 80075ae: b086 sub sp, #24 + 80075b0: af02 add r7, sp, #8 + 80075b2: 60f8 str r0, [r7, #12] + 80075b4: 4608 mov r0, r1 + 80075b6: 4611 mov r1, r2 + 80075b8: 461a mov r2, r3 + 80075ba: 4603 mov r3, r0 + 80075bc: 817b strh r3, [r7, #10] + 80075be: 460b mov r3, r1 + 80075c0: 813b strh r3, [r7, #8] + 80075c2: 4613 mov r3, r2 + 80075c4: 80fb strh r3, [r7, #6] I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - 8006c4e: 88fb ldrh r3, [r7, #6] - 8006c50: b2da uxtb r2, r3 - 8006c52: 8979 ldrh r1, [r7, #10] - 8006c54: 4b20 ldr r3, [pc, #128] ; (8006cd8 ) - 8006c56: 9300 str r3, [sp, #0] - 8006c58: f04f 7380 mov.w r3, #16777216 ; 0x1000000 - 8006c5c: 68f8 ldr r0, [r7, #12] - 8006c5e: f000 fa1b bl 8007098 + 80075c6: 88fb ldrh r3, [r7, #6] + 80075c8: b2da uxtb r2, r3 + 80075ca: 8979 ldrh r1, [r7, #10] + 80075cc: 4b20 ldr r3, [pc, #128] ; (8007650 ) + 80075ce: 9300 str r3, [sp, #0] + 80075d0: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 80075d4: 68f8 ldr r0, [r7, #12] + 80075d6: f000 fa1b bl 8007a10 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - 8006c62: 69fa ldr r2, [r7, #28] - 8006c64: 69b9 ldr r1, [r7, #24] - 8006c66: 68f8 ldr r0, [r7, #12] - 8006c68: f000 f8ab bl 8006dc2 - 8006c6c: 4603 mov r3, r0 - 8006c6e: 2b00 cmp r3, #0 - 8006c70: d001 beq.n 8006c76 + 80075da: 69fa ldr r2, [r7, #28] + 80075dc: 69b9 ldr r1, [r7, #24] + 80075de: 68f8 ldr r0, [r7, #12] + 80075e0: f000 f8ab bl 800773a + 80075e4: 4603 mov r3, r0 + 80075e6: 2b00 cmp r3, #0 + 80075e8: d001 beq.n 80075ee { return HAL_ERROR; - 8006c72: 2301 movs r3, #1 - 8006c74: e02c b.n 8006cd0 + 80075ea: 2301 movs r3, #1 + 80075ec: e02c b.n 8007648 } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - 8006c76: 88fb ldrh r3, [r7, #6] - 8006c78: 2b01 cmp r3, #1 - 8006c7a: d105 bne.n 8006c88 + 80075ee: 88fb ldrh r3, [r7, #6] + 80075f0: 2b01 cmp r3, #1 + 80075f2: d105 bne.n 8007600 { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - 8006c7c: 893b ldrh r3, [r7, #8] - 8006c7e: b2da uxtb r2, r3 - 8006c80: 68fb ldr r3, [r7, #12] - 8006c82: 681b ldr r3, [r3, #0] - 8006c84: 629a str r2, [r3, #40] ; 0x28 - 8006c86: e015 b.n 8006cb4 + 80075f4: 893b ldrh r3, [r7, #8] + 80075f6: b2da uxtb r2, r3 + 80075f8: 68fb ldr r3, [r7, #12] + 80075fa: 681b ldr r3, [r3, #0] + 80075fc: 629a str r2, [r3, #40] ; 0x28 + 80075fe: e015 b.n 800762c } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - 8006c88: 893b ldrh r3, [r7, #8] - 8006c8a: 0a1b lsrs r3, r3, #8 - 8006c8c: b29b uxth r3, r3 - 8006c8e: b2da uxtb r2, r3 - 8006c90: 68fb ldr r3, [r7, #12] - 8006c92: 681b ldr r3, [r3, #0] - 8006c94: 629a str r2, [r3, #40] ; 0x28 + 8007600: 893b ldrh r3, [r7, #8] + 8007602: 0a1b lsrs r3, r3, #8 + 8007604: b29b uxth r3, r3 + 8007606: b2da uxtb r2, r3 + 8007608: 68fb ldr r3, [r7, #12] + 800760a: 681b ldr r3, [r3, #0] + 800760c: 629a str r2, [r3, #40] ; 0x28 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - 8006c96: 69fa ldr r2, [r7, #28] - 8006c98: 69b9 ldr r1, [r7, #24] - 8006c9a: 68f8 ldr r0, [r7, #12] - 8006c9c: f000 f891 bl 8006dc2 - 8006ca0: 4603 mov r3, r0 - 8006ca2: 2b00 cmp r3, #0 - 8006ca4: d001 beq.n 8006caa + 800760e: 69fa ldr r2, [r7, #28] + 8007610: 69b9 ldr r1, [r7, #24] + 8007612: 68f8 ldr r0, [r7, #12] + 8007614: f000 f891 bl 800773a + 8007618: 4603 mov r3, r0 + 800761a: 2b00 cmp r3, #0 + 800761c: d001 beq.n 8007622 { return HAL_ERROR; - 8006ca6: 2301 movs r3, #1 - 8006ca8: e012 b.n 8006cd0 + 800761e: 2301 movs r3, #1 + 8007620: e012 b.n 8007648 } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - 8006caa: 893b ldrh r3, [r7, #8] - 8006cac: b2da uxtb r2, r3 - 8006cae: 68fb ldr r3, [r7, #12] - 8006cb0: 681b ldr r3, [r3, #0] - 8006cb2: 629a str r2, [r3, #40] ; 0x28 + 8007622: 893b ldrh r3, [r7, #8] + 8007624: b2da uxtb r2, r3 + 8007626: 68fb ldr r3, [r7, #12] + 8007628: 681b ldr r3, [r3, #0] + 800762a: 629a str r2, [r3, #40] ; 0x28 } /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - 8006cb4: 69fb ldr r3, [r7, #28] - 8006cb6: 9300 str r3, [sp, #0] - 8006cb8: 69bb ldr r3, [r7, #24] - 8006cba: 2200 movs r2, #0 - 8006cbc: 2180 movs r1, #128 ; 0x80 - 8006cbe: 68f8 ldr r0, [r7, #12] - 8006cc0: f000 f830 bl 8006d24 - 8006cc4: 4603 mov r3, r0 - 8006cc6: 2b00 cmp r3, #0 - 8006cc8: d001 beq.n 8006cce + 800762c: 69fb ldr r3, [r7, #28] + 800762e: 9300 str r3, [sp, #0] + 8007630: 69bb ldr r3, [r7, #24] + 8007632: 2200 movs r2, #0 + 8007634: 2180 movs r1, #128 ; 0x80 + 8007636: 68f8 ldr r0, [r7, #12] + 8007638: f000 f830 bl 800769c + 800763c: 4603 mov r3, r0 + 800763e: 2b00 cmp r3, #0 + 8007640: d001 beq.n 8007646 { return HAL_ERROR; - 8006cca: 2301 movs r3, #1 - 8006ccc: e000 b.n 8006cd0 + 8007642: 2301 movs r3, #1 + 8007644: e000 b.n 8007648 } return HAL_OK; - 8006cce: 2300 movs r3, #0 + 8007646: 2300 movs r3, #0 } - 8006cd0: 4618 mov r0, r3 - 8006cd2: 3710 adds r7, #16 - 8006cd4: 46bd mov sp, r7 - 8006cd6: bd80 pop {r7, pc} - 8006cd8: 80002000 .word 0x80002000 + 8007648: 4618 mov r0, r3 + 800764a: 3710 adds r7, #16 + 800764c: 46bd mov sp, r7 + 800764e: bd80 pop {r7, pc} + 8007650: 80002000 .word 0x80002000 -08006cdc : +08007654 : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { - 8006cdc: b480 push {r7} - 8006cde: b083 sub sp, #12 - 8006ce0: af00 add r7, sp, #0 - 8006ce2: 6078 str r0, [r7, #4] + 8007654: b480 push {r7} + 8007656: b083 sub sp, #12 + 8007658: af00 add r7, sp, #0 + 800765a: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - 8006ce4: 687b ldr r3, [r7, #4] - 8006ce6: 681b ldr r3, [r3, #0] - 8006ce8: 699b ldr r3, [r3, #24] - 8006cea: f003 0302 and.w r3, r3, #2 - 8006cee: 2b02 cmp r3, #2 - 8006cf0: d103 bne.n 8006cfa + 800765c: 687b ldr r3, [r7, #4] + 800765e: 681b ldr r3, [r3, #0] + 8007660: 699b ldr r3, [r3, #24] + 8007662: f003 0302 and.w r3, r3, #2 + 8007666: 2b02 cmp r3, #2 + 8007668: d103 bne.n 8007672 { hi2c->Instance->TXDR = 0x00U; - 8006cf2: 687b ldr r3, [r7, #4] - 8006cf4: 681b ldr r3, [r3, #0] - 8006cf6: 2200 movs r2, #0 - 8006cf8: 629a str r2, [r3, #40] ; 0x28 + 800766a: 687b ldr r3, [r7, #4] + 800766c: 681b ldr r3, [r3, #0] + 800766e: 2200 movs r2, #0 + 8007670: 629a str r2, [r3, #40] ; 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - 8006cfa: 687b ldr r3, [r7, #4] - 8006cfc: 681b ldr r3, [r3, #0] - 8006cfe: 699b ldr r3, [r3, #24] - 8006d00: f003 0301 and.w r3, r3, #1 - 8006d04: 2b01 cmp r3, #1 - 8006d06: d007 beq.n 8006d18 + 8007672: 687b ldr r3, [r7, #4] + 8007674: 681b ldr r3, [r3, #0] + 8007676: 699b ldr r3, [r3, #24] + 8007678: f003 0301 and.w r3, r3, #1 + 800767c: 2b01 cmp r3, #1 + 800767e: d007 beq.n 8007690 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - 8006d08: 687b ldr r3, [r7, #4] - 8006d0a: 681b ldr r3, [r3, #0] - 8006d0c: 699a ldr r2, [r3, #24] - 8006d0e: 687b ldr r3, [r7, #4] - 8006d10: 681b ldr r3, [r3, #0] - 8006d12: f042 0201 orr.w r2, r2, #1 - 8006d16: 619a str r2, [r3, #24] - } -} - 8006d18: bf00 nop - 8006d1a: 370c adds r7, #12 - 8006d1c: 46bd mov sp, r7 - 8006d1e: f85d 7b04 ldr.w r7, [sp], #4 - 8006d22: 4770 bx lr - -08006d24 : + 8007680: 687b ldr r3, [r7, #4] + 8007682: 681b ldr r3, [r3, #0] + 8007684: 699a ldr r2, [r3, #24] + 8007686: 687b ldr r3, [r7, #4] + 8007688: 681b ldr r3, [r3, #0] + 800768a: f042 0201 orr.w r2, r2, #1 + 800768e: 619a str r2, [r3, #24] + } +} + 8007690: bf00 nop + 8007692: 370c adds r7, #12 + 8007694: 46bd mov sp, r7 + 8007696: f85d 7b04 ldr.w r7, [sp], #4 + 800769a: 4770 bx lr + +0800769c : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - 8006d24: b580 push {r7, lr} - 8006d26: b084 sub sp, #16 - 8006d28: af00 add r7, sp, #0 - 8006d2a: 60f8 str r0, [r7, #12] - 8006d2c: 60b9 str r1, [r7, #8] - 8006d2e: 603b str r3, [r7, #0] - 8006d30: 4613 mov r3, r2 - 8006d32: 71fb strb r3, [r7, #7] + 800769c: b580 push {r7, lr} + 800769e: b084 sub sp, #16 + 80076a0: af00 add r7, sp, #0 + 80076a2: 60f8 str r0, [r7, #12] + 80076a4: 60b9 str r1, [r7, #8] + 80076a6: 603b str r3, [r7, #0] + 80076a8: 4613 mov r3, r2 + 80076aa: 71fb strb r3, [r7, #7] while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - 8006d34: e031 b.n 8006d9a + 80076ac: e031 b.n 8007712 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8006d36: 683b ldr r3, [r7, #0] - 8006d38: f1b3 3fff cmp.w r3, #4294967295 - 8006d3c: d02d beq.n 8006d9a + 80076ae: 683b ldr r3, [r7, #0] + 80076b0: f1b3 3fff cmp.w r3, #4294967295 + 80076b4: d02d beq.n 8007712 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8006d3e: f7fd fc3d bl 80045bc - 8006d42: 4602 mov r2, r0 - 8006d44: 69bb ldr r3, [r7, #24] - 8006d46: 1ad3 subs r3, r2, r3 - 8006d48: 683a ldr r2, [r7, #0] - 8006d4a: 429a cmp r2, r3 - 8006d4c: d302 bcc.n 8006d54 - 8006d4e: 683b ldr r3, [r7, #0] - 8006d50: 2b00 cmp r3, #0 - 8006d52: d122 bne.n 8006d9a + 80076b6: f7fd fdcb bl 8005250 + 80076ba: 4602 mov r2, r0 + 80076bc: 69bb ldr r3, [r7, #24] + 80076be: 1ad3 subs r3, r2, r3 + 80076c0: 683a ldr r2, [r7, #0] + 80076c2: 429a cmp r2, r3 + 80076c4: d302 bcc.n 80076cc + 80076c6: 683b ldr r3, [r7, #0] + 80076c8: 2b00 cmp r3, #0 + 80076ca: d122 bne.n 8007712 { if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) - 8006d54: 68fb ldr r3, [r7, #12] - 8006d56: 681b ldr r3, [r3, #0] - 8006d58: 699a ldr r2, [r3, #24] - 8006d5a: 68bb ldr r3, [r7, #8] - 8006d5c: 4013 ands r3, r2 - 8006d5e: 68ba ldr r2, [r7, #8] - 8006d60: 429a cmp r2, r3 - 8006d62: bf0c ite eq - 8006d64: 2301 moveq r3, #1 - 8006d66: 2300 movne r3, #0 - 8006d68: b2db uxtb r3, r3 - 8006d6a: 461a mov r2, r3 - 8006d6c: 79fb ldrb r3, [r7, #7] - 8006d6e: 429a cmp r2, r3 - 8006d70: d113 bne.n 8006d9a + 80076cc: 68fb ldr r3, [r7, #12] + 80076ce: 681b ldr r3, [r3, #0] + 80076d0: 699a ldr r2, [r3, #24] + 80076d2: 68bb ldr r3, [r7, #8] + 80076d4: 4013 ands r3, r2 + 80076d6: 68ba ldr r2, [r7, #8] + 80076d8: 429a cmp r2, r3 + 80076da: bf0c ite eq + 80076dc: 2301 moveq r3, #1 + 80076de: 2300 movne r3, #0 + 80076e0: b2db uxtb r3, r3 + 80076e2: 461a mov r2, r3 + 80076e4: 79fb ldrb r3, [r7, #7] + 80076e6: 429a cmp r2, r3 + 80076e8: d113 bne.n 8007712 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - 8006d72: 68fb ldr r3, [r7, #12] - 8006d74: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006d76: f043 0220 orr.w r2, r3, #32 - 8006d7a: 68fb ldr r3, [r7, #12] - 8006d7c: 645a str r2, [r3, #68] ; 0x44 + 80076ea: 68fb ldr r3, [r7, #12] + 80076ec: 6c5b ldr r3, [r3, #68] ; 0x44 + 80076ee: f043 0220 orr.w r2, r3, #32 + 80076f2: 68fb ldr r3, [r7, #12] + 80076f4: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; - 8006d7e: 68fb ldr r3, [r7, #12] - 8006d80: 2220 movs r2, #32 - 8006d82: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 80076f6: 68fb ldr r3, [r7, #12] + 80076f8: 2220 movs r2, #32 + 80076fa: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; - 8006d86: 68fb ldr r3, [r7, #12] - 8006d88: 2200 movs r2, #0 - 8006d8a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 80076fe: 68fb ldr r3, [r7, #12] + 8007700: 2200 movs r2, #0 + 8007702: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8006d8e: 68fb ldr r3, [r7, #12] - 8006d90: 2200 movs r2, #0 - 8006d92: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007706: 68fb ldr r3, [r7, #12] + 8007708: 2200 movs r2, #0 + 800770a: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; - 8006d96: 2301 movs r3, #1 - 8006d98: e00f b.n 8006dba + 800770e: 2301 movs r3, #1 + 8007710: e00f b.n 8007732 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - 8006d9a: 68fb ldr r3, [r7, #12] - 8006d9c: 681b ldr r3, [r3, #0] - 8006d9e: 699a ldr r2, [r3, #24] - 8006da0: 68bb ldr r3, [r7, #8] - 8006da2: 4013 ands r3, r2 - 8006da4: 68ba ldr r2, [r7, #8] - 8006da6: 429a cmp r2, r3 - 8006da8: bf0c ite eq - 8006daa: 2301 moveq r3, #1 - 8006dac: 2300 movne r3, #0 - 8006dae: b2db uxtb r3, r3 - 8006db0: 461a mov r2, r3 - 8006db2: 79fb ldrb r3, [r7, #7] - 8006db4: 429a cmp r2, r3 - 8006db6: d0be beq.n 8006d36 + 8007712: 68fb ldr r3, [r7, #12] + 8007714: 681b ldr r3, [r3, #0] + 8007716: 699a ldr r2, [r3, #24] + 8007718: 68bb ldr r3, [r7, #8] + 800771a: 4013 ands r3, r2 + 800771c: 68ba ldr r2, [r7, #8] + 800771e: 429a cmp r2, r3 + 8007720: bf0c ite eq + 8007722: 2301 moveq r3, #1 + 8007724: 2300 movne r3, #0 + 8007726: b2db uxtb r3, r3 + 8007728: 461a mov r2, r3 + 800772a: 79fb ldrb r3, [r7, #7] + 800772c: 429a cmp r2, r3 + 800772e: d0be beq.n 80076ae } } } } return HAL_OK; - 8006db8: 2300 movs r3, #0 + 8007730: 2300 movs r3, #0 } - 8006dba: 4618 mov r0, r3 - 8006dbc: 3710 adds r7, #16 - 8006dbe: 46bd mov sp, r7 - 8006dc0: bd80 pop {r7, pc} + 8007732: 4618 mov r0, r3 + 8007734: 3710 adds r7, #16 + 8007736: 46bd mov sp, r7 + 8007738: bd80 pop {r7, pc} -08006dc2 : +0800773a : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - 8006dc2: b580 push {r7, lr} - 8006dc4: b084 sub sp, #16 - 8006dc6: af00 add r7, sp, #0 - 8006dc8: 60f8 str r0, [r7, #12] - 8006dca: 60b9 str r1, [r7, #8] - 8006dcc: 607a str r2, [r7, #4] + 800773a: b580 push {r7, lr} + 800773c: b084 sub sp, #16 + 800773e: af00 add r7, sp, #0 + 8007740: 60f8 str r0, [r7, #12] + 8007742: 60b9 str r1, [r7, #8] + 8007744: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - 8006dce: e033 b.n 8006e38 + 8007746: e033 b.n 80077b0 { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - 8006dd0: 687a ldr r2, [r7, #4] - 8006dd2: 68b9 ldr r1, [r7, #8] - 8006dd4: 68f8 ldr r0, [r7, #12] - 8006dd6: f000 f87f bl 8006ed8 - 8006dda: 4603 mov r3, r0 - 8006ddc: 2b00 cmp r3, #0 - 8006dde: d001 beq.n 8006de4 + 8007748: 687a ldr r2, [r7, #4] + 800774a: 68b9 ldr r1, [r7, #8] + 800774c: 68f8 ldr r0, [r7, #12] + 800774e: f000 f87f bl 8007850 + 8007752: 4603 mov r3, r0 + 8007754: 2b00 cmp r3, #0 + 8007756: d001 beq.n 800775c { return HAL_ERROR; - 8006de0: 2301 movs r3, #1 - 8006de2: e031 b.n 8006e48 + 8007758: 2301 movs r3, #1 + 800775a: e031 b.n 80077c0 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8006de4: 68bb ldr r3, [r7, #8] - 8006de6: f1b3 3fff cmp.w r3, #4294967295 - 8006dea: d025 beq.n 8006e38 + 800775c: 68bb ldr r3, [r7, #8] + 800775e: f1b3 3fff cmp.w r3, #4294967295 + 8007762: d025 beq.n 80077b0 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8006dec: f7fd fbe6 bl 80045bc - 8006df0: 4602 mov r2, r0 - 8006df2: 687b ldr r3, [r7, #4] - 8006df4: 1ad3 subs r3, r2, r3 - 8006df6: 68ba ldr r2, [r7, #8] - 8006df8: 429a cmp r2, r3 - 8006dfa: d302 bcc.n 8006e02 - 8006dfc: 68bb ldr r3, [r7, #8] - 8006dfe: 2b00 cmp r3, #0 - 8006e00: d11a bne.n 8006e38 + 8007764: f7fd fd74 bl 8005250 + 8007768: 4602 mov r2, r0 + 800776a: 687b ldr r3, [r7, #4] + 800776c: 1ad3 subs r3, r2, r3 + 800776e: 68ba ldr r2, [r7, #8] + 8007770: 429a cmp r2, r3 + 8007772: d302 bcc.n 800777a + 8007774: 68bb ldr r3, [r7, #8] + 8007776: 2b00 cmp r3, #0 + 8007778: d11a bne.n 80077b0 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) - 8006e02: 68fb ldr r3, [r7, #12] - 8006e04: 681b ldr r3, [r3, #0] - 8006e06: 699b ldr r3, [r3, #24] - 8006e08: f003 0302 and.w r3, r3, #2 - 8006e0c: 2b02 cmp r3, #2 - 8006e0e: d013 beq.n 8006e38 + 800777a: 68fb ldr r3, [r7, #12] + 800777c: 681b ldr r3, [r3, #0] + 800777e: 699b ldr r3, [r3, #24] + 8007780: f003 0302 and.w r3, r3, #2 + 8007784: 2b02 cmp r3, #2 + 8007786: d013 beq.n 80077b0 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - 8006e10: 68fb ldr r3, [r7, #12] - 8006e12: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006e14: f043 0220 orr.w r2, r3, #32 - 8006e18: 68fb ldr r3, [r7, #12] - 8006e1a: 645a str r2, [r3, #68] ; 0x44 + 8007788: 68fb ldr r3, [r7, #12] + 800778a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800778c: f043 0220 orr.w r2, r3, #32 + 8007790: 68fb ldr r3, [r7, #12] + 8007792: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; - 8006e1c: 68fb ldr r3, [r7, #12] - 8006e1e: 2220 movs r2, #32 - 8006e20: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007794: 68fb ldr r3, [r7, #12] + 8007796: 2220 movs r2, #32 + 8007798: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; - 8006e24: 68fb ldr r3, [r7, #12] - 8006e26: 2200 movs r2, #0 - 8006e28: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 800779c: 68fb ldr r3, [r7, #12] + 800779e: 2200 movs r2, #0 + 80077a0: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8006e2c: 68fb ldr r3, [r7, #12] - 8006e2e: 2200 movs r2, #0 - 8006e30: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 80077a4: 68fb ldr r3, [r7, #12] + 80077a6: 2200 movs r2, #0 + 80077a8: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; - 8006e34: 2301 movs r3, #1 - 8006e36: e007 b.n 8006e48 + 80077ac: 2301 movs r3, #1 + 80077ae: e007 b.n 80077c0 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - 8006e38: 68fb ldr r3, [r7, #12] - 8006e3a: 681b ldr r3, [r3, #0] - 8006e3c: 699b ldr r3, [r3, #24] - 8006e3e: f003 0302 and.w r3, r3, #2 - 8006e42: 2b02 cmp r3, #2 - 8006e44: d1c4 bne.n 8006dd0 + 80077b0: 68fb ldr r3, [r7, #12] + 80077b2: 681b ldr r3, [r3, #0] + 80077b4: 699b ldr r3, [r3, #24] + 80077b6: f003 0302 and.w r3, r3, #2 + 80077ba: 2b02 cmp r3, #2 + 80077bc: d1c4 bne.n 8007748 } } } } return HAL_OK; - 8006e46: 2300 movs r3, #0 + 80077be: 2300 movs r3, #0 } - 8006e48: 4618 mov r0, r3 - 8006e4a: 3710 adds r7, #16 - 8006e4c: 46bd mov sp, r7 - 8006e4e: bd80 pop {r7, pc} + 80077c0: 4618 mov r0, r3 + 80077c2: 3710 adds r7, #16 + 80077c4: 46bd mov sp, r7 + 80077c6: bd80 pop {r7, pc} -08006e50 : +080077c8 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - 8006e50: b580 push {r7, lr} - 8006e52: b084 sub sp, #16 - 8006e54: af00 add r7, sp, #0 - 8006e56: 60f8 str r0, [r7, #12] - 8006e58: 60b9 str r1, [r7, #8] - 8006e5a: 607a str r2, [r7, #4] + 80077c8: b580 push {r7, lr} + 80077ca: b084 sub sp, #16 + 80077cc: af00 add r7, sp, #0 + 80077ce: 60f8 str r0, [r7, #12] + 80077d0: 60b9 str r1, [r7, #8] + 80077d2: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - 8006e5c: e02f b.n 8006ebe + 80077d4: e02f b.n 8007836 { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - 8006e5e: 687a ldr r2, [r7, #4] - 8006e60: 68b9 ldr r1, [r7, #8] - 8006e62: 68f8 ldr r0, [r7, #12] - 8006e64: f000 f838 bl 8006ed8 - 8006e68: 4603 mov r3, r0 - 8006e6a: 2b00 cmp r3, #0 - 8006e6c: d001 beq.n 8006e72 + 80077d6: 687a ldr r2, [r7, #4] + 80077d8: 68b9 ldr r1, [r7, #8] + 80077da: 68f8 ldr r0, [r7, #12] + 80077dc: f000 f838 bl 8007850 + 80077e0: 4603 mov r3, r0 + 80077e2: 2b00 cmp r3, #0 + 80077e4: d001 beq.n 80077ea { return HAL_ERROR; - 8006e6e: 2301 movs r3, #1 - 8006e70: e02d b.n 8006ece + 80077e6: 2301 movs r3, #1 + 80077e8: e02d b.n 8007846 } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8006e72: f7fd fba3 bl 80045bc - 8006e76: 4602 mov r2, r0 - 8006e78: 687b ldr r3, [r7, #4] - 8006e7a: 1ad3 subs r3, r2, r3 - 8006e7c: 68ba ldr r2, [r7, #8] - 8006e7e: 429a cmp r2, r3 - 8006e80: d302 bcc.n 8006e88 - 8006e82: 68bb ldr r3, [r7, #8] - 8006e84: 2b00 cmp r3, #0 - 8006e86: d11a bne.n 8006ebe + 80077ea: f7fd fd31 bl 8005250 + 80077ee: 4602 mov r2, r0 + 80077f0: 687b ldr r3, [r7, #4] + 80077f2: 1ad3 subs r3, r2, r3 + 80077f4: 68ba ldr r2, [r7, #8] + 80077f6: 429a cmp r2, r3 + 80077f8: d302 bcc.n 8007800 + 80077fa: 68bb ldr r3, [r7, #8] + 80077fc: 2b00 cmp r3, #0 + 80077fe: d11a bne.n 8007836 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) - 8006e88: 68fb ldr r3, [r7, #12] - 8006e8a: 681b ldr r3, [r3, #0] - 8006e8c: 699b ldr r3, [r3, #24] - 8006e8e: f003 0320 and.w r3, r3, #32 - 8006e92: 2b20 cmp r3, #32 - 8006e94: d013 beq.n 8006ebe + 8007800: 68fb ldr r3, [r7, #12] + 8007802: 681b ldr r3, [r3, #0] + 8007804: 699b ldr r3, [r3, #24] + 8007806: f003 0320 and.w r3, r3, #32 + 800780a: 2b20 cmp r3, #32 + 800780c: d013 beq.n 8007836 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - 8006e96: 68fb ldr r3, [r7, #12] - 8006e98: 6c5b ldr r3, [r3, #68] ; 0x44 - 8006e9a: f043 0220 orr.w r2, r3, #32 - 8006e9e: 68fb ldr r3, [r7, #12] - 8006ea0: 645a str r2, [r3, #68] ; 0x44 + 800780e: 68fb ldr r3, [r7, #12] + 8007810: 6c5b ldr r3, [r3, #68] ; 0x44 + 8007812: f043 0220 orr.w r2, r3, #32 + 8007816: 68fb ldr r3, [r7, #12] + 8007818: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; - 8006ea2: 68fb ldr r3, [r7, #12] - 8006ea4: 2220 movs r2, #32 - 8006ea6: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 800781a: 68fb ldr r3, [r7, #12] + 800781c: 2220 movs r2, #32 + 800781e: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; - 8006eaa: 68fb ldr r3, [r7, #12] - 8006eac: 2200 movs r2, #0 - 8006eae: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 8007822: 68fb ldr r3, [r7, #12] + 8007824: 2200 movs r2, #0 + 8007826: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8006eb2: 68fb ldr r3, [r7, #12] - 8006eb4: 2200 movs r2, #0 - 8006eb6: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 800782a: 68fb ldr r3, [r7, #12] + 800782c: 2200 movs r2, #0 + 800782e: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_ERROR; - 8006eba: 2301 movs r3, #1 - 8006ebc: e007 b.n 8006ece + 8007832: 2301 movs r3, #1 + 8007834: e007 b.n 8007846 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - 8006ebe: 68fb ldr r3, [r7, #12] - 8006ec0: 681b ldr r3, [r3, #0] - 8006ec2: 699b ldr r3, [r3, #24] - 8006ec4: f003 0320 and.w r3, r3, #32 - 8006ec8: 2b20 cmp r3, #32 - 8006eca: d1c8 bne.n 8006e5e + 8007836: 68fb ldr r3, [r7, #12] + 8007838: 681b ldr r3, [r3, #0] + 800783a: 699b ldr r3, [r3, #24] + 800783c: f003 0320 and.w r3, r3, #32 + 8007840: 2b20 cmp r3, #32 + 8007842: d1c8 bne.n 80077d6 } } } return HAL_OK; - 8006ecc: 2300 movs r3, #0 + 8007844: 2300 movs r3, #0 } - 8006ece: 4618 mov r0, r3 - 8006ed0: 3710 adds r7, #16 - 8006ed2: 46bd mov sp, r7 - 8006ed4: bd80 pop {r7, pc} + 8007846: 4618 mov r0, r3 + 8007848: 3710 adds r7, #16 + 800784a: 46bd mov sp, r7 + 800784c: bd80 pop {r7, pc} ... -08006ed8 : +08007850 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - 8006ed8: b580 push {r7, lr} - 8006eda: b08a sub sp, #40 ; 0x28 - 8006edc: af00 add r7, sp, #0 - 8006ede: 60f8 str r0, [r7, #12] - 8006ee0: 60b9 str r1, [r7, #8] - 8006ee2: 607a str r2, [r7, #4] + 8007850: b580 push {r7, lr} + 8007852: b08a sub sp, #40 ; 0x28 + 8007854: af00 add r7, sp, #0 + 8007856: 60f8 str r0, [r7, #12] + 8007858: 60b9 str r1, [r7, #8] + 800785a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8006ee4: 2300 movs r3, #0 - 8006ee6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800785c: 2300 movs r3, #0 + 800785e: f887 3027 strb.w r3, [r7, #39] ; 0x27 uint32_t itflag = hi2c->Instance->ISR; - 8006eea: 68fb ldr r3, [r7, #12] - 8006eec: 681b ldr r3, [r3, #0] - 8006eee: 699b ldr r3, [r3, #24] - 8006ef0: 61bb str r3, [r7, #24] + 8007862: 68fb ldr r3, [r7, #12] + 8007864: 681b ldr r3, [r3, #0] + 8007866: 699b ldr r3, [r3, #24] + 8007868: 61bb str r3, [r7, #24] uint32_t error_code = 0; - 8006ef2: 2300 movs r3, #0 - 8006ef4: 623b str r3, [r7, #32] + 800786a: 2300 movs r3, #0 + 800786c: 623b str r3, [r7, #32] uint32_t tickstart = Tickstart; - 8006ef6: 687b ldr r3, [r7, #4] - 8006ef8: 61fb str r3, [r7, #28] + 800786e: 687b ldr r3, [r7, #4] + 8007870: 61fb str r3, [r7, #28] uint32_t tmp1; HAL_I2C_ModeTypeDef tmp2; if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) - 8006efa: 69bb ldr r3, [r7, #24] - 8006efc: f003 0310 and.w r3, r3, #16 - 8006f00: 2b00 cmp r3, #0 - 8006f02: d068 beq.n 8006fd6 + 8007872: 69bb ldr r3, [r7, #24] + 8007874: f003 0310 and.w r3, r3, #16 + 8007878: 2b00 cmp r3, #0 + 800787a: d068 beq.n 800794e { /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - 8006f04: 68fb ldr r3, [r7, #12] - 8006f06: 681b ldr r3, [r3, #0] - 8006f08: 2210 movs r2, #16 - 8006f0a: 61da str r2, [r3, #28] + 800787c: 68fb ldr r3, [r7, #12] + 800787e: 681b ldr r3, [r3, #0] + 8007880: 2210 movs r2, #16 + 8007882: 61da str r2, [r3, #28] /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) - 8006f0c: e049 b.n 8006fa2 + 8007884: e049 b.n 800791a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8006f0e: 68bb ldr r3, [r7, #8] - 8006f10: f1b3 3fff cmp.w r3, #4294967295 - 8006f14: d045 beq.n 8006fa2 + 8007886: 68bb ldr r3, [r7, #8] + 8007888: f1b3 3fff cmp.w r3, #4294967295 + 800788c: d045 beq.n 800791a { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - 8006f16: f7fd fb51 bl 80045bc - 8006f1a: 4602 mov r2, r0 - 8006f1c: 69fb ldr r3, [r7, #28] - 8006f1e: 1ad3 subs r3, r2, r3 - 8006f20: 68ba ldr r2, [r7, #8] - 8006f22: 429a cmp r2, r3 - 8006f24: d302 bcc.n 8006f2c - 8006f26: 68bb ldr r3, [r7, #8] - 8006f28: 2b00 cmp r3, #0 - 8006f2a: d13a bne.n 8006fa2 + 800788e: f7fd fcdf bl 8005250 + 8007892: 4602 mov r2, r0 + 8007894: 69fb ldr r3, [r7, #28] + 8007896: 1ad3 subs r3, r2, r3 + 8007898: 68ba ldr r2, [r7, #8] + 800789a: 429a cmp r2, r3 + 800789c: d302 bcc.n 80078a4 + 800789e: 68bb ldr r3, [r7, #8] + 80078a0: 2b00 cmp r3, #0 + 80078a2: d13a bne.n 800791a { tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); - 8006f2c: 68fb ldr r3, [r7, #12] - 8006f2e: 681b ldr r3, [r3, #0] - 8006f30: 685b ldr r3, [r3, #4] - 8006f32: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8006f36: 617b str r3, [r7, #20] + 80078a4: 68fb ldr r3, [r7, #12] + 80078a6: 681b ldr r3, [r3, #0] + 80078a8: 685b ldr r3, [r3, #4] + 80078aa: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80078ae: 617b str r3, [r7, #20] tmp2 = hi2c->Mode; - 8006f38: 68fb ldr r3, [r7, #12] - 8006f3a: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 - 8006f3e: 74fb strb r3, [r7, #19] + 80078b0: 68fb ldr r3, [r7, #12] + 80078b2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 80078b6: 74fb strb r3, [r7, #19] /* In case of I2C still busy, try to regenerate a STOP manually */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ - 8006f40: 68fb ldr r3, [r7, #12] - 8006f42: 681b ldr r3, [r3, #0] - 8006f44: 699b ldr r3, [r3, #24] - 8006f46: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8006f4a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8006f4e: d121 bne.n 8006f94 - 8006f50: 697b ldr r3, [r7, #20] - 8006f52: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 8006f56: d01d beq.n 8006f94 + 80078b8: 68fb ldr r3, [r7, #12] + 80078ba: 681b ldr r3, [r3, #0] + 80078bc: 699b ldr r3, [r3, #24] + 80078be: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 80078c2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 80078c6: d121 bne.n 800790c + 80078c8: 697b ldr r3, [r7, #20] + 80078ca: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80078ce: d01d beq.n 800790c (tmp1 != I2C_CR2_STOP) && \ - 8006f58: 7cfb ldrb r3, [r7, #19] - 8006f5a: 2b20 cmp r3, #32 - 8006f5c: d01a beq.n 8006f94 + 80078d0: 7cfb ldrb r3, [r7, #19] + 80078d2: 2b20 cmp r3, #32 + 80078d4: d01a beq.n 800790c (tmp2 != HAL_I2C_MODE_SLAVE)) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - 8006f5e: 68fb ldr r3, [r7, #12] - 8006f60: 681b ldr r3, [r3, #0] - 8006f62: 685a ldr r2, [r3, #4] - 8006f64: 68fb ldr r3, [r7, #12] - 8006f66: 681b ldr r3, [r3, #0] - 8006f68: f442 4280 orr.w r2, r2, #16384 ; 0x4000 - 8006f6c: 605a str r2, [r3, #4] + 80078d6: 68fb ldr r3, [r7, #12] + 80078d8: 681b ldr r3, [r3, #0] + 80078da: 685a ldr r2, [r3, #4] + 80078dc: 68fb ldr r3, [r7, #12] + 80078de: 681b ldr r3, [r3, #0] + 80078e0: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 80078e4: 605a str r2, [r3, #4] /* Update Tick with new reference */ tickstart = HAL_GetTick(); - 8006f6e: f7fd fb25 bl 80045bc - 8006f72: 61f8 str r0, [r7, #28] + 80078e6: f7fd fcb3 bl 8005250 + 80078ea: 61f8 str r0, [r7, #28] } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - 8006f74: e00e b.n 8006f94 + 80078ec: e00e b.n 800790c { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) - 8006f76: f7fd fb21 bl 80045bc - 8006f7a: 4602 mov r2, r0 - 8006f7c: 69fb ldr r3, [r7, #28] - 8006f7e: 1ad3 subs r3, r2, r3 - 8006f80: 2b19 cmp r3, #25 - 8006f82: d907 bls.n 8006f94 + 80078ee: f7fd fcaf bl 8005250 + 80078f2: 4602 mov r2, r0 + 80078f4: 69fb ldr r3, [r7, #28] + 80078f6: 1ad3 subs r3, r2, r3 + 80078f8: 2b19 cmp r3, #25 + 80078fa: d907 bls.n 800790c { error_code |= HAL_I2C_ERROR_TIMEOUT; - 8006f84: 6a3b ldr r3, [r7, #32] - 8006f86: f043 0320 orr.w r3, r3, #32 - 8006f8a: 623b str r3, [r7, #32] + 80078fc: 6a3b ldr r3, [r7, #32] + 80078fe: f043 0320 orr.w r3, r3, #32 + 8007902: 623b str r3, [r7, #32] status = HAL_ERROR; - 8006f8c: 2301 movs r3, #1 - 8006f8e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8007904: 2301 movs r3, #1 + 8007906: f887 3027 strb.w r3, [r7, #39] ; 0x27 break; - 8006f92: e006 b.n 8006fa2 + 800790a: e006 b.n 800791a while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - 8006f94: 68fb ldr r3, [r7, #12] - 8006f96: 681b ldr r3, [r3, #0] - 8006f98: 699b ldr r3, [r3, #24] - 8006f9a: f003 0320 and.w r3, r3, #32 - 8006f9e: 2b20 cmp r3, #32 - 8006fa0: d1e9 bne.n 8006f76 + 800790c: 68fb ldr r3, [r7, #12] + 800790e: 681b ldr r3, [r3, #0] + 8007910: 699b ldr r3, [r3, #24] + 8007912: f003 0320 and.w r3, r3, #32 + 8007916: 2b20 cmp r3, #32 + 8007918: d1e9 bne.n 80078ee while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) - 8006fa2: 68fb ldr r3, [r7, #12] - 8006fa4: 681b ldr r3, [r3, #0] - 8006fa6: 699b ldr r3, [r3, #24] - 8006fa8: f003 0320 and.w r3, r3, #32 - 8006fac: 2b20 cmp r3, #32 - 8006fae: d003 beq.n 8006fb8 - 8006fb0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8006fb4: 2b00 cmp r3, #0 - 8006fb6: d0aa beq.n 8006f0e + 800791a: 68fb ldr r3, [r7, #12] + 800791c: 681b ldr r3, [r3, #0] + 800791e: 699b ldr r3, [r3, #24] + 8007920: f003 0320 and.w r3, r3, #32 + 8007924: 2b20 cmp r3, #32 + 8007926: d003 beq.n 8007930 + 8007928: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800792c: 2b00 cmp r3, #0 + 800792e: d0aa beq.n 8007886 } } } /* In case STOP Flag is detected, clear it */ if (status == HAL_OK) - 8006fb8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8006fbc: 2b00 cmp r3, #0 - 8006fbe: d103 bne.n 8006fc8 + 8007930: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8007934: 2b00 cmp r3, #0 + 8007936: d103 bne.n 8007940 { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - 8006fc0: 68fb ldr r3, [r7, #12] - 8006fc2: 681b ldr r3, [r3, #0] - 8006fc4: 2220 movs r2, #32 - 8006fc6: 61da str r2, [r3, #28] + 8007938: 68fb ldr r3, [r7, #12] + 800793a: 681b ldr r3, [r3, #0] + 800793c: 2220 movs r2, #32 + 800793e: 61da str r2, [r3, #28] } error_code |= HAL_I2C_ERROR_AF; - 8006fc8: 6a3b ldr r3, [r7, #32] - 8006fca: f043 0304 orr.w r3, r3, #4 - 8006fce: 623b str r3, [r7, #32] + 8007940: 6a3b ldr r3, [r7, #32] + 8007942: f043 0304 orr.w r3, r3, #4 + 8007946: 623b str r3, [r7, #32] status = HAL_ERROR; - 8006fd0: 2301 movs r3, #1 - 8006fd2: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8007948: 2301 movs r3, #1 + 800794a: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* Refresh Content of Status register */ itflag = hi2c->Instance->ISR; - 8006fd6: 68fb ldr r3, [r7, #12] - 8006fd8: 681b ldr r3, [r3, #0] - 8006fda: 699b ldr r3, [r3, #24] - 8006fdc: 61bb str r3, [r7, #24] + 800794e: 68fb ldr r3, [r7, #12] + 8007950: 681b ldr r3, [r3, #0] + 8007952: 699b ldr r3, [r3, #24] + 8007954: 61bb str r3, [r7, #24] /* Then verify if an additional errors occurs */ /* Check if a Bus error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) - 8006fde: 69bb ldr r3, [r7, #24] - 8006fe0: f403 7380 and.w r3, r3, #256 ; 0x100 - 8006fe4: 2b00 cmp r3, #0 - 8006fe6: d00b beq.n 8007000 + 8007956: 69bb ldr r3, [r7, #24] + 8007958: f403 7380 and.w r3, r3, #256 ; 0x100 + 800795c: 2b00 cmp r3, #0 + 800795e: d00b beq.n 8007978 { error_code |= HAL_I2C_ERROR_BERR; - 8006fe8: 6a3b ldr r3, [r7, #32] - 8006fea: f043 0301 orr.w r3, r3, #1 - 8006fee: 623b str r3, [r7, #32] + 8007960: 6a3b ldr r3, [r7, #32] + 8007962: f043 0301 orr.w r3, r3, #1 + 8007966: 623b str r3, [r7, #32] /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - 8006ff0: 68fb ldr r3, [r7, #12] - 8006ff2: 681b ldr r3, [r3, #0] - 8006ff4: f44f 7280 mov.w r2, #256 ; 0x100 - 8006ff8: 61da str r2, [r3, #28] + 8007968: 68fb ldr r3, [r7, #12] + 800796a: 681b ldr r3, [r3, #0] + 800796c: f44f 7280 mov.w r2, #256 ; 0x100 + 8007970: 61da str r2, [r3, #28] status = HAL_ERROR; - 8006ffa: 2301 movs r3, #1 - 8006ffc: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8007972: 2301 movs r3, #1 + 8007974: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* Check if an Over-Run/Under-Run error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) - 8007000: 69bb ldr r3, [r7, #24] - 8007002: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8007006: 2b00 cmp r3, #0 - 8007008: d00b beq.n 8007022 + 8007978: 69bb ldr r3, [r7, #24] + 800797a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800797e: 2b00 cmp r3, #0 + 8007980: d00b beq.n 800799a { error_code |= HAL_I2C_ERROR_OVR; - 800700a: 6a3b ldr r3, [r7, #32] - 800700c: f043 0308 orr.w r3, r3, #8 - 8007010: 623b str r3, [r7, #32] + 8007982: 6a3b ldr r3, [r7, #32] + 8007984: f043 0308 orr.w r3, r3, #8 + 8007988: 623b str r3, [r7, #32] /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - 8007012: 68fb ldr r3, [r7, #12] - 8007014: 681b ldr r3, [r3, #0] - 8007016: f44f 6280 mov.w r2, #1024 ; 0x400 - 800701a: 61da str r2, [r3, #28] + 800798a: 68fb ldr r3, [r7, #12] + 800798c: 681b ldr r3, [r3, #0] + 800798e: f44f 6280 mov.w r2, #1024 ; 0x400 + 8007992: 61da str r2, [r3, #28] status = HAL_ERROR; - 800701c: 2301 movs r3, #1 - 800701e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8007994: 2301 movs r3, #1 + 8007996: f887 3027 strb.w r3, [r7, #39] ; 0x27 } /* Check if an Arbitration Loss error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) - 8007022: 69bb ldr r3, [r7, #24] - 8007024: f403 7300 and.w r3, r3, #512 ; 0x200 - 8007028: 2b00 cmp r3, #0 - 800702a: d00b beq.n 8007044 + 800799a: 69bb ldr r3, [r7, #24] + 800799c: f403 7300 and.w r3, r3, #512 ; 0x200 + 80079a0: 2b00 cmp r3, #0 + 80079a2: d00b beq.n 80079bc { error_code |= HAL_I2C_ERROR_ARLO; - 800702c: 6a3b ldr r3, [r7, #32] - 800702e: f043 0302 orr.w r3, r3, #2 - 8007032: 623b str r3, [r7, #32] + 80079a4: 6a3b ldr r3, [r7, #32] + 80079a6: f043 0302 orr.w r3, r3, #2 + 80079aa: 623b str r3, [r7, #32] /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - 8007034: 68fb ldr r3, [r7, #12] - 8007036: 681b ldr r3, [r3, #0] - 8007038: f44f 7200 mov.w r2, #512 ; 0x200 - 800703c: 61da str r2, [r3, #28] + 80079ac: 68fb ldr r3, [r7, #12] + 80079ae: 681b ldr r3, [r3, #0] + 80079b0: f44f 7200 mov.w r2, #512 ; 0x200 + 80079b4: 61da str r2, [r3, #28] status = HAL_ERROR; - 800703e: 2301 movs r3, #1 - 8007040: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 80079b6: 2301 movs r3, #1 + 80079b8: f887 3027 strb.w r3, [r7, #39] ; 0x27 } if (status != HAL_OK) - 8007044: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8007048: 2b00 cmp r3, #0 - 800704a: d01c beq.n 8007086 + 80079bc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80079c0: 2b00 cmp r3, #0 + 80079c2: d01c beq.n 80079fe { /* Flush TX register */ I2C_Flush_TXDR(hi2c); - 800704c: 68f8 ldr r0, [r7, #12] - 800704e: f7ff fe45 bl 8006cdc + 80079c4: 68f8 ldr r0, [r7, #12] + 80079c6: f7ff fe45 bl 8007654 /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - 8007052: 68fb ldr r3, [r7, #12] - 8007054: 681b ldr r3, [r3, #0] - 8007056: 6859 ldr r1, [r3, #4] - 8007058: 68fb ldr r3, [r7, #12] - 800705a: 681a ldr r2, [r3, #0] - 800705c: 4b0d ldr r3, [pc, #52] ; (8007094 ) - 800705e: 400b ands r3, r1 - 8007060: 6053 str r3, [r2, #4] + 80079ca: 68fb ldr r3, [r7, #12] + 80079cc: 681b ldr r3, [r3, #0] + 80079ce: 6859 ldr r1, [r3, #4] + 80079d0: 68fb ldr r3, [r7, #12] + 80079d2: 681a ldr r2, [r3, #0] + 80079d4: 4b0d ldr r3, [pc, #52] ; (8007a0c ) + 80079d6: 400b ands r3, r1 + 80079d8: 6053 str r3, [r2, #4] hi2c->ErrorCode |= error_code; - 8007062: 68fb ldr r3, [r7, #12] - 8007064: 6c5a ldr r2, [r3, #68] ; 0x44 - 8007066: 6a3b ldr r3, [r7, #32] - 8007068: 431a orrs r2, r3 - 800706a: 68fb ldr r3, [r7, #12] - 800706c: 645a str r2, [r3, #68] ; 0x44 + 80079da: 68fb ldr r3, [r7, #12] + 80079dc: 6c5a ldr r2, [r3, #68] ; 0x44 + 80079de: 6a3b ldr r3, [r7, #32] + 80079e0: 431a orrs r2, r3 + 80079e2: 68fb ldr r3, [r7, #12] + 80079e4: 645a str r2, [r3, #68] ; 0x44 hi2c->State = HAL_I2C_STATE_READY; - 800706e: 68fb ldr r3, [r7, #12] - 8007070: 2220 movs r2, #32 - 8007072: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 80079e6: 68fb ldr r3, [r7, #12] + 80079e8: 2220 movs r2, #32 + 80079ea: f883 2041 strb.w r2, [r3, #65] ; 0x41 hi2c->Mode = HAL_I2C_MODE_NONE; - 8007076: 68fb ldr r3, [r7, #12] - 8007078: 2200 movs r2, #0 - 800707a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 80079ee: 68fb ldr r3, [r7, #12] + 80079f0: 2200 movs r2, #0 + 80079f2: f883 2042 strb.w r2, [r3, #66] ; 0x42 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 800707e: 68fb ldr r3, [r7, #12] - 8007080: 2200 movs r2, #0 - 8007082: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 80079f6: 68fb ldr r3, [r7, #12] + 80079f8: 2200 movs r2, #0 + 80079fa: f883 2040 strb.w r2, [r3, #64] ; 0x40 } return status; - 8007086: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80079fe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } - 800708a: 4618 mov r0, r3 - 800708c: 3728 adds r7, #40 ; 0x28 - 800708e: 46bd mov sp, r7 - 8007090: bd80 pop {r7, pc} - 8007092: bf00 nop - 8007094: fe00e800 .word 0xfe00e800 + 8007a02: 4618 mov r0, r3 + 8007a04: 3728 adds r7, #40 ; 0x28 + 8007a06: 46bd mov sp, r7 + 8007a08: bd80 pop {r7, pc} + 8007a0a: bf00 nop + 8007a0c: fe00e800 .word 0xfe00e800 -08007098 : +08007a10 : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - 8007098: b480 push {r7} - 800709a: b087 sub sp, #28 - 800709c: af00 add r7, sp, #0 - 800709e: 60f8 str r0, [r7, #12] - 80070a0: 607b str r3, [r7, #4] - 80070a2: 460b mov r3, r1 - 80070a4: 817b strh r3, [r7, #10] - 80070a6: 4613 mov r3, r2 - 80070a8: 727b strb r3, [r7, #9] + 8007a10: b480 push {r7} + 8007a12: b087 sub sp, #28 + 8007a14: af00 add r7, sp, #0 + 8007a16: 60f8 str r0, [r7, #12] + 8007a18: 607b str r3, [r7, #4] + 8007a1a: 460b mov r3, r1 + 8007a1c: 817b strh r3, [r7, #10] + 8007a1e: 4613 mov r3, r2 + 8007a20: 727b strb r3, [r7, #9] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - 80070aa: 897b ldrh r3, [r7, #10] - 80070ac: f3c3 0209 ubfx r2, r3, #0, #10 + 8007a22: 897b ldrh r3, [r7, #10] + 8007a24: f3c3 0209 ubfx r2, r3, #0, #10 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - 80070b0: 7a7b ldrb r3, [r7, #9] - 80070b2: 041b lsls r3, r3, #16 - 80070b4: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8007a28: 7a7b ldrb r3, [r7, #9] + 8007a2a: 041b lsls r3, r3, #16 + 8007a2c: f403 037f and.w r3, r3, #16711680 ; 0xff0000 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - 80070b8: 431a orrs r2, r3 + 8007a30: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - 80070ba: 687b ldr r3, [r7, #4] - 80070bc: 431a orrs r2, r3 + 8007a32: 687b ldr r3, [r7, #4] + 8007a34: 431a orrs r2, r3 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - 80070be: 6a3b ldr r3, [r7, #32] - 80070c0: 4313 orrs r3, r2 - 80070c2: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 - 80070c6: 617b str r3, [r7, #20] + 8007a36: 6a3b ldr r3, [r7, #32] + 8007a38: 4313 orrs r3, r2 + 8007a3a: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8007a3e: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ - 80070c8: 68fb ldr r3, [r7, #12] - 80070ca: 681b ldr r3, [r3, #0] - 80070cc: 685a ldr r2, [r3, #4] - 80070ce: 6a3b ldr r3, [r7, #32] - 80070d0: 0d5b lsrs r3, r3, #21 - 80070d2: f403 6180 and.w r1, r3, #1024 ; 0x400 - 80070d6: 4b08 ldr r3, [pc, #32] ; (80070f8 ) - 80070d8: 430b orrs r3, r1 - 80070da: 43db mvns r3, r3 - 80070dc: ea02 0103 and.w r1, r2, r3 - 80070e0: 68fb ldr r3, [r7, #12] - 80070e2: 681b ldr r3, [r3, #0] - 80070e4: 697a ldr r2, [r7, #20] - 80070e6: 430a orrs r2, r1 - 80070e8: 605a str r2, [r3, #4] + 8007a40: 68fb ldr r3, [r7, #12] + 8007a42: 681b ldr r3, [r3, #0] + 8007a44: 685a ldr r2, [r3, #4] + 8007a46: 6a3b ldr r3, [r7, #32] + 8007a48: 0d5b lsrs r3, r3, #21 + 8007a4a: f403 6180 and.w r1, r3, #1024 ; 0x400 + 8007a4e: 4b08 ldr r3, [pc, #32] ; (8007a70 ) + 8007a50: 430b orrs r3, r1 + 8007a52: 43db mvns r3, r3 + 8007a54: ea02 0103 and.w r1, r2, r3 + 8007a58: 68fb ldr r3, [r7, #12] + 8007a5a: 681b ldr r3, [r3, #0] + 8007a5c: 697a ldr r2, [r7, #20] + 8007a5e: 430a orrs r2, r1 + 8007a60: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } - 80070ea: bf00 nop - 80070ec: 371c adds r7, #28 - 80070ee: 46bd mov sp, r7 - 80070f0: f85d 7b04 ldr.w r7, [sp], #4 - 80070f4: 4770 bx lr - 80070f6: bf00 nop - 80070f8: 03ff63ff .word 0x03ff63ff + 8007a62: bf00 nop + 8007a64: 371c adds r7, #28 + 8007a66: 46bd mov sp, r7 + 8007a68: f85d 7b04 ldr.w r7, [sp], #4 + 8007a6c: 4770 bx lr + 8007a6e: bf00 nop + 8007a70: 03ff63ff .word 0x03ff63ff -080070fc : +08007a74 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { - 80070fc: b480 push {r7} - 80070fe: b083 sub sp, #12 - 8007100: af00 add r7, sp, #0 - 8007102: 6078 str r0, [r7, #4] - 8007104: 6039 str r1, [r7, #0] + 8007a74: b480 push {r7} + 8007a76: b083 sub sp, #12 + 8007a78: af00 add r7, sp, #0 + 8007a7a: 6078 str r0, [r7, #4] + 8007a7c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) - 8007106: 687b ldr r3, [r7, #4] - 8007108: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 - 800710c: b2db uxtb r3, r3 - 800710e: 2b20 cmp r3, #32 - 8007110: d138 bne.n 8007184 + 8007a7e: 687b ldr r3, [r7, #4] + 8007a80: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8007a84: b2db uxtb r3, r3 + 8007a86: 2b20 cmp r3, #32 + 8007a88: d138 bne.n 8007afc { /* Process Locked */ __HAL_LOCK(hi2c); - 8007112: 687b ldr r3, [r7, #4] - 8007114: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 - 8007118: 2b01 cmp r3, #1 - 800711a: d101 bne.n 8007120 - 800711c: 2302 movs r3, #2 - 800711e: e032 b.n 8007186 - 8007120: 687b ldr r3, [r7, #4] - 8007122: 2201 movs r2, #1 - 8007124: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007a8a: 687b ldr r3, [r7, #4] + 8007a8c: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8007a90: 2b01 cmp r3, #1 + 8007a92: d101 bne.n 8007a98 + 8007a94: 2302 movs r3, #2 + 8007a96: e032 b.n 8007afe + 8007a98: 687b ldr r3, [r7, #4] + 8007a9a: 2201 movs r2, #1 + 8007a9c: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; - 8007128: 687b ldr r3, [r7, #4] - 800712a: 2224 movs r2, #36 ; 0x24 - 800712c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007aa0: 687b ldr r3, [r7, #4] + 8007aa2: 2224 movs r2, #36 ; 0x24 + 8007aa4: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - 8007130: 687b ldr r3, [r7, #4] - 8007132: 681b ldr r3, [r3, #0] - 8007134: 681a ldr r2, [r3, #0] - 8007136: 687b ldr r3, [r7, #4] - 8007138: 681b ldr r3, [r3, #0] - 800713a: f022 0201 bic.w r2, r2, #1 - 800713e: 601a str r2, [r3, #0] + 8007aa8: 687b ldr r3, [r7, #4] + 8007aaa: 681b ldr r3, [r3, #0] + 8007aac: 681a ldr r2, [r3, #0] + 8007aae: 687b ldr r3, [r7, #4] + 8007ab0: 681b ldr r3, [r3, #0] + 8007ab2: f022 0201 bic.w r2, r2, #1 + 8007ab6: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - 8007140: 687b ldr r3, [r7, #4] - 8007142: 681b ldr r3, [r3, #0] - 8007144: 681a ldr r2, [r3, #0] - 8007146: 687b ldr r3, [r7, #4] - 8007148: 681b ldr r3, [r3, #0] - 800714a: f422 5280 bic.w r2, r2, #4096 ; 0x1000 - 800714e: 601a str r2, [r3, #0] + 8007ab8: 687b ldr r3, [r7, #4] + 8007aba: 681b ldr r3, [r3, #0] + 8007abc: 681a ldr r2, [r3, #0] + 8007abe: 687b ldr r3, [r7, #4] + 8007ac0: 681b ldr r3, [r3, #0] + 8007ac2: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8007ac6: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; - 8007150: 687b ldr r3, [r7, #4] - 8007152: 681b ldr r3, [r3, #0] - 8007154: 6819 ldr r1, [r3, #0] - 8007156: 687b ldr r3, [r7, #4] - 8007158: 681b ldr r3, [r3, #0] - 800715a: 683a ldr r2, [r7, #0] - 800715c: 430a orrs r2, r1 - 800715e: 601a str r2, [r3, #0] + 8007ac8: 687b ldr r3, [r7, #4] + 8007aca: 681b ldr r3, [r3, #0] + 8007acc: 6819 ldr r1, [r3, #0] + 8007ace: 687b ldr r3, [r7, #4] + 8007ad0: 681b ldr r3, [r3, #0] + 8007ad2: 683a ldr r2, [r7, #0] + 8007ad4: 430a orrs r2, r1 + 8007ad6: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); - 8007160: 687b ldr r3, [r7, #4] - 8007162: 681b ldr r3, [r3, #0] - 8007164: 681a ldr r2, [r3, #0] - 8007166: 687b ldr r3, [r7, #4] - 8007168: 681b ldr r3, [r3, #0] - 800716a: f042 0201 orr.w r2, r2, #1 - 800716e: 601a str r2, [r3, #0] + 8007ad8: 687b ldr r3, [r7, #4] + 8007ada: 681b ldr r3, [r3, #0] + 8007adc: 681a ldr r2, [r3, #0] + 8007ade: 687b ldr r3, [r7, #4] + 8007ae0: 681b ldr r3, [r3, #0] + 8007ae2: f042 0201 orr.w r2, r2, #1 + 8007ae6: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; - 8007170: 687b ldr r3, [r7, #4] - 8007172: 2220 movs r2, #32 - 8007174: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007ae8: 687b ldr r3, [r7, #4] + 8007aea: 2220 movs r2, #32 + 8007aec: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8007178: 687b ldr r3, [r7, #4] - 800717a: 2200 movs r2, #0 - 800717c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007af0: 687b ldr r3, [r7, #4] + 8007af2: 2200 movs r2, #0 + 8007af4: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; - 8007180: 2300 movs r3, #0 - 8007182: e000 b.n 8007186 + 8007af8: 2300 movs r3, #0 + 8007afa: e000 b.n 8007afe } else { return HAL_BUSY; - 8007184: 2302 movs r3, #2 + 8007afc: 2302 movs r3, #2 } } - 8007186: 4618 mov r0, r3 - 8007188: 370c adds r7, #12 - 800718a: 46bd mov sp, r7 - 800718c: f85d 7b04 ldr.w r7, [sp], #4 - 8007190: 4770 bx lr + 8007afe: 4618 mov r0, r3 + 8007b00: 370c adds r7, #12 + 8007b02: 46bd mov sp, r7 + 8007b04: f85d 7b04 ldr.w r7, [sp], #4 + 8007b08: 4770 bx lr -08007192 : +08007b0a : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { - 8007192: b480 push {r7} - 8007194: b085 sub sp, #20 - 8007196: af00 add r7, sp, #0 - 8007198: 6078 str r0, [r7, #4] - 800719a: 6039 str r1, [r7, #0] + 8007b0a: b480 push {r7} + 8007b0c: b085 sub sp, #20 + 8007b0e: af00 add r7, sp, #0 + 8007b10: 6078 str r0, [r7, #4] + 8007b12: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) - 800719c: 687b ldr r3, [r7, #4] - 800719e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 - 80071a2: b2db uxtb r3, r3 - 80071a4: 2b20 cmp r3, #32 - 80071a6: d139 bne.n 800721c + 8007b14: 687b ldr r3, [r7, #4] + 8007b16: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8007b1a: b2db uxtb r3, r3 + 8007b1c: 2b20 cmp r3, #32 + 8007b1e: d139 bne.n 8007b94 { /* Process Locked */ __HAL_LOCK(hi2c); - 80071a8: 687b ldr r3, [r7, #4] - 80071aa: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 - 80071ae: 2b01 cmp r3, #1 - 80071b0: d101 bne.n 80071b6 - 80071b2: 2302 movs r3, #2 - 80071b4: e033 b.n 800721e - 80071b6: 687b ldr r3, [r7, #4] - 80071b8: 2201 movs r2, #1 - 80071ba: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007b20: 687b ldr r3, [r7, #4] + 8007b22: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8007b26: 2b01 cmp r3, #1 + 8007b28: d101 bne.n 8007b2e + 8007b2a: 2302 movs r3, #2 + 8007b2c: e033 b.n 8007b96 + 8007b2e: 687b ldr r3, [r7, #4] + 8007b30: 2201 movs r2, #1 + 8007b32: f883 2040 strb.w r2, [r3, #64] ; 0x40 hi2c->State = HAL_I2C_STATE_BUSY; - 80071be: 687b ldr r3, [r7, #4] - 80071c0: 2224 movs r2, #36 ; 0x24 - 80071c2: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007b36: 687b ldr r3, [r7, #4] + 8007b38: 2224 movs r2, #36 ; 0x24 + 8007b3a: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); - 80071c6: 687b ldr r3, [r7, #4] - 80071c8: 681b ldr r3, [r3, #0] - 80071ca: 681a ldr r2, [r3, #0] - 80071cc: 687b ldr r3, [r7, #4] - 80071ce: 681b ldr r3, [r3, #0] - 80071d0: f022 0201 bic.w r2, r2, #1 - 80071d4: 601a str r2, [r3, #0] + 8007b3e: 687b ldr r3, [r7, #4] + 8007b40: 681b ldr r3, [r3, #0] + 8007b42: 681a ldr r2, [r3, #0] + 8007b44: 687b ldr r3, [r7, #4] + 8007b46: 681b ldr r3, [r3, #0] + 8007b48: f022 0201 bic.w r2, r2, #1 + 8007b4c: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; - 80071d6: 687b ldr r3, [r7, #4] - 80071d8: 681b ldr r3, [r3, #0] - 80071da: 681b ldr r3, [r3, #0] - 80071dc: 60fb str r3, [r7, #12] + 8007b4e: 687b ldr r3, [r7, #4] + 8007b50: 681b ldr r3, [r3, #0] + 8007b52: 681b ldr r3, [r3, #0] + 8007b54: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); - 80071de: 68fb ldr r3, [r7, #12] - 80071e0: f423 6370 bic.w r3, r3, #3840 ; 0xf00 - 80071e4: 60fb str r3, [r7, #12] + 8007b56: 68fb ldr r3, [r7, #12] + 8007b58: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 8007b5c: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; - 80071e6: 683b ldr r3, [r7, #0] - 80071e8: 021b lsls r3, r3, #8 - 80071ea: 68fa ldr r2, [r7, #12] - 80071ec: 4313 orrs r3, r2 - 80071ee: 60fb str r3, [r7, #12] + 8007b5e: 683b ldr r3, [r7, #0] + 8007b60: 021b lsls r3, r3, #8 + 8007b62: 68fa ldr r2, [r7, #12] + 8007b64: 4313 orrs r3, r2 + 8007b66: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; - 80071f0: 687b ldr r3, [r7, #4] - 80071f2: 681b ldr r3, [r3, #0] - 80071f4: 68fa ldr r2, [r7, #12] - 80071f6: 601a str r2, [r3, #0] + 8007b68: 687b ldr r3, [r7, #4] + 8007b6a: 681b ldr r3, [r3, #0] + 8007b6c: 68fa ldr r2, [r7, #12] + 8007b6e: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); - 80071f8: 687b ldr r3, [r7, #4] - 80071fa: 681b ldr r3, [r3, #0] - 80071fc: 681a ldr r2, [r3, #0] - 80071fe: 687b ldr r3, [r7, #4] - 8007200: 681b ldr r3, [r3, #0] - 8007202: f042 0201 orr.w r2, r2, #1 - 8007206: 601a str r2, [r3, #0] + 8007b70: 687b ldr r3, [r7, #4] + 8007b72: 681b ldr r3, [r3, #0] + 8007b74: 681a ldr r2, [r3, #0] + 8007b76: 687b ldr r3, [r7, #4] + 8007b78: 681b ldr r3, [r3, #0] + 8007b7a: f042 0201 orr.w r2, r2, #1 + 8007b7e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; - 8007208: 687b ldr r3, [r7, #4] - 800720a: 2220 movs r2, #32 - 800720c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 8007b80: 687b ldr r3, [r7, #4] + 8007b82: 2220 movs r2, #32 + 8007b84: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Process Unlocked */ __HAL_UNLOCK(hi2c); - 8007210: 687b ldr r3, [r7, #4] - 8007212: 2200 movs r2, #0 - 8007214: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8007b88: 687b ldr r3, [r7, #4] + 8007b8a: 2200 movs r2, #0 + 8007b8c: f883 2040 strb.w r2, [r3, #64] ; 0x40 return HAL_OK; - 8007218: 2300 movs r3, #0 - 800721a: e000 b.n 800721e + 8007b90: 2300 movs r3, #0 + 8007b92: e000 b.n 8007b96 } else { return HAL_BUSY; - 800721c: 2302 movs r3, #2 + 8007b94: 2302 movs r3, #2 } } - 800721e: 4618 mov r0, r3 - 8007220: 3714 adds r7, #20 - 8007222: 46bd mov sp, r7 - 8007224: f85d 7b04 ldr.w r7, [sp], #4 - 8007228: 4770 bx lr + 8007b96: 4618 mov r0, r3 + 8007b98: 3714 adds r7, #20 + 8007b9a: 46bd mov sp, r7 + 8007b9c: f85d 7b04 ldr.w r7, [sp], #4 + 8007ba0: 4770 bx lr ... -0800722c : +08007ba4 : * @note For all I2C4 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C4 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) { - 800722c: b480 push {r7} - 800722e: b085 sub sp, #20 - 8007230: af00 add r7, sp, #0 - 8007232: 6078 str r0, [r7, #4] + 8007ba4: b480 push {r7} + 8007ba6: b085 sub sp, #20 + 8007ba8: af00 add r7, sp, #0 + 8007baa: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8007234: 4b0b ldr r3, [pc, #44] ; (8007264 ) - 8007236: 6e1b ldr r3, [r3, #96] ; 0x60 - 8007238: 4a0a ldr r2, [pc, #40] ; (8007264 ) - 800723a: f043 0301 orr.w r3, r3, #1 - 800723e: 6613 str r3, [r2, #96] ; 0x60 - 8007240: 4b08 ldr r3, [pc, #32] ; (8007264 ) - 8007242: 6e1b ldr r3, [r3, #96] ; 0x60 - 8007244: f003 0301 and.w r3, r3, #1 - 8007248: 60fb str r3, [r7, #12] - 800724a: 68fb ldr r3, [r7, #12] + 8007bac: 4b0b ldr r3, [pc, #44] ; (8007bdc ) + 8007bae: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007bb0: 4a0a ldr r2, [pc, #40] ; (8007bdc ) + 8007bb2: f043 0301 orr.w r3, r3, #1 + 8007bb6: 6613 str r3, [r2, #96] ; 0x60 + 8007bb8: 4b08 ldr r3, [pc, #32] ; (8007bdc ) + 8007bba: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007bbc: f003 0301 and.w r3, r3, #1 + 8007bc0: 60fb str r3, [r7, #12] + 8007bc2: 68fb ldr r3, [r7, #12] /* Enable fast mode plus driving capability for selected pin */ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); - 800724c: 4b06 ldr r3, [pc, #24] ; (8007268 ) - 800724e: 685a ldr r2, [r3, #4] - 8007250: 4905 ldr r1, [pc, #20] ; (8007268 ) - 8007252: 687b ldr r3, [r7, #4] - 8007254: 4313 orrs r3, r2 - 8007256: 604b str r3, [r1, #4] -} - 8007258: bf00 nop - 800725a: 3714 adds r7, #20 - 800725c: 46bd mov sp, r7 - 800725e: f85d 7b04 ldr.w r7, [sp], #4 - 8007262: 4770 bx lr - 8007264: 40021000 .word 0x40021000 - 8007268: 40010000 .word 0x40010000 - -0800726c : + 8007bc4: 4b06 ldr r3, [pc, #24] ; (8007be0 ) + 8007bc6: 685a ldr r2, [r3, #4] + 8007bc8: 4905 ldr r1, [pc, #20] ; (8007be0 ) + 8007bca: 687b ldr r3, [r7, #4] + 8007bcc: 4313 orrs r3, r2 + 8007bce: 604b str r3, [r1, #4] +} + 8007bd0: bf00 nop + 8007bd2: 3714 adds r7, #20 + 8007bd4: 46bd mov sp, r7 + 8007bd6: f85d 7b04 ldr.w r7, [sp], #4 + 8007bda: 4770 bx lr + 8007bdc: 40021000 .word 0x40021000 + 8007be0: 40010000 .word 0x40010000 + +08007be4 : * parameters in the PCD_InitTypeDef and initialize the associated handle. * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - 800726c: b5f0 push {r4, r5, r6, r7, lr} - 800726e: b08b sub sp, #44 ; 0x2c - 8007270: af06 add r7, sp, #24 - 8007272: 6078 str r0, [r7, #4] + 8007be4: b5f0 push {r4, r5, r6, r7, lr} + 8007be6: b08b sub sp, #44 ; 0x2c + 8007be8: af06 add r7, sp, #24 + 8007bea: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx; #endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ if (hpcd == NULL) - 8007274: 687b ldr r3, [r7, #4] - 8007276: 2b00 cmp r3, #0 - 8007278: d101 bne.n 800727e + 8007bec: 687b ldr r3, [r7, #4] + 8007bee: 2b00 cmp r3, #0 + 8007bf0: d101 bne.n 8007bf6 { return HAL_ERROR; - 800727a: 2301 movs r3, #1 - 800727c: e0f8 b.n 8007470 + 8007bf2: 2301 movs r3, #1 + 8007bf4: e0f8 b.n 8007de8 #if defined (USB_OTG_FS) USBx = hpcd->Instance; #endif /* defined (USB_OTG_FS) */ if (hpcd->State == HAL_PCD_STATE_RESET) - 800727e: 687b ldr r3, [r7, #4] - 8007280: f893 32a9 ldrb.w r3, [r3, #681] ; 0x2a9 - 8007284: b2db uxtb r3, r3 - 8007286: 2b00 cmp r3, #0 - 8007288: d106 bne.n 8007298 + 8007bf6: 687b ldr r3, [r7, #4] + 8007bf8: f893 32a9 ldrb.w r3, [r3, #681] ; 0x2a9 + 8007bfc: b2db uxtb r3, r3 + 8007bfe: 2b00 cmp r3, #0 + 8007c00: d106 bne.n 8007c10 { /* Allocate lock resource and initialize it */ hpcd->Lock = HAL_UNLOCKED; - 800728a: 687b ldr r3, [r7, #4] - 800728c: 2200 movs r2, #0 - 800728e: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8007c02: 687b ldr r3, [r7, #4] + 8007c04: 2200 movs r2, #0 + 8007c06: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 /* Init the low level hardware */ hpcd->MspInitCallback(hpcd); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_PCD_MspInit(hpcd); - 8007292: 6878 ldr r0, [r7, #4] - 8007294: f009 f8f4 bl 8010480 + 8007c0a: 6878 ldr r0, [r7, #4] + 8007c0c: f00a fe66 bl 80128dc #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ } hpcd->State = HAL_PCD_STATE_BUSY; - 8007298: 687b ldr r3, [r7, #4] - 800729a: 2203 movs r2, #3 - 800729c: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 + 8007c10: 687b ldr r3, [r7, #4] + 8007c12: 2203 movs r2, #3 + 8007c14: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 hpcd->Init.dma_enable = 0U; } #endif /* defined (USB_OTG_FS) */ /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); - 80072a0: 687b ldr r3, [r7, #4] - 80072a2: 681b ldr r3, [r3, #0] - 80072a4: 4618 mov r0, r3 - 80072a6: f004 ff6f bl 800c188 + 8007c18: 687b ldr r3, [r7, #4] + 8007c1a: 681b ldr r3, [r3, #0] + 8007c1c: 4618 mov r0, r3 + 8007c1e: f005 fc0b bl 800d438 /*Init the Core (common init.) */ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) - 80072aa: 687b ldr r3, [r7, #4] - 80072ac: 681b ldr r3, [r3, #0] - 80072ae: 603b str r3, [r7, #0] - 80072b0: 687e ldr r6, [r7, #4] - 80072b2: 466d mov r5, sp - 80072b4: f106 0410 add.w r4, r6, #16 - 80072b8: cc0f ldmia r4!, {r0, r1, r2, r3} - 80072ba: c50f stmia r5!, {r0, r1, r2, r3} - 80072bc: 6823 ldr r3, [r4, #0] - 80072be: 602b str r3, [r5, #0] - 80072c0: 1d33 adds r3, r6, #4 - 80072c2: cb0e ldmia r3, {r1, r2, r3} - 80072c4: 6838 ldr r0, [r7, #0] - 80072c6: f004 ff37 bl 800c138 - 80072ca: 4603 mov r3, r0 - 80072cc: 2b00 cmp r3, #0 - 80072ce: d005 beq.n 80072dc + 8007c22: 687b ldr r3, [r7, #4] + 8007c24: 681b ldr r3, [r3, #0] + 8007c26: 603b str r3, [r7, #0] + 8007c28: 687e ldr r6, [r7, #4] + 8007c2a: 466d mov r5, sp + 8007c2c: f106 0410 add.w r4, r6, #16 + 8007c30: cc0f ldmia r4!, {r0, r1, r2, r3} + 8007c32: c50f stmia r5!, {r0, r1, r2, r3} + 8007c34: 6823 ldr r3, [r4, #0] + 8007c36: 602b str r3, [r5, #0] + 8007c38: 1d33 adds r3, r6, #4 + 8007c3a: cb0e ldmia r3, {r1, r2, r3} + 8007c3c: 6838 ldr r0, [r7, #0] + 8007c3e: f005 fbd3 bl 800d3e8 + 8007c42: 4603 mov r3, r0 + 8007c44: 2b00 cmp r3, #0 + 8007c46: d005 beq.n 8007c54 { hpcd->State = HAL_PCD_STATE_ERROR; - 80072d0: 687b ldr r3, [r7, #4] - 80072d2: 2202 movs r2, #2 - 80072d4: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 + 8007c48: 687b ldr r3, [r7, #4] + 8007c4a: 2202 movs r2, #2 + 8007c4c: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 return HAL_ERROR; - 80072d8: 2301 movs r3, #1 - 80072da: e0c9 b.n 8007470 + 8007c50: 2301 movs r3, #1 + 8007c52: e0c9 b.n 8007de8 } /* Force Device Mode*/ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); - 80072dc: 687b ldr r3, [r7, #4] - 80072de: 681b ldr r3, [r3, #0] - 80072e0: 2100 movs r1, #0 - 80072e2: 4618 mov r0, r3 - 80072e4: f004 ff6b bl 800c1be + 8007c54: 687b ldr r3, [r7, #4] + 8007c56: 681b ldr r3, [r3, #0] + 8007c58: 2100 movs r1, #0 + 8007c5a: 4618 mov r0, r3 + 8007c5c: f005 fc07 bl 800d46e /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - 80072e8: 2300 movs r3, #0 - 80072ea: 73fb strb r3, [r7, #15] - 80072ec: e040 b.n 8007370 + 8007c60: 2300 movs r3, #0 + 8007c62: 73fb strb r3, [r7, #15] + 8007c64: e040 b.n 8007ce8 { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; - 80072ee: 7bfb ldrb r3, [r7, #15] - 80072f0: 6879 ldr r1, [r7, #4] - 80072f2: 1c5a adds r2, r3, #1 - 80072f4: 4613 mov r3, r2 - 80072f6: 009b lsls r3, r3, #2 - 80072f8: 4413 add r3, r2 - 80072fa: 00db lsls r3, r3, #3 - 80072fc: 440b add r3, r1 - 80072fe: 3301 adds r3, #1 - 8007300: 2201 movs r2, #1 - 8007302: 701a strb r2, [r3, #0] + 8007c66: 7bfb ldrb r3, [r7, #15] + 8007c68: 6879 ldr r1, [r7, #4] + 8007c6a: 1c5a adds r2, r3, #1 + 8007c6c: 4613 mov r3, r2 + 8007c6e: 009b lsls r3, r3, #2 + 8007c70: 4413 add r3, r2 + 8007c72: 00db lsls r3, r3, #3 + 8007c74: 440b add r3, r1 + 8007c76: 3301 adds r3, #1 + 8007c78: 2201 movs r2, #1 + 8007c7a: 701a strb r2, [r3, #0] hpcd->IN_ep[i].num = i; - 8007304: 7bfb ldrb r3, [r7, #15] - 8007306: 6879 ldr r1, [r7, #4] - 8007308: 1c5a adds r2, r3, #1 - 800730a: 4613 mov r3, r2 - 800730c: 009b lsls r3, r3, #2 - 800730e: 4413 add r3, r2 - 8007310: 00db lsls r3, r3, #3 - 8007312: 440b add r3, r1 - 8007314: 7bfa ldrb r2, [r7, #15] - 8007316: 701a strb r2, [r3, #0] + 8007c7c: 7bfb ldrb r3, [r7, #15] + 8007c7e: 6879 ldr r1, [r7, #4] + 8007c80: 1c5a adds r2, r3, #1 + 8007c82: 4613 mov r3, r2 + 8007c84: 009b lsls r3, r3, #2 + 8007c86: 4413 add r3, r2 + 8007c88: 00db lsls r3, r3, #3 + 8007c8a: 440b add r3, r1 + 8007c8c: 7bfa ldrb r2, [r7, #15] + 8007c8e: 701a strb r2, [r3, #0] #if defined (USB_OTG_FS) hpcd->IN_ep[i].tx_fifo_num = i; #endif /* defined (USB_OTG_FS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; - 8007318: 7bfb ldrb r3, [r7, #15] - 800731a: 6879 ldr r1, [r7, #4] - 800731c: 1c5a adds r2, r3, #1 - 800731e: 4613 mov r3, r2 - 8007320: 009b lsls r3, r3, #2 - 8007322: 4413 add r3, r2 - 8007324: 00db lsls r3, r3, #3 - 8007326: 440b add r3, r1 - 8007328: 3303 adds r3, #3 - 800732a: 2200 movs r2, #0 - 800732c: 701a strb r2, [r3, #0] + 8007c90: 7bfb ldrb r3, [r7, #15] + 8007c92: 6879 ldr r1, [r7, #4] + 8007c94: 1c5a adds r2, r3, #1 + 8007c96: 4613 mov r3, r2 + 8007c98: 009b lsls r3, r3, #2 + 8007c9a: 4413 add r3, r2 + 8007c9c: 00db lsls r3, r3, #3 + 8007c9e: 440b add r3, r1 + 8007ca0: 3303 adds r3, #3 + 8007ca2: 2200 movs r2, #0 + 8007ca4: 701a strb r2, [r3, #0] hpcd->IN_ep[i].maxpacket = 0U; - 800732e: 7bfa ldrb r2, [r7, #15] - 8007330: 6879 ldr r1, [r7, #4] - 8007332: 4613 mov r3, r2 - 8007334: 009b lsls r3, r3, #2 - 8007336: 4413 add r3, r2 - 8007338: 00db lsls r3, r3, #3 - 800733a: 440b add r3, r1 - 800733c: 3338 adds r3, #56 ; 0x38 - 800733e: 2200 movs r2, #0 - 8007340: 601a str r2, [r3, #0] + 8007ca6: 7bfa ldrb r2, [r7, #15] + 8007ca8: 6879 ldr r1, [r7, #4] + 8007caa: 4613 mov r3, r2 + 8007cac: 009b lsls r3, r3, #2 + 8007cae: 4413 add r3, r2 + 8007cb0: 00db lsls r3, r3, #3 + 8007cb2: 440b add r3, r1 + 8007cb4: 3338 adds r3, #56 ; 0x38 + 8007cb6: 2200 movs r2, #0 + 8007cb8: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_buff = 0U; - 8007342: 7bfa ldrb r2, [r7, #15] - 8007344: 6879 ldr r1, [r7, #4] - 8007346: 4613 mov r3, r2 - 8007348: 009b lsls r3, r3, #2 - 800734a: 4413 add r3, r2 - 800734c: 00db lsls r3, r3, #3 - 800734e: 440b add r3, r1 - 8007350: 333c adds r3, #60 ; 0x3c - 8007352: 2200 movs r2, #0 - 8007354: 601a str r2, [r3, #0] + 8007cba: 7bfa ldrb r2, [r7, #15] + 8007cbc: 6879 ldr r1, [r7, #4] + 8007cbe: 4613 mov r3, r2 + 8007cc0: 009b lsls r3, r3, #2 + 8007cc2: 4413 add r3, r2 + 8007cc4: 00db lsls r3, r3, #3 + 8007cc6: 440b add r3, r1 + 8007cc8: 333c adds r3, #60 ; 0x3c + 8007cca: 2200 movs r2, #0 + 8007ccc: 601a str r2, [r3, #0] hpcd->IN_ep[i].xfer_len = 0U; - 8007356: 7bfa ldrb r2, [r7, #15] - 8007358: 6879 ldr r1, [r7, #4] - 800735a: 4613 mov r3, r2 - 800735c: 009b lsls r3, r3, #2 - 800735e: 4413 add r3, r2 - 8007360: 00db lsls r3, r3, #3 - 8007362: 440b add r3, r1 - 8007364: 3340 adds r3, #64 ; 0x40 - 8007366: 2200 movs r2, #0 - 8007368: 601a str r2, [r3, #0] + 8007cce: 7bfa ldrb r2, [r7, #15] + 8007cd0: 6879 ldr r1, [r7, #4] + 8007cd2: 4613 mov r3, r2 + 8007cd4: 009b lsls r3, r3, #2 + 8007cd6: 4413 add r3, r2 + 8007cd8: 00db lsls r3, r3, #3 + 8007cda: 440b add r3, r1 + 8007cdc: 3340 adds r3, #64 ; 0x40 + 8007cde: 2200 movs r2, #0 + 8007ce0: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - 800736a: 7bfb ldrb r3, [r7, #15] - 800736c: 3301 adds r3, #1 - 800736e: 73fb strb r3, [r7, #15] - 8007370: 7bfa ldrb r2, [r7, #15] - 8007372: 687b ldr r3, [r7, #4] - 8007374: 685b ldr r3, [r3, #4] - 8007376: 429a cmp r2, r3 - 8007378: d3b9 bcc.n 80072ee + 8007ce2: 7bfb ldrb r3, [r7, #15] + 8007ce4: 3301 adds r3, #1 + 8007ce6: 73fb strb r3, [r7, #15] + 8007ce8: 7bfa ldrb r2, [r7, #15] + 8007cea: 687b ldr r3, [r7, #4] + 8007cec: 685b ldr r3, [r3, #4] + 8007cee: 429a cmp r2, r3 + 8007cf0: d3b9 bcc.n 8007c66 } for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - 800737a: 2300 movs r3, #0 - 800737c: 73fb strb r3, [r7, #15] - 800737e: e044 b.n 800740a + 8007cf2: 2300 movs r3, #0 + 8007cf4: 73fb strb r3, [r7, #15] + 8007cf6: e044 b.n 8007d82 { hpcd->OUT_ep[i].is_in = 0U; - 8007380: 7bfa ldrb r2, [r7, #15] - 8007382: 6879 ldr r1, [r7, #4] - 8007384: 4613 mov r3, r2 - 8007386: 009b lsls r3, r3, #2 - 8007388: 4413 add r3, r2 - 800738a: 00db lsls r3, r3, #3 - 800738c: 440b add r3, r1 - 800738e: f203 1369 addw r3, r3, #361 ; 0x169 - 8007392: 2200 movs r2, #0 - 8007394: 701a strb r2, [r3, #0] + 8007cf8: 7bfa ldrb r2, [r7, #15] + 8007cfa: 6879 ldr r1, [r7, #4] + 8007cfc: 4613 mov r3, r2 + 8007cfe: 009b lsls r3, r3, #2 + 8007d00: 4413 add r3, r2 + 8007d02: 00db lsls r3, r3, #3 + 8007d04: 440b add r3, r1 + 8007d06: f203 1369 addw r3, r3, #361 ; 0x169 + 8007d0a: 2200 movs r2, #0 + 8007d0c: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].num = i; - 8007396: 7bfa ldrb r2, [r7, #15] - 8007398: 6879 ldr r1, [r7, #4] - 800739a: 4613 mov r3, r2 - 800739c: 009b lsls r3, r3, #2 - 800739e: 4413 add r3, r2 - 80073a0: 00db lsls r3, r3, #3 - 80073a2: 440b add r3, r1 - 80073a4: f503 73b4 add.w r3, r3, #360 ; 0x168 - 80073a8: 7bfa ldrb r2, [r7, #15] - 80073aa: 701a strb r2, [r3, #0] + 8007d0e: 7bfa ldrb r2, [r7, #15] + 8007d10: 6879 ldr r1, [r7, #4] + 8007d12: 4613 mov r3, r2 + 8007d14: 009b lsls r3, r3, #2 + 8007d16: 4413 add r3, r2 + 8007d18: 00db lsls r3, r3, #3 + 8007d1a: 440b add r3, r1 + 8007d1c: f503 73b4 add.w r3, r3, #360 ; 0x168 + 8007d20: 7bfa ldrb r2, [r7, #15] + 8007d22: 701a strb r2, [r3, #0] /* Control until ep is activated */ hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - 80073ac: 7bfa ldrb r2, [r7, #15] - 80073ae: 6879 ldr r1, [r7, #4] - 80073b0: 4613 mov r3, r2 - 80073b2: 009b lsls r3, r3, #2 - 80073b4: 4413 add r3, r2 - 80073b6: 00db lsls r3, r3, #3 - 80073b8: 440b add r3, r1 - 80073ba: f203 136b addw r3, r3, #363 ; 0x16b - 80073be: 2200 movs r2, #0 - 80073c0: 701a strb r2, [r3, #0] + 8007d24: 7bfa ldrb r2, [r7, #15] + 8007d26: 6879 ldr r1, [r7, #4] + 8007d28: 4613 mov r3, r2 + 8007d2a: 009b lsls r3, r3, #2 + 8007d2c: 4413 add r3, r2 + 8007d2e: 00db lsls r3, r3, #3 + 8007d30: 440b add r3, r1 + 8007d32: f203 136b addw r3, r3, #363 ; 0x16b + 8007d36: 2200 movs r2, #0 + 8007d38: 701a strb r2, [r3, #0] hpcd->OUT_ep[i].maxpacket = 0U; - 80073c2: 7bfa ldrb r2, [r7, #15] - 80073c4: 6879 ldr r1, [r7, #4] - 80073c6: 4613 mov r3, r2 - 80073c8: 009b lsls r3, r3, #2 - 80073ca: 4413 add r3, r2 - 80073cc: 00db lsls r3, r3, #3 - 80073ce: 440b add r3, r1 - 80073d0: f503 73bc add.w r3, r3, #376 ; 0x178 - 80073d4: 2200 movs r2, #0 - 80073d6: 601a str r2, [r3, #0] + 8007d3a: 7bfa ldrb r2, [r7, #15] + 8007d3c: 6879 ldr r1, [r7, #4] + 8007d3e: 4613 mov r3, r2 + 8007d40: 009b lsls r3, r3, #2 + 8007d42: 4413 add r3, r2 + 8007d44: 00db lsls r3, r3, #3 + 8007d46: 440b add r3, r1 + 8007d48: f503 73bc add.w r3, r3, #376 ; 0x178 + 8007d4c: 2200 movs r2, #0 + 8007d4e: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_buff = 0U; - 80073d8: 7bfa ldrb r2, [r7, #15] - 80073da: 6879 ldr r1, [r7, #4] - 80073dc: 4613 mov r3, r2 - 80073de: 009b lsls r3, r3, #2 - 80073e0: 4413 add r3, r2 - 80073e2: 00db lsls r3, r3, #3 - 80073e4: 440b add r3, r1 - 80073e6: f503 73be add.w r3, r3, #380 ; 0x17c - 80073ea: 2200 movs r2, #0 - 80073ec: 601a str r2, [r3, #0] + 8007d50: 7bfa ldrb r2, [r7, #15] + 8007d52: 6879 ldr r1, [r7, #4] + 8007d54: 4613 mov r3, r2 + 8007d56: 009b lsls r3, r3, #2 + 8007d58: 4413 add r3, r2 + 8007d5a: 00db lsls r3, r3, #3 + 8007d5c: 440b add r3, r1 + 8007d5e: f503 73be add.w r3, r3, #380 ; 0x17c + 8007d62: 2200 movs r2, #0 + 8007d64: 601a str r2, [r3, #0] hpcd->OUT_ep[i].xfer_len = 0U; - 80073ee: 7bfa ldrb r2, [r7, #15] - 80073f0: 6879 ldr r1, [r7, #4] - 80073f2: 4613 mov r3, r2 - 80073f4: 009b lsls r3, r3, #2 - 80073f6: 4413 add r3, r2 - 80073f8: 00db lsls r3, r3, #3 - 80073fa: 440b add r3, r1 - 80073fc: f503 73c0 add.w r3, r3, #384 ; 0x180 - 8007400: 2200 movs r2, #0 - 8007402: 601a str r2, [r3, #0] + 8007d66: 7bfa ldrb r2, [r7, #15] + 8007d68: 6879 ldr r1, [r7, #4] + 8007d6a: 4613 mov r3, r2 + 8007d6c: 009b lsls r3, r3, #2 + 8007d6e: 4413 add r3, r2 + 8007d70: 00db lsls r3, r3, #3 + 8007d72: 440b add r3, r1 + 8007d74: f503 73c0 add.w r3, r3, #384 ; 0x180 + 8007d78: 2200 movs r2, #0 + 8007d7a: 601a str r2, [r3, #0] for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - 8007404: 7bfb ldrb r3, [r7, #15] - 8007406: 3301 adds r3, #1 - 8007408: 73fb strb r3, [r7, #15] - 800740a: 7bfa ldrb r2, [r7, #15] - 800740c: 687b ldr r3, [r7, #4] - 800740e: 685b ldr r3, [r3, #4] - 8007410: 429a cmp r2, r3 - 8007412: d3b5 bcc.n 8007380 + 8007d7c: 7bfb ldrb r3, [r7, #15] + 8007d7e: 3301 adds r3, #1 + 8007d80: 73fb strb r3, [r7, #15] + 8007d82: 7bfa ldrb r2, [r7, #15] + 8007d84: 687b ldr r3, [r7, #4] + 8007d86: 685b ldr r3, [r3, #4] + 8007d88: 429a cmp r2, r3 + 8007d8a: d3b5 bcc.n 8007cf8 } /* Init Device */ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) - 8007414: 687b ldr r3, [r7, #4] - 8007416: 681b ldr r3, [r3, #0] - 8007418: 603b str r3, [r7, #0] - 800741a: 687e ldr r6, [r7, #4] - 800741c: 466d mov r5, sp - 800741e: f106 0410 add.w r4, r6, #16 - 8007422: cc0f ldmia r4!, {r0, r1, r2, r3} - 8007424: c50f stmia r5!, {r0, r1, r2, r3} - 8007426: 6823 ldr r3, [r4, #0] - 8007428: 602b str r3, [r5, #0] - 800742a: 1d33 adds r3, r6, #4 - 800742c: cb0e ldmia r3, {r1, r2, r3} - 800742e: 6838 ldr r0, [r7, #0] - 8007430: f004 fed2 bl 800c1d8 - 8007434: 4603 mov r3, r0 - 8007436: 2b00 cmp r3, #0 - 8007438: d005 beq.n 8007446 + 8007d8c: 687b ldr r3, [r7, #4] + 8007d8e: 681b ldr r3, [r3, #0] + 8007d90: 603b str r3, [r7, #0] + 8007d92: 687e ldr r6, [r7, #4] + 8007d94: 466d mov r5, sp + 8007d96: f106 0410 add.w r4, r6, #16 + 8007d9a: cc0f ldmia r4!, {r0, r1, r2, r3} + 8007d9c: c50f stmia r5!, {r0, r1, r2, r3} + 8007d9e: 6823 ldr r3, [r4, #0] + 8007da0: 602b str r3, [r5, #0] + 8007da2: 1d33 adds r3, r6, #4 + 8007da4: cb0e ldmia r3, {r1, r2, r3} + 8007da6: 6838 ldr r0, [r7, #0] + 8007da8: f005 fb6e bl 800d488 + 8007dac: 4603 mov r3, r0 + 8007dae: 2b00 cmp r3, #0 + 8007db0: d005 beq.n 8007dbe { hpcd->State = HAL_PCD_STATE_ERROR; - 800743a: 687b ldr r3, [r7, #4] - 800743c: 2202 movs r2, #2 - 800743e: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 + 8007db2: 687b ldr r3, [r7, #4] + 8007db4: 2202 movs r2, #2 + 8007db6: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 return HAL_ERROR; - 8007442: 2301 movs r3, #1 - 8007444: e014 b.n 8007470 + 8007dba: 2301 movs r3, #1 + 8007dbc: e014 b.n 8007de8 } hpcd->USB_Address = 0U; - 8007446: 687b ldr r3, [r7, #4] - 8007448: 2200 movs r2, #0 - 800744a: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8007dbe: 687b ldr r3, [r7, #4] + 8007dc0: 2200 movs r2, #0 + 8007dc2: f883 2024 strb.w r2, [r3, #36] ; 0x24 hpcd->State = HAL_PCD_STATE_READY; - 800744e: 687b ldr r3, [r7, #4] - 8007450: 2201 movs r2, #1 - 8007452: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 + 8007dc6: 687b ldr r3, [r7, #4] + 8007dc8: 2201 movs r2, #1 + 8007dca: f883 22a9 strb.w r2, [r3, #681] ; 0x2a9 /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) - 8007456: 687b ldr r3, [r7, #4] - 8007458: 69db ldr r3, [r3, #28] - 800745a: 2b01 cmp r3, #1 - 800745c: d102 bne.n 8007464 + 8007dce: 687b ldr r3, [r7, #4] + 8007dd0: 69db ldr r3, [r3, #28] + 8007dd2: 2b01 cmp r3, #1 + 8007dd4: d102 bne.n 8007ddc { (void)HAL_PCDEx_ActivateLPM(hpcd); - 800745e: 6878 ldr r0, [r7, #4] - 8007460: f001 fc40 bl 8008ce4 + 8007dd6: 6878 ldr r0, [r7, #4] + 8007dd8: f001 fc58 bl 800968c } (void)USB_DevDisconnect(hpcd->Instance); - 8007464: 687b ldr r3, [r7, #4] - 8007466: 681b ldr r3, [r3, #0] - 8007468: 4618 mov r0, r3 - 800746a: f007 f963 bl 800e734 + 8007ddc: 687b ldr r3, [r7, #4] + 8007dde: 681b ldr r3, [r3, #0] + 8007de0: 4618 mov r0, r3 + 8007de2: f007 fdff bl 800f9e4 return HAL_OK; - 800746e: 2300 movs r3, #0 + 8007de6: 2300 movs r3, #0 } - 8007470: 4618 mov r0, r3 - 8007472: 3714 adds r7, #20 - 8007474: 46bd mov sp, r7 - 8007476: bdf0 pop {r4, r5, r6, r7, pc} + 8007de8: 4618 mov r0, r3 + 8007dea: 3714 adds r7, #20 + 8007dec: 46bd mov sp, r7 + 8007dee: bdf0 pop {r4, r5, r6, r7, pc} -08007478 : +08007df0 : * @brief Start the USB device * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { - 8007478: b580 push {r7, lr} - 800747a: b082 sub sp, #8 - 800747c: af00 add r7, sp, #0 - 800747e: 6078 str r0, [r7, #4] + 8007df0: b580 push {r7, lr} + 8007df2: b082 sub sp, #8 + 8007df4: af00 add r7, sp, #0 + 8007df6: 6078 str r0, [r7, #4] #if defined (USB_OTG_FS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; #endif /* defined (USB_OTG_FS) */ __HAL_LOCK(hpcd); - 8007480: 687b ldr r3, [r7, #4] - 8007482: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 8007486: 2b01 cmp r3, #1 - 8007488: d101 bne.n 800748e - 800748a: 2302 movs r3, #2 - 800748c: e012 b.n 80074b4 - 800748e: 687b ldr r3, [r7, #4] - 8007490: 2201 movs r2, #1 - 8007492: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8007df8: 687b ldr r3, [r7, #4] + 8007dfa: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8007dfe: 2b01 cmp r3, #1 + 8007e00: d101 bne.n 8007e06 + 8007e02: 2302 movs r3, #2 + 8007e04: e012 b.n 8007e2c + 8007e06: 687b ldr r3, [r7, #4] + 8007e08: 2201 movs r2, #1 + 8007e0a: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } #endif /* defined (USB_OTG_FS) */ __HAL_PCD_ENABLE(hpcd); - 8007496: 687b ldr r3, [r7, #4] - 8007498: 681b ldr r3, [r3, #0] - 800749a: 4618 mov r0, r3 - 800749c: f004 fe5d bl 800c15a + 8007e0e: 687b ldr r3, [r7, #4] + 8007e10: 681b ldr r3, [r3, #0] + 8007e12: 4618 mov r0, r3 + 8007e14: f005 faf9 bl 800d40a (void)USB_DevConnect(hpcd->Instance); - 80074a0: 687b ldr r3, [r7, #4] - 80074a2: 681b ldr r3, [r3, #0] - 80074a4: 4618 mov r0, r3 - 80074a6: f007 f92e bl 800e706 + 8007e18: 687b ldr r3, [r7, #4] + 8007e1a: 681b ldr r3, [r3, #0] + 8007e1c: 4618 mov r0, r3 + 8007e1e: f007 fdca bl 800f9b6 __HAL_UNLOCK(hpcd); - 80074aa: 687b ldr r3, [r7, #4] - 80074ac: 2200 movs r2, #0 - 80074ae: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8007e22: 687b ldr r3, [r7, #4] + 8007e24: 2200 movs r2, #0 + 8007e26: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return HAL_OK; - 80074b2: 2300 movs r3, #0 + 8007e2a: 2300 movs r3, #0 } - 80074b4: 4618 mov r0, r3 - 80074b6: 3708 adds r7, #8 - 80074b8: 46bd mov sp, r7 - 80074ba: bd80 pop {r7, pc} + 8007e2c: 4618 mov r0, r3 + 8007e2e: 3708 adds r7, #8 + 8007e30: 46bd mov sp, r7 + 8007e32: bd80 pop {r7, pc} -080074bc : +08007e34 : * @brief This function handles PCD interrupt request. * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - 80074bc: b580 push {r7, lr} - 80074be: b084 sub sp, #16 - 80074c0: af00 add r7, sp, #0 - 80074c2: 6078 str r0, [r7, #4] + 8007e34: b580 push {r7, lr} + 8007e36: b084 sub sp, #16 + 8007e38: af00 add r7, sp, #0 + 8007e3a: 6078 str r0, [r7, #4] uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); - 80074c4: 687b ldr r3, [r7, #4] - 80074c6: 681b ldr r3, [r3, #0] - 80074c8: 4618 mov r0, r3 - 80074ca: f007 f948 bl 800e75e - 80074ce: 60f8 str r0, [r7, #12] + 8007e3c: 687b ldr r3, [r7, #4] + 8007e3e: 681b ldr r3, [r3, #0] + 8007e40: 4618 mov r0, r3 + 8007e42: f007 fde4 bl 800fa0e + 8007e46: 60f8 str r0, [r7, #12] if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) - 80074d0: 68fb ldr r3, [r7, #12] - 80074d2: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 80074d6: 2b00 cmp r3, #0 - 80074d8: d003 beq.n 80074e2 + 8007e48: 68fb ldr r3, [r7, #12] + 8007e4a: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8007e4e: 2b00 cmp r3, #0 + 8007e50: d003 beq.n 8007e5a { /* servicing of the endpoint correct transfer interrupt */ /* clear of the CTR flag into the sub */ (void)PCD_EP_ISR_Handler(hpcd); - 80074da: 6878 ldr r0, [r7, #4] - 80074dc: f000 fafb bl 8007ad6 + 8007e52: 6878 ldr r0, [r7, #4] + 8007e54: f000 fb13 bl 800847e return; - 80074e0: e110 b.n 8007704 + 8007e58: e110 b.n 800807c } if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) - 80074e2: 68fb ldr r3, [r7, #12] - 80074e4: f403 6380 and.w r3, r3, #1024 ; 0x400 - 80074e8: 2b00 cmp r3, #0 - 80074ea: d013 beq.n 8007514 + 8007e5a: 68fb ldr r3, [r7, #12] + 8007e5c: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8007e60: 2b00 cmp r3, #0 + 8007e62: d013 beq.n 8007e8c { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - 80074ec: 687b ldr r3, [r7, #4] - 80074ee: 681b ldr r3, [r3, #0] - 80074f0: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 80074f4: b29a uxth r2, r3 - 80074f6: 687b ldr r3, [r7, #4] - 80074f8: 681b ldr r3, [r3, #0] - 80074fa: f422 6280 bic.w r2, r2, #1024 ; 0x400 - 80074fe: b292 uxth r2, r2 - 8007500: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007e64: 687b ldr r3, [r7, #4] + 8007e66: 681b ldr r3, [r3, #0] + 8007e68: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007e6c: b29a uxth r2, r3 + 8007e6e: 687b ldr r3, [r7, #4] + 8007e70: 681b ldr r3, [r3, #0] + 8007e72: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8007e76: b292 uxth r2, r2 + 8007e78: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResetCallback(hpcd); #else HAL_PCD_ResetCallback(hpcd); - 8007504: 6878 ldr r0, [r7, #4] - 8007506: f009 f836 bl 8010576 + 8007e7c: 6878 ldr r0, [r7, #4] + 8007e7e: f00a fda8 bl 80129d2 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ (void)HAL_PCD_SetAddress(hpcd, 0U); - 800750a: 2100 movs r1, #0 - 800750c: 6878 ldr r0, [r7, #4] - 800750e: f000 f8fc bl 800770a + 8007e82: 2100 movs r1, #0 + 8007e84: 6878 ldr r0, [r7, #4] + 8007e86: f000 f8fc bl 8008082 return; - 8007512: e0f7 b.n 8007704 + 8007e8a: e0f7 b.n 800807c } if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) - 8007514: 68fb ldr r3, [r7, #12] - 8007516: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800751a: 2b00 cmp r3, #0 - 800751c: d00c beq.n 8007538 + 8007e8c: 68fb ldr r3, [r7, #12] + 8007e8e: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8007e92: 2b00 cmp r3, #0 + 8007e94: d00c beq.n 8007eb0 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); - 800751e: 687b ldr r3, [r7, #4] - 8007520: 681b ldr r3, [r3, #0] - 8007522: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 8007526: b29a uxth r2, r3 - 8007528: 687b ldr r3, [r7, #4] - 800752a: 681b ldr r3, [r3, #0] - 800752c: f422 4280 bic.w r2, r2, #16384 ; 0x4000 - 8007530: b292 uxth r2, r2 - 8007532: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007e96: 687b ldr r3, [r7, #4] + 8007e98: 681b ldr r3, [r3, #0] + 8007e9a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007e9e: b29a uxth r2, r3 + 8007ea0: 687b ldr r3, [r7, #4] + 8007ea2: 681b ldr r3, [r3, #0] + 8007ea4: f422 4280 bic.w r2, r2, #16384 ; 0x4000 + 8007ea8: b292 uxth r2, r2 + 8007eaa: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 return; - 8007536: e0e5 b.n 8007704 + 8007eae: e0e5 b.n 800807c } if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) - 8007538: 68fb ldr r3, [r7, #12] - 800753a: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 800753e: 2b00 cmp r3, #0 - 8007540: d00c beq.n 800755c + 8007eb0: 68fb ldr r3, [r7, #12] + 8007eb2: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8007eb6: 2b00 cmp r3, #0 + 8007eb8: d00c beq.n 8007ed4 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - 8007542: 687b ldr r3, [r7, #4] - 8007544: 681b ldr r3, [r3, #0] - 8007546: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 800754a: b29a uxth r2, r3 - 800754c: 687b ldr r3, [r7, #4] - 800754e: 681b ldr r3, [r3, #0] - 8007550: f422 5200 bic.w r2, r2, #8192 ; 0x2000 - 8007554: b292 uxth r2, r2 - 8007556: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007eba: 687b ldr r3, [r7, #4] + 8007ebc: 681b ldr r3, [r3, #0] + 8007ebe: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007ec2: b29a uxth r2, r3 + 8007ec4: 687b ldr r3, [r7, #4] + 8007ec6: 681b ldr r3, [r3, #0] + 8007ec8: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8007ecc: b292 uxth r2, r2 + 8007ece: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 return; - 800755a: e0d3 b.n 8007704 + 8007ed2: e0d3 b.n 800807c } if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) - 800755c: 68fb ldr r3, [r7, #12] - 800755e: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8007562: 2b00 cmp r3, #0 - 8007564: d034 beq.n 80075d0 + 8007ed4: 68fb ldr r3, [r7, #12] + 8007ed6: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8007eda: 2b00 cmp r3, #0 + 8007edc: d034 beq.n 8007f48 { hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE); - 8007566: 687b ldr r3, [r7, #4] - 8007568: 681b ldr r3, [r3, #0] - 800756a: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 800756e: b29a uxth r2, r3 - 8007570: 687b ldr r3, [r7, #4] - 8007572: 681b ldr r3, [r3, #0] - 8007574: f022 0204 bic.w r2, r2, #4 - 8007578: b292 uxth r2, r2 - 800757a: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007ede: 687b ldr r3, [r7, #4] + 8007ee0: 681b ldr r3, [r3, #0] + 8007ee2: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007ee6: b29a uxth r2, r3 + 8007ee8: 687b ldr r3, [r7, #4] + 8007eea: 681b ldr r3, [r3, #0] + 8007eec: f022 0204 bic.w r2, r2, #4 + 8007ef0: b292 uxth r2, r2 + 8007ef2: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); - 800757e: 687b ldr r3, [r7, #4] - 8007580: 681b ldr r3, [r3, #0] - 8007582: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 8007586: b29a uxth r2, r3 - 8007588: 687b ldr r3, [r7, #4] - 800758a: 681b ldr r3, [r3, #0] - 800758c: f022 0208 bic.w r2, r2, #8 - 8007590: b292 uxth r2, r2 - 8007592: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007ef6: 687b ldr r3, [r7, #4] + 8007ef8: 681b ldr r3, [r3, #0] + 8007efa: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007efe: b29a uxth r2, r3 + 8007f00: 687b ldr r3, [r7, #4] + 8007f02: 681b ldr r3, [r3, #0] + 8007f04: f022 0208 bic.w r2, r2, #8 + 8007f08: b292 uxth r2, r2 + 8007f0a: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 if (hpcd->LPM_State == LPM_L1) - 8007596: 687b ldr r3, [r7, #4] - 8007598: f893 32e0 ldrb.w r3, [r3, #736] ; 0x2e0 - 800759c: 2b01 cmp r3, #1 - 800759e: d107 bne.n 80075b0 + 8007f0e: 687b ldr r3, [r7, #4] + 8007f10: f893 32e0 ldrb.w r3, [r3, #736] ; 0x2e0 + 8007f14: 2b01 cmp r3, #1 + 8007f16: d107 bne.n 8007f28 { hpcd->LPM_State = LPM_L0; - 80075a0: 687b ldr r3, [r7, #4] - 80075a2: 2200 movs r2, #0 - 80075a4: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 + 8007f18: 687b ldr r3, [r7, #4] + 8007f1a: 2200 movs r2, #0 + 8007f1c: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - 80075a8: 2100 movs r1, #0 - 80075aa: 6878 ldr r0, [r7, #4] - 80075ac: f009 fa6e bl 8010a8c + 8007f20: 2100 movs r1, #0 + 8007f22: 6878 ldr r0, [r7, #4] + 8007f24: f00b f806 bl 8012f34 } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ResumeCallback(hpcd); #else HAL_PCD_ResumeCallback(hpcd); - 80075b0: 6878 ldr r0, [r7, #4] - 80075b2: f009 f819 bl 80105e8 + 8007f28: 6878 ldr r0, [r7, #4] + 8007f2a: f00a fd8b bl 8012a44 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - 80075b6: 687b ldr r3, [r7, #4] - 80075b8: 681b ldr r3, [r3, #0] - 80075ba: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 80075be: b29a uxth r2, r3 - 80075c0: 687b ldr r3, [r7, #4] - 80075c2: 681b ldr r3, [r3, #0] - 80075c4: f422 5280 bic.w r2, r2, #4096 ; 0x1000 - 80075c8: b292 uxth r2, r2 - 80075ca: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007f2e: 687b ldr r3, [r7, #4] + 8007f30: 681b ldr r3, [r3, #0] + 8007f32: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007f36: b29a uxth r2, r3 + 8007f38: 687b ldr r3, [r7, #4] + 8007f3a: 681b ldr r3, [r3, #0] + 8007f3c: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8007f40: b292 uxth r2, r2 + 8007f42: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 return; - 80075ce: e099 b.n 8007704 + 8007f46: e099 b.n 800807c } if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) - 80075d0: 68fb ldr r3, [r7, #12] - 80075d2: f403 6300 and.w r3, r3, #2048 ; 0x800 - 80075d6: 2b00 cmp r3, #0 - 80075d8: d027 beq.n 800762a + 8007f48: 68fb ldr r3, [r7, #12] + 8007f4a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8007f4e: 2b00 cmp r3, #0 + 8007f50: d027 beq.n 8007fa2 { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; - 80075da: 687b ldr r3, [r7, #4] - 80075dc: 681b ldr r3, [r3, #0] - 80075de: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 80075e2: b29a uxth r2, r3 - 80075e4: 687b ldr r3, [r7, #4] - 80075e6: 681b ldr r3, [r3, #0] - 80075e8: f042 0208 orr.w r2, r2, #8 - 80075ec: b292 uxth r2, r2 - 80075ee: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007f52: 687b ldr r3, [r7, #4] + 8007f54: 681b ldr r3, [r3, #0] + 8007f56: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007f5a: b29a uxth r2, r3 + 8007f5c: 687b ldr r3, [r7, #4] + 8007f5e: 681b ldr r3, [r3, #0] + 8007f60: f042 0208 orr.w r2, r2, #8 + 8007f64: b292 uxth r2, r2 + 8007f66: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - 80075f2: 687b ldr r3, [r7, #4] - 80075f4: 681b ldr r3, [r3, #0] - 80075f6: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 80075fa: b29a uxth r2, r3 - 80075fc: 687b ldr r3, [r7, #4] - 80075fe: 681b ldr r3, [r3, #0] - 8007600: f422 6200 bic.w r2, r2, #2048 ; 0x800 - 8007604: b292 uxth r2, r2 - 8007606: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007f6a: 687b ldr r3, [r7, #4] + 8007f6c: 681b ldr r3, [r3, #0] + 8007f6e: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007f72: b29a uxth r2, r3 + 8007f74: 687b ldr r3, [r7, #4] + 8007f76: 681b ldr r3, [r3, #0] + 8007f78: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8007f7c: b292 uxth r2, r2 + 8007f7e: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; - 800760a: 687b ldr r3, [r7, #4] - 800760c: 681b ldr r3, [r3, #0] - 800760e: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 8007612: b29a uxth r2, r3 - 8007614: 687b ldr r3, [r7, #4] - 8007616: 681b ldr r3, [r3, #0] - 8007618: f042 0204 orr.w r2, r2, #4 - 800761c: b292 uxth r2, r2 - 800761e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007f82: 687b ldr r3, [r7, #4] + 8007f84: 681b ldr r3, [r3, #0] + 8007f86: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007f8a: b29a uxth r2, r3 + 8007f8c: 687b ldr r3, [r7, #4] + 8007f8e: 681b ldr r3, [r3, #0] + 8007f90: f042 0204 orr.w r2, r2, #4 + 8007f94: b292 uxth r2, r2 + 8007f96: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SuspendCallback(hpcd); #else HAL_PCD_SuspendCallback(hpcd); - 8007622: 6878 ldr r0, [r7, #4] - 8007624: f008 ffc6 bl 80105b4 + 8007f9a: 6878 ldr r0, [r7, #4] + 8007f9c: f00a fd38 bl 8012a10 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; - 8007628: e06c b.n 8007704 + 8007fa0: e06c b.n 800807c } /* Handle LPM Interrupt */ if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) - 800762a: 68fb ldr r3, [r7, #12] - 800762c: f003 0380 and.w r3, r3, #128 ; 0x80 - 8007630: 2b00 cmp r3, #0 - 8007632: d040 beq.n 80076b6 + 8007fa2: 68fb ldr r3, [r7, #12] + 8007fa4: f003 0380 and.w r3, r3, #128 ; 0x80 + 8007fa8: 2b00 cmp r3, #0 + 8007faa: d040 beq.n 800802e { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - 8007634: 687b ldr r3, [r7, #4] - 8007636: 681b ldr r3, [r3, #0] - 8007638: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 800763c: b29a uxth r2, r3 - 800763e: 687b ldr r3, [r7, #4] - 8007640: 681b ldr r3, [r3, #0] - 8007642: f022 0280 bic.w r2, r2, #128 ; 0x80 - 8007646: b292 uxth r2, r2 - 8007648: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8007fac: 687b ldr r3, [r7, #4] + 8007fae: 681b ldr r3, [r3, #0] + 8007fb0: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8007fb4: b29a uxth r2, r3 + 8007fb6: 687b ldr r3, [r7, #4] + 8007fb8: 681b ldr r3, [r3, #0] + 8007fba: f022 0280 bic.w r2, r2, #128 ; 0x80 + 8007fbe: b292 uxth r2, r2 + 8007fc0: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 if (hpcd->LPM_State == LPM_L0) - 800764c: 687b ldr r3, [r7, #4] - 800764e: f893 32e0 ldrb.w r3, [r3, #736] ; 0x2e0 - 8007652: 2b00 cmp r3, #0 - 8007654: d12b bne.n 80076ae + 8007fc4: 687b ldr r3, [r7, #4] + 8007fc6: f893 32e0 ldrb.w r3, [r3, #736] ; 0x2e0 + 8007fca: 2b00 cmp r3, #0 + 8007fcc: d12b bne.n 8008026 { /* Force suspend and low-power mode before going to L1 state*/ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; - 8007656: 687b ldr r3, [r7, #4] - 8007658: 681b ldr r3, [r3, #0] - 800765a: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 800765e: b29a uxth r2, r3 - 8007660: 687b ldr r3, [r7, #4] - 8007662: 681b ldr r3, [r3, #0] - 8007664: f042 0204 orr.w r2, r2, #4 - 8007668: b292 uxth r2, r2 - 800766a: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007fce: 687b ldr r3, [r7, #4] + 8007fd0: 681b ldr r3, [r3, #0] + 8007fd2: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007fd6: b29a uxth r2, r3 + 8007fd8: 687b ldr r3, [r7, #4] + 8007fda: 681b ldr r3, [r3, #0] + 8007fdc: f042 0204 orr.w r2, r2, #4 + 8007fe0: b292 uxth r2, r2 + 8007fe2: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; - 800766e: 687b ldr r3, [r7, #4] - 8007670: 681b ldr r3, [r3, #0] - 8007672: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 8007676: b29a uxth r2, r3 - 8007678: 687b ldr r3, [r7, #4] - 800767a: 681b ldr r3, [r3, #0] - 800767c: f042 0208 orr.w r2, r2, #8 - 8007680: b292 uxth r2, r2 - 8007682: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 8007fe6: 687b ldr r3, [r7, #4] + 8007fe8: 681b ldr r3, [r3, #0] + 8007fea: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 8007fee: b29a uxth r2, r3 + 8007ff0: 687b ldr r3, [r7, #4] + 8007ff2: 681b ldr r3, [r3, #0] + 8007ff4: f042 0208 orr.w r2, r2, #8 + 8007ff8: b292 uxth r2, r2 + 8007ffa: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 hpcd->LPM_State = LPM_L1; - 8007686: 687b ldr r3, [r7, #4] - 8007688: 2201 movs r2, #1 - 800768a: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 + 8007ffe: 687b ldr r3, [r7, #4] + 8008000: 2201 movs r2, #1 + 8008002: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; - 800768e: 687b ldr r3, [r7, #4] - 8007690: 681b ldr r3, [r3, #0] - 8007692: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 - 8007696: b29b uxth r3, r3 - 8007698: 089b lsrs r3, r3, #2 - 800769a: f003 023c and.w r2, r3, #60 ; 0x3c - 800769e: 687b ldr r3, [r7, #4] - 80076a0: f8c3 22e4 str.w r2, [r3, #740] ; 0x2e4 + 8008006: 687b ldr r3, [r7, #4] + 8008008: 681b ldr r3, [r3, #0] + 800800a: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 + 800800e: b29b uxth r3, r3 + 8008010: 089b lsrs r3, r3, #2 + 8008012: f003 023c and.w r2, r3, #60 ; 0x3c + 8008016: 687b ldr r3, [r7, #4] + 8008018: f8c3 22e4 str.w r2, [r3, #740] ; 0x2e4 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); #else HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - 80076a4: 2101 movs r1, #1 - 80076a6: 6878 ldr r0, [r7, #4] - 80076a8: f009 f9f0 bl 8010a8c + 800801c: 2101 movs r1, #1 + 800801e: 6878 ldr r0, [r7, #4] + 8008020: f00a ff88 bl 8012f34 #else HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } return; - 80076ac: e02a b.n 8007704 + 8008024: e02a b.n 800807c HAL_PCD_SuspendCallback(hpcd); - 80076ae: 6878 ldr r0, [r7, #4] - 80076b0: f008 ff80 bl 80105b4 + 8008026: 6878 ldr r0, [r7, #4] + 8008028: f00a fcf2 bl 8012a10 return; - 80076b4: e026 b.n 8007704 + 800802c: e026 b.n 800807c } if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) - 80076b6: 68fb ldr r3, [r7, #12] - 80076b8: f403 7300 and.w r3, r3, #512 ; 0x200 - 80076bc: 2b00 cmp r3, #0 - 80076be: d00f beq.n 80076e0 + 800802e: 68fb ldr r3, [r7, #12] + 8008030: f403 7300 and.w r3, r3, #512 ; 0x200 + 8008034: 2b00 cmp r3, #0 + 8008036: d00f beq.n 8008058 { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - 80076c0: 687b ldr r3, [r7, #4] - 80076c2: 681b ldr r3, [r3, #0] - 80076c4: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 80076c8: b29a uxth r2, r3 - 80076ca: 687b ldr r3, [r7, #4] - 80076cc: 681b ldr r3, [r3, #0] - 80076ce: f422 7200 bic.w r2, r2, #512 ; 0x200 - 80076d2: b292 uxth r2, r2 - 80076d4: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8008038: 687b ldr r3, [r7, #4] + 800803a: 681b ldr r3, [r3, #0] + 800803c: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8008040: b29a uxth r2, r3 + 8008042: 687b ldr r3, [r7, #4] + 8008044: 681b ldr r3, [r3, #0] + 8008046: f422 7200 bic.w r2, r2, #512 ; 0x200 + 800804a: b292 uxth r2, r2 + 800804c: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else HAL_PCD_SOFCallback(hpcd); - 80076d8: 6878 ldr r0, [r7, #4] - 80076da: f008 ff3e bl 801055a + 8008050: 6878 ldr r0, [r7, #4] + 8008052: f00a fcb0 bl 80129b6 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ return; - 80076de: e011 b.n 8007704 + 8008056: e011 b.n 800807c } if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) - 80076e0: 68fb ldr r3, [r7, #12] - 80076e2: f403 7380 and.w r3, r3, #256 ; 0x100 - 80076e6: 2b00 cmp r3, #0 - 80076e8: d00c beq.n 8007704 + 8008058: 68fb ldr r3, [r7, #12] + 800805a: f403 7380 and.w r3, r3, #256 ; 0x100 + 800805e: 2b00 cmp r3, #0 + 8008060: d00c beq.n 800807c { /* clear ESOF flag in ISTR */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - 80076ea: 687b ldr r3, [r7, #4] - 80076ec: 681b ldr r3, [r3, #0] - 80076ee: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 80076f2: b29a uxth r2, r3 - 80076f4: 687b ldr r3, [r7, #4] - 80076f6: 681b ldr r3, [r3, #0] - 80076f8: f422 7280 bic.w r2, r2, #256 ; 0x100 - 80076fc: b292 uxth r2, r2 - 80076fe: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 8008062: 687b ldr r3, [r7, #4] + 8008064: 681b ldr r3, [r3, #0] + 8008066: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 800806a: b29a uxth r2, r3 + 800806c: 687b ldr r3, [r7, #4] + 800806e: 681b ldr r3, [r3, #0] + 8008070: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8008074: b292 uxth r2, r2 + 8008076: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 return; - 8007702: bf00 nop + 800807a: bf00 nop } } - 8007704: 3710 adds r7, #16 - 8007706: 46bd mov sp, r7 - 8007708: bd80 pop {r7, pc} + 800807c: 3710 adds r7, #16 + 800807e: 46bd mov sp, r7 + 8008080: bd80 pop {r7, pc} -0800770a : +08008082 : * @param hpcd PCD handle * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { - 800770a: b580 push {r7, lr} - 800770c: b082 sub sp, #8 - 800770e: af00 add r7, sp, #0 - 8007710: 6078 str r0, [r7, #4] - 8007712: 460b mov r3, r1 - 8007714: 70fb strb r3, [r7, #3] + 8008082: b580 push {r7, lr} + 8008084: b082 sub sp, #8 + 8008086: af00 add r7, sp, #0 + 8008088: 6078 str r0, [r7, #4] + 800808a: 460b mov r3, r1 + 800808c: 70fb strb r3, [r7, #3] __HAL_LOCK(hpcd); - 8007716: 687b ldr r3, [r7, #4] - 8007718: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 800771c: 2b01 cmp r3, #1 - 800771e: d101 bne.n 8007724 - 8007720: 2302 movs r3, #2 - 8007722: e013 b.n 800774c - 8007724: 687b ldr r3, [r7, #4] - 8007726: 2201 movs r2, #1 - 8007728: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 800808e: 687b ldr r3, [r7, #4] + 8008090: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8008094: 2b01 cmp r3, #1 + 8008096: d101 bne.n 800809c + 8008098: 2302 movs r3, #2 + 800809a: e013 b.n 80080c4 + 800809c: 687b ldr r3, [r7, #4] + 800809e: 2201 movs r2, #1 + 80080a0: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 hpcd->USB_Address = address; - 800772c: 687b ldr r3, [r7, #4] - 800772e: 78fa ldrb r2, [r7, #3] - 8007730: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 80080a4: 687b ldr r3, [r7, #4] + 80080a6: 78fa ldrb r2, [r7, #3] + 80080a8: f883 2024 strb.w r2, [r3, #36] ; 0x24 (void)USB_SetDevAddress(hpcd->Instance, address); - 8007734: 687b ldr r3, [r7, #4] - 8007736: 681b ldr r3, [r3, #0] - 8007738: 78fa ldrb r2, [r7, #3] - 800773a: 4611 mov r1, r2 - 800773c: 4618 mov r0, r3 - 800773e: f006 ffce bl 800e6de + 80080ac: 687b ldr r3, [r7, #4] + 80080ae: 681b ldr r3, [r3, #0] + 80080b0: 78fa ldrb r2, [r7, #3] + 80080b2: 4611 mov r1, r2 + 80080b4: 4618 mov r0, r3 + 80080b6: f007 fc6a bl 800f98e __HAL_UNLOCK(hpcd); - 8007742: 687b ldr r3, [r7, #4] - 8007744: 2200 movs r2, #0 - 8007746: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 80080ba: 687b ldr r3, [r7, #4] + 80080bc: 2200 movs r2, #0 + 80080be: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return HAL_OK; - 800774a: 2300 movs r3, #0 + 80080c2: 2300 movs r3, #0 } - 800774c: 4618 mov r0, r3 - 800774e: 3708 adds r7, #8 - 8007750: 46bd mov sp, r7 - 8007752: bd80 pop {r7, pc} + 80080c4: 4618 mov r0, r3 + 80080c6: 3708 adds r7, #8 + 80080c8: 46bd mov sp, r7 + 80080ca: bd80 pop {r7, pc} -08007754 : +080080cc : * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - 8007754: b580 push {r7, lr} - 8007756: b084 sub sp, #16 - 8007758: af00 add r7, sp, #0 - 800775a: 6078 str r0, [r7, #4] - 800775c: 4608 mov r0, r1 - 800775e: 4611 mov r1, r2 - 8007760: 461a mov r2, r3 - 8007762: 4603 mov r3, r0 - 8007764: 70fb strb r3, [r7, #3] - 8007766: 460b mov r3, r1 - 8007768: 803b strh r3, [r7, #0] - 800776a: 4613 mov r3, r2 - 800776c: 70bb strb r3, [r7, #2] + 80080cc: b580 push {r7, lr} + 80080ce: b084 sub sp, #16 + 80080d0: af00 add r7, sp, #0 + 80080d2: 6078 str r0, [r7, #4] + 80080d4: 4608 mov r0, r1 + 80080d6: 4611 mov r1, r2 + 80080d8: 461a mov r2, r3 + 80080da: 4603 mov r3, r0 + 80080dc: 70fb strb r3, [r7, #3] + 80080de: 460b mov r3, r1 + 80080e0: 803b strh r3, [r7, #0] + 80080e2: 4613 mov r3, r2 + 80080e4: 70bb strb r3, [r7, #2] HAL_StatusTypeDef ret = HAL_OK; - 800776e: 2300 movs r3, #0 - 8007770: 72fb strb r3, [r7, #11] + 80080e6: 2300 movs r3, #0 + 80080e8: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) - 8007772: f997 3003 ldrsb.w r3, [r7, #3] - 8007776: 2b00 cmp r3, #0 - 8007778: da0e bge.n 8007798 + 80080ea: f997 3003 ldrsb.w r3, [r7, #3] + 80080ee: 2b00 cmp r3, #0 + 80080f0: da0e bge.n 8008110 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 800777a: 78fb ldrb r3, [r7, #3] - 800777c: f003 0307 and.w r3, r3, #7 - 8007780: 1c5a adds r2, r3, #1 - 8007782: 4613 mov r3, r2 - 8007784: 009b lsls r3, r3, #2 - 8007786: 4413 add r3, r2 - 8007788: 00db lsls r3, r3, #3 - 800778a: 687a ldr r2, [r7, #4] - 800778c: 4413 add r3, r2 - 800778e: 60fb str r3, [r7, #12] + 80080f2: 78fb ldrb r3, [r7, #3] + 80080f4: f003 0307 and.w r3, r3, #7 + 80080f8: 1c5a adds r2, r3, #1 + 80080fa: 4613 mov r3, r2 + 80080fc: 009b lsls r3, r3, #2 + 80080fe: 4413 add r3, r2 + 8008100: 00db lsls r3, r3, #3 + 8008102: 687a ldr r2, [r7, #4] + 8008104: 4413 add r3, r2 + 8008106: 60fb str r3, [r7, #12] ep->is_in = 1U; - 8007790: 68fb ldr r3, [r7, #12] - 8007792: 2201 movs r2, #1 - 8007794: 705a strb r2, [r3, #1] - 8007796: e00e b.n 80077b6 + 8008108: 68fb ldr r3, [r7, #12] + 800810a: 2201 movs r2, #1 + 800810c: 705a strb r2, [r3, #1] + 800810e: e00e b.n 800812e } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - 8007798: 78fb ldrb r3, [r7, #3] - 800779a: f003 0207 and.w r2, r3, #7 - 800779e: 4613 mov r3, r2 - 80077a0: 009b lsls r3, r3, #2 - 80077a2: 4413 add r3, r2 - 80077a4: 00db lsls r3, r3, #3 - 80077a6: f503 73b4 add.w r3, r3, #360 ; 0x168 - 80077aa: 687a ldr r2, [r7, #4] - 80077ac: 4413 add r3, r2 - 80077ae: 60fb str r3, [r7, #12] + 8008110: 78fb ldrb r3, [r7, #3] + 8008112: f003 0207 and.w r2, r3, #7 + 8008116: 4613 mov r3, r2 + 8008118: 009b lsls r3, r3, #2 + 800811a: 4413 add r3, r2 + 800811c: 00db lsls r3, r3, #3 + 800811e: f503 73b4 add.w r3, r3, #360 ; 0x168 + 8008122: 687a ldr r2, [r7, #4] + 8008124: 4413 add r3, r2 + 8008126: 60fb str r3, [r7, #12] ep->is_in = 0U; - 80077b0: 68fb ldr r3, [r7, #12] - 80077b2: 2200 movs r2, #0 - 80077b4: 705a strb r2, [r3, #1] + 8008128: 68fb ldr r3, [r7, #12] + 800812a: 2200 movs r2, #0 + 800812c: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; - 80077b6: 78fb ldrb r3, [r7, #3] - 80077b8: f003 0307 and.w r3, r3, #7 - 80077bc: b2da uxtb r2, r3 - 80077be: 68fb ldr r3, [r7, #12] - 80077c0: 701a strb r2, [r3, #0] + 800812e: 78fb ldrb r3, [r7, #3] + 8008130: f003 0307 and.w r3, r3, #7 + 8008134: b2da uxtb r2, r3 + 8008136: 68fb ldr r3, [r7, #12] + 8008138: 701a strb r2, [r3, #0] ep->maxpacket = ep_mps; - 80077c2: 883a ldrh r2, [r7, #0] - 80077c4: 68fb ldr r3, [r7, #12] - 80077c6: 611a str r2, [r3, #16] + 800813a: 883a ldrh r2, [r7, #0] + 800813c: 68fb ldr r3, [r7, #12] + 800813e: 611a str r2, [r3, #16] ep->type = ep_type; - 80077c8: 68fb ldr r3, [r7, #12] - 80077ca: 78ba ldrb r2, [r7, #2] - 80077cc: 70da strb r2, [r3, #3] + 8008140: 68fb ldr r3, [r7, #12] + 8008142: 78ba ldrb r2, [r7, #2] + 8008144: 70da strb r2, [r3, #3] ep->tx_fifo_num = ep->num; } #endif /* defined (USB_OTG_FS) */ /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) - 80077ce: 78bb ldrb r3, [r7, #2] - 80077d0: 2b02 cmp r3, #2 - 80077d2: d102 bne.n 80077da + 8008146: 78bb ldrb r3, [r7, #2] + 8008148: 2b02 cmp r3, #2 + 800814a: d102 bne.n 8008152 { ep->data_pid_start = 0U; - 80077d4: 68fb ldr r3, [r7, #12] - 80077d6: 2200 movs r2, #0 - 80077d8: 711a strb r2, [r3, #4] + 800814c: 68fb ldr r3, [r7, #12] + 800814e: 2200 movs r2, #0 + 8008150: 711a strb r2, [r3, #4] } __HAL_LOCK(hpcd); - 80077da: 687b ldr r3, [r7, #4] - 80077dc: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 80077e0: 2b01 cmp r3, #1 - 80077e2: d101 bne.n 80077e8 - 80077e4: 2302 movs r3, #2 - 80077e6: e00e b.n 8007806 - 80077e8: 687b ldr r3, [r7, #4] - 80077ea: 2201 movs r2, #1 - 80077ec: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8008152: 687b ldr r3, [r7, #4] + 8008154: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8008158: 2b01 cmp r3, #1 + 800815a: d101 bne.n 8008160 + 800815c: 2302 movs r3, #2 + 800815e: e00e b.n 800817e + 8008160: 687b ldr r3, [r7, #4] + 8008162: 2201 movs r2, #1 + 8008164: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 (void)USB_ActivateEndpoint(hpcd->Instance, ep); - 80077f0: 687b ldr r3, [r7, #4] - 80077f2: 681b ldr r3, [r3, #0] - 80077f4: 68f9 ldr r1, [r7, #12] - 80077f6: 4618 mov r0, r3 - 80077f8: f004 fd10 bl 800c21c + 8008168: 687b ldr r3, [r7, #4] + 800816a: 681b ldr r3, [r3, #0] + 800816c: 68f9 ldr r1, [r7, #12] + 800816e: 4618 mov r0, r3 + 8008170: f005 f9ac bl 800d4cc __HAL_UNLOCK(hpcd); - 80077fc: 687b ldr r3, [r7, #4] - 80077fe: 2200 movs r2, #0 - 8007800: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8008174: 687b ldr r3, [r7, #4] + 8008176: 2200 movs r2, #0 + 8008178: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return ret; - 8007804: 7afb ldrb r3, [r7, #11] + 800817c: 7afb ldrb r3, [r7, #11] } - 8007806: 4618 mov r0, r3 - 8007808: 3710 adds r7, #16 - 800780a: 46bd mov sp, r7 - 800780c: bd80 pop {r7, pc} + 800817e: 4618 mov r0, r3 + 8008180: 3710 adds r7, #16 + 8008182: 46bd mov sp, r7 + 8008184: bd80 pop {r7, pc} -0800780e : +08008186 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - 800780e: b580 push {r7, lr} - 8007810: b084 sub sp, #16 - 8007812: af00 add r7, sp, #0 - 8007814: 6078 str r0, [r7, #4] - 8007816: 460b mov r3, r1 - 8007818: 70fb strb r3, [r7, #3] + 8008186: b580 push {r7, lr} + 8008188: b084 sub sp, #16 + 800818a: af00 add r7, sp, #0 + 800818c: 6078 str r0, [r7, #4] + 800818e: 460b mov r3, r1 + 8008190: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) - 800781a: f997 3003 ldrsb.w r3, [r7, #3] - 800781e: 2b00 cmp r3, #0 - 8007820: da0e bge.n 8007840 + 8008192: f997 3003 ldrsb.w r3, [r7, #3] + 8008196: 2b00 cmp r3, #0 + 8008198: da0e bge.n 80081b8 { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 8007822: 78fb ldrb r3, [r7, #3] - 8007824: f003 0307 and.w r3, r3, #7 - 8007828: 1c5a adds r2, r3, #1 - 800782a: 4613 mov r3, r2 - 800782c: 009b lsls r3, r3, #2 - 800782e: 4413 add r3, r2 - 8007830: 00db lsls r3, r3, #3 - 8007832: 687a ldr r2, [r7, #4] - 8007834: 4413 add r3, r2 - 8007836: 60fb str r3, [r7, #12] + 800819a: 78fb ldrb r3, [r7, #3] + 800819c: f003 0307 and.w r3, r3, #7 + 80081a0: 1c5a adds r2, r3, #1 + 80081a2: 4613 mov r3, r2 + 80081a4: 009b lsls r3, r3, #2 + 80081a6: 4413 add r3, r2 + 80081a8: 00db lsls r3, r3, #3 + 80081aa: 687a ldr r2, [r7, #4] + 80081ac: 4413 add r3, r2 + 80081ae: 60fb str r3, [r7, #12] ep->is_in = 1U; - 8007838: 68fb ldr r3, [r7, #12] - 800783a: 2201 movs r2, #1 - 800783c: 705a strb r2, [r3, #1] - 800783e: e00e b.n 800785e + 80081b0: 68fb ldr r3, [r7, #12] + 80081b2: 2201 movs r2, #1 + 80081b4: 705a strb r2, [r3, #1] + 80081b6: e00e b.n 80081d6 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - 8007840: 78fb ldrb r3, [r7, #3] - 8007842: f003 0207 and.w r2, r3, #7 - 8007846: 4613 mov r3, r2 - 8007848: 009b lsls r3, r3, #2 - 800784a: 4413 add r3, r2 - 800784c: 00db lsls r3, r3, #3 - 800784e: f503 73b4 add.w r3, r3, #360 ; 0x168 - 8007852: 687a ldr r2, [r7, #4] - 8007854: 4413 add r3, r2 - 8007856: 60fb str r3, [r7, #12] + 80081b8: 78fb ldrb r3, [r7, #3] + 80081ba: f003 0207 and.w r2, r3, #7 + 80081be: 4613 mov r3, r2 + 80081c0: 009b lsls r3, r3, #2 + 80081c2: 4413 add r3, r2 + 80081c4: 00db lsls r3, r3, #3 + 80081c6: f503 73b4 add.w r3, r3, #360 ; 0x168 + 80081ca: 687a ldr r2, [r7, #4] + 80081cc: 4413 add r3, r2 + 80081ce: 60fb str r3, [r7, #12] ep->is_in = 0U; - 8007858: 68fb ldr r3, [r7, #12] - 800785a: 2200 movs r2, #0 - 800785c: 705a strb r2, [r3, #1] + 80081d0: 68fb ldr r3, [r7, #12] + 80081d2: 2200 movs r2, #0 + 80081d4: 705a strb r2, [r3, #1] } ep->num = ep_addr & EP_ADDR_MSK; - 800785e: 78fb ldrb r3, [r7, #3] - 8007860: f003 0307 and.w r3, r3, #7 - 8007864: b2da uxtb r2, r3 - 8007866: 68fb ldr r3, [r7, #12] - 8007868: 701a strb r2, [r3, #0] + 80081d6: 78fb ldrb r3, [r7, #3] + 80081d8: f003 0307 and.w r3, r3, #7 + 80081dc: b2da uxtb r2, r3 + 80081de: 68fb ldr r3, [r7, #12] + 80081e0: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); - 800786a: 687b ldr r3, [r7, #4] - 800786c: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 8007870: 2b01 cmp r3, #1 - 8007872: d101 bne.n 8007878 - 8007874: 2302 movs r3, #2 - 8007876: e00e b.n 8007896 - 8007878: 687b ldr r3, [r7, #4] - 800787a: 2201 movs r2, #1 - 800787c: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 80081e2: 687b ldr r3, [r7, #4] + 80081e4: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 80081e8: 2b01 cmp r3, #1 + 80081ea: d101 bne.n 80081f0 + 80081ec: 2302 movs r3, #2 + 80081ee: e00e b.n 800820e + 80081f0: 687b ldr r3, [r7, #4] + 80081f2: 2201 movs r2, #1 + 80081f4: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 (void)USB_DeactivateEndpoint(hpcd->Instance, ep); - 8007880: 687b ldr r3, [r7, #4] - 8007882: 681b ldr r3, [r3, #0] - 8007884: 68f9 ldr r1, [r7, #12] - 8007886: 4618 mov r0, r3 - 8007888: f005 f88c bl 800c9a4 + 80081f8: 687b ldr r3, [r7, #4] + 80081fa: 681b ldr r3, [r3, #0] + 80081fc: 68f9 ldr r1, [r7, #12] + 80081fe: 4618 mov r0, r3 + 8008200: f005 fd28 bl 800dc54 __HAL_UNLOCK(hpcd); - 800788c: 687b ldr r3, [r7, #4] - 800788e: 2200 movs r2, #0 - 8007890: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8008204: 687b ldr r3, [r7, #4] + 8008206: 2200 movs r2, #0 + 8008208: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return HAL_OK; - 8007894: 2300 movs r3, #0 + 800820c: 2300 movs r3, #0 } - 8007896: 4618 mov r0, r3 - 8007898: 3710 adds r7, #16 - 800789a: 46bd mov sp, r7 - 800789c: bd80 pop {r7, pc} + 800820e: 4618 mov r0, r3 + 8008210: 3710 adds r7, #16 + 8008212: 46bd mov sp, r7 + 8008214: bd80 pop {r7, pc} -0800789e : +08008216 : * @param pBuf pointer to the reception buffer * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - 800789e: b580 push {r7, lr} - 80078a0: b086 sub sp, #24 - 80078a2: af00 add r7, sp, #0 - 80078a4: 60f8 str r0, [r7, #12] - 80078a6: 607a str r2, [r7, #4] - 80078a8: 603b str r3, [r7, #0] - 80078aa: 460b mov r3, r1 - 80078ac: 72fb strb r3, [r7, #11] + 8008216: b580 push {r7, lr} + 8008218: b086 sub sp, #24 + 800821a: af00 add r7, sp, #0 + 800821c: 60f8 str r0, [r7, #12] + 800821e: 607a str r2, [r7, #4] + 8008220: 603b str r3, [r7, #0] + 8008222: 460b mov r3, r1 + 8008224: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - 80078ae: 7afb ldrb r3, [r7, #11] - 80078b0: f003 0207 and.w r2, r3, #7 - 80078b4: 4613 mov r3, r2 - 80078b6: 009b lsls r3, r3, #2 - 80078b8: 4413 add r3, r2 - 80078ba: 00db lsls r3, r3, #3 - 80078bc: f503 73b4 add.w r3, r3, #360 ; 0x168 - 80078c0: 68fa ldr r2, [r7, #12] - 80078c2: 4413 add r3, r2 - 80078c4: 617b str r3, [r7, #20] + 8008226: 7afb ldrb r3, [r7, #11] + 8008228: f003 0207 and.w r2, r3, #7 + 800822c: 4613 mov r3, r2 + 800822e: 009b lsls r3, r3, #2 + 8008230: 4413 add r3, r2 + 8008232: 00db lsls r3, r3, #3 + 8008234: f503 73b4 add.w r3, r3, #360 ; 0x168 + 8008238: 68fa ldr r2, [r7, #12] + 800823a: 4413 add r3, r2 + 800823c: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; - 80078c6: 697b ldr r3, [r7, #20] - 80078c8: 687a ldr r2, [r7, #4] - 80078ca: 615a str r2, [r3, #20] + 800823e: 697b ldr r3, [r7, #20] + 8008240: 687a ldr r2, [r7, #4] + 8008242: 615a str r2, [r3, #20] ep->xfer_len = len; - 80078cc: 697b ldr r3, [r7, #20] - 80078ce: 683a ldr r2, [r7, #0] - 80078d0: 619a str r2, [r3, #24] + 8008244: 697b ldr r3, [r7, #20] + 8008246: 683a ldr r2, [r7, #0] + 8008248: 619a str r2, [r3, #24] ep->xfer_count = 0U; - 80078d2: 697b ldr r3, [r7, #20] - 80078d4: 2200 movs r2, #0 - 80078d6: 61da str r2, [r3, #28] + 800824a: 697b ldr r3, [r7, #20] + 800824c: 2200 movs r2, #0 + 800824e: 61da str r2, [r3, #28] ep->is_in = 0U; - 80078d8: 697b ldr r3, [r7, #20] - 80078da: 2200 movs r2, #0 - 80078dc: 705a strb r2, [r3, #1] + 8008250: 697b ldr r3, [r7, #20] + 8008252: 2200 movs r2, #0 + 8008254: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; - 80078de: 7afb ldrb r3, [r7, #11] - 80078e0: f003 0307 and.w r3, r3, #7 - 80078e4: b2da uxtb r2, r3 - 80078e6: 697b ldr r3, [r7, #20] - 80078e8: 701a strb r2, [r3, #0] + 8008256: 7afb ldrb r3, [r7, #11] + 8008258: f003 0307 and.w r3, r3, #7 + 800825c: b2da uxtb r2, r3 + 800825e: 697b ldr r3, [r7, #20] + 8008260: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); - 80078ea: 68fb ldr r3, [r7, #12] - 80078ec: 681b ldr r3, [r3, #0] - 80078ee: 6979 ldr r1, [r7, #20] - 80078f0: 4618 mov r0, r3 - 80078f2: f005 fa44 bl 800cd7e + 8008262: 68fb ldr r3, [r7, #12] + 8008264: 681b ldr r3, [r3, #0] + 8008266: 6979 ldr r1, [r7, #20] + 8008268: 4618 mov r0, r3 + 800826a: f005 fee0 bl 800e02e return HAL_OK; - 80078f6: 2300 movs r3, #0 + 800826e: 2300 movs r3, #0 } - 80078f8: 4618 mov r0, r3 - 80078fa: 3718 adds r7, #24 - 80078fc: 46bd mov sp, r7 - 80078fe: bd80 pop {r7, pc} + 8008270: 4618 mov r0, r3 + 8008272: 3718 adds r7, #24 + 8008274: 46bd mov sp, r7 + 8008276: bd80 pop {r7, pc} -08007900 : +08008278 : + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + 8008278: b480 push {r7} + 800827a: b083 sub sp, #12 + 800827c: af00 add r7, sp, #0 + 800827e: 6078 str r0, [r7, #4] + 8008280: 460b mov r3, r1 + 8008282: 70fb strb r3, [r7, #3] + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; + 8008284: 78fb ldrb r3, [r7, #3] + 8008286: f003 0207 and.w r2, r3, #7 + 800828a: 6879 ldr r1, [r7, #4] + 800828c: 4613 mov r3, r2 + 800828e: 009b lsls r3, r3, #2 + 8008290: 4413 add r3, r2 + 8008292: 00db lsls r3, r3, #3 + 8008294: 440b add r3, r1 + 8008296: f503 73c2 add.w r3, r3, #388 ; 0x184 + 800829a: 681b ldr r3, [r3, #0] +} + 800829c: 4618 mov r0, r3 + 800829e: 370c adds r7, #12 + 80082a0: 46bd mov sp, r7 + 80082a2: f85d 7b04 ldr.w r7, [sp], #4 + 80082a6: 4770 bx lr + +080082a8 : * @param pBuf pointer to the transmission buffer * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { - 8007900: b580 push {r7, lr} - 8007902: b086 sub sp, #24 - 8007904: af00 add r7, sp, #0 - 8007906: 60f8 str r0, [r7, #12] - 8007908: 607a str r2, [r7, #4] - 800790a: 603b str r3, [r7, #0] - 800790c: 460b mov r3, r1 - 800790e: 72fb strb r3, [r7, #11] + 80082a8: b580 push {r7, lr} + 80082aa: b086 sub sp, #24 + 80082ac: af00 add r7, sp, #0 + 80082ae: 60f8 str r0, [r7, #12] + 80082b0: 607a str r2, [r7, #4] + 80082b2: 603b str r3, [r7, #0] + 80082b4: 460b mov r3, r1 + 80082b6: 72fb strb r3, [r7, #11] PCD_EPTypeDef *ep; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 8007910: 7afb ldrb r3, [r7, #11] - 8007912: f003 0307 and.w r3, r3, #7 - 8007916: 1c5a adds r2, r3, #1 - 8007918: 4613 mov r3, r2 - 800791a: 009b lsls r3, r3, #2 - 800791c: 4413 add r3, r2 - 800791e: 00db lsls r3, r3, #3 - 8007920: 68fa ldr r2, [r7, #12] - 8007922: 4413 add r3, r2 - 8007924: 617b str r3, [r7, #20] + 80082b8: 7afb ldrb r3, [r7, #11] + 80082ba: f003 0307 and.w r3, r3, #7 + 80082be: 1c5a adds r2, r3, #1 + 80082c0: 4613 mov r3, r2 + 80082c2: 009b lsls r3, r3, #2 + 80082c4: 4413 add r3, r2 + 80082c6: 00db lsls r3, r3, #3 + 80082c8: 68fa ldr r2, [r7, #12] + 80082ca: 4413 add r3, r2 + 80082cc: 617b str r3, [r7, #20] /*setup and start the Xfer */ ep->xfer_buff = pBuf; - 8007926: 697b ldr r3, [r7, #20] - 8007928: 687a ldr r2, [r7, #4] - 800792a: 615a str r2, [r3, #20] + 80082ce: 697b ldr r3, [r7, #20] + 80082d0: 687a ldr r2, [r7, #4] + 80082d2: 615a str r2, [r3, #20] ep->xfer_len = len; - 800792c: 697b ldr r3, [r7, #20] - 800792e: 683a ldr r2, [r7, #0] - 8007930: 619a str r2, [r3, #24] + 80082d4: 697b ldr r3, [r7, #20] + 80082d6: 683a ldr r2, [r7, #0] + 80082d8: 619a str r2, [r3, #24] #if defined (USB) ep->xfer_fill_db = 1U; - 8007932: 697b ldr r3, [r7, #20] - 8007934: 2201 movs r2, #1 - 8007936: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 80082da: 697b ldr r3, [r7, #20] + 80082dc: 2201 movs r2, #1 + 80082de: f883 2024 strb.w r2, [r3, #36] ; 0x24 ep->xfer_len_db = len; - 800793a: 697b ldr r3, [r7, #20] - 800793c: 683a ldr r2, [r7, #0] - 800793e: 621a str r2, [r3, #32] + 80082e2: 697b ldr r3, [r7, #20] + 80082e4: 683a ldr r2, [r7, #0] + 80082e6: 621a str r2, [r3, #32] #endif /* defined (USB) */ ep->xfer_count = 0U; - 8007940: 697b ldr r3, [r7, #20] - 8007942: 2200 movs r2, #0 - 8007944: 61da str r2, [r3, #28] + 80082e8: 697b ldr r3, [r7, #20] + 80082ea: 2200 movs r2, #0 + 80082ec: 61da str r2, [r3, #28] ep->is_in = 1U; - 8007946: 697b ldr r3, [r7, #20] - 8007948: 2201 movs r2, #1 - 800794a: 705a strb r2, [r3, #1] + 80082ee: 697b ldr r3, [r7, #20] + 80082f0: 2201 movs r2, #1 + 80082f2: 705a strb r2, [r3, #1] ep->num = ep_addr & EP_ADDR_MSK; - 800794c: 7afb ldrb r3, [r7, #11] - 800794e: f003 0307 and.w r3, r3, #7 - 8007952: b2da uxtb r2, r3 - 8007954: 697b ldr r3, [r7, #20] - 8007956: 701a strb r2, [r3, #0] + 80082f4: 7afb ldrb r3, [r7, #11] + 80082f6: f003 0307 and.w r3, r3, #7 + 80082fa: b2da uxtb r2, r3 + 80082fc: 697b ldr r3, [r7, #20] + 80082fe: 701a strb r2, [r3, #0] (void)USB_EPStartXfer(hpcd->Instance, ep); - 8007958: 68fb ldr r3, [r7, #12] - 800795a: 681b ldr r3, [r3, #0] - 800795c: 6979 ldr r1, [r7, #20] - 800795e: 4618 mov r0, r3 - 8007960: f005 fa0d bl 800cd7e + 8008300: 68fb ldr r3, [r7, #12] + 8008302: 681b ldr r3, [r3, #0] + 8008304: 6979 ldr r1, [r7, #20] + 8008306: 4618 mov r0, r3 + 8008308: f005 fe91 bl 800e02e return HAL_OK; - 8007964: 2300 movs r3, #0 + 800830c: 2300 movs r3, #0 } - 8007966: 4618 mov r0, r3 - 8007968: 3718 adds r7, #24 - 800796a: 46bd mov sp, r7 - 800796c: bd80 pop {r7, pc} + 800830e: 4618 mov r0, r3 + 8008310: 3718 adds r7, #24 + 8008312: 46bd mov sp, r7 + 8008314: bd80 pop {r7, pc} -0800796e : +08008316 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - 800796e: b580 push {r7, lr} - 8007970: b084 sub sp, #16 - 8007972: af00 add r7, sp, #0 - 8007974: 6078 str r0, [r7, #4] - 8007976: 460b mov r3, r1 - 8007978: 70fb strb r3, [r7, #3] + 8008316: b580 push {r7, lr} + 8008318: b084 sub sp, #16 + 800831a: af00 add r7, sp, #0 + 800831c: 6078 str r0, [r7, #4] + 800831e: 460b mov r3, r1 + 8008320: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) - 800797a: 78fb ldrb r3, [r7, #3] - 800797c: f003 0207 and.w r2, r3, #7 - 8007980: 687b ldr r3, [r7, #4] - 8007982: 685b ldr r3, [r3, #4] - 8007984: 429a cmp r2, r3 - 8007986: d901 bls.n 800798c + 8008322: 78fb ldrb r3, [r7, #3] + 8008324: f003 0207 and.w r2, r3, #7 + 8008328: 687b ldr r3, [r7, #4] + 800832a: 685b ldr r3, [r3, #4] + 800832c: 429a cmp r2, r3 + 800832e: d901 bls.n 8008334 { return HAL_ERROR; - 8007988: 2301 movs r3, #1 - 800798a: e04c b.n 8007a26 + 8008330: 2301 movs r3, #1 + 8008332: e04c b.n 80083ce } if ((0x80U & ep_addr) == 0x80U) - 800798c: f997 3003 ldrsb.w r3, [r7, #3] - 8007990: 2b00 cmp r3, #0 - 8007992: da0e bge.n 80079b2 + 8008334: f997 3003 ldrsb.w r3, [r7, #3] + 8008338: 2b00 cmp r3, #0 + 800833a: da0e bge.n 800835a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 8007994: 78fb ldrb r3, [r7, #3] - 8007996: f003 0307 and.w r3, r3, #7 - 800799a: 1c5a adds r2, r3, #1 - 800799c: 4613 mov r3, r2 - 800799e: 009b lsls r3, r3, #2 - 80079a0: 4413 add r3, r2 - 80079a2: 00db lsls r3, r3, #3 - 80079a4: 687a ldr r2, [r7, #4] - 80079a6: 4413 add r3, r2 - 80079a8: 60fb str r3, [r7, #12] + 800833c: 78fb ldrb r3, [r7, #3] + 800833e: f003 0307 and.w r3, r3, #7 + 8008342: 1c5a adds r2, r3, #1 + 8008344: 4613 mov r3, r2 + 8008346: 009b lsls r3, r3, #2 + 8008348: 4413 add r3, r2 + 800834a: 00db lsls r3, r3, #3 + 800834c: 687a ldr r2, [r7, #4] + 800834e: 4413 add r3, r2 + 8008350: 60fb str r3, [r7, #12] ep->is_in = 1U; - 80079aa: 68fb ldr r3, [r7, #12] - 80079ac: 2201 movs r2, #1 - 80079ae: 705a strb r2, [r3, #1] - 80079b0: e00c b.n 80079cc + 8008352: 68fb ldr r3, [r7, #12] + 8008354: 2201 movs r2, #1 + 8008356: 705a strb r2, [r3, #1] + 8008358: e00c b.n 8008374 } else { ep = &hpcd->OUT_ep[ep_addr]; - 80079b2: 78fa ldrb r2, [r7, #3] - 80079b4: 4613 mov r3, r2 - 80079b6: 009b lsls r3, r3, #2 - 80079b8: 4413 add r3, r2 - 80079ba: 00db lsls r3, r3, #3 - 80079bc: f503 73b4 add.w r3, r3, #360 ; 0x168 - 80079c0: 687a ldr r2, [r7, #4] - 80079c2: 4413 add r3, r2 - 80079c4: 60fb str r3, [r7, #12] + 800835a: 78fa ldrb r2, [r7, #3] + 800835c: 4613 mov r3, r2 + 800835e: 009b lsls r3, r3, #2 + 8008360: 4413 add r3, r2 + 8008362: 00db lsls r3, r3, #3 + 8008364: f503 73b4 add.w r3, r3, #360 ; 0x168 + 8008368: 687a ldr r2, [r7, #4] + 800836a: 4413 add r3, r2 + 800836c: 60fb str r3, [r7, #12] ep->is_in = 0U; - 80079c6: 68fb ldr r3, [r7, #12] - 80079c8: 2200 movs r2, #0 - 80079ca: 705a strb r2, [r3, #1] + 800836e: 68fb ldr r3, [r7, #12] + 8008370: 2200 movs r2, #0 + 8008372: 705a strb r2, [r3, #1] } ep->is_stall = 1U; - 80079cc: 68fb ldr r3, [r7, #12] - 80079ce: 2201 movs r2, #1 - 80079d0: 709a strb r2, [r3, #2] + 8008374: 68fb ldr r3, [r7, #12] + 8008376: 2201 movs r2, #1 + 8008378: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; - 80079d2: 78fb ldrb r3, [r7, #3] - 80079d4: f003 0307 and.w r3, r3, #7 - 80079d8: b2da uxtb r2, r3 - 80079da: 68fb ldr r3, [r7, #12] - 80079dc: 701a strb r2, [r3, #0] + 800837a: 78fb ldrb r3, [r7, #3] + 800837c: f003 0307 and.w r3, r3, #7 + 8008380: b2da uxtb r2, r3 + 8008382: 68fb ldr r3, [r7, #12] + 8008384: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); - 80079de: 687b ldr r3, [r7, #4] - 80079e0: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 80079e4: 2b01 cmp r3, #1 - 80079e6: d101 bne.n 80079ec - 80079e8: 2302 movs r3, #2 - 80079ea: e01c b.n 8007a26 - 80079ec: 687b ldr r3, [r7, #4] - 80079ee: 2201 movs r2, #1 - 80079f0: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 8008386: 687b ldr r3, [r7, #4] + 8008388: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 800838c: 2b01 cmp r3, #1 + 800838e: d101 bne.n 8008394 + 8008390: 2302 movs r3, #2 + 8008392: e01c b.n 80083ce + 8008394: 687b ldr r3, [r7, #4] + 8008396: 2201 movs r2, #1 + 8008398: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 (void)USB_EPSetStall(hpcd->Instance, ep); - 80079f4: 687b ldr r3, [r7, #4] - 80079f6: 681b ldr r3, [r3, #0] - 80079f8: 68f9 ldr r1, [r7, #12] - 80079fa: 4618 mov r0, r3 - 80079fc: f006 fd70 bl 800e4e0 + 800839c: 687b ldr r3, [r7, #4] + 800839e: 681b ldr r3, [r3, #0] + 80083a0: 68f9 ldr r1, [r7, #12] + 80083a2: 4618 mov r0, r3 + 80083a4: f007 f9f4 bl 800f790 if ((ep_addr & EP_ADDR_MSK) == 0U) - 8007a00: 78fb ldrb r3, [r7, #3] - 8007a02: f003 0307 and.w r3, r3, #7 - 8007a06: 2b00 cmp r3, #0 - 8007a08: d108 bne.n 8007a1c + 80083a8: 78fb ldrb r3, [r7, #3] + 80083aa: f003 0307 and.w r3, r3, #7 + 80083ae: 2b00 cmp r3, #0 + 80083b0: d108 bne.n 80083c4 { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - 8007a0a: 687b ldr r3, [r7, #4] - 8007a0c: 681a ldr r2, [r3, #0] - 8007a0e: 687b ldr r3, [r7, #4] - 8007a10: f503 732c add.w r3, r3, #688 ; 0x2b0 - 8007a14: 4619 mov r1, r3 - 8007a16: 4610 mov r0, r2 - 8007a18: f006 feb1 bl 800e77e + 80083b2: 687b ldr r3, [r7, #4] + 80083b4: 681a ldr r2, [r3, #0] + 80083b6: 687b ldr r3, [r7, #4] + 80083b8: f503 732c add.w r3, r3, #688 ; 0x2b0 + 80083bc: 4619 mov r1, r3 + 80083be: 4610 mov r0, r2 + 80083c0: f007 fb35 bl 800fa2e } __HAL_UNLOCK(hpcd); - 8007a1c: 687b ldr r3, [r7, #4] - 8007a1e: 2200 movs r2, #0 - 8007a20: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 80083c4: 687b ldr r3, [r7, #4] + 80083c6: 2200 movs r2, #0 + 80083c8: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return HAL_OK; - 8007a24: 2300 movs r3, #0 + 80083cc: 2300 movs r3, #0 } - 8007a26: 4618 mov r0, r3 - 8007a28: 3710 adds r7, #16 - 8007a2a: 46bd mov sp, r7 - 8007a2c: bd80 pop {r7, pc} + 80083ce: 4618 mov r0, r3 + 80083d0: 3710 adds r7, #16 + 80083d2: 46bd mov sp, r7 + 80083d4: bd80 pop {r7, pc} -08007a2e : +080083d6 : * @param hpcd PCD handle * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - 8007a2e: b580 push {r7, lr} - 8007a30: b084 sub sp, #16 - 8007a32: af00 add r7, sp, #0 - 8007a34: 6078 str r0, [r7, #4] - 8007a36: 460b mov r3, r1 - 8007a38: 70fb strb r3, [r7, #3] + 80083d6: b580 push {r7, lr} + 80083d8: b084 sub sp, #16 + 80083da: af00 add r7, sp, #0 + 80083dc: 6078 str r0, [r7, #4] + 80083de: 460b mov r3, r1 + 80083e0: 70fb strb r3, [r7, #3] PCD_EPTypeDef *ep; if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) - 8007a3a: 78fb ldrb r3, [r7, #3] - 8007a3c: f003 020f and.w r2, r3, #15 - 8007a40: 687b ldr r3, [r7, #4] - 8007a42: 685b ldr r3, [r3, #4] - 8007a44: 429a cmp r2, r3 - 8007a46: d901 bls.n 8007a4c + 80083e2: 78fb ldrb r3, [r7, #3] + 80083e4: f003 020f and.w r2, r3, #15 + 80083e8: 687b ldr r3, [r7, #4] + 80083ea: 685b ldr r3, [r3, #4] + 80083ec: 429a cmp r2, r3 + 80083ee: d901 bls.n 80083f4 { return HAL_ERROR; - 8007a48: 2301 movs r3, #1 - 8007a4a: e040 b.n 8007ace + 80083f0: 2301 movs r3, #1 + 80083f2: e040 b.n 8008476 } if ((0x80U & ep_addr) == 0x80U) - 8007a4c: f997 3003 ldrsb.w r3, [r7, #3] - 8007a50: 2b00 cmp r3, #0 - 8007a52: da0e bge.n 8007a72 + 80083f4: f997 3003 ldrsb.w r3, [r7, #3] + 80083f8: 2b00 cmp r3, #0 + 80083fa: da0e bge.n 800841a { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 8007a54: 78fb ldrb r3, [r7, #3] - 8007a56: f003 0307 and.w r3, r3, #7 - 8007a5a: 1c5a adds r2, r3, #1 - 8007a5c: 4613 mov r3, r2 - 8007a5e: 009b lsls r3, r3, #2 - 8007a60: 4413 add r3, r2 - 8007a62: 00db lsls r3, r3, #3 - 8007a64: 687a ldr r2, [r7, #4] - 8007a66: 4413 add r3, r2 - 8007a68: 60fb str r3, [r7, #12] + 80083fc: 78fb ldrb r3, [r7, #3] + 80083fe: f003 0307 and.w r3, r3, #7 + 8008402: 1c5a adds r2, r3, #1 + 8008404: 4613 mov r3, r2 + 8008406: 009b lsls r3, r3, #2 + 8008408: 4413 add r3, r2 + 800840a: 00db lsls r3, r3, #3 + 800840c: 687a ldr r2, [r7, #4] + 800840e: 4413 add r3, r2 + 8008410: 60fb str r3, [r7, #12] ep->is_in = 1U; - 8007a6a: 68fb ldr r3, [r7, #12] - 8007a6c: 2201 movs r2, #1 - 8007a6e: 705a strb r2, [r3, #1] - 8007a70: e00e b.n 8007a90 + 8008412: 68fb ldr r3, [r7, #12] + 8008414: 2201 movs r2, #1 + 8008416: 705a strb r2, [r3, #1] + 8008418: e00e b.n 8008438 } else { ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - 8007a72: 78fb ldrb r3, [r7, #3] - 8007a74: f003 0207 and.w r2, r3, #7 - 8007a78: 4613 mov r3, r2 - 8007a7a: 009b lsls r3, r3, #2 - 8007a7c: 4413 add r3, r2 - 8007a7e: 00db lsls r3, r3, #3 - 8007a80: f503 73b4 add.w r3, r3, #360 ; 0x168 - 8007a84: 687a ldr r2, [r7, #4] - 8007a86: 4413 add r3, r2 - 8007a88: 60fb str r3, [r7, #12] + 800841a: 78fb ldrb r3, [r7, #3] + 800841c: f003 0207 and.w r2, r3, #7 + 8008420: 4613 mov r3, r2 + 8008422: 009b lsls r3, r3, #2 + 8008424: 4413 add r3, r2 + 8008426: 00db lsls r3, r3, #3 + 8008428: f503 73b4 add.w r3, r3, #360 ; 0x168 + 800842c: 687a ldr r2, [r7, #4] + 800842e: 4413 add r3, r2 + 8008430: 60fb str r3, [r7, #12] ep->is_in = 0U; - 8007a8a: 68fb ldr r3, [r7, #12] - 8007a8c: 2200 movs r2, #0 - 8007a8e: 705a strb r2, [r3, #1] + 8008432: 68fb ldr r3, [r7, #12] + 8008434: 2200 movs r2, #0 + 8008436: 705a strb r2, [r3, #1] } ep->is_stall = 0U; - 8007a90: 68fb ldr r3, [r7, #12] - 8007a92: 2200 movs r2, #0 - 8007a94: 709a strb r2, [r3, #2] + 8008438: 68fb ldr r3, [r7, #12] + 800843a: 2200 movs r2, #0 + 800843c: 709a strb r2, [r3, #2] ep->num = ep_addr & EP_ADDR_MSK; - 8007a96: 78fb ldrb r3, [r7, #3] - 8007a98: f003 0307 and.w r3, r3, #7 - 8007a9c: b2da uxtb r2, r3 - 8007a9e: 68fb ldr r3, [r7, #12] - 8007aa0: 701a strb r2, [r3, #0] + 800843e: 78fb ldrb r3, [r7, #3] + 8008440: f003 0307 and.w r3, r3, #7 + 8008444: b2da uxtb r2, r3 + 8008446: 68fb ldr r3, [r7, #12] + 8008448: 701a strb r2, [r3, #0] __HAL_LOCK(hpcd); - 8007aa2: 687b ldr r3, [r7, #4] - 8007aa4: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 - 8007aa8: 2b01 cmp r3, #1 - 8007aaa: d101 bne.n 8007ab0 - 8007aac: 2302 movs r3, #2 - 8007aae: e00e b.n 8007ace - 8007ab0: 687b ldr r3, [r7, #4] - 8007ab2: 2201 movs r2, #1 - 8007ab4: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 800844a: 687b ldr r3, [r7, #4] + 800844c: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8 + 8008450: 2b01 cmp r3, #1 + 8008452: d101 bne.n 8008458 + 8008454: 2302 movs r3, #2 + 8008456: e00e b.n 8008476 + 8008458: 687b ldr r3, [r7, #4] + 800845a: 2201 movs r2, #1 + 800845c: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 (void)USB_EPClearStall(hpcd->Instance, ep); - 8007ab8: 687b ldr r3, [r7, #4] - 8007aba: 681b ldr r3, [r3, #0] - 8007abc: 68f9 ldr r1, [r7, #12] - 8007abe: 4618 mov r0, r3 - 8007ac0: f006 fd5f bl 800e582 + 8008460: 687b ldr r3, [r7, #4] + 8008462: 681b ldr r3, [r3, #0] + 8008464: 68f9 ldr r1, [r7, #12] + 8008466: 4618 mov r0, r3 + 8008468: f007 f9e3 bl 800f832 __HAL_UNLOCK(hpcd); - 8007ac4: 687b ldr r3, [r7, #4] - 8007ac6: 2200 movs r2, #0 - 8007ac8: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 + 800846c: 687b ldr r3, [r7, #4] + 800846e: 2200 movs r2, #0 + 8008470: f883 22a8 strb.w r2, [r3, #680] ; 0x2a8 return HAL_OK; - 8007acc: 2300 movs r3, #0 + 8008474: 2300 movs r3, #0 } - 8007ace: 4618 mov r0, r3 - 8007ad0: 3710 adds r7, #16 - 8007ad2: 46bd mov sp, r7 - 8007ad4: bd80 pop {r7, pc} + 8008476: 4618 mov r0, r3 + 8008478: 3710 adds r7, #16 + 800847a: 46bd mov sp, r7 + 800847c: bd80 pop {r7, pc} -08007ad6 : +0800847e : * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle * @retval HAL status */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { - 8007ad6: b580 push {r7, lr} - 8007ad8: b096 sub sp, #88 ; 0x58 - 8007ada: af00 add r7, sp, #0 - 8007adc: 6078 str r0, [r7, #4] + 800847e: b580 push {r7, lr} + 8008480: b096 sub sp, #88 ; 0x58 + 8008482: af00 add r7, sp, #0 + 8008484: 6078 str r0, [r7, #4] #if (USE_USB_DOUBLE_BUFFER != 1U) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) - 8007ade: e3b1 b.n 8008244 + 8008486: e3b1 b.n 8008bec { wIstr = hpcd->Instance->ISTR; - 8007ae0: 687b ldr r3, [r7, #4] - 8007ae2: 681b ldr r3, [r3, #0] - 8007ae4: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 8007ae8: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + 8008488: 687b ldr r3, [r7, #4] + 800848a: 681b ldr r3, [r3, #0] + 800848c: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8008490: f8a7 304e strh.w r3, [r7, #78] ; 0x4e /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - 8007aec: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e - 8007af0: b2db uxtb r3, r3 - 8007af2: f003 030f and.w r3, r3, #15 - 8007af6: f887 304d strb.w r3, [r7, #77] ; 0x4d + 8008494: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 8008498: b2db uxtb r3, r3 + 800849a: f003 030f and.w r3, r3, #15 + 800849e: f887 304d strb.w r3, [r7, #77] ; 0x4d if (epindex == 0U) - 8007afa: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8007afe: 2b00 cmp r3, #0 - 8007b00: f040 8173 bne.w 8007dea + 80084a2: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80084a6: 2b00 cmp r3, #0 + 80084a8: f040 8173 bne.w 8008792 { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ if ((wIstr & USB_ISTR_DIR) == 0U) - 8007b04: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e - 8007b08: f003 0310 and.w r3, r3, #16 - 8007b0c: 2b00 cmp r3, #0 - 8007b0e: d150 bne.n 8007bb2 + 80084ac: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 80084b0: f003 0310 and.w r3, r3, #16 + 80084b4: 2b00 cmp r3, #0 + 80084b6: d150 bne.n 800855a { /* DIR = 0 */ /* DIR = 0 => IN int */ /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - 8007b10: 687b ldr r3, [r7, #4] - 8007b12: 681b ldr r3, [r3, #0] - 8007b14: 881b ldrh r3, [r3, #0] - 8007b16: b29b uxth r3, r3 - 8007b18: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 - 8007b1c: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8007b20: 81fb strh r3, [r7, #14] - 8007b22: 687b ldr r3, [r7, #4] - 8007b24: 681a ldr r2, [r3, #0] - 8007b26: 89fb ldrh r3, [r7, #14] - 8007b28: ea6f 4343 mvn.w r3, r3, lsl #17 - 8007b2c: ea6f 4353 mvn.w r3, r3, lsr #17 - 8007b30: b29b uxth r3, r3 - 8007b32: 8013 strh r3, [r2, #0] + 80084b8: 687b ldr r3, [r7, #4] + 80084ba: 681b ldr r3, [r3, #0] + 80084bc: 881b ldrh r3, [r3, #0] + 80084be: b29b uxth r3, r3 + 80084c0: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 + 80084c4: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80084c8: 81fb strh r3, [r7, #14] + 80084ca: 687b ldr r3, [r7, #4] + 80084cc: 681a ldr r2, [r3, #0] + 80084ce: 89fb ldrh r3, [r7, #14] + 80084d0: ea6f 4343 mvn.w r3, r3, lsl #17 + 80084d4: ea6f 4353 mvn.w r3, r3, lsr #17 + 80084d8: b29b uxth r3, r3 + 80084da: 8013 strh r3, [r2, #0] ep = &hpcd->IN_ep[0]; - 8007b34: 687b ldr r3, [r7, #4] - 8007b36: 3328 adds r3, #40 ; 0x28 - 8007b38: 657b str r3, [r7, #84] ; 0x54 + 80084dc: 687b ldr r3, [r7, #4] + 80084de: 3328 adds r3, #40 ; 0x28 + 80084e0: 657b str r3, [r7, #84] ; 0x54 ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - 8007b3a: 687b ldr r3, [r7, #4] - 8007b3c: 681b ldr r3, [r3, #0] - 8007b3e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007b42: b29b uxth r3, r3 - 8007b44: 461a mov r2, r3 - 8007b46: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b48: 781b ldrb r3, [r3, #0] - 8007b4a: 00db lsls r3, r3, #3 - 8007b4c: 4413 add r3, r2 - 8007b4e: 687a ldr r2, [r7, #4] - 8007b50: 6812 ldr r2, [r2, #0] - 8007b52: 4413 add r3, r2 - 8007b54: f203 4302 addw r3, r3, #1026 ; 0x402 - 8007b58: 881b ldrh r3, [r3, #0] - 8007b5a: f3c3 0209 ubfx r2, r3, #0, #10 - 8007b5e: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b60: 61da str r2, [r3, #28] + 80084e2: 687b ldr r3, [r7, #4] + 80084e4: 681b ldr r3, [r3, #0] + 80084e6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80084ea: b29b uxth r3, r3 + 80084ec: 461a mov r2, r3 + 80084ee: 6d7b ldr r3, [r7, #84] ; 0x54 + 80084f0: 781b ldrb r3, [r3, #0] + 80084f2: 00db lsls r3, r3, #3 + 80084f4: 4413 add r3, r2 + 80084f6: 687a ldr r2, [r7, #4] + 80084f8: 6812 ldr r2, [r2, #0] + 80084fa: 4413 add r3, r2 + 80084fc: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008500: 881b ldrh r3, [r3, #0] + 8008502: f3c3 0209 ubfx r2, r3, #0, #10 + 8008506: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008508: 61da str r2, [r3, #28] ep->xfer_buff += ep->xfer_count; - 8007b62: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b64: 695a ldr r2, [r3, #20] - 8007b66: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b68: 69db ldr r3, [r3, #28] - 8007b6a: 441a add r2, r3 - 8007b6c: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b6e: 615a str r2, [r3, #20] + 800850a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800850c: 695a ldr r2, [r3, #20] + 800850e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008510: 69db ldr r3, [r3, #28] + 8008512: 441a add r2, r3 + 8008514: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008516: 615a str r2, [r3, #20] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, 0U); #else HAL_PCD_DataInStageCallback(hpcd, 0U); - 8007b70: 2100 movs r1, #0 - 8007b72: 6878 ldr r0, [r7, #4] - 8007b74: f008 fcd7 bl 8010526 + 8008518: 2100 movs r1, #0 + 800851a: 6878 ldr r0, [r7, #4] + 800851c: f00a fa31 bl 8012982 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) - 8007b78: 687b ldr r3, [r7, #4] - 8007b7a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 - 8007b7e: b2db uxtb r3, r3 - 8007b80: 2b00 cmp r3, #0 - 8007b82: f000 835f beq.w 8008244 - 8007b86: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007b88: 699b ldr r3, [r3, #24] - 8007b8a: 2b00 cmp r3, #0 - 8007b8c: f040 835a bne.w 8008244 + 8008520: 687b ldr r3, [r7, #4] + 8008522: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8008526: b2db uxtb r3, r3 + 8008528: 2b00 cmp r3, #0 + 800852a: f000 835f beq.w 8008bec + 800852e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008530: 699b ldr r3, [r3, #24] + 8008532: 2b00 cmp r3, #0 + 8008534: f040 835a bne.w 8008bec { hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); - 8007b90: 687b ldr r3, [r7, #4] - 8007b92: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 - 8007b96: b2db uxtb r3, r3 - 8007b98: f063 037f orn r3, r3, #127 ; 0x7f - 8007b9c: b2da uxtb r2, r3 - 8007b9e: 687b ldr r3, [r7, #4] - 8007ba0: 681b ldr r3, [r3, #0] - 8007ba2: b292 uxth r2, r2 - 8007ba4: f8a3 204c strh.w r2, [r3, #76] ; 0x4c + 8008538: 687b ldr r3, [r7, #4] + 800853a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 800853e: b2db uxtb r3, r3 + 8008540: f063 037f orn r3, r3, #127 ; 0x7f + 8008544: b2da uxtb r2, r3 + 8008546: 687b ldr r3, [r7, #4] + 8008548: 681b ldr r3, [r3, #0] + 800854a: b292 uxth r2, r2 + 800854c: f8a3 204c strh.w r2, [r3, #76] ; 0x4c hpcd->USB_Address = 0U; - 8007ba8: 687b ldr r3, [r7, #4] - 8007baa: 2200 movs r2, #0 - 8007bac: f883 2024 strb.w r2, [r3, #36] ; 0x24 - 8007bb0: e348 b.n 8008244 + 8008550: 687b ldr r3, [r7, #4] + 8008552: 2200 movs r2, #0 + 8008554: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8008558: e348 b.n 8008bec { /* DIR = 1 */ /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; - 8007bb2: 687b ldr r3, [r7, #4] - 8007bb4: f503 73b4 add.w r3, r3, #360 ; 0x168 - 8007bb8: 657b str r3, [r7, #84] ; 0x54 + 800855a: 687b ldr r3, [r7, #4] + 800855c: f503 73b4 add.w r3, r3, #360 ; 0x168 + 8008560: 657b str r3, [r7, #84] ; 0x54 wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - 8007bba: 687b ldr r3, [r7, #4] - 8007bbc: 681b ldr r3, [r3, #0] - 8007bbe: 881b ldrh r3, [r3, #0] - 8007bc0: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + 8008562: 687b ldr r3, [r7, #4] + 8008564: 681b ldr r3, [r3, #0] + 8008566: 881b ldrh r3, [r3, #0] + 8008568: f8a7 304a strh.w r3, [r7, #74] ; 0x4a if ((wEPVal & USB_EP_SETUP) != 0U) - 8007bc4: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8007bc8: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8007bcc: 2b00 cmp r3, #0 - 8007bce: d032 beq.n 8007c36 + 800856c: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008570: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8008574: 2b00 cmp r3, #0 + 8008576: d032 beq.n 80085de { /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - 8007bd0: 687b ldr r3, [r7, #4] - 8007bd2: 681b ldr r3, [r3, #0] - 8007bd4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007bd8: b29b uxth r3, r3 - 8007bda: 461a mov r2, r3 - 8007bdc: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007bde: 781b ldrb r3, [r3, #0] - 8007be0: 00db lsls r3, r3, #3 - 8007be2: 4413 add r3, r2 - 8007be4: 687a ldr r2, [r7, #4] - 8007be6: 6812 ldr r2, [r2, #0] - 8007be8: 4413 add r3, r2 - 8007bea: f203 4306 addw r3, r3, #1030 ; 0x406 - 8007bee: 881b ldrh r3, [r3, #0] - 8007bf0: f3c3 0209 ubfx r2, r3, #0, #10 - 8007bf4: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007bf6: 61da str r2, [r3, #28] + 8008578: 687b ldr r3, [r7, #4] + 800857a: 681b ldr r3, [r3, #0] + 800857c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008580: b29b uxth r3, r3 + 8008582: 461a mov r2, r3 + 8008584: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008586: 781b ldrb r3, [r3, #0] + 8008588: 00db lsls r3, r3, #3 + 800858a: 4413 add r3, r2 + 800858c: 687a ldr r2, [r7, #4] + 800858e: 6812 ldr r2, [r2, #0] + 8008590: 4413 add r3, r2 + 8008592: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008596: 881b ldrh r3, [r3, #0] + 8008598: f3c3 0209 ubfx r2, r3, #0, #10 + 800859c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800859e: 61da str r2, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, - 8007bf8: 687b ldr r3, [r7, #4] - 8007bfa: 6818 ldr r0, [r3, #0] - 8007bfc: 687b ldr r3, [r7, #4] - 8007bfe: f503 712c add.w r1, r3, #688 ; 0x2b0 - 8007c02: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c04: 88da ldrh r2, [r3, #6] + 80085a0: 687b ldr r3, [r7, #4] + 80085a2: 6818 ldr r0, [r3, #0] + 80085a4: 687b ldr r3, [r7, #4] + 80085a6: f503 712c add.w r1, r3, #688 ; 0x2b0 + 80085aa: 6d7b ldr r3, [r7, #84] ; 0x54 + 80085ac: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); - 8007c06: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c08: 69db ldr r3, [r3, #28] + 80085ae: 6d7b ldr r3, [r7, #84] ; 0x54 + 80085b0: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, - 8007c0a: b29b uxth r3, r3 - 8007c0c: f006 fe05 bl 800e81a + 80085b2: b29b uxth r3, r3 + 80085b4: f007 fa89 bl 800faca /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - 8007c10: 687b ldr r3, [r7, #4] - 8007c12: 681b ldr r3, [r3, #0] - 8007c14: 881b ldrh r3, [r3, #0] - 8007c16: b29a uxth r2, r3 - 8007c18: f640 738f movw r3, #3983 ; 0xf8f - 8007c1c: 4013 ands r3, r2 - 8007c1e: 823b strh r3, [r7, #16] - 8007c20: 687b ldr r3, [r7, #4] - 8007c22: 681b ldr r3, [r3, #0] - 8007c24: 8a3a ldrh r2, [r7, #16] - 8007c26: f042 0280 orr.w r2, r2, #128 ; 0x80 - 8007c2a: b292 uxth r2, r2 - 8007c2c: 801a strh r2, [r3, #0] + 80085b8: 687b ldr r3, [r7, #4] + 80085ba: 681b ldr r3, [r3, #0] + 80085bc: 881b ldrh r3, [r3, #0] + 80085be: b29a uxth r2, r3 + 80085c0: f640 738f movw r3, #3983 ; 0xf8f + 80085c4: 4013 ands r3, r2 + 80085c6: 823b strh r3, [r7, #16] + 80085c8: 687b ldr r3, [r7, #4] + 80085ca: 681b ldr r3, [r3, #0] + 80085cc: 8a3a ldrh r2, [r7, #16] + 80085ce: f042 0280 orr.w r2, r2, #128 ; 0x80 + 80085d2: b292 uxth r2, r2 + 80085d4: 801a strh r2, [r3, #0] /* Process SETUP Packet*/ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SetupStageCallback(hpcd); #else HAL_PCD_SetupStageCallback(hpcd); - 8007c2e: 6878 ldr r0, [r7, #4] - 8007c30: f008 fc4c bl 80104cc - 8007c34: e306 b.n 8008244 + 80085d6: 6878 ldr r0, [r7, #4] + 80085d8: f00a f9a6 bl 8012928 + 80085dc: e306 b.n 8008bec #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else if ((wEPVal & USB_EP_CTR_RX) != 0U) - 8007c36: f9b7 304a ldrsh.w r3, [r7, #74] ; 0x4a - 8007c3a: 2b00 cmp r3, #0 - 8007c3c: f280 8302 bge.w 8008244 + 80085de: f9b7 304a ldrsh.w r3, [r7, #74] ; 0x4a + 80085e2: 2b00 cmp r3, #0 + 80085e4: f280 8302 bge.w 8008bec { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - 8007c40: 687b ldr r3, [r7, #4] - 8007c42: 681b ldr r3, [r3, #0] - 8007c44: 881b ldrh r3, [r3, #0] - 8007c46: b29a uxth r2, r3 - 8007c48: f640 738f movw r3, #3983 ; 0xf8f - 8007c4c: 4013 ands r3, r2 - 8007c4e: 83fb strh r3, [r7, #30] - 8007c50: 687b ldr r3, [r7, #4] - 8007c52: 681b ldr r3, [r3, #0] - 8007c54: 8bfa ldrh r2, [r7, #30] - 8007c56: f042 0280 orr.w r2, r2, #128 ; 0x80 - 8007c5a: b292 uxth r2, r2 - 8007c5c: 801a strh r2, [r3, #0] + 80085e8: 687b ldr r3, [r7, #4] + 80085ea: 681b ldr r3, [r3, #0] + 80085ec: 881b ldrh r3, [r3, #0] + 80085ee: b29a uxth r2, r3 + 80085f0: f640 738f movw r3, #3983 ; 0xf8f + 80085f4: 4013 ands r3, r2 + 80085f6: 83fb strh r3, [r7, #30] + 80085f8: 687b ldr r3, [r7, #4] + 80085fa: 681b ldr r3, [r3, #0] + 80085fc: 8bfa ldrh r2, [r7, #30] + 80085fe: f042 0280 orr.w r2, r2, #128 ; 0x80 + 8008602: b292 uxth r2, r2 + 8008604: 801a strh r2, [r3, #0] /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - 8007c5e: 687b ldr r3, [r7, #4] - 8007c60: 681b ldr r3, [r3, #0] - 8007c62: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007c66: b29b uxth r3, r3 - 8007c68: 461a mov r2, r3 - 8007c6a: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c6c: 781b ldrb r3, [r3, #0] - 8007c6e: 00db lsls r3, r3, #3 - 8007c70: 4413 add r3, r2 - 8007c72: 687a ldr r2, [r7, #4] - 8007c74: 6812 ldr r2, [r2, #0] - 8007c76: 4413 add r3, r2 - 8007c78: f203 4306 addw r3, r3, #1030 ; 0x406 - 8007c7c: 881b ldrh r3, [r3, #0] - 8007c7e: f3c3 0209 ubfx r2, r3, #0, #10 - 8007c82: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c84: 61da str r2, [r3, #28] + 8008606: 687b ldr r3, [r7, #4] + 8008608: 681b ldr r3, [r3, #0] + 800860a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800860e: b29b uxth r3, r3 + 8008610: 461a mov r2, r3 + 8008612: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008614: 781b ldrb r3, [r3, #0] + 8008616: 00db lsls r3, r3, #3 + 8008618: 4413 add r3, r2 + 800861a: 687a ldr r2, [r7, #4] + 800861c: 6812 ldr r2, [r2, #0] + 800861e: 4413 add r3, r2 + 8008620: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008624: 881b ldrh r3, [r3, #0] + 8008626: f3c3 0209 ubfx r2, r3, #0, #10 + 800862a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800862c: 61da str r2, [r3, #28] if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) - 8007c86: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c88: 69db ldr r3, [r3, #28] - 8007c8a: 2b00 cmp r3, #0 - 8007c8c: d019 beq.n 8007cc2 - 8007c8e: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c90: 695b ldr r3, [r3, #20] - 8007c92: 2b00 cmp r3, #0 - 8007c94: d015 beq.n 8007cc2 + 800862e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008630: 69db ldr r3, [r3, #28] + 8008632: 2b00 cmp r3, #0 + 8008634: d019 beq.n 800866a + 8008636: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008638: 695b ldr r3, [r3, #20] + 800863a: 2b00 cmp r3, #0 + 800863c: d015 beq.n 800866a { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - 8007c96: 687b ldr r3, [r7, #4] - 8007c98: 6818 ldr r0, [r3, #0] - 8007c9a: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007c9c: 6959 ldr r1, [r3, #20] - 8007c9e: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007ca0: 88da ldrh r2, [r3, #6] + 800863e: 687b ldr r3, [r7, #4] + 8008640: 6818 ldr r0, [r3, #0] + 8008642: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008644: 6959 ldr r1, [r3, #20] + 8008646: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008648: 88da ldrh r2, [r3, #6] ep->pmaadress, (uint16_t)ep->xfer_count); - 8007ca2: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007ca4: 69db ldr r3, [r3, #28] + 800864a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800864c: 69db ldr r3, [r3, #28] USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - 8007ca6: b29b uxth r3, r3 - 8007ca8: f006 fdb7 bl 800e81a + 800864e: b29b uxth r3, r3 + 8008650: f007 fa3b bl 800faca ep->xfer_buff += ep->xfer_count; - 8007cac: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007cae: 695a ldr r2, [r3, #20] - 8007cb0: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007cb2: 69db ldr r3, [r3, #28] - 8007cb4: 441a add r2, r3 - 8007cb6: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007cb8: 615a str r2, [r3, #20] + 8008654: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008656: 695a ldr r2, [r3, #20] + 8008658: 6d7b ldr r3, [r7, #84] ; 0x54 + 800865a: 69db ldr r3, [r3, #28] + 800865c: 441a add r2, r3 + 800865e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008660: 615a str r2, [r3, #20] /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else HAL_PCD_DataOutStageCallback(hpcd, 0U); - 8007cba: 2100 movs r1, #0 - 8007cbc: 6878 ldr r0, [r7, #4] - 8007cbe: f008 fc17 bl 80104f0 + 8008662: 2100 movs r1, #0 + 8008664: 6878 ldr r0, [r7, #4] + 8008666: f00a f971 bl 801294c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - 8007cc2: 687b ldr r3, [r7, #4] - 8007cc4: 681b ldr r3, [r3, #0] - 8007cc6: 881b ldrh r3, [r3, #0] - 8007cc8: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + 800866a: 687b ldr r3, [r7, #4] + 800866c: 681b ldr r3, [r3, #0] + 800866e: 881b ldrh r3, [r3, #0] + 8008670: f8a7 304a strh.w r3, [r7, #74] ; 0x4a if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - 8007ccc: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8007cd0: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8007cd4: 2b00 cmp r3, #0 - 8007cd6: f040 82b5 bne.w 8008244 - 8007cda: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8007cde: f403 5340 and.w r3, r3, #12288 ; 0x3000 - 8007ce2: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 - 8007ce6: f000 82ad beq.w 8008244 + 8008674: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008678: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800867c: 2b00 cmp r3, #0 + 800867e: f040 82b5 bne.w 8008bec + 8008682: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008686: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 800868a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 800868e: f000 82ad beq.w 8008bec { PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - 8007cea: 687b ldr r3, [r7, #4] - 8007cec: 681b ldr r3, [r3, #0] - 8007cee: 61bb str r3, [r7, #24] - 8007cf0: 687b ldr r3, [r7, #4] - 8007cf2: 681b ldr r3, [r3, #0] - 8007cf4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007cf8: b29b uxth r3, r3 - 8007cfa: 461a mov r2, r3 - 8007cfc: 69bb ldr r3, [r7, #24] - 8007cfe: 4413 add r3, r2 - 8007d00: 61bb str r3, [r7, #24] - 8007d02: 69bb ldr r3, [r7, #24] - 8007d04: f203 4306 addw r3, r3, #1030 ; 0x406 - 8007d08: 617b str r3, [r7, #20] - 8007d0a: 697b ldr r3, [r7, #20] - 8007d0c: 881b ldrh r3, [r3, #0] - 8007d0e: b29b uxth r3, r3 - 8007d10: f3c3 0309 ubfx r3, r3, #0, #10 - 8007d14: b29a uxth r2, r3 - 8007d16: 697b ldr r3, [r7, #20] - 8007d18: 801a strh r2, [r3, #0] - 8007d1a: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d1c: 691b ldr r3, [r3, #16] - 8007d1e: 2b3e cmp r3, #62 ; 0x3e - 8007d20: d91d bls.n 8007d5e - 8007d22: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d24: 691b ldr r3, [r3, #16] - 8007d26: 095b lsrs r3, r3, #5 - 8007d28: 647b str r3, [r7, #68] ; 0x44 - 8007d2a: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d2c: 691b ldr r3, [r3, #16] - 8007d2e: f003 031f and.w r3, r3, #31 - 8007d32: 2b00 cmp r3, #0 - 8007d34: d102 bne.n 8007d3c - 8007d36: 6c7b ldr r3, [r7, #68] ; 0x44 - 8007d38: 3b01 subs r3, #1 - 8007d3a: 647b str r3, [r7, #68] ; 0x44 - 8007d3c: 697b ldr r3, [r7, #20] - 8007d3e: 881b ldrh r3, [r3, #0] - 8007d40: b29a uxth r2, r3 - 8007d42: 6c7b ldr r3, [r7, #68] ; 0x44 - 8007d44: b29b uxth r3, r3 - 8007d46: 029b lsls r3, r3, #10 - 8007d48: b29b uxth r3, r3 - 8007d4a: 4313 orrs r3, r2 - 8007d4c: b29b uxth r3, r3 - 8007d4e: ea6f 4343 mvn.w r3, r3, lsl #17 - 8007d52: ea6f 4353 mvn.w r3, r3, lsr #17 - 8007d56: b29a uxth r2, r3 - 8007d58: 697b ldr r3, [r7, #20] - 8007d5a: 801a strh r2, [r3, #0] - 8007d5c: e026 b.n 8007dac - 8007d5e: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d60: 691b ldr r3, [r3, #16] - 8007d62: 2b00 cmp r3, #0 - 8007d64: d10a bne.n 8007d7c - 8007d66: 697b ldr r3, [r7, #20] - 8007d68: 881b ldrh r3, [r3, #0] - 8007d6a: b29b uxth r3, r3 - 8007d6c: ea6f 4343 mvn.w r3, r3, lsl #17 - 8007d70: ea6f 4353 mvn.w r3, r3, lsr #17 - 8007d74: b29a uxth r2, r3 - 8007d76: 697b ldr r3, [r7, #20] - 8007d78: 801a strh r2, [r3, #0] - 8007d7a: e017 b.n 8007dac - 8007d7c: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d7e: 691b ldr r3, [r3, #16] - 8007d80: 085b lsrs r3, r3, #1 - 8007d82: 647b str r3, [r7, #68] ; 0x44 - 8007d84: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007d86: 691b ldr r3, [r3, #16] - 8007d88: f003 0301 and.w r3, r3, #1 - 8007d8c: 2b00 cmp r3, #0 - 8007d8e: d002 beq.n 8007d96 - 8007d90: 6c7b ldr r3, [r7, #68] ; 0x44 - 8007d92: 3301 adds r3, #1 - 8007d94: 647b str r3, [r7, #68] ; 0x44 - 8007d96: 697b ldr r3, [r7, #20] - 8007d98: 881b ldrh r3, [r3, #0] - 8007d9a: b29a uxth r2, r3 - 8007d9c: 6c7b ldr r3, [r7, #68] ; 0x44 - 8007d9e: b29b uxth r3, r3 - 8007da0: 029b lsls r3, r3, #10 - 8007da2: b29b uxth r3, r3 - 8007da4: 4313 orrs r3, r2 - 8007da6: b29a uxth r2, r3 - 8007da8: 697b ldr r3, [r7, #20] - 8007daa: 801a strh r2, [r3, #0] + 8008692: 687b ldr r3, [r7, #4] + 8008694: 681b ldr r3, [r3, #0] + 8008696: 61bb str r3, [r7, #24] + 8008698: 687b ldr r3, [r7, #4] + 800869a: 681b ldr r3, [r3, #0] + 800869c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80086a0: b29b uxth r3, r3 + 80086a2: 461a mov r2, r3 + 80086a4: 69bb ldr r3, [r7, #24] + 80086a6: 4413 add r3, r2 + 80086a8: 61bb str r3, [r7, #24] + 80086aa: 69bb ldr r3, [r7, #24] + 80086ac: f203 4306 addw r3, r3, #1030 ; 0x406 + 80086b0: 617b str r3, [r7, #20] + 80086b2: 697b ldr r3, [r7, #20] + 80086b4: 881b ldrh r3, [r3, #0] + 80086b6: b29b uxth r3, r3 + 80086b8: f3c3 0309 ubfx r3, r3, #0, #10 + 80086bc: b29a uxth r2, r3 + 80086be: 697b ldr r3, [r7, #20] + 80086c0: 801a strh r2, [r3, #0] + 80086c2: 6d7b ldr r3, [r7, #84] ; 0x54 + 80086c4: 691b ldr r3, [r3, #16] + 80086c6: 2b3e cmp r3, #62 ; 0x3e + 80086c8: d91d bls.n 8008706 + 80086ca: 6d7b ldr r3, [r7, #84] ; 0x54 + 80086cc: 691b ldr r3, [r3, #16] + 80086ce: 095b lsrs r3, r3, #5 + 80086d0: 647b str r3, [r7, #68] ; 0x44 + 80086d2: 6d7b ldr r3, [r7, #84] ; 0x54 + 80086d4: 691b ldr r3, [r3, #16] + 80086d6: f003 031f and.w r3, r3, #31 + 80086da: 2b00 cmp r3, #0 + 80086dc: d102 bne.n 80086e4 + 80086de: 6c7b ldr r3, [r7, #68] ; 0x44 + 80086e0: 3b01 subs r3, #1 + 80086e2: 647b str r3, [r7, #68] ; 0x44 + 80086e4: 697b ldr r3, [r7, #20] + 80086e6: 881b ldrh r3, [r3, #0] + 80086e8: b29a uxth r2, r3 + 80086ea: 6c7b ldr r3, [r7, #68] ; 0x44 + 80086ec: b29b uxth r3, r3 + 80086ee: 029b lsls r3, r3, #10 + 80086f0: b29b uxth r3, r3 + 80086f2: 4313 orrs r3, r2 + 80086f4: b29b uxth r3, r3 + 80086f6: ea6f 4343 mvn.w r3, r3, lsl #17 + 80086fa: ea6f 4353 mvn.w r3, r3, lsr #17 + 80086fe: b29a uxth r2, r3 + 8008700: 697b ldr r3, [r7, #20] + 8008702: 801a strh r2, [r3, #0] + 8008704: e026 b.n 8008754 + 8008706: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008708: 691b ldr r3, [r3, #16] + 800870a: 2b00 cmp r3, #0 + 800870c: d10a bne.n 8008724 + 800870e: 697b ldr r3, [r7, #20] + 8008710: 881b ldrh r3, [r3, #0] + 8008712: b29b uxth r3, r3 + 8008714: ea6f 4343 mvn.w r3, r3, lsl #17 + 8008718: ea6f 4353 mvn.w r3, r3, lsr #17 + 800871c: b29a uxth r2, r3 + 800871e: 697b ldr r3, [r7, #20] + 8008720: 801a strh r2, [r3, #0] + 8008722: e017 b.n 8008754 + 8008724: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008726: 691b ldr r3, [r3, #16] + 8008728: 085b lsrs r3, r3, #1 + 800872a: 647b str r3, [r7, #68] ; 0x44 + 800872c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800872e: 691b ldr r3, [r3, #16] + 8008730: f003 0301 and.w r3, r3, #1 + 8008734: 2b00 cmp r3, #0 + 8008736: d002 beq.n 800873e + 8008738: 6c7b ldr r3, [r7, #68] ; 0x44 + 800873a: 3301 adds r3, #1 + 800873c: 647b str r3, [r7, #68] ; 0x44 + 800873e: 697b ldr r3, [r7, #20] + 8008740: 881b ldrh r3, [r3, #0] + 8008742: b29a uxth r2, r3 + 8008744: 6c7b ldr r3, [r7, #68] ; 0x44 + 8008746: b29b uxth r3, r3 + 8008748: 029b lsls r3, r3, #10 + 800874a: b29b uxth r3, r3 + 800874c: 4313 orrs r3, r2 + 800874e: b29a uxth r2, r3 + 8008750: 697b ldr r3, [r7, #20] + 8008752: 801a strh r2, [r3, #0] PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - 8007dac: 687b ldr r3, [r7, #4] - 8007dae: 681b ldr r3, [r3, #0] - 8007db0: 881b ldrh r3, [r3, #0] - 8007db2: b29b uxth r3, r3 - 8007db4: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 8007db8: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8007dbc: 827b strh r3, [r7, #18] - 8007dbe: 8a7b ldrh r3, [r7, #18] - 8007dc0: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 8007dc4: 827b strh r3, [r7, #18] - 8007dc6: 8a7b ldrh r3, [r7, #18] - 8007dc8: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 8007dcc: 827b strh r3, [r7, #18] - 8007dce: 687b ldr r3, [r7, #4] - 8007dd0: 681a ldr r2, [r3, #0] - 8007dd2: 8a7b ldrh r3, [r7, #18] - 8007dd4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8007dd8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8007ddc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8007de0: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8007de4: b29b uxth r3, r3 - 8007de6: 8013 strh r3, [r2, #0] - 8007de8: e22c b.n 8008244 + 8008754: 687b ldr r3, [r7, #4] + 8008756: 681b ldr r3, [r3, #0] + 8008758: 881b ldrh r3, [r3, #0] + 800875a: b29b uxth r3, r3 + 800875c: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8008760: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008764: 827b strh r3, [r7, #18] + 8008766: 8a7b ldrh r3, [r7, #18] + 8008768: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800876c: 827b strh r3, [r7, #18] + 800876e: 8a7b ldrh r3, [r7, #18] + 8008770: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 8008774: 827b strh r3, [r7, #18] + 8008776: 687b ldr r3, [r7, #4] + 8008778: 681a ldr r2, [r3, #0] + 800877a: 8a7b ldrh r3, [r7, #18] + 800877c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008780: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008784: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8008788: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800878c: b29b uxth r3, r3 + 800878e: 8013 strh r3, [r2, #0] + 8008790: e22c b.n 8008bec } else { /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - 8007dea: 687b ldr r3, [r7, #4] - 8007dec: 681b ldr r3, [r3, #0] - 8007dee: 461a mov r2, r3 - 8007df0: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8007df4: 009b lsls r3, r3, #2 - 8007df6: 4413 add r3, r2 - 8007df8: 881b ldrh r3, [r3, #0] - 8007dfa: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + 8008792: 687b ldr r3, [r7, #4] + 8008794: 681b ldr r3, [r3, #0] + 8008796: 461a mov r2, r3 + 8008798: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 800879c: 009b lsls r3, r3, #2 + 800879e: 4413 add r3, r2 + 80087a0: 881b ldrh r3, [r3, #0] + 80087a2: f8a7 304a strh.w r3, [r7, #74] ; 0x4a if ((wEPVal & USB_EP_CTR_RX) != 0U) - 8007dfe: f9b7 304a ldrsh.w r3, [r7, #74] ; 0x4a - 8007e02: 2b00 cmp r3, #0 - 8007e04: f280 80f6 bge.w 8007ff4 + 80087a6: f9b7 304a ldrsh.w r3, [r7, #74] ; 0x4a + 80087aa: 2b00 cmp r3, #0 + 80087ac: f280 80f6 bge.w 800899c { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); - 8007e08: 687b ldr r3, [r7, #4] - 8007e0a: 681b ldr r3, [r3, #0] - 8007e0c: 461a mov r2, r3 - 8007e0e: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8007e12: 009b lsls r3, r3, #2 - 8007e14: 4413 add r3, r2 - 8007e16: 881b ldrh r3, [r3, #0] - 8007e18: b29a uxth r2, r3 - 8007e1a: f640 738f movw r3, #3983 ; 0xf8f - 8007e1e: 4013 ands r3, r2 - 8007e20: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 - 8007e24: 687b ldr r3, [r7, #4] - 8007e26: 681b ldr r3, [r3, #0] - 8007e28: 461a mov r2, r3 - 8007e2a: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8007e2e: 009b lsls r3, r3, #2 - 8007e30: 4413 add r3, r2 - 8007e32: f8b7 2048 ldrh.w r2, [r7, #72] ; 0x48 - 8007e36: f042 0280 orr.w r2, r2, #128 ; 0x80 - 8007e3a: b292 uxth r2, r2 - 8007e3c: 801a strh r2, [r3, #0] + 80087b0: 687b ldr r3, [r7, #4] + 80087b2: 681b ldr r3, [r3, #0] + 80087b4: 461a mov r2, r3 + 80087b6: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80087ba: 009b lsls r3, r3, #2 + 80087bc: 4413 add r3, r2 + 80087be: 881b ldrh r3, [r3, #0] + 80087c0: b29a uxth r2, r3 + 80087c2: f640 738f movw r3, #3983 ; 0xf8f + 80087c6: 4013 ands r3, r2 + 80087c8: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + 80087cc: 687b ldr r3, [r7, #4] + 80087ce: 681b ldr r3, [r3, #0] + 80087d0: 461a mov r2, r3 + 80087d2: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80087d6: 009b lsls r3, r3, #2 + 80087d8: 4413 add r3, r2 + 80087da: f8b7 2048 ldrh.w r2, [r7, #72] ; 0x48 + 80087de: f042 0280 orr.w r2, r2, #128 ; 0x80 + 80087e2: b292 uxth r2, r2 + 80087e4: 801a strh r2, [r3, #0] ep = &hpcd->OUT_ep[epindex]; - 8007e3e: f897 204d ldrb.w r2, [r7, #77] ; 0x4d - 8007e42: 4613 mov r3, r2 - 8007e44: 009b lsls r3, r3, #2 - 8007e46: 4413 add r3, r2 - 8007e48: 00db lsls r3, r3, #3 - 8007e4a: f503 73b4 add.w r3, r3, #360 ; 0x168 - 8007e4e: 687a ldr r2, [r7, #4] - 8007e50: 4413 add r3, r2 - 8007e52: 657b str r3, [r7, #84] ; 0x54 + 80087e6: f897 204d ldrb.w r2, [r7, #77] ; 0x4d + 80087ea: 4613 mov r3, r2 + 80087ec: 009b lsls r3, r3, #2 + 80087ee: 4413 add r3, r2 + 80087f0: 00db lsls r3, r3, #3 + 80087f2: f503 73b4 add.w r3, r3, #360 ; 0x168 + 80087f6: 687a ldr r2, [r7, #4] + 80087f8: 4413 add r3, r2 + 80087fa: 657b str r3, [r7, #84] ; 0x54 /* OUT Single Buffering */ if (ep->doublebuffer == 0U) - 8007e54: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007e56: 7b1b ldrb r3, [r3, #12] - 8007e58: 2b00 cmp r3, #0 - 8007e5a: d123 bne.n 8007ea4 + 80087fc: 6d7b ldr r3, [r7, #84] ; 0x54 + 80087fe: 7b1b ldrb r3, [r3, #12] + 8008800: 2b00 cmp r3, #0 + 8008802: d123 bne.n 800884c { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - 8007e5c: 687b ldr r3, [r7, #4] - 8007e5e: 681b ldr r3, [r3, #0] - 8007e60: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007e64: b29b uxth r3, r3 - 8007e66: 461a mov r2, r3 - 8007e68: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007e6a: 781b ldrb r3, [r3, #0] - 8007e6c: 00db lsls r3, r3, #3 - 8007e6e: 4413 add r3, r2 - 8007e70: 687a ldr r2, [r7, #4] - 8007e72: 6812 ldr r2, [r2, #0] - 8007e74: 4413 add r3, r2 - 8007e76: f203 4306 addw r3, r3, #1030 ; 0x406 - 8007e7a: 881b ldrh r3, [r3, #0] - 8007e7c: f3c3 0309 ubfx r3, r3, #0, #10 - 8007e80: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 + 8008804: 687b ldr r3, [r7, #4] + 8008806: 681b ldr r3, [r3, #0] + 8008808: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800880c: b29b uxth r3, r3 + 800880e: 461a mov r2, r3 + 8008810: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008812: 781b ldrb r3, [r3, #0] + 8008814: 00db lsls r3, r3, #3 + 8008816: 4413 add r3, r2 + 8008818: 687a ldr r2, [r7, #4] + 800881a: 6812 ldr r2, [r2, #0] + 800881c: 4413 add r3, r2 + 800881e: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008822: 881b ldrh r3, [r3, #0] + 8008824: f3c3 0309 ubfx r3, r3, #0, #10 + 8008828: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 if (count != 0U) - 8007e84: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007e88: 2b00 cmp r3, #0 - 8007e8a: f000 808e beq.w 8007faa + 800882c: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 8008830: 2b00 cmp r3, #0 + 8008832: f000 808e beq.w 8008952 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - 8007e8e: 687b ldr r3, [r7, #4] - 8007e90: 6818 ldr r0, [r3, #0] - 8007e92: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007e94: 6959 ldr r1, [r3, #20] - 8007e96: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007e98: 88da ldrh r2, [r3, #6] - 8007e9a: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007e9e: f006 fcbc bl 800e81a - 8007ea2: e082 b.n 8007faa + 8008836: 687b ldr r3, [r7, #4] + 8008838: 6818 ldr r0, [r3, #0] + 800883a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800883c: 6959 ldr r1, [r3, #20] + 800883e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008840: 88da ldrh r2, [r3, #6] + 8008842: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 8008846: f007 f940 bl 800faca + 800884a: e082 b.n 8008952 } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* manage double buffer bulk out */ if (ep->type == EP_TYPE_BULK) - 8007ea4: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007ea6: 78db ldrb r3, [r3, #3] - 8007ea8: 2b02 cmp r3, #2 - 8007eaa: d10a bne.n 8007ec2 + 800884c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800884e: 78db ldrb r3, [r3, #3] + 8008850: 2b02 cmp r3, #2 + 8008852: d10a bne.n 800886a { count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); - 8007eac: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8007eb0: 461a mov r2, r3 - 8007eb2: 6d79 ldr r1, [r7, #84] ; 0x54 - 8007eb4: 6878 ldr r0, [r7, #4] - 8007eb6: f000 f9d3 bl 8008260 - 8007eba: 4603 mov r3, r0 - 8007ebc: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 - 8007ec0: e073 b.n 8007faa + 8008854: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008858: 461a mov r2, r3 + 800885a: 6d79 ldr r1, [r7, #84] ; 0x54 + 800885c: 6878 ldr r0, [r7, #4] + 800885e: f000 f9d3 bl 8008c08 + 8008862: 4603 mov r3, r0 + 8008864: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 + 8008868: e073 b.n 8008952 } else /* manage double buffer iso out */ { /* free EP OUT Buffer */ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - 8007ec2: 687b ldr r3, [r7, #4] - 8007ec4: 681b ldr r3, [r3, #0] - 8007ec6: 461a mov r2, r3 - 8007ec8: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007eca: 781b ldrb r3, [r3, #0] - 8007ecc: 009b lsls r3, r3, #2 - 8007ece: 4413 add r3, r2 - 8007ed0: 881b ldrh r3, [r3, #0] - 8007ed2: b29b uxth r3, r3 - 8007ed4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8007ed8: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8007edc: f8a7 3052 strh.w r3, [r7, #82] ; 0x52 - 8007ee0: 687b ldr r3, [r7, #4] - 8007ee2: 681b ldr r3, [r3, #0] - 8007ee4: 461a mov r2, r3 - 8007ee6: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007ee8: 781b ldrb r3, [r3, #0] - 8007eea: 009b lsls r3, r3, #2 - 8007eec: 441a add r2, r3 - 8007eee: f8b7 3052 ldrh.w r3, [r7, #82] ; 0x52 - 8007ef2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8007ef6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8007efa: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8007efe: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 8007f02: b29b uxth r3, r3 - 8007f04: 8013 strh r3, [r2, #0] + 800886a: 687b ldr r3, [r7, #4] + 800886c: 681b ldr r3, [r3, #0] + 800886e: 461a mov r2, r3 + 8008870: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008872: 781b ldrb r3, [r3, #0] + 8008874: 009b lsls r3, r3, #2 + 8008876: 4413 add r3, r2 + 8008878: 881b ldrh r3, [r3, #0] + 800887a: b29b uxth r3, r3 + 800887c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8008880: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008884: f8a7 3052 strh.w r3, [r7, #82] ; 0x52 + 8008888: 687b ldr r3, [r7, #4] + 800888a: 681b ldr r3, [r3, #0] + 800888c: 461a mov r2, r3 + 800888e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008890: 781b ldrb r3, [r3, #0] + 8008892: 009b lsls r3, r3, #2 + 8008894: 441a add r2, r3 + 8008896: f8b7 3052 ldrh.w r3, [r7, #82] ; 0x52 + 800889a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800889e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 80088a2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80088a6: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 80088aa: b29b uxth r3, r3 + 80088ac: 8013 strh r3, [r2, #0] if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) - 8007f06: 687b ldr r3, [r7, #4] - 8007f08: 681b ldr r3, [r3, #0] - 8007f0a: 461a mov r2, r3 - 8007f0c: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f0e: 781b ldrb r3, [r3, #0] - 8007f10: 009b lsls r3, r3, #2 - 8007f12: 4413 add r3, r2 - 8007f14: 881b ldrh r3, [r3, #0] - 8007f16: b29b uxth r3, r3 - 8007f18: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8007f1c: 2b00 cmp r3, #0 - 8007f1e: d022 beq.n 8007f66 + 80088ae: 687b ldr r3, [r7, #4] + 80088b0: 681b ldr r3, [r3, #0] + 80088b2: 461a mov r2, r3 + 80088b4: 6d7b ldr r3, [r7, #84] ; 0x54 + 80088b6: 781b ldrb r3, [r3, #0] + 80088b8: 009b lsls r3, r3, #2 + 80088ba: 4413 add r3, r2 + 80088bc: 881b ldrh r3, [r3, #0] + 80088be: b29b uxth r3, r3 + 80088c0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80088c4: 2b00 cmp r3, #0 + 80088c6: d022 beq.n 800890e { /* read from endpoint BUF0Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - 8007f20: 687b ldr r3, [r7, #4] - 8007f22: 681b ldr r3, [r3, #0] - 8007f24: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007f28: b29b uxth r3, r3 - 8007f2a: 461a mov r2, r3 - 8007f2c: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f2e: 781b ldrb r3, [r3, #0] - 8007f30: 00db lsls r3, r3, #3 - 8007f32: 4413 add r3, r2 - 8007f34: 687a ldr r2, [r7, #4] - 8007f36: 6812 ldr r2, [r2, #0] - 8007f38: 4413 add r3, r2 - 8007f3a: f203 4302 addw r3, r3, #1026 ; 0x402 - 8007f3e: 881b ldrh r3, [r3, #0] - 8007f40: f3c3 0309 ubfx r3, r3, #0, #10 - 8007f44: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 + 80088c8: 687b ldr r3, [r7, #4] + 80088ca: 681b ldr r3, [r3, #0] + 80088cc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80088d0: b29b uxth r3, r3 + 80088d2: 461a mov r2, r3 + 80088d4: 6d7b ldr r3, [r7, #84] ; 0x54 + 80088d6: 781b ldrb r3, [r3, #0] + 80088d8: 00db lsls r3, r3, #3 + 80088da: 4413 add r3, r2 + 80088dc: 687a ldr r2, [r7, #4] + 80088de: 6812 ldr r2, [r2, #0] + 80088e0: 4413 add r3, r2 + 80088e2: f203 4302 addw r3, r3, #1026 ; 0x402 + 80088e6: 881b ldrh r3, [r3, #0] + 80088e8: f3c3 0309 ubfx r3, r3, #0, #10 + 80088ec: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 if (count != 0U) - 8007f48: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007f4c: 2b00 cmp r3, #0 - 8007f4e: d02c beq.n 8007faa + 80088f0: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 80088f4: 2b00 cmp r3, #0 + 80088f6: d02c beq.n 8008952 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - 8007f50: 687b ldr r3, [r7, #4] - 8007f52: 6818 ldr r0, [r3, #0] - 8007f54: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f56: 6959 ldr r1, [r3, #20] - 8007f58: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f5a: 891a ldrh r2, [r3, #8] - 8007f5c: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007f60: f006 fc5b bl 800e81a - 8007f64: e021 b.n 8007faa + 80088f8: 687b ldr r3, [r7, #4] + 80088fa: 6818 ldr r0, [r3, #0] + 80088fc: 6d7b ldr r3, [r7, #84] ; 0x54 + 80088fe: 6959 ldr r1, [r3, #20] + 8008900: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008902: 891a ldrh r2, [r3, #8] + 8008904: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 8008908: f007 f8df bl 800faca + 800890c: e021 b.n 8008952 } } else { /* read from endpoint BUF1Addr buffer */ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - 8007f66: 687b ldr r3, [r7, #4] - 8007f68: 681b ldr r3, [r3, #0] - 8007f6a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8007f6e: b29b uxth r3, r3 - 8007f70: 461a mov r2, r3 - 8007f72: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f74: 781b ldrb r3, [r3, #0] - 8007f76: 00db lsls r3, r3, #3 - 8007f78: 4413 add r3, r2 - 8007f7a: 687a ldr r2, [r7, #4] - 8007f7c: 6812 ldr r2, [r2, #0] - 8007f7e: 4413 add r3, r2 - 8007f80: f203 4306 addw r3, r3, #1030 ; 0x406 - 8007f84: 881b ldrh r3, [r3, #0] - 8007f86: f3c3 0309 ubfx r3, r3, #0, #10 - 8007f8a: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 + 800890e: 687b ldr r3, [r7, #4] + 8008910: 681b ldr r3, [r3, #0] + 8008912: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008916: b29b uxth r3, r3 + 8008918: 461a mov r2, r3 + 800891a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800891c: 781b ldrb r3, [r3, #0] + 800891e: 00db lsls r3, r3, #3 + 8008920: 4413 add r3, r2 + 8008922: 687a ldr r2, [r7, #4] + 8008924: 6812 ldr r2, [r2, #0] + 8008926: 4413 add r3, r2 + 8008928: f203 4306 addw r3, r3, #1030 ; 0x406 + 800892c: 881b ldrh r3, [r3, #0] + 800892e: f3c3 0309 ubfx r3, r3, #0, #10 + 8008932: f8a7 3050 strh.w r3, [r7, #80] ; 0x50 if (count != 0U) - 8007f8e: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007f92: 2b00 cmp r3, #0 - 8007f94: d009 beq.n 8007faa + 8008936: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 800893a: 2b00 cmp r3, #0 + 800893c: d009 beq.n 8008952 { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - 8007f96: 687b ldr r3, [r7, #4] - 8007f98: 6818 ldr r0, [r3, #0] - 8007f9a: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007f9c: 6959 ldr r1, [r3, #20] - 8007f9e: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fa0: 895a ldrh r2, [r3, #10] - 8007fa2: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007fa6: f006 fc38 bl 800e81a + 800893e: 687b ldr r3, [r7, #4] + 8008940: 6818 ldr r0, [r3, #0] + 8008942: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008944: 6959 ldr r1, [r3, #20] + 8008946: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008948: 895a ldrh r2, [r3, #10] + 800894a: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 800894e: f007 f8bc bl 800faca } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - 8007faa: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fac: 69da ldr r2, [r3, #28] - 8007fae: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007fb2: 441a add r2, r3 - 8007fb4: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fb6: 61da str r2, [r3, #28] + 8008952: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008954: 69da ldr r2, [r3, #28] + 8008956: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 800895a: 441a add r2, r3 + 800895c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800895e: 61da str r2, [r3, #28] ep->xfer_buff += count; - 8007fb8: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fba: 695a ldr r2, [r3, #20] - 8007fbc: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 - 8007fc0: 441a add r2, r3 - 8007fc2: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fc4: 615a str r2, [r3, #20] + 8008960: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008962: 695a ldr r2, [r3, #20] + 8008964: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50 + 8008968: 441a add r2, r3 + 800896a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800896c: 615a str r2, [r3, #20] if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) - 8007fc6: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fc8: 699b ldr r3, [r3, #24] - 8007fca: 2b00 cmp r3, #0 - 8007fcc: d005 beq.n 8007fda - 8007fce: f8b7 2050 ldrh.w r2, [r7, #80] ; 0x50 - 8007fd2: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fd4: 691b ldr r3, [r3, #16] - 8007fd6: 429a cmp r2, r3 - 8007fd8: d206 bcs.n 8007fe8 + 800896e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008970: 699b ldr r3, [r3, #24] + 8008972: 2b00 cmp r3, #0 + 8008974: d005 beq.n 8008982 + 8008976: f8b7 2050 ldrh.w r2, [r7, #80] ; 0x50 + 800897a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800897c: 691b ldr r3, [r3, #16] + 800897e: 429a cmp r2, r3 + 8008980: d206 bcs.n 8008990 { /* RX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, ep->num); #else HAL_PCD_DataOutStageCallback(hpcd, ep->num); - 8007fda: 6d7b ldr r3, [r7, #84] ; 0x54 - 8007fdc: 781b ldrb r3, [r3, #0] - 8007fde: 4619 mov r1, r3 - 8007fe0: 6878 ldr r0, [r7, #4] - 8007fe2: f008 fa85 bl 80104f0 - 8007fe6: e005 b.n 8007ff4 + 8008982: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008984: 781b ldrb r3, [r3, #0] + 8008986: 4619 mov r1, r3 + 8008988: 6878 ldr r0, [r7, #4] + 800898a: f009 ffdf bl 801294c + 800898e: e005 b.n 800899c #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { (void)USB_EPStartXfer(hpcd->Instance, ep); - 8007fe8: 687b ldr r3, [r7, #4] - 8007fea: 681b ldr r3, [r3, #0] - 8007fec: 6d79 ldr r1, [r7, #84] ; 0x54 - 8007fee: 4618 mov r0, r3 - 8007ff0: f004 fec5 bl 800cd7e + 8008990: 687b ldr r3, [r7, #4] + 8008992: 681b ldr r3, [r3, #0] + 8008994: 6d79 ldr r1, [r7, #84] ; 0x54 + 8008996: 4618 mov r0, r3 + 8008998: f005 fb49 bl 800e02e } } if ((wEPVal & USB_EP_CTR_TX) != 0U) - 8007ff4: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8007ff8: f003 0380 and.w r3, r3, #128 ; 0x80 - 8007ffc: 2b00 cmp r3, #0 - 8007ffe: f000 8121 beq.w 8008244 + 800899c: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 80089a0: f003 0380 and.w r3, r3, #128 ; 0x80 + 80089a4: 2b00 cmp r3, #0 + 80089a6: f000 8121 beq.w 8008bec { ep = &hpcd->IN_ep[epindex]; - 8008002: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8008006: 1c5a adds r2, r3, #1 - 8008008: 4613 mov r3, r2 - 800800a: 009b lsls r3, r3, #2 - 800800c: 4413 add r3, r2 - 800800e: 00db lsls r3, r3, #3 - 8008010: 687a ldr r2, [r7, #4] - 8008012: 4413 add r3, r2 - 8008014: 657b str r3, [r7, #84] ; 0x54 + 80089aa: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80089ae: 1c5a adds r2, r3, #1 + 80089b0: 4613 mov r3, r2 + 80089b2: 009b lsls r3, r3, #2 + 80089b4: 4413 add r3, r2 + 80089b6: 00db lsls r3, r3, #3 + 80089b8: 687a ldr r2, [r7, #4] + 80089ba: 4413 add r3, r2 + 80089bc: 657b str r3, [r7, #84] ; 0x54 /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - 8008016: 687b ldr r3, [r7, #4] - 8008018: 681b ldr r3, [r3, #0] - 800801a: 461a mov r2, r3 - 800801c: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 8008020: 009b lsls r3, r3, #2 - 8008022: 4413 add r3, r2 - 8008024: 881b ldrh r3, [r3, #0] - 8008026: b29b uxth r3, r3 - 8008028: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 - 800802c: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8008030: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 - 8008034: 687b ldr r3, [r7, #4] - 8008036: 681b ldr r3, [r3, #0] - 8008038: 461a mov r2, r3 - 800803a: f897 304d ldrb.w r3, [r7, #77] ; 0x4d - 800803e: 009b lsls r3, r3, #2 - 8008040: 441a add r2, r3 - 8008042: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 - 8008046: ea6f 4343 mvn.w r3, r3, lsl #17 - 800804a: ea6f 4353 mvn.w r3, r3, lsr #17 - 800804e: b29b uxth r3, r3 - 8008050: 8013 strh r3, [r2, #0] + 80089be: 687b ldr r3, [r7, #4] + 80089c0: 681b ldr r3, [r3, #0] + 80089c2: 461a mov r2, r3 + 80089c4: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80089c8: 009b lsls r3, r3, #2 + 80089ca: 4413 add r3, r2 + 80089cc: 881b ldrh r3, [r3, #0] + 80089ce: b29b uxth r3, r3 + 80089d0: f423 43e1 bic.w r3, r3, #28800 ; 0x7080 + 80089d4: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80089d8: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + 80089dc: 687b ldr r3, [r7, #4] + 80089de: 681b ldr r3, [r3, #0] + 80089e0: 461a mov r2, r3 + 80089e2: f897 304d ldrb.w r3, [r7, #77] ; 0x4d + 80089e6: 009b lsls r3, r3, #2 + 80089e8: 441a add r2, r3 + 80089ea: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 80089ee: ea6f 4343 mvn.w r3, r3, lsl #17 + 80089f2: ea6f 4353 mvn.w r3, r3, lsr #17 + 80089f6: b29b uxth r3, r3 + 80089f8: 8013 strh r3, [r2, #0] if (ep->type == EP_TYPE_ISOC) - 8008052: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008054: 78db ldrb r3, [r3, #3] - 8008056: 2b01 cmp r3, #1 - 8008058: f040 80a2 bne.w 80081a0 + 80089fa: 6d7b ldr r3, [r7, #84] ; 0x54 + 80089fc: 78db ldrb r3, [r3, #3] + 80089fe: 2b01 cmp r3, #1 + 8008a00: f040 80a2 bne.w 8008b48 { ep->xfer_len = 0U; - 800805c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800805e: 2200 movs r2, #0 - 8008060: 619a str r2, [r3, #24] + 8008a04: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a06: 2200 movs r2, #0 + 8008a08: 619a str r2, [r3, #24] #if (USE_USB_DOUBLE_BUFFER == 1U) if (ep->doublebuffer != 0U) - 8008062: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008064: 7b1b ldrb r3, [r3, #12] - 8008066: 2b00 cmp r3, #0 - 8008068: f000 8093 beq.w 8008192 + 8008a0a: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a0c: 7b1b ldrb r3, [r3, #12] + 8008a0e: 2b00 cmp r3, #0 + 8008a10: f000 8093 beq.w 8008b3a { if ((wEPVal & USB_EP_DTOG_TX) != 0U) - 800806c: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 8008070: f003 0340 and.w r3, r3, #64 ; 0x40 - 8008074: 2b00 cmp r3, #0 - 8008076: d046 beq.n 8008106 + 8008a14: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008a18: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008a1c: 2b00 cmp r3, #0 + 8008a1e: d046 beq.n 8008aae { PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 8008078: 6d7b ldr r3, [r7, #84] ; 0x54 - 800807a: 785b ldrb r3, [r3, #1] - 800807c: 2b00 cmp r3, #0 - 800807e: d126 bne.n 80080ce - 8008080: 687b ldr r3, [r7, #4] - 8008082: 681b ldr r3, [r3, #0] - 8008084: 627b str r3, [r7, #36] ; 0x24 - 8008086: 687b ldr r3, [r7, #4] - 8008088: 681b ldr r3, [r3, #0] - 800808a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800808e: b29b uxth r3, r3 - 8008090: 461a mov r2, r3 - 8008092: 6a7b ldr r3, [r7, #36] ; 0x24 - 8008094: 4413 add r3, r2 - 8008096: 627b str r3, [r7, #36] ; 0x24 - 8008098: 6d7b ldr r3, [r7, #84] ; 0x54 - 800809a: 781b ldrb r3, [r3, #0] - 800809c: 00da lsls r2, r3, #3 - 800809e: 6a7b ldr r3, [r7, #36] ; 0x24 - 80080a0: 4413 add r3, r2 - 80080a2: f203 4302 addw r3, r3, #1026 ; 0x402 - 80080a6: 623b str r3, [r7, #32] - 80080a8: 6a3b ldr r3, [r7, #32] - 80080aa: 881b ldrh r3, [r3, #0] - 80080ac: b29b uxth r3, r3 - 80080ae: f3c3 0309 ubfx r3, r3, #0, #10 - 80080b2: b29a uxth r2, r3 - 80080b4: 6a3b ldr r3, [r7, #32] - 80080b6: 801a strh r2, [r3, #0] - 80080b8: 6a3b ldr r3, [r7, #32] - 80080ba: 881b ldrh r3, [r3, #0] - 80080bc: b29b uxth r3, r3 - 80080be: ea6f 4343 mvn.w r3, r3, lsl #17 - 80080c2: ea6f 4353 mvn.w r3, r3, lsr #17 - 80080c6: b29a uxth r2, r3 - 80080c8: 6a3b ldr r3, [r7, #32] - 80080ca: 801a strh r2, [r3, #0] - 80080cc: e061 b.n 8008192 - 80080ce: 6d7b ldr r3, [r7, #84] ; 0x54 - 80080d0: 785b ldrb r3, [r3, #1] - 80080d2: 2b01 cmp r3, #1 - 80080d4: d15d bne.n 8008192 - 80080d6: 687b ldr r3, [r7, #4] - 80080d8: 681b ldr r3, [r3, #0] - 80080da: 62fb str r3, [r7, #44] ; 0x2c - 80080dc: 687b ldr r3, [r7, #4] - 80080de: 681b ldr r3, [r3, #0] - 80080e0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 80080e4: b29b uxth r3, r3 - 80080e6: 461a mov r2, r3 - 80080e8: 6afb ldr r3, [r7, #44] ; 0x2c - 80080ea: 4413 add r3, r2 - 80080ec: 62fb str r3, [r7, #44] ; 0x2c - 80080ee: 6d7b ldr r3, [r7, #84] ; 0x54 - 80080f0: 781b ldrb r3, [r3, #0] - 80080f2: 00da lsls r2, r3, #3 - 80080f4: 6afb ldr r3, [r7, #44] ; 0x2c - 80080f6: 4413 add r3, r2 - 80080f8: f203 4302 addw r3, r3, #1026 ; 0x402 - 80080fc: 62bb str r3, [r7, #40] ; 0x28 - 80080fe: 6abb ldr r3, [r7, #40] ; 0x28 - 8008100: 2200 movs r2, #0 - 8008102: 801a strh r2, [r3, #0] - 8008104: e045 b.n 8008192 + 8008a20: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a22: 785b ldrb r3, [r3, #1] + 8008a24: 2b00 cmp r3, #0 + 8008a26: d126 bne.n 8008a76 + 8008a28: 687b ldr r3, [r7, #4] + 8008a2a: 681b ldr r3, [r3, #0] + 8008a2c: 627b str r3, [r7, #36] ; 0x24 + 8008a2e: 687b ldr r3, [r7, #4] + 8008a30: 681b ldr r3, [r3, #0] + 8008a32: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008a36: b29b uxth r3, r3 + 8008a38: 461a mov r2, r3 + 8008a3a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008a3c: 4413 add r3, r2 + 8008a3e: 627b str r3, [r7, #36] ; 0x24 + 8008a40: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a42: 781b ldrb r3, [r3, #0] + 8008a44: 00da lsls r2, r3, #3 + 8008a46: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008a48: 4413 add r3, r2 + 8008a4a: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008a4e: 623b str r3, [r7, #32] + 8008a50: 6a3b ldr r3, [r7, #32] + 8008a52: 881b ldrh r3, [r3, #0] + 8008a54: b29b uxth r3, r3 + 8008a56: f3c3 0309 ubfx r3, r3, #0, #10 + 8008a5a: b29a uxth r2, r3 + 8008a5c: 6a3b ldr r3, [r7, #32] + 8008a5e: 801a strh r2, [r3, #0] + 8008a60: 6a3b ldr r3, [r7, #32] + 8008a62: 881b ldrh r3, [r3, #0] + 8008a64: b29b uxth r3, r3 + 8008a66: ea6f 4343 mvn.w r3, r3, lsl #17 + 8008a6a: ea6f 4353 mvn.w r3, r3, lsr #17 + 8008a6e: b29a uxth r2, r3 + 8008a70: 6a3b ldr r3, [r7, #32] + 8008a72: 801a strh r2, [r3, #0] + 8008a74: e061 b.n 8008b3a + 8008a76: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a78: 785b ldrb r3, [r3, #1] + 8008a7a: 2b01 cmp r3, #1 + 8008a7c: d15d bne.n 8008b3a + 8008a7e: 687b ldr r3, [r7, #4] + 8008a80: 681b ldr r3, [r3, #0] + 8008a82: 62fb str r3, [r7, #44] ; 0x2c + 8008a84: 687b ldr r3, [r7, #4] + 8008a86: 681b ldr r3, [r3, #0] + 8008a88: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008a8c: b29b uxth r3, r3 + 8008a8e: 461a mov r2, r3 + 8008a90: 6afb ldr r3, [r7, #44] ; 0x2c + 8008a92: 4413 add r3, r2 + 8008a94: 62fb str r3, [r7, #44] ; 0x2c + 8008a96: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008a98: 781b ldrb r3, [r3, #0] + 8008a9a: 00da lsls r2, r3, #3 + 8008a9c: 6afb ldr r3, [r7, #44] ; 0x2c + 8008a9e: 4413 add r3, r2 + 8008aa0: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008aa4: 62bb str r3, [r7, #40] ; 0x28 + 8008aa6: 6abb ldr r3, [r7, #40] ; 0x28 + 8008aa8: 2200 movs r2, #0 + 8008aaa: 801a strh r2, [r3, #0] + 8008aac: e045 b.n 8008b3a } else { PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 8008106: 687b ldr r3, [r7, #4] - 8008108: 681b ldr r3, [r3, #0] - 800810a: 63fb str r3, [r7, #60] ; 0x3c - 800810c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800810e: 785b ldrb r3, [r3, #1] - 8008110: 2b00 cmp r3, #0 - 8008112: d126 bne.n 8008162 - 8008114: 687b ldr r3, [r7, #4] - 8008116: 681b ldr r3, [r3, #0] - 8008118: 637b str r3, [r7, #52] ; 0x34 - 800811a: 687b ldr r3, [r7, #4] - 800811c: 681b ldr r3, [r3, #0] - 800811e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008122: b29b uxth r3, r3 - 8008124: 461a mov r2, r3 - 8008126: 6b7b ldr r3, [r7, #52] ; 0x34 - 8008128: 4413 add r3, r2 - 800812a: 637b str r3, [r7, #52] ; 0x34 - 800812c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800812e: 781b ldrb r3, [r3, #0] - 8008130: 00da lsls r2, r3, #3 - 8008132: 6b7b ldr r3, [r7, #52] ; 0x34 - 8008134: 4413 add r3, r2 - 8008136: f203 4306 addw r3, r3, #1030 ; 0x406 - 800813a: 633b str r3, [r7, #48] ; 0x30 - 800813c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800813e: 881b ldrh r3, [r3, #0] - 8008140: b29b uxth r3, r3 - 8008142: f3c3 0309 ubfx r3, r3, #0, #10 - 8008146: b29a uxth r2, r3 - 8008148: 6b3b ldr r3, [r7, #48] ; 0x30 - 800814a: 801a strh r2, [r3, #0] - 800814c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800814e: 881b ldrh r3, [r3, #0] - 8008150: b29b uxth r3, r3 - 8008152: ea6f 4343 mvn.w r3, r3, lsl #17 - 8008156: ea6f 4353 mvn.w r3, r3, lsr #17 - 800815a: b29a uxth r2, r3 - 800815c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800815e: 801a strh r2, [r3, #0] - 8008160: e017 b.n 8008192 - 8008162: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008164: 785b ldrb r3, [r3, #1] - 8008166: 2b01 cmp r3, #1 - 8008168: d113 bne.n 8008192 - 800816a: 687b ldr r3, [r7, #4] - 800816c: 681b ldr r3, [r3, #0] - 800816e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008172: b29b uxth r3, r3 - 8008174: 461a mov r2, r3 - 8008176: 6bfb ldr r3, [r7, #60] ; 0x3c - 8008178: 4413 add r3, r2 - 800817a: 63fb str r3, [r7, #60] ; 0x3c - 800817c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800817e: 781b ldrb r3, [r3, #0] - 8008180: 00da lsls r2, r3, #3 - 8008182: 6bfb ldr r3, [r7, #60] ; 0x3c - 8008184: 4413 add r3, r2 - 8008186: f203 4306 addw r3, r3, #1030 ; 0x406 - 800818a: 63bb str r3, [r7, #56] ; 0x38 - 800818c: 6bbb ldr r3, [r7, #56] ; 0x38 - 800818e: 2200 movs r2, #0 - 8008190: 801a strh r2, [r3, #0] + 8008aae: 687b ldr r3, [r7, #4] + 8008ab0: 681b ldr r3, [r3, #0] + 8008ab2: 63fb str r3, [r7, #60] ; 0x3c + 8008ab4: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008ab6: 785b ldrb r3, [r3, #1] + 8008ab8: 2b00 cmp r3, #0 + 8008aba: d126 bne.n 8008b0a + 8008abc: 687b ldr r3, [r7, #4] + 8008abe: 681b ldr r3, [r3, #0] + 8008ac0: 637b str r3, [r7, #52] ; 0x34 + 8008ac2: 687b ldr r3, [r7, #4] + 8008ac4: 681b ldr r3, [r3, #0] + 8008ac6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008aca: b29b uxth r3, r3 + 8008acc: 461a mov r2, r3 + 8008ace: 6b7b ldr r3, [r7, #52] ; 0x34 + 8008ad0: 4413 add r3, r2 + 8008ad2: 637b str r3, [r7, #52] ; 0x34 + 8008ad4: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008ad6: 781b ldrb r3, [r3, #0] + 8008ad8: 00da lsls r2, r3, #3 + 8008ada: 6b7b ldr r3, [r7, #52] ; 0x34 + 8008adc: 4413 add r3, r2 + 8008ade: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008ae2: 633b str r3, [r7, #48] ; 0x30 + 8008ae4: 6b3b ldr r3, [r7, #48] ; 0x30 + 8008ae6: 881b ldrh r3, [r3, #0] + 8008ae8: b29b uxth r3, r3 + 8008aea: f3c3 0309 ubfx r3, r3, #0, #10 + 8008aee: b29a uxth r2, r3 + 8008af0: 6b3b ldr r3, [r7, #48] ; 0x30 + 8008af2: 801a strh r2, [r3, #0] + 8008af4: 6b3b ldr r3, [r7, #48] ; 0x30 + 8008af6: 881b ldrh r3, [r3, #0] + 8008af8: b29b uxth r3, r3 + 8008afa: ea6f 4343 mvn.w r3, r3, lsl #17 + 8008afe: ea6f 4353 mvn.w r3, r3, lsr #17 + 8008b02: b29a uxth r2, r3 + 8008b04: 6b3b ldr r3, [r7, #48] ; 0x30 + 8008b06: 801a strh r2, [r3, #0] + 8008b08: e017 b.n 8008b3a + 8008b0a: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b0c: 785b ldrb r3, [r3, #1] + 8008b0e: 2b01 cmp r3, #1 + 8008b10: d113 bne.n 8008b3a + 8008b12: 687b ldr r3, [r7, #4] + 8008b14: 681b ldr r3, [r3, #0] + 8008b16: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008b1a: b29b uxth r3, r3 + 8008b1c: 461a mov r2, r3 + 8008b1e: 6bfb ldr r3, [r7, #60] ; 0x3c + 8008b20: 4413 add r3, r2 + 8008b22: 63fb str r3, [r7, #60] ; 0x3c + 8008b24: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b26: 781b ldrb r3, [r3, #0] + 8008b28: 00da lsls r2, r3, #3 + 8008b2a: 6bfb ldr r3, [r7, #60] ; 0x3c + 8008b2c: 4413 add r3, r2 + 8008b2e: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008b32: 63bb str r3, [r7, #56] ; 0x38 + 8008b34: 6bbb ldr r3, [r7, #56] ; 0x38 + 8008b36: 2200 movs r2, #0 + 8008b38: 801a strh r2, [r3, #0] /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); - 8008192: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008194: 781b ldrb r3, [r3, #0] - 8008196: 4619 mov r1, r3 - 8008198: 6878 ldr r0, [r7, #4] - 800819a: f008 f9c4 bl 8010526 - 800819e: e051 b.n 8008244 + 8008b3a: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b3c: 781b ldrb r3, [r3, #0] + 8008b3e: 4619 mov r1, r3 + 8008b40: 6878 ldr r0, [r7, #4] + 8008b42: f009 ff1e bl 8012982 + 8008b46: e051 b.n 8008bec #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) - 80081a0: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 80081a4: f403 7380 and.w r3, r3, #256 ; 0x100 - 80081a8: 2b00 cmp r3, #0 - 80081aa: d144 bne.n 8008236 + 8008b48: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008b4c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8008b50: 2b00 cmp r3, #0 + 8008b52: d144 bne.n 8008bde { /* multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - 80081ac: 687b ldr r3, [r7, #4] - 80081ae: 681b ldr r3, [r3, #0] - 80081b0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 80081b4: b29b uxth r3, r3 - 80081b6: 461a mov r2, r3 - 80081b8: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081ba: 781b ldrb r3, [r3, #0] - 80081bc: 00db lsls r3, r3, #3 - 80081be: 4413 add r3, r2 - 80081c0: 687a ldr r2, [r7, #4] - 80081c2: 6812 ldr r2, [r2, #0] - 80081c4: 4413 add r3, r2 - 80081c6: f203 4302 addw r3, r3, #1026 ; 0x402 - 80081ca: 881b ldrh r3, [r3, #0] - 80081cc: f3c3 0309 ubfx r3, r3, #0, #10 - 80081d0: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + 8008b54: 687b ldr r3, [r7, #4] + 8008b56: 681b ldr r3, [r3, #0] + 8008b58: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008b5c: b29b uxth r3, r3 + 8008b5e: 461a mov r2, r3 + 8008b60: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b62: 781b ldrb r3, [r3, #0] + 8008b64: 00db lsls r3, r3, #3 + 8008b66: 4413 add r3, r2 + 8008b68: 687a ldr r2, [r7, #4] + 8008b6a: 6812 ldr r2, [r2, #0] + 8008b6c: 4413 add r3, r2 + 8008b6e: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008b72: 881b ldrh r3, [r3, #0] + 8008b74: f3c3 0309 ubfx r3, r3, #0, #10 + 8008b78: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 if (ep->xfer_len > TxPctSize) - 80081d4: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081d6: 699a ldr r2, [r3, #24] - 80081d8: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 - 80081dc: 429a cmp r2, r3 - 80081de: d907 bls.n 80081f0 + 8008b7c: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b7e: 699a ldr r2, [r3, #24] + 8008b80: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8008b84: 429a cmp r2, r3 + 8008b86: d907 bls.n 8008b98 { ep->xfer_len -= TxPctSize; - 80081e0: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081e2: 699a ldr r2, [r3, #24] - 80081e4: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 - 80081e8: 1ad2 subs r2, r2, r3 - 80081ea: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081ec: 619a str r2, [r3, #24] - 80081ee: e002 b.n 80081f6 + 8008b88: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b8a: 699a ldr r2, [r3, #24] + 8008b8c: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8008b90: 1ad2 subs r2, r2, r3 + 8008b92: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b94: 619a str r2, [r3, #24] + 8008b96: e002 b.n 8008b9e } else { ep->xfer_len = 0U; - 80081f0: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081f2: 2200 movs r2, #0 - 80081f4: 619a str r2, [r3, #24] + 8008b98: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008b9a: 2200 movs r2, #0 + 8008b9c: 619a str r2, [r3, #24] } /* Zero Length Packet? */ if (ep->xfer_len == 0U) - 80081f6: 6d7b ldr r3, [r7, #84] ; 0x54 - 80081f8: 699b ldr r3, [r3, #24] - 80081fa: 2b00 cmp r3, #0 - 80081fc: d106 bne.n 800820c + 8008b9e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008ba0: 699b ldr r3, [r3, #24] + 8008ba2: 2b00 cmp r3, #0 + 8008ba4: d106 bne.n 8008bb4 { /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); #else HAL_PCD_DataInStageCallback(hpcd, ep->num); - 80081fe: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008200: 781b ldrb r3, [r3, #0] - 8008202: 4619 mov r1, r3 - 8008204: 6878 ldr r0, [r7, #4] - 8008206: f008 f98e bl 8010526 - 800820a: e01b b.n 8008244 + 8008ba6: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008ba8: 781b ldrb r3, [r3, #0] + 8008baa: 4619 mov r1, r3 + 8008bac: 6878 ldr r0, [r7, #4] + 8008bae: f009 fee8 bl 8012982 + 8008bb2: e01b b.n 8008bec #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } else { /* Transfer is not yet Done */ ep->xfer_buff += TxPctSize; - 800820c: 6d7b ldr r3, [r7, #84] ; 0x54 - 800820e: 695a ldr r2, [r3, #20] - 8008210: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 - 8008214: 441a add r2, r3 - 8008216: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008218: 615a str r2, [r3, #20] + 8008bb4: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008bb6: 695a ldr r2, [r3, #20] + 8008bb8: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8008bbc: 441a add r2, r3 + 8008bbe: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008bc0: 615a str r2, [r3, #20] ep->xfer_count += TxPctSize; - 800821a: 6d7b ldr r3, [r7, #84] ; 0x54 - 800821c: 69da ldr r2, [r3, #28] - 800821e: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 - 8008222: 441a add r2, r3 - 8008224: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008226: 61da str r2, [r3, #28] + 8008bc2: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008bc4: 69da ldr r2, [r3, #28] + 8008bc6: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 8008bca: 441a add r2, r3 + 8008bcc: 6d7b ldr r3, [r7, #84] ; 0x54 + 8008bce: 61da str r2, [r3, #28] (void)USB_EPStartXfer(hpcd->Instance, ep); - 8008228: 687b ldr r3, [r7, #4] - 800822a: 681b ldr r3, [r3, #0] - 800822c: 6d79 ldr r1, [r7, #84] ; 0x54 - 800822e: 4618 mov r0, r3 - 8008230: f004 fda5 bl 800cd7e - 8008234: e006 b.n 8008244 + 8008bd0: 687b ldr r3, [r7, #4] + 8008bd2: 681b ldr r3, [r3, #0] + 8008bd4: 6d79 ldr r1, [r7, #84] ; 0x54 + 8008bd6: 4618 mov r0, r3 + 8008bd8: f005 fa29 bl 800e02e + 8008bdc: e006 b.n 8008bec } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); - 8008236: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 800823a: 461a mov r2, r3 - 800823c: 6d79 ldr r1, [r7, #84] ; 0x54 - 800823e: 6878 ldr r0, [r7, #4] - 8008240: f000 f917 bl 8008472 + 8008bde: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 8008be2: 461a mov r2, r3 + 8008be4: 6d79 ldr r1, [r7, #84] ; 0x54 + 8008be6: 6878 ldr r0, [r7, #4] + 8008be8: f000 f917 bl 8008e1a while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) - 8008244: 687b ldr r3, [r7, #4] - 8008246: 681b ldr r3, [r3, #0] - 8008248: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 800824c: b29b uxth r3, r3 - 800824e: b21b sxth r3, r3 - 8008250: 2b00 cmp r3, #0 - 8008252: f6ff ac45 blt.w 8007ae0 + 8008bec: 687b ldr r3, [r7, #4] + 8008bee: 681b ldr r3, [r3, #0] + 8008bf0: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 8008bf4: b29b uxth r3, r3 + 8008bf6: b21b sxth r3, r3 + 8008bf8: 2b00 cmp r3, #0 + 8008bfa: f6ff ac45 blt.w 8008488 + } + } + } + } + + return HAL_OK; + 8008bfe: 2300 movs r3, #0 +} + 8008c00: 4618 mov r0, r3 + 8008c02: 3758 adds r7, #88 ; 0x58 + 8008c04: 46bd mov sp, r7 + 8008c06: bd80 pop {r7, pc} + +08008c08 : + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + 8008c08: b580 push {r7, lr} + 8008c0a: b088 sub sp, #32 + 8008c0c: af00 add r7, sp, #0 + 8008c0e: 60f8 str r0, [r7, #12] + 8008c10: 60b9 str r1, [r7, #8] + 8008c12: 4613 mov r3, r2 + 8008c14: 80fb strh r3, [r7, #6] + uint16_t count; + + /* Manage Buffer0 OUT */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + 8008c16: 88fb ldrh r3, [r7, #6] + 8008c18: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8008c1c: 2b00 cmp r3, #0 + 8008c1e: d07c beq.n 8008d1a + { + /* Get count of received Data on buffer0 */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + 8008c20: 68fb ldr r3, [r7, #12] + 8008c22: 681b ldr r3, [r3, #0] + 8008c24: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008c28: b29b uxth r3, r3 + 8008c2a: 461a mov r2, r3 + 8008c2c: 68bb ldr r3, [r7, #8] + 8008c2e: 781b ldrb r3, [r3, #0] + 8008c30: 00db lsls r3, r3, #3 + 8008c32: 4413 add r3, r2 + 8008c34: 68fa ldr r2, [r7, #12] + 8008c36: 6812 ldr r2, [r2, #0] + 8008c38: 4413 add r3, r2 + 8008c3a: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008c3e: 881b ldrh r3, [r3, #0] + 8008c40: f3c3 0309 ubfx r3, r3, #0, #10 + 8008c44: 837b strh r3, [r7, #26] + + if (ep->xfer_len >= count) + 8008c46: 68bb ldr r3, [r7, #8] + 8008c48: 699a ldr r2, [r3, #24] + 8008c4a: 8b7b ldrh r3, [r7, #26] + 8008c4c: 429a cmp r2, r3 + 8008c4e: d306 bcc.n 8008c5e + { + ep->xfer_len -= count; + 8008c50: 68bb ldr r3, [r7, #8] + 8008c52: 699a ldr r2, [r3, #24] + 8008c54: 8b7b ldrh r3, [r7, #26] + 8008c56: 1ad2 subs r2, r2, r3 + 8008c58: 68bb ldr r3, [r7, #8] + 8008c5a: 619a str r2, [r3, #24] + 8008c5c: e002 b.n 8008c64 + } + else + { + ep->xfer_len = 0U; + 8008c5e: 68bb ldr r3, [r7, #8] + 8008c60: 2200 movs r2, #0 + 8008c62: 619a str r2, [r3, #24] + } + + if (ep->xfer_len == 0U) + 8008c64: 68bb ldr r3, [r7, #8] + 8008c66: 699b ldr r3, [r3, #24] + 8008c68: 2b00 cmp r3, #0 + 8008c6a: d123 bne.n 8008cb4 + { + /* set NAK to OUT endpoint since double buffer is enabled */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + 8008c6c: 68fb ldr r3, [r7, #12] + 8008c6e: 681b ldr r3, [r3, #0] + 8008c70: 461a mov r2, r3 + 8008c72: 68bb ldr r3, [r7, #8] + 8008c74: 781b ldrb r3, [r3, #0] + 8008c76: 009b lsls r3, r3, #2 + 8008c78: 4413 add r3, r2 + 8008c7a: 881b ldrh r3, [r3, #0] + 8008c7c: b29b uxth r3, r3 + 8008c7e: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8008c82: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008c86: 833b strh r3, [r7, #24] + 8008c88: 8b3b ldrh r3, [r7, #24] + 8008c8a: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 8008c8e: 833b strh r3, [r7, #24] + 8008c90: 68fb ldr r3, [r7, #12] + 8008c92: 681b ldr r3, [r3, #0] + 8008c94: 461a mov r2, r3 + 8008c96: 68bb ldr r3, [r7, #8] + 8008c98: 781b ldrb r3, [r3, #0] + 8008c9a: 009b lsls r3, r3, #2 + 8008c9c: 441a add r2, r3 + 8008c9e: 8b3b ldrh r3, [r7, #24] + 8008ca0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008ca4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008ca8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8008cac: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8008cb0: b29b uxth r3, r3 + 8008cb2: 8013 strh r3, [r2, #0] + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + 8008cb4: 88fb ldrh r3, [r7, #6] + 8008cb6: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008cba: 2b00 cmp r3, #0 + 8008cbc: d01f beq.n 8008cfe + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + 8008cbe: 68fb ldr r3, [r7, #12] + 8008cc0: 681b ldr r3, [r3, #0] + 8008cc2: 461a mov r2, r3 + 8008cc4: 68bb ldr r3, [r7, #8] + 8008cc6: 781b ldrb r3, [r3, #0] + 8008cc8: 009b lsls r3, r3, #2 + 8008cca: 4413 add r3, r2 + 8008ccc: 881b ldrh r3, [r3, #0] + 8008cce: b29b uxth r3, r3 + 8008cd0: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8008cd4: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008cd8: 82fb strh r3, [r7, #22] + 8008cda: 68fb ldr r3, [r7, #12] + 8008cdc: 681b ldr r3, [r3, #0] + 8008cde: 461a mov r2, r3 + 8008ce0: 68bb ldr r3, [r7, #8] + 8008ce2: 781b ldrb r3, [r3, #0] + 8008ce4: 009b lsls r3, r3, #2 + 8008ce6: 441a add r2, r3 + 8008ce8: 8afb ldrh r3, [r7, #22] + 8008cea: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008cee: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008cf2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8008cf6: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 8008cfa: b29b uxth r3, r3 + 8008cfc: 8013 strh r3, [r2, #0] + } + + if (count != 0U) + 8008cfe: 8b7b ldrh r3, [r7, #26] + 8008d00: 2b00 cmp r3, #0 + 8008d02: f000 8085 beq.w 8008e10 + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + 8008d06: 68fb ldr r3, [r7, #12] + 8008d08: 6818 ldr r0, [r3, #0] + 8008d0a: 68bb ldr r3, [r7, #8] + 8008d0c: 6959 ldr r1, [r3, #20] + 8008d0e: 68bb ldr r3, [r7, #8] + 8008d10: 891a ldrh r2, [r3, #8] + 8008d12: 8b7b ldrh r3, [r7, #26] + 8008d14: f006 fed9 bl 800faca + 8008d18: e07a b.n 8008e10 + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + 8008d1a: 68fb ldr r3, [r7, #12] + 8008d1c: 681b ldr r3, [r3, #0] + 8008d1e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008d22: b29b uxth r3, r3 + 8008d24: 461a mov r2, r3 + 8008d26: 68bb ldr r3, [r7, #8] + 8008d28: 781b ldrb r3, [r3, #0] + 8008d2a: 00db lsls r3, r3, #3 + 8008d2c: 4413 add r3, r2 + 8008d2e: 68fa ldr r2, [r7, #12] + 8008d30: 6812 ldr r2, [r2, #0] + 8008d32: 4413 add r3, r2 + 8008d34: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008d38: 881b ldrh r3, [r3, #0] + 8008d3a: f3c3 0309 ubfx r3, r3, #0, #10 + 8008d3e: 837b strh r3, [r7, #26] + + if (ep->xfer_len >= count) + 8008d40: 68bb ldr r3, [r7, #8] + 8008d42: 699a ldr r2, [r3, #24] + 8008d44: 8b7b ldrh r3, [r7, #26] + 8008d46: 429a cmp r2, r3 + 8008d48: d306 bcc.n 8008d58 + { + ep->xfer_len -= count; + 8008d4a: 68bb ldr r3, [r7, #8] + 8008d4c: 699a ldr r2, [r3, #24] + 8008d4e: 8b7b ldrh r3, [r7, #26] + 8008d50: 1ad2 subs r2, r2, r3 + 8008d52: 68bb ldr r3, [r7, #8] + 8008d54: 619a str r2, [r3, #24] + 8008d56: e002 b.n 8008d5e + } + else + { + ep->xfer_len = 0U; + 8008d58: 68bb ldr r3, [r7, #8] + 8008d5a: 2200 movs r2, #0 + 8008d5c: 619a str r2, [r3, #24] + } + + if (ep->xfer_len == 0U) + 8008d5e: 68bb ldr r3, [r7, #8] + 8008d60: 699b ldr r3, [r3, #24] + 8008d62: 2b00 cmp r3, #0 + 8008d64: d123 bne.n 8008dae + { + /* set NAK on the current endpoint */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + 8008d66: 68fb ldr r3, [r7, #12] + 8008d68: 681b ldr r3, [r3, #0] + 8008d6a: 461a mov r2, r3 + 8008d6c: 68bb ldr r3, [r7, #8] + 8008d6e: 781b ldrb r3, [r3, #0] + 8008d70: 009b lsls r3, r3, #2 + 8008d72: 4413 add r3, r2 + 8008d74: 881b ldrh r3, [r3, #0] + 8008d76: b29b uxth r3, r3 + 8008d78: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8008d7c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008d80: 83fb strh r3, [r7, #30] + 8008d82: 8bfb ldrh r3, [r7, #30] + 8008d84: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 8008d88: 83fb strh r3, [r7, #30] + 8008d8a: 68fb ldr r3, [r7, #12] + 8008d8c: 681b ldr r3, [r3, #0] + 8008d8e: 461a mov r2, r3 + 8008d90: 68bb ldr r3, [r7, #8] + 8008d92: 781b ldrb r3, [r3, #0] + 8008d94: 009b lsls r3, r3, #2 + 8008d96: 441a add r2, r3 + 8008d98: 8bfb ldrh r3, [r7, #30] + 8008d9a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008d9e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008da2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8008da6: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8008daa: b29b uxth r3, r3 + 8008dac: 8013 strh r3, [r2, #0] + } + + /*Need to FreeUser Buffer*/ + if ((wEPVal & USB_EP_DTOG_TX) == 0U) + 8008dae: 88fb ldrh r3, [r7, #6] + 8008db0: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008db4: 2b00 cmp r3, #0 + 8008db6: d11f bne.n 8008df8 + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + 8008db8: 68fb ldr r3, [r7, #12] + 8008dba: 681b ldr r3, [r3, #0] + 8008dbc: 461a mov r2, r3 + 8008dbe: 68bb ldr r3, [r7, #8] + 8008dc0: 781b ldrb r3, [r3, #0] + 8008dc2: 009b lsls r3, r3, #2 + 8008dc4: 4413 add r3, r2 + 8008dc6: 881b ldrh r3, [r3, #0] + 8008dc8: b29b uxth r3, r3 + 8008dca: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8008dce: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008dd2: 83bb strh r3, [r7, #28] + 8008dd4: 68fb ldr r3, [r7, #12] + 8008dd6: 681b ldr r3, [r3, #0] + 8008dd8: 461a mov r2, r3 + 8008dda: 68bb ldr r3, [r7, #8] + 8008ddc: 781b ldrb r3, [r3, #0] + 8008dde: 009b lsls r3, r3, #2 + 8008de0: 441a add r2, r3 + 8008de2: 8bbb ldrh r3, [r7, #28] + 8008de4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008de8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008dec: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8008df0: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 8008df4: b29b uxth r3, r3 + 8008df6: 8013 strh r3, [r2, #0] + } + + if (count != 0U) + 8008df8: 8b7b ldrh r3, [r7, #26] + 8008dfa: 2b00 cmp r3, #0 + 8008dfc: d008 beq.n 8008e10 + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + 8008dfe: 68fb ldr r3, [r7, #12] + 8008e00: 6818 ldr r0, [r3, #0] + 8008e02: 68bb ldr r3, [r7, #8] + 8008e04: 6959 ldr r1, [r3, #20] + 8008e06: 68bb ldr r3, [r7, #8] + 8008e08: 895a ldrh r2, [r3, #10] + 8008e0a: 8b7b ldrh r3, [r7, #26] + 8008e0c: f006 fe5d bl 800faca + } + } + + return count; + 8008e10: 8b7b ldrh r3, [r7, #26] +} + 8008e12: 4618 mov r0, r3 + 8008e14: 3720 adds r7, #32 + 8008e16: 46bd mov sp, r7 + 8008e18: bd80 pop {r7, pc} + +08008e1a : + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + 8008e1a: b580 push {r7, lr} + 8008e1c: b0a4 sub sp, #144 ; 0x90 + 8008e1e: af00 add r7, sp, #0 + 8008e20: 60f8 str r0, [r7, #12] + 8008e22: 60b9 str r1, [r7, #8] + 8008e24: 4613 mov r3, r2 + 8008e26: 80fb strh r3, [r7, #6] + uint32_t len; + uint16_t TxPctSize; + + /* Data Buffer0 ACK received */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + 8008e28: 88fb ldrh r3, [r7, #6] + 8008e2a: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008e2e: 2b00 cmp r3, #0 + 8008e30: f000 81db beq.w 80091ea + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + 8008e34: 68fb ldr r3, [r7, #12] + 8008e36: 681b ldr r3, [r3, #0] + 8008e38: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008e3c: b29b uxth r3, r3 + 8008e3e: 461a mov r2, r3 + 8008e40: 68bb ldr r3, [r7, #8] + 8008e42: 781b ldrb r3, [r3, #0] + 8008e44: 00db lsls r3, r3, #3 + 8008e46: 4413 add r3, r2 + 8008e48: 68fa ldr r2, [r7, #12] + 8008e4a: 6812 ldr r2, [r2, #0] + 8008e4c: 4413 add r3, r2 + 8008e4e: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008e52: 881b ldrh r3, [r3, #0] + 8008e54: f3c3 0309 ubfx r3, r3, #0, #10 + 8008e58: f8a7 3086 strh.w r3, [r7, #134] ; 0x86 + + if (ep->xfer_len > TxPctSize) + 8008e5c: 68bb ldr r3, [r7, #8] + 8008e5e: 699a ldr r2, [r3, #24] + 8008e60: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 8008e64: 429a cmp r2, r3 + 8008e66: d907 bls.n 8008e78 + { + ep->xfer_len -= TxPctSize; + 8008e68: 68bb ldr r3, [r7, #8] + 8008e6a: 699a ldr r2, [r3, #24] + 8008e6c: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 8008e70: 1ad2 subs r2, r2, r3 + 8008e72: 68bb ldr r3, [r7, #8] + 8008e74: 619a str r2, [r3, #24] + 8008e76: e002 b.n 8008e7e + } + else + { + ep->xfer_len = 0U; + 8008e78: 68bb ldr r3, [r7, #8] + 8008e7a: 2200 movs r2, #0 + 8008e7c: 619a str r2, [r3, #24] + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + 8008e7e: 68bb ldr r3, [r7, #8] + 8008e80: 699b ldr r3, [r3, #24] + 8008e82: 2b00 cmp r3, #0 + 8008e84: f040 80b9 bne.w 8008ffa + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + 8008e88: 68bb ldr r3, [r7, #8] + 8008e8a: 785b ldrb r3, [r3, #1] + 8008e8c: 2b00 cmp r3, #0 + 8008e8e: d126 bne.n 8008ede + 8008e90: 68fb ldr r3, [r7, #12] + 8008e92: 681b ldr r3, [r3, #0] + 8008e94: 62fb str r3, [r7, #44] ; 0x2c + 8008e96: 68fb ldr r3, [r7, #12] + 8008e98: 681b ldr r3, [r3, #0] + 8008e9a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008e9e: b29b uxth r3, r3 + 8008ea0: 461a mov r2, r3 + 8008ea2: 6afb ldr r3, [r7, #44] ; 0x2c + 8008ea4: 4413 add r3, r2 + 8008ea6: 62fb str r3, [r7, #44] ; 0x2c + 8008ea8: 68bb ldr r3, [r7, #8] + 8008eaa: 781b ldrb r3, [r3, #0] + 8008eac: 00da lsls r2, r3, #3 + 8008eae: 6afb ldr r3, [r7, #44] ; 0x2c + 8008eb0: 4413 add r3, r2 + 8008eb2: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008eb6: 62bb str r3, [r7, #40] ; 0x28 + 8008eb8: 6abb ldr r3, [r7, #40] ; 0x28 + 8008eba: 881b ldrh r3, [r3, #0] + 8008ebc: b29b uxth r3, r3 + 8008ebe: f3c3 0309 ubfx r3, r3, #0, #10 + 8008ec2: b29a uxth r2, r3 + 8008ec4: 6abb ldr r3, [r7, #40] ; 0x28 + 8008ec6: 801a strh r2, [r3, #0] + 8008ec8: 6abb ldr r3, [r7, #40] ; 0x28 + 8008eca: 881b ldrh r3, [r3, #0] + 8008ecc: b29b uxth r3, r3 + 8008ece: ea6f 4343 mvn.w r3, r3, lsl #17 + 8008ed2: ea6f 4353 mvn.w r3, r3, lsr #17 + 8008ed6: b29a uxth r2, r3 + 8008ed8: 6abb ldr r3, [r7, #40] ; 0x28 + 8008eda: 801a strh r2, [r3, #0] + 8008edc: e01a b.n 8008f14 + 8008ede: 68bb ldr r3, [r7, #8] + 8008ee0: 785b ldrb r3, [r3, #1] + 8008ee2: 2b01 cmp r3, #1 + 8008ee4: d116 bne.n 8008f14 + 8008ee6: 68fb ldr r3, [r7, #12] + 8008ee8: 681b ldr r3, [r3, #0] + 8008eea: 637b str r3, [r7, #52] ; 0x34 + 8008eec: 68fb ldr r3, [r7, #12] + 8008eee: 681b ldr r3, [r3, #0] + 8008ef0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008ef4: b29b uxth r3, r3 + 8008ef6: 461a mov r2, r3 + 8008ef8: 6b7b ldr r3, [r7, #52] ; 0x34 + 8008efa: 4413 add r3, r2 + 8008efc: 637b str r3, [r7, #52] ; 0x34 + 8008efe: 68bb ldr r3, [r7, #8] + 8008f00: 781b ldrb r3, [r3, #0] + 8008f02: 00da lsls r2, r3, #3 + 8008f04: 6b7b ldr r3, [r7, #52] ; 0x34 + 8008f06: 4413 add r3, r2 + 8008f08: f203 4302 addw r3, r3, #1026 ; 0x402 + 8008f0c: 633b str r3, [r7, #48] ; 0x30 + 8008f0e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8008f10: 2200 movs r2, #0 + 8008f12: 801a strh r2, [r3, #0] + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + 8008f14: 68fb ldr r3, [r7, #12] + 8008f16: 681b ldr r3, [r3, #0] + 8008f18: 627b str r3, [r7, #36] ; 0x24 + 8008f1a: 68bb ldr r3, [r7, #8] + 8008f1c: 785b ldrb r3, [r3, #1] + 8008f1e: 2b00 cmp r3, #0 + 8008f20: d126 bne.n 8008f70 + 8008f22: 68fb ldr r3, [r7, #12] + 8008f24: 681b ldr r3, [r3, #0] + 8008f26: 61fb str r3, [r7, #28] + 8008f28: 68fb ldr r3, [r7, #12] + 8008f2a: 681b ldr r3, [r3, #0] + 8008f2c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008f30: b29b uxth r3, r3 + 8008f32: 461a mov r2, r3 + 8008f34: 69fb ldr r3, [r7, #28] + 8008f36: 4413 add r3, r2 + 8008f38: 61fb str r3, [r7, #28] + 8008f3a: 68bb ldr r3, [r7, #8] + 8008f3c: 781b ldrb r3, [r3, #0] + 8008f3e: 00da lsls r2, r3, #3 + 8008f40: 69fb ldr r3, [r7, #28] + 8008f42: 4413 add r3, r2 + 8008f44: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008f48: 61bb str r3, [r7, #24] + 8008f4a: 69bb ldr r3, [r7, #24] + 8008f4c: 881b ldrh r3, [r3, #0] + 8008f4e: b29b uxth r3, r3 + 8008f50: f3c3 0309 ubfx r3, r3, #0, #10 + 8008f54: b29a uxth r2, r3 + 8008f56: 69bb ldr r3, [r7, #24] + 8008f58: 801a strh r2, [r3, #0] + 8008f5a: 69bb ldr r3, [r7, #24] + 8008f5c: 881b ldrh r3, [r3, #0] + 8008f5e: b29b uxth r3, r3 + 8008f60: ea6f 4343 mvn.w r3, r3, lsl #17 + 8008f64: ea6f 4353 mvn.w r3, r3, lsr #17 + 8008f68: b29a uxth r2, r3 + 8008f6a: 69bb ldr r3, [r7, #24] + 8008f6c: 801a strh r2, [r3, #0] + 8008f6e: e017 b.n 8008fa0 + 8008f70: 68bb ldr r3, [r7, #8] + 8008f72: 785b ldrb r3, [r3, #1] + 8008f74: 2b01 cmp r3, #1 + 8008f76: d113 bne.n 8008fa0 + 8008f78: 68fb ldr r3, [r7, #12] + 8008f7a: 681b ldr r3, [r3, #0] + 8008f7c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8008f80: b29b uxth r3, r3 + 8008f82: 461a mov r2, r3 + 8008f84: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008f86: 4413 add r3, r2 + 8008f88: 627b str r3, [r7, #36] ; 0x24 + 8008f8a: 68bb ldr r3, [r7, #8] + 8008f8c: 781b ldrb r3, [r3, #0] + 8008f8e: 00da lsls r2, r3, #3 + 8008f90: 6a7b ldr r3, [r7, #36] ; 0x24 + 8008f92: 4413 add r3, r2 + 8008f94: f203 4306 addw r3, r3, #1030 ; 0x406 + 8008f98: 623b str r3, [r7, #32] + 8008f9a: 6a3b ldr r3, [r7, #32] + 8008f9c: 2200 movs r2, #0 + 8008f9e: 801a strh r2, [r3, #0] + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); + 8008fa0: 68bb ldr r3, [r7, #8] + 8008fa2: 781b ldrb r3, [r3, #0] + 8008fa4: 4619 mov r1, r3 + 8008fa6: 68f8 ldr r0, [r7, #12] + 8008fa8: f009 fceb bl 8012982 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + 8008fac: 88fb ldrh r3, [r7, #6] + 8008fae: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8008fb2: 2b00 cmp r3, #0 + 8008fb4: f000 82fa beq.w 80095ac + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + 8008fb8: 68fb ldr r3, [r7, #12] + 8008fba: 681b ldr r3, [r3, #0] + 8008fbc: 461a mov r2, r3 + 8008fbe: 68bb ldr r3, [r7, #8] + 8008fc0: 781b ldrb r3, [r3, #0] + 8008fc2: 009b lsls r3, r3, #2 + 8008fc4: 4413 add r3, r2 + 8008fc6: 881b ldrh r3, [r3, #0] + 8008fc8: b29b uxth r3, r3 + 8008fca: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 8008fce: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008fd2: 82fb strh r3, [r7, #22] + 8008fd4: 68fb ldr r3, [r7, #12] + 8008fd6: 681b ldr r3, [r3, #0] + 8008fd8: 461a mov r2, r3 + 8008fda: 68bb ldr r3, [r7, #8] + 8008fdc: 781b ldrb r3, [r3, #0] + 8008fde: 009b lsls r3, r3, #2 + 8008fe0: 441a add r2, r3 + 8008fe2: 8afb ldrh r3, [r7, #22] + 8008fe4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8008fe8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8008fec: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8008ff0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8008ff4: b29b uxth r3, r3 + 8008ff6: 8013 strh r3, [r2, #0] + 8008ff8: e2d8 b.n 80095ac + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + 8008ffa: 88fb ldrh r3, [r7, #6] + 8008ffc: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8009000: 2b00 cmp r3, #0 + 8009002: d021 beq.n 8009048 + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + 8009004: 68fb ldr r3, [r7, #12] + 8009006: 681b ldr r3, [r3, #0] + 8009008: 461a mov r2, r3 + 800900a: 68bb ldr r3, [r7, #8] + 800900c: 781b ldrb r3, [r3, #0] + 800900e: 009b lsls r3, r3, #2 + 8009010: 4413 add r3, r2 + 8009012: 881b ldrh r3, [r3, #0] + 8009014: b29b uxth r3, r3 + 8009016: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800901a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800901e: f8a7 308a strh.w r3, [r7, #138] ; 0x8a + 8009022: 68fb ldr r3, [r7, #12] + 8009024: 681b ldr r3, [r3, #0] + 8009026: 461a mov r2, r3 + 8009028: 68bb ldr r3, [r7, #8] + 800902a: 781b ldrb r3, [r3, #0] + 800902c: 009b lsls r3, r3, #2 + 800902e: 441a add r2, r3 + 8009030: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a + 8009034: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 8009038: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800903c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8009040: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8009044: b29b uxth r3, r3 + 8009046: 8013 strh r3, [r2, #0] + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + 8009048: 68bb ldr r3, [r7, #8] + 800904a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 800904e: 2b01 cmp r3, #1 + 8009050: f040 82ac bne.w 80095ac + { + ep->xfer_buff += TxPctSize; + 8009054: 68bb ldr r3, [r7, #8] + 8009056: 695a ldr r2, [r3, #20] + 8009058: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 800905c: 441a add r2, r3 + 800905e: 68bb ldr r3, [r7, #8] + 8009060: 615a str r2, [r3, #20] + ep->xfer_count += TxPctSize; + 8009062: 68bb ldr r3, [r7, #8] + 8009064: 69da ldr r2, [r3, #28] + 8009066: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 800906a: 441a add r2, r3 + 800906c: 68bb ldr r3, [r7, #8] + 800906e: 61da str r2, [r3, #28] + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + 8009070: 68bb ldr r3, [r7, #8] + 8009072: 6a1a ldr r2, [r3, #32] + 8009074: 68bb ldr r3, [r7, #8] + 8009076: 691b ldr r3, [r3, #16] + 8009078: 429a cmp r2, r3 + 800907a: d30b bcc.n 8009094 + { + len = ep->maxpacket; + 800907c: 68bb ldr r3, [r7, #8] + 800907e: 691b ldr r3, [r3, #16] + 8009080: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_len_db -= len; + 8009084: 68bb ldr r3, [r7, #8] + 8009086: 6a1a ldr r2, [r3, #32] + 8009088: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800908c: 1ad2 subs r2, r2, r3 + 800908e: 68bb ldr r3, [r7, #8] + 8009090: 621a str r2, [r3, #32] + 8009092: e017 b.n 80090c4 + } + else if (ep->xfer_len_db == 0U) + 8009094: 68bb ldr r3, [r7, #8] + 8009096: 6a1b ldr r3, [r3, #32] + 8009098: 2b00 cmp r3, #0 + 800909a: d108 bne.n 80090ae + { + len = TxPctSize; + 800909c: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 80090a0: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_fill_db = 0U; + 80090a4: 68bb ldr r3, [r7, #8] + 80090a6: 2200 movs r2, #0 + 80090a8: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 80090ac: e00a b.n 80090c4 + } + else + { + ep->xfer_fill_db = 0U; + 80090ae: 68bb ldr r3, [r7, #8] + 80090b0: 2200 movs r2, #0 + 80090b2: f883 2024 strb.w r2, [r3, #36] ; 0x24 + len = ep->xfer_len_db; + 80090b6: 68bb ldr r3, [r7, #8] + 80090b8: 6a1b ldr r3, [r3, #32] + 80090ba: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_len_db = 0U; + 80090be: 68bb ldr r3, [r7, #8] + 80090c0: 2200 movs r2, #0 + 80090c2: 621a str r2, [r3, #32] + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer1 */ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + 80090c4: 68bb ldr r3, [r7, #8] + 80090c6: 785b ldrb r3, [r3, #1] + 80090c8: 2b00 cmp r3, #0 + 80090ca: d165 bne.n 8009198 + 80090cc: 68fb ldr r3, [r7, #12] + 80090ce: 681b ldr r3, [r3, #0] + 80090d0: 63fb str r3, [r7, #60] ; 0x3c + 80090d2: 68fb ldr r3, [r7, #12] + 80090d4: 681b ldr r3, [r3, #0] + 80090d6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80090da: b29b uxth r3, r3 + 80090dc: 461a mov r2, r3 + 80090de: 6bfb ldr r3, [r7, #60] ; 0x3c + 80090e0: 4413 add r3, r2 + 80090e2: 63fb str r3, [r7, #60] ; 0x3c + 80090e4: 68bb ldr r3, [r7, #8] + 80090e6: 781b ldrb r3, [r3, #0] + 80090e8: 00da lsls r2, r3, #3 + 80090ea: 6bfb ldr r3, [r7, #60] ; 0x3c + 80090ec: 4413 add r3, r2 + 80090ee: f203 4302 addw r3, r3, #1026 ; 0x402 + 80090f2: 63bb str r3, [r7, #56] ; 0x38 + 80090f4: 6bbb ldr r3, [r7, #56] ; 0x38 + 80090f6: 881b ldrh r3, [r3, #0] + 80090f8: b29b uxth r3, r3 + 80090fa: f3c3 0309 ubfx r3, r3, #0, #10 + 80090fe: b29a uxth r2, r3 + 8009100: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009102: 801a strh r2, [r3, #0] + 8009104: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009108: 2b3e cmp r3, #62 ; 0x3e + 800910a: d91d bls.n 8009148 + 800910c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009110: 095b lsrs r3, r3, #5 + 8009112: 64bb str r3, [r7, #72] ; 0x48 + 8009114: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009118: f003 031f and.w r3, r3, #31 + 800911c: 2b00 cmp r3, #0 + 800911e: d102 bne.n 8009126 + 8009120: 6cbb ldr r3, [r7, #72] ; 0x48 + 8009122: 3b01 subs r3, #1 + 8009124: 64bb str r3, [r7, #72] ; 0x48 + 8009126: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009128: 881b ldrh r3, [r3, #0] + 800912a: b29a uxth r2, r3 + 800912c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800912e: b29b uxth r3, r3 + 8009130: 029b lsls r3, r3, #10 + 8009132: b29b uxth r3, r3 + 8009134: 4313 orrs r3, r2 + 8009136: b29b uxth r3, r3 + 8009138: ea6f 4343 mvn.w r3, r3, lsl #17 + 800913c: ea6f 4353 mvn.w r3, r3, lsr #17 + 8009140: b29a uxth r2, r3 + 8009142: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009144: 801a strh r2, [r3, #0] + 8009146: e044 b.n 80091d2 + 8009148: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800914c: 2b00 cmp r3, #0 + 800914e: d10a bne.n 8009166 + 8009150: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009152: 881b ldrh r3, [r3, #0] + 8009154: b29b uxth r3, r3 + 8009156: ea6f 4343 mvn.w r3, r3, lsl #17 + 800915a: ea6f 4353 mvn.w r3, r3, lsr #17 + 800915e: b29a uxth r2, r3 + 8009160: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009162: 801a strh r2, [r3, #0] + 8009164: e035 b.n 80091d2 + 8009166: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800916a: 085b lsrs r3, r3, #1 + 800916c: 64bb str r3, [r7, #72] ; 0x48 + 800916e: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009172: f003 0301 and.w r3, r3, #1 + 8009176: 2b00 cmp r3, #0 + 8009178: d002 beq.n 8009180 + 800917a: 6cbb ldr r3, [r7, #72] ; 0x48 + 800917c: 3301 adds r3, #1 + 800917e: 64bb str r3, [r7, #72] ; 0x48 + 8009180: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009182: 881b ldrh r3, [r3, #0] + 8009184: b29a uxth r2, r3 + 8009186: 6cbb ldr r3, [r7, #72] ; 0x48 + 8009188: b29b uxth r3, r3 + 800918a: 029b lsls r3, r3, #10 + 800918c: b29b uxth r3, r3 + 800918e: 4313 orrs r3, r2 + 8009190: b29a uxth r2, r3 + 8009192: 6bbb ldr r3, [r7, #56] ; 0x38 + 8009194: 801a strh r2, [r3, #0] + 8009196: e01c b.n 80091d2 + 8009198: 68bb ldr r3, [r7, #8] + 800919a: 785b ldrb r3, [r3, #1] + 800919c: 2b01 cmp r3, #1 + 800919e: d118 bne.n 80091d2 + 80091a0: 68fb ldr r3, [r7, #12] + 80091a2: 681b ldr r3, [r3, #0] + 80091a4: 647b str r3, [r7, #68] ; 0x44 + 80091a6: 68fb ldr r3, [r7, #12] + 80091a8: 681b ldr r3, [r3, #0] + 80091aa: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80091ae: b29b uxth r3, r3 + 80091b0: 461a mov r2, r3 + 80091b2: 6c7b ldr r3, [r7, #68] ; 0x44 + 80091b4: 4413 add r3, r2 + 80091b6: 647b str r3, [r7, #68] ; 0x44 + 80091b8: 68bb ldr r3, [r7, #8] + 80091ba: 781b ldrb r3, [r3, #0] + 80091bc: 00da lsls r2, r3, #3 + 80091be: 6c7b ldr r3, [r7, #68] ; 0x44 + 80091c0: 4413 add r3, r2 + 80091c2: f203 4302 addw r3, r3, #1026 ; 0x402 + 80091c6: 643b str r3, [r7, #64] ; 0x40 + 80091c8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80091cc: b29a uxth r2, r3 + 80091ce: 6c3b ldr r3, [r7, #64] ; 0x40 + 80091d0: 801a strh r2, [r3, #0] + + /* Copy user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); + 80091d2: 68fb ldr r3, [r7, #12] + 80091d4: 6818 ldr r0, [r3, #0] + 80091d6: 68bb ldr r3, [r7, #8] + 80091d8: 6959 ldr r1, [r3, #20] + 80091da: 68bb ldr r3, [r7, #8] + 80091dc: 891a ldrh r2, [r3, #8] + 80091de: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80091e2: b29b uxth r3, r3 + 80091e4: f006 fc2f bl 800fa46 + 80091e8: e1e0 b.n 80095ac + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + 80091ea: 68fb ldr r3, [r7, #12] + 80091ec: 681b ldr r3, [r3, #0] + 80091ee: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80091f2: b29b uxth r3, r3 + 80091f4: 461a mov r2, r3 + 80091f6: 68bb ldr r3, [r7, #8] + 80091f8: 781b ldrb r3, [r3, #0] + 80091fa: 00db lsls r3, r3, #3 + 80091fc: 4413 add r3, r2 + 80091fe: 68fa ldr r2, [r7, #12] + 8009200: 6812 ldr r2, [r2, #0] + 8009202: 4413 add r3, r2 + 8009204: f203 4306 addw r3, r3, #1030 ; 0x406 + 8009208: 881b ldrh r3, [r3, #0] + 800920a: f3c3 0309 ubfx r3, r3, #0, #10 + 800920e: f8a7 3086 strh.w r3, [r7, #134] ; 0x86 + + if (ep->xfer_len >= TxPctSize) + 8009212: 68bb ldr r3, [r7, #8] + 8009214: 699a ldr r2, [r3, #24] + 8009216: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 800921a: 429a cmp r2, r3 + 800921c: d307 bcc.n 800922e + { + ep->xfer_len -= TxPctSize; + 800921e: 68bb ldr r3, [r7, #8] + 8009220: 699a ldr r2, [r3, #24] + 8009222: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 8009226: 1ad2 subs r2, r2, r3 + 8009228: 68bb ldr r3, [r7, #8] + 800922a: 619a str r2, [r3, #24] + 800922c: e002 b.n 8009234 + } + else + { + ep->xfer_len = 0U; + 800922e: 68bb ldr r3, [r7, #8] + 8009230: 2200 movs r2, #0 + 8009232: 619a str r2, [r3, #24] + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + 8009234: 68bb ldr r3, [r7, #8] + 8009236: 699b ldr r3, [r3, #24] + 8009238: 2b00 cmp r3, #0 + 800923a: f040 80c0 bne.w 80093be + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + 800923e: 68bb ldr r3, [r7, #8] + 8009240: 785b ldrb r3, [r3, #1] + 8009242: 2b00 cmp r3, #0 + 8009244: d126 bne.n 8009294 + 8009246: 68fb ldr r3, [r7, #12] + 8009248: 681b ldr r3, [r3, #0] + 800924a: 67fb str r3, [r7, #124] ; 0x7c + 800924c: 68fb ldr r3, [r7, #12] + 800924e: 681b ldr r3, [r3, #0] + 8009250: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8009254: b29b uxth r3, r3 + 8009256: 461a mov r2, r3 + 8009258: 6ffb ldr r3, [r7, #124] ; 0x7c + 800925a: 4413 add r3, r2 + 800925c: 67fb str r3, [r7, #124] ; 0x7c + 800925e: 68bb ldr r3, [r7, #8] + 8009260: 781b ldrb r3, [r3, #0] + 8009262: 00da lsls r2, r3, #3 + 8009264: 6ffb ldr r3, [r7, #124] ; 0x7c + 8009266: 4413 add r3, r2 + 8009268: f203 4302 addw r3, r3, #1026 ; 0x402 + 800926c: 67bb str r3, [r7, #120] ; 0x78 + 800926e: 6fbb ldr r3, [r7, #120] ; 0x78 + 8009270: 881b ldrh r3, [r3, #0] + 8009272: b29b uxth r3, r3 + 8009274: f3c3 0309 ubfx r3, r3, #0, #10 + 8009278: b29a uxth r2, r3 + 800927a: 6fbb ldr r3, [r7, #120] ; 0x78 + 800927c: 801a strh r2, [r3, #0] + 800927e: 6fbb ldr r3, [r7, #120] ; 0x78 + 8009280: 881b ldrh r3, [r3, #0] + 8009282: b29b uxth r3, r3 + 8009284: ea6f 4343 mvn.w r3, r3, lsl #17 + 8009288: ea6f 4353 mvn.w r3, r3, lsr #17 + 800928c: b29a uxth r2, r3 + 800928e: 6fbb ldr r3, [r7, #120] ; 0x78 + 8009290: 801a strh r2, [r3, #0] + 8009292: e01a b.n 80092ca + 8009294: 68bb ldr r3, [r7, #8] + 8009296: 785b ldrb r3, [r3, #1] + 8009298: 2b01 cmp r3, #1 + 800929a: d116 bne.n 80092ca + 800929c: 68fb ldr r3, [r7, #12] + 800929e: 681b ldr r3, [r3, #0] + 80092a0: 667b str r3, [r7, #100] ; 0x64 + 80092a2: 68fb ldr r3, [r7, #12] + 80092a4: 681b ldr r3, [r3, #0] + 80092a6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80092aa: b29b uxth r3, r3 + 80092ac: 461a mov r2, r3 + 80092ae: 6e7b ldr r3, [r7, #100] ; 0x64 + 80092b0: 4413 add r3, r2 + 80092b2: 667b str r3, [r7, #100] ; 0x64 + 80092b4: 68bb ldr r3, [r7, #8] + 80092b6: 781b ldrb r3, [r3, #0] + 80092b8: 00da lsls r2, r3, #3 + 80092ba: 6e7b ldr r3, [r7, #100] ; 0x64 + 80092bc: 4413 add r3, r2 + 80092be: f203 4302 addw r3, r3, #1026 ; 0x402 + 80092c2: 663b str r3, [r7, #96] ; 0x60 + 80092c4: 6e3b ldr r3, [r7, #96] ; 0x60 + 80092c6: 2200 movs r2, #0 + 80092c8: 801a strh r2, [r3, #0] + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + 80092ca: 68fb ldr r3, [r7, #12] + 80092cc: 681b ldr r3, [r3, #0] + 80092ce: 677b str r3, [r7, #116] ; 0x74 + 80092d0: 68bb ldr r3, [r7, #8] + 80092d2: 785b ldrb r3, [r3, #1] + 80092d4: 2b00 cmp r3, #0 + 80092d6: d12b bne.n 8009330 + 80092d8: 68fb ldr r3, [r7, #12] + 80092da: 681b ldr r3, [r3, #0] + 80092dc: 66fb str r3, [r7, #108] ; 0x6c + 80092de: 68fb ldr r3, [r7, #12] + 80092e0: 681b ldr r3, [r3, #0] + 80092e2: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80092e6: b29b uxth r3, r3 + 80092e8: 461a mov r2, r3 + 80092ea: 6efb ldr r3, [r7, #108] ; 0x6c + 80092ec: 4413 add r3, r2 + 80092ee: 66fb str r3, [r7, #108] ; 0x6c + 80092f0: 68bb ldr r3, [r7, #8] + 80092f2: 781b ldrb r3, [r3, #0] + 80092f4: 00da lsls r2, r3, #3 + 80092f6: 6efb ldr r3, [r7, #108] ; 0x6c + 80092f8: 4413 add r3, r2 + 80092fa: f203 4306 addw r3, r3, #1030 ; 0x406 + 80092fe: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 8009302: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 8009306: 881b ldrh r3, [r3, #0] + 8009308: b29b uxth r3, r3 + 800930a: f3c3 0309 ubfx r3, r3, #0, #10 + 800930e: b29a uxth r2, r3 + 8009310: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 8009314: 801a strh r2, [r3, #0] + 8009316: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 800931a: 881b ldrh r3, [r3, #0] + 800931c: b29b uxth r3, r3 + 800931e: ea6f 4343 mvn.w r3, r3, lsl #17 + 8009322: ea6f 4353 mvn.w r3, r3, lsr #17 + 8009326: b29a uxth r2, r3 + 8009328: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 800932c: 801a strh r2, [r3, #0] + 800932e: e017 b.n 8009360 + 8009330: 68bb ldr r3, [r7, #8] + 8009332: 785b ldrb r3, [r3, #1] + 8009334: 2b01 cmp r3, #1 + 8009336: d113 bne.n 8009360 + 8009338: 68fb ldr r3, [r7, #12] + 800933a: 681b ldr r3, [r3, #0] + 800933c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8009340: b29b uxth r3, r3 + 8009342: 461a mov r2, r3 + 8009344: 6f7b ldr r3, [r7, #116] ; 0x74 + 8009346: 4413 add r3, r2 + 8009348: 677b str r3, [r7, #116] ; 0x74 + 800934a: 68bb ldr r3, [r7, #8] + 800934c: 781b ldrb r3, [r3, #0] + 800934e: 00da lsls r2, r3, #3 + 8009350: 6f7b ldr r3, [r7, #116] ; 0x74 + 8009352: 4413 add r3, r2 + 8009354: f203 4306 addw r3, r3, #1030 ; 0x406 + 8009358: 673b str r3, [r7, #112] ; 0x70 + 800935a: 6f3b ldr r3, [r7, #112] ; 0x70 + 800935c: 2200 movs r2, #0 + 800935e: 801a strh r2, [r3, #0] + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); + 8009360: 68bb ldr r3, [r7, #8] + 8009362: 781b ldrb r3, [r3, #0] + 8009364: 4619 mov r1, r3 + 8009366: 68f8 ldr r0, [r7, #12] + 8009368: f009 fb0b bl 8012982 +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + 800936c: 88fb ldrh r3, [r7, #6] + 800936e: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8009372: 2b00 cmp r3, #0 + 8009374: f040 811a bne.w 80095ac + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + 8009378: 68fb ldr r3, [r7, #12] + 800937a: 681b ldr r3, [r3, #0] + 800937c: 461a mov r2, r3 + 800937e: 68bb ldr r3, [r7, #8] + 8009380: 781b ldrb r3, [r3, #0] + 8009382: 009b lsls r3, r3, #2 + 8009384: 4413 add r3, r2 + 8009386: 881b ldrh r3, [r3, #0] + 8009388: b29b uxth r3, r3 + 800938a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800938e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8009392: f8a7 3088 strh.w r3, [r7, #136] ; 0x88 + 8009396: 68fb ldr r3, [r7, #12] + 8009398: 681b ldr r3, [r3, #0] + 800939a: 461a mov r2, r3 + 800939c: 68bb ldr r3, [r7, #8] + 800939e: 781b ldrb r3, [r3, #0] + 80093a0: 009b lsls r3, r3, #2 + 80093a2: 441a add r2, r3 + 80093a4: f8b7 3088 ldrh.w r3, [r7, #136] ; 0x88 + 80093a8: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 80093ac: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 80093b0: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 80093b4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80093b8: b29b uxth r3, r3 + 80093ba: 8013 strh r3, [r2, #0] + 80093bc: e0f6 b.n 80095ac + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + 80093be: 88fb ldrh r3, [r7, #6] + 80093c0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80093c4: 2b00 cmp r3, #0 + 80093c6: d121 bne.n 800940c + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + 80093c8: 68fb ldr r3, [r7, #12] + 80093ca: 681b ldr r3, [r3, #0] + 80093cc: 461a mov r2, r3 + 80093ce: 68bb ldr r3, [r7, #8] + 80093d0: 781b ldrb r3, [r3, #0] + 80093d2: 009b lsls r3, r3, #2 + 80093d4: 4413 add r3, r2 + 80093d6: 881b ldrh r3, [r3, #0] + 80093d8: b29b uxth r3, r3 + 80093da: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 80093de: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80093e2: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + 80093e6: 68fb ldr r3, [r7, #12] + 80093e8: 681b ldr r3, [r3, #0] + 80093ea: 461a mov r2, r3 + 80093ec: 68bb ldr r3, [r7, #8] + 80093ee: 781b ldrb r3, [r3, #0] + 80093f0: 009b lsls r3, r3, #2 + 80093f2: 441a add r2, r3 + 80093f4: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 80093f8: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 80093fc: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 8009400: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8009404: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8009408: b29b uxth r3, r3 + 800940a: 8013 strh r3, [r2, #0] + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + 800940c: 68bb ldr r3, [r7, #8] + 800940e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8009412: 2b01 cmp r3, #1 + 8009414: f040 80ca bne.w 80095ac + { + ep->xfer_buff += TxPctSize; + 8009418: 68bb ldr r3, [r7, #8] + 800941a: 695a ldr r2, [r3, #20] + 800941c: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 8009420: 441a add r2, r3 + 8009422: 68bb ldr r3, [r7, #8] + 8009424: 615a str r2, [r3, #20] + ep->xfer_count += TxPctSize; + 8009426: 68bb ldr r3, [r7, #8] + 8009428: 69da ldr r2, [r3, #28] + 800942a: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 800942e: 441a add r2, r3 + 8009430: 68bb ldr r3, [r7, #8] + 8009432: 61da str r2, [r3, #28] + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + 8009434: 68bb ldr r3, [r7, #8] + 8009436: 6a1a ldr r2, [r3, #32] + 8009438: 68bb ldr r3, [r7, #8] + 800943a: 691b ldr r3, [r3, #16] + 800943c: 429a cmp r2, r3 + 800943e: d30b bcc.n 8009458 + { + len = ep->maxpacket; + 8009440: 68bb ldr r3, [r7, #8] + 8009442: 691b ldr r3, [r3, #16] + 8009444: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_len_db -= len; + 8009448: 68bb ldr r3, [r7, #8] + 800944a: 6a1a ldr r2, [r3, #32] + 800944c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009450: 1ad2 subs r2, r2, r3 + 8009452: 68bb ldr r3, [r7, #8] + 8009454: 621a str r2, [r3, #32] + 8009456: e017 b.n 8009488 + } + else if (ep->xfer_len_db == 0U) + 8009458: 68bb ldr r3, [r7, #8] + 800945a: 6a1b ldr r3, [r3, #32] + 800945c: 2b00 cmp r3, #0 + 800945e: d108 bne.n 8009472 + { + len = TxPctSize; + 8009460: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 + 8009464: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_fill_db = 0U; + 8009468: 68bb ldr r3, [r7, #8] + 800946a: 2200 movs r2, #0 + 800946c: f883 2024 strb.w r2, [r3, #36] ; 0x24 + 8009470: e00a b.n 8009488 + } + else + { + len = ep->xfer_len_db; + 8009472: 68bb ldr r3, [r7, #8] + 8009474: 6a1b ldr r3, [r3, #32] + 8009476: f8c7 308c str.w r3, [r7, #140] ; 0x8c + ep->xfer_len_db = 0U; + 800947a: 68bb ldr r3, [r7, #8] + 800947c: 2200 movs r2, #0 + 800947e: 621a str r2, [r3, #32] + ep->xfer_fill_db = 0; + 8009480: 68bb ldr r3, [r7, #8] + 8009482: 2200 movs r2, #0 + 8009484: f883 2024 strb.w r2, [r3, #36] ; 0x24 } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + 8009488: 68fb ldr r3, [r7, #12] + 800948a: 681b ldr r3, [r3, #0] + 800948c: 657b str r3, [r7, #84] ; 0x54 + 800948e: 68bb ldr r3, [r7, #8] + 8009490: 785b ldrb r3, [r3, #1] + 8009492: 2b00 cmp r3, #0 + 8009494: d165 bne.n 8009562 + 8009496: 68fb ldr r3, [r7, #12] + 8009498: 681b ldr r3, [r3, #0] + 800949a: 65fb str r3, [r7, #92] ; 0x5c + 800949c: 68fb ldr r3, [r7, #12] + 800949e: 681b ldr r3, [r3, #0] + 80094a0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 80094a4: b29b uxth r3, r3 + 80094a6: 461a mov r2, r3 + 80094a8: 6dfb ldr r3, [r7, #92] ; 0x5c + 80094aa: 4413 add r3, r2 + 80094ac: 65fb str r3, [r7, #92] ; 0x5c + 80094ae: 68bb ldr r3, [r7, #8] + 80094b0: 781b ldrb r3, [r3, #0] + 80094b2: 00da lsls r2, r3, #3 + 80094b4: 6dfb ldr r3, [r7, #92] ; 0x5c + 80094b6: 4413 add r3, r2 + 80094b8: f203 4306 addw r3, r3, #1030 ; 0x406 + 80094bc: 65bb str r3, [r7, #88] ; 0x58 + 80094be: 6dbb ldr r3, [r7, #88] ; 0x58 + 80094c0: 881b ldrh r3, [r3, #0] + 80094c2: b29b uxth r3, r3 + 80094c4: f3c3 0309 ubfx r3, r3, #0, #10 + 80094c8: b29a uxth r2, r3 + 80094ca: 6dbb ldr r3, [r7, #88] ; 0x58 + 80094cc: 801a strh r2, [r3, #0] + 80094ce: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80094d2: 2b3e cmp r3, #62 ; 0x3e + 80094d4: d91d bls.n 8009512 + 80094d6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80094da: 095b lsrs r3, r3, #5 + 80094dc: 66bb str r3, [r7, #104] ; 0x68 + 80094de: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80094e2: f003 031f and.w r3, r3, #31 + 80094e6: 2b00 cmp r3, #0 + 80094e8: d102 bne.n 80094f0 + 80094ea: 6ebb ldr r3, [r7, #104] ; 0x68 + 80094ec: 3b01 subs r3, #1 + 80094ee: 66bb str r3, [r7, #104] ; 0x68 + 80094f0: 6dbb ldr r3, [r7, #88] ; 0x58 + 80094f2: 881b ldrh r3, [r3, #0] + 80094f4: b29a uxth r2, r3 + 80094f6: 6ebb ldr r3, [r7, #104] ; 0x68 + 80094f8: b29b uxth r3, r3 + 80094fa: 029b lsls r3, r3, #10 + 80094fc: b29b uxth r3, r3 + 80094fe: 4313 orrs r3, r2 + 8009500: b29b uxth r3, r3 + 8009502: ea6f 4343 mvn.w r3, r3, lsl #17 + 8009506: ea6f 4353 mvn.w r3, r3, lsr #17 + 800950a: b29a uxth r2, r3 + 800950c: 6dbb ldr r3, [r7, #88] ; 0x58 + 800950e: 801a strh r2, [r3, #0] + 8009510: e041 b.n 8009596 + 8009512: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009516: 2b00 cmp r3, #0 + 8009518: d10a bne.n 8009530 + 800951a: 6dbb ldr r3, [r7, #88] ; 0x58 + 800951c: 881b ldrh r3, [r3, #0] + 800951e: b29b uxth r3, r3 + 8009520: ea6f 4343 mvn.w r3, r3, lsl #17 + 8009524: ea6f 4353 mvn.w r3, r3, lsr #17 + 8009528: b29a uxth r2, r3 + 800952a: 6dbb ldr r3, [r7, #88] ; 0x58 + 800952c: 801a strh r2, [r3, #0] + 800952e: e032 b.n 8009596 + 8009530: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009534: 085b lsrs r3, r3, #1 + 8009536: 66bb str r3, [r7, #104] ; 0x68 + 8009538: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800953c: f003 0301 and.w r3, r3, #1 + 8009540: 2b00 cmp r3, #0 + 8009542: d002 beq.n 800954a + 8009544: 6ebb ldr r3, [r7, #104] ; 0x68 + 8009546: 3301 adds r3, #1 + 8009548: 66bb str r3, [r7, #104] ; 0x68 + 800954a: 6dbb ldr r3, [r7, #88] ; 0x58 + 800954c: 881b ldrh r3, [r3, #0] + 800954e: b29a uxth r2, r3 + 8009550: 6ebb ldr r3, [r7, #104] ; 0x68 + 8009552: b29b uxth r3, r3 + 8009554: 029b lsls r3, r3, #10 + 8009556: b29b uxth r3, r3 + 8009558: 4313 orrs r3, r2 + 800955a: b29a uxth r2, r3 + 800955c: 6dbb ldr r3, [r7, #88] ; 0x58 + 800955e: 801a strh r2, [r3, #0] + 8009560: e019 b.n 8009596 + 8009562: 68bb ldr r3, [r7, #8] + 8009564: 785b ldrb r3, [r3, #1] + 8009566: 2b01 cmp r3, #1 + 8009568: d115 bne.n 8009596 + 800956a: 68fb ldr r3, [r7, #12] + 800956c: 681b ldr r3, [r3, #0] + 800956e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 8009572: b29b uxth r3, r3 + 8009574: 461a mov r2, r3 + 8009576: 6d7b ldr r3, [r7, #84] ; 0x54 + 8009578: 4413 add r3, r2 + 800957a: 657b str r3, [r7, #84] ; 0x54 + 800957c: 68bb ldr r3, [r7, #8] + 800957e: 781b ldrb r3, [r3, #0] + 8009580: 00da lsls r2, r3, #3 + 8009582: 6d7b ldr r3, [r7, #84] ; 0x54 + 8009584: 4413 add r3, r2 + 8009586: f203 4306 addw r3, r3, #1030 ; 0x406 + 800958a: 653b str r3, [r7, #80] ; 0x50 + 800958c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8009590: b29a uxth r2, r3 + 8009592: 6d3b ldr r3, [r7, #80] ; 0x50 + 8009594: 801a strh r2, [r3, #0] + + /* Copy the user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); + 8009596: 68fb ldr r3, [r7, #12] + 8009598: 6818 ldr r0, [r3, #0] + 800959a: 68bb ldr r3, [r7, #8] + 800959c: 6959 ldr r1, [r3, #20] + 800959e: 68bb ldr r3, [r7, #8] + 80095a0: 895a ldrh r2, [r3, #10] + 80095a2: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 80095a6: b29b uxth r3, r3 + 80095a8: f006 fa4d bl 800fa46 } } } + /*enable endpoint IN*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + 80095ac: 68fb ldr r3, [r7, #12] + 80095ae: 681b ldr r3, [r3, #0] + 80095b0: 461a mov r2, r3 + 80095b2: 68bb ldr r3, [r7, #8] + 80095b4: 781b ldrb r3, [r3, #0] + 80095b6: 009b lsls r3, r3, #2 + 80095b8: 4413 add r3, r2 + 80095ba: 881b ldrh r3, [r3, #0] + 80095bc: b29b uxth r3, r3 + 80095be: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 80095c2: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80095c6: 82bb strh r3, [r7, #20] + 80095c8: 8abb ldrh r3, [r7, #20] + 80095ca: f083 0310 eor.w r3, r3, #16 + 80095ce: 82bb strh r3, [r7, #20] + 80095d0: 8abb ldrh r3, [r7, #20] + 80095d2: f083 0320 eor.w r3, r3, #32 + 80095d6: 82bb strh r3, [r7, #20] + 80095d8: 68fb ldr r3, [r7, #12] + 80095da: 681b ldr r3, [r3, #0] + 80095dc: 461a mov r2, r3 + 80095de: 68bb ldr r3, [r7, #8] + 80095e0: 781b ldrb r3, [r3, #0] + 80095e2: 009b lsls r3, r3, #2 + 80095e4: 441a add r2, r3 + 80095e6: 8abb ldrh r3, [r7, #20] + 80095e8: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 80095ec: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 80095f0: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80095f4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80095f8: b29b uxth r3, r3 + 80095fa: 8013 strh r3, [r2, #0] + return HAL_OK; - 8008256: 2300 movs r3, #0 + 80095fc: 2300 movs r3, #0 } - 8008258: 4618 mov r0, r3 - 800825a: 3758 adds r7, #88 ; 0x58 - 800825c: 46bd mov sp, r7 - 800825e: bd80 pop {r7, pc} + 80095fe: 4618 mov r0, r3 + 8009600: 3790 adds r7, #144 ; 0x90 + 8009602: 46bd mov sp, r7 + 8009604: bd80 pop {r7, pc} -08008260 : - * @param wEPVal Last snapshot of EPRx register value taken in ISR +08009606 : * @retval HAL status */ -static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, - PCD_EPTypeDef *ep, uint16_t wEPVal) + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) { - 8008260: b580 push {r7, lr} - 8008262: b088 sub sp, #32 - 8008264: af00 add r7, sp, #0 - 8008266: 60f8 str r0, [r7, #12] - 8008268: 60b9 str r1, [r7, #8] - 800826a: 4613 mov r3, r2 - 800826c: 80fb strh r3, [r7, #6] - uint16_t count; + 8009606: b480 push {r7} + 8009608: b087 sub sp, #28 + 800960a: af00 add r7, sp, #0 + 800960c: 60f8 str r0, [r7, #12] + 800960e: 607b str r3, [r7, #4] + 8009610: 460b mov r3, r1 + 8009612: 817b strh r3, [r7, #10] + 8009614: 4613 mov r3, r2 + 8009616: 813b strh r3, [r7, #8] + PCD_EPTypeDef *ep; - /* Manage Buffer0 OUT */ - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - 800826e: 88fb ldrh r3, [r7, #6] - 8008270: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8008274: 2b00 cmp r3, #0 - 8008276: d07c beq.n 8008372 + /* initialize ep structure*/ + if ((0x80U & ep_addr) == 0x80U) + 8009618: 897b ldrh r3, [r7, #10] + 800961a: f003 0380 and.w r3, r3, #128 ; 0x80 + 800961e: b29b uxth r3, r3 + 8009620: 2b00 cmp r3, #0 + 8009622: d00b beq.n 800963c { - /* Get count of received Data on buffer0 */ - count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - 8008278: 68fb ldr r3, [r7, #12] - 800827a: 681b ldr r3, [r3, #0] - 800827c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008280: b29b uxth r3, r3 - 8008282: 461a mov r2, r3 - 8008284: 68bb ldr r3, [r7, #8] - 8008286: 781b ldrb r3, [r3, #0] - 8008288: 00db lsls r3, r3, #3 - 800828a: 4413 add r3, r2 - 800828c: 68fa ldr r2, [r7, #12] - 800828e: 6812 ldr r2, [r2, #0] - 8008290: 4413 add r3, r2 - 8008292: f203 4302 addw r3, r3, #1026 ; 0x402 - 8008296: 881b ldrh r3, [r3, #0] - 8008298: f3c3 0309 ubfx r3, r3, #0, #10 - 800829c: 837b strh r3, [r7, #26] + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + 8009624: 897b ldrh r3, [r7, #10] + 8009626: f003 0307 and.w r3, r3, #7 + 800962a: 1c5a adds r2, r3, #1 + 800962c: 4613 mov r3, r2 + 800962e: 009b lsls r3, r3, #2 + 8009630: 4413 add r3, r2 + 8009632: 00db lsls r3, r3, #3 + 8009634: 68fa ldr r2, [r7, #12] + 8009636: 4413 add r3, r2 + 8009638: 617b str r3, [r7, #20] + 800963a: e009 b.n 8009650 + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + 800963c: 897a ldrh r2, [r7, #10] + 800963e: 4613 mov r3, r2 + 8009640: 009b lsls r3, r3, #2 + 8009642: 4413 add r3, r2 + 8009644: 00db lsls r3, r3, #3 + 8009646: f503 73b4 add.w r3, r3, #360 ; 0x168 + 800964a: 68fa ldr r2, [r7, #12] + 800964c: 4413 add r3, r2 + 800964e: 617b str r3, [r7, #20] + } - if (ep->xfer_len >= count) - 800829e: 68bb ldr r3, [r7, #8] - 80082a0: 699a ldr r2, [r3, #24] - 80082a2: 8b7b ldrh r3, [r7, #26] - 80082a4: 429a cmp r2, r3 - 80082a6: d306 bcc.n 80082b6 - { - ep->xfer_len -= count; - 80082a8: 68bb ldr r3, [r7, #8] - 80082aa: 699a ldr r2, [r3, #24] - 80082ac: 8b7b ldrh r3, [r7, #26] - 80082ae: 1ad2 subs r2, r2, r3 - 80082b0: 68bb ldr r3, [r7, #8] - 80082b2: 619a str r2, [r3, #24] - 80082b4: e002 b.n 80082bc - } - else - { - ep->xfer_len = 0U; - 80082b6: 68bb ldr r3, [r7, #8] - 80082b8: 2200 movs r2, #0 - 80082ba: 619a str r2, [r3, #24] - } + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + 8009650: 893b ldrh r3, [r7, #8] + 8009652: 2b00 cmp r3, #0 + 8009654: d107 bne.n 8009666 + { + /* Single Buffer */ + ep->doublebuffer = 0U; + 8009656: 697b ldr r3, [r7, #20] + 8009658: 2200 movs r2, #0 + 800965a: 731a strb r2, [r3, #12] + /* Configure the PMA */ + ep->pmaadress = (uint16_t)pmaadress; + 800965c: 687b ldr r3, [r7, #4] + 800965e: b29a uxth r2, r3 + 8009660: 697b ldr r3, [r7, #20] + 8009662: 80da strh r2, [r3, #6] + 8009664: e00b b.n 800967e + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + 8009666: 697b ldr r3, [r7, #20] + 8009668: 2201 movs r2, #1 + 800966a: 731a strb r2, [r3, #12] + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + 800966c: 687b ldr r3, [r7, #4] + 800966e: b29a uxth r2, r3 + 8009670: 697b ldr r3, [r7, #20] + 8009672: 811a strh r2, [r3, #8] + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); + 8009674: 687b ldr r3, [r7, #4] + 8009676: 0c1b lsrs r3, r3, #16 + 8009678: b29a uxth r2, r3 + 800967a: 697b ldr r3, [r7, #20] + 800967c: 815a strh r2, [r3, #10] + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - if (ep->xfer_len == 0U) - 80082bc: 68bb ldr r3, [r7, #8] - 80082be: 699b ldr r3, [r3, #24] - 80082c0: 2b00 cmp r3, #0 - 80082c2: d123 bne.n 800830c - { - /* set NAK to OUT endpoint since double buffer is enabled */ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); - 80082c4: 68fb ldr r3, [r7, #12] - 80082c6: 681b ldr r3, [r3, #0] - 80082c8: 461a mov r2, r3 - 80082ca: 68bb ldr r3, [r7, #8] - 80082cc: 781b ldrb r3, [r3, #0] - 80082ce: 009b lsls r3, r3, #2 - 80082d0: 4413 add r3, r2 - 80082d2: 881b ldrh r3, [r3, #0] - 80082d4: b29b uxth r3, r3 - 80082d6: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 80082da: f023 0370 bic.w r3, r3, #112 ; 0x70 - 80082de: 833b strh r3, [r7, #24] - 80082e0: 8b3b ldrh r3, [r7, #24] - 80082e2: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 80082e6: 833b strh r3, [r7, #24] - 80082e8: 68fb ldr r3, [r7, #12] - 80082ea: 681b ldr r3, [r3, #0] - 80082ec: 461a mov r2, r3 - 80082ee: 68bb ldr r3, [r7, #8] - 80082f0: 781b ldrb r3, [r3, #0] - 80082f2: 009b lsls r3, r3, #2 - 80082f4: 441a add r2, r3 - 80082f6: 8b3b ldrh r3, [r7, #24] - 80082f8: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 80082fc: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008300: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8008304: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8008308: b29b uxth r3, r3 - 800830a: 8013 strh r3, [r2, #0] - } + return HAL_OK; + 800967e: 2300 movs r3, #0 +} + 8009680: 4618 mov r0, r3 + 8009682: 371c adds r7, #28 + 8009684: 46bd mov sp, r7 + 8009686: f85d 7b04 ldr.w r7, [sp], #4 + 800968a: 4770 bx lr - /* Check if Buffer1 is in blocked state which requires to toggle */ - if ((wEPVal & USB_EP_DTOG_TX) != 0U) - 800830c: 88fb ldrh r3, [r7, #6] - 800830e: f003 0340 and.w r3, r3, #64 ; 0x40 - 8008312: 2b00 cmp r3, #0 - 8008314: d01f beq.n 8008356 - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - 8008316: 68fb ldr r3, [r7, #12] - 8008318: 681b ldr r3, [r3, #0] - 800831a: 461a mov r2, r3 - 800831c: 68bb ldr r3, [r7, #8] - 800831e: 781b ldrb r3, [r3, #0] - 8008320: 009b lsls r3, r3, #2 - 8008322: 4413 add r3, r2 - 8008324: 881b ldrh r3, [r3, #0] - 8008326: b29b uxth r3, r3 - 8008328: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800832c: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8008330: 82fb strh r3, [r7, #22] - 8008332: 68fb ldr r3, [r7, #12] - 8008334: 681b ldr r3, [r3, #0] - 8008336: 461a mov r2, r3 - 8008338: 68bb ldr r3, [r7, #8] - 800833a: 781b ldrb r3, [r3, #0] - 800833c: 009b lsls r3, r3, #2 - 800833e: 441a add r2, r3 - 8008340: 8afb ldrh r3, [r7, #22] - 8008342: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008346: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800834a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800834e: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 8008352: b29b uxth r3, r3 - 8008354: 8013 strh r3, [r2, #0] - } +0800968c : + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + 800968c: b480 push {r7} + 800968e: b085 sub sp, #20 + 8009690: af00 add r7, sp, #0 + 8009692: 6078 str r0, [r7, #4] - if (count != 0U) - 8008356: 8b7b ldrh r3, [r7, #26] - 8008358: 2b00 cmp r3, #0 - 800835a: f000 8085 beq.w 8008468 - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - 800835e: 68fb ldr r3, [r7, #12] - 8008360: 6818 ldr r0, [r3, #0] - 8008362: 68bb ldr r3, [r7, #8] - 8008364: 6959 ldr r1, [r3, #20] - 8008366: 68bb ldr r3, [r7, #8] - 8008368: 891a ldrh r2, [r3, #8] - 800836a: 8b7b ldrh r3, [r7, #26] - 800836c: f006 fa55 bl 800e81a - 8008370: e07a b.n 8008468 - } - /* Manage Buffer 1 DTOG_RX=0 */ - else - { - /* Get count of received data */ - count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - 8008372: 68fb ldr r3, [r7, #12] - 8008374: 681b ldr r3, [r3, #0] - 8008376: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800837a: b29b uxth r3, r3 - 800837c: 461a mov r2, r3 - 800837e: 68bb ldr r3, [r7, #8] - 8008380: 781b ldrb r3, [r3, #0] - 8008382: 00db lsls r3, r3, #3 - 8008384: 4413 add r3, r2 - 8008386: 68fa ldr r2, [r7, #12] - 8008388: 6812 ldr r2, [r2, #0] - 800838a: 4413 add r3, r2 - 800838c: f203 4306 addw r3, r3, #1030 ; 0x406 - 8008390: 881b ldrh r3, [r3, #0] - 8008392: f3c3 0309 ubfx r3, r3, #0, #10 - 8008396: 837b strh r3, [r7, #26] + USB_TypeDef *USBx = hpcd->Instance; + 8009694: 687b ldr r3, [r7, #4] + 8009696: 681b ldr r3, [r3, #0] + 8009698: 60fb str r3, [r7, #12] + hpcd->lpm_active = 1U; + 800969a: 687b ldr r3, [r7, #4] + 800969c: 2201 movs r2, #1 + 800969e: f8c3 22ec str.w r2, [r3, #748] ; 0x2ec + hpcd->LPM_State = LPM_L0; + 80096a2: 687b ldr r3, [r7, #4] + 80096a4: 2200 movs r2, #0 + 80096a6: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 - if (ep->xfer_len >= count) - 8008398: 68bb ldr r3, [r7, #8] - 800839a: 699a ldr r2, [r3, #24] - 800839c: 8b7b ldrh r3, [r7, #26] - 800839e: 429a cmp r2, r3 - 80083a0: d306 bcc.n 80083b0 - { - ep->xfer_len -= count; - 80083a2: 68bb ldr r3, [r7, #8] - 80083a4: 699a ldr r2, [r3, #24] - 80083a6: 8b7b ldrh r3, [r7, #26] - 80083a8: 1ad2 subs r2, r2, r3 - 80083aa: 68bb ldr r3, [r7, #8] - 80083ac: 619a str r2, [r3, #24] - 80083ae: e002 b.n 80083b6 - } + USBx->LPMCSR |= USB_LPMCSR_LMPEN; + 80096aa: 68fb ldr r3, [r7, #12] + 80096ac: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 + 80096b0: b29b uxth r3, r3 + 80096b2: f043 0301 orr.w r3, r3, #1 + 80096b6: b29a uxth r2, r3 + 80096b8: 68fb ldr r3, [r7, #12] + 80096ba: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 + USBx->LPMCSR |= USB_LPMCSR_LPMACK; + 80096be: 68fb ldr r3, [r7, #12] + 80096c0: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 + 80096c4: b29b uxth r3, r3 + 80096c6: f043 0302 orr.w r3, r3, #2 + 80096ca: b29a uxth r2, r3 + 80096cc: 68fb ldr r3, [r7, #12] + 80096ce: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 + + return HAL_OK; + 80096d2: 2300 movs r3, #0 +} + 80096d4: 4618 mov r0, r3 + 80096d6: 3714 adds r7, #20 + 80096d8: 46bd mov sp, r7 + 80096da: f85d 7b04 ldr.w r7, [sp], #4 + 80096de: 4770 bx lr + +080096e0 : + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 + * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 80096e0: b480 push {r7} + 80096e2: af00 add r7, sp, #0 else { - ep->xfer_len = 0U; - 80083b0: 68bb ldr r3, [r7, #8] - 80083b2: 2200 movs r2, #0 - 80083b4: 619a str r2, [r3, #24] + return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; } +#else + return (PWR->CR1 & PWR_CR1_VOS); + 80096e4: 4b04 ldr r3, [pc, #16] ; (80096f8 ) + 80096e6: 681b ldr r3, [r3, #0] + 80096e8: f403 63c0 and.w r3, r3, #1536 ; 0x600 +#endif +} + 80096ec: 4618 mov r0, r3 + 80096ee: 46bd mov sp, r7 + 80096f0: f85d 7b04 ldr.w r7, [sp], #4 + 80096f4: 4770 bx lr + 80096f6: bf00 nop + 80096f8: 40007000 .word 0x40007000 - if (ep->xfer_len == 0U) - 80083b6: 68bb ldr r3, [r7, #8] - 80083b8: 699b ldr r3, [r3, #24] - 80083ba: 2b00 cmp r3, #0 - 80083bc: d123 bne.n 8008406 - { - /* set NAK on the current endpoint */ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); - 80083be: 68fb ldr r3, [r7, #12] - 80083c0: 681b ldr r3, [r3, #0] - 80083c2: 461a mov r2, r3 - 80083c4: 68bb ldr r3, [r7, #8] - 80083c6: 781b ldrb r3, [r3, #0] - 80083c8: 009b lsls r3, r3, #2 - 80083ca: 4413 add r3, r2 - 80083cc: 881b ldrh r3, [r3, #0] - 80083ce: b29b uxth r3, r3 - 80083d0: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 80083d4: f023 0370 bic.w r3, r3, #112 ; 0x70 - 80083d8: 83fb strh r3, [r7, #30] - 80083da: 8bfb ldrh r3, [r7, #30] - 80083dc: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 80083e0: 83fb strh r3, [r7, #30] - 80083e2: 68fb ldr r3, [r7, #12] - 80083e4: 681b ldr r3, [r3, #0] - 80083e6: 461a mov r2, r3 - 80083e8: 68bb ldr r3, [r7, #8] - 80083ea: 781b ldrb r3, [r3, #0] - 80083ec: 009b lsls r3, r3, #2 - 80083ee: 441a add r2, r3 - 80083f0: 8bfb ldrh r3, [r7, #30] - 80083f2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 80083f6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 80083fa: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 80083fe: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8008402: b29b uxth r3, r3 - 8008404: 8013 strh r3, [r2, #0] - } +080096fc : + * cleared before returning the status. If the flag is not cleared within + * 50 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + 80096fc: b480 push {r7} + 80096fe: b085 sub sp, #20 + 8009700: af00 add r7, sp, #0 + 8009702: 6078 str r0, [r7, #4] + } - /*Need to FreeUser Buffer*/ - if ((wEPVal & USB_EP_DTOG_TX) == 0U) - 8008406: 88fb ldrh r3, [r7, #6] - 8008408: f003 0340 and.w r3, r3, #64 ; 0x40 - 800840c: 2b00 cmp r3, #0 - 800840e: d11f bne.n 8008450 +#else + + /* If Set Range 1 */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + 8009704: 687b ldr r3, [r7, #4] + 8009706: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800970a: d130 bne.n 800976e + { + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) + 800970c: 4b23 ldr r3, [pc, #140] ; (800979c ) + 800970e: 681b ldr r3, [r3, #0] + 8009710: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8009714: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8009718: d038 beq.n 800978c { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - 8008410: 68fb ldr r3, [r7, #12] - 8008412: 681b ldr r3, [r3, #0] - 8008414: 461a mov r2, r3 - 8008416: 68bb ldr r3, [r7, #8] - 8008418: 781b ldrb r3, [r3, #0] - 800841a: 009b lsls r3, r3, #2 - 800841c: 4413 add r3, r2 - 800841e: 881b ldrh r3, [r3, #0] - 8008420: b29b uxth r3, r3 - 8008422: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8008426: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800842a: 83bb strh r3, [r7, #28] - 800842c: 68fb ldr r3, [r7, #12] - 800842e: 681b ldr r3, [r3, #0] - 8008430: 461a mov r2, r3 - 8008432: 68bb ldr r3, [r7, #8] - 8008434: 781b ldrb r3, [r3, #0] - 8008436: 009b lsls r3, r3, #2 - 8008438: 441a add r2, r3 - 800843a: 8bbb ldrh r3, [r7, #28] - 800843c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008440: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008444: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8008448: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800844c: b29b uxth r3, r3 - 800844e: 8013 strh r3, [r2, #0] - } + /* Set Range 1 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + 800971a: 4b20 ldr r3, [pc, #128] ; (800979c ) + 800971c: 681b ldr r3, [r3, #0] + 800971e: f423 63c0 bic.w r3, r3, #1536 ; 0x600 + 8009722: 4a1e ldr r2, [pc, #120] ; (800979c ) + 8009724: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8009728: 6013 str r3, [r2, #0] - if (count != 0U) - 8008450: 8b7b ldrh r3, [r7, #26] - 8008452: 2b00 cmp r3, #0 - 8008454: d008 beq.n 8008468 + /* Wait until VOSF is cleared */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; + 800972a: 4b1d ldr r3, [pc, #116] ; (80097a0 ) + 800972c: 681b ldr r3, [r3, #0] + 800972e: 2232 movs r2, #50 ; 0x32 + 8009730: fb02 f303 mul.w r3, r2, r3 + 8009734: 4a1b ldr r2, [pc, #108] ; (80097a4 ) + 8009736: fba2 2303 umull r2, r3, r2, r3 + 800973a: 0c9b lsrs r3, r3, #18 + 800973c: 3301 adds r3, #1 + 800973e: 60fb str r3, [r7, #12] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) + 8009740: e002 b.n 8009748 + { + wait_loop_index--; + 8009742: 68fb ldr r3, [r7, #12] + 8009744: 3b01 subs r3, #1 + 8009746: 60fb str r3, [r7, #12] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) + 8009748: 4b14 ldr r3, [pc, #80] ; (800979c ) + 800974a: 695b ldr r3, [r3, #20] + 800974c: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8009750: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8009754: d102 bne.n 800975c + 8009756: 68fb ldr r3, [r7, #12] + 8009758: 2b00 cmp r3, #0 + 800975a: d1f2 bne.n 8009742 + } + if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + 800975c: 4b0f ldr r3, [pc, #60] ; (800979c ) + 800975e: 695b ldr r3, [r3, #20] + 8009760: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8009764: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8009768: d110 bne.n 800978c + { + return HAL_TIMEOUT; + 800976a: 2303 movs r3, #3 + 800976c: e00f b.n 800978e + } + } + } + else + { + if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) + 800976e: 4b0b ldr r3, [pc, #44] ; (800979c ) + 8009770: 681b ldr r3, [r3, #0] + 8009772: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8009776: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800977a: d007 beq.n 800978c { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - 8008456: 68fb ldr r3, [r7, #12] - 8008458: 6818 ldr r0, [r3, #0] - 800845a: 68bb ldr r3, [r7, #8] - 800845c: 6959 ldr r1, [r3, #20] - 800845e: 68bb ldr r3, [r7, #8] - 8008460: 895a ldrh r2, [r3, #10] - 8008462: 8b7b ldrh r3, [r7, #26] - 8008464: f006 f9d9 bl 800e81a + /* Set Range 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); + 800977c: 4b07 ldr r3, [pc, #28] ; (800979c ) + 800977e: 681b ldr r3, [r3, #0] + 8009780: f423 63c0 bic.w r3, r3, #1536 ; 0x600 + 8009784: 4a05 ldr r2, [pc, #20] ; (800979c ) + 8009786: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 800978a: 6013 str r3, [r2, #0] + /* No need to wait for VOSF to be cleared for this transition */ } } +#endif - return count; - 8008468: 8b7b ldrh r3, [r7, #26] -} - 800846a: 4618 mov r0, r3 - 800846c: 3720 adds r7, #32 - 800846e: 46bd mov sp, r7 - 8008470: bd80 pop {r7, pc} - -08008472 : - * @param wEPVal Last snapshot of EPRx register value taken in ISR + return HAL_OK; + 800978c: 2300 movs r3, #0 +} + 800978e: 4618 mov r0, r3 + 8009790: 3714 adds r7, #20 + 8009792: 46bd mov sp, r7 + 8009794: f85d 7b04 ldr.w r7, [sp], #4 + 8009798: 4770 bx lr + 800979a: bf00 nop + 800979c: 40007000 .word 0x40007000 + 80097a0: 20000020 .word 0x20000020 + 80097a4: 431bde83 .word 0x431bde83 + +080097a8 : + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @retval None + */ +void HAL_PWREx_EnableVddUSB(void) +{ + 80097a8: b480 push {r7} + 80097aa: af00 add r7, sp, #0 + SET_BIT(PWR->CR2, PWR_CR2_USV); + 80097ac: 4b05 ldr r3, [pc, #20] ; (80097c4 ) + 80097ae: 685b ldr r3, [r3, #4] + 80097b0: 4a04 ldr r2, [pc, #16] ; (80097c4 ) + 80097b2: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 80097b6: 6053 str r3, [r2, #4] +} + 80097b8: bf00 nop + 80097ba: 46bd mov sp, r7 + 80097bc: f85d 7b04 ldr.w r7, [sp], #4 + 80097c0: 4770 bx lr + 80097c2: bf00 nop + 80097c4: 40007000 .word 0x40007000 + +080097c8 : + * @note If HSE failed to start, HSE should be disabled before recalling + HAL_RCC_OscConfig(). * @retval HAL status */ -static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, - PCD_EPTypeDef *ep, uint16_t wEPVal) +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8008472: b580 push {r7, lr} - 8008474: b0a4 sub sp, #144 ; 0x90 - 8008476: af00 add r7, sp, #0 - 8008478: 60f8 str r0, [r7, #12] - 800847a: 60b9 str r1, [r7, #8] - 800847c: 4613 mov r3, r2 - 800847e: 80fb strh r3, [r7, #6] - uint32_t len; - uint16_t TxPctSize; + 80097c8: b580 push {r7, lr} + 80097ca: b088 sub sp, #32 + 80097cc: af00 add r7, sp, #0 + 80097ce: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 80097d0: 687b ldr r3, [r7, #4] + 80097d2: 2b00 cmp r3, #0 + 80097d4: d102 bne.n 80097dc + { + return HAL_ERROR; + 80097d6: 2301 movs r3, #1 + 80097d8: f000 bc02 b.w 8009fe0 + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80097dc: 4b96 ldr r3, [pc, #600] ; (8009a38 ) + 80097de: 689b ldr r3, [r3, #8] + 80097e0: f003 030c and.w r3, r3, #12 + 80097e4: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80097e6: 4b94 ldr r3, [pc, #592] ; (8009a38 ) + 80097e8: 68db ldr r3, [r3, #12] + 80097ea: f003 0303 and.w r3, r3, #3 + 80097ee: 617b str r3, [r7, #20] + + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 80097f0: 687b ldr r3, [r7, #4] + 80097f2: 681b ldr r3, [r3, #0] + 80097f4: f003 0310 and.w r3, r3, #16 + 80097f8: 2b00 cmp r3, #0 + 80097fa: f000 80e4 beq.w 80099c6 + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_CFGR_SWS_MSI) || + 80097fe: 69bb ldr r3, [r7, #24] + 8009800: 2b00 cmp r3, #0 + 8009802: d007 beq.n 8009814 + 8009804: 69bb ldr r3, [r7, #24] + 8009806: 2b0c cmp r3, #12 + 8009808: f040 808b bne.w 8009922 + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI))) + 800980c: 697b ldr r3, [r7, #20] + 800980e: 2b01 cmp r3, #1 + 8009810: f040 8087 bne.w 8009922 + { + if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8009814: 4b88 ldr r3, [pc, #544] ; (8009a38 ) + 8009816: 681b ldr r3, [r3, #0] + 8009818: f003 0302 and.w r3, r3, #2 + 800981c: 2b00 cmp r3, #0 + 800981e: d005 beq.n 800982c + 8009820: 687b ldr r3, [r7, #4] + 8009822: 699b ldr r3, [r3, #24] + 8009824: 2b00 cmp r3, #0 + 8009826: d101 bne.n 800982c + { + return HAL_ERROR; + 8009828: 2301 movs r3, #1 + 800982a: e3d9 b.n 8009fe0 + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 800982c: 687b ldr r3, [r7, #4] + 800982e: 6a1a ldr r2, [r3, #32] + 8009830: 4b81 ldr r3, [pc, #516] ; (8009a38 ) + 8009832: 681b ldr r3, [r3, #0] + 8009834: f003 0308 and.w r3, r3, #8 + 8009838: 2b00 cmp r3, #0 + 800983a: d004 beq.n 8009846 + 800983c: 4b7e ldr r3, [pc, #504] ; (8009a38 ) + 800983e: 681b ldr r3, [r3, #0] + 8009840: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8009844: e005 b.n 8009852 + 8009846: 4b7c ldr r3, [pc, #496] ; (8009a38 ) + 8009848: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800984c: 091b lsrs r3, r3, #4 + 800984e: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8009852: 4293 cmp r3, r2 + 8009854: d223 bcs.n 800989e + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8009856: 687b ldr r3, [r7, #4] + 8009858: 6a1b ldr r3, [r3, #32] + 800985a: 4618 mov r0, r3 + 800985c: f000 fd8c bl 800a378 + 8009860: 4603 mov r3, r0 + 8009862: 2b00 cmp r3, #0 + 8009864: d001 beq.n 800986a + { + return HAL_ERROR; + 8009866: 2301 movs r3, #1 + 8009868: e3ba b.n 8009fe0 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800986a: 4b73 ldr r3, [pc, #460] ; (8009a38 ) + 800986c: 681b ldr r3, [r3, #0] + 800986e: 4a72 ldr r2, [pc, #456] ; (8009a38 ) + 8009870: f043 0308 orr.w r3, r3, #8 + 8009874: 6013 str r3, [r2, #0] + 8009876: 4b70 ldr r3, [pc, #448] ; (8009a38 ) + 8009878: 681b ldr r3, [r3, #0] + 800987a: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800987e: 687b ldr r3, [r7, #4] + 8009880: 6a1b ldr r3, [r3, #32] + 8009882: 496d ldr r1, [pc, #436] ; (8009a38 ) + 8009884: 4313 orrs r3, r2 + 8009886: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8009888: 4b6b ldr r3, [pc, #428] ; (8009a38 ) + 800988a: 685b ldr r3, [r3, #4] + 800988c: f423 427f bic.w r2, r3, #65280 ; 0xff00 + 8009890: 687b ldr r3, [r7, #4] + 8009892: 69db ldr r3, [r3, #28] + 8009894: 021b lsls r3, r3, #8 + 8009896: 4968 ldr r1, [pc, #416] ; (8009a38 ) + 8009898: 4313 orrs r3, r2 + 800989a: 604b str r3, [r1, #4] + 800989c: e025 b.n 80098ea + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800989e: 4b66 ldr r3, [pc, #408] ; (8009a38 ) + 80098a0: 681b ldr r3, [r3, #0] + 80098a2: 4a65 ldr r2, [pc, #404] ; (8009a38 ) + 80098a4: f043 0308 orr.w r3, r3, #8 + 80098a8: 6013 str r3, [r2, #0] + 80098aa: 4b63 ldr r3, [pc, #396] ; (8009a38 ) + 80098ac: 681b ldr r3, [r3, #0] + 80098ae: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80098b2: 687b ldr r3, [r7, #4] + 80098b4: 6a1b ldr r3, [r3, #32] + 80098b6: 4960 ldr r1, [pc, #384] ; (8009a38 ) + 80098b8: 4313 orrs r3, r2 + 80098ba: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80098bc: 4b5e ldr r3, [pc, #376] ; (8009a38 ) + 80098be: 685b ldr r3, [r3, #4] + 80098c0: f423 427f bic.w r2, r3, #65280 ; 0xff00 + 80098c4: 687b ldr r3, [r7, #4] + 80098c6: 69db ldr r3, [r3, #28] + 80098c8: 021b lsls r3, r3, #8 + 80098ca: 495b ldr r1, [pc, #364] ; (8009a38 ) + 80098cc: 4313 orrs r3, r2 + 80098ce: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + /* Only possible when MSI is the System clock source */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 80098d0: 69bb ldr r3, [r7, #24] + 80098d2: 2b00 cmp r3, #0 + 80098d4: d109 bne.n 80098ea + { + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80098d6: 687b ldr r3, [r7, #4] + 80098d8: 6a1b ldr r3, [r3, #32] + 80098da: 4618 mov r0, r3 + 80098dc: f000 fd4c bl 800a378 + 80098e0: 4603 mov r3, r0 + 80098e2: 2b00 cmp r3, #0 + 80098e4: d001 beq.n 80098ea + { + return HAL_ERROR; + 80098e6: 2301 movs r3, #1 + 80098e8: e37a b.n 8009fe0 + } + } + } - /* Data Buffer0 ACK received */ - if ((wEPVal & USB_EP_DTOG_TX) != 0U) - 8008480: 88fb ldrh r3, [r7, #6] - 8008482: f003 0340 and.w r3, r3, #64 ; 0x40 - 8008486: 2b00 cmp r3, #0 - 8008488: f000 81db beq.w 8008842 - { - /* multi-packet on the NON control IN endpoint */ - TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - 800848c: 68fb ldr r3, [r7, #12] - 800848e: 681b ldr r3, [r3, #0] - 8008490: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008494: b29b uxth r3, r3 - 8008496: 461a mov r2, r3 - 8008498: 68bb ldr r3, [r7, #8] - 800849a: 781b ldrb r3, [r3, #0] - 800849c: 00db lsls r3, r3, #3 - 800849e: 4413 add r3, r2 - 80084a0: 68fa ldr r2, [r7, #12] - 80084a2: 6812 ldr r2, [r2, #0] - 80084a4: 4413 add r3, r2 - 80084a6: f203 4302 addw r3, r3, #1026 ; 0x402 - 80084aa: 881b ldrh r3, [r3, #0] - 80084ac: f3c3 0309 ubfx r3, r3, #0, #10 - 80084b0: f8a7 3086 strh.w r3, [r7, #134] ; 0x86 + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); + 80098ea: f000 fc81 bl 800a1f0 + 80098ee: 4602 mov r2, r0 + 80098f0: 4b51 ldr r3, [pc, #324] ; (8009a38 ) + 80098f2: 689b ldr r3, [r3, #8] + 80098f4: 091b lsrs r3, r3, #4 + 80098f6: f003 030f and.w r3, r3, #15 + 80098fa: 4950 ldr r1, [pc, #320] ; (8009a3c ) + 80098fc: 5ccb ldrb r3, [r1, r3] + 80098fe: f003 031f and.w r3, r3, #31 + 8009902: fa22 f303 lsr.w r3, r2, r3 + 8009906: 4a4e ldr r2, [pc, #312] ; (8009a40 ) + 8009908: 6013 str r3, [r2, #0] - if (ep->xfer_len > TxPctSize) - 80084b4: 68bb ldr r3, [r7, #8] - 80084b6: 699a ldr r2, [r3, #24] - 80084b8: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 80084bc: 429a cmp r2, r3 - 80084be: d907 bls.n 80084d0 - { - ep->xfer_len -= TxPctSize; - 80084c0: 68bb ldr r3, [r7, #8] - 80084c2: 699a ldr r2, [r3, #24] - 80084c4: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 80084c8: 1ad2 subs r2, r2, r3 - 80084ca: 68bb ldr r3, [r7, #8] - 80084cc: 619a str r2, [r3, #24] - 80084ce: e002 b.n 80084d6 + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800990a: 4b4e ldr r3, [pc, #312] ; (8009a44 ) + 800990c: 681b ldr r3, [r3, #0] + 800990e: 4618 mov r0, r3 + 8009910: f7fb fc4e bl 80051b0 + 8009914: 4603 mov r3, r0 + 8009916: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8009918: 7bfb ldrb r3, [r7, #15] + 800991a: 2b00 cmp r3, #0 + 800991c: d052 beq.n 80099c4 + { + return status; + 800991e: 7bfb ldrb r3, [r7, #15] + 8009920: e35e b.n 8009fe0 + } } else { - ep->xfer_len = 0U; - 80084d0: 68bb ldr r3, [r7, #8] - 80084d2: 2200 movs r2, #0 - 80084d4: 619a str r2, [r3, #24] - } + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8009922: 687b ldr r3, [r7, #4] + 8009924: 699b ldr r3, [r3, #24] + 8009926: 2b00 cmp r3, #0 + 8009928: d032 beq.n 8009990 + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800992a: 4b43 ldr r3, [pc, #268] ; (8009a38 ) + 800992c: 681b ldr r3, [r3, #0] + 800992e: 4a42 ldr r2, [pc, #264] ; (8009a38 ) + 8009930: f043 0301 orr.w r3, r3, #1 + 8009934: 6013 str r3, [r2, #0] - /* Transfer is completed */ - if (ep->xfer_len == 0U) - 80084d6: 68bb ldr r3, [r7, #8] - 80084d8: 699b ldr r3, [r3, #24] - 80084da: 2b00 cmp r3, #0 - 80084dc: f040 80b9 bne.w 8008652 - { - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 80084e0: 68bb ldr r3, [r7, #8] - 80084e2: 785b ldrb r3, [r3, #1] - 80084e4: 2b00 cmp r3, #0 - 80084e6: d126 bne.n 8008536 - 80084e8: 68fb ldr r3, [r7, #12] - 80084ea: 681b ldr r3, [r3, #0] - 80084ec: 62fb str r3, [r7, #44] ; 0x2c - 80084ee: 68fb ldr r3, [r7, #12] - 80084f0: 681b ldr r3, [r3, #0] - 80084f2: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 80084f6: b29b uxth r3, r3 - 80084f8: 461a mov r2, r3 - 80084fa: 6afb ldr r3, [r7, #44] ; 0x2c - 80084fc: 4413 add r3, r2 - 80084fe: 62fb str r3, [r7, #44] ; 0x2c - 8008500: 68bb ldr r3, [r7, #8] - 8008502: 781b ldrb r3, [r3, #0] - 8008504: 00da lsls r2, r3, #3 - 8008506: 6afb ldr r3, [r7, #44] ; 0x2c - 8008508: 4413 add r3, r2 - 800850a: f203 4302 addw r3, r3, #1026 ; 0x402 - 800850e: 62bb str r3, [r7, #40] ; 0x28 - 8008510: 6abb ldr r3, [r7, #40] ; 0x28 - 8008512: 881b ldrh r3, [r3, #0] - 8008514: b29b uxth r3, r3 - 8008516: f3c3 0309 ubfx r3, r3, #0, #10 - 800851a: b29a uxth r2, r3 - 800851c: 6abb ldr r3, [r7, #40] ; 0x28 - 800851e: 801a strh r2, [r3, #0] - 8008520: 6abb ldr r3, [r7, #40] ; 0x28 - 8008522: 881b ldrh r3, [r3, #0] - 8008524: b29b uxth r3, r3 - 8008526: ea6f 4343 mvn.w r3, r3, lsl #17 - 800852a: ea6f 4353 mvn.w r3, r3, lsr #17 - 800852e: b29a uxth r2, r3 - 8008530: 6abb ldr r3, [r7, #40] ; 0x28 - 8008532: 801a strh r2, [r3, #0] - 8008534: e01a b.n 800856c - 8008536: 68bb ldr r3, [r7, #8] - 8008538: 785b ldrb r3, [r3, #1] - 800853a: 2b01 cmp r3, #1 - 800853c: d116 bne.n 800856c - 800853e: 68fb ldr r3, [r7, #12] - 8008540: 681b ldr r3, [r3, #0] - 8008542: 637b str r3, [r7, #52] ; 0x34 - 8008544: 68fb ldr r3, [r7, #12] - 8008546: 681b ldr r3, [r3, #0] - 8008548: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800854c: b29b uxth r3, r3 - 800854e: 461a mov r2, r3 - 8008550: 6b7b ldr r3, [r7, #52] ; 0x34 - 8008552: 4413 add r3, r2 - 8008554: 637b str r3, [r7, #52] ; 0x34 - 8008556: 68bb ldr r3, [r7, #8] - 8008558: 781b ldrb r3, [r3, #0] - 800855a: 00da lsls r2, r3, #3 - 800855c: 6b7b ldr r3, [r7, #52] ; 0x34 - 800855e: 4413 add r3, r2 - 8008560: f203 4302 addw r3, r3, #1026 ; 0x402 - 8008564: 633b str r3, [r7, #48] ; 0x30 - 8008566: 6b3b ldr r3, [r7, #48] ; 0x30 - 8008568: 2200 movs r2, #0 - 800856a: 801a strh r2, [r3, #0] - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 800856c: 68fb ldr r3, [r7, #12] - 800856e: 681b ldr r3, [r3, #0] - 8008570: 627b str r3, [r7, #36] ; 0x24 - 8008572: 68bb ldr r3, [r7, #8] - 8008574: 785b ldrb r3, [r3, #1] - 8008576: 2b00 cmp r3, #0 - 8008578: d126 bne.n 80085c8 - 800857a: 68fb ldr r3, [r7, #12] - 800857c: 681b ldr r3, [r3, #0] - 800857e: 61fb str r3, [r7, #28] - 8008580: 68fb ldr r3, [r7, #12] - 8008582: 681b ldr r3, [r3, #0] - 8008584: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008588: b29b uxth r3, r3 - 800858a: 461a mov r2, r3 - 800858c: 69fb ldr r3, [r7, #28] - 800858e: 4413 add r3, r2 - 8008590: 61fb str r3, [r7, #28] - 8008592: 68bb ldr r3, [r7, #8] - 8008594: 781b ldrb r3, [r3, #0] - 8008596: 00da lsls r2, r3, #3 - 8008598: 69fb ldr r3, [r7, #28] - 800859a: 4413 add r3, r2 - 800859c: f203 4306 addw r3, r3, #1030 ; 0x406 - 80085a0: 61bb str r3, [r7, #24] - 80085a2: 69bb ldr r3, [r7, #24] - 80085a4: 881b ldrh r3, [r3, #0] - 80085a6: b29b uxth r3, r3 - 80085a8: f3c3 0309 ubfx r3, r3, #0, #10 - 80085ac: b29a uxth r2, r3 - 80085ae: 69bb ldr r3, [r7, #24] - 80085b0: 801a strh r2, [r3, #0] - 80085b2: 69bb ldr r3, [r7, #24] - 80085b4: 881b ldrh r3, [r3, #0] - 80085b6: b29b uxth r3, r3 - 80085b8: ea6f 4343 mvn.w r3, r3, lsl #17 - 80085bc: ea6f 4353 mvn.w r3, r3, lsr #17 - 80085c0: b29a uxth r2, r3 - 80085c2: 69bb ldr r3, [r7, #24] - 80085c4: 801a strh r2, [r3, #0] - 80085c6: e017 b.n 80085f8 - 80085c8: 68bb ldr r3, [r7, #8] - 80085ca: 785b ldrb r3, [r3, #1] - 80085cc: 2b01 cmp r3, #1 - 80085ce: d113 bne.n 80085f8 - 80085d0: 68fb ldr r3, [r7, #12] - 80085d2: 681b ldr r3, [r3, #0] - 80085d4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 80085d8: b29b uxth r3, r3 - 80085da: 461a mov r2, r3 - 80085dc: 6a7b ldr r3, [r7, #36] ; 0x24 - 80085de: 4413 add r3, r2 - 80085e0: 627b str r3, [r7, #36] ; 0x24 - 80085e2: 68bb ldr r3, [r7, #8] - 80085e4: 781b ldrb r3, [r3, #0] - 80085e6: 00da lsls r2, r3, #3 - 80085e8: 6a7b ldr r3, [r7, #36] ; 0x24 - 80085ea: 4413 add r3, r2 - 80085ec: f203 4306 addw r3, r3, #1030 ; 0x406 - 80085f0: 623b str r3, [r7, #32] - 80085f2: 6a3b ldr r3, [r7, #32] - 80085f4: 2200 movs r2, #0 - 80085f6: 801a strh r2, [r3, #0] + /* Get timeout */ + tickstart = HAL_GetTick(); + 8009936: f7fb fc8b bl 8005250 + 800993a: 6138 str r0, [r7, #16] - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); - 80085f8: 68bb ldr r3, [r7, #8] - 80085fa: 781b ldrb r3, [r3, #0] - 80085fc: 4619 mov r1, r3 - 80085fe: 68f8 ldr r0, [r7, #12] - 8008600: f007 ff91 bl 8010526 -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + /* Wait till MSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + 800993c: e008 b.n 8009950 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 800993e: f7fb fc87 bl 8005250 + 8009942: 4602 mov r2, r0 + 8009944: 693b ldr r3, [r7, #16] + 8009946: 1ad3 subs r3, r2, r3 + 8009948: 2b02 cmp r3, #2 + 800994a: d901 bls.n 8009950 + { + return HAL_TIMEOUT; + 800994c: 2303 movs r3, #3 + 800994e: e347 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + 8009950: 4b39 ldr r3, [pc, #228] ; (8009a38 ) + 8009952: 681b ldr r3, [r3, #0] + 8009954: f003 0302 and.w r3, r3, #2 + 8009958: 2b00 cmp r3, #0 + 800995a: d0f0 beq.n 800993e + } + } + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800995c: 4b36 ldr r3, [pc, #216] ; (8009a38 ) + 800995e: 681b ldr r3, [r3, #0] + 8009960: 4a35 ldr r2, [pc, #212] ; (8009a38 ) + 8009962: f043 0308 orr.w r3, r3, #8 + 8009966: 6013 str r3, [r2, #0] + 8009968: 4b33 ldr r3, [pc, #204] ; (8009a38 ) + 800996a: 681b ldr r3, [r3, #0] + 800996c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8009970: 687b ldr r3, [r7, #4] + 8009972: 6a1b ldr r3, [r3, #32] + 8009974: 4930 ldr r1, [pc, #192] ; (8009a38 ) + 8009976: 4313 orrs r3, r2 + 8009978: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800997a: 4b2f ldr r3, [pc, #188] ; (8009a38 ) + 800997c: 685b ldr r3, [r3, #4] + 800997e: f423 427f bic.w r2, r3, #65280 ; 0xff00 + 8009982: 687b ldr r3, [r7, #4] + 8009984: 69db ldr r3, [r3, #28] + 8009986: 021b lsls r3, r3, #8 + 8009988: 492b ldr r1, [pc, #172] ; (8009a38 ) + 800998a: 4313 orrs r3, r2 + 800998c: 604b str r3, [r1, #4] + 800998e: e01a b.n 80099c6 - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - 8008604: 88fb ldrh r3, [r7, #6] - 8008606: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800860a: 2b00 cmp r3, #0 - 800860c: f000 82fa beq.w 8008c04 - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - 8008610: 68fb ldr r3, [r7, #12] - 8008612: 681b ldr r3, [r3, #0] - 8008614: 461a mov r2, r3 - 8008616: 68bb ldr r3, [r7, #8] - 8008618: 781b ldrb r3, [r3, #0] - 800861a: 009b lsls r3, r3, #2 - 800861c: 4413 add r3, r2 - 800861e: 881b ldrh r3, [r3, #0] - 8008620: b29b uxth r3, r3 - 8008622: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8008626: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800862a: 82fb strh r3, [r7, #22] - 800862c: 68fb ldr r3, [r7, #12] - 800862e: 681b ldr r3, [r3, #0] - 8008630: 461a mov r2, r3 - 8008632: 68bb ldr r3, [r7, #8] - 8008634: 781b ldrb r3, [r3, #0] - 8008636: 009b lsls r3, r3, #2 - 8008638: 441a add r2, r3 - 800863a: 8afb ldrh r3, [r7, #22] - 800863c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008640: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008644: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 8008648: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800864c: b29b uxth r3, r3 - 800864e: 8013 strh r3, [r2, #0] - 8008650: e2d8 b.n 8008c04 } - } - else /* Transfer is not yet Done */ - { - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - 8008652: 88fb ldrh r3, [r7, #6] - 8008654: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8008658: 2b00 cmp r3, #0 - 800865a: d021 beq.n 80086a0 + else { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - 800865c: 68fb ldr r3, [r7, #12] - 800865e: 681b ldr r3, [r3, #0] - 8008660: 461a mov r2, r3 - 8008662: 68bb ldr r3, [r7, #8] - 8008664: 781b ldrb r3, [r3, #0] - 8008666: 009b lsls r3, r3, #2 - 8008668: 4413 add r3, r2 - 800866a: 881b ldrh r3, [r3, #0] - 800866c: b29b uxth r3, r3 - 800866e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8008672: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8008676: f8a7 308a strh.w r3, [r7, #138] ; 0x8a - 800867a: 68fb ldr r3, [r7, #12] - 800867c: 681b ldr r3, [r3, #0] - 800867e: 461a mov r2, r3 - 8008680: 68bb ldr r3, [r7, #8] - 8008682: 781b ldrb r3, [r3, #0] - 8008684: 009b lsls r3, r3, #2 - 8008686: 441a add r2, r3 - 8008688: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a - 800868c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008690: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008694: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 8008698: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800869c: b29b uxth r3, r3 - 800869e: 8013 strh r3, [r2, #0] - } + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8009990: 4b29 ldr r3, [pc, #164] ; (8009a38 ) + 8009992: 681b ldr r3, [r3, #0] + 8009994: 4a28 ldr r2, [pc, #160] ; (8009a38 ) + 8009996: f023 0301 bic.w r3, r3, #1 + 800999a: 6013 str r3, [r2, #0] - /* Still there is data to Fill in the next Buffer */ - if (ep->xfer_fill_db == 1U) - 80086a0: 68bb ldr r3, [r7, #8] - 80086a2: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 - 80086a6: 2b01 cmp r3, #1 - 80086a8: f040 82ac bne.w 8008c04 - { - ep->xfer_buff += TxPctSize; - 80086ac: 68bb ldr r3, [r7, #8] - 80086ae: 695a ldr r2, [r3, #20] - 80086b0: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 80086b4: 441a add r2, r3 - 80086b6: 68bb ldr r3, [r7, #8] - 80086b8: 615a str r2, [r3, #20] - ep->xfer_count += TxPctSize; - 80086ba: 68bb ldr r3, [r7, #8] - 80086bc: 69da ldr r2, [r3, #28] - 80086be: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 80086c2: 441a add r2, r3 - 80086c4: 68bb ldr r3, [r7, #8] - 80086c6: 61da str r2, [r3, #28] + /* Get timeout */ + tickstart = HAL_GetTick(); + 800999c: f7fb fc58 bl 8005250 + 80099a0: 6138 str r0, [r7, #16] - /* Calculate the len of the new buffer to fill */ - if (ep->xfer_len_db >= ep->maxpacket) - 80086c8: 68bb ldr r3, [r7, #8] - 80086ca: 6a1a ldr r2, [r3, #32] - 80086cc: 68bb ldr r3, [r7, #8] - 80086ce: 691b ldr r3, [r3, #16] - 80086d0: 429a cmp r2, r3 - 80086d2: d30b bcc.n 80086ec - { - len = ep->maxpacket; - 80086d4: 68bb ldr r3, [r7, #8] - 80086d6: 691b ldr r3, [r3, #16] - 80086d8: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_len_db -= len; - 80086dc: 68bb ldr r3, [r7, #8] - 80086de: 6a1a ldr r2, [r3, #32] - 80086e0: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 80086e4: 1ad2 subs r2, r2, r3 - 80086e6: 68bb ldr r3, [r7, #8] - 80086e8: 621a str r2, [r3, #32] - 80086ea: e017 b.n 800871c - } - else if (ep->xfer_len_db == 0U) - 80086ec: 68bb ldr r3, [r7, #8] - 80086ee: 6a1b ldr r3, [r3, #32] - 80086f0: 2b00 cmp r3, #0 - 80086f2: d108 bne.n 8008706 - { - len = TxPctSize; - 80086f4: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 80086f8: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_fill_db = 0U; - 80086fc: 68bb ldr r3, [r7, #8] - 80086fe: 2200 movs r2, #0 - 8008700: f883 2024 strb.w r2, [r3, #36] ; 0x24 - 8008704: e00a b.n 800871c - } - else + /* Wait till MSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) + 80099a2: e008 b.n 80099b6 { - ep->xfer_fill_db = 0U; - 8008706: 68bb ldr r3, [r7, #8] - 8008708: 2200 movs r2, #0 - 800870a: f883 2024 strb.w r2, [r3, #36] ; 0x24 - len = ep->xfer_len_db; - 800870e: 68bb ldr r3, [r7, #8] - 8008710: 6a1b ldr r3, [r3, #32] - 8008712: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_len_db = 0U; - 8008716: 68bb ldr r3, [r7, #8] - 8008718: 2200 movs r2, #0 - 800871a: 621a str r2, [r3, #32] + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80099a4: f7fb fc54 bl 8005250 + 80099a8: 4602 mov r2, r0 + 80099aa: 693b ldr r3, [r7, #16] + 80099ac: 1ad3 subs r3, r2, r3 + 80099ae: 2b02 cmp r3, #2 + 80099b0: d901 bls.n 80099b6 + { + return HAL_TIMEOUT; + 80099b2: 2303 movs r3, #3 + 80099b4: e314 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) + 80099b6: 4b20 ldr r3, [pc, #128] ; (8009a38 ) + 80099b8: 681b ldr r3, [r3, #0] + 80099ba: f003 0302 and.w r3, r3, #2 + 80099be: 2b00 cmp r3, #0 + 80099c0: d1f0 bne.n 80099a4 + 80099c2: e000 b.n 80099c6 + if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 80099c4: bf00 nop } - - /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); - 800871c: 68bb ldr r3, [r7, #8] - 800871e: 785b ldrb r3, [r3, #1] - 8008720: 2b00 cmp r3, #0 - 8008722: d165 bne.n 80087f0 - 8008724: 68fb ldr r3, [r7, #12] - 8008726: 681b ldr r3, [r3, #0] - 8008728: 63fb str r3, [r7, #60] ; 0x3c - 800872a: 68fb ldr r3, [r7, #12] - 800872c: 681b ldr r3, [r3, #0] - 800872e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008732: b29b uxth r3, r3 - 8008734: 461a mov r2, r3 - 8008736: 6bfb ldr r3, [r7, #60] ; 0x3c - 8008738: 4413 add r3, r2 - 800873a: 63fb str r3, [r7, #60] ; 0x3c - 800873c: 68bb ldr r3, [r7, #8] - 800873e: 781b ldrb r3, [r3, #0] - 8008740: 00da lsls r2, r3, #3 - 8008742: 6bfb ldr r3, [r7, #60] ; 0x3c - 8008744: 4413 add r3, r2 - 8008746: f203 4302 addw r3, r3, #1026 ; 0x402 - 800874a: 63bb str r3, [r7, #56] ; 0x38 - 800874c: 6bbb ldr r3, [r7, #56] ; 0x38 - 800874e: 881b ldrh r3, [r3, #0] - 8008750: b29b uxth r3, r3 - 8008752: f3c3 0309 ubfx r3, r3, #0, #10 - 8008756: b29a uxth r2, r3 - 8008758: 6bbb ldr r3, [r7, #56] ; 0x38 - 800875a: 801a strh r2, [r3, #0] - 800875c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008760: 2b3e cmp r3, #62 ; 0x3e - 8008762: d91d bls.n 80087a0 - 8008764: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008768: 095b lsrs r3, r3, #5 - 800876a: 64bb str r3, [r7, #72] ; 0x48 - 800876c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008770: f003 031f and.w r3, r3, #31 - 8008774: 2b00 cmp r3, #0 - 8008776: d102 bne.n 800877e - 8008778: 6cbb ldr r3, [r7, #72] ; 0x48 - 800877a: 3b01 subs r3, #1 - 800877c: 64bb str r3, [r7, #72] ; 0x48 - 800877e: 6bbb ldr r3, [r7, #56] ; 0x38 - 8008780: 881b ldrh r3, [r3, #0] - 8008782: b29a uxth r2, r3 - 8008784: 6cbb ldr r3, [r7, #72] ; 0x48 - 8008786: b29b uxth r3, r3 - 8008788: 029b lsls r3, r3, #10 - 800878a: b29b uxth r3, r3 - 800878c: 4313 orrs r3, r2 - 800878e: b29b uxth r3, r3 - 8008790: ea6f 4343 mvn.w r3, r3, lsl #17 - 8008794: ea6f 4353 mvn.w r3, r3, lsr #17 - 8008798: b29a uxth r2, r3 - 800879a: 6bbb ldr r3, [r7, #56] ; 0x38 - 800879c: 801a strh r2, [r3, #0] - 800879e: e044 b.n 800882a - 80087a0: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 80087a4: 2b00 cmp r3, #0 - 80087a6: d10a bne.n 80087be - 80087a8: 6bbb ldr r3, [r7, #56] ; 0x38 - 80087aa: 881b ldrh r3, [r3, #0] - 80087ac: b29b uxth r3, r3 - 80087ae: ea6f 4343 mvn.w r3, r3, lsl #17 - 80087b2: ea6f 4353 mvn.w r3, r3, lsr #17 - 80087b6: b29a uxth r2, r3 - 80087b8: 6bbb ldr r3, [r7, #56] ; 0x38 - 80087ba: 801a strh r2, [r3, #0] - 80087bc: e035 b.n 800882a - 80087be: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 80087c2: 085b lsrs r3, r3, #1 - 80087c4: 64bb str r3, [r7, #72] ; 0x48 - 80087c6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 80087ca: f003 0301 and.w r3, r3, #1 - 80087ce: 2b00 cmp r3, #0 - 80087d0: d002 beq.n 80087d8 - 80087d2: 6cbb ldr r3, [r7, #72] ; 0x48 - 80087d4: 3301 adds r3, #1 - 80087d6: 64bb str r3, [r7, #72] ; 0x48 - 80087d8: 6bbb ldr r3, [r7, #56] ; 0x38 - 80087da: 881b ldrh r3, [r3, #0] - 80087dc: b29a uxth r2, r3 - 80087de: 6cbb ldr r3, [r7, #72] ; 0x48 - 80087e0: b29b uxth r3, r3 - 80087e2: 029b lsls r3, r3, #10 - 80087e4: b29b uxth r3, r3 - 80087e6: 4313 orrs r3, r2 - 80087e8: b29a uxth r2, r3 - 80087ea: 6bbb ldr r3, [r7, #56] ; 0x38 - 80087ec: 801a strh r2, [r3, #0] - 80087ee: e01c b.n 800882a - 80087f0: 68bb ldr r3, [r7, #8] - 80087f2: 785b ldrb r3, [r3, #1] - 80087f4: 2b01 cmp r3, #1 - 80087f6: d118 bne.n 800882a - 80087f8: 68fb ldr r3, [r7, #12] - 80087fa: 681b ldr r3, [r3, #0] - 80087fc: 647b str r3, [r7, #68] ; 0x44 - 80087fe: 68fb ldr r3, [r7, #12] - 8008800: 681b ldr r3, [r3, #0] - 8008802: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008806: b29b uxth r3, r3 - 8008808: 461a mov r2, r3 - 800880a: 6c7b ldr r3, [r7, #68] ; 0x44 - 800880c: 4413 add r3, r2 - 800880e: 647b str r3, [r7, #68] ; 0x44 - 8008810: 68bb ldr r3, [r7, #8] - 8008812: 781b ldrb r3, [r3, #0] - 8008814: 00da lsls r2, r3, #3 - 8008816: 6c7b ldr r3, [r7, #68] ; 0x44 - 8008818: 4413 add r3, r2 - 800881a: f203 4302 addw r3, r3, #1026 ; 0x402 - 800881e: 643b str r3, [r7, #64] ; 0x40 - 8008820: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008824: b29a uxth r2, r3 - 8008826: 6c3b ldr r3, [r7, #64] ; 0x40 - 8008828: 801a strh r2, [r3, #0] - - /* Copy user buffer to USB PMA */ - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); - 800882a: 68fb ldr r3, [r7, #12] - 800882c: 6818 ldr r0, [r3, #0] - 800882e: 68bb ldr r3, [r7, #8] - 8008830: 6959 ldr r1, [r3, #20] - 8008832: 68bb ldr r3, [r7, #8] - 8008834: 891a ldrh r2, [r3, #8] - 8008836: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800883a: b29b uxth r3, r3 - 800883c: f005 ffab bl 800e796 - 8008840: e1e0 b.n 8008c04 + } } } - else /* Data Buffer1 ACK received */ + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80099c6: 687b ldr r3, [r7, #4] + 80099c8: 681b ldr r3, [r3, #0] + 80099ca: f003 0301 and.w r3, r3, #1 + 80099ce: 2b00 cmp r3, #0 + 80099d0: d073 beq.n 8009aba { - /* multi-packet on the NON control IN endpoint */ - TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - 8008842: 68fb ldr r3, [r7, #12] - 8008844: 681b ldr r3, [r3, #0] - 8008846: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800884a: b29b uxth r3, r3 - 800884c: 461a mov r2, r3 - 800884e: 68bb ldr r3, [r7, #8] - 8008850: 781b ldrb r3, [r3, #0] - 8008852: 00db lsls r3, r3, #3 - 8008854: 4413 add r3, r2 - 8008856: 68fa ldr r2, [r7, #12] - 8008858: 6812 ldr r2, [r2, #0] - 800885a: 4413 add r3, r2 - 800885c: f203 4306 addw r3, r3, #1030 ; 0x406 - 8008860: 881b ldrh r3, [r3, #0] - 8008862: f3c3 0309 ubfx r3, r3, #0, #10 - 8008866: f8a7 3086 strh.w r3, [r7, #134] ; 0x86 - - if (ep->xfer_len >= TxPctSize) - 800886a: 68bb ldr r3, [r7, #8] - 800886c: 699a ldr r2, [r3, #24] - 800886e: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 8008872: 429a cmp r2, r3 - 8008874: d307 bcc.n 8008886 - { - ep->xfer_len -= TxPctSize; - 8008876: 68bb ldr r3, [r7, #8] - 8008878: 699a ldr r2, [r3, #24] - 800887a: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 800887e: 1ad2 subs r2, r2, r3 - 8008880: 68bb ldr r3, [r7, #8] - 8008882: 619a str r2, [r3, #24] - 8008884: e002 b.n 800888c - } - else - { - ep->xfer_len = 0U; - 8008886: 68bb ldr r3, [r7, #8] - 8008888: 2200 movs r2, #0 - 800888a: 619a str r2, [r3, #24] - } + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* Transfer is completed */ - if (ep->xfer_len == 0U) - 800888c: 68bb ldr r3, [r7, #8] - 800888e: 699b ldr r3, [r3, #24] - 8008890: 2b00 cmp r3, #0 - 8008892: f040 80c0 bne.w 8008a16 + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_CFGR_SWS_HSE) || + 80099d2: 69bb ldr r3, [r7, #24] + 80099d4: 2b08 cmp r3, #8 + 80099d6: d005 beq.n 80099e4 + 80099d8: 69bb ldr r3, [r7, #24] + 80099da: 2b0c cmp r3, #12 + 80099dc: d10e bne.n 80099fc + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE))) + 80099de: 697b ldr r3, [r7, #20] + 80099e0: 2b03 cmp r3, #3 + 80099e2: d10b bne.n 80099fc { - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 8008896: 68bb ldr r3, [r7, #8] - 8008898: 785b ldrb r3, [r3, #1] - 800889a: 2b00 cmp r3, #0 - 800889c: d126 bne.n 80088ec - 800889e: 68fb ldr r3, [r7, #12] - 80088a0: 681b ldr r3, [r3, #0] - 80088a2: 67fb str r3, [r7, #124] ; 0x7c - 80088a4: 68fb ldr r3, [r7, #12] - 80088a6: 681b ldr r3, [r3, #0] - 80088a8: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 80088ac: b29b uxth r3, r3 - 80088ae: 461a mov r2, r3 - 80088b0: 6ffb ldr r3, [r7, #124] ; 0x7c - 80088b2: 4413 add r3, r2 - 80088b4: 67fb str r3, [r7, #124] ; 0x7c - 80088b6: 68bb ldr r3, [r7, #8] - 80088b8: 781b ldrb r3, [r3, #0] - 80088ba: 00da lsls r2, r3, #3 - 80088bc: 6ffb ldr r3, [r7, #124] ; 0x7c - 80088be: 4413 add r3, r2 - 80088c0: f203 4302 addw r3, r3, #1026 ; 0x402 - 80088c4: 67bb str r3, [r7, #120] ; 0x78 - 80088c6: 6fbb ldr r3, [r7, #120] ; 0x78 - 80088c8: 881b ldrh r3, [r3, #0] - 80088ca: b29b uxth r3, r3 - 80088cc: f3c3 0309 ubfx r3, r3, #0, #10 - 80088d0: b29a uxth r2, r3 - 80088d2: 6fbb ldr r3, [r7, #120] ; 0x78 - 80088d4: 801a strh r2, [r3, #0] - 80088d6: 6fbb ldr r3, [r7, #120] ; 0x78 - 80088d8: 881b ldrh r3, [r3, #0] - 80088da: b29b uxth r3, r3 - 80088dc: ea6f 4343 mvn.w r3, r3, lsl #17 - 80088e0: ea6f 4353 mvn.w r3, r3, lsr #17 - 80088e4: b29a uxth r2, r3 - 80088e6: 6fbb ldr r3, [r7, #120] ; 0x78 - 80088e8: 801a strh r2, [r3, #0] - 80088ea: e01a b.n 8008922 - 80088ec: 68bb ldr r3, [r7, #8] - 80088ee: 785b ldrb r3, [r3, #1] - 80088f0: 2b01 cmp r3, #1 - 80088f2: d116 bne.n 8008922 - 80088f4: 68fb ldr r3, [r7, #12] - 80088f6: 681b ldr r3, [r3, #0] - 80088f8: 667b str r3, [r7, #100] ; 0x64 - 80088fa: 68fb ldr r3, [r7, #12] - 80088fc: 681b ldr r3, [r3, #0] - 80088fe: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008902: b29b uxth r3, r3 - 8008904: 461a mov r2, r3 - 8008906: 6e7b ldr r3, [r7, #100] ; 0x64 - 8008908: 4413 add r3, r2 - 800890a: 667b str r3, [r7, #100] ; 0x64 - 800890c: 68bb ldr r3, [r7, #8] - 800890e: 781b ldrb r3, [r3, #0] - 8008910: 00da lsls r2, r3, #3 - 8008912: 6e7b ldr r3, [r7, #100] ; 0x64 - 8008914: 4413 add r3, r2 - 8008916: f203 4302 addw r3, r3, #1026 ; 0x402 - 800891a: 663b str r3, [r7, #96] ; 0x60 - 800891c: 6e3b ldr r3, [r7, #96] ; 0x60 - 800891e: 2200 movs r2, #0 - 8008920: 801a strh r2, [r3, #0] - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - 8008922: 68fb ldr r3, [r7, #12] - 8008924: 681b ldr r3, [r3, #0] - 8008926: 677b str r3, [r7, #116] ; 0x74 - 8008928: 68bb ldr r3, [r7, #8] - 800892a: 785b ldrb r3, [r3, #1] - 800892c: 2b00 cmp r3, #0 - 800892e: d12b bne.n 8008988 - 8008930: 68fb ldr r3, [r7, #12] - 8008932: 681b ldr r3, [r3, #0] - 8008934: 66fb str r3, [r7, #108] ; 0x6c - 8008936: 68fb ldr r3, [r7, #12] - 8008938: 681b ldr r3, [r3, #0] - 800893a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800893e: b29b uxth r3, r3 - 8008940: 461a mov r2, r3 - 8008942: 6efb ldr r3, [r7, #108] ; 0x6c - 8008944: 4413 add r3, r2 - 8008946: 66fb str r3, [r7, #108] ; 0x6c - 8008948: 68bb ldr r3, [r7, #8] - 800894a: 781b ldrb r3, [r3, #0] - 800894c: 00da lsls r2, r3, #3 - 800894e: 6efb ldr r3, [r7, #108] ; 0x6c - 8008950: 4413 add r3, r2 - 8008952: f203 4306 addw r3, r3, #1030 ; 0x406 - 8008956: f8c7 3080 str.w r3, [r7, #128] ; 0x80 - 800895a: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 800895e: 881b ldrh r3, [r3, #0] - 8008960: b29b uxth r3, r3 - 8008962: f3c3 0309 ubfx r3, r3, #0, #10 - 8008966: b29a uxth r2, r3 - 8008968: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 800896c: 801a strh r2, [r3, #0] - 800896e: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 8008972: 881b ldrh r3, [r3, #0] - 8008974: b29b uxth r3, r3 - 8008976: ea6f 4343 mvn.w r3, r3, lsl #17 - 800897a: ea6f 4353 mvn.w r3, r3, lsr #17 - 800897e: b29a uxth r2, r3 - 8008980: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 8008984: 801a strh r2, [r3, #0] - 8008986: e017 b.n 80089b8 - 8008988: 68bb ldr r3, [r7, #8] - 800898a: 785b ldrb r3, [r3, #1] - 800898c: 2b01 cmp r3, #1 - 800898e: d113 bne.n 80089b8 - 8008990: 68fb ldr r3, [r7, #12] - 8008992: 681b ldr r3, [r3, #0] - 8008994: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008998: b29b uxth r3, r3 - 800899a: 461a mov r2, r3 - 800899c: 6f7b ldr r3, [r7, #116] ; 0x74 - 800899e: 4413 add r3, r2 - 80089a0: 677b str r3, [r7, #116] ; 0x74 - 80089a2: 68bb ldr r3, [r7, #8] - 80089a4: 781b ldrb r3, [r3, #0] - 80089a6: 00da lsls r2, r3, #3 - 80089a8: 6f7b ldr r3, [r7, #116] ; 0x74 - 80089aa: 4413 add r3, r2 - 80089ac: f203 4306 addw r3, r3, #1030 ; 0x406 - 80089b0: 673b str r3, [r7, #112] ; 0x70 - 80089b2: 6f3b ldr r3, [r7, #112] ; 0x70 - 80089b4: 2200 movs r2, #0 - 80089b6: 801a strh r2, [r3, #0] - - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); - 80089b8: 68bb ldr r3, [r7, #8] - 80089ba: 781b ldrb r3, [r3, #0] - 80089bc: 4619 mov r1, r3 - 80089be: 68f8 ldr r0, [r7, #12] - 80089c0: f007 fdb1 bl 8010526 -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) == 0U) - 80089c4: 88fb ldrh r3, [r7, #6] - 80089c6: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 80089ca: 2b00 cmp r3, #0 - 80089cc: f040 811a bne.w 8008c04 + if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80099e4: 4b14 ldr r3, [pc, #80] ; (8009a38 ) + 80099e6: 681b ldr r3, [r3, #0] + 80099e8: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80099ec: 2b00 cmp r3, #0 + 80099ee: d063 beq.n 8009ab8 + 80099f0: 687b ldr r3, [r7, #4] + 80099f2: 685b ldr r3, [r3, #4] + 80099f4: 2b00 cmp r3, #0 + 80099f6: d15f bne.n 8009ab8 { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - 80089d0: 68fb ldr r3, [r7, #12] - 80089d2: 681b ldr r3, [r3, #0] - 80089d4: 461a mov r2, r3 - 80089d6: 68bb ldr r3, [r7, #8] - 80089d8: 781b ldrb r3, [r3, #0] - 80089da: 009b lsls r3, r3, #2 - 80089dc: 4413 add r3, r2 - 80089de: 881b ldrh r3, [r3, #0] - 80089e0: b29b uxth r3, r3 - 80089e2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 80089e6: f023 0370 bic.w r3, r3, #112 ; 0x70 - 80089ea: f8a7 3088 strh.w r3, [r7, #136] ; 0x88 - 80089ee: 68fb ldr r3, [r7, #12] - 80089f0: 681b ldr r3, [r3, #0] - 80089f2: 461a mov r2, r3 - 80089f4: 68bb ldr r3, [r7, #8] - 80089f6: 781b ldrb r3, [r3, #0] - 80089f8: 009b lsls r3, r3, #2 - 80089fa: 441a add r2, r3 - 80089fc: f8b7 3088 ldrh.w r3, [r7, #136] ; 0x88 - 8008a00: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008a04: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008a08: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 8008a0c: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8008a10: b29b uxth r3, r3 - 8008a12: 8013 strh r3, [r2, #0] - 8008a14: e0f6 b.n 8008c04 + return HAL_ERROR; + 80099f8: 2301 movs r3, #1 + 80099fa: e2f1 b.n 8009fe0 } } - else /* Transfer is not yet Done */ + else { - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) == 0U) - 8008a16: 88fb ldrh r3, [r7, #6] - 8008a18: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8008a1c: 2b00 cmp r3, #0 - 8008a1e: d121 bne.n 8008a64 - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - 8008a20: 68fb ldr r3, [r7, #12] - 8008a22: 681b ldr r3, [r3, #0] - 8008a24: 461a mov r2, r3 - 8008a26: 68bb ldr r3, [r7, #8] - 8008a28: 781b ldrb r3, [r3, #0] - 8008a2a: 009b lsls r3, r3, #2 - 8008a2c: 4413 add r3, r2 - 8008a2e: 881b ldrh r3, [r3, #0] - 8008a30: b29b uxth r3, r3 - 8008a32: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8008a36: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8008a3a: f8a7 304e strh.w r3, [r7, #78] ; 0x4e - 8008a3e: 68fb ldr r3, [r7, #12] - 8008a40: 681b ldr r3, [r3, #0] - 8008a42: 461a mov r2, r3 - 8008a44: 68bb ldr r3, [r7, #8] - 8008a46: 781b ldrb r3, [r3, #0] - 8008a48: 009b lsls r3, r3, #2 - 8008a4a: 441a add r2, r3 - 8008a4c: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e - 8008a50: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008a54: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008a58: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 8008a5c: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8008a60: b29b uxth r3, r3 - 8008a62: 8013 strh r3, [r2, #0] - } + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80099fc: 687b ldr r3, [r7, #4] + 80099fe: 685b ldr r3, [r3, #4] + 8009a00: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8009a04: d106 bne.n 8009a14 + 8009a06: 4b0c ldr r3, [pc, #48] ; (8009a38 ) + 8009a08: 681b ldr r3, [r3, #0] + 8009a0a: 4a0b ldr r2, [pc, #44] ; (8009a38 ) + 8009a0c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8009a10: 6013 str r3, [r2, #0] + 8009a12: e025 b.n 8009a60 + 8009a14: 687b ldr r3, [r7, #4] + 8009a16: 685b ldr r3, [r3, #4] + 8009a18: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8009a1c: d114 bne.n 8009a48 + 8009a1e: 4b06 ldr r3, [pc, #24] ; (8009a38 ) + 8009a20: 681b ldr r3, [r3, #0] + 8009a22: 4a05 ldr r2, [pc, #20] ; (8009a38 ) + 8009a24: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8009a28: 6013 str r3, [r2, #0] + 8009a2a: 4b03 ldr r3, [pc, #12] ; (8009a38 ) + 8009a2c: 681b ldr r3, [r3, #0] + 8009a2e: 4a02 ldr r2, [pc, #8] ; (8009a38 ) + 8009a30: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8009a34: 6013 str r3, [r2, #0] + 8009a36: e013 b.n 8009a60 + 8009a38: 40021000 .word 0x40021000 + 8009a3c: 0801aba4 .word 0x0801aba4 + 8009a40: 20000020 .word 0x20000020 + 8009a44: 20000024 .word 0x20000024 + 8009a48: 4ba0 ldr r3, [pc, #640] ; (8009ccc ) + 8009a4a: 681b ldr r3, [r3, #0] + 8009a4c: 4a9f ldr r2, [pc, #636] ; (8009ccc ) + 8009a4e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8009a52: 6013 str r3, [r2, #0] + 8009a54: 4b9d ldr r3, [pc, #628] ; (8009ccc ) + 8009a56: 681b ldr r3, [r3, #0] + 8009a58: 4a9c ldr r2, [pc, #624] ; (8009ccc ) + 8009a5a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8009a5e: 6013 str r3, [r2, #0] - /* Still there is data to Fill in the next Buffer */ - if (ep->xfer_fill_db == 1U) - 8008a64: 68bb ldr r3, [r7, #8] - 8008a66: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 - 8008a6a: 2b01 cmp r3, #1 - 8008a6c: f040 80ca bne.w 8008c04 + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8009a60: 687b ldr r3, [r7, #4] + 8009a62: 685b ldr r3, [r3, #4] + 8009a64: 2b00 cmp r3, #0 + 8009a66: d013 beq.n 8009a90 { - ep->xfer_buff += TxPctSize; - 8008a70: 68bb ldr r3, [r7, #8] - 8008a72: 695a ldr r2, [r3, #20] - 8008a74: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 8008a78: 441a add r2, r3 - 8008a7a: 68bb ldr r3, [r7, #8] - 8008a7c: 615a str r2, [r3, #20] - ep->xfer_count += TxPctSize; - 8008a7e: 68bb ldr r3, [r7, #8] - 8008a80: 69da ldr r2, [r3, #28] - 8008a82: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 8008a86: 441a add r2, r3 - 8008a88: 68bb ldr r3, [r7, #8] - 8008a8a: 61da str r2, [r3, #28] + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009a68: f7fb fbf2 bl 8005250 + 8009a6c: 6138 str r0, [r7, #16] - /* Calculate the len of the new buffer to fill */ - if (ep->xfer_len_db >= ep->maxpacket) - 8008a8c: 68bb ldr r3, [r7, #8] - 8008a8e: 6a1a ldr r2, [r3, #32] - 8008a90: 68bb ldr r3, [r7, #8] - 8008a92: 691b ldr r3, [r3, #16] - 8008a94: 429a cmp r2, r3 - 8008a96: d30b bcc.n 8008ab0 - { - len = ep->maxpacket; - 8008a98: 68bb ldr r3, [r7, #8] - 8008a9a: 691b ldr r3, [r3, #16] - 8008a9c: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_len_db -= len; - 8008aa0: 68bb ldr r3, [r7, #8] - 8008aa2: 6a1a ldr r2, [r3, #32] - 8008aa4: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008aa8: 1ad2 subs r2, r2, r3 - 8008aaa: 68bb ldr r3, [r7, #8] - 8008aac: 621a str r2, [r3, #32] - 8008aae: e017 b.n 8008ae0 - } - else if (ep->xfer_len_db == 0U) - 8008ab0: 68bb ldr r3, [r7, #8] - 8008ab2: 6a1b ldr r3, [r3, #32] - 8008ab4: 2b00 cmp r3, #0 - 8008ab6: d108 bne.n 8008aca + /* Wait till HSE is ready */ + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 8009a6e: e008 b.n 8009a82 { - len = TxPctSize; - 8008ab8: f8b7 3086 ldrh.w r3, [r7, #134] ; 0x86 - 8008abc: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_fill_db = 0U; - 8008ac0: 68bb ldr r3, [r7, #8] - 8008ac2: 2200 movs r2, #0 - 8008ac4: f883 2024 strb.w r2, [r3, #36] ; 0x24 - 8008ac8: e00a b.n 8008ae0 + if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8009a70: f7fb fbee bl 8005250 + 8009a74: 4602 mov r2, r0 + 8009a76: 693b ldr r3, [r7, #16] + 8009a78: 1ad3 subs r3, r2, r3 + 8009a7a: 2b64 cmp r3, #100 ; 0x64 + 8009a7c: d901 bls.n 8009a82 + { + return HAL_TIMEOUT; + 8009a7e: 2303 movs r3, #3 + 8009a80: e2ae b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 8009a82: 4b92 ldr r3, [pc, #584] ; (8009ccc ) + 8009a84: 681b ldr r3, [r3, #0] + 8009a86: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8009a8a: 2b00 cmp r3, #0 + 8009a8c: d0f0 beq.n 8009a70 + 8009a8e: e014 b.n 8009aba } - else + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009a90: f7fb fbde bl 8005250 + 8009a94: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 8009a96: e008 b.n 8009aaa { - len = ep->xfer_len_db; - 8008aca: 68bb ldr r3, [r7, #8] - 8008acc: 6a1b ldr r3, [r3, #32] - 8008ace: f8c7 308c str.w r3, [r7, #140] ; 0x8c - ep->xfer_len_db = 0U; - 8008ad2: 68bb ldr r3, [r7, #8] - 8008ad4: 2200 movs r2, #0 - 8008ad6: 621a str r2, [r3, #32] - ep->xfer_fill_db = 0; - 8008ad8: 68bb ldr r3, [r7, #8] - 8008ada: 2200 movs r2, #0 - 8008adc: f883 2024 strb.w r2, [r3, #36] ; 0x24 + if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8009a98: f7fb fbda bl 8005250 + 8009a9c: 4602 mov r2, r0 + 8009a9e: 693b ldr r3, [r7, #16] + 8009aa0: 1ad3 subs r3, r2, r3 + 8009aa2: 2b64 cmp r3, #100 ; 0x64 + 8009aa4: d901 bls.n 8009aaa + { + return HAL_TIMEOUT; + 8009aa6: 2303 movs r3, #3 + 8009aa8: e29a b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 8009aaa: 4b88 ldr r3, [pc, #544] ; (8009ccc ) + 8009aac: 681b ldr r3, [r3, #0] + 8009aae: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8009ab2: 2b00 cmp r3, #0 + 8009ab4: d1f0 bne.n 8009a98 + 8009ab6: e000 b.n 8009aba + if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8009ab8: bf00 nop } - - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); - 8008ae0: 68fb ldr r3, [r7, #12] - 8008ae2: 681b ldr r3, [r3, #0] - 8008ae4: 657b str r3, [r7, #84] ; 0x54 - 8008ae6: 68bb ldr r3, [r7, #8] - 8008ae8: 785b ldrb r3, [r3, #1] - 8008aea: 2b00 cmp r3, #0 - 8008aec: d165 bne.n 8008bba - 8008aee: 68fb ldr r3, [r7, #12] - 8008af0: 681b ldr r3, [r3, #0] - 8008af2: 65fb str r3, [r7, #92] ; 0x5c - 8008af4: 68fb ldr r3, [r7, #12] - 8008af6: 681b ldr r3, [r3, #0] - 8008af8: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008afc: b29b uxth r3, r3 - 8008afe: 461a mov r2, r3 - 8008b00: 6dfb ldr r3, [r7, #92] ; 0x5c - 8008b02: 4413 add r3, r2 - 8008b04: 65fb str r3, [r7, #92] ; 0x5c - 8008b06: 68bb ldr r3, [r7, #8] - 8008b08: 781b ldrb r3, [r3, #0] - 8008b0a: 00da lsls r2, r3, #3 - 8008b0c: 6dfb ldr r3, [r7, #92] ; 0x5c - 8008b0e: 4413 add r3, r2 - 8008b10: f203 4306 addw r3, r3, #1030 ; 0x406 - 8008b14: 65bb str r3, [r7, #88] ; 0x58 - 8008b16: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b18: 881b ldrh r3, [r3, #0] - 8008b1a: b29b uxth r3, r3 - 8008b1c: f3c3 0309 ubfx r3, r3, #0, #10 - 8008b20: b29a uxth r2, r3 - 8008b22: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b24: 801a strh r2, [r3, #0] - 8008b26: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b2a: 2b3e cmp r3, #62 ; 0x3e - 8008b2c: d91d bls.n 8008b6a - 8008b2e: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b32: 095b lsrs r3, r3, #5 - 8008b34: 66bb str r3, [r7, #104] ; 0x68 - 8008b36: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b3a: f003 031f and.w r3, r3, #31 - 8008b3e: 2b00 cmp r3, #0 - 8008b40: d102 bne.n 8008b48 - 8008b42: 6ebb ldr r3, [r7, #104] ; 0x68 - 8008b44: 3b01 subs r3, #1 - 8008b46: 66bb str r3, [r7, #104] ; 0x68 - 8008b48: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b4a: 881b ldrh r3, [r3, #0] - 8008b4c: b29a uxth r2, r3 - 8008b4e: 6ebb ldr r3, [r7, #104] ; 0x68 - 8008b50: b29b uxth r3, r3 - 8008b52: 029b lsls r3, r3, #10 - 8008b54: b29b uxth r3, r3 - 8008b56: 4313 orrs r3, r2 - 8008b58: b29b uxth r3, r3 - 8008b5a: ea6f 4343 mvn.w r3, r3, lsl #17 - 8008b5e: ea6f 4353 mvn.w r3, r3, lsr #17 - 8008b62: b29a uxth r2, r3 - 8008b64: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b66: 801a strh r2, [r3, #0] - 8008b68: e041 b.n 8008bee - 8008b6a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b6e: 2b00 cmp r3, #0 - 8008b70: d10a bne.n 8008b88 - 8008b72: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b74: 881b ldrh r3, [r3, #0] - 8008b76: b29b uxth r3, r3 - 8008b78: ea6f 4343 mvn.w r3, r3, lsl #17 - 8008b7c: ea6f 4353 mvn.w r3, r3, lsr #17 - 8008b80: b29a uxth r2, r3 - 8008b82: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008b84: 801a strh r2, [r3, #0] - 8008b86: e032 b.n 8008bee - 8008b88: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b8c: 085b lsrs r3, r3, #1 - 8008b8e: 66bb str r3, [r7, #104] ; 0x68 - 8008b90: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008b94: f003 0301 and.w r3, r3, #1 - 8008b98: 2b00 cmp r3, #0 - 8008b9a: d002 beq.n 8008ba2 - 8008b9c: 6ebb ldr r3, [r7, #104] ; 0x68 - 8008b9e: 3301 adds r3, #1 - 8008ba0: 66bb str r3, [r7, #104] ; 0x68 - 8008ba2: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008ba4: 881b ldrh r3, [r3, #0] - 8008ba6: b29a uxth r2, r3 - 8008ba8: 6ebb ldr r3, [r7, #104] ; 0x68 - 8008baa: b29b uxth r3, r3 - 8008bac: 029b lsls r3, r3, #10 - 8008bae: b29b uxth r3, r3 - 8008bb0: 4313 orrs r3, r2 - 8008bb2: b29a uxth r2, r3 - 8008bb4: 6dbb ldr r3, [r7, #88] ; 0x58 - 8008bb6: 801a strh r2, [r3, #0] - 8008bb8: e019 b.n 8008bee - 8008bba: 68bb ldr r3, [r7, #8] - 8008bbc: 785b ldrb r3, [r3, #1] - 8008bbe: 2b01 cmp r3, #1 - 8008bc0: d115 bne.n 8008bee - 8008bc2: 68fb ldr r3, [r7, #12] - 8008bc4: 681b ldr r3, [r3, #0] - 8008bc6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 8008bca: b29b uxth r3, r3 - 8008bcc: 461a mov r2, r3 - 8008bce: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008bd0: 4413 add r3, r2 - 8008bd2: 657b str r3, [r7, #84] ; 0x54 - 8008bd4: 68bb ldr r3, [r7, #8] - 8008bd6: 781b ldrb r3, [r3, #0] - 8008bd8: 00da lsls r2, r3, #3 - 8008bda: 6d7b ldr r3, [r7, #84] ; 0x54 - 8008bdc: 4413 add r3, r2 - 8008bde: f203 4306 addw r3, r3, #1030 ; 0x406 - 8008be2: 653b str r3, [r7, #80] ; 0x50 - 8008be4: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008be8: b29a uxth r2, r3 - 8008bea: 6d3b ldr r3, [r7, #80] ; 0x50 - 8008bec: 801a strh r2, [r3, #0] - - /* Copy the user buffer to USB PMA */ - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); - 8008bee: 68fb ldr r3, [r7, #12] - 8008bf0: 6818 ldr r0, [r3, #0] - 8008bf2: 68bb ldr r3, [r7, #8] - 8008bf4: 6959 ldr r1, [r3, #20] - 8008bf6: 68bb ldr r3, [r7, #8] - 8008bf8: 895a ldrh r2, [r3, #10] - 8008bfa: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 8008bfe: b29b uxth r3, r3 - 8008c00: f005 fdc9 bl 800e796 } } } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8009aba: 687b ldr r3, [r7, #4] + 8009abc: 681b ldr r3, [r3, #0] + 8009abe: f003 0302 and.w r3, r3, #2 + 8009ac2: 2b00 cmp r3, #0 + 8009ac4: d060 beq.n 8009b88 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /*enable endpoint IN*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); - 8008c04: 68fb ldr r3, [r7, #12] - 8008c06: 681b ldr r3, [r3, #0] - 8008c08: 461a mov r2, r3 - 8008c0a: 68bb ldr r3, [r7, #8] - 8008c0c: 781b ldrb r3, [r3, #0] - 8008c0e: 009b lsls r3, r3, #2 - 8008c10: 4413 add r3, r2 - 8008c12: 881b ldrh r3, [r3, #0] - 8008c14: b29b uxth r3, r3 - 8008c16: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 8008c1a: f023 0340 bic.w r3, r3, #64 ; 0x40 - 8008c1e: 82bb strh r3, [r7, #20] - 8008c20: 8abb ldrh r3, [r7, #20] - 8008c22: f083 0310 eor.w r3, r3, #16 - 8008c26: 82bb strh r3, [r7, #20] - 8008c28: 8abb ldrh r3, [r7, #20] - 8008c2a: f083 0320 eor.w r3, r3, #32 - 8008c2e: 82bb strh r3, [r7, #20] - 8008c30: 68fb ldr r3, [r7, #12] - 8008c32: 681b ldr r3, [r3, #0] - 8008c34: 461a mov r2, r3 - 8008c36: 68bb ldr r3, [r7, #8] - 8008c38: 781b ldrb r3, [r3, #0] - 8008c3a: 009b lsls r3, r3, #2 - 8008c3c: 441a add r2, r3 - 8008c3e: 8abb ldrh r3, [r7, #20] - 8008c40: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 8008c44: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 8008c48: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 8008c4c: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8008c50: b29b uxth r3, r3 - 8008c52: 8013 strh r3, [r2, #0] - - return HAL_OK; - 8008c54: 2300 movs r3, #0 -} - 8008c56: 4618 mov r0, r3 - 8008c58: 3790 adds r7, #144 ; 0x90 - 8008c5a: 46bd mov sp, r7 - 8008c5c: bd80 pop {r7, pc} - -08008c5e : - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, - uint16_t ep_kind, uint32_t pmaadress) -{ - 8008c5e: b480 push {r7} - 8008c60: b087 sub sp, #28 - 8008c62: af00 add r7, sp, #0 - 8008c64: 60f8 str r0, [r7, #12] - 8008c66: 607b str r3, [r7, #4] - 8008c68: 460b mov r3, r1 - 8008c6a: 817b strh r3, [r7, #10] - 8008c6c: 4613 mov r3, r2 - 8008c6e: 813b strh r3, [r7, #8] - PCD_EPTypeDef *ep; - - /* initialize ep structure*/ - if ((0x80U & ep_addr) == 0x80U) - 8008c70: 897b ldrh r3, [r7, #10] - 8008c72: f003 0380 and.w r3, r3, #128 ; 0x80 - 8008c76: b29b uxth r3, r3 - 8008c78: 2b00 cmp r3, #0 - 8008c7a: d00b beq.n 8008c94 - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - 8008c7c: 897b ldrh r3, [r7, #10] - 8008c7e: f003 0307 and.w r3, r3, #7 - 8008c82: 1c5a adds r2, r3, #1 - 8008c84: 4613 mov r3, r2 - 8008c86: 009b lsls r3, r3, #2 - 8008c88: 4413 add r3, r2 - 8008c8a: 00db lsls r3, r3, #3 - 8008c8c: 68fa ldr r2, [r7, #12] - 8008c8e: 4413 add r3, r2 - 8008c90: 617b str r3, [r7, #20] - 8008c92: e009 b.n 8008ca8 - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - 8008c94: 897a ldrh r2, [r7, #10] - 8008c96: 4613 mov r3, r2 - 8008c98: 009b lsls r3, r3, #2 - 8008c9a: 4413 add r3, r2 - 8008c9c: 00db lsls r3, r3, #3 - 8008c9e: f503 73b4 add.w r3, r3, #360 ; 0x168 - 8008ca2: 68fa ldr r2, [r7, #12] - 8008ca4: 4413 add r3, r2 - 8008ca6: 617b str r3, [r7, #20] - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - 8008ca8: 893b ldrh r3, [r7, #8] - 8008caa: 2b00 cmp r3, #0 - 8008cac: d107 bne.n 8008cbe - { - /* Single Buffer */ - ep->doublebuffer = 0U; - 8008cae: 697b ldr r3, [r7, #20] - 8008cb0: 2200 movs r2, #0 - 8008cb2: 731a strb r2, [r3, #12] - /* Configure the PMA */ - ep->pmaadress = (uint16_t)pmaadress; - 8008cb4: 687b ldr r3, [r7, #4] - 8008cb6: b29a uxth r2, r3 - 8008cb8: 697b ldr r3, [r7, #20] - 8008cba: 80da strh r2, [r3, #6] - 8008cbc: e00b b.n 8008cd6 - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else /* USB_DBL_BUF */ - { - /* Double Buffer Endpoint */ - ep->doublebuffer = 1U; - 8008cbe: 697b ldr r3, [r7, #20] - 8008cc0: 2201 movs r2, #1 - 8008cc2: 731a strb r2, [r3, #12] - /* Configure the PMA */ - ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); - 8008cc4: 687b ldr r3, [r7, #4] - 8008cc6: b29a uxth r2, r3 - 8008cc8: 697b ldr r3, [r7, #20] - 8008cca: 811a strh r2, [r3, #8] - ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); - 8008ccc: 687b ldr r3, [r7, #4] - 8008cce: 0c1b lsrs r3, r3, #16 - 8008cd0: b29a uxth r2, r3 - 8008cd2: 697b ldr r3, [r7, #20] - 8008cd4: 815a strh r2, [r3, #10] - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return HAL_OK; - 8008cd6: 2300 movs r3, #0 -} - 8008cd8: 4618 mov r0, r3 - 8008cda: 371c adds r7, #28 - 8008cdc: 46bd mov sp, r7 - 8008cde: f85d 7b04 ldr.w r7, [sp], #4 - 8008ce2: 4770 bx lr + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_CFGR_SWS_HSI) || + 8009ac6: 69bb ldr r3, [r7, #24] + 8009ac8: 2b04 cmp r3, #4 + 8009aca: d005 beq.n 8009ad8 + 8009acc: 69bb ldr r3, [r7, #24] + 8009ace: 2b0c cmp r3, #12 + 8009ad0: d119 bne.n 8009b06 + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI))) + 8009ad2: 697b ldr r3, [r7, #20] + 8009ad4: 2b02 cmp r3, #2 + 8009ad6: d116 bne.n 8009b06 + { + /* When HSI is used as system clock it will not be disabled */ + if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 8009ad8: 4b7c ldr r3, [pc, #496] ; (8009ccc ) + 8009ada: 681b ldr r3, [r3, #0] + 8009adc: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8009ae0: 2b00 cmp r3, #0 + 8009ae2: d005 beq.n 8009af0 + 8009ae4: 687b ldr r3, [r7, #4] + 8009ae6: 68db ldr r3, [r3, #12] + 8009ae8: 2b00 cmp r3, #0 + 8009aea: d101 bne.n 8009af0 + { + return HAL_ERROR; + 8009aec: 2301 movs r3, #1 + 8009aee: e277 b.n 8009fe0 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8009af0: 4b76 ldr r3, [pc, #472] ; (8009ccc ) + 8009af2: 685b ldr r3, [r3, #4] + 8009af4: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 + 8009af8: 687b ldr r3, [r7, #4] + 8009afa: 691b ldr r3, [r3, #16] + 8009afc: 061b lsls r3, r3, #24 + 8009afe: 4973 ldr r1, [pc, #460] ; (8009ccc ) + 8009b00: 4313 orrs r3, r2 + 8009b02: 604b str r3, [r1, #4] + if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 8009b04: e040 b.n 8009b88 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8009b06: 687b ldr r3, [r7, #4] + 8009b08: 68db ldr r3, [r3, #12] + 8009b0a: 2b00 cmp r3, #0 + 8009b0c: d023 beq.n 8009b56 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8009b0e: 4b6f ldr r3, [pc, #444] ; (8009ccc ) + 8009b10: 681b ldr r3, [r3, #0] + 8009b12: 4a6e ldr r2, [pc, #440] ; (8009ccc ) + 8009b14: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8009b18: 6013 str r3, [r2, #0] -08008ce4 : - * @brief Activate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - 8008ce4: b480 push {r7} - 8008ce6: b085 sub sp, #20 - 8008ce8: af00 add r7, sp, #0 - 8008cea: 6078 str r0, [r7, #4] + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009b1a: f7fb fb99 bl 8005250 + 8009b1e: 6138 str r0, [r7, #16] - USB_TypeDef *USBx = hpcd->Instance; - 8008cec: 687b ldr r3, [r7, #4] - 8008cee: 681b ldr r3, [r3, #0] - 8008cf0: 60fb str r3, [r7, #12] - hpcd->lpm_active = 1U; - 8008cf2: 687b ldr r3, [r7, #4] - 8008cf4: 2201 movs r2, #1 - 8008cf6: f8c3 22ec str.w r2, [r3, #748] ; 0x2ec - hpcd->LPM_State = LPM_L0; - 8008cfa: 687b ldr r3, [r7, #4] - 8008cfc: 2200 movs r2, #0 - 8008cfe: f883 22e0 strb.w r2, [r3, #736] ; 0x2e0 + /* Wait till HSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 8009b20: e008 b.n 8009b34 + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8009b22: f7fb fb95 bl 8005250 + 8009b26: 4602 mov r2, r0 + 8009b28: 693b ldr r3, [r7, #16] + 8009b2a: 1ad3 subs r3, r2, r3 + 8009b2c: 2b02 cmp r3, #2 + 8009b2e: d901 bls.n 8009b34 + { + return HAL_TIMEOUT; + 8009b30: 2303 movs r3, #3 + 8009b32: e255 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 8009b34: 4b65 ldr r3, [pc, #404] ; (8009ccc ) + 8009b36: 681b ldr r3, [r3, #0] + 8009b38: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8009b3c: 2b00 cmp r3, #0 + 8009b3e: d0f0 beq.n 8009b22 + } + } - USBx->LPMCSR |= USB_LPMCSR_LMPEN; - 8008d02: 68fb ldr r3, [r7, #12] - 8008d04: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 - 8008d08: b29b uxth r3, r3 - 8008d0a: f043 0301 orr.w r3, r3, #1 - 8008d0e: b29a uxth r2, r3 - 8008d10: 68fb ldr r3, [r7, #12] - 8008d12: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 - USBx->LPMCSR |= USB_LPMCSR_LPMACK; - 8008d16: 68fb ldr r3, [r7, #12] - 8008d18: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 - 8008d1c: b29b uxth r3, r3 - 8008d1e: f043 0302 orr.w r3, r3, #2 - 8008d22: b29a uxth r2, r3 - 8008d24: 68fb ldr r3, [r7, #12] - 8008d26: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8009b40: 4b62 ldr r3, [pc, #392] ; (8009ccc ) + 8009b42: 685b ldr r3, [r3, #4] + 8009b44: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 + 8009b48: 687b ldr r3, [r7, #4] + 8009b4a: 691b ldr r3, [r3, #16] + 8009b4c: 061b lsls r3, r3, #24 + 8009b4e: 495f ldr r1, [pc, #380] ; (8009ccc ) + 8009b50: 4313 orrs r3, r2 + 8009b52: 604b str r3, [r1, #4] + 8009b54: e018 b.n 8009b88 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8009b56: 4b5d ldr r3, [pc, #372] ; (8009ccc ) + 8009b58: 681b ldr r3, [r3, #0] + 8009b5a: 4a5c ldr r2, [pc, #368] ; (8009ccc ) + 8009b5c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8009b60: 6013 str r3, [r2, #0] - return HAL_OK; - 8008d2a: 2300 movs r3, #0 -} - 8008d2c: 4618 mov r0, r3 - 8008d2e: 3714 adds r7, #20 - 8008d30: 46bd mov sp, r7 - 8008d32: f85d 7b04 ldr.w r7, [sp], #4 - 8008d36: 4770 bx lr + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009b62: f7fb fb75 bl 8005250 + 8009b66: 6138 str r0, [r7, #16] -08008d38 : - * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 - * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - 8008d38: b480 push {r7} - 8008d3a: af00 add r7, sp, #0 - else - { - return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; + /* Wait till HSI is disabled */ + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 8009b68: e008 b.n 8009b7c + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8009b6a: f7fb fb71 bl 8005250 + 8009b6e: 4602 mov r2, r0 + 8009b70: 693b ldr r3, [r7, #16] + 8009b72: 1ad3 subs r3, r2, r3 + 8009b74: 2b02 cmp r3, #2 + 8009b76: d901 bls.n 8009b7c + { + return HAL_TIMEOUT; + 8009b78: 2303 movs r3, #3 + 8009b7a: e231 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 8009b7c: 4b53 ldr r3, [pc, #332] ; (8009ccc ) + 8009b7e: 681b ldr r3, [r3, #0] + 8009b80: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8009b84: 2b00 cmp r3, #0 + 8009b86: d1f0 bne.n 8009b6a + } + } } -#else - return (PWR->CR1 & PWR_CR1_VOS); - 8008d3c: 4b04 ldr r3, [pc, #16] ; (8008d50 ) - 8008d3e: 681b ldr r3, [r3, #0] - 8008d40: f403 63c0 and.w r3, r3, #1536 ; 0x600 -#endif -} - 8008d44: 4618 mov r0, r3 - 8008d46: 46bd mov sp, r7 - 8008d48: f85d 7b04 ldr.w r7, [sp], #4 - 8008d4c: 4770 bx lr - 8008d4e: bf00 nop - 8008d50: 40007000 .word 0x40007000 - -08008d54 : - * cleared before returning the status. If the flag is not cleared within - * 50 microseconds, HAL_TIMEOUT status is reported. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - 8008d54: b480 push {r7} - 8008d56: b085 sub sp, #20 - 8008d58: af00 add r7, sp, #0 - 8008d5a: 6078 str r0, [r7, #4] } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8009b88: 687b ldr r3, [r7, #4] + 8009b8a: 681b ldr r3, [r3, #0] + 8009b8c: f003 0308 and.w r3, r3, #8 + 8009b90: 2b00 cmp r3, #0 + 8009b92: d03c beq.n 8009c0e + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); -#else + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8009b94: 687b ldr r3, [r7, #4] + 8009b96: 695b ldr r3, [r3, #20] + 8009b98: 2b00 cmp r3, #0 + 8009b9a: d01c beq.n 8009bd6 + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv); + } +#endif /* RCC_CSR_LSIPREDIV */ - /* If Set Range 1 */ - if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - 8008d5c: 687b ldr r3, [r7, #4] - 8008d5e: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8008d62: d130 bne.n 8008dc6 - { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) - 8008d64: 4b23 ldr r3, [pc, #140] ; (8008df4 ) - 8008d66: 681b ldr r3, [r3, #0] - 8008d68: f403 63c0 and.w r3, r3, #1536 ; 0x600 - 8008d6c: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8008d70: d038 beq.n 8008de4 - { - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - 8008d72: 4b20 ldr r3, [pc, #128] ; (8008df4 ) - 8008d74: 681b ldr r3, [r3, #0] - 8008d76: f423 63c0 bic.w r3, r3, #1536 ; 0x600 - 8008d7a: 4a1e ldr r2, [pc, #120] ; (8008df4 ) - 8008d7c: f443 7300 orr.w r3, r3, #512 ; 0x200 - 8008d80: 6013 str r3, [r2, #0] + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8009b9c: 4b4b ldr r3, [pc, #300] ; (8009ccc ) + 8009b9e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8009ba2: 4a4a ldr r2, [pc, #296] ; (8009ccc ) + 8009ba4: f043 0301 orr.w r3, r3, #1 + 8009ba8: f8c2 3094 str.w r3, [r2, #148] ; 0x94 - /* Wait until VOSF is cleared */ - wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; - 8008d82: 4b1d ldr r3, [pc, #116] ; (8008df8 ) - 8008d84: 681b ldr r3, [r3, #0] - 8008d86: 2232 movs r2, #50 ; 0x32 - 8008d88: fb02 f303 mul.w r3, r2, r3 - 8008d8c: 4a1b ldr r2, [pc, #108] ; (8008dfc ) - 8008d8e: fba2 2303 umull r2, r3, r2, r3 - 8008d92: 0c9b lsrs r3, r3, #18 - 8008d94: 3301 adds r3, #1 - 8008d96: 60fb str r3, [r7, #12] - while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8008d98: e002 b.n 8008da0 + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009bac: f7fb fb50 bl 8005250 + 8009bb0: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 8009bb2: e008 b.n 8009bc6 { - wait_loop_index--; - 8008d9a: 68fb ldr r3, [r7, #12] - 8008d9c: 3b01 subs r3, #1 - 8008d9e: 60fb str r3, [r7, #12] - while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8008da0: 4b14 ldr r3, [pc, #80] ; (8008df4 ) - 8008da2: 695b ldr r3, [r3, #20] - 8008da4: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8008da8: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 8008dac: d102 bne.n 8008db4 - 8008dae: 68fb ldr r3, [r7, #12] - 8008db0: 2b00 cmp r3, #0 - 8008db2: d1f2 bne.n 8008d9a + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8009bb4: f7fb fb4c bl 8005250 + 8009bb8: 4602 mov r2, r0 + 8009bba: 693b ldr r3, [r7, #16] + 8009bbc: 1ad3 subs r3, r2, r3 + 8009bbe: 2b02 cmp r3, #2 + 8009bc0: d901 bls.n 8009bc6 + { + return HAL_TIMEOUT; + 8009bc2: 2303 movs r3, #3 + 8009bc4: e20c b.n 8009fe0 + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 8009bc6: 4b41 ldr r3, [pc, #260] ; (8009ccc ) + 8009bc8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8009bcc: f003 0302 and.w r3, r3, #2 + 8009bd0: 2b00 cmp r3, #0 + 8009bd2: d0ef beq.n 8009bb4 + 8009bd4: e01b b.n 8009c0e } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - 8008db4: 4b0f ldr r3, [pc, #60] ; (8008df4 ) - 8008db6: 695b ldr r3, [r3, #20] - 8008db8: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8008dbc: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 8008dc0: d110 bne.n 8008de4 + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8009bd6: 4b3d ldr r3, [pc, #244] ; (8009ccc ) + 8009bd8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8009bdc: 4a3b ldr r2, [pc, #236] ; (8009ccc ) + 8009bde: f023 0301 bic.w r3, r3, #1 + 8009be2: f8c2 3094 str.w r3, [r2, #148] ; 0x94 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009be6: f7fb fb33 bl 8005250 + 8009bea: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + 8009bec: e008 b.n 8009c00 { - return HAL_TIMEOUT; - 8008dc2: 2303 movs r3, #3 - 8008dc4: e00f b.n 8008de6 + if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8009bee: f7fb fb2f bl 8005250 + 8009bf2: 4602 mov r2, r0 + 8009bf4: 693b ldr r3, [r7, #16] + 8009bf6: 1ad3 subs r3, r2, r3 + 8009bf8: 2b02 cmp r3, #2 + 8009bfa: d901 bls.n 8009c00 + { + return HAL_TIMEOUT; + 8009bfc: 2303 movs r3, #3 + 8009bfe: e1ef b.n 8009fe0 + while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + 8009c00: 4b32 ldr r3, [pc, #200] ; (8009ccc ) + 8009c02: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8009c06: f003 0302 and.w r3, r3, #2 + 8009c0a: 2b00 cmp r3, #0 + 8009c0c: d1ef bne.n 8009bee + } } } } - else + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8009c0e: 687b ldr r3, [r7, #4] + 8009c10: 681b ldr r3, [r3, #0] + 8009c12: f003 0304 and.w r3, r3, #4 + 8009c16: 2b00 cmp r3, #0 + 8009c18: f000 80a6 beq.w 8009d68 { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) - 8008dc6: 4b0b ldr r3, [pc, #44] ; (8008df4 ) - 8008dc8: 681b ldr r3, [r3, #0] - 8008dca: f403 63c0 and.w r3, r3, #1536 ; 0x600 - 8008dce: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 8008dd2: d007 beq.n 8008de4 + FlagStatus pwrclkchanged = RESET; + 8009c1c: 2300 movs r3, #0 + 8009c1e: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) + 8009c20: 4b2a ldr r3, [pc, #168] ; (8009ccc ) + 8009c22: 6d9b ldr r3, [r3, #88] ; 0x58 + 8009c24: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8009c28: 2b00 cmp r3, #0 + 8009c2a: d10d bne.n 8009c48 { - /* Set Range 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - 8008dd4: 4b07 ldr r3, [pc, #28] ; (8008df4 ) - 8008dd6: 681b ldr r3, [r3, #0] - 8008dd8: f423 63c0 bic.w r3, r3, #1536 ; 0x600 - 8008ddc: 4a05 ldr r2, [pc, #20] ; (8008df4 ) - 8008dde: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 8008de2: 6013 str r3, [r2, #0] - /* No need to wait for VOSF to be cleared for this transition */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8009c2c: 4b27 ldr r3, [pc, #156] ; (8009ccc ) + 8009c2e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8009c30: 4a26 ldr r2, [pc, #152] ; (8009ccc ) + 8009c32: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8009c36: 6593 str r3, [r2, #88] ; 0x58 + 8009c38: 4b24 ldr r3, [pc, #144] ; (8009ccc ) + 8009c3a: 6d9b ldr r3, [r3, #88] ; 0x58 + 8009c3c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8009c40: 60bb str r3, [r7, #8] + 8009c42: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8009c44: 2301 movs r3, #1 + 8009c46: 77fb strb r3, [r7, #31] } - } -#endif - - return HAL_OK; - 8008de4: 2300 movs r3, #0 -} - 8008de6: 4618 mov r0, r3 - 8008de8: 3714 adds r7, #20 - 8008dea: 46bd mov sp, r7 - 8008dec: f85d 7b04 ldr.w r7, [sp], #4 - 8008df0: 4770 bx lr - 8008df2: bf00 nop - 8008df4: 40007000 .word 0x40007000 - 8008df8: 20000020 .word 0x20000020 - 8008dfc: 431bde83 .word 0x431bde83 - -08008e00 : - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. - * @retval None - */ -void HAL_PWREx_EnableVddUSB(void) -{ - 8008e00: b480 push {r7} - 8008e02: af00 add r7, sp, #0 - SET_BIT(PWR->CR2, PWR_CR2_USV); - 8008e04: 4b05 ldr r3, [pc, #20] ; (8008e1c ) - 8008e06: 685b ldr r3, [r3, #4] - 8008e08: 4a04 ldr r2, [pc, #16] ; (8008e1c ) - 8008e0a: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 8008e0e: 6053 str r3, [r2, #4] -} - 8008e10: bf00 nop - 8008e12: 46bd mov sp, r7 - 8008e14: f85d 7b04 ldr.w r7, [sp], #4 - 8008e18: 4770 bx lr - 8008e1a: bf00 nop - 8008e1c: 40007000 .word 0x40007000 - -08008e20 : - * @note If HSE failed to start, HSE should be disabled before recalling - HAL_RCC_OscConfig(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - 8008e20: b580 push {r7, lr} - 8008e22: b088 sub sp, #32 - 8008e24: af00 add r7, sp, #0 - 8008e26: 6078 str r0, [r7, #4] - uint32_t tickstart; - HAL_StatusTypeDef status; - uint32_t sysclk_source, pll_config; - - /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) - 8008e28: 687b ldr r3, [r7, #4] - 8008e2a: 2b00 cmp r3, #0 - 8008e2c: d102 bne.n 8008e34 - { - return HAL_ERROR; - 8008e2e: 2301 movs r3, #1 - 8008e30: f000 bc02 b.w 8009638 - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8008e34: 4b96 ldr r3, [pc, #600] ; (8009090 ) - 8008e36: 689b ldr r3, [r3, #8] - 8008e38: f003 030c and.w r3, r3, #12 - 8008e3c: 61bb str r3, [r7, #24] - pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8008e3e: 4b94 ldr r3, [pc, #592] ; (8009090 ) - 8008e40: 68db ldr r3, [r3, #12] - 8008e42: f003 0303 and.w r3, r3, #3 - 8008e46: 617b str r3, [r7, #20] + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8009c48: 4b21 ldr r3, [pc, #132] ; (8009cd0 ) + 8009c4a: 681b ldr r3, [r3, #0] + 8009c4c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8009c50: 2b00 cmp r3, #0 + 8009c52: d118 bne.n 8009c86 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8009c54: 4b1e ldr r3, [pc, #120] ; (8009cd0 ) + 8009c56: 681b ldr r3, [r3, #0] + 8009c58: 4a1d ldr r2, [pc, #116] ; (8009cd0 ) + 8009c5a: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8009c5e: 6013 str r3, [r2, #0] - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - 8008e48: 687b ldr r3, [r7, #4] - 8008e4a: 681b ldr r3, [r3, #0] - 8008e4c: f003 0310 and.w r3, r3, #16 - 8008e50: 2b00 cmp r3, #0 - 8008e52: f000 80e4 beq.w 800901e - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8009c60: f7fb faf6 bl 8005250 + 8009c64: 6138 str r0, [r7, #16] - /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((sysclk_source == RCC_CFGR_SWS_MSI) || - 8008e56: 69bb ldr r3, [r7, #24] - 8008e58: 2b00 cmp r3, #0 - 8008e5a: d007 beq.n 8008e6c - 8008e5c: 69bb ldr r3, [r7, #24] - 8008e5e: 2b0c cmp r3, #12 - 8008e60: f040 808b bne.w 8008f7a - ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI))) - 8008e64: 697b ldr r3, [r7, #20] - 8008e66: 2b01 cmp r3, #1 - 8008e68: f040 8087 bne.w 8008f7a - { - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - 8008e6c: 4b88 ldr r3, [pc, #544] ; (8009090 ) - 8008e6e: 681b ldr r3, [r3, #0] - 8008e70: f003 0302 and.w r3, r3, #2 - 8008e74: 2b00 cmp r3, #0 - 8008e76: d005 beq.n 8008e84 - 8008e78: 687b ldr r3, [r7, #4] - 8008e7a: 699b ldr r3, [r3, #24] - 8008e7c: 2b00 cmp r3, #0 - 8008e7e: d101 bne.n 8008e84 - { - return HAL_ERROR; - 8008e80: 2301 movs r3, #1 - 8008e82: e3d9 b.n 8009638 - else + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8009c66: e008 b.n 8009c7a { - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - 8008e84: 687b ldr r3, [r7, #4] - 8008e86: 6a1a ldr r2, [r3, #32] - 8008e88: 4b81 ldr r3, [pc, #516] ; (8009090 ) - 8008e8a: 681b ldr r3, [r3, #0] - 8008e8c: f003 0308 and.w r3, r3, #8 - 8008e90: 2b00 cmp r3, #0 - 8008e92: d004 beq.n 8008e9e - 8008e94: 4b7e ldr r3, [pc, #504] ; (8009090 ) - 8008e96: 681b ldr r3, [r3, #0] - 8008e98: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8008e9c: e005 b.n 8008eaa - 8008e9e: 4b7c ldr r3, [pc, #496] ; (8009090 ) - 8008ea0: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8008ea4: 091b lsrs r3, r3, #4 - 8008ea6: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8008eaa: 4293 cmp r3, r2 - 8008eac: d223 bcs.n 8008ef6 - { - /* First increase number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 8008eae: 687b ldr r3, [r7, #4] - 8008eb0: 6a1b ldr r3, [r3, #32] - 8008eb2: 4618 mov r0, r3 - 8008eb4: f000 fd8c bl 80099d0 - 8008eb8: 4603 mov r3, r0 - 8008eba: 2b00 cmp r3, #0 - 8008ebc: d001 beq.n 8008ec2 - { - return HAL_ERROR; - 8008ebe: 2301 movs r3, #1 - 8008ec0: e3ba b.n 8009638 - } - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8008ec2: 4b73 ldr r3, [pc, #460] ; (8009090 ) - 8008ec4: 681b ldr r3, [r3, #0] - 8008ec6: 4a72 ldr r2, [pc, #456] ; (8009090 ) - 8008ec8: f043 0308 orr.w r3, r3, #8 - 8008ecc: 6013 str r3, [r2, #0] - 8008ece: 4b70 ldr r3, [pc, #448] ; (8009090 ) - 8008ed0: 681b ldr r3, [r3, #0] - 8008ed2: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8008ed6: 687b ldr r3, [r7, #4] - 8008ed8: 6a1b ldr r3, [r3, #32] - 8008eda: 496d ldr r1, [pc, #436] ; (8009090 ) - 8008edc: 4313 orrs r3, r2 - 8008ede: 600b str r3, [r1, #0] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 8008ee0: 4b6b ldr r3, [pc, #428] ; (8009090 ) - 8008ee2: 685b ldr r3, [r3, #4] - 8008ee4: f423 427f bic.w r2, r3, #65280 ; 0xff00 - 8008ee8: 687b ldr r3, [r7, #4] - 8008eea: 69db ldr r3, [r3, #28] - 8008eec: 021b lsls r3, r3, #8 - 8008eee: 4968 ldr r1, [pc, #416] ; (8009090 ) - 8008ef0: 4313 orrs r3, r2 - 8008ef2: 604b str r3, [r1, #4] - 8008ef4: e025 b.n 8008f42 - } - else + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8009c68: f7fb faf2 bl 8005250 + 8009c6c: 4602 mov r2, r0 + 8009c6e: 693b ldr r3, [r7, #16] + 8009c70: 1ad3 subs r3, r2, r3 + 8009c72: 2b02 cmp r3, #2 + 8009c74: d901 bls.n 8009c7a { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8008ef6: 4b66 ldr r3, [pc, #408] ; (8009090 ) - 8008ef8: 681b ldr r3, [r3, #0] - 8008efa: 4a65 ldr r2, [pc, #404] ; (8009090 ) - 8008efc: f043 0308 orr.w r3, r3, #8 - 8008f00: 6013 str r3, [r2, #0] - 8008f02: 4b63 ldr r3, [pc, #396] ; (8009090 ) - 8008f04: 681b ldr r3, [r3, #0] - 8008f06: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8008f0a: 687b ldr r3, [r7, #4] - 8008f0c: 6a1b ldr r3, [r3, #32] - 8008f0e: 4960 ldr r1, [pc, #384] ; (8009090 ) - 8008f10: 4313 orrs r3, r2 - 8008f12: 600b str r3, [r1, #0] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 8008f14: 4b5e ldr r3, [pc, #376] ; (8009090 ) - 8008f16: 685b ldr r3, [r3, #4] - 8008f18: f423 427f bic.w r2, r3, #65280 ; 0xff00 - 8008f1c: 687b ldr r3, [r7, #4] - 8008f1e: 69db ldr r3, [r3, #28] - 8008f20: 021b lsls r3, r3, #8 - 8008f22: 495b ldr r1, [pc, #364] ; (8009090 ) - 8008f24: 4313 orrs r3, r2 - 8008f26: 604b str r3, [r1, #4] - - /* Decrease number of wait states update if necessary */ - /* Only possible when MSI is the System clock source */ - if(sysclk_source == RCC_CFGR_SWS_MSI) - 8008f28: 69bb ldr r3, [r7, #24] - 8008f2a: 2b00 cmp r3, #0 - 8008f2c: d109 bne.n 8008f42 - { - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 8008f2e: 687b ldr r3, [r7, #4] - 8008f30: 6a1b ldr r3, [r3, #32] - 8008f32: 4618 mov r0, r3 - 8008f34: f000 fd4c bl 80099d0 - 8008f38: 4603 mov r3, r0 - 8008f3a: 2b00 cmp r3, #0 - 8008f3c: d001 beq.n 8008f42 - { - return HAL_ERROR; - 8008f3e: 2301 movs r3, #1 - 8008f40: e37a b.n 8009638 - } - } - } + return HAL_TIMEOUT; + 8009c76: 2303 movs r3, #3 + 8009c78: e1b2 b.n 8009fe0 + while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8009c7a: 4b15 ldr r3, [pc, #84] ; (8009cd0 ) + 8009c7c: 681b ldr r3, [r3, #0] + 8009c7e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8009c82: 2b00 cmp r3, #0 + 8009c84: d0f0 beq.n 8009c68 + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + } +#else + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8009c86: 687b ldr r3, [r7, #4] + 8009c88: 689b ldr r3, [r3, #8] + 8009c8a: 2b01 cmp r3, #1 + 8009c8c: d108 bne.n 8009ca0 + 8009c8e: 4b0f ldr r3, [pc, #60] ; (8009ccc ) + 8009c90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009c94: 4a0d ldr r2, [pc, #52] ; (8009ccc ) + 8009c96: f043 0301 orr.w r3, r3, #1 + 8009c9a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8009c9e: e029 b.n 8009cf4 + 8009ca0: 687b ldr r3, [r7, #4] + 8009ca2: 689b ldr r3, [r3, #8] + 8009ca4: 2b05 cmp r3, #5 + 8009ca6: d115 bne.n 8009cd4 + 8009ca8: 4b08 ldr r3, [pc, #32] ; (8009ccc ) + 8009caa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009cae: 4a07 ldr r2, [pc, #28] ; (8009ccc ) + 8009cb0: f043 0304 orr.w r3, r3, #4 + 8009cb4: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8009cb8: 4b04 ldr r3, [pc, #16] ; (8009ccc ) + 8009cba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009cbe: 4a03 ldr r2, [pc, #12] ; (8009ccc ) + 8009cc0: f043 0301 orr.w r3, r3, #1 + 8009cc4: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8009cc8: e014 b.n 8009cf4 + 8009cca: bf00 nop + 8009ccc: 40021000 .word 0x40021000 + 8009cd0: 40007000 .word 0x40007000 + 8009cd4: 4b9a ldr r3, [pc, #616] ; (8009f40 ) + 8009cd6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009cda: 4a99 ldr r2, [pc, #612] ; (8009f40 ) + 8009cdc: f023 0301 bic.w r3, r3, #1 + 8009ce0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8009ce4: 4b96 ldr r3, [pc, #600] ; (8009f40 ) + 8009ce6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009cea: 4a95 ldr r2, [pc, #596] ; (8009f40 ) + 8009cec: f023 0304 bic.w r3, r3, #4 + 8009cf0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +#endif /* RCC_BDCR_LSESYSDIS */ - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); - 8008f42: f000 fc81 bl 8009848 - 8008f46: 4602 mov r2, r0 - 8008f48: 4b51 ldr r3, [pc, #324] ; (8009090 ) - 8008f4a: 689b ldr r3, [r3, #8] - 8008f4c: 091b lsrs r3, r3, #4 - 8008f4e: f003 030f and.w r3, r3, #15 - 8008f52: 4950 ldr r1, [pc, #320] ; (8009094 ) - 8008f54: 5ccb ldrb r3, [r1, r3] - 8008f56: f003 031f and.w r3, r3, #31 - 8008f5a: fa22 f303 lsr.w r3, r2, r3 - 8008f5e: 4a4e ldr r2, [pc, #312] ; (8009098 ) - 8008f60: 6013 str r3, [r2, #0] + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8009cf4: 687b ldr r3, [r7, #4] + 8009cf6: 689b ldr r3, [r3, #8] + 8009cf8: 2b00 cmp r3, #0 + 8009cfa: d016 beq.n 8009d2a + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009cfc: f7fb faa8 bl 8005250 + 8009d00: 6138 str r0, [r7, #16] - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - 8008f62: 4b4e ldr r3, [pc, #312] ; (800909c ) - 8008f64: 681b ldr r3, [r3, #0] - 8008f66: 4618 mov r0, r3 - 8008f68: f7fb fad8 bl 800451c - 8008f6c: 4603 mov r3, r0 - 8008f6e: 73fb strb r3, [r7, #15] - if(status != HAL_OK) - 8008f70: 7bfb ldrb r3, [r7, #15] - 8008f72: 2b00 cmp r3, #0 - 8008f74: d052 beq.n 800901c + /* Wait till LSE is ready */ + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 8009d02: e00a b.n 8009d1a + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8009d04: f7fb faa4 bl 8005250 + 8009d08: 4602 mov r2, r0 + 8009d0a: 693b ldr r3, [r7, #16] + 8009d0c: 1ad3 subs r3, r2, r3 + 8009d0e: f241 3288 movw r2, #5000 ; 0x1388 + 8009d12: 4293 cmp r3, r2 + 8009d14: d901 bls.n 8009d1a { - return status; - 8008f76: 7bfb ldrb r3, [r7, #15] - 8008f78: e35e b.n 8009638 + return HAL_TIMEOUT; + 8009d16: 2303 movs r3, #3 + 8009d18: e162 b.n 8009fe0 + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 8009d1a: 4b89 ldr r3, [pc, #548] ; (8009f40 ) + 8009d1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009d20: f003 0302 and.w r3, r3, #2 + 8009d24: 2b00 cmp r3, #0 + 8009d26: d0ed beq.n 8009d04 + 8009d28: e015 b.n 8009d56 } } else { - /* Check the MSI State */ - if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - 8008f7a: 687b ldr r3, [r7, #4] - 8008f7c: 699b ldr r3, [r3, #24] - 8008f7e: 2b00 cmp r3, #0 - 8008f80: d032 beq.n 8008fe8 - { - /* Enable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - 8008f82: 4b43 ldr r3, [pc, #268] ; (8009090 ) - 8008f84: 681b ldr r3, [r3, #0] - 8008f86: 4a42 ldr r2, [pc, #264] ; (8009090 ) - 8008f88: f043 0301 orr.w r3, r3, #1 - 8008f8c: 6013 str r3, [r2, #0] - - /* Get timeout */ - tickstart = HAL_GetTick(); - 8008f8e: f7fb fb15 bl 80045bc - 8008f92: 6138 str r0, [r7, #16] - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) - 8008f94: e008 b.n 8008fa8 - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8008f96: f7fb fb11 bl 80045bc - 8008f9a: 4602 mov r2, r0 - 8008f9c: 693b ldr r3, [r7, #16] - 8008f9e: 1ad3 subs r3, r2, r3 - 8008fa0: 2b02 cmp r3, #2 - 8008fa2: d901 bls.n 8008fa8 - { - return HAL_TIMEOUT; - 8008fa4: 2303 movs r3, #3 - 8008fa6: e347 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) - 8008fa8: 4b39 ldr r3, [pc, #228] ; (8009090 ) - 8008faa: 681b ldr r3, [r3, #0] - 8008fac: f003 0302 and.w r3, r3, #2 - 8008fb0: 2b00 cmp r3, #0 - 8008fb2: d0f0 beq.n 8008f96 - } - } - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8008fb4: 4b36 ldr r3, [pc, #216] ; (8009090 ) - 8008fb6: 681b ldr r3, [r3, #0] - 8008fb8: 4a35 ldr r2, [pc, #212] ; (8009090 ) - 8008fba: f043 0308 orr.w r3, r3, #8 - 8008fbe: 6013 str r3, [r2, #0] - 8008fc0: 4b33 ldr r3, [pc, #204] ; (8009090 ) - 8008fc2: 681b ldr r3, [r3, #0] - 8008fc4: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8008fc8: 687b ldr r3, [r7, #4] - 8008fca: 6a1b ldr r3, [r3, #32] - 8008fcc: 4930 ldr r1, [pc, #192] ; (8009090 ) - 8008fce: 4313 orrs r3, r2 - 8008fd0: 600b str r3, [r1, #0] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 8008fd2: 4b2f ldr r3, [pc, #188] ; (8009090 ) - 8008fd4: 685b ldr r3, [r3, #4] - 8008fd6: f423 427f bic.w r2, r3, #65280 ; 0xff00 - 8008fda: 687b ldr r3, [r7, #4] - 8008fdc: 69db ldr r3, [r3, #28] - 8008fde: 021b lsls r3, r3, #8 - 8008fe0: 492b ldr r1, [pc, #172] ; (8009090 ) - 8008fe2: 4313 orrs r3, r2 - 8008fe4: 604b str r3, [r1, #4] - 8008fe6: e01a b.n 800901e + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009d2a: f7fb fa91 bl 8005250 + 8009d2e: 6138 str r0, [r7, #16] - } - else + /* Wait till LSE is disabled */ + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + 8009d30: e00a b.n 8009d48 { - /* Disable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - 8008fe8: 4b29 ldr r3, [pc, #164] ; (8009090 ) - 8008fea: 681b ldr r3, [r3, #0] - 8008fec: 4a28 ldr r2, [pc, #160] ; (8009090 ) - 8008fee: f023 0301 bic.w r3, r3, #1 - 8008ff2: 6013 str r3, [r2, #0] - - /* Get timeout */ - tickstart = HAL_GetTick(); - 8008ff4: f7fb fae2 bl 80045bc - 8008ff8: 6138 str r0, [r7, #16] - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) - 8008ffa: e008 b.n 800900e + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8009d32: f7fb fa8d bl 8005250 + 8009d36: 4602 mov r2, r0 + 8009d38: 693b ldr r3, [r7, #16] + 8009d3a: 1ad3 subs r3, r2, r3 + 8009d3c: f241 3288 movw r2, #5000 ; 0x1388 + 8009d40: 4293 cmp r3, r2 + 8009d42: d901 bls.n 8009d48 { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8008ffc: f7fb fade bl 80045bc - 8009000: 4602 mov r2, r0 - 8009002: 693b ldr r3, [r7, #16] - 8009004: 1ad3 subs r3, r2, r3 - 8009006: 2b02 cmp r3, #2 - 8009008: d901 bls.n 800900e - { - return HAL_TIMEOUT; - 800900a: 2303 movs r3, #3 - 800900c: e314 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) - 800900e: 4b20 ldr r3, [pc, #128] ; (8009090 ) - 8009010: 681b ldr r3, [r3, #0] - 8009012: f003 0302 and.w r3, r3, #2 - 8009016: 2b00 cmp r3, #0 - 8009018: d1f0 bne.n 8008ffc - 800901a: e000 b.n 800901e - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - 800901c: bf00 nop - } - } + return HAL_TIMEOUT; + 8009d44: 2303 movs r3, #3 + 8009d46: e14b b.n 8009fe0 + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + 8009d48: 4b7d ldr r3, [pc, #500] ; (8009f40 ) + 8009d4a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009d4e: f003 0302 and.w r3, r3, #2 + 8009d52: 2b00 cmp r3, #0 + 8009d54: d1ed bne.n 8009d32 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); +#endif /* RCC_BDCR_LSESYSDIS */ + } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 8009d56: 7ffb ldrb r3, [r7, #31] + 8009d58: 2b01 cmp r3, #1 + 8009d5a: d105 bne.n 8009d68 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8009d5c: 4b78 ldr r3, [pc, #480] ; (8009f40 ) + 8009d5e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8009d60: 4a77 ldr r2, [pc, #476] ; (8009f40 ) + 8009d62: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8009d66: 6593 str r3, [r2, #88] ; 0x58 } } - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 800901e: 687b ldr r3, [r7, #4] - 8009020: 681b ldr r3, [r3, #0] - 8009022: f003 0301 and.w r3, r3, #1 - 8009026: 2b00 cmp r3, #0 - 8009028: d073 beq.n 8009112 +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 8009d68: 687b ldr r3, [r7, #4] + 8009d6a: 681b ldr r3, [r3, #0] + 8009d6c: f003 0320 and.w r3, r3, #32 + 8009d70: 2b00 cmp r3, #0 + 8009d72: d03c beq.n 8009dee { /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((sysclk_source == RCC_CFGR_SWS_HSE) || - 800902a: 69bb ldr r3, [r7, #24] - 800902c: 2b08 cmp r3, #8 - 800902e: d005 beq.n 800903c - 8009030: 69bb ldr r3, [r7, #24] - 8009032: 2b0c cmp r3, #12 - 8009034: d10e bne.n 8009054 - ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE))) - 8009036: 697b ldr r3, [r7, #20] - 8009038: 2b03 cmp r3, #3 - 800903a: d10b bne.n 8009054 + /* Check the LSI State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 8009d74: 687b ldr r3, [r7, #4] + 8009d76: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009d78: 2b00 cmp r3, #0 + 8009d7a: d01c beq.n 8009db6 { - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 800903c: 4b14 ldr r3, [pc, #80] ; (8009090 ) - 800903e: 681b ldr r3, [r3, #0] - 8009040: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8009044: 2b00 cmp r3, #0 - 8009046: d063 beq.n 8009110 - 8009048: 687b ldr r3, [r7, #4] - 800904a: 685b ldr r3, [r3, #4] - 800904c: 2b00 cmp r3, #0 - 800904e: d15f bne.n 8009110 + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 8009d7c: 4b70 ldr r3, [pc, #448] ; (8009f40 ) + 8009d7e: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 + 8009d82: 4a6f ldr r2, [pc, #444] ; (8009f40 ) + 8009d84: f043 0301 orr.w r3, r3, #1 + 8009d88: f8c2 3098 str.w r3, [r2, #152] ; 0x98 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009d8c: f7fb fa60 bl 8005250 + 8009d90: 6138 str r0, [r7, #16] + + /* Wait till HSI48 is ready */ + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) + 8009d92: e008 b.n 8009da6 { - return HAL_ERROR; - 8009050: 2301 movs r3, #1 - 8009052: e2f1 b.n 8009638 + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8009d94: f7fb fa5c bl 8005250 + 8009d98: 4602 mov r2, r0 + 8009d9a: 693b ldr r3, [r7, #16] + 8009d9c: 1ad3 subs r3, r2, r3 + 8009d9e: 2b02 cmp r3, #2 + 8009da0: d901 bls.n 8009da6 + { + return HAL_TIMEOUT; + 8009da2: 2303 movs r3, #3 + 8009da4: e11c b.n 8009fe0 + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) + 8009da6: 4b66 ldr r3, [pc, #408] ; (8009f40 ) + 8009da8: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 + 8009dac: f003 0302 and.w r3, r3, #2 + 8009db0: 2b00 cmp r3, #0 + 8009db2: d0ef beq.n 8009d94 + 8009db4: e01b b.n 8009dee } } else { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8009054: 687b ldr r3, [r7, #4] - 8009056: 685b ldr r3, [r3, #4] - 8009058: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800905c: d106 bne.n 800906c - 800905e: 4b0c ldr r3, [pc, #48] ; (8009090 ) - 8009060: 681b ldr r3, [r3, #0] - 8009062: 4a0b ldr r2, [pc, #44] ; (8009090 ) - 8009064: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8009068: 6013 str r3, [r2, #0] - 800906a: e025 b.n 80090b8 - 800906c: 687b ldr r3, [r7, #4] - 800906e: 685b ldr r3, [r3, #4] - 8009070: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 - 8009074: d114 bne.n 80090a0 - 8009076: 4b06 ldr r3, [pc, #24] ; (8009090 ) - 8009078: 681b ldr r3, [r3, #0] - 800907a: 4a05 ldr r2, [pc, #20] ; (8009090 ) - 800907c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 8009080: 6013 str r3, [r2, #0] - 8009082: 4b03 ldr r3, [pc, #12] ; (8009090 ) - 8009084: 681b ldr r3, [r3, #0] - 8009086: 4a02 ldr r2, [pc, #8] ; (8009090 ) - 8009088: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 800908c: 6013 str r3, [r2, #0] - 800908e: e013 b.n 80090b8 - 8009090: 40021000 .word 0x40021000 - 8009094: 080186cc .word 0x080186cc - 8009098: 20000020 .word 0x20000020 - 800909c: 20000024 .word 0x20000024 - 80090a0: 4ba0 ldr r3, [pc, #640] ; (8009324 ) - 80090a2: 681b ldr r3, [r3, #0] - 80090a4: 4a9f ldr r2, [pc, #636] ; (8009324 ) - 80090a6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 80090aa: 6013 str r3, [r2, #0] - 80090ac: 4b9d ldr r3, [pc, #628] ; (8009324 ) - 80090ae: 681b ldr r3, [r3, #0] - 80090b0: 4a9c ldr r2, [pc, #624] ; (8009324 ) - 80090b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 80090b6: 6013 str r3, [r2, #0] + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 8009db6: 4b62 ldr r3, [pc, #392] ; (8009f40 ) + 8009db8: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 + 8009dbc: 4a60 ldr r2, [pc, #384] ; (8009f40 ) + 8009dbe: f023 0301 bic.w r3, r3, #1 + 8009dc2: f8c2 3098 str.w r3, [r2, #152] ; 0x98 - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 80090b8: 687b ldr r3, [r7, #4] - 80090ba: 685b ldr r3, [r3, #4] - 80090bc: 2b00 cmp r3, #0 - 80090be: d013 beq.n 80090e8 + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009dc6: f7fb fa43 bl 8005250 + 8009dca: 6138 str r0, [r7, #16] + + /* Wait till HSI48 is disabled */ + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) + 8009dcc: e008 b.n 8009de0 { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80090c0: f7fb fa7c bl 80045bc - 80090c4: 6138 str r0, [r7, #16] + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8009dce: f7fb fa3f bl 8005250 + 8009dd2: 4602 mov r2, r0 + 8009dd4: 693b ldr r3, [r7, #16] + 8009dd6: 1ad3 subs r3, r2, r3 + 8009dd8: 2b02 cmp r3, #2 + 8009dda: d901 bls.n 8009de0 + { + return HAL_TIMEOUT; + 8009ddc: 2303 movs r3, #3 + 8009dde: e0ff b.n 8009fe0 + while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) + 8009de0: 4b57 ldr r3, [pc, #348] ; (8009f40 ) + 8009de2: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 + 8009de6: f003 0302 and.w r3, r3, #2 + 8009dea: 2b00 cmp r3, #0 + 8009dec: d1ef bne.n 8009dce +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - /* Wait till HSE is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 80090c6: e008 b.n 80090da + if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 8009dee: 687b ldr r3, [r7, #4] + 8009df0: 6a9b ldr r3, [r3, #40] ; 0x28 + 8009df2: 2b00 cmp r3, #0 + 8009df4: f000 80f3 beq.w 8009fde + { + /* PLL On ? */ + if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 8009df8: 687b ldr r3, [r7, #4] + 8009dfa: 6a9b ldr r3, [r3, #40] ; 0x28 + 8009dfc: 2b02 cmp r3, #2 + 8009dfe: f040 80c9 bne.w 8009f94 +#endif /* RCC_PLLP_SUPPORT */ + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Do nothing if PLL configuration is the unchanged */ + pll_config = RCC->PLLCFGR; + 8009e02: 4b4f ldr r3, [pc, #316] ; (8009f40 ) + 8009e04: 68db ldr r3, [r3, #12] + 8009e06: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8009e08: 697b ldr r3, [r7, #20] + 8009e0a: f003 0203 and.w r2, r3, #3 + 8009e0e: 687b ldr r3, [r7, #4] + 8009e10: 6adb ldr r3, [r3, #44] ; 0x2c + 8009e12: 429a cmp r2, r3 + 8009e14: d12c bne.n 8009e70 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || + 8009e16: 697b ldr r3, [r7, #20] + 8009e18: f003 0270 and.w r2, r3, #112 ; 0x70 + 8009e1c: 687b ldr r3, [r7, #4] + 8009e1e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8009e20: 3b01 subs r3, #1 + 8009e22: 011b lsls r3, r3, #4 + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8009e24: 429a cmp r2, r3 + 8009e26: d123 bne.n 8009e70 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 8009e28: 697b ldr r3, [r7, #20] + 8009e2a: f403 42fe and.w r2, r3, #32512 ; 0x7f00 + 8009e2e: 687b ldr r3, [r7, #4] + 8009e30: 6b5b ldr r3, [r3, #52] ; 0x34 + 8009e32: 021b lsls r3, r3, #8 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || + 8009e34: 429a cmp r2, r3 + 8009e36: d11b bne.n 8009e70 +#if defined(RCC_PLLP_SUPPORT) +#if defined(RCC_PLLP_DIV_2_31_SUPPORT) + (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || + 8009e38: 697b ldr r3, [r7, #20] + 8009e3a: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000 + 8009e3e: 687b ldr r3, [r7, #4] + 8009e40: 6b9b ldr r3, [r3, #56] ; 0x38 + 8009e42: 06db lsls r3, r3, #27 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 8009e44: 429a cmp r2, r3 + 8009e46: d113 bne.n 8009e70 +#else + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) || +#endif +#endif + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + 8009e48: 697b ldr r3, [r7, #20] + 8009e4a: f403 02c0 and.w r2, r3, #6291456 ; 0x600000 + 8009e4e: 687b ldr r3, [r7, #4] + 8009e50: 6bdb ldr r3, [r3, #60] ; 0x3c + 8009e52: 085b lsrs r3, r3, #1 + 8009e54: 3b01 subs r3, #1 + 8009e56: 055b lsls r3, r3, #21 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || + 8009e58: 429a cmp r2, r3 + 8009e5a: d109 bne.n 8009e70 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) + 8009e5c: 697b ldr r3, [r7, #20] + 8009e5e: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000 + 8009e62: 687b ldr r3, [r7, #4] + 8009e64: 6c1b ldr r3, [r3, #64] ; 0x40 + 8009e66: 085b lsrs r3, r3, #1 + 8009e68: 3b01 subs r3, #1 + 8009e6a: 065b lsls r3, r3, #25 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + 8009e6c: 429a cmp r2, r3 + 8009e6e: d06b beq.n 8009f48 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_CFGR_SWS_PLL) + 8009e70: 69bb ldr r3, [r7, #24] + 8009e72: 2b0c cmp r3, #12 + 8009e74: d062 beq.n 8009f3c { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 80090c8: f7fb fa78 bl 80045bc - 80090cc: 4602 mov r2, r0 - 80090ce: 693b ldr r3, [r7, #16] - 80090d0: 1ad3 subs r3, r2, r3 - 80090d2: 2b64 cmp r3, #100 ; 0x64 - 80090d4: d901 bls.n 80090da +#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT) + /* Check if main PLL can be updated */ + /* Not possible if the source is shared by other enabled PLLSAIx */ + if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) + 8009e76: 4b32 ldr r3, [pc, #200] ; (8009f40 ) + 8009e78: 681b ldr r3, [r3, #0] + 8009e7a: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8009e7e: 2b00 cmp r3, #0 + 8009e80: d001 beq.n 8009e86 +#if defined(RCC_PLLSAI2_SUPPORT) + || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U) +#endif + ) { - return HAL_TIMEOUT; - 80090d6: 2303 movs r3, #3 - 80090d8: e2ae b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 80090da: 4b92 ldr r3, [pc, #584] ; (8009324 ) - 80090dc: 681b ldr r3, [r3, #0] - 80090de: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80090e2: 2b00 cmp r3, #0 - 80090e4: d0f0 beq.n 80090c8 - 80090e6: e014 b.n 8009112 + return HAL_ERROR; + 8009e82: 2301 movs r3, #1 + 8009e84: e0ac b.n 8009fe0 + } + else +#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */ + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8009e86: 4b2e ldr r3, [pc, #184] ; (8009f40 ) + 8009e88: 681b ldr r3, [r3, #0] + 8009e8a: 4a2d ldr r2, [pc, #180] ; (8009f40 ) + 8009e8c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8009e90: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009e92: f7fb f9dd bl 8005250 + 8009e96: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8009e98: e008 b.n 8009eac + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8009e9a: f7fb f9d9 bl 8005250 + 8009e9e: 4602 mov r2, r0 + 8009ea0: 693b ldr r3, [r7, #16] + 8009ea2: 1ad3 subs r3, r2, r3 + 8009ea4: 2b02 cmp r3, #2 + 8009ea6: d901 bls.n 8009eac + { + return HAL_TIMEOUT; + 8009ea8: 2303 movs r3, #3 + 8009eaa: e099 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8009eac: 4b24 ldr r3, [pc, #144] ; (8009f40 ) + 8009eae: 681b ldr r3, [r3, #0] + 8009eb0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8009eb4: 2b00 cmp r3, #0 + 8009eb6: d1f0 bne.n 8009e9a + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined(RCC_PLLP_SUPPORT) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8009eb8: 4b21 ldr r3, [pc, #132] ; (8009f40 ) + 8009eba: 68da ldr r2, [r3, #12] + 8009ebc: 4b21 ldr r3, [pc, #132] ; (8009f44 ) + 8009ebe: 4013 ands r3, r2 + 8009ec0: 687a ldr r2, [r7, #4] + 8009ec2: 6ad1 ldr r1, [r2, #44] ; 0x2c + 8009ec4: 687a ldr r2, [r7, #4] + 8009ec6: 6b12 ldr r2, [r2, #48] ; 0x30 + 8009ec8: 3a01 subs r2, #1 + 8009eca: 0112 lsls r2, r2, #4 + 8009ecc: 4311 orrs r1, r2 + 8009ece: 687a ldr r2, [r7, #4] + 8009ed0: 6b52 ldr r2, [r2, #52] ; 0x34 + 8009ed2: 0212 lsls r2, r2, #8 + 8009ed4: 4311 orrs r1, r2 + 8009ed6: 687a ldr r2, [r7, #4] + 8009ed8: 6bd2 ldr r2, [r2, #60] ; 0x3c + 8009eda: 0852 lsrs r2, r2, #1 + 8009edc: 3a01 subs r2, #1 + 8009ede: 0552 lsls r2, r2, #21 + 8009ee0: 4311 orrs r1, r2 + 8009ee2: 687a ldr r2, [r7, #4] + 8009ee4: 6c12 ldr r2, [r2, #64] ; 0x40 + 8009ee6: 0852 lsrs r2, r2, #1 + 8009ee8: 3a01 subs r2, #1 + 8009eea: 0652 lsls r2, r2, #25 + 8009eec: 4311 orrs r1, r2 + 8009eee: 687a ldr r2, [r7, #4] + 8009ef0: 6b92 ldr r2, [r2, #56] ; 0x38 + 8009ef2: 06d2 lsls r2, r2, #27 + 8009ef4: 430a orrs r2, r1 + 8009ef6: 4912 ldr r1, [pc, #72] ; (8009f40 ) + 8009ef8: 4313 orrs r3, r2 + 8009efa: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8009efc: 4b10 ldr r3, [pc, #64] ; (8009f40 ) + 8009efe: 681b ldr r3, [r3, #0] + 8009f00: 4a0f ldr r2, [pc, #60] ; (8009f40 ) + 8009f02: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8009f06: 6013 str r3, [r2, #0] + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8009f08: 4b0d ldr r3, [pc, #52] ; (8009f40 ) + 8009f0a: 68db ldr r3, [r3, #12] + 8009f0c: 4a0c ldr r2, [pc, #48] ; (8009f40 ) + 8009f0e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8009f12: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009f14: f7fb f99c bl 8005250 + 8009f18: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8009f1a: e008 b.n 8009f2e + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8009f1c: f7fb f998 bl 8005250 + 8009f20: 4602 mov r2, r0 + 8009f22: 693b ldr r3, [r7, #16] + 8009f24: 1ad3 subs r3, r2, r3 + 8009f26: 2b02 cmp r3, #2 + 8009f28: d901 bls.n 8009f2e + { + return HAL_TIMEOUT; + 8009f2a: 2303 movs r3, #3 + 8009f2c: e058 b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8009f2e: 4b04 ldr r3, [pc, #16] ; (8009f40 ) + 8009f30: 681b ldr r3, [r3, #0] + 8009f32: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8009f36: 2b00 cmp r3, #0 + 8009f38: d0f0 beq.n 8009f1c + if(sysclk_source != RCC_CFGR_SWS_PLL) + 8009f3a: e050 b.n 8009fde + } } + else + { + /* PLL is already used as System core clock */ + return HAL_ERROR; + 8009f3c: 2301 movs r3, #1 + 8009f3e: e04f b.n 8009fe0 + 8009f40: 40021000 .word 0x40021000 + 8009f44: 019d808c .word 0x019d808c } else { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80090e8: f7fb fa68 bl 80045bc - 80090ec: 6138 str r0, [r7, #16] - - /* Wait till HSE is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 80090ee: e008 b.n 8009102 + /* PLL configuration is unchanged */ + /* Re-enable PLL if it was disabled (ie. low power mode) */ + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8009f48: 4b27 ldr r3, [pc, #156] ; (8009fe8 ) + 8009f4a: 681b ldr r3, [r3, #0] + 8009f4c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8009f50: 2b00 cmp r3, #0 + 8009f52: d144 bne.n 8009fde { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 80090f0: f7fb fa64 bl 80045bc - 80090f4: 4602 mov r2, r0 - 80090f6: 693b ldr r3, [r7, #16] - 80090f8: 1ad3 subs r3, r2, r3 - 80090fa: 2b64 cmp r3, #100 ; 0x64 - 80090fc: d901 bls.n 8009102 - { - return HAL_TIMEOUT; - 80090fe: 2303 movs r3, #3 - 8009100: e29a b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 8009102: 4b88 ldr r3, [pc, #544] ; (8009324 ) - 8009104: 681b ldr r3, [r3, #0] - 8009106: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800910a: 2b00 cmp r3, #0 - 800910c: d1f0 bne.n 80090f0 - 800910e: e000 b.n 8009112 - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8009110: bf00 nop - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8009112: 687b ldr r3, [r7, #4] - 8009114: 681b ldr r3, [r3, #0] - 8009116: f003 0302 and.w r3, r3, #2 - 800911a: 2b00 cmp r3, #0 - 800911c: d060 beq.n 80091e0 - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8009f54: 4b24 ldr r3, [pc, #144] ; (8009fe8 ) + 8009f56: 681b ldr r3, [r3, #0] + 8009f58: 4a23 ldr r2, [pc, #140] ; (8009fe8 ) + 8009f5a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8009f5e: 6013 str r3, [r2, #0] - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((sysclk_source == RCC_CFGR_SWS_HSI) || - 800911e: 69bb ldr r3, [r7, #24] - 8009120: 2b04 cmp r3, #4 - 8009122: d005 beq.n 8009130 - 8009124: 69bb ldr r3, [r7, #24] - 8009126: 2b0c cmp r3, #12 - 8009128: d119 bne.n 800915e - ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI))) - 800912a: 697b ldr r3, [r7, #20] - 800912c: 2b02 cmp r3, #2 - 800912e: d116 bne.n 800915e - { - /* When HSI is used as system clock it will not be disabled */ - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - 8009130: 4b7c ldr r3, [pc, #496] ; (8009324 ) - 8009132: 681b ldr r3, [r3, #0] - 8009134: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8009138: 2b00 cmp r3, #0 - 800913a: d005 beq.n 8009148 - 800913c: 687b ldr r3, [r7, #4] - 800913e: 68db ldr r3, [r3, #12] - 8009140: 2b00 cmp r3, #0 - 8009142: d101 bne.n 8009148 - { - return HAL_ERROR; - 8009144: 2301 movs r3, #1 - 8009146: e277 b.n 8009638 - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8009148: 4b76 ldr r3, [pc, #472] ; (8009324 ) - 800914a: 685b ldr r3, [r3, #4] - 800914c: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 - 8009150: 687b ldr r3, [r7, #4] - 8009152: 691b ldr r3, [r3, #16] - 8009154: 061b lsls r3, r3, #24 - 8009156: 4973 ldr r1, [pc, #460] ; (8009324 ) - 8009158: 4313 orrs r3, r2 - 800915a: 604b str r3, [r1, #4] - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - 800915c: e040 b.n 80091e0 + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8009f60: 4b21 ldr r3, [pc, #132] ; (8009fe8 ) + 8009f62: 68db ldr r3, [r3, #12] + 8009f64: 4a20 ldr r2, [pc, #128] ; (8009fe8 ) + 8009f66: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8009f6a: 60d3 str r3, [r2, #12] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8009f6c: f7fb f970 bl 8005250 + 8009f70: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8009f72: e008 b.n 8009f86 + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8009f74: f7fb f96c bl 8005250 + 8009f78: 4602 mov r2, r0 + 8009f7a: 693b ldr r3, [r7, #16] + 8009f7c: 1ad3 subs r3, r2, r3 + 8009f7e: 2b02 cmp r3, #2 + 8009f80: d901 bls.n 8009f86 + { + return HAL_TIMEOUT; + 8009f82: 2303 movs r3, #3 + 8009f84: e02c b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 8009f86: 4b18 ldr r3, [pc, #96] ; (8009fe8 ) + 8009f88: 681b ldr r3, [r3, #0] + 8009f8a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8009f8e: 2b00 cmp r3, #0 + 8009f90: d0f0 beq.n 8009f74 + 8009f92: e024 b.n 8009fde } } else { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 800915e: 687b ldr r3, [r7, #4] - 8009160: 68db ldr r3, [r3, #12] - 8009162: 2b00 cmp r3, #0 - 8009164: d023 beq.n 80091ae - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - 8009166: 4b6f ldr r3, [pc, #444] ; (8009324 ) - 8009168: 681b ldr r3, [r3, #0] - 800916a: 4a6e ldr r2, [pc, #440] ; (8009324 ) - 800916c: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8009170: 6013 str r3, [r2, #0] + /* Check that PLL is not used as system clock or not */ + if(sysclk_source != RCC_CFGR_SWS_PLL) + 8009f94: 69bb ldr r3, [r7, #24] + 8009f96: 2b0c cmp r3, #12 + 8009f98: d01f beq.n 8009fda + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8009f9a: 4b13 ldr r3, [pc, #76] ; (8009fe8 ) + 8009f9c: 681b ldr r3, [r3, #0] + 8009f9e: 4a12 ldr r2, [pc, #72] ; (8009fe8 ) + 8009fa0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8009fa4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8009172: f7fb fa23 bl 80045bc - 8009176: 6138 str r0, [r7, #16] + 8009fa6: f7fb f953 bl 8005250 + 8009faa: 6138 str r0, [r7, #16] - /* Wait till HSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8009178: e008 b.n 800918c + /* Wait till PLL is disabled */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8009fac: e008 b.n 8009fc0 { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 800917a: f7fb fa1f bl 80045bc - 800917e: 4602 mov r2, r0 - 8009180: 693b ldr r3, [r7, #16] - 8009182: 1ad3 subs r3, r2, r3 - 8009184: 2b02 cmp r3, #2 - 8009186: d901 bls.n 800918c + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8009fae: f7fb f94f bl 8005250 + 8009fb2: 4602 mov r2, r0 + 8009fb4: 693b ldr r3, [r7, #16] + 8009fb6: 1ad3 subs r3, r2, r3 + 8009fb8: 2b02 cmp r3, #2 + 8009fba: d901 bls.n 8009fc0 { return HAL_TIMEOUT; - 8009188: 2303 movs r3, #3 - 800918a: e255 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 800918c: 4b65 ldr r3, [pc, #404] ; (8009324 ) - 800918e: 681b ldr r3, [r3, #0] - 8009190: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8009194: 2b00 cmp r3, #0 - 8009196: d0f0 beq.n 800917a - } + 8009fbc: 2303 movs r3, #3 + 8009fbe: e00f b.n 8009fe0 + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 8009fc0: 4b09 ldr r3, [pc, #36] ; (8009fe8 ) + 8009fc2: 681b ldr r3, [r3, #0] + 8009fc4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8009fc8: 2b00 cmp r3, #0 + 8009fca: d1f0 bne.n 8009fae } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8009198: 4b62 ldr r3, [pc, #392] ; (8009324 ) - 800919a: 685b ldr r3, [r3, #4] - 800919c: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 - 80091a0: 687b ldr r3, [r7, #4] - 80091a2: 691b ldr r3, [r3, #16] - 80091a4: 061b lsls r3, r3, #24 - 80091a6: 495f ldr r1, [pc, #380] ; (8009324 ) - 80091a8: 4313 orrs r3, r2 - 80091aa: 604b str r3, [r1, #4] - 80091ac: e018 b.n 80091e0 + /* Unselect main PLL clock source and disable main PLL outputs to save power */ +#if defined(RCC_PLLSAI2_SUPPORT) + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); +#elif defined(RCC_PLLSAI1_SUPPORT) + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); + 8009fcc: 4b06 ldr r3, [pc, #24] ; (8009fe8 ) + 8009fce: 68da ldr r2, [r3, #12] + 8009fd0: 4905 ldr r1, [pc, #20] ; (8009fe8 ) + 8009fd2: 4b06 ldr r3, [pc, #24] ; (8009fec ) + 8009fd4: 4013 ands r3, r2 + 8009fd6: 60cb str r3, [r1, #12] + 8009fd8: e001 b.n 8009fde +#endif /* RCC_PLLSAI2_SUPPORT */ } else { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - 80091ae: 4b5d ldr r3, [pc, #372] ; (8009324 ) - 80091b0: 681b ldr r3, [r3, #0] - 80091b2: 4a5c ldr r2, [pc, #368] ; (8009324 ) - 80091b4: f423 7380 bic.w r3, r3, #256 ; 0x100 - 80091b8: 6013 str r3, [r2, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80091ba: f7fb f9ff bl 80045bc - 80091be: 6138 str r0, [r7, #16] - - /* Wait till HSI is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 80091c0: e008 b.n 80091d4 - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 80091c2: f7fb f9fb bl 80045bc - 80091c6: 4602 mov r2, r0 - 80091c8: 693b ldr r3, [r7, #16] - 80091ca: 1ad3 subs r3, r2, r3 - 80091cc: 2b02 cmp r3, #2 - 80091ce: d901 bls.n 80091d4 - { - return HAL_TIMEOUT; - 80091d0: 2303 movs r3, #3 - 80091d2: e231 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 80091d4: 4b53 ldr r3, [pc, #332] ; (8009324 ) - 80091d6: 681b ldr r3, [r3, #0] - 80091d8: f403 6380 and.w r3, r3, #1024 ; 0x400 - 80091dc: 2b00 cmp r3, #0 - 80091de: d1f0 bne.n 80091c2 - } + /* PLL is already used as System core clock */ + return HAL_ERROR; + 8009fda: 2301 movs r3, #1 + 8009fdc: e000 b.n 8009fe0 } } } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 80091e0: 687b ldr r3, [r7, #4] - 80091e2: 681b ldr r3, [r3, #0] - 80091e4: f003 0308 and.w r3, r3, #8 - 80091e8: 2b00 cmp r3, #0 - 80091ea: d03c beq.n 8009266 - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + return HAL_OK; + 8009fde: 2300 movs r3, #0 +} + 8009fe0: 4618 mov r0, r3 + 8009fe2: 3720 adds r7, #32 + 8009fe4: 46bd mov sp, r7 + 8009fe6: bd80 pop {r7, pc} + 8009fe8: 40021000 .word 0x40021000 + 8009fec: feeefffc .word 0xfeeefffc - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 80091ec: 687b ldr r3, [r7, #4] - 80091ee: 695b ldr r3, [r3, #20] - 80091f0: 2b00 cmp r3, #0 - 80091f2: d01c beq.n 800922e - MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv); - } -#endif /* RCC_CSR_LSIPREDIV */ +08009ff0 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8009ff0: b580 push {r7, lr} + 8009ff2: b084 sub sp, #16 + 8009ff4: af00 add r7, sp, #0 + 8009ff6: 6078 str r0, [r7, #4] + 8009ff8: 6039 str r1, [r7, #0] + uint32_t hpre = RCC_SYSCLK_DIV1; +#endif + HAL_StatusTypeDef status; - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - 80091f4: 4b4b ldr r3, [pc, #300] ; (8009324 ) - 80091f6: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 80091fa: 4a4a ldr r2, [pc, #296] ; (8009324 ) - 80091fc: f043 0301 orr.w r3, r3, #1 - 8009200: f8c2 3094 str.w r3, [r2, #148] ; 0x94 + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8009ffa: 687b ldr r3, [r7, #4] + 8009ffc: 2b00 cmp r3, #0 + 8009ffe: d101 bne.n 800a004 + { + return HAL_ERROR; + 800a000: 2301 movs r3, #1 + 800a002: e0e7 b.n 800a1d4 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009204: f7fb f9da bl 80045bc - 8009208: 6138 str r0, [r7, #16] + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 800a004: 4b75 ldr r3, [pc, #468] ; (800a1dc ) + 800a006: 681b ldr r3, [r3, #0] + 800a008: f003 0307 and.w r3, r3, #7 + 800a00c: 683a ldr r2, [r7, #0] + 800a00e: 429a cmp r2, r3 + 800a010: d910 bls.n 800a034 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800a012: 4b72 ldr r3, [pc, #456] ; (800a1dc ) + 800a014: 681b ldr r3, [r3, #0] + 800a016: f023 0207 bic.w r2, r3, #7 + 800a01a: 4970 ldr r1, [pc, #448] ; (800a1dc ) + 800a01c: 683b ldr r3, [r7, #0] + 800a01e: 4313 orrs r3, r2 + 800a020: 600b str r3, [r1, #0] - /* Wait till LSI is ready */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) - 800920a: e008 b.n 800921e - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 800920c: f7fb f9d6 bl 80045bc - 8009210: 4602 mov r2, r0 - 8009212: 693b ldr r3, [r7, #16] - 8009214: 1ad3 subs r3, r2, r3 - 8009216: 2b02 cmp r3, #2 - 8009218: d901 bls.n 800921e - { - return HAL_TIMEOUT; - 800921a: 2303 movs r3, #3 - 800921c: e20c b.n 8009638 - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) - 800921e: 4b41 ldr r3, [pc, #260] ; (8009324 ) - 8009220: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8009224: f003 0302 and.w r3, r3, #2 - 8009228: 2b00 cmp r3, #0 - 800922a: d0ef beq.n 800920c - 800922c: e01b b.n 8009266 - } - } - else + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800a022: 4b6e ldr r3, [pc, #440] ; (800a1dc ) + 800a024: 681b ldr r3, [r3, #0] + 800a026: f003 0307 and.w r3, r3, #7 + 800a02a: 683a ldr r2, [r7, #0] + 800a02c: 429a cmp r2, r3 + 800a02e: d001 beq.n 800a034 { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - 800922e: 4b3d ldr r3, [pc, #244] ; (8009324 ) - 8009230: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8009234: 4a3b ldr r2, [pc, #236] ; (8009324 ) - 8009236: f023 0301 bic.w r3, r3, #1 - 800923a: f8c2 3094 str.w r3, [r2, #148] ; 0x94 - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 800923e: f7fb f9bd bl 80045bc - 8009242: 6138 str r0, [r7, #16] - - /* Wait till LSI is disabled */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) - 8009244: e008 b.n 8009258 - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8009246: f7fb f9b9 bl 80045bc - 800924a: 4602 mov r2, r0 - 800924c: 693b ldr r3, [r7, #16] - 800924e: 1ad3 subs r3, r2, r3 - 8009250: 2b02 cmp r3, #2 - 8009252: d901 bls.n 8009258 - { - return HAL_TIMEOUT; - 8009254: 2303 movs r3, #3 - 8009256: e1ef b.n 8009638 - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) - 8009258: 4b32 ldr r3, [pc, #200] ; (8009324 ) - 800925a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 800925e: f003 0302 and.w r3, r3, #2 - 8009262: 2b00 cmp r3, #0 - 8009264: d1ef bne.n 8009246 - } - } + return HAL_ERROR; + 800a030: 2301 movs r3, #1 + 800a032: e0cf b.n 800a1d4 } } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8009266: 687b ldr r3, [r7, #4] - 8009268: 681b ldr r3, [r3, #0] - 800926a: f003 0304 and.w r3, r3, #4 - 800926e: 2b00 cmp r3, #0 - 8009270: f000 80a6 beq.w 80093c0 + + /*----------------- HCLK Configuration prior to SYSCLK----------------------*/ + /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800a034: 687b ldr r3, [r7, #4] + 800a036: 681b ldr r3, [r3, #0] + 800a038: f003 0302 and.w r3, r3, #2 + 800a03c: 2b00 cmp r3, #0 + 800a03e: d010 beq.n 800a062 { - FlagStatus pwrclkchanged = RESET; - 8009274: 2300 movs r3, #0 - 8009276: 77fb strb r3, [r7, #31] - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) - 8009278: 4b2a ldr r3, [pc, #168] ; (8009324 ) - 800927a: 6d9b ldr r3, [r3, #88] ; 0x58 - 800927c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8009280: 2b00 cmp r3, #0 - 8009282: d10d bne.n 80092a0 + if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) + 800a040: 687b ldr r3, [r7, #4] + 800a042: 689a ldr r2, [r3, #8] + 800a044: 4b66 ldr r3, [pc, #408] ; (800a1e0 ) + 800a046: 689b ldr r3, [r3, #8] + 800a048: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800a04c: 429a cmp r2, r3 + 800a04e: d908 bls.n 800a062 { - __HAL_RCC_PWR_CLK_ENABLE(); - 8009284: 4b27 ldr r3, [pc, #156] ; (8009324 ) - 8009286: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009288: 4a26 ldr r2, [pc, #152] ; (8009324 ) - 800928a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 800928e: 6593 str r3, [r2, #88] ; 0x58 - 8009290: 4b24 ldr r3, [pc, #144] ; (8009324 ) - 8009292: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009294: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8009298: 60bb str r3, [r7, #8] - 800929a: 68bb ldr r3, [r7, #8] - pwrclkchanged = SET; - 800929c: 2301 movs r3, #1 - 800929e: 77fb strb r3, [r7, #31] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800a050: 4b63 ldr r3, [pc, #396] ; (800a1e0 ) + 800a052: 689b ldr r3, [r3, #8] + 800a054: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800a058: 687b ldr r3, [r7, #4] + 800a05a: 689b ldr r3, [r3, #8] + 800a05c: 4960 ldr r1, [pc, #384] ; (800a1e0 ) + 800a05e: 4313 orrs r3, r2 + 800a060: 608b str r3, [r1, #8] } + } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 80092a0: 4b21 ldr r3, [pc, #132] ; (8009328 ) - 80092a2: 681b ldr r3, [r3, #0] - 80092a4: f403 7380 and.w r3, r3, #256 ; 0x100 - 80092a8: 2b00 cmp r3, #0 - 80092aa: d118 bne.n 80092de - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - 80092ac: 4b1e ldr r3, [pc, #120] ; (8009328 ) - 80092ae: 681b ldr r3, [r3, #0] - 80092b0: 4a1d ldr r2, [pc, #116] ; (8009328 ) - 80092b2: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80092b6: 6013 str r3, [r2, #0] - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - 80092b8: f7fb f980 bl 80045bc - 80092bc: 6138 str r0, [r7, #16] + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800a062: 687b ldr r3, [r7, #4] + 800a064: 681b ldr r3, [r3, #0] + 800a066: f003 0301 and.w r3, r3, #1 + 800a06a: 2b00 cmp r3, #0 + 800a06c: d04c beq.n 800a108 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 80092be: e008 b.n 80092d2 - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80092c0: f7fb f97c bl 80045bc - 80092c4: 4602 mov r2, r0 - 80092c6: 693b ldr r3, [r7, #16] - 80092c8: 1ad3 subs r3, r2, r3 - 80092ca: 2b02 cmp r3, #2 - 80092cc: d901 bls.n 80092d2 - { - return HAL_TIMEOUT; - 80092ce: 2303 movs r3, #3 - 80092d0: e1b2 b.n 8009638 - while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 80092d2: 4b15 ldr r3, [pc, #84] ; (8009328 ) - 80092d4: 681b ldr r3, [r3, #0] - 80092d6: f403 7380 and.w r3, r3, #256 ; 0x100 - 80092da: 2b00 cmp r3, #0 - 80092dc: d0f0 beq.n 80092c0 + /* PLL is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800a06e: 687b ldr r3, [r7, #4] + 800a070: 685b ldr r3, [r3, #4] + 800a072: 2b03 cmp r3, #3 + 800a074: d107 bne.n 800a086 { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + /* Check the PLL ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 800a076: 4b5a ldr r3, [pc, #360] ; (800a1e0 ) + 800a078: 681b ldr r3, [r3, #0] + 800a07a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800a07e: 2b00 cmp r3, #0 + 800a080: d121 bne.n 800a0c6 + { + return HAL_ERROR; + 800a082: 2301 movs r3, #1 + 800a084: e0a6 b.n 800a1d4 +#endif } -#else - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 80092de: 687b ldr r3, [r7, #4] - 80092e0: 689b ldr r3, [r3, #8] - 80092e2: 2b01 cmp r3, #1 - 80092e4: d108 bne.n 80092f8 - 80092e6: 4b0f ldr r3, [pc, #60] ; (8009324 ) - 80092e8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80092ec: 4a0d ldr r2, [pc, #52] ; (8009324 ) - 80092ee: f043 0301 orr.w r3, r3, #1 - 80092f2: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - 80092f6: e029 b.n 800934c - 80092f8: 687b ldr r3, [r7, #4] - 80092fa: 689b ldr r3, [r3, #8] - 80092fc: 2b05 cmp r3, #5 - 80092fe: d115 bne.n 800932c - 8009300: 4b08 ldr r3, [pc, #32] ; (8009324 ) - 8009302: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009306: 4a07 ldr r2, [pc, #28] ; (8009324 ) - 8009308: f043 0304 orr.w r3, r3, #4 - 800930c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - 8009310: 4b04 ldr r3, [pc, #16] ; (8009324 ) - 8009312: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009316: 4a03 ldr r2, [pc, #12] ; (8009324 ) - 8009318: f043 0301 orr.w r3, r3, #1 - 800931c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - 8009320: e014 b.n 800934c - 8009322: bf00 nop - 8009324: 40021000 .word 0x40021000 - 8009328: 40007000 .word 0x40007000 - 800932c: 4b9a ldr r3, [pc, #616] ; (8009598 ) - 800932e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009332: 4a99 ldr r2, [pc, #612] ; (8009598 ) - 8009334: f023 0301 bic.w r3, r3, #1 - 8009338: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - 800933c: 4b96 ldr r3, [pc, #600] ; (8009598 ) - 800933e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009342: 4a95 ldr r2, [pc, #596] ; (8009598 ) - 8009344: f023 0304 bic.w r3, r3, #4 - 8009348: f8c2 3090 str.w r3, [r2, #144] ; 0x90 -#endif /* RCC_BDCR_LSESYSDIS */ - - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 800934c: 687b ldr r3, [r7, #4] - 800934e: 689b ldr r3, [r3, #8] - 8009350: 2b00 cmp r3, #0 - 8009352: d016 beq.n 8009382 + else { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009354: f7fb f932 bl 80045bc - 8009358: 6138 str r0, [r7, #16] - - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 800935a: e00a b.n 8009372 + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800a086: 687b ldr r3, [r7, #4] + 800a088: 685b ldr r3, [r3, #4] + 800a08a: 2b02 cmp r3, #2 + 800a08c: d107 bne.n 800a09e { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 800935c: f7fb f92e bl 80045bc - 8009360: 4602 mov r2, r0 - 8009362: 693b ldr r3, [r7, #16] - 8009364: 1ad3 subs r3, r2, r3 - 8009366: f241 3288 movw r2, #5000 ; 0x1388 - 800936a: 4293 cmp r3, r2 - 800936c: d901 bls.n 8009372 + /* Check the HSE ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 800a08e: 4b54 ldr r3, [pc, #336] ; (800a1e0 ) + 800a090: 681b ldr r3, [r3, #0] + 800a092: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800a096: 2b00 cmp r3, #0 + 800a098: d115 bne.n 800a0c6 { - return HAL_TIMEOUT; - 800936e: 2303 movs r3, #3 - 8009370: e162 b.n 8009638 - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 8009372: 4b89 ldr r3, [pc, #548] ; (8009598 ) - 8009374: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009378: f003 0302 and.w r3, r3, #2 - 800937c: 2b00 cmp r3, #0 - 800937e: d0ed beq.n 800935c - 8009380: e015 b.n 80093ae + return HAL_ERROR; + 800a09a: 2301 movs r3, #1 + 800a09c: e09a b.n 800a1d4 + } } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009382: f7fb f91b bl 80045bc - 8009386: 6138 str r0, [r7, #16] - - /* Wait till LSE is disabled */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) - 8009388: e00a b.n 80093a0 + /* MSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 800a09e: 687b ldr r3, [r7, #4] + 800a0a0: 685b ldr r3, [r3, #4] + 800a0a2: 2b00 cmp r3, #0 + 800a0a4: d107 bne.n 800a0b6 { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 800938a: f7fb f917 bl 80045bc - 800938e: 4602 mov r2, r0 - 8009390: 693b ldr r3, [r7, #16] - 8009392: 1ad3 subs r3, r2, r3 - 8009394: f241 3288 movw r2, #5000 ; 0x1388 - 8009398: 4293 cmp r3, r2 - 800939a: d901 bls.n 80093a0 + /* Check the MSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + 800a0a6: 4b4e ldr r3, [pc, #312] ; (800a1e0 ) + 800a0a8: 681b ldr r3, [r3, #0] + 800a0aa: f003 0302 and.w r3, r3, #2 + 800a0ae: 2b00 cmp r3, #0 + 800a0b0: d109 bne.n 800a0c6 { - return HAL_TIMEOUT; - 800939c: 2303 movs r3, #3 - 800939e: e14b b.n 8009638 - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) - 80093a0: 4b7d ldr r3, [pc, #500] ; (8009598 ) - 80093a2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80093a6: f003 0302 and.w r3, r3, #2 - 80093aa: 2b00 cmp r3, #0 - 80093ac: d1ed bne.n 800938a - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS); -#endif /* RCC_BDCR_LSESYSDIS */ + return HAL_ERROR; + 800a0b2: 2301 movs r3, #1 + 800a0b4: e08e b.n 800a1d4 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 800a0b6: 4b4a ldr r3, [pc, #296] ; (800a1e0 ) + 800a0b8: 681b ldr r3, [r3, #0] + 800a0ba: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800a0be: 2b00 cmp r3, #0 + 800a0c0: d101 bne.n 800a0c6 + { + return HAL_ERROR; + 800a0c2: 2301 movs r3, #1 + 800a0c4: e086 b.n 800a1d4 + } +#endif + } - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - 80093ae: 7ffb ldrb r3, [r7, #31] - 80093b0: 2b01 cmp r3, #1 - 80093b2: d105 bne.n 80093c0 + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + 800a0c6: 4b46 ldr r3, [pc, #280] ; (800a1e0 ) + 800a0c8: 689b ldr r3, [r3, #8] + 800a0ca: f023 0203 bic.w r2, r3, #3 + 800a0ce: 687b ldr r3, [r7, #4] + 800a0d0: 685b ldr r3, [r3, #4] + 800a0d2: 4943 ldr r1, [pc, #268] ; (800a1e0 ) + 800a0d4: 4313 orrs r3, r2 + 800a0d6: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800a0d8: f7fb f8ba bl 8005250 + 800a0dc: 60f8 str r0, [r7, #12] + + while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800a0de: e00a b.n 800a0f6 { - __HAL_RCC_PWR_CLK_DISABLE(); - 80093b4: 4b78 ldr r3, [pc, #480] ; (8009598 ) - 80093b6: 6d9b ldr r3, [r3, #88] ; 0x58 - 80093b8: 4a77 ldr r2, [pc, #476] ; (8009598 ) - 80093ba: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 80093be: 6593 str r3, [r2, #88] ; 0x58 + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800a0e0: f7fb f8b6 bl 8005250 + 800a0e4: 4602 mov r2, r0 + 800a0e6: 68fb ldr r3, [r7, #12] + 800a0e8: 1ad3 subs r3, r2, r3 + 800a0ea: f241 3288 movw r2, #5000 ; 0x1388 + 800a0ee: 4293 cmp r3, r2 + 800a0f0: d901 bls.n 800a0f6 + { + return HAL_TIMEOUT; + 800a0f2: 2303 movs r3, #3 + 800a0f4: e06e b.n 800a1d4 + while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800a0f6: 4b3a ldr r3, [pc, #232] ; (800a1e0 ) + 800a0f8: 689b ldr r3, [r3, #8] + 800a0fa: f003 020c and.w r2, r3, #12 + 800a0fe: 687b ldr r3, [r7, #4] + 800a100: 685b ldr r3, [r3, #4] + 800a102: 009b lsls r3, r3, #2 + 800a104: 429a cmp r2, r3 + 800a106: d1eb bne.n 800a0e0 + } +#endif + + /*----------------- HCLK Configuration after SYSCLK-------------------------*/ + /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800a108: 687b ldr r3, [r7, #4] + 800a10a: 681b ldr r3, [r3, #0] + 800a10c: f003 0302 and.w r3, r3, #2 + 800a110: 2b00 cmp r3, #0 + 800a112: d010 beq.n 800a136 + { + if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) + 800a114: 687b ldr r3, [r7, #4] + 800a116: 689a ldr r2, [r3, #8] + 800a118: 4b31 ldr r3, [pc, #196] ; (800a1e0 ) + 800a11a: 689b ldr r3, [r3, #8] + 800a11c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800a120: 429a cmp r2, r3 + 800a122: d208 bcs.n 800a136 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800a124: 4b2e ldr r3, [pc, #184] ; (800a1e0 ) + 800a126: 689b ldr r3, [r3, #8] + 800a128: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800a12c: 687b ldr r3, [r7, #4] + 800a12e: 689b ldr r3, [r3, #8] + 800a130: 492b ldr r1, [pc, #172] ; (800a1e0 ) + 800a132: 4313 orrs r3, r2 + 800a134: 608b str r3, [r1, #8] } } -#if defined(RCC_HSI48_SUPPORT) - /*------------------------------ HSI48 Configuration -----------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - 80093c0: 687b ldr r3, [r7, #4] - 80093c2: 681b ldr r3, [r3, #0] - 80093c4: f003 0320 and.w r3, r3, #32 - 80093c8: 2b00 cmp r3, #0 - 80093ca: d03c beq.n 8009446 + + /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 800a136: 4b29 ldr r3, [pc, #164] ; (800a1dc ) + 800a138: 681b ldr r3, [r3, #0] + 800a13a: f003 0307 and.w r3, r3, #7 + 800a13e: 683a ldr r2, [r7, #0] + 800a140: 429a cmp r2, r3 + 800a142: d210 bcs.n 800a166 { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800a144: 4b25 ldr r3, [pc, #148] ; (800a1dc ) + 800a146: 681b ldr r3, [r3, #0] + 800a148: f023 0207 bic.w r2, r3, #7 + 800a14c: 4923 ldr r1, [pc, #140] ; (800a1dc ) + 800a14e: 683b ldr r3, [r7, #0] + 800a150: 4313 orrs r3, r2 + 800a152: 600b str r3, [r1, #0] - /* Check the LSI State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - 80093cc: 687b ldr r3, [r7, #4] - 80093ce: 6a5b ldr r3, [r3, #36] ; 0x24 - 80093d0: 2b00 cmp r3, #0 - 80093d2: d01c beq.n 800940e + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800a154: 4b21 ldr r3, [pc, #132] ; (800a1dc ) + 800a156: 681b ldr r3, [r3, #0] + 800a158: f003 0307 and.w r3, r3, #7 + 800a15c: 683a ldr r2, [r7, #0] + 800a15e: 429a cmp r2, r3 + 800a160: d001 beq.n 800a166 { - /* Enable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - 80093d4: 4b70 ldr r3, [pc, #448] ; (8009598 ) - 80093d6: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 - 80093da: 4a6f ldr r2, [pc, #444] ; (8009598 ) - 80093dc: f043 0301 orr.w r3, r3, #1 - 80093e0: f8c2 3098 str.w r3, [r2, #152] ; 0x98 + return HAL_ERROR; + 800a162: 2301 movs r3, #1 + 800a164: e036 b.n 800a1d4 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 800a166: 687b ldr r3, [r7, #4] + 800a168: 681b ldr r3, [r3, #0] + 800a16a: f003 0304 and.w r3, r3, #4 + 800a16e: 2b00 cmp r3, #0 + 800a170: d008 beq.n 800a184 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 800a172: 4b1b ldr r3, [pc, #108] ; (800a1e0 ) + 800a174: 689b ldr r3, [r3, #8] + 800a176: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 800a17a: 687b ldr r3, [r7, #4] + 800a17c: 68db ldr r3, [r3, #12] + 800a17e: 4918 ldr r1, [pc, #96] ; (800a1e0 ) + 800a180: 4313 orrs r3, r2 + 800a182: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 800a184: 687b ldr r3, [r7, #4] + 800a186: 681b ldr r3, [r3, #0] + 800a188: f003 0308 and.w r3, r3, #8 + 800a18c: 2b00 cmp r3, #0 + 800a18e: d009 beq.n 800a1a4 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 800a190: 4b13 ldr r3, [pc, #76] ; (800a1e0 ) + 800a192: 689b ldr r3, [r3, #8] + 800a194: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 800a198: 687b ldr r3, [r7, #4] + 800a19a: 691b ldr r3, [r3, #16] + 800a19c: 00db lsls r3, r3, #3 + 800a19e: 4910 ldr r1, [pc, #64] ; (800a1e0 ) + 800a1a0: 4313 orrs r3, r2 + 800a1a2: 608b str r3, [r1, #8] + } - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80093e4: f7fb f8ea bl 80045bc - 80093e8: 6138 str r0, [r7, #16] + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); + 800a1a4: f000 f824 bl 800a1f0 + 800a1a8: 4602 mov r2, r0 + 800a1aa: 4b0d ldr r3, [pc, #52] ; (800a1e0 ) + 800a1ac: 689b ldr r3, [r3, #8] + 800a1ae: 091b lsrs r3, r3, #4 + 800a1b0: f003 030f and.w r3, r3, #15 + 800a1b4: 490b ldr r1, [pc, #44] ; (800a1e4 ) + 800a1b6: 5ccb ldrb r3, [r1, r3] + 800a1b8: f003 031f and.w r3, r3, #31 + 800a1bc: fa22 f303 lsr.w r3, r2, r3 + 800a1c0: 4a09 ldr r2, [pc, #36] ; (800a1e8 ) + 800a1c2: 6013 str r3, [r2, #0] - /* Wait till HSI48 is ready */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) - 80093ea: e008 b.n 80093fe - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - 80093ec: f7fb f8e6 bl 80045bc - 80093f0: 4602 mov r2, r0 - 80093f2: 693b ldr r3, [r7, #16] - 80093f4: 1ad3 subs r3, r2, r3 - 80093f6: 2b02 cmp r3, #2 - 80093f8: d901 bls.n 80093fe - { - return HAL_TIMEOUT; - 80093fa: 2303 movs r3, #3 - 80093fc: e11c b.n 8009638 - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) - 80093fe: 4b66 ldr r3, [pc, #408] ; (8009598 ) - 8009400: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 - 8009404: f003 0302 and.w r3, r3, #2 - 8009408: 2b00 cmp r3, #0 - 800940a: d0ef beq.n 80093ec - 800940c: e01b b.n 8009446 - } - } - else - { - /* Disable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - 800940e: 4b62 ldr r3, [pc, #392] ; (8009598 ) - 8009410: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 - 8009414: 4a60 ldr r2, [pc, #384] ; (8009598 ) - 8009416: f023 0301 bic.w r3, r3, #1 - 800941a: f8c2 3098 str.w r3, [r2, #152] ; 0x98 + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800a1c4: 4b09 ldr r3, [pc, #36] ; (800a1ec ) + 800a1c6: 681b ldr r3, [r3, #0] + 800a1c8: 4618 mov r0, r3 + 800a1ca: f7fa fff1 bl 80051b0 + 800a1ce: 4603 mov r3, r0 + 800a1d0: 72fb strb r3, [r7, #11] - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 800941e: f7fb f8cd bl 80045bc - 8009422: 6138 str r0, [r7, #16] + return status; + 800a1d2: 7afb ldrb r3, [r7, #11] +} + 800a1d4: 4618 mov r0, r3 + 800a1d6: 3710 adds r7, #16 + 800a1d8: 46bd mov sp, r7 + 800a1da: bd80 pop {r7, pc} + 800a1dc: 40022000 .word 0x40022000 + 800a1e0: 40021000 .word 0x40021000 + 800a1e4: 0801aba4 .word 0x0801aba4 + 800a1e8: 20000020 .word 0x20000020 + 800a1ec: 20000024 .word 0x20000024 + +0800a1f0 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 800a1f0: b480 push {r7} + 800a1f2: b089 sub sp, #36 ; 0x24 + 800a1f4: af00 add r7, sp, #0 + uint32_t msirange = 0U, sysclockfreq = 0U; + 800a1f6: 2300 movs r3, #0 + 800a1f8: 61fb str r3, [r7, #28] + 800a1fa: 2300 movs r3, #0 + 800a1fc: 61bb str r3, [r7, #24] + uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */ + uint32_t sysclk_source, pll_oscsource; - /* Wait till HSI48 is disabled */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) - 8009424: e008 b.n 8009438 - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - 8009426: f7fb f8c9 bl 80045bc - 800942a: 4602 mov r2, r0 - 800942c: 693b ldr r3, [r7, #16] - 800942e: 1ad3 subs r3, r2, r3 - 8009430: 2b02 cmp r3, #2 - 8009432: d901 bls.n 8009438 - { - return HAL_TIMEOUT; - 8009434: 2303 movs r3, #3 - 8009436: e0ff b.n 8009638 - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) - 8009438: 4b57 ldr r3, [pc, #348] ; (8009598 ) - 800943a: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 - 800943e: f003 0302 and.w r3, r3, #2 - 8009442: 2b00 cmp r3, #0 - 8009444: d1ef bne.n 8009426 -#endif /* RCC_HSI48_SUPPORT */ - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 800a1fe: 4b3e ldr r3, [pc, #248] ; (800a2f8 ) + 800a200: 689b ldr r3, [r3, #8] + 800a202: f003 030c and.w r3, r3, #12 + 800a206: 613b str r3, [r7, #16] + pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + 800a208: 4b3b ldr r3, [pc, #236] ; (800a2f8 ) + 800a20a: 68db ldr r3, [r3, #12] + 800a20c: f003 0303 and.w r3, r3, #3 + 800a210: 60fb str r3, [r7, #12] - if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) - 8009446: 687b ldr r3, [r7, #4] - 8009448: 6a9b ldr r3, [r3, #40] ; 0x28 - 800944a: 2b00 cmp r3, #0 - 800944c: f000 80f3 beq.w 8009636 + if((sysclk_source == RCC_CFGR_SWS_MSI) || + 800a212: 693b ldr r3, [r7, #16] + 800a214: 2b00 cmp r3, #0 + 800a216: d005 beq.n 800a224 + 800a218: 693b ldr r3, [r7, #16] + 800a21a: 2b0c cmp r3, #12 + 800a21c: d121 bne.n 800a262 + ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) + 800a21e: 68fb ldr r3, [r7, #12] + 800a220: 2b01 cmp r3, #1 + 800a222: d11e bne.n 800a262 { - /* PLL On ? */ - if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) - 8009450: 687b ldr r3, [r7, #4] - 8009452: 6a9b ldr r3, [r3, #40] ; 0x28 - 8009454: 2b02 cmp r3, #2 - 8009456: f040 80c9 bne.w 80095ec -#endif /* RCC_PLLP_SUPPORT */ - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + /* MSI or PLL with MSI source used as system clock source */ - /* Do nothing if PLL configuration is the unchanged */ - pll_config = RCC->PLLCFGR; - 800945a: 4b4f ldr r3, [pc, #316] ; (8009598 ) - 800945c: 68db ldr r3, [r3, #12] - 800945e: 617b str r3, [r7, #20] - if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8009460: 697b ldr r3, [r7, #20] - 8009462: f003 0203 and.w r2, r3, #3 - 8009466: 687b ldr r3, [r7, #4] - 8009468: 6adb ldr r3, [r3, #44] ; 0x2c - 800946a: 429a cmp r2, r3 - 800946c: d12c bne.n 80094c8 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || - 800946e: 697b ldr r3, [r7, #20] - 8009470: f003 0270 and.w r2, r3, #112 ; 0x70 - 8009474: 687b ldr r3, [r7, #4] - 8009476: 6b1b ldr r3, [r3, #48] ; 0x30 - 8009478: 3b01 subs r3, #1 - 800947a: 011b lsls r3, r3, #4 - if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800947c: 429a cmp r2, r3 - 800947e: d123 bne.n 80094c8 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 8009480: 697b ldr r3, [r7, #20] - 8009482: f403 42fe and.w r2, r3, #32512 ; 0x7f00 - 8009486: 687b ldr r3, [r7, #4] - 8009488: 6b5b ldr r3, [r3, #52] ; 0x34 - 800948a: 021b lsls r3, r3, #8 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) || - 800948c: 429a cmp r2, r3 - 800948e: d11b bne.n 80094c8 -#if defined(RCC_PLLP_SUPPORT) -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || - 8009490: 697b ldr r3, [r7, #20] - 8009492: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000 - 8009496: 687b ldr r3, [r7, #4] - 8009498: 6b9b ldr r3, [r3, #56] ; 0x38 - 800949a: 06db lsls r3, r3, #27 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 800949c: 429a cmp r2, r3 - 800949e: d113 bne.n 80094c8 -#else - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) || -#endif -#endif - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || - 80094a0: 697b ldr r3, [r7, #20] - 80094a2: f403 02c0 and.w r2, r3, #6291456 ; 0x600000 - 80094a6: 687b ldr r3, [r7, #4] - 80094a8: 6bdb ldr r3, [r3, #60] ; 0x3c - 80094aa: 085b lsrs r3, r3, #1 - 80094ac: 3b01 subs r3, #1 - 80094ae: 055b lsls r3, r3, #21 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) || - 80094b0: 429a cmp r2, r3 - 80094b2: d109 bne.n 80094c8 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) - 80094b4: 697b ldr r3, [r7, #20] - 80094b6: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000 - 80094ba: 687b ldr r3, [r7, #4] - 80094bc: 6c1b ldr r3, [r3, #64] ; 0x40 - 80094be: 085b lsrs r3, r3, #1 - 80094c0: 3b01 subs r3, #1 - 80094c2: 065b lsls r3, r3, #25 - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || - 80094c4: 429a cmp r2, r3 - 80094c6: d06b beq.n 80095a0 - { - /* Check if the PLL is used as system clock or not */ - if(sysclk_source != RCC_CFGR_SWS_PLL) - 80094c8: 69bb ldr r3, [r7, #24] - 80094ca: 2b0c cmp r3, #12 - 80094cc: d062 beq.n 8009594 - { -#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT) - /* Check if main PLL can be updated */ - /* Not possible if the source is shared by other enabled PLLSAIx */ - if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U) - 80094ce: 4b32 ldr r3, [pc, #200] ; (8009598 ) - 80094d0: 681b ldr r3, [r3, #0] - 80094d2: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 - 80094d6: 2b00 cmp r3, #0 - 80094d8: d001 beq.n 80094de -#if defined(RCC_PLLSAI2_SUPPORT) - || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U) -#endif - ) - { - return HAL_ERROR; - 80094da: 2301 movs r3, #1 - 80094dc: e0ac b.n 8009638 - } - else -#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */ - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 80094de: 4b2e ldr r3, [pc, #184] ; (8009598 ) - 80094e0: 681b ldr r3, [r3, #0] - 80094e2: 4a2d ldr r2, [pc, #180] ; (8009598 ) - 80094e4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 80094e8: 6013 str r3, [r2, #0] + /* Get SYSCLK source */ + if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) + 800a224: 4b34 ldr r3, [pc, #208] ; (800a2f8 ) + 800a226: 681b ldr r3, [r3, #0] + 800a228: f003 0308 and.w r3, r3, #8 + 800a22c: 2b00 cmp r3, #0 + 800a22e: d107 bne.n 800a240 + { /* MSISRANGE from RCC_CSR applies */ + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; + 800a230: 4b31 ldr r3, [pc, #196] ; (800a2f8 ) + 800a232: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800a236: 0a1b lsrs r3, r3, #8 + 800a238: f003 030f and.w r3, r3, #15 + 800a23c: 61fb str r3, [r7, #28] + 800a23e: e005 b.n 800a24c + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; + 800a240: 4b2d ldr r3, [pc, #180] ; (800a2f8 ) + 800a242: 681b ldr r3, [r3, #0] + 800a244: 091b lsrs r3, r3, #4 + 800a246: f003 030f and.w r3, r3, #15 + 800a24a: 61fb str r3, [r7, #28] + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + 800a24c: 4a2b ldr r2, [pc, #172] ; (800a2fc ) + 800a24e: 69fb ldr r3, [r7, #28] + 800a250: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800a254: 61fb str r3, [r7, #28] - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80094ea: f7fb f867 bl 80045bc - 80094ee: 6138 str r0, [r7, #16] + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800a256: 693b ldr r3, [r7, #16] + 800a258: 2b00 cmp r3, #0 + 800a25a: d10d bne.n 800a278 + { + /* MSI used as system clock source */ + sysclockfreq = msirange; + 800a25c: 69fb ldr r3, [r7, #28] + 800a25e: 61bb str r3, [r7, #24] + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800a260: e00a b.n 800a278 + } + } + else if(sysclk_source == RCC_CFGR_SWS_HSI) + 800a262: 693b ldr r3, [r7, #16] + 800a264: 2b04 cmp r3, #4 + 800a266: d102 bne.n 800a26e + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 800a268: 4b25 ldr r3, [pc, #148] ; (800a300 ) + 800a26a: 61bb str r3, [r7, #24] + 800a26c: e004 b.n 800a278 + } + else if(sysclk_source == RCC_CFGR_SWS_HSE) + 800a26e: 693b ldr r3, [r7, #16] + 800a270: 2b08 cmp r3, #8 + 800a272: d101 bne.n 800a278 + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + 800a274: 4b23 ldr r3, [pc, #140] ; (800a304 ) + 800a276: 61bb str r3, [r7, #24] + else + { + /* unexpected case: sysclockfreq at 0 */ + } - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 80094f0: e008 b.n 8009504 - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 80094f2: f7fb f863 bl 80045bc - 80094f6: 4602 mov r2, r0 - 80094f8: 693b ldr r3, [r7, #16] - 80094fa: 1ad3 subs r3, r2, r3 - 80094fc: 2b02 cmp r3, #2 - 80094fe: d901 bls.n 8009504 - { - return HAL_TIMEOUT; - 8009500: 2303 movs r3, #3 - 8009502: e099 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 8009504: 4b24 ldr r3, [pc, #144] ; (8009598 ) - 8009506: 681b ldr r3, [r3, #0] - 8009508: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 800950c: 2b00 cmp r3, #0 - 800950e: d1f0 bne.n 80094f2 - } - } + if(sysclk_source == RCC_CFGR_SWS_PLL) + 800a278: 693b ldr r3, [r7, #16] + 800a27a: 2b0c cmp r3, #12 + 800a27c: d134 bne.n 800a2e8 + /* PLL used as system clock source */ - /* Configure the main PLL clock source, multiplication and division factors. */ -#if defined(RCC_PLLP_SUPPORT) - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 8009510: 4b21 ldr r3, [pc, #132] ; (8009598 ) - 8009512: 68da ldr r2, [r3, #12] - 8009514: 4b21 ldr r3, [pc, #132] ; (800959c ) - 8009516: 4013 ands r3, r2 - 8009518: 687a ldr r2, [r7, #4] - 800951a: 6ad1 ldr r1, [r2, #44] ; 0x2c - 800951c: 687a ldr r2, [r7, #4] - 800951e: 6b12 ldr r2, [r2, #48] ; 0x30 - 8009520: 3a01 subs r2, #1 - 8009522: 0112 lsls r2, r2, #4 - 8009524: 4311 orrs r1, r2 - 8009526: 687a ldr r2, [r7, #4] - 8009528: 6b52 ldr r2, [r2, #52] ; 0x34 - 800952a: 0212 lsls r2, r2, #8 - 800952c: 4311 orrs r1, r2 - 800952e: 687a ldr r2, [r7, #4] - 8009530: 6bd2 ldr r2, [r2, #60] ; 0x3c - 8009532: 0852 lsrs r2, r2, #1 - 8009534: 3a01 subs r2, #1 - 8009536: 0552 lsls r2, r2, #21 - 8009538: 4311 orrs r1, r2 - 800953a: 687a ldr r2, [r7, #4] - 800953c: 6c12 ldr r2, [r2, #64] ; 0x40 - 800953e: 0852 lsrs r2, r2, #1 - 8009540: 3a01 subs r2, #1 - 8009542: 0652 lsls r2, r2, #25 - 8009544: 4311 orrs r1, r2 - 8009546: 687a ldr r2, [r7, #4] - 8009548: 6b92 ldr r2, [r2, #56] ; 0x38 - 800954a: 06d2 lsls r2, r2, #27 - 800954c: 430a orrs r2, r1 - 800954e: 4912 ldr r1, [pc, #72] ; (8009598 ) - 8009550: 4313 orrs r3, r2 - 8009552: 60cb str r3, [r1, #12] - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); -#endif + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM + SYSCLK = PLL_VCO / PLLR + */ + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + 800a27e: 4b1e ldr r3, [pc, #120] ; (800a2f8 ) + 800a280: 68db ldr r3, [r3, #12] + 800a282: f003 0303 and.w r3, r3, #3 + 800a286: 60bb str r3, [r7, #8] - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - 8009554: 4b10 ldr r3, [pc, #64] ; (8009598 ) - 8009556: 681b ldr r3, [r3, #0] - 8009558: 4a0f ldr r2, [pc, #60] ; (8009598 ) - 800955a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 800955e: 6013 str r3, [r2, #0] + switch (pllsource) + 800a288: 68bb ldr r3, [r7, #8] + 800a28a: 2b02 cmp r3, #2 + 800a28c: d003 beq.n 800a296 + 800a28e: 68bb ldr r3, [r7, #8] + 800a290: 2b03 cmp r3, #3 + 800a292: d003 beq.n 800a29c + 800a294: e005 b.n 800a2a2 + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllvco = HSI_VALUE; + 800a296: 4b1a ldr r3, [pc, #104] ; (800a300 ) + 800a298: 617b str r3, [r7, #20] + break; + 800a29a: e005 b.n 800a2a8 - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - 8009560: 4b0d ldr r3, [pc, #52] ; (8009598 ) - 8009562: 68db ldr r3, [r3, #12] - 8009564: 4a0c ldr r2, [pc, #48] ; (8009598 ) - 8009566: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 800956a: 60d3 str r3, [r2, #12] + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = HSE_VALUE; + 800a29c: 4b19 ldr r3, [pc, #100] ; (800a304 ) + 800a29e: 617b str r3, [r7, #20] + break; + 800a2a0: e002 b.n 800a2a8 - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 800956c: f7fb f826 bl 80045bc - 8009570: 6138 str r0, [r7, #16] + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllvco = msirange; + 800a2a2: 69fb ldr r3, [r7, #28] + 800a2a4: 617b str r3, [r7, #20] + break; + 800a2a6: bf00 nop + } + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + 800a2a8: 4b13 ldr r3, [pc, #76] ; (800a2f8 ) + 800a2aa: 68db ldr r3, [r3, #12] + 800a2ac: 091b lsrs r3, r3, #4 + 800a2ae: f003 0307 and.w r3, r3, #7 + 800a2b2: 3301 adds r3, #1 + 800a2b4: 607b str r3, [r7, #4] + pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm; + 800a2b6: 4b10 ldr r3, [pc, #64] ; (800a2f8 ) + 800a2b8: 68db ldr r3, [r3, #12] + 800a2ba: 0a1b lsrs r3, r3, #8 + 800a2bc: f003 037f and.w r3, r3, #127 ; 0x7f + 800a2c0: 697a ldr r2, [r7, #20] + 800a2c2: fb03 f202 mul.w r2, r3, r2 + 800a2c6: 687b ldr r3, [r7, #4] + 800a2c8: fbb2 f3f3 udiv r3, r2, r3 + 800a2cc: 617b str r3, [r7, #20] + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + 800a2ce: 4b0a ldr r3, [pc, #40] ; (800a2f8 ) + 800a2d0: 68db ldr r3, [r3, #12] + 800a2d2: 0e5b lsrs r3, r3, #25 + 800a2d4: f003 0303 and.w r3, r3, #3 + 800a2d8: 3301 adds r3, #1 + 800a2da: 005b lsls r3, r3, #1 + 800a2dc: 603b str r3, [r7, #0] + sysclockfreq = pllvco / pllr; + 800a2de: 697a ldr r2, [r7, #20] + 800a2e0: 683b ldr r3, [r7, #0] + 800a2e2: fbb2 f3f3 udiv r3, r2, r3 + 800a2e6: 61bb str r3, [r7, #24] + } - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 8009572: e008 b.n 8009586 - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8009574: f7fb f822 bl 80045bc - 8009578: 4602 mov r2, r0 - 800957a: 693b ldr r3, [r7, #16] - 800957c: 1ad3 subs r3, r2, r3 - 800957e: 2b02 cmp r3, #2 - 8009580: d901 bls.n 8009586 - { - return HAL_TIMEOUT; - 8009582: 2303 movs r3, #3 - 8009584: e058 b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 8009586: 4b04 ldr r3, [pc, #16] ; (8009598 ) - 8009588: 681b ldr r3, [r3, #0] - 800958a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 800958e: 2b00 cmp r3, #0 - 8009590: d0f0 beq.n 8009574 - if(sysclk_source != RCC_CFGR_SWS_PLL) - 8009592: e050 b.n 8009636 - } - } - else - { - /* PLL is already used as System core clock */ - return HAL_ERROR; - 8009594: 2301 movs r3, #1 - 8009596: e04f b.n 8009638 - 8009598: 40021000 .word 0x40021000 - 800959c: 019d808c .word 0x019d808c - } - else - { - /* PLL configuration is unchanged */ - /* Re-enable PLL if it was disabled (ie. low power mode) */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80095a0: 4b27 ldr r3, [pc, #156] ; (8009640 ) - 80095a2: 681b ldr r3, [r3, #0] - 80095a4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80095a8: 2b00 cmp r3, #0 - 80095aa: d144 bne.n 8009636 - { - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - 80095ac: 4b24 ldr r3, [pc, #144] ; (8009640 ) - 80095ae: 681b ldr r3, [r3, #0] - 80095b0: 4a23 ldr r2, [pc, #140] ; (8009640 ) - 80095b2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 80095b6: 6013 str r3, [r2, #0] + return sysclockfreq; + 800a2e8: 69bb ldr r3, [r7, #24] +} + 800a2ea: 4618 mov r0, r3 + 800a2ec: 3724 adds r7, #36 ; 0x24 + 800a2ee: 46bd mov sp, r7 + 800a2f0: f85d 7b04 ldr.w r7, [sp], #4 + 800a2f4: 4770 bx lr + 800a2f6: bf00 nop + 800a2f8: 40021000 .word 0x40021000 + 800a2fc: 0801abbc .word 0x0801abbc + 800a300: 00f42400 .word 0x00f42400 + 800a304: 007a1200 .word 0x007a1200 + +0800a308 : + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 800a308: b480 push {r7} + 800a30a: af00 add r7, sp, #0 + return SystemCoreClock; + 800a30c: 4b03 ldr r3, [pc, #12] ; (800a31c ) + 800a30e: 681b ldr r3, [r3, #0] +} + 800a310: 4618 mov r0, r3 + 800a312: 46bd mov sp, r7 + 800a314: f85d 7b04 ldr.w r7, [sp], #4 + 800a318: 4770 bx lr + 800a31a: bf00 nop + 800a31c: 20000020 .word 0x20000020 - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - 80095b8: 4b21 ldr r3, [pc, #132] ; (8009640 ) - 80095ba: 68db ldr r3, [r3, #12] - 80095bc: 4a20 ldr r2, [pc, #128] ; (8009640 ) - 80095be: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 80095c2: 60d3 str r3, [r2, #12] +0800a320 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 800a320: b580 push {r7, lr} + 800a322: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); + 800a324: f7ff fff0 bl 800a308 + 800a328: 4602 mov r2, r0 + 800a32a: 4b06 ldr r3, [pc, #24] ; (800a344 ) + 800a32c: 689b ldr r3, [r3, #8] + 800a32e: 0a1b lsrs r3, r3, #8 + 800a330: f003 0307 and.w r3, r3, #7 + 800a334: 4904 ldr r1, [pc, #16] ; (800a348 ) + 800a336: 5ccb ldrb r3, [r1, r3] + 800a338: f003 031f and.w r3, r3, #31 + 800a33c: fa22 f303 lsr.w r3, r2, r3 +} + 800a340: 4618 mov r0, r3 + 800a342: bd80 pop {r7, pc} + 800a344: 40021000 .word 0x40021000 + 800a348: 0801abb4 .word 0x0801abb4 + +0800a34c : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 800a34c: b580 push {r7, lr} + 800a34e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); + 800a350: f7ff ffda bl 800a308 + 800a354: 4602 mov r2, r0 + 800a356: 4b06 ldr r3, [pc, #24] ; (800a370 ) + 800a358: 689b ldr r3, [r3, #8] + 800a35a: 0adb lsrs r3, r3, #11 + 800a35c: f003 0307 and.w r3, r3, #7 + 800a360: 4904 ldr r1, [pc, #16] ; (800a374 ) + 800a362: 5ccb ldrb r3, [r1, r3] + 800a364: f003 031f and.w r3, r3, #31 + 800a368: fa22 f303 lsr.w r3, r2, r3 +} + 800a36c: 4618 mov r0, r3 + 800a36e: bd80 pop {r7, pc} + 800a370: 40021000 .word 0x40021000 + 800a374: 0801abb4 .word 0x0801abb4 + +0800a378 : + voltage range. + * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) +{ + 800a378: b580 push {r7, lr} + 800a37a: b086 sub sp, #24 + 800a37c: af00 add r7, sp, #0 + 800a37e: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 800a380: 2300 movs r3, #0 + 800a382: 613b str r3, [r7, #16] - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80095c4: f7fa fffa bl 80045bc - 80095c8: 6138 str r0, [r7, #16] + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 800a384: 4b2a ldr r3, [pc, #168] ; (800a430 ) + 800a386: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a388: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800a38c: 2b00 cmp r3, #0 + 800a38e: d003 beq.n 800a398 + { + vos = HAL_PWREx_GetVoltageRange(); + 800a390: f7ff f9a6 bl 80096e0 + 800a394: 6178 str r0, [r7, #20] + 800a396: e014 b.n 800a3c2 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 800a398: 4b25 ldr r3, [pc, #148] ; (800a430 ) + 800a39a: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a39c: 4a24 ldr r2, [pc, #144] ; (800a430 ) + 800a39e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800a3a2: 6593 str r3, [r2, #88] ; 0x58 + 800a3a4: 4b22 ldr r3, [pc, #136] ; (800a430 ) + 800a3a6: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a3a8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800a3ac: 60fb str r3, [r7, #12] + 800a3ae: 68fb ldr r3, [r7, #12] + vos = HAL_PWREx_GetVoltageRange(); + 800a3b0: f7ff f996 bl 80096e0 + 800a3b4: 6178 str r0, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 800a3b6: 4b1e ldr r3, [pc, #120] ; (800a430 ) + 800a3b8: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a3ba: 4a1d ldr r2, [pc, #116] ; (800a430 ) + 800a3bc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800a3c0: 6593 str r3, [r2, #88] ; 0x58 + } - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80095ca: e008 b.n 80095de - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 80095cc: f7fa fff6 bl 80045bc - 80095d0: 4602 mov r2, r0 - 80095d2: 693b ldr r3, [r7, #16] - 80095d4: 1ad3 subs r3, r2, r3 - 80095d6: 2b02 cmp r3, #2 - 80095d8: d901 bls.n 80095de - { - return HAL_TIMEOUT; - 80095da: 2303 movs r3, #3 - 80095dc: e02c b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80095de: 4b18 ldr r3, [pc, #96] ; (8009640 ) - 80095e0: 681b ldr r3, [r3, #0] - 80095e2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80095e6: 2b00 cmp r3, #0 - 80095e8: d0f0 beq.n 80095cc - 80095ea: e024 b.n 8009636 + if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) + 800a3c2: 697b ldr r3, [r7, #20] + 800a3c4: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800a3c8: d10b bne.n 800a3e2 + { + if(msirange > RCC_MSIRANGE_8) + 800a3ca: 687b ldr r3, [r7, #4] + 800a3cc: 2b80 cmp r3, #128 ; 0x80 + 800a3ce: d919 bls.n 800a404 + { + /* MSI > 16Mhz */ + if(msirange > RCC_MSIRANGE_10) + 800a3d0: 687b ldr r3, [r7, #4] + 800a3d2: 2ba0 cmp r3, #160 ; 0xa0 + 800a3d4: d902 bls.n 800a3dc + { + /* MSI 48Mhz */ + latency = FLASH_LATENCY_2; /* 2WS */ + 800a3d6: 2302 movs r3, #2 + 800a3d8: 613b str r3, [r7, #16] + 800a3da: e013 b.n 800a404 + } + else + { + /* MSI 24Mhz or 32Mhz */ + latency = FLASH_LATENCY_1; /* 1WS */ + 800a3dc: 2301 movs r3, #1 + 800a3de: 613b str r3, [r7, #16] + 800a3e0: e010 b.n 800a404 + latency = FLASH_LATENCY_1; /* 1WS */ } + /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + } +#else + if(msirange > RCC_MSIRANGE_8) + 800a3e2: 687b ldr r3, [r7, #4] + 800a3e4: 2b80 cmp r3, #128 ; 0x80 + 800a3e6: d902 bls.n 800a3ee + { + /* MSI > 16Mhz */ + latency = FLASH_LATENCY_3; /* 3WS */ + 800a3e8: 2303 movs r3, #3 + 800a3ea: 613b str r3, [r7, #16] + 800a3ec: e00a b.n 800a404 } else { - /* Check that PLL is not used as system clock or not */ - if(sysclk_source != RCC_CFGR_SWS_PLL) - 80095ec: 69bb ldr r3, [r7, #24] - 80095ee: 2b0c cmp r3, #12 - 80095f0: d01f beq.n 8009632 + if(msirange == RCC_MSIRANGE_8) + 800a3ee: 687b ldr r3, [r7, #4] + 800a3f0: 2b80 cmp r3, #128 ; 0x80 + 800a3f2: d102 bne.n 800a3fa { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - 80095f2: 4b13 ldr r3, [pc, #76] ; (8009640 ) - 80095f4: 681b ldr r3, [r3, #0] - 80095f6: 4a12 ldr r2, [pc, #72] ; (8009640 ) - 80095f8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 80095fc: 6013 str r3, [r2, #0] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 80095fe: f7fa ffdd bl 80045bc - 8009602: 6138 str r0, [r7, #16] - - /* Wait till PLL is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 8009604: e008 b.n 8009618 - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8009606: f7fa ffd9 bl 80045bc - 800960a: 4602 mov r2, r0 - 800960c: 693b ldr r3, [r7, #16] - 800960e: 1ad3 subs r3, r2, r3 - 8009610: 2b02 cmp r3, #2 - 8009612: d901 bls.n 8009618 - { - return HAL_TIMEOUT; - 8009614: 2303 movs r3, #3 - 8009616: e00f b.n 8009638 - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 8009618: 4b09 ldr r3, [pc, #36] ; (8009640 ) - 800961a: 681b ldr r3, [r3, #0] - 800961c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8009620: 2b00 cmp r3, #0 - 8009622: d1f0 bne.n 8009606 - } - /* Unselect main PLL clock source and disable main PLL outputs to save power */ -#if defined(RCC_PLLSAI2_SUPPORT) - RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); -#elif defined(RCC_PLLSAI1_SUPPORT) - RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); - 8009624: 4b06 ldr r3, [pc, #24] ; (8009640 ) - 8009626: 68da ldr r2, [r3, #12] - 8009628: 4905 ldr r1, [pc, #20] ; (8009640 ) - 800962a: 4b06 ldr r3, [pc, #24] ; (8009644 ) - 800962c: 4013 ands r3, r2 - 800962e: 60cb str r3, [r1, #12] - 8009630: e001 b.n 8009636 -#endif /* RCC_PLLSAI2_SUPPORT */ + /* MSI 16Mhz */ + latency = FLASH_LATENCY_2; /* 2WS */ + 800a3f4: 2302 movs r3, #2 + 800a3f6: 613b str r3, [r7, #16] + 800a3f8: e004 b.n 800a404 } - else + else if(msirange == RCC_MSIRANGE_7) + 800a3fa: 687b ldr r3, [r7, #4] + 800a3fc: 2b70 cmp r3, #112 ; 0x70 + 800a3fe: d101 bne.n 800a404 { - /* PLL is already used as System core clock */ - return HAL_ERROR; - 8009632: 2301 movs r3, #1 - 8009634: e000 b.n 8009638 - } + /* MSI 8Mhz */ + latency = FLASH_LATENCY_1; /* 1WS */ + 800a400: 2301 movs r3, #1 + 800a402: 613b str r3, [r7, #16] + /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ } +#endif + } + + __HAL_FLASH_SET_LATENCY(latency); + 800a404: 4b0b ldr r3, [pc, #44] ; (800a434 ) + 800a406: 681b ldr r3, [r3, #0] + 800a408: f023 0207 bic.w r2, r3, #7 + 800a40c: 4909 ldr r1, [pc, #36] ; (800a434 ) + 800a40e: 693b ldr r3, [r7, #16] + 800a410: 4313 orrs r3, r2 + 800a412: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 800a414: 4b07 ldr r3, [pc, #28] ; (800a434 ) + 800a416: 681b ldr r3, [r3, #0] + 800a418: f003 0307 and.w r3, r3, #7 + 800a41c: 693a ldr r2, [r7, #16] + 800a41e: 429a cmp r2, r3 + 800a420: d001 beq.n 800a426 + { + return HAL_ERROR; + 800a422: 2301 movs r3, #1 + 800a424: e000 b.n 800a428 } + return HAL_OK; - 8009636: 2300 movs r3, #0 + 800a426: 2300 movs r3, #0 } - 8009638: 4618 mov r0, r3 - 800963a: 3720 adds r7, #32 - 800963c: 46bd mov sp, r7 - 800963e: bd80 pop {r7, pc} - 8009640: 40021000 .word 0x40021000 - 8009644: feeefffc .word 0xfeeefffc + 800a428: 4618 mov r0, r3 + 800a42a: 3718 adds r7, #24 + 800a42c: 46bd mov sp, r7 + 800a42e: bd80 pop {r7, pc} + 800a430: 40021000 .word 0x40021000 + 800a434: 40022000 .word 0x40022000 -08009648 : - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None +0800a438 : + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8009648: b580 push {r7, lr} - 800964a: b084 sub sp, #16 - 800964c: af00 add r7, sp, #0 - 800964e: 6078 str r0, [r7, #4] - 8009650: 6039 str r1, [r7, #0] - uint32_t hpre = RCC_SYSCLK_DIV1; -#endif - HAL_StatusTypeDef status; + 800a438: b580 push {r7, lr} + 800a43a: b086 sub sp, #24 + 800a43c: af00 add r7, sp, #0 + 800a43e: 6078 str r0, [r7, #4] + uint32_t tmpregister, tickstart; /* no init needed */ + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 800a440: 2300 movs r3, #0 + 800a442: 74fb strb r3, [r7, #19] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 800a444: 2300 movs r3, #0 + 800a446: 74bb strb r3, [r7, #18] + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) - 8009652: 687b ldr r3, [r7, #4] - 8009654: 2b00 cmp r3, #0 - 8009656: d101 bne.n 800965c - { - return HAL_ERROR; - 8009658: 2301 movs r3, #1 - 800965a: e0e7 b.n 800982c - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ +#if defined(SAI1) - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) - 800965c: 4b75 ldr r3, [pc, #468] ; (8009834 ) - 800965e: 681b ldr r3, [r3, #0] - 8009660: f003 0307 and.w r3, r3, #7 - 8009664: 683a ldr r2, [r7, #0] - 8009666: 429a cmp r2, r3 - 8009668: d910 bls.n 800968c + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) + 800a448: 687b ldr r3, [r7, #4] + 800a44a: 681b ldr r3, [r3, #0] + 800a44c: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800a450: 2b00 cmp r3, #0 + 800a452: d031 beq.n 800a4b8 { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 800966a: 4b72 ldr r3, [pc, #456] ; (8009834 ) - 800966c: 681b ldr r3, [r3, #0] - 800966e: f023 0207 bic.w r2, r3, #7 - 8009672: 4970 ldr r1, [pc, #448] ; (8009834 ) - 8009674: 683b ldr r3, [r7, #0] - 8009676: 4313 orrs r3, r2 - 8009678: 600b str r3, [r1, #0] + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - 800967a: 4b6e ldr r3, [pc, #440] ; (8009834 ) - 800967c: 681b ldr r3, [r3, #0] - 800967e: f003 0307 and.w r3, r3, #7 - 8009682: 683a ldr r2, [r7, #0] - 8009684: 429a cmp r2, r3 - 8009686: d001 beq.n 800968c + switch(PeriphClkInit->Sai1ClockSelection) + 800a454: 687b ldr r3, [r7, #4] + 800a456: 6bdb ldr r3, [r3, #60] ; 0x3c + 800a458: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000 + 800a45c: d01a beq.n 800a494 + 800a45e: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000 + 800a462: d814 bhi.n 800a48e + 800a464: 2b00 cmp r3, #0 + 800a466: d009 beq.n 800a47c + 800a468: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 + 800a46c: d10f bne.n 800a48e + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated from System PLL . */ +#if defined(RCC_PLLSAI2_SUPPORT) + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); +#else + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); + 800a46e: 4b5d ldr r3, [pc, #372] ; (800a5e4 ) + 800a470: 68db ldr r3, [r3, #12] + 800a472: 4a5c ldr r2, [pc, #368] ; (800a5e4 ) + 800a474: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800a478: 60d3 str r3, [r2, #12] +#endif /* RCC_PLLSAI2_SUPPORT */ + /* SAI1 clock source config set later after clock selection check */ + break; + 800a47a: e00c b.n 800a496 + + case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ + /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); + 800a47c: 687b ldr r3, [r7, #4] + 800a47e: 3304 adds r3, #4 + 800a480: 2100 movs r1, #0 + 800a482: 4618 mov r0, r3 + 800a484: f000 f9ce bl 800a824 + 800a488: 4603 mov r3, r0 + 800a48a: 74fb strb r3, [r7, #19] + /* SAI1 clock source config set later after clock selection check */ + break; + 800a48c: e003 b.n 800a496 +#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ + /* SAI1 clock source config set later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + 800a48e: 2301 movs r3, #1 + 800a490: 74fb strb r3, [r7, #19] + break; + 800a492: e000 b.n 800a496 + break; + 800a494: bf00 nop + } + + if(ret == HAL_OK) + 800a496: 7cfb ldrb r3, [r7, #19] + 800a498: 2b00 cmp r3, #0 + 800a49a: d10b bne.n 800a4b4 { - return HAL_ERROR; - 8009688: 2301 movs r3, #1 - 800968a: e0cf b.n 800982c + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 800a49c: 4b51 ldr r3, [pc, #324] ; (800a5e4 ) + 800a49e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a4a2: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 800a4a6: 687b ldr r3, [r7, #4] + 800a4a8: 6bdb ldr r3, [r3, #60] ; 0x3c + 800a4aa: 494e ldr r1, [pc, #312] ; (800a5e4 ) + 800a4ac: 4313 orrs r3, r2 + 800a4ae: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 800a4b2: e001 b.n 800a4b8 + } + else + { + /* set overall return value */ + status = ret; + 800a4b4: 7cfb ldrb r3, [r7, #19] + 800a4b6: 74bb strb r3, [r7, #18] } } +#endif /* SAI2 */ - /*----------------- HCLK Configuration prior to SYSCLK----------------------*/ - /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 800968c: 687b ldr r3, [r7, #4] - 800968e: 681b ldr r3, [r3, #0] - 8009690: f003 0302 and.w r3, r3, #2 - 8009694: 2b00 cmp r3, #0 - 8009696: d010 beq.n 80096ba + /*-------------------------- RTC clock source configuration ----------------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 800a4b8: 687b ldr r3, [r7, #4] + 800a4ba: 681b ldr r3, [r3, #0] + 800a4bc: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800a4c0: 2b00 cmp r3, #0 + 800a4c2: f000 809e beq.w 800a602 { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + FlagStatus pwrclkchanged = RESET; + 800a4c6: 2300 movs r3, #0 + 800a4c8: 747b strb r3, [r7, #17] - if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) - 8009698: 687b ldr r3, [r7, #4] - 800969a: 689a ldr r2, [r3, #8] - 800969c: 4b66 ldr r3, [pc, #408] ; (8009838 ) - 800969e: 689b ldr r3, [r3, #8] - 80096a0: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 80096a4: 429a cmp r2, r3 - 80096a6: d908 bls.n 80096ba + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + 800a4ca: 4b46 ldr r3, [pc, #280] ; (800a5e4 ) + 800a4cc: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a4ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800a4d2: 2b00 cmp r3, #0 + 800a4d4: d101 bne.n 800a4da + 800a4d6: 2301 movs r3, #1 + 800a4d8: e000 b.n 800a4dc + 800a4da: 2300 movs r3, #0 + 800a4dc: 2b00 cmp r3, #0 + 800a4de: d00d beq.n 800a4fc { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 80096a8: 4b63 ldr r3, [pc, #396] ; (8009838 ) - 80096aa: 689b ldr r3, [r3, #8] - 80096ac: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 80096b0: 687b ldr r3, [r7, #4] - 80096b2: 689b ldr r3, [r3, #8] - 80096b4: 4960 ldr r1, [pc, #384] ; (8009838 ) - 80096b6: 4313 orrs r3, r2 - 80096b8: 608b str r3, [r1, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800a4e0: 4b40 ldr r3, [pc, #256] ; (800a5e4 ) + 800a4e2: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a4e4: 4a3f ldr r2, [pc, #252] ; (800a5e4 ) + 800a4e6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800a4ea: 6593 str r3, [r2, #88] ; 0x58 + 800a4ec: 4b3d ldr r3, [pc, #244] ; (800a5e4 ) + 800a4ee: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a4f0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800a4f4: 60bb str r3, [r7, #8] + 800a4f6: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 800a4f8: 2301 movs r3, #1 + 800a4fa: 747b strb r3, [r7, #17] } - } - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 80096ba: 687b ldr r3, [r7, #4] - 80096bc: 681b ldr r3, [r3, #0] - 80096be: f003 0301 and.w r3, r3, #1 - 80096c2: 2b00 cmp r3, #0 - 80096c4: d04c beq.n 8009760 - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 800a4fc: 4b3a ldr r3, [pc, #232] ; (800a5e8 ) + 800a4fe: 681b ldr r3, [r3, #0] + 800a500: 4a39 ldr r2, [pc, #228] ; (800a5e8 ) + 800a502: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800a506: 6013 str r3, [r2, #0] - /* PLL is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 80096c6: 687b ldr r3, [r7, #4] - 80096c8: 685b ldr r3, [r3, #4] - 80096ca: 2b03 cmp r3, #3 - 80096cc: d107 bne.n 80096de + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 800a508: f7fa fea2 bl 8005250 + 800a50c: 60f8 str r0, [r7, #12] + + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) + 800a50e: e009 b.n 800a524 { - /* Check the PLL ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80096ce: 4b5a ldr r3, [pc, #360] ; (8009838 ) - 80096d0: 681b ldr r3, [r3, #0] - 80096d2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80096d6: 2b00 cmp r3, #0 - 80096d8: d121 bne.n 800971e + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 800a510: f7fa fe9e bl 8005250 + 800a514: 4602 mov r2, r0 + 800a516: 68fb ldr r3, [r7, #12] + 800a518: 1ad3 subs r3, r2, r3 + 800a51a: 2b02 cmp r3, #2 + 800a51c: d902 bls.n 800a524 { - return HAL_ERROR; - 80096da: 2301 movs r3, #1 - 80096dc: e0a6 b.n 800982c -#endif + ret = HAL_TIMEOUT; + 800a51e: 2303 movs r3, #3 + 800a520: 74fb strb r3, [r7, #19] + break; + 800a522: e005 b.n 800a530 + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) + 800a524: 4b30 ldr r3, [pc, #192] ; (800a5e8 ) + 800a526: 681b ldr r3, [r3, #0] + 800a528: f403 7380 and.w r3, r3, #256 ; 0x100 + 800a52c: 2b00 cmp r3, #0 + 800a52e: d0ef beq.n 800a510 + } } - else + + if(ret == HAL_OK) + 800a530: 7cfb ldrb r3, [r7, #19] + 800a532: 2b00 cmp r3, #0 + 800a534: d15a bne.n 800a5ec { - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 80096de: 687b ldr r3, [r7, #4] - 80096e0: 685b ldr r3, [r3, #4] - 80096e2: 2b02 cmp r3, #2 - 80096e4: d107 bne.n 80096f6 + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + 800a536: 4b2b ldr r3, [pc, #172] ; (800a5e4 ) + 800a538: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a53c: f403 7340 and.w r3, r3, #768 ; 0x300 + 800a540: 617b str r3, [r7, #20] + + if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) + 800a542: 697b ldr r3, [r7, #20] + 800a544: 2b00 cmp r3, #0 + 800a546: d01e beq.n 800a586 + 800a548: 687b ldr r3, [r7, #4] + 800a54a: 6d1b ldr r3, [r3, #80] ; 0x50 + 800a54c: 697a ldr r2, [r7, #20] + 800a54e: 429a cmp r2, r3 + 800a550: d019 beq.n 800a586 { - /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 80096e6: 4b54 ldr r3, [pc, #336] ; (8009838 ) - 80096e8: 681b ldr r3, [r3, #0] - 80096ea: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80096ee: 2b00 cmp r3, #0 - 80096f0: d115 bne.n 800971e + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 800a552: 4b24 ldr r3, [pc, #144] ; (800a5e4 ) + 800a554: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a558: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800a55c: 617b str r3, [r7, #20] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 800a55e: 4b21 ldr r3, [pc, #132] ; (800a5e4 ) + 800a560: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a564: 4a1f ldr r2, [pc, #124] ; (800a5e4 ) + 800a566: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800a56a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + __HAL_RCC_BACKUPRESET_RELEASE(); + 800a56e: 4b1d ldr r3, [pc, #116] ; (800a5e4 ) + 800a570: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a574: 4a1b ldr r2, [pc, #108] ; (800a5e4 ) + 800a576: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800a57a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + 800a57e: 4a19 ldr r2, [pc, #100] ; (800a5e4 ) + 800a580: 697b ldr r3, [r7, #20] + 800a582: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + 800a586: 697b ldr r3, [r7, #20] + 800a588: f003 0301 and.w r3, r3, #1 + 800a58c: 2b00 cmp r3, #0 + 800a58e: d016 beq.n 800a5be + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800a590: f7fa fe5e bl 8005250 + 800a594: 60f8 str r0, [r7, #12] + + /* Wait till LSE is ready */ + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 800a596: e00b b.n 800a5b0 { - return HAL_ERROR; - 80096f2: 2301 movs r3, #1 - 80096f4: e09a b.n 800982c + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800a598: f7fa fe5a bl 8005250 + 800a59c: 4602 mov r2, r0 + 800a59e: 68fb ldr r3, [r7, #12] + 800a5a0: 1ad3 subs r3, r2, r3 + 800a5a2: f241 3288 movw r2, #5000 ; 0x1388 + 800a5a6: 4293 cmp r3, r2 + 800a5a8: d902 bls.n 800a5b0 + { + ret = HAL_TIMEOUT; + 800a5aa: 2303 movs r3, #3 + 800a5ac: 74fb strb r3, [r7, #19] + break; + 800a5ae: e006 b.n 800a5be + while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 800a5b0: 4b0c ldr r3, [pc, #48] ; (800a5e4 ) + 800a5b2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a5b6: f003 0302 and.w r3, r3, #2 + 800a5ba: 2b00 cmp r3, #0 + 800a5bc: d0ec beq.n 800a598 + } } } - /* MSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - 80096f6: 687b ldr r3, [r7, #4] - 80096f8: 685b ldr r3, [r3, #4] - 80096fa: 2b00 cmp r3, #0 - 80096fc: d107 bne.n 800970e + + if(ret == HAL_OK) + 800a5be: 7cfb ldrb r3, [r7, #19] + 800a5c0: 2b00 cmp r3, #0 + 800a5c2: d10b bne.n 800a5dc { - /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) - 80096fe: 4b4e ldr r3, [pc, #312] ; (8009838 ) - 8009700: 681b ldr r3, [r3, #0] - 8009702: f003 0302 and.w r3, r3, #2 - 8009706: 2b00 cmp r3, #0 - 8009708: d109 bne.n 800971e - { - return HAL_ERROR; - 800970a: 2301 movs r3, #1 - 800970c: e08e b.n 800982c + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800a5c4: 4b07 ldr r3, [pc, #28] ; (800a5e4 ) + 800a5c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a5ca: f423 7240 bic.w r2, r3, #768 ; 0x300 + 800a5ce: 687b ldr r3, [r7, #4] + 800a5d0: 6d1b ldr r3, [r3, #80] ; 0x50 + 800a5d2: 4904 ldr r1, [pc, #16] ; (800a5e4 ) + 800a5d4: 4313 orrs r3, r2 + 800a5d6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 800a5da: e009 b.n 800a5f0 } - /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 800970e: 4b4a ldr r3, [pc, #296] ; (8009838 ) - 8009710: 681b ldr r3, [r3, #0] - 8009712: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8009716: 2b00 cmp r3, #0 - 8009718: d101 bne.n 800971e - { - return HAL_ERROR; - 800971a: 2301 movs r3, #1 - 800971c: e086 b.n 800982c + /* set overall return value */ + status = ret; + 800a5dc: 7cfb ldrb r3, [r7, #19] + 800a5de: 74bb strb r3, [r7, #18] + 800a5e0: e006 b.n 800a5f0 + 800a5e2: bf00 nop + 800a5e4: 40021000 .word 0x40021000 + 800a5e8: 40007000 .word 0x40007000 } -#endif - } - - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - 800971e: 4b46 ldr r3, [pc, #280] ; (8009838 ) - 8009720: 689b ldr r3, [r3, #8] - 8009722: f023 0203 bic.w r2, r3, #3 - 8009726: 687b ldr r3, [r7, #4] - 8009728: 685b ldr r3, [r3, #4] - 800972a: 4943 ldr r1, [pc, #268] ; (8009838 ) - 800972c: 4313 orrs r3, r2 - 800972e: 608b str r3, [r1, #8] - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009730: f7fa ff44 bl 80045bc - 8009734: 60f8 str r0, [r7, #12] - - while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8009736: e00a b.n 800974e - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8009738: f7fa ff40 bl 80045bc - 800973c: 4602 mov r2, r0 - 800973e: 68fb ldr r3, [r7, #12] - 8009740: 1ad3 subs r3, r2, r3 - 8009742: f241 3288 movw r2, #5000 ; 0x1388 - 8009746: 4293 cmp r3, r2 - 8009748: d901 bls.n 800974e - { - return HAL_TIMEOUT; - 800974a: 2303 movs r3, #3 - 800974c: e06e b.n 800982c - while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 800974e: 4b3a ldr r3, [pc, #232] ; (8009838 ) - 8009750: 689b ldr r3, [r3, #8] - 8009752: f003 020c and.w r2, r3, #12 - 8009756: 687b ldr r3, [r7, #4] - 8009758: 685b ldr r3, [r3, #4] - 800975a: 009b lsls r3, r3, #2 - 800975c: 429a cmp r2, r3 - 800975e: d1eb bne.n 8009738 - } -#endif - - /*----------------- HCLK Configuration after SYSCLK-------------------------*/ - /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8009760: 687b ldr r3, [r7, #4] - 8009762: 681b ldr r3, [r3, #0] - 8009764: f003 0302 and.w r3, r3, #2 - 8009768: 2b00 cmp r3, #0 - 800976a: d010 beq.n 800978e - { - if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)) - 800976c: 687b ldr r3, [r7, #4] - 800976e: 689a ldr r2, [r3, #8] - 8009770: 4b31 ldr r3, [pc, #196] ; (8009838 ) - 8009772: 689b ldr r3, [r3, #8] - 8009774: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8009778: 429a cmp r2, r3 - 800977a: d208 bcs.n 800978e + else { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 800977c: 4b2e ldr r3, [pc, #184] ; (8009838 ) - 800977e: 689b ldr r3, [r3, #8] - 8009780: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8009784: 687b ldr r3, [r7, #4] - 8009786: 689b ldr r3, [r3, #8] - 8009788: 492b ldr r1, [pc, #172] ; (8009838 ) - 800978a: 4313 orrs r3, r2 - 800978c: 608b str r3, [r1, #8] - } - } - - /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) - 800978e: 4b29 ldr r3, [pc, #164] ; (8009834 ) - 8009790: 681b ldr r3, [r3, #0] - 8009792: f003 0307 and.w r3, r3, #7 - 8009796: 683a ldr r2, [r7, #0] - 8009798: 429a cmp r2, r3 - 800979a: d210 bcs.n 80097be - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - 800979c: 4b25 ldr r3, [pc, #148] ; (8009834 ) - 800979e: 681b ldr r3, [r3, #0] - 80097a0: f023 0207 bic.w r2, r3, #7 - 80097a4: 4923 ldr r1, [pc, #140] ; (8009834 ) - 80097a6: 683b ldr r3, [r7, #0] - 80097a8: 4313 orrs r3, r2 - 80097aa: 600b str r3, [r1, #0] + /* set overall return value */ + status = ret; + 800a5ec: 7cfb ldrb r3, [r7, #19] + 800a5ee: 74bb strb r3, [r7, #18] + } - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - 80097ac: 4b21 ldr r3, [pc, #132] ; (8009834 ) - 80097ae: 681b ldr r3, [r3, #0] - 80097b0: f003 0307 and.w r3, r3, #7 - 80097b4: 683a ldr r2, [r7, #0] - 80097b6: 429a cmp r2, r3 - 80097b8: d001 beq.n 80097be + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + 800a5f0: 7c7b ldrb r3, [r7, #17] + 800a5f2: 2b01 cmp r3, #1 + 800a5f4: d105 bne.n 800a602 { - return HAL_ERROR; - 80097ba: 2301 movs r3, #1 - 80097bc: e036 b.n 800982c + __HAL_RCC_PWR_CLK_DISABLE(); + 800a5f6: 4b8a ldr r3, [pc, #552] ; (800a820 ) + 800a5f8: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a5fa: 4a89 ldr r2, [pc, #548] ; (800a820 ) + 800a5fc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800a600: 6593 str r3, [r2, #88] ; 0x58 } } - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80097be: 687b ldr r3, [r7, #4] - 80097c0: 681b ldr r3, [r3, #0] - 80097c2: f003 0304 and.w r3, r3, #4 - 80097c6: 2b00 cmp r3, #0 - 80097c8: d008 beq.n 80097dc + /*-------------------------- USART1 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 800a602: 687b ldr r3, [r7, #4] + 800a604: 681b ldr r3, [r3, #0] + 800a606: f003 0301 and.w r3, r3, #1 + 800a60a: 2b00 cmp r3, #0 + 800a60c: d00a beq.n 800a624 { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 80097ca: 4b1b ldr r3, [pc, #108] ; (8009838 ) - 80097cc: 689b ldr r3, [r3, #8] - 80097ce: f423 62e0 bic.w r2, r3, #1792 ; 0x700 - 80097d2: 687b ldr r3, [r7, #4] - 80097d4: 68db ldr r3, [r3, #12] - 80097d6: 4918 ldr r1, [pc, #96] ; (8009838 ) - 80097d8: 4313 orrs r3, r2 - 80097da: 608b str r3, [r1, #8] - } + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 80097dc: 687b ldr r3, [r7, #4] - 80097de: 681b ldr r3, [r3, #0] - 80097e0: f003 0308 and.w r3, r3, #8 - 80097e4: 2b00 cmp r3, #0 - 80097e6: d009 beq.n 80097fc - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 80097e8: 4b13 ldr r3, [pc, #76] ; (8009838 ) - 80097ea: 689b ldr r3, [r3, #8] - 80097ec: f423 5260 bic.w r2, r3, #14336 ; 0x3800 - 80097f0: 687b ldr r3, [r7, #4] - 80097f2: 691b ldr r3, [r3, #16] - 80097f4: 00db lsls r3, r3, #3 - 80097f6: 4910 ldr r1, [pc, #64] ; (8009838 ) - 80097f8: 4313 orrs r3, r2 - 80097fa: 608b str r3, [r1, #8] + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 800a60e: 4b84 ldr r3, [pc, #528] ; (800a820 ) + 800a610: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a614: f023 0203 bic.w r2, r3, #3 + 800a618: 687b ldr r3, [r7, #4] + 800a61a: 6a1b ldr r3, [r3, #32] + 800a61c: 4980 ldr r1, [pc, #512] ; (800a820 ) + 800a61e: 4313 orrs r3, r2 + 800a620: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); - 80097fc: f000 f824 bl 8009848 - 8009800: 4602 mov r2, r0 - 8009802: 4b0d ldr r3, [pc, #52] ; (8009838 ) - 8009804: 689b ldr r3, [r3, #8] - 8009806: 091b lsrs r3, r3, #4 - 8009808: f003 030f and.w r3, r3, #15 - 800980c: 490b ldr r1, [pc, #44] ; (800983c ) - 800980e: 5ccb ldrb r3, [r1, r3] - 8009810: f003 031f and.w r3, r3, #31 - 8009814: fa22 f303 lsr.w r3, r2, r3 - 8009818: 4a09 ldr r2, [pc, #36] ; (8009840 ) - 800981a: 6013 str r3, [r2, #0] - - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - 800981c: 4b09 ldr r3, [pc, #36] ; (8009844 ) - 800981e: 681b ldr r3, [r3, #0] - 8009820: 4618 mov r0, r3 - 8009822: f7fa fe7b bl 800451c - 8009826: 4603 mov r3, r0 - 8009828: 72fb strb r3, [r7, #11] + /*-------------------------- USART2 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 800a624: 687b ldr r3, [r7, #4] + 800a626: 681b ldr r3, [r3, #0] + 800a628: f003 0302 and.w r3, r3, #2 + 800a62c: 2b00 cmp r3, #0 + 800a62e: d00a beq.n 800a646 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - return status; - 800982a: 7afb ldrb r3, [r7, #11] -} - 800982c: 4618 mov r0, r3 - 800982e: 3710 adds r7, #16 - 8009830: 46bd mov sp, r7 - 8009832: bd80 pop {r7, pc} - 8009834: 40022000 .word 0x40022000 - 8009838: 40021000 .word 0x40021000 - 800983c: 080186cc .word 0x080186cc - 8009840: 20000020 .word 0x20000020 - 8009844: 20000024 .word 0x20000024 - -08009848 : - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - 8009848: b480 push {r7} - 800984a: b089 sub sp, #36 ; 0x24 - 800984c: af00 add r7, sp, #0 - uint32_t msirange = 0U, sysclockfreq = 0U; - 800984e: 2300 movs r3, #0 - 8009850: 61fb str r3, [r7, #28] - 8009852: 2300 movs r3, #0 - 8009854: 61bb str r3, [r7, #24] - uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */ - uint32_t sysclk_source, pll_oscsource; + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 800a630: 4b7b ldr r3, [pc, #492] ; (800a820 ) + 800a632: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a636: f023 020c bic.w r2, r3, #12 + 800a63a: 687b ldr r3, [r7, #4] + 800a63c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a63e: 4978 ldr r1, [pc, #480] ; (800a820 ) + 800a640: 4313 orrs r3, r2 + 800a642: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8009856: 4b3e ldr r3, [pc, #248] ; (8009950 ) - 8009858: 689b ldr r3, [r3, #8] - 800985a: f003 030c and.w r3, r3, #12 - 800985e: 613b str r3, [r7, #16] - pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8009860: 4b3b ldr r3, [pc, #236] ; (8009950 ) - 8009862: 68db ldr r3, [r3, #12] - 8009864: f003 0303 and.w r3, r3, #3 - 8009868: 60fb str r3, [r7, #12] +#endif /* UART5 */ - if((sysclk_source == RCC_CFGR_SWS_MSI) || - 800986a: 693b ldr r3, [r7, #16] - 800986c: 2b00 cmp r3, #0 - 800986e: d005 beq.n 800987c - 8009870: 693b ldr r3, [r7, #16] - 8009872: 2b0c cmp r3, #12 - 8009874: d121 bne.n 80098ba - ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI))) - 8009876: 68fb ldr r3, [r7, #12] - 8009878: 2b01 cmp r3, #1 - 800987a: d11e bne.n 80098ba + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 800a646: 687b ldr r3, [r7, #4] + 800a648: 681b ldr r3, [r3, #0] + 800a64a: f003 0320 and.w r3, r3, #32 + 800a64e: 2b00 cmp r3, #0 + 800a650: d00a beq.n 800a668 { - /* MSI or PLL with MSI source used as system clock source */ - - /* Get SYSCLK source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U) - 800987c: 4b34 ldr r3, [pc, #208] ; (8009950 ) - 800987e: 681b ldr r3, [r3, #0] - 8009880: f003 0308 and.w r3, r3, #8 - 8009884: 2b00 cmp r3, #0 - 8009886: d107 bne.n 8009898 - { /* MSISRANGE from RCC_CSR applies */ - msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; - 8009888: 4b31 ldr r3, [pc, #196] ; (8009950 ) - 800988a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 800988e: 0a1b lsrs r3, r3, #8 - 8009890: f003 030f and.w r3, r3, #15 - 8009894: 61fb str r3, [r7, #28] - 8009896: e005 b.n 80098a4 - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; - 8009898: 4b2d ldr r3, [pc, #180] ; (8009950 ) - 800989a: 681b ldr r3, [r3, #0] - 800989c: 091b lsrs r3, r3, #4 - 800989e: f003 030f and.w r3, r3, #15 - 80098a2: 61fb str r3, [r7, #28] - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - 80098a4: 4a2b ldr r2, [pc, #172] ; (8009954 ) - 80098a6: 69fb ldr r3, [r7, #28] - 80098a8: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80098ac: 61fb str r3, [r7, #28] + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); - if(sysclk_source == RCC_CFGR_SWS_MSI) - 80098ae: 693b ldr r3, [r7, #16] - 80098b0: 2b00 cmp r3, #0 - 80098b2: d10d bne.n 80098d0 - { - /* MSI used as system clock source */ - sysclockfreq = msirange; - 80098b4: 69fb ldr r3, [r7, #28] - 80098b6: 61bb str r3, [r7, #24] - if(sysclk_source == RCC_CFGR_SWS_MSI) - 80098b8: e00a b.n 80098d0 - } + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 800a652: 4b73 ldr r3, [pc, #460] ; (800a820 ) + 800a654: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a658: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 800a65c: 687b ldr r3, [r7, #4] + 800a65e: 6a9b ldr r3, [r3, #40] ; 0x28 + 800a660: 496f ldr r1, [pc, #444] ; (800a820 ) + 800a662: 4313 orrs r3, r2 + 800a664: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } - else if(sysclk_source == RCC_CFGR_SWS_HSI) - 80098ba: 693b ldr r3, [r7, #16] - 80098bc: 2b04 cmp r3, #4 - 80098be: d102 bne.n 80098c6 + + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 800a668: 687b ldr r3, [r7, #4] + 800a66a: 681b ldr r3, [r3, #0] + 800a66c: f403 7300 and.w r3, r3, #512 ; 0x200 + 800a670: 2b00 cmp r3, #0 + 800a672: d00a beq.n 800a68a { - /* HSI used as system clock source */ - sysclockfreq = HSI_VALUE; - 80098c0: 4b25 ldr r3, [pc, #148] ; (8009958 ) - 80098c2: 61bb str r3, [r7, #24] - 80098c4: e004 b.n 80098d0 + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 800a674: 4b6a ldr r3, [pc, #424] ; (800a820 ) + 800a676: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a67a: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 800a67e: 687b ldr r3, [r7, #4] + 800a680: 6b5b ldr r3, [r3, #52] ; 0x34 + 800a682: 4967 ldr r1, [pc, #412] ; (800a820 ) + 800a684: 4313 orrs r3, r2 + 800a686: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } - else if(sysclk_source == RCC_CFGR_SWS_HSE) - 80098c6: 693b ldr r3, [r7, #16] - 80098c8: 2b08 cmp r3, #8 - 80098ca: d101 bne.n 80098d0 + + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 800a68a: 687b ldr r3, [r7, #4] + 800a68c: 681b ldr r3, [r3, #0] + 800a68e: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800a692: 2b00 cmp r3, #0 + 800a694: d00a beq.n 800a6ac { - /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - 80098cc: 4b23 ldr r3, [pc, #140] ; (800995c ) - 80098ce: 61bb str r3, [r7, #24] - else + assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 800a696: 4b62 ldr r3, [pc, #392] ; (800a820 ) + 800a698: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a69c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 800a6a0: 687b ldr r3, [r7, #4] + 800a6a2: 6b9b ldr r3, [r3, #56] ; 0x38 + 800a6a4: 495e ldr r1, [pc, #376] ; (800a820 ) + 800a6a6: 4313 orrs r3, r2 + 800a6a8: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 800a6ac: 687b ldr r3, [r7, #4] + 800a6ae: 681b ldr r3, [r3, #0] + 800a6b0: f003 0340 and.w r3, r3, #64 ; 0x40 + 800a6b4: 2b00 cmp r3, #0 + 800a6b6: d00a beq.n 800a6ce { - /* unexpected case: sysclockfreq at 0 */ + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 800a6b8: 4b59 ldr r3, [pc, #356] ; (800a820 ) + 800a6ba: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a6be: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 800a6c2: 687b ldr r3, [r7, #4] + 800a6c4: 6adb ldr r3, [r3, #44] ; 0x2c + 800a6c6: 4956 ldr r1, [pc, #344] ; (800a820 ) + 800a6c8: 4313 orrs r3, r2 + 800a6ca: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } - if(sysclk_source == RCC_CFGR_SWS_PLL) - 80098d0: 693b ldr r3, [r7, #16] - 80098d2: 2b0c cmp r3, #12 - 80098d4: d134 bne.n 8009940 - /* PLL used as system clock source */ +#endif /* I2C2 */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM - SYSCLK = PLL_VCO / PLLR - */ - pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - 80098d6: 4b1e ldr r3, [pc, #120] ; (8009950 ) - 80098d8: 68db ldr r3, [r3, #12] - 80098da: f003 0303 and.w r3, r3, #3 - 80098de: 60bb str r3, [r7, #8] + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 800a6ce: 687b ldr r3, [r7, #4] + 800a6d0: 681b ldr r3, [r3, #0] + 800a6d2: f403 7380 and.w r3, r3, #256 ; 0x100 + 800a6d6: 2b00 cmp r3, #0 + 800a6d8: d00a beq.n 800a6f0 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - switch (pllsource) - 80098e0: 68bb ldr r3, [r7, #8] - 80098e2: 2b02 cmp r3, #2 - 80098e4: d003 beq.n 80098ee - 80098e6: 68bb ldr r3, [r7, #8] - 80098e8: 2b03 cmp r3, #3 - 80098ea: d003 beq.n 80098f4 - 80098ec: e005 b.n 80098fa - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = HSI_VALUE; - 80098ee: 4b1a ldr r3, [pc, #104] ; (8009958 ) - 80098f0: 617b str r3, [r7, #20] - break; - 80098f2: e005 b.n 8009900 + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 800a6da: 4b51 ldr r3, [pc, #324] ; (800a820 ) + 800a6dc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a6e0: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 800a6e4: 687b ldr r3, [r7, #4] + 800a6e6: 6b1b ldr r3, [r3, #48] ; 0x30 + 800a6e8: 494d ldr r1, [pc, #308] ; (800a820 ) + 800a6ea: 4313 orrs r3, r2 + 800a6ec: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +#endif /* I2C4 */ - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = HSE_VALUE; - 80098f4: 4b19 ldr r3, [pc, #100] ; (800995c ) - 80098f6: 617b str r3, [r7, #20] - break; - 80098f8: e002 b.n 8009900 +#if defined(USB_OTG_FS) || defined(USB) - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = msirange; - 80098fa: 69fb ldr r3, [r7, #28] - 80098fc: 617b str r3, [r7, #20] - break; - 80098fe: bf00 nop + /*-------------------------- USB clock source configuration ----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) + 800a6f0: 687b ldr r3, [r7, #4] + 800a6f2: 681b ldr r3, [r3, #0] + 800a6f4: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 800a6f8: 2b00 cmp r3, #0 + 800a6fa: d028 beq.n 800a74e + { + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 800a6fc: 4b48 ldr r3, [pc, #288] ; (800a820 ) + 800a6fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a702: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 + 800a706: 687b ldr r3, [r7, #4] + 800a708: 6c1b ldr r3, [r3, #64] ; 0x40 + 800a70a: 4945 ldr r1, [pc, #276] ; (800a820 ) + 800a70c: 4313 orrs r3, r2 + 800a70e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + 800a712: 687b ldr r3, [r7, #4] + 800a714: 6c1b ldr r3, [r3, #64] ; 0x40 + 800a716: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 800a71a: d106 bne.n 800a72a + { + /* Enable PLL48M1CLK output clock */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); + 800a71c: 4b40 ldr r3, [pc, #256] ; (800a820 ) + 800a71e: 68db ldr r3, [r3, #12] + 800a720: 4a3f ldr r2, [pc, #252] ; (800a820 ) + 800a722: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 800a726: 60d3 str r3, [r2, #12] + 800a728: e011 b.n 800a74e } - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - 8009900: 4b13 ldr r3, [pc, #76] ; (8009950 ) - 8009902: 68db ldr r3, [r3, #12] - 8009904: 091b lsrs r3, r3, #4 - 8009906: f003 0307 and.w r3, r3, #7 - 800990a: 3301 adds r3, #1 - 800990c: 607b str r3, [r7, #4] - pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm; - 800990e: 4b10 ldr r3, [pc, #64] ; (8009950 ) - 8009910: 68db ldr r3, [r3, #12] - 8009912: 0a1b lsrs r3, r3, #8 - 8009914: f003 037f and.w r3, r3, #127 ; 0x7f - 8009918: 697a ldr r2, [r7, #20] - 800991a: fb03 f202 mul.w r2, r3, r2 - 800991e: 687b ldr r3, [r7, #4] - 8009920: fbb2 f3f3 udiv r3, r2, r3 - 8009924: 617b str r3, [r7, #20] - pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - 8009926: 4b0a ldr r3, [pc, #40] ; (8009950 ) - 8009928: 68db ldr r3, [r3, #12] - 800992a: 0e5b lsrs r3, r3, #25 - 800992c: f003 0303 and.w r3, r3, #3 - 8009930: 3301 adds r3, #1 - 8009932: 005b lsls r3, r3, #1 - 8009934: 603b str r3, [r7, #0] - sysclockfreq = pllvco / pllr; - 8009936: 697a ldr r2, [r7, #20] - 8009938: 683b ldr r3, [r7, #0] - 800993a: fbb2 f3f3 udiv r3, r2, r3 - 800993e: 61bb str r3, [r7, #24] - } + else + { +#if defined(RCC_PLLSAI1_SUPPORT) + if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) + 800a72a: 687b ldr r3, [r7, #4] + 800a72c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800a72e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 + 800a732: d10c bne.n 800a74e + { + /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); + 800a734: 687b ldr r3, [r7, #4] + 800a736: 3304 adds r3, #4 + 800a738: 2101 movs r1, #1 + 800a73a: 4618 mov r0, r3 + 800a73c: f000 f872 bl 800a824 + 800a740: 4603 mov r3, r0 + 800a742: 74fb strb r3, [r7, #19] - return sysclockfreq; - 8009940: 69bb ldr r3, [r7, #24] -} - 8009942: 4618 mov r0, r3 - 8009944: 3724 adds r7, #36 ; 0x24 - 8009946: 46bd mov sp, r7 - 8009948: f85d 7b04 ldr.w r7, [sp], #4 - 800994c: 4770 bx lr - 800994e: bf00 nop - 8009950: 40021000 .word 0x40021000 - 8009954: 080186e4 .word 0x080186e4 - 8009958: 00f42400 .word 0x00f42400 - 800995c: 007a1200 .word 0x007a1200 - -08009960 : - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency in Hz - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - 8009960: b480 push {r7} - 8009962: af00 add r7, sp, #0 - return SystemCoreClock; - 8009964: 4b03 ldr r3, [pc, #12] ; (8009974 ) - 8009966: 681b ldr r3, [r3, #0] -} - 8009968: 4618 mov r0, r3 - 800996a: 46bd mov sp, r7 - 800996c: f85d 7b04 ldr.w r7, [sp], #4 - 8009970: 4770 bx lr - 8009972: bf00 nop - 8009974: 20000020 .word 0x20000020 + if(ret != HAL_OK) + 800a744: 7cfb ldrb r3, [r7, #19] + 800a746: 2b00 cmp r3, #0 + 800a748: d001 beq.n 800a74e + { + /* set overall return value */ + status = ret; + 800a74a: 7cfb ldrb r3, [r7, #19] + 800a74c: 74bb strb r3, [r7, #18] + } -08009978 : - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - 8009978: b580 push {r7, lr} - 800997a: af00 add r7, sp, #0 - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); - 800997c: f7ff fff0 bl 8009960 - 8009980: 4602 mov r2, r0 - 8009982: 4b06 ldr r3, [pc, #24] ; (800999c ) - 8009984: 689b ldr r3, [r3, #8] - 8009986: 0a1b lsrs r3, r3, #8 - 8009988: f003 0307 and.w r3, r3, #7 - 800998c: 4904 ldr r1, [pc, #16] ; (80099a0 ) - 800998e: 5ccb ldrb r3, [r1, r3] - 8009990: f003 031f and.w r3, r3, #31 - 8009994: fa22 f303 lsr.w r3, r2, r3 -} - 8009998: 4618 mov r0, r3 - 800999a: bd80 pop {r7, pc} - 800999c: 40021000 .word 0x40021000 - 80099a0: 080186dc .word 0x080186dc - -080099a4 : - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - 80099a4: b580 push {r7, lr} - 80099a6: af00 add r7, sp, #0 - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); - 80099a8: f7ff ffda bl 8009960 - 80099ac: 4602 mov r2, r0 - 80099ae: 4b06 ldr r3, [pc, #24] ; (80099c8 ) - 80099b0: 689b ldr r3, [r3, #8] - 80099b2: 0adb lsrs r3, r3, #11 - 80099b4: f003 0307 and.w r3, r3, #7 - 80099b8: 4904 ldr r1, [pc, #16] ; (80099cc ) - 80099ba: 5ccb ldrb r3, [r1, r3] - 80099bc: f003 031f and.w r3, r3, #31 - 80099c0: fa22 f303 lsr.w r3, r2, r3 -} - 80099c4: 4618 mov r0, r3 - 80099c6: bd80 pop {r7, pc} - 80099c8: 40021000 .word 0x40021000 - 80099cc: 080186dc .word 0x080186dc - -080099d0 : - voltage range. - * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 - * @retval HAL status - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) -{ - 80099d0: b580 push {r7, lr} - 80099d2: b086 sub sp, #24 - 80099d4: af00 add r7, sp, #0 - 80099d6: 6078 str r0, [r7, #4] - uint32_t vos; - uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - 80099d8: 2300 movs r3, #0 - 80099da: 613b str r3, [r7, #16] +#endif /* SDMMC1 */ - if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - 80099dc: 4b2a ldr r3, [pc, #168] ; (8009a88 ) - 80099de: 6d9b ldr r3, [r3, #88] ; 0x58 - 80099e0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80099e4: 2b00 cmp r3, #0 - 80099e6: d003 beq.n 80099f0 - { - vos = HAL_PWREx_GetVoltageRange(); - 80099e8: f7ff f9a6 bl 8008d38 - 80099ec: 6178 str r0, [r7, #20] - 80099ee: e014 b.n 8009a1a - } - else + /*-------------------------- RNG clock source configuration ----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 800a74e: 687b ldr r3, [r7, #4] + 800a750: 681b ldr r3, [r3, #0] + 800a752: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 800a756: 2b00 cmp r3, #0 + 800a758: d028 beq.n 800a7ac { - __HAL_RCC_PWR_CLK_ENABLE(); - 80099f0: 4b25 ldr r3, [pc, #148] ; (8009a88 ) - 80099f2: 6d9b ldr r3, [r3, #88] ; 0x58 - 80099f4: 4a24 ldr r2, [pc, #144] ; (8009a88 ) - 80099f6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 80099fa: 6593 str r3, [r2, #88] ; 0x58 - 80099fc: 4b22 ldr r3, [pc, #136] ; (8009a88 ) - 80099fe: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009a00: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8009a04: 60fb str r3, [r7, #12] - 8009a06: 68fb ldr r3, [r7, #12] - vos = HAL_PWREx_GetVoltageRange(); - 8009a08: f7ff f996 bl 8008d38 - 8009a0c: 6178 str r0, [r7, #20] - __HAL_RCC_PWR_CLK_DISABLE(); - 8009a0e: 4b1e ldr r3, [pc, #120] ; (8009a88 ) - 8009a10: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009a12: 4a1d ldr r2, [pc, #116] ; (8009a88 ) - 8009a14: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8009a18: 6593 str r3, [r2, #88] ; 0x58 - } + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 800a75a: 4b31 ldr r3, [pc, #196] ; (800a820 ) + 800a75c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a760: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 + 800a764: 687b ldr r3, [r7, #4] + 800a766: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a768: 492d ldr r1, [pc, #180] ; (800a820 ) + 800a76a: 4313 orrs r3, r2 + 800a76c: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) - 8009a1a: 697b ldr r3, [r7, #20] - 8009a1c: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8009a20: d10b bne.n 8009a3a - { - if(msirange > RCC_MSIRANGE_8) - 8009a22: 687b ldr r3, [r7, #4] - 8009a24: 2b80 cmp r3, #128 ; 0x80 - 8009a26: d919 bls.n 8009a5c + if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 800a770: 687b ldr r3, [r7, #4] + 800a772: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a774: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 800a778: d106 bne.n 800a788 { - /* MSI > 16Mhz */ - if(msirange > RCC_MSIRANGE_10) - 8009a28: 687b ldr r3, [r7, #4] - 8009a2a: 2ba0 cmp r3, #160 ; 0xa0 - 8009a2c: d902 bls.n 8009a34 - { - /* MSI 48Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - 8009a2e: 2302 movs r3, #2 - 8009a30: 613b str r3, [r7, #16] - 8009a32: e013 b.n 8009a5c - } - else - { - /* MSI 24Mhz or 32Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - 8009a34: 2301 movs r3, #1 - 8009a36: 613b str r3, [r7, #16] - 8009a38: e010 b.n 8009a5c - latency = FLASH_LATENCY_1; /* 1WS */ - } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ + /* Enable PLL48M1CLK output clock */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); + 800a77a: 4b29 ldr r3, [pc, #164] ; (800a820 ) + 800a77c: 68db ldr r3, [r3, #12] + 800a77e: 4a28 ldr r2, [pc, #160] ; (800a820 ) + 800a780: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 800a784: 60d3 str r3, [r2, #12] + 800a786: e011 b.n 800a7ac } -#else - if(msirange > RCC_MSIRANGE_8) - 8009a3a: 687b ldr r3, [r7, #4] - 8009a3c: 2b80 cmp r3, #128 ; 0x80 - 8009a3e: d902 bls.n 8009a46 +#if defined(RCC_PLLSAI1_SUPPORT) + else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) + 800a788: 687b ldr r3, [r7, #4] + 800a78a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a78c: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 + 800a790: d10c bne.n 800a7ac { - /* MSI > 16Mhz */ - latency = FLASH_LATENCY_3; /* 3WS */ - 8009a40: 2303 movs r3, #3 - 8009a42: 613b str r3, [r7, #16] - 8009a44: e00a b.n 8009a5c + /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); + 800a792: 687b ldr r3, [r7, #4] + 800a794: 3304 adds r3, #4 + 800a796: 2101 movs r1, #1 + 800a798: 4618 mov r0, r3 + 800a79a: f000 f843 bl 800a824 + 800a79e: 4603 mov r3, r0 + 800a7a0: 74fb strb r3, [r7, #19] + + if(ret != HAL_OK) + 800a7a2: 7cfb ldrb r3, [r7, #19] + 800a7a4: 2b00 cmp r3, #0 + 800a7a6: d001 beq.n 800a7ac + { + /* set overall return value */ + status = ret; + 800a7a8: 7cfb ldrb r3, [r7, #19] + 800a7aa: 74bb strb r3, [r7, #18] } - else + } + + /*-------------------------- ADC clock source configuration ----------------------*/ +#if !defined(STM32L412xx) && !defined(STM32L422xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 800a7ac: 687b ldr r3, [r7, #4] + 800a7ae: 681b ldr r3, [r3, #0] + 800a7b0: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800a7b4: 2b00 cmp r3, #0 + 800a7b6: d01c beq.n 800a7f2 + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 800a7b8: 4b19 ldr r3, [pc, #100] ; (800a820 ) + 800a7ba: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a7be: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 + 800a7c2: 687b ldr r3, [r7, #4] + 800a7c4: 6c9b ldr r3, [r3, #72] ; 0x48 + 800a7c6: 4916 ldr r1, [pc, #88] ; (800a820 ) + 800a7c8: 4313 orrs r3, r2 + 800a7ca: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + +#if defined(RCC_PLLSAI1_SUPPORT) + if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) + 800a7ce: 687b ldr r3, [r7, #4] + 800a7d0: 6c9b ldr r3, [r3, #72] ; 0x48 + 800a7d2: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 800a7d6: d10c bne.n 800a7f2 { - if(msirange == RCC_MSIRANGE_8) - 8009a46: 687b ldr r3, [r7, #4] - 8009a48: 2b80 cmp r3, #128 ; 0x80 - 8009a4a: d102 bne.n 8009a52 - { - /* MSI 16Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - 8009a4c: 2302 movs r3, #2 - 8009a4e: 613b str r3, [r7, #16] - 8009a50: e004 b.n 8009a5c - } - else if(msirange == RCC_MSIRANGE_7) - 8009a52: 687b ldr r3, [r7, #4] - 8009a54: 2b70 cmp r3, #112 ; 0x70 - 8009a56: d101 bne.n 8009a5c + /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ + ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); + 800a7d8: 687b ldr r3, [r7, #4] + 800a7da: 3304 adds r3, #4 + 800a7dc: 2102 movs r1, #2 + 800a7de: 4618 mov r0, r3 + 800a7e0: f000 f820 bl 800a824 + 800a7e4: 4603 mov r3, r0 + 800a7e6: 74fb strb r3, [r7, #19] + + if(ret != HAL_OK) + 800a7e8: 7cfb ldrb r3, [r7, #19] + 800a7ea: 2b00 cmp r3, #0 + 800a7ec: d001 beq.n 800a7f2 { - /* MSI 8Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - 8009a58: 2301 movs r3, #1 - 8009a5a: 613b str r3, [r7, #16] - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ - } -#endif - } + /* set overall return value */ + status = ret; + 800a7ee: 7cfb ldrb r3, [r7, #19] + 800a7f0: 74bb strb r3, [r7, #18] +#endif /* !STM32L412xx && !STM32L422xx */ - __HAL_FLASH_SET_LATENCY(latency); - 8009a5c: 4b0b ldr r3, [pc, #44] ; (8009a8c ) - 8009a5e: 681b ldr r3, [r3, #0] - 8009a60: f023 0207 bic.w r2, r3, #7 - 8009a64: 4909 ldr r1, [pc, #36] ; (8009a8c ) - 8009a66: 693b ldr r3, [r7, #16] - 8009a68: 4313 orrs r3, r2 - 8009a6a: 600b str r3, [r1, #0] +#if defined(SWPMI1) - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != latency) - 8009a6c: 4b07 ldr r3, [pc, #28] ; (8009a8c ) - 8009a6e: 681b ldr r3, [r3, #0] - 8009a70: f003 0307 and.w r3, r3, #7 - 8009a74: 693a ldr r2, [r7, #16] - 8009a76: 429a cmp r2, r3 - 8009a78: d001 beq.n 8009a7e + /*-------------------------- SWPMI1 clock source configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + 800a7f2: 687b ldr r3, [r7, #4] + 800a7f4: 681b ldr r3, [r3, #0] + 800a7f6: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 800a7fa: 2b00 cmp r3, #0 + 800a7fc: d00a beq.n 800a814 { - return HAL_ERROR; - 8009a7a: 2301 movs r3, #1 - 8009a7c: e000 b.n 8009a80 + /* Check the parameters */ + assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); + + /* Configure the SWPMI1 clock source */ + __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); + 800a7fe: 4b08 ldr r3, [pc, #32] ; (800a820 ) + 800a800: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800a804: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 + 800a808: 687b ldr r3, [r7, #4] + 800a80a: 6cdb ldr r3, [r3, #76] ; 0x4c + 800a80c: 4904 ldr r1, [pc, #16] ; (800a820 ) + 800a80e: 4313 orrs r3, r2 + 800a810: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } } - return HAL_OK; - 8009a7e: 2300 movs r3, #0 +#endif /* OCTOSPI1 || OCTOSPI2 */ + + return status; + 800a814: 7cbb ldrb r3, [r7, #18] } - 8009a80: 4618 mov r0, r3 - 8009a82: 3718 adds r7, #24 - 8009a84: 46bd mov sp, r7 - 8009a86: bd80 pop {r7, pc} - 8009a88: 40021000 .word 0x40021000 - 8009a8c: 40022000 .word 0x40022000 + 800a816: 4618 mov r0, r3 + 800a818: 3718 adds r7, #24 + 800a81a: 46bd mov sp, r7 + 800a81c: bd80 pop {r7, pc} + 800a81e: bf00 nop + 800a820: 40021000 .word 0x40021000 -08009a90 : - * the RTC clock source: in this case the access to Backup domain is enabled. +0800a824 : + * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) { - 8009a90: b580 push {r7, lr} - 8009a92: b086 sub sp, #24 - 8009a94: af00 add r7, sp, #0 - 8009a96: 6078 str r0, [r7, #4] - uint32_t tmpregister, tickstart; /* no init needed */ - HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - 8009a98: 2300 movs r3, #0 - 8009a9a: 74fb strb r3, [r7, #19] - HAL_StatusTypeDef status = HAL_OK; /* Final status */ - 8009a9c: 2300 movs r3, #0 - 8009a9e: 74bb strb r3, [r7, #18] - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - -#if defined(SAI1) + 800a824: b580 push {r7, lr} + 800a826: b084 sub sp, #16 + 800a828: af00 add r7, sp, #0 + 800a82a: 6078 str r0, [r7, #4] + 800a82c: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 800a82e: 2300 movs r3, #0 + 800a830: 73fb strb r3, [r7, #15] + assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); + assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); + assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - /*-------------------------- SAI1 clock source configuration ---------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) - 8009aa0: 687b ldr r3, [r7, #4] - 8009aa2: 681b ldr r3, [r3, #0] - 8009aa4: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8009aa8: 2b00 cmp r3, #0 - 8009aaa: d031 beq.n 8009b10 + /* Check that PLLSAI1 clock source and divider M can be applied */ + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) + 800a832: 4b74 ldr r3, [pc, #464] ; (800aa04 ) + 800a834: 68db ldr r3, [r3, #12] + 800a836: f003 0303 and.w r3, r3, #3 + 800a83a: 2b00 cmp r3, #0 + 800a83c: d018 beq.n 800a870 { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); - - switch(PeriphClkInit->Sai1ClockSelection) - 8009aac: 687b ldr r3, [r7, #4] - 8009aae: 6bdb ldr r3, [r3, #60] ; 0x3c - 8009ab0: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000 - 8009ab4: d01a beq.n 8009aec - 8009ab6: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000 - 8009aba: d814 bhi.n 8009ae6 - 8009abc: 2b00 cmp r3, #0 - 8009abe: d009 beq.n 8009ad4 - 8009ac0: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 - 8009ac4: d10f bne.n 8009ae6 - case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ - /* Enable SAI Clock output generated from System PLL . */ -#if defined(RCC_PLLSAI2_SUPPORT) - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); -#else - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); - 8009ac6: 4b5d ldr r3, [pc, #372] ; (8009c3c ) - 8009ac8: 68db ldr r3, [r3, #12] - 8009aca: 4a5c ldr r2, [pc, #368] ; (8009c3c ) - 8009acc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8009ad0: 60d3 str r3, [r2, #12] -#endif /* RCC_PLLSAI2_SUPPORT */ - /* SAI1 clock source config set later after clock selection check */ + /* PLL clock source and divider M already set, check that no request for change */ + if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) + 800a83e: 4b71 ldr r3, [pc, #452] ; (800aa04 ) + 800a840: 68db ldr r3, [r3, #12] + 800a842: f003 0203 and.w r2, r3, #3 + 800a846: 687b ldr r3, [r7, #4] + 800a848: 681b ldr r3, [r3, #0] + 800a84a: 429a cmp r2, r3 + 800a84c: d10d bne.n 800a86a + || + (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) + 800a84e: 687b ldr r3, [r7, #4] + 800a850: 681b ldr r3, [r3, #0] + || + 800a852: 2b00 cmp r3, #0 + 800a854: d009 beq.n 800a86a +#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + || + (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) + 800a856: 4b6b ldr r3, [pc, #428] ; (800aa04 ) + 800a858: 68db ldr r3, [r3, #12] + 800a85a: 091b lsrs r3, r3, #4 + 800a85c: f003 0307 and.w r3, r3, #7 + 800a860: 1c5a adds r2, r3, #1 + 800a862: 687b ldr r3, [r7, #4] + 800a864: 685b ldr r3, [r3, #4] + || + 800a866: 429a cmp r2, r3 + 800a868: d047 beq.n 800a8fa +#endif + ) + { + status = HAL_ERROR; + 800a86a: 2301 movs r3, #1 + 800a86c: 73fb strb r3, [r7, #15] + 800a86e: e044 b.n 800a8fa + } + } + else + { + /* Check PLLSAI1 clock source availability */ + switch(PllSai1->PLLSAI1Source) + 800a870: 687b ldr r3, [r7, #4] + 800a872: 681b ldr r3, [r3, #0] + 800a874: 2b03 cmp r3, #3 + 800a876: d018 beq.n 800a8aa + 800a878: 2b03 cmp r3, #3 + 800a87a: d825 bhi.n 800a8c8 + 800a87c: 2b01 cmp r3, #1 + 800a87e: d002 beq.n 800a886 + 800a880: 2b02 cmp r3, #2 + 800a882: d009 beq.n 800a898 + 800a884: e020 b.n 800a8c8 + { + case RCC_PLLSOURCE_MSI: + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) + 800a886: 4b5f ldr r3, [pc, #380] ; (800aa04 ) + 800a888: 681b ldr r3, [r3, #0] + 800a88a: f003 0302 and.w r3, r3, #2 + 800a88e: 2b00 cmp r3, #0 + 800a890: d11d bne.n 800a8ce + { + status = HAL_ERROR; + 800a892: 2301 movs r3, #1 + 800a894: 73fb strb r3, [r7, #15] + } break; - 8009ad2: e00c b.n 8009aee - - case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ - /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); - 8009ad4: 687b ldr r3, [r7, #4] - 8009ad6: 3304 adds r3, #4 - 8009ad8: 2100 movs r1, #0 - 8009ada: 4618 mov r0, r3 - 8009adc: f000 f9ce bl 8009e7c - 8009ae0: 4603 mov r3, r0 - 8009ae2: 74fb strb r3, [r7, #19] - /* SAI1 clock source config set later after clock selection check */ + 800a896: e01a b.n 800a8ce + case RCC_PLLSOURCE_HSI: + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) + 800a898: 4b5a ldr r3, [pc, #360] ; (800aa04 ) + 800a89a: 681b ldr r3, [r3, #0] + 800a89c: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800a8a0: 2b00 cmp r3, #0 + 800a8a2: d116 bne.n 800a8d2 + { + status = HAL_ERROR; + 800a8a4: 2301 movs r3, #1 + 800a8a6: 73fb strb r3, [r7, #15] + } break; - 8009ae4: e003 b.n 8009aee -#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* SAI1 clock source config set later after clock selection check */ + 800a8a8: e013 b.n 800a8d2 + case RCC_PLLSOURCE_HSE: + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) + 800a8aa: 4b56 ldr r3, [pc, #344] ; (800aa04 ) + 800a8ac: 681b ldr r3, [r3, #0] + 800a8ae: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800a8b2: 2b00 cmp r3, #0 + 800a8b4: d10f bne.n 800a8d6 + { + if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) + 800a8b6: 4b53 ldr r3, [pc, #332] ; (800aa04 ) + 800a8b8: 681b ldr r3, [r3, #0] + 800a8ba: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 800a8be: 2b00 cmp r3, #0 + 800a8c0: d109 bne.n 800a8d6 + { + status = HAL_ERROR; + 800a8c2: 2301 movs r3, #1 + 800a8c4: 73fb strb r3, [r7, #15] + } + } break; - + 800a8c6: e006 b.n 800a8d6 default: - ret = HAL_ERROR; - 8009ae6: 2301 movs r3, #1 - 8009ae8: 74fb strb r3, [r7, #19] + status = HAL_ERROR; + 800a8c8: 2301 movs r3, #1 + 800a8ca: 73fb strb r3, [r7, #15] + break; + 800a8cc: e004 b.n 800a8d8 + break; + 800a8ce: bf00 nop + 800a8d0: e002 b.n 800a8d8 break; - 8009aea: e000 b.n 8009aee + 800a8d2: bf00 nop + 800a8d4: e000 b.n 800a8d8 break; - 8009aec: bf00 nop + 800a8d6: bf00 nop } - if(ret == HAL_OK) - 8009aee: 7cfb ldrb r3, [r7, #19] - 8009af0: 2b00 cmp r3, #0 - 8009af2: d10b bne.n 8009b0c - { - /* Set the source of SAI1 clock*/ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - 8009af4: 4b51 ldr r3, [pc, #324] ; (8009c3c ) - 8009af6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009afa: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 - 8009afe: 687b ldr r3, [r7, #4] - 8009b00: 6bdb ldr r3, [r3, #60] ; 0x3c - 8009b02: 494e ldr r1, [pc, #312] ; (8009c3c ) - 8009b04: 4313 orrs r3, r2 - 8009b06: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - 8009b0a: e001 b.n 8009b10 - } - else - { - /* set overall return value */ - status = ret; - 8009b0c: 7cfb ldrb r3, [r7, #19] - 8009b0e: 74bb strb r3, [r7, #18] + if(status == HAL_OK) + 800a8d8: 7bfb ldrb r3, [r7, #15] + 800a8da: 2b00 cmp r3, #0 + 800a8dc: d10d bne.n 800a8fa +#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) + /* Set PLLSAI1 clock source */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); +#else + /* Set PLLSAI1 clock source and divider M */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); + 800a8de: 4b49 ldr r3, [pc, #292] ; (800aa04 ) + 800a8e0: 68db ldr r3, [r3, #12] + 800a8e2: f023 0273 bic.w r2, r3, #115 ; 0x73 + 800a8e6: 687b ldr r3, [r7, #4] + 800a8e8: 6819 ldr r1, [r3, #0] + 800a8ea: 687b ldr r3, [r7, #4] + 800a8ec: 685b ldr r3, [r3, #4] + 800a8ee: 3b01 subs r3, #1 + 800a8f0: 011b lsls r3, r3, #4 + 800a8f2: 430b orrs r3, r1 + 800a8f4: 4943 ldr r1, [pc, #268] ; (800aa04 ) + 800a8f6: 4313 orrs r3, r2 + 800a8f8: 60cb str r3, [r1, #12] +#endif } } -#endif /* SAI2 */ - /*-------------------------- RTC clock source configuration ----------------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 8009b10: 687b ldr r3, [r7, #4] - 8009b12: 681b ldr r3, [r3, #0] - 8009b14: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8009b18: 2b00 cmp r3, #0 - 8009b1a: f000 809e beq.w 8009c5a + if(status == HAL_OK) + 800a8fa: 7bfb ldrb r3, [r7, #15] + 800a8fc: 2b00 cmp r3, #0 + 800a8fe: d17c bne.n 800a9fa { - FlagStatus pwrclkchanged = RESET; - 8009b1e: 2300 movs r3, #0 - 8009b20: 747b strb r3, [r7, #17] - - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) - 8009b22: 4b46 ldr r3, [pc, #280] ; (8009c3c ) - 8009b24: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009b26: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8009b2a: 2b00 cmp r3, #0 - 8009b2c: d101 bne.n 8009b32 - 8009b2e: 2301 movs r3, #1 - 8009b30: e000 b.n 8009b34 - 8009b32: 2300 movs r3, #0 - 8009b34: 2b00 cmp r3, #0 - 8009b36: d00d beq.n 8009b54 - { - __HAL_RCC_PWR_CLK_ENABLE(); - 8009b38: 4b40 ldr r3, [pc, #256] ; (8009c3c ) - 8009b3a: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009b3c: 4a3f ldr r2, [pc, #252] ; (8009c3c ) - 8009b3e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8009b42: 6593 str r3, [r2, #88] ; 0x58 - 8009b44: 4b3d ldr r3, [pc, #244] ; (8009c3c ) - 8009b46: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009b48: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8009b4c: 60bb str r3, [r7, #8] - 8009b4e: 68bb ldr r3, [r7, #8] - pwrclkchanged = SET; - 8009b50: 2301 movs r3, #1 - 8009b52: 747b strb r3, [r7, #17] - } - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - 8009b54: 4b3a ldr r3, [pc, #232] ; (8009c40 ) - 8009b56: 681b ldr r3, [r3, #0] - 8009b58: 4a39 ldr r2, [pc, #228] ; (8009c40 ) - 8009b5a: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8009b5e: 6013 str r3, [r2, #0] + /* Disable the PLLSAI1 */ + __HAL_RCC_PLLSAI1_DISABLE(); + 800a900: 4b40 ldr r3, [pc, #256] ; (800aa04 ) + 800a902: 681b ldr r3, [r3, #0] + 800a904: 4a3f ldr r2, [pc, #252] ; (800aa04 ) + 800a906: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 800a90a: 6013 str r3, [r2, #0] - /* Wait for Backup domain Write protection disable */ + /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8009b60: f7fa fd2c bl 80045bc - 8009b64: 60f8 str r0, [r7, #12] + 800a90c: f7fa fca0 bl 8005250 + 800a910: 60b8 str r0, [r7, #8] - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) - 8009b66: e009 b.n 8009b7c + /* Wait till PLLSAI1 is ready to be updated */ + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) + 800a912: e009 b.n 800a928 { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8009b68: f7fa fd28 bl 80045bc - 8009b6c: 4602 mov r2, r0 - 8009b6e: 68fb ldr r3, [r7, #12] - 8009b70: 1ad3 subs r3, r2, r3 - 8009b72: 2b02 cmp r3, #2 - 8009b74: d902 bls.n 8009b7c + if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 800a914: f7fa fc9c bl 8005250 + 800a918: 4602 mov r2, r0 + 800a91a: 68bb ldr r3, [r7, #8] + 800a91c: 1ad3 subs r3, r2, r3 + 800a91e: 2b02 cmp r3, #2 + 800a920: d902 bls.n 800a928 { - ret = HAL_TIMEOUT; - 8009b76: 2303 movs r3, #3 - 8009b78: 74fb strb r3, [r7, #19] + status = HAL_TIMEOUT; + 800a922: 2303 movs r3, #3 + 800a924: 73fb strb r3, [r7, #15] break; - 8009b7a: e005 b.n 8009b88 - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U) - 8009b7c: 4b30 ldr r3, [pc, #192] ; (8009c40 ) - 8009b7e: 681b ldr r3, [r3, #0] - 8009b80: f403 7380 and.w r3, r3, #256 ; 0x100 - 8009b84: 2b00 cmp r3, #0 - 8009b86: d0ef beq.n 8009b68 + 800a926: e005 b.n 800a934 + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) + 800a928: 4b36 ldr r3, [pc, #216] ; (800aa04 ) + 800a92a: 681b ldr r3, [r3, #0] + 800a92c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800a930: 2b00 cmp r3, #0 + 800a932: d1ef bne.n 800a914 } } - if(ret == HAL_OK) - 8009b88: 7cfb ldrb r3, [r7, #19] - 8009b8a: 2b00 cmp r3, #0 - 8009b8c: d15a bne.n 8009c44 + if(status == HAL_OK) + 800a934: 7bfb ldrb r3, [r7, #15] + 800a936: 2b00 cmp r3, #0 + 800a938: d15f bne.n 800a9fa { - /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ - tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - 8009b8e: 4b2b ldr r3, [pc, #172] ; (8009c3c ) - 8009b90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009b94: f403 7340 and.w r3, r3, #768 ; 0x300 - 8009b98: 617b str r3, [r7, #20] + if(Divider == DIVIDER_P_UPDATE) + 800a93a: 683b ldr r3, [r7, #0] + 800a93c: 2b00 cmp r3, #0 + 800a93e: d110 bne.n 800a962 +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - 8009b9a: 697b ldr r3, [r7, #20] - 8009b9c: 2b00 cmp r3, #0 - 8009b9e: d01e beq.n 8009bde - 8009ba0: 687b ldr r3, [r7, #4] - 8009ba2: 6d1b ldr r3, [r3, #80] ; 0x50 - 8009ba4: 697a ldr r2, [r7, #20] - 8009ba6: 429a cmp r2, r3 - 8009ba8: d019 beq.n 8009bde - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - 8009baa: 4b24 ldr r3, [pc, #144] ; (8009c3c ) - 8009bac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009bb0: f423 7340 bic.w r3, r3, #768 ; 0x300 - 8009bb4: 617b str r3, [r7, #20] - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - 8009bb6: 4b21 ldr r3, [pc, #132] ; (8009c3c ) - 8009bb8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009bbc: 4a1f ldr r2, [pc, #124] ; (8009c3c ) - 8009bbe: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8009bc2: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - __HAL_RCC_BACKUPRESET_RELEASE(); - 8009bc6: 4b1d ldr r3, [pc, #116] ; (8009c3c ) - 8009bc8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009bcc: 4a1b ldr r2, [pc, #108] ; (8009c3c ) - 8009bce: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8009bd2: f8c2 3090 str.w r3, [r2, #144] ; 0x90 - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpregister; - 8009bd6: 4a19 ldr r2, [pc, #100] ; (8009c3c ) - 8009bd8: 697b ldr r3, [r7, #20] - 8009bda: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +#else + /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ +#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) + MODIFY_REG(RCC->PLLSAI1CFGR, + 800a940: 4b30 ldr r3, [pc, #192] ; (800aa04 ) + 800a942: 691b ldr r3, [r3, #16] + 800a944: f023 4378 bic.w r3, r3, #4160749568 ; 0xf8000000 + 800a948: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 + 800a94c: 687a ldr r2, [r7, #4] + 800a94e: 6892 ldr r2, [r2, #8] + 800a950: 0211 lsls r1, r2, #8 + 800a952: 687a ldr r2, [r7, #4] + 800a954: 68d2 ldr r2, [r2, #12] + 800a956: 06d2 lsls r2, r2, #27 + 800a958: 430a orrs r2, r1 + 800a95a: 492a ldr r1, [pc, #168] ; (800aa04 ) + 800a95c: 4313 orrs r3, r2 + 800a95e: 610b str r3, [r1, #16] + 800a960: e027 b.n 800a9b2 + ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); +#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ + } + else if(Divider == DIVIDER_Q_UPDATE) + 800a962: 683b ldr r3, [r7, #0] + 800a964: 2b01 cmp r3, #1 + 800a966: d112 bne.n 800a98e + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else + /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + 800a968: 4b26 ldr r3, [pc, #152] ; (800aa04 ) + 800a96a: 691b ldr r3, [r3, #16] + 800a96c: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000 + 800a970: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 + 800a974: 687a ldr r2, [r7, #4] + 800a976: 6892 ldr r2, [r2, #8] + 800a978: 0211 lsls r1, r2, #8 + 800a97a: 687a ldr r2, [r7, #4] + 800a97c: 6912 ldr r2, [r2, #16] + 800a97e: 0852 lsrs r2, r2, #1 + 800a980: 3a01 subs r2, #1 + 800a982: 0552 lsls r2, r2, #21 + 800a984: 430a orrs r2, r1 + 800a986: 491f ldr r1, [pc, #124] ; (800aa04 ) + 800a988: 4313 orrs r3, r2 + 800a98a: 610b str r3, [r1, #16] + 800a98c: e011 b.n 800a9b2 + (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | + ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); +#else + /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ + MODIFY_REG(RCC->PLLSAI1CFGR, + 800a98e: 4b1d ldr r3, [pc, #116] ; (800aa04 ) + 800a990: 691b ldr r3, [r3, #16] + 800a992: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000 + 800a996: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 + 800a99a: 687a ldr r2, [r7, #4] + 800a99c: 6892 ldr r2, [r2, #8] + 800a99e: 0211 lsls r1, r2, #8 + 800a9a0: 687a ldr r2, [r7, #4] + 800a9a2: 6952 ldr r2, [r2, #20] + 800a9a4: 0852 lsrs r2, r2, #1 + 800a9a6: 3a01 subs r2, #1 + 800a9a8: 0652 lsls r2, r2, #25 + 800a9aa: 430a orrs r2, r1 + 800a9ac: 4915 ldr r1, [pc, #84] ; (800aa04 ) + 800a9ae: 4313 orrs r3, r2 + 800a9b0: 610b str r3, [r1, #16] + (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); +#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ } - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) - 8009bde: 697b ldr r3, [r7, #20] - 8009be0: f003 0301 and.w r3, r3, #1 - 8009be4: 2b00 cmp r3, #0 - 8009be6: d016 beq.n 8009c16 - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009be8: f7fa fce8 bl 80045bc - 8009bec: 60f8 str r0, [r7, #12] + /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ + __HAL_RCC_PLLSAI1_ENABLE(); + 800a9b2: 4b14 ldr r3, [pc, #80] ; (800aa04 ) + 800a9b4: 681b ldr r3, [r3, #0] + 800a9b6: 4a13 ldr r2, [pc, #76] ; (800aa04 ) + 800a9b8: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 800a9bc: 6013 str r3, [r2, #0] - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 8009bee: e00b b.n 8009c08 - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8009bf0: f7fa fce4 bl 80045bc - 8009bf4: 4602 mov r2, r0 - 8009bf6: 68fb ldr r3, [r7, #12] - 8009bf8: 1ad3 subs r3, r2, r3 - 8009bfa: f241 3288 movw r2, #5000 ; 0x1388 - 8009bfe: 4293 cmp r3, r2 - 8009c00: d902 bls.n 8009c08 - { - ret = HAL_TIMEOUT; - 8009c02: 2303 movs r3, #3 - 8009c04: 74fb strb r3, [r7, #19] - break; - 8009c06: e006 b.n 8009c16 - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 8009c08: 4b0c ldr r3, [pc, #48] ; (8009c3c ) - 8009c0a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009c0e: f003 0302 and.w r3, r3, #2 - 8009c12: 2b00 cmp r3, #0 - 8009c14: d0ec beq.n 8009bf0 - } - } - } + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800a9be: f7fa fc47 bl 8005250 + 800a9c2: 60b8 str r0, [r7, #8] - if(ret == HAL_OK) - 8009c16: 7cfb ldrb r3, [r7, #19] - 8009c18: 2b00 cmp r3, #0 - 8009c1a: d10b bne.n 8009c34 - { - /* Apply new RTC clock source selection */ - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8009c1c: 4b07 ldr r3, [pc, #28] ; (8009c3c ) - 8009c1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8009c22: f423 7240 bic.w r2, r3, #768 ; 0x300 - 8009c26: 687b ldr r3, [r7, #4] - 8009c28: 6d1b ldr r3, [r3, #80] ; 0x50 - 8009c2a: 4904 ldr r1, [pc, #16] ; (8009c3c ) - 8009c2c: 4313 orrs r3, r2 - 8009c2e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 - 8009c32: e009 b.n 8009c48 - } - else + /* Wait till PLLSAI1 is ready */ + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + 800a9c4: e009 b.n 800a9da { - /* set overall return value */ - status = ret; - 8009c34: 7cfb ldrb r3, [r7, #19] - 8009c36: 74bb strb r3, [r7, #18] - 8009c38: e006 b.n 8009c48 - 8009c3a: bf00 nop - 8009c3c: 40021000 .word 0x40021000 - 8009c40: 40007000 .word 0x40007000 - } - } - else - { - /* set overall return value */ - status = ret; - 8009c44: 7cfb ldrb r3, [r7, #19] - 8009c46: 74bb strb r3, [r7, #18] - } + if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) + 800a9c6: f7fa fc43 bl 8005250 + 800a9ca: 4602 mov r2, r0 + 800a9cc: 68bb ldr r3, [r7, #8] + 800a9ce: 1ad3 subs r3, r2, r3 + 800a9d0: 2b02 cmp r3, #2 + 800a9d2: d902 bls.n 800a9da + { + status = HAL_TIMEOUT; + 800a9d4: 2303 movs r3, #3 + 800a9d6: 73fb strb r3, [r7, #15] + break; + 800a9d8: e005 b.n 800a9e6 + while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + 800a9da: 4b0a ldr r3, [pc, #40] ; (800aa04 ) + 800a9dc: 681b ldr r3, [r3, #0] + 800a9de: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800a9e2: 2b00 cmp r3, #0 + 800a9e4: d0ef beq.n 800a9c6 + } + } - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - 8009c48: 7c7b ldrb r3, [r7, #17] - 8009c4a: 2b01 cmp r3, #1 - 8009c4c: d105 bne.n 8009c5a - { - __HAL_RCC_PWR_CLK_DISABLE(); - 8009c4e: 4b8a ldr r3, [pc, #552] ; (8009e78 ) - 8009c50: 6d9b ldr r3, [r3, #88] ; 0x58 - 8009c52: 4a89 ldr r2, [pc, #548] ; (8009e78 ) - 8009c54: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8009c58: 6593 str r3, [r2, #88] ; 0x58 + if(status == HAL_OK) + 800a9e6: 7bfb ldrb r3, [r7, #15] + 800a9e8: 2b00 cmp r3, #0 + 800a9ea: d106 bne.n 800a9fa + { + /* Configure the PLLSAI1 Clock output(s) */ + __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); + 800a9ec: 4b05 ldr r3, [pc, #20] ; (800aa04 ) + 800a9ee: 691a ldr r2, [r3, #16] + 800a9f0: 687b ldr r3, [r7, #4] + 800a9f2: 699b ldr r3, [r3, #24] + 800a9f4: 4903 ldr r1, [pc, #12] ; (800aa04 ) + 800a9f6: 4313 orrs r3, r2 + 800a9f8: 610b str r3, [r1, #16] + } } } - /*-------------------------- USART1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8009c5a: 687b ldr r3, [r7, #4] - 8009c5c: 681b ldr r3, [r3, #0] - 8009c5e: f003 0301 and.w r3, r3, #1 - 8009c62: 2b00 cmp r3, #0 - 8009c64: d00a beq.n 8009c7c - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + return status; + 800a9fa: 7bfb ldrb r3, [r7, #15] +} + 800a9fc: 4618 mov r0, r3 + 800a9fe: 3710 adds r7, #16 + 800aa00: 46bd mov sp, r7 + 800aa02: bd80 pop {r7, pc} + 800aa04: 40021000 .word 0x40021000 - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8009c66: 4b84 ldr r3, [pc, #528] ; (8009e78 ) - 8009c68: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009c6c: f023 0203 bic.w r2, r3, #3 - 8009c70: 687b ldr r3, [r7, #4] - 8009c72: 6a1b ldr r3, [r3, #32] - 8009c74: 4980 ldr r1, [pc, #512] ; (8009e78 ) - 8009c76: 4313 orrs r3, r2 - 8009c78: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - } +0800aa08 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 800aa08: b580 push {r7, lr} + 800aa0a: b084 sub sp, #16 + 800aa0c: af00 add r7, sp, #0 + 800aa0e: 6078 str r0, [r7, #4] + uint32_t frxth; - /*-------------------------- USART2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 8009c7c: 687b ldr r3, [r7, #4] - 8009c7e: 681b ldr r3, [r3, #0] - 8009c80: f003 0302 and.w r3, r3, #2 - 8009c84: 2b00 cmp r3, #0 - 8009c86: d00a beq.n 8009c9e + /* Check the SPI handle allocation */ + if (hspi == NULL) + 800aa10: 687b ldr r3, [r7, #4] + 800aa12: 2b00 cmp r3, #0 + 800aa14: d101 bne.n 800aa1a { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8009c88: 4b7b ldr r3, [pc, #492] ; (8009e78 ) - 8009c8a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009c8e: f023 020c bic.w r2, r3, #12 - 8009c92: 687b ldr r3, [r7, #4] - 8009c94: 6a5b ldr r3, [r3, #36] ; 0x24 - 8009c96: 4978 ldr r1, [pc, #480] ; (8009e78 ) - 8009c98: 4313 orrs r3, r2 - 8009c9a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - } - -#endif /* UART5 */ - - /*-------------------------- LPUART1 clock source configuration ------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - 8009c9e: 687b ldr r3, [r7, #4] - 8009ca0: 681b ldr r3, [r3, #0] - 8009ca2: f003 0320 and.w r3, r3, #32 - 8009ca6: 2b00 cmp r3, #0 - 8009ca8: d00a beq.n 8009cc0 + return HAL_ERROR; + 800aa16: 2301 movs r3, #1 + 800aa18: e095 b.n 800ab46 + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 800aa1a: 687b ldr r3, [r7, #4] + 800aa1c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800aa1e: 2b00 cmp r3, #0 + 800aa20: d108 bne.n 800aa34 { - /* Check the parameters */ - assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); - - /* Configure the LPUART1 clock source */ - __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); - 8009caa: 4b73 ldr r3, [pc, #460] ; (8009e78 ) - 8009cac: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009cb0: f423 6240 bic.w r2, r3, #3072 ; 0xc00 - 8009cb4: 687b ldr r3, [r7, #4] - 8009cb6: 6a9b ldr r3, [r3, #40] ; 0x28 - 8009cb8: 496f ldr r1, [pc, #444] ; (8009e78 ) - 8009cba: 4313 orrs r3, r2 - 8009cbc: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - } + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - /*-------------------------- LPTIM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) - 8009cc0: 687b ldr r3, [r7, #4] - 8009cc2: 681b ldr r3, [r3, #0] - 8009cc4: f403 7300 and.w r3, r3, #512 ; 0x200 - 8009cc8: 2b00 cmp r3, #0 - 8009cca: d00a beq.n 8009ce2 + if (hspi->Init.Mode == SPI_MODE_MASTER) + 800aa22: 687b ldr r3, [r7, #4] + 800aa24: 685b ldr r3, [r3, #4] + 800aa26: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800aa2a: d009 beq.n 800aa40 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 800aa2c: 687b ldr r3, [r7, #4] + 800aa2e: 2200 movs r2, #0 + 800aa30: 61da str r2, [r3, #28] + 800aa32: e005 b.n 800aa40 + else { - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - 8009ccc: 4b6a ldr r3, [pc, #424] ; (8009e78 ) - 8009cce: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009cd2: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 - 8009cd6: 687b ldr r3, [r7, #4] - 8009cd8: 6b5b ldr r3, [r3, #52] ; 0x34 - 8009cda: 4967 ldr r1, [pc, #412] ; (8009e78 ) - 8009cdc: 4313 orrs r3, r2 - 8009cde: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - } + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - /*-------------------------- LPTIM2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) - 8009ce2: 687b ldr r3, [r7, #4] - 8009ce4: 681b ldr r3, [r3, #0] - 8009ce6: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8009cea: 2b00 cmp r3, #0 - 8009cec: d00a beq.n 8009d04 + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 800aa34: 687b ldr r3, [r7, #4] + 800aa36: 2200 movs r2, #0 + 800aa38: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 800aa3a: 687b ldr r3, [r7, #4] + 800aa3c: 2200 movs r2, #0 + 800aa3e: 615a str r2, [r3, #20] { - assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); - __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); - 8009cee: 4b62 ldr r3, [pc, #392] ; (8009e78 ) - 8009cf0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009cf4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 - 8009cf8: 687b ldr r3, [r7, #4] - 8009cfa: 6b9b ldr r3, [r3, #56] ; 0x38 - 8009cfc: 495e ldr r1, [pc, #376] ; (8009e78 ) - 8009cfe: 4313 orrs r3, r2 - 8009d00: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } - - /*-------------------------- I2C1 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 8009d04: 687b ldr r3, [r7, #4] - 8009d06: 681b ldr r3, [r3, #0] - 8009d08: f003 0340 and.w r3, r3, #64 ; 0x40 - 8009d0c: 2b00 cmp r3, #0 - 8009d0e: d00a beq.n 8009d26 +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 800aa40: 687b ldr r3, [r7, #4] + 800aa42: 2200 movs r2, #0 + 800aa44: 629a str r2, [r3, #40] ; 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 800aa46: 687b ldr r3, [r7, #4] + 800aa48: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 800aa4c: b2db uxtb r3, r3 + 800aa4e: 2b00 cmp r3, #0 + 800aa50: d106 bne.n 800aa60 { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 800aa52: 687b ldr r3, [r7, #4] + 800aa54: 2200 movs r2, #0 + 800aa56: f883 205c strb.w r2, [r3, #92] ; 0x5c - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 8009d10: 4b59 ldr r3, [pc, #356] ; (8009e78 ) - 8009d12: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009d16: f423 5240 bic.w r2, r3, #12288 ; 0x3000 - 8009d1a: 687b ldr r3, [r7, #4] - 8009d1c: 6adb ldr r3, [r3, #44] ; 0x2c - 8009d1e: 4956 ldr r1, [pc, #344] ; (8009e78 ) - 8009d20: 4313 orrs r3, r2 - 8009d22: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 800aa5a: 6878 ldr r0, [r7, #4] + 800aa5c: f7f7 fbd4 bl 8002208 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 800aa60: 687b ldr r3, [r7, #4] + 800aa62: 2202 movs r2, #2 + 800aa64: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800aa68: 687b ldr r3, [r7, #4] + 800aa6a: 681b ldr r3, [r3, #0] + 800aa6c: 681a ldr r2, [r3, #0] + 800aa6e: 687b ldr r3, [r7, #4] + 800aa70: 681b ldr r3, [r3, #0] + 800aa72: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800aa76: 601a str r2, [r3, #0] + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 800aa78: 687b ldr r3, [r7, #4] + 800aa7a: 68db ldr r3, [r3, #12] + 800aa7c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800aa80: d902 bls.n 800aa88 + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + 800aa82: 2300 movs r3, #0 + 800aa84: 60fb str r3, [r7, #12] + 800aa86: e002 b.n 800aa8e } - -#endif /* I2C2 */ - - /*-------------------------- I2C3 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - 8009d26: 687b ldr r3, [r7, #4] - 8009d28: 681b ldr r3, [r3, #0] - 8009d2a: f403 7380 and.w r3, r3, #256 ; 0x100 - 8009d2e: 2b00 cmp r3, #0 - 8009d30: d00a beq.n 8009d48 + else { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + frxth = SPI_RXFIFO_THRESHOLD_QF; + 800aa88: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800aa8c: 60fb str r3, [r7, #12] + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 800aa8e: 687b ldr r3, [r7, #4] + 800aa90: 68db ldr r3, [r3, #12] + 800aa92: f5b3 6f70 cmp.w r3, #3840 ; 0xf00 + 800aa96: d007 beq.n 800aaa8 + 800aa98: 687b ldr r3, [r7, #4] + 800aa9a: 68db ldr r3, [r3, #12] + 800aa9c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800aaa0: d002 beq.n 800aaa8 + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 800aaa2: 687b ldr r3, [r7, #4] + 800aaa4: 2200 movs r2, #0 + 800aaa6: 629a str r2, [r3, #40] ; 0x28 + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 800aaa8: 687b ldr r3, [r7, #4] + 800aaaa: 685b ldr r3, [r3, #4] + 800aaac: f403 7282 and.w r2, r3, #260 ; 0x104 + 800aab0: 687b ldr r3, [r7, #4] + 800aab2: 689b ldr r3, [r3, #8] + 800aab4: f403 4304 and.w r3, r3, #33792 ; 0x8400 + 800aab8: 431a orrs r2, r3 + 800aaba: 687b ldr r3, [r7, #4] + 800aabc: 691b ldr r3, [r3, #16] + 800aabe: f003 0302 and.w r3, r3, #2 + 800aac2: 431a orrs r2, r3 + 800aac4: 687b ldr r3, [r7, #4] + 800aac6: 695b ldr r3, [r3, #20] + 800aac8: f003 0301 and.w r3, r3, #1 + 800aacc: 431a orrs r2, r3 + 800aace: 687b ldr r3, [r7, #4] + 800aad0: 699b ldr r3, [r3, #24] + 800aad2: f403 7300 and.w r3, r3, #512 ; 0x200 + 800aad6: 431a orrs r2, r3 + 800aad8: 687b ldr r3, [r7, #4] + 800aada: 69db ldr r3, [r3, #28] + 800aadc: f003 0338 and.w r3, r3, #56 ; 0x38 + 800aae0: 431a orrs r2, r3 + 800aae2: 687b ldr r3, [r7, #4] + 800aae4: 6a1b ldr r3, [r3, #32] + 800aae6: f003 0380 and.w r3, r3, #128 ; 0x80 + 800aaea: ea42 0103 orr.w r1, r2, r3 + 800aaee: 687b ldr r3, [r7, #4] + 800aaf0: 6a9b ldr r3, [r3, #40] ; 0x28 + 800aaf2: f403 5200 and.w r2, r3, #8192 ; 0x2000 + 800aaf6: 687b ldr r3, [r7, #4] + 800aaf8: 681b ldr r3, [r3, #0] + 800aafa: 430a orrs r2, r1 + 800aafc: 601a str r2, [r3, #0] + } + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + 800aafe: 687b ldr r3, [r7, #4] + 800ab00: 699b ldr r3, [r3, #24] + 800ab02: 0c1b lsrs r3, r3, #16 + 800ab04: f003 0204 and.w r2, r3, #4 + 800ab08: 687b ldr r3, [r7, #4] + 800ab0a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800ab0c: f003 0310 and.w r3, r3, #16 + 800ab10: 431a orrs r2, r3 + 800ab12: 687b ldr r3, [r7, #4] + 800ab14: 6b5b ldr r3, [r3, #52] ; 0x34 + 800ab16: f003 0308 and.w r3, r3, #8 + 800ab1a: 431a orrs r2, r3 + 800ab1c: 687b ldr r3, [r7, #4] + 800ab1e: 68db ldr r3, [r3, #12] + 800ab20: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 800ab24: ea42 0103 orr.w r1, r2, r3 + 800ab28: 68fb ldr r3, [r7, #12] + 800ab2a: f403 5280 and.w r2, r3, #4096 ; 0x1000 + 800ab2e: 687b ldr r3, [r7, #4] + 800ab30: 681b ldr r3, [r3, #0] + 800ab32: 430a orrs r2, r1 + 800ab34: 605a str r2, [r3, #4] +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800ab36: 687b ldr r3, [r7, #4] + 800ab38: 2200 movs r2, #0 + 800ab3a: 661a str r2, [r3, #96] ; 0x60 + hspi->State = HAL_SPI_STATE_READY; + 800ab3c: 687b ldr r3, [r7, #4] + 800ab3e: 2201 movs r2, #1 + 800ab40: f883 205d strb.w r2, [r3, #93] ; 0x5d - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - 8009d32: 4b51 ldr r3, [pc, #324] ; (8009e78 ) - 8009d34: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009d38: f423 3240 bic.w r2, r3, #196608 ; 0x30000 - 8009d3c: 687b ldr r3, [r7, #4] - 8009d3e: 6b1b ldr r3, [r3, #48] ; 0x30 - 8009d40: 494d ldr r1, [pc, #308] ; (8009e78 ) - 8009d42: 4313 orrs r3, r2 - 8009d44: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -#endif /* I2C4 */ + return HAL_OK; + 800ab44: 2300 movs r3, #0 +} + 800ab46: 4618 mov r0, r3 + 800ab48: 3710 adds r7, #16 + 800ab4a: 46bd mov sp, r7 + 800ab4c: bd80 pop {r7, pc} -#if defined(USB_OTG_FS) || defined(USB) +0800ab4e : + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800ab4e: b580 push {r7, lr} + 800ab50: b088 sub sp, #32 + 800ab52: af00 add r7, sp, #0 + 800ab54: 60f8 str r0, [r7, #12] + 800ab56: 60b9 str r1, [r7, #8] + 800ab58: 603b str r3, [r7, #0] + 800ab5a: 4613 mov r3, r2 + 800ab5c: 80fb strh r3, [r7, #6] + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + 800ab5e: 2300 movs r3, #0 + 800ab60: 77fb strb r3, [r7, #31] - /*-------------------------- USB clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) - 8009d48: 687b ldr r3, [r7, #4] - 8009d4a: 681b ldr r3, [r3, #0] - 8009d4c: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8009d50: 2b00 cmp r3, #0 - 8009d52: d028 beq.n 8009da6 - { - assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - 8009d54: 4b48 ldr r3, [pc, #288] ; (8009e78 ) - 8009d56: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009d5a: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 - 8009d5e: 687b ldr r3, [r7, #4] - 8009d60: 6c1b ldr r3, [r3, #64] ; 0x40 - 8009d62: 4945 ldr r1, [pc, #276] ; (8009e78 ) - 8009d64: 4313 orrs r3, r2 - 8009d66: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) - 8009d6a: 687b ldr r3, [r7, #4] - 8009d6c: 6c1b ldr r3, [r3, #64] ; 0x40 - 8009d6e: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 8009d72: d106 bne.n 8009d82 + /* Process Locked */ + __HAL_LOCK(hspi); + 800ab62: 68fb ldr r3, [r7, #12] + 800ab64: f893 305c ldrb.w r3, [r3, #92] ; 0x5c + 800ab68: 2b01 cmp r3, #1 + 800ab6a: d101 bne.n 800ab70 + 800ab6c: 2302 movs r3, #2 + 800ab6e: e15f b.n 800ae30 + 800ab70: 68fb ldr r3, [r7, #12] + 800ab72: 2201 movs r2, #1 + 800ab74: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 800ab78: f7fa fb6a bl 8005250 + 800ab7c: 61b8 str r0, [r7, #24] + initial_TxXferCount = Size; + 800ab7e: 88fb ldrh r3, [r7, #6] + 800ab80: 82fb strh r3, [r7, #22] + + if (hspi->State != HAL_SPI_STATE_READY) + 800ab82: 68fb ldr r3, [r7, #12] + 800ab84: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 800ab88: b2db uxtb r3, r3 + 800ab8a: 2b01 cmp r3, #1 + 800ab8c: d002 beq.n 800ab94 + { + errorcode = HAL_BUSY; + 800ab8e: 2302 movs r3, #2 + 800ab90: 77fb strb r3, [r7, #31] + goto error; + 800ab92: e148 b.n 800ae26 + } + + if ((pData == NULL) || (Size == 0U)) + 800ab94: 68bb ldr r3, [r7, #8] + 800ab96: 2b00 cmp r3, #0 + 800ab98: d002 beq.n 800aba0 + 800ab9a: 88fb ldrh r3, [r7, #6] + 800ab9c: 2b00 cmp r3, #0 + 800ab9e: d102 bne.n 800aba6 + { + errorcode = HAL_ERROR; + 800aba0: 2301 movs r3, #1 + 800aba2: 77fb strb r3, [r7, #31] + goto error; + 800aba4: e13f b.n 800ae26 + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 800aba6: 68fb ldr r3, [r7, #12] + 800aba8: 2203 movs r2, #3 + 800abaa: f883 205d strb.w r2, [r3, #93] ; 0x5d + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800abae: 68fb ldr r3, [r7, #12] + 800abb0: 2200 movs r2, #0 + 800abb2: 661a str r2, [r3, #96] ; 0x60 + hspi->pTxBuffPtr = (uint8_t *)pData; + 800abb4: 68fb ldr r3, [r7, #12] + 800abb6: 68ba ldr r2, [r7, #8] + 800abb8: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferSize = Size; + 800abba: 68fb ldr r3, [r7, #12] + 800abbc: 88fa ldrh r2, [r7, #6] + 800abbe: 879a strh r2, [r3, #60] ; 0x3c + hspi->TxXferCount = Size; + 800abc0: 68fb ldr r3, [r7, #12] + 800abc2: 88fa ldrh r2, [r7, #6] + 800abc4: 87da strh r2, [r3, #62] ; 0x3e + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 800abc6: 68fb ldr r3, [r7, #12] + 800abc8: 2200 movs r2, #0 + 800abca: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferSize = 0U; + 800abcc: 68fb ldr r3, [r7, #12] + 800abce: 2200 movs r2, #0 + 800abd0: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + hspi->RxXferCount = 0U; + 800abd4: 68fb ldr r3, [r7, #12] + 800abd6: 2200 movs r2, #0 + 800abd8: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + hspi->TxISR = NULL; + 800abdc: 68fb ldr r3, [r7, #12] + 800abde: 2200 movs r2, #0 + 800abe0: 651a str r2, [r3, #80] ; 0x50 + hspi->RxISR = NULL; + 800abe2: 68fb ldr r3, [r7, #12] + 800abe4: 2200 movs r2, #0 + 800abe6: 64da str r2, [r3, #76] ; 0x4c + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800abe8: 68fb ldr r3, [r7, #12] + 800abea: 689b ldr r3, [r3, #8] + 800abec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800abf0: d10f bne.n 800ac12 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 800abf2: 68fb ldr r3, [r7, #12] + 800abf4: 681b ldr r3, [r3, #0] + 800abf6: 681a ldr r2, [r3, #0] + 800abf8: 68fb ldr r3, [r7, #12] + 800abfa: 681b ldr r3, [r3, #0] + 800abfc: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800ac00: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 800ac02: 68fb ldr r3, [r7, #12] + 800ac04: 681b ldr r3, [r3, #0] + 800ac06: 681a ldr r2, [r3, #0] + 800ac08: 68fb ldr r3, [r7, #12] + 800ac0a: 681b ldr r3, [r3, #0] + 800ac0c: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 800ac10: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 800ac12: 68fb ldr r3, [r7, #12] + 800ac14: 681b ldr r3, [r3, #0] + 800ac16: 681b ldr r3, [r3, #0] + 800ac18: f003 0340 and.w r3, r3, #64 ; 0x40 + 800ac1c: 2b40 cmp r3, #64 ; 0x40 + 800ac1e: d007 beq.n 800ac30 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 800ac20: 68fb ldr r3, [r7, #12] + 800ac22: 681b ldr r3, [r3, #0] + 800ac24: 681a ldr r2, [r3, #0] + 800ac26: 68fb ldr r3, [r7, #12] + 800ac28: 681b ldr r3, [r3, #0] + 800ac2a: f042 0240 orr.w r2, r2, #64 ; 0x40 + 800ac2e: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 800ac30: 68fb ldr r3, [r7, #12] + 800ac32: 68db ldr r3, [r3, #12] + 800ac34: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800ac38: d94f bls.n 800acda + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800ac3a: 68fb ldr r3, [r7, #12] + 800ac3c: 685b ldr r3, [r3, #4] + 800ac3e: 2b00 cmp r3, #0 + 800ac40: d002 beq.n 800ac48 + 800ac42: 8afb ldrh r3, [r7, #22] + 800ac44: 2b01 cmp r3, #1 + 800ac46: d142 bne.n 800acce { - /* Enable PLL48M1CLK output clock */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 8009d74: 4b40 ldr r3, [pc, #256] ; (8009e78 ) - 8009d76: 68db ldr r3, [r3, #12] - 8009d78: 4a3f ldr r2, [pc, #252] ; (8009e78 ) - 8009d7a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 - 8009d7e: 60d3 str r3, [r2, #12] - 8009d80: e011 b.n 8009da6 + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800ac48: 68fb ldr r3, [r7, #12] + 800ac4a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ac4c: 881a ldrh r2, [r3, #0] + 800ac4e: 68fb ldr r3, [r7, #12] + 800ac50: 681b ldr r3, [r3, #0] + 800ac52: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800ac54: 68fb ldr r3, [r7, #12] + 800ac56: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ac58: 1c9a adds r2, r3, #2 + 800ac5a: 68fb ldr r3, [r7, #12] + 800ac5c: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800ac5e: 68fb ldr r3, [r7, #12] + 800ac60: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ac62: b29b uxth r3, r3 + 800ac64: 3b01 subs r3, #1 + 800ac66: b29a uxth r2, r3 + 800ac68: 68fb ldr r3, [r7, #12] + 800ac6a: 87da strh r2, [r3, #62] ; 0x3e } - else + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 800ac6c: e02f b.n 800acce { -#if defined(RCC_PLLSAI1_SUPPORT) - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) - 8009d82: 687b ldr r3, [r7, #4] - 8009d84: 6c1b ldr r3, [r3, #64] ; 0x40 - 8009d86: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 - 8009d8a: d10c bne.n 8009da6 + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 800ac6e: 68fb ldr r3, [r7, #12] + 800ac70: 681b ldr r3, [r3, #0] + 800ac72: 689b ldr r3, [r3, #8] + 800ac74: f003 0302 and.w r3, r3, #2 + 800ac78: 2b02 cmp r3, #2 + 800ac7a: d112 bne.n 800aca2 { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - 8009d8c: 687b ldr r3, [r7, #4] - 8009d8e: 3304 adds r3, #4 - 8009d90: 2101 movs r1, #1 - 8009d92: 4618 mov r0, r3 - 8009d94: f000 f872 bl 8009e7c - 8009d98: 4603 mov r3, r0 - 8009d9a: 74fb strb r3, [r7, #19] - - if(ret != HAL_OK) - 8009d9c: 7cfb ldrb r3, [r7, #19] - 8009d9e: 2b00 cmp r3, #0 - 8009da0: d001 beq.n 8009da6 + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800ac7c: 68fb ldr r3, [r7, #12] + 800ac7e: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ac80: 881a ldrh r2, [r3, #0] + 800ac82: 68fb ldr r3, [r7, #12] + 800ac84: 681b ldr r3, [r3, #0] + 800ac86: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800ac88: 68fb ldr r3, [r7, #12] + 800ac8a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ac8c: 1c9a adds r2, r3, #2 + 800ac8e: 68fb ldr r3, [r7, #12] + 800ac90: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800ac92: 68fb ldr r3, [r7, #12] + 800ac94: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ac96: b29b uxth r3, r3 + 800ac98: 3b01 subs r3, #1 + 800ac9a: b29a uxth r2, r3 + 800ac9c: 68fb ldr r3, [r7, #12] + 800ac9e: 87da strh r2, [r3, #62] ; 0x3e + 800aca0: e015 b.n 800acce + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800aca2: f7fa fad5 bl 8005250 + 800aca6: 4602 mov r2, r0 + 800aca8: 69bb ldr r3, [r7, #24] + 800acaa: 1ad3 subs r3, r2, r3 + 800acac: 683a ldr r2, [r7, #0] + 800acae: 429a cmp r2, r3 + 800acb0: d803 bhi.n 800acba + 800acb2: 683b ldr r3, [r7, #0] + 800acb4: f1b3 3fff cmp.w r3, #4294967295 + 800acb8: d102 bne.n 800acc0 + 800acba: 683b ldr r3, [r7, #0] + 800acbc: 2b00 cmp r3, #0 + 800acbe: d106 bne.n 800acce { - /* set overall return value */ - status = ret; - 8009da2: 7cfb ldrb r3, [r7, #19] - 8009da4: 74bb strb r3, [r7, #18] + errorcode = HAL_TIMEOUT; + 800acc0: 2303 movs r3, #3 + 800acc2: 77fb strb r3, [r7, #31] + hspi->State = HAL_SPI_STATE_READY; + 800acc4: 68fb ldr r3, [r7, #12] + 800acc6: 2201 movs r2, #1 + 800acc8: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800accc: e0ab b.n 800ae26 + while (hspi->TxXferCount > 0U) + 800acce: 68fb ldr r3, [r7, #12] + 800acd0: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800acd2: b29b uxth r3, r3 + 800acd4: 2b00 cmp r3, #0 + 800acd6: d1ca bne.n 800ac6e + 800acd8: e080 b.n 800addc + } } - -#endif /* SDMMC1 */ - - /*-------------------------- RNG clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) - 8009da6: 687b ldr r3, [r7, #4] - 8009da8: 681b ldr r3, [r3, #0] - 8009daa: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 8009dae: 2b00 cmp r3, #0 - 8009db0: d028 beq.n 8009e04 + /* Transmit data in 8 Bit mode */ + else { - assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); - __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); - 8009db2: 4b31 ldr r3, [pc, #196] ; (8009e78 ) - 8009db4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009db8: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 - 8009dbc: 687b ldr r3, [r7, #4] - 8009dbe: 6c5b ldr r3, [r3, #68] ; 0x44 - 8009dc0: 492d ldr r1, [pc, #180] ; (8009e78 ) - 8009dc2: 4313 orrs r3, r2 - 8009dc4: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - - if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) - 8009dc8: 687b ldr r3, [r7, #4] - 8009dca: 6c5b ldr r3, [r3, #68] ; 0x44 - 8009dcc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 8009dd0: d106 bne.n 8009de0 + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800acda: 68fb ldr r3, [r7, #12] + 800acdc: 685b ldr r3, [r3, #4] + 800acde: 2b00 cmp r3, #0 + 800ace0: d002 beq.n 800ace8 + 800ace2: 8afb ldrh r3, [r7, #22] + 800ace4: 2b01 cmp r3, #1 + 800ace6: d174 bne.n 800add2 { - /* Enable PLL48M1CLK output clock */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 8009dd2: 4b29 ldr r3, [pc, #164] ; (8009e78 ) - 8009dd4: 68db ldr r3, [r3, #12] - 8009dd6: 4a28 ldr r2, [pc, #160] ; (8009e78 ) - 8009dd8: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 - 8009ddc: 60d3 str r3, [r2, #12] - 8009dde: e011 b.n 8009e04 + if (hspi->TxXferCount > 1U) + 800ace8: 68fb ldr r3, [r7, #12] + 800acea: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800acec: b29b uxth r3, r3 + 800acee: 2b01 cmp r3, #1 + 800acf0: d912 bls.n 800ad18 + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800acf2: 68fb ldr r3, [r7, #12] + 800acf4: 6b9b ldr r3, [r3, #56] ; 0x38 + 800acf6: 881a ldrh r2, [r3, #0] + 800acf8: 68fb ldr r3, [r7, #12] + 800acfa: 681b ldr r3, [r3, #0] + 800acfc: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800acfe: 68fb ldr r3, [r7, #12] + 800ad00: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ad02: 1c9a adds r2, r3, #2 + 800ad04: 68fb ldr r3, [r7, #12] + 800ad06: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 800ad08: 68fb ldr r3, [r7, #12] + 800ad0a: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ad0c: b29b uxth r3, r3 + 800ad0e: 3b02 subs r3, #2 + 800ad10: b29a uxth r2, r3 + 800ad12: 68fb ldr r3, [r7, #12] + 800ad14: 87da strh r2, [r3, #62] ; 0x3e + 800ad16: e05c b.n 800add2 + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 800ad18: 68fb ldr r3, [r7, #12] + 800ad1a: 6b9a ldr r2, [r3, #56] ; 0x38 + 800ad1c: 68fb ldr r3, [r7, #12] + 800ad1e: 681b ldr r3, [r3, #0] + 800ad20: 330c adds r3, #12 + 800ad22: 7812 ldrb r2, [r2, #0] + 800ad24: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr ++; + 800ad26: 68fb ldr r3, [r7, #12] + 800ad28: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ad2a: 1c5a adds r2, r3, #1 + 800ad2c: 68fb ldr r3, [r7, #12] + 800ad2e: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800ad30: 68fb ldr r3, [r7, #12] + 800ad32: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ad34: b29b uxth r3, r3 + 800ad36: 3b01 subs r3, #1 + 800ad38: b29a uxth r2, r3 + 800ad3a: 68fb ldr r3, [r7, #12] + 800ad3c: 87da strh r2, [r3, #62] ; 0x3e + } } -#if defined(RCC_PLLSAI1_SUPPORT) - else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) - 8009de0: 687b ldr r3, [r7, #4] - 8009de2: 6c5b ldr r3, [r3, #68] ; 0x44 - 8009de4: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 - 8009de8: d10c bne.n 8009e04 + while (hspi->TxXferCount > 0U) + 800ad3e: e048 b.n 800add2 { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - 8009dea: 687b ldr r3, [r7, #4] - 8009dec: 3304 adds r3, #4 - 8009dee: 2101 movs r1, #1 - 8009df0: 4618 mov r0, r3 - 8009df2: f000 f843 bl 8009e7c - 8009df6: 4603 mov r3, r0 - 8009df8: 74fb strb r3, [r7, #19] - - if(ret != HAL_OK) - 8009dfa: 7cfb ldrb r3, [r7, #19] - 8009dfc: 2b00 cmp r3, #0 - 8009dfe: d001 beq.n 8009e04 + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 800ad40: 68fb ldr r3, [r7, #12] + 800ad42: 681b ldr r3, [r3, #0] + 800ad44: 689b ldr r3, [r3, #8] + 800ad46: f003 0302 and.w r3, r3, #2 + 800ad4a: 2b02 cmp r3, #2 + 800ad4c: d12b bne.n 800ada6 { - /* set overall return value */ - status = ret; - 8009e00: 7cfb ldrb r3, [r7, #19] - 8009e02: 74bb strb r3, [r7, #18] - } + if (hspi->TxXferCount > 1U) + 800ad4e: 68fb ldr r3, [r7, #12] + 800ad50: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ad52: b29b uxth r3, r3 + 800ad54: 2b01 cmp r3, #1 + 800ad56: d912 bls.n 800ad7e + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800ad58: 68fb ldr r3, [r7, #12] + 800ad5a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ad5c: 881a ldrh r2, [r3, #0] + 800ad5e: 68fb ldr r3, [r7, #12] + 800ad60: 681b ldr r3, [r3, #0] + 800ad62: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800ad64: 68fb ldr r3, [r7, #12] + 800ad66: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ad68: 1c9a adds r2, r3, #2 + 800ad6a: 68fb ldr r3, [r7, #12] + 800ad6c: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 800ad6e: 68fb ldr r3, [r7, #12] + 800ad70: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ad72: b29b uxth r3, r3 + 800ad74: 3b02 subs r3, #2 + 800ad76: b29a uxth r2, r3 + 800ad78: 68fb ldr r3, [r7, #12] + 800ad7a: 87da strh r2, [r3, #62] ; 0x3e + 800ad7c: e029 b.n 800add2 + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 800ad7e: 68fb ldr r3, [r7, #12] + 800ad80: 6b9a ldr r2, [r3, #56] ; 0x38 + 800ad82: 68fb ldr r3, [r7, #12] + 800ad84: 681b ldr r3, [r3, #0] + 800ad86: 330c adds r3, #12 + 800ad88: 7812 ldrb r2, [r2, #0] + 800ad8a: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 800ad8c: 68fb ldr r3, [r7, #12] + 800ad8e: 6b9b ldr r3, [r3, #56] ; 0x38 + 800ad90: 1c5a adds r2, r3, #1 + 800ad92: 68fb ldr r3, [r7, #12] + 800ad94: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800ad96: 68fb ldr r3, [r7, #12] + 800ad98: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800ad9a: b29b uxth r3, r3 + 800ad9c: 3b01 subs r3, #1 + 800ad9e: b29a uxth r2, r3 + 800ada0: 68fb ldr r3, [r7, #12] + 800ada2: 87da strh r2, [r3, #62] ; 0x3e + 800ada4: e015 b.n 800add2 + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800ada6: f7fa fa53 bl 8005250 + 800adaa: 4602 mov r2, r0 + 800adac: 69bb ldr r3, [r7, #24] + 800adae: 1ad3 subs r3, r2, r3 + 800adb0: 683a ldr r2, [r7, #0] + 800adb2: 429a cmp r2, r3 + 800adb4: d803 bhi.n 800adbe + 800adb6: 683b ldr r3, [r7, #0] + 800adb8: f1b3 3fff cmp.w r3, #4294967295 + 800adbc: d102 bne.n 800adc4 + 800adbe: 683b ldr r3, [r7, #0] + 800adc0: 2b00 cmp r3, #0 + 800adc2: d106 bne.n 800add2 + { + errorcode = HAL_TIMEOUT; + 800adc4: 2303 movs r3, #3 + 800adc6: 77fb strb r3, [r7, #31] + hspi->State = HAL_SPI_STATE_READY; + 800adc8: 68fb ldr r3, [r7, #12] + 800adca: 2201 movs r2, #1 + 800adcc: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800add0: e029 b.n 800ae26 + while (hspi->TxXferCount > 0U) + 800add2: 68fb ldr r3, [r7, #12] + 800add4: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800add6: b29b uxth r3, r3 + 800add8: 2b00 cmp r3, #0 + 800adda: d1b1 bne.n 800ad40 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 800addc: 69ba ldr r2, [r7, #24] + 800adde: 6839 ldr r1, [r7, #0] + 800ade0: 68f8 ldr r0, [r7, #12] + 800ade2: f000 fcf9 bl 800b7d8 + 800ade6: 4603 mov r3, r0 + 800ade8: 2b00 cmp r3, #0 + 800adea: d002 beq.n 800adf2 + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 800adec: 68fb ldr r3, [r7, #12] + 800adee: 2220 movs r2, #32 + 800adf0: 661a str r2, [r3, #96] ; 0x60 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 800adf2: 68fb ldr r3, [r7, #12] + 800adf4: 689b ldr r3, [r3, #8] + 800adf6: 2b00 cmp r3, #0 + 800adf8: d10a bne.n 800ae10 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 800adfa: 2300 movs r3, #0 + 800adfc: 613b str r3, [r7, #16] + 800adfe: 68fb ldr r3, [r7, #12] + 800ae00: 681b ldr r3, [r3, #0] + 800ae02: 68db ldr r3, [r3, #12] + 800ae04: 613b str r3, [r7, #16] + 800ae06: 68fb ldr r3, [r7, #12] + 800ae08: 681b ldr r3, [r3, #0] + 800ae0a: 689b ldr r3, [r3, #8] + 800ae0c: 613b str r3, [r7, #16] + 800ae0e: 693b ldr r3, [r7, #16] + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 800ae10: 68fb ldr r3, [r7, #12] + 800ae12: 6e1b ldr r3, [r3, #96] ; 0x60 + 800ae14: 2b00 cmp r3, #0 + 800ae16: d002 beq.n 800ae1e + { + errorcode = HAL_ERROR; + 800ae18: 2301 movs r3, #1 + 800ae1a: 77fb strb r3, [r7, #31] + 800ae1c: e003 b.n 800ae26 } - - /*-------------------------- ADC clock source configuration ----------------------*/ -#if !defined(STM32L412xx) && !defined(STM32L422xx) - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - 8009e04: 687b ldr r3, [r7, #4] - 8009e06: 681b ldr r3, [r3, #0] - 8009e08: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8009e0c: 2b00 cmp r3, #0 - 8009e0e: d01c beq.n 8009e4a + else { - /* Check the parameters */ - assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); - - /* Configure the ADC interface clock source */ - __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - 8009e10: 4b19 ldr r3, [pc, #100] ; (8009e78 ) - 8009e12: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009e16: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 - 8009e1a: 687b ldr r3, [r7, #4] - 8009e1c: 6c9b ldr r3, [r3, #72] ; 0x48 - 8009e1e: 4916 ldr r1, [pc, #88] ; (8009e78 ) - 8009e20: 4313 orrs r3, r2 - 8009e22: f8c1 3088 str.w r3, [r1, #136] ; 0x88 - -#if defined(RCC_PLLSAI1_SUPPORT) - if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) - 8009e26: 687b ldr r3, [r7, #4] - 8009e28: 6c9b ldr r3, [r3, #72] ; 0x48 - 8009e2a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 - 8009e2e: d10c bne.n 8009e4a - { - /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); - 8009e30: 687b ldr r3, [r7, #4] - 8009e32: 3304 adds r3, #4 - 8009e34: 2102 movs r1, #2 - 8009e36: 4618 mov r0, r3 - 8009e38: f000 f820 bl 8009e7c - 8009e3c: 4603 mov r3, r0 - 8009e3e: 74fb strb r3, [r7, #19] + hspi->State = HAL_SPI_STATE_READY; + 800ae1e: 68fb ldr r3, [r7, #12] + 800ae20: 2201 movs r2, #1 + 800ae22: f883 205d strb.w r2, [r3, #93] ; 0x5d + } - if(ret != HAL_OK) - 8009e40: 7cfb ldrb r3, [r7, #19] - 8009e42: 2b00 cmp r3, #0 - 8009e44: d001 beq.n 8009e4a - { - /* set overall return value */ - status = ret; - 8009e46: 7cfb ldrb r3, [r7, #19] - 8009e48: 74bb strb r3, [r7, #18] -#endif /* !STM32L412xx && !STM32L422xx */ +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 800ae26: 68fb ldr r3, [r7, #12] + 800ae28: 2200 movs r2, #0 + 800ae2a: f883 205c strb.w r2, [r3, #92] ; 0x5c + return errorcode; + 800ae2e: 7ffb ldrb r3, [r7, #31] +} + 800ae30: 4618 mov r0, r3 + 800ae32: 3720 adds r7, #32 + 800ae34: 46bd mov sp, r7 + 800ae36: bd80 pop {r7, pc} -#if defined(SWPMI1) +0800ae38 : + * @param Size amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800ae38: b580 push {r7, lr} + 800ae3a: b088 sub sp, #32 + 800ae3c: af02 add r7, sp, #8 + 800ae3e: 60f8 str r0, [r7, #12] + 800ae40: 60b9 str r1, [r7, #8] + 800ae42: 603b str r3, [r7, #0] + 800ae44: 4613 mov r3, r2 + 800ae46: 80fb strh r3, [r7, #6] + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + 800ae48: 2300 movs r3, #0 + 800ae4a: 75fb strb r3, [r7, #23] + + if (hspi->State != HAL_SPI_STATE_READY) + 800ae4c: 68fb ldr r3, [r7, #12] + 800ae4e: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 800ae52: b2db uxtb r3, r3 + 800ae54: 2b01 cmp r3, #1 + 800ae56: d002 beq.n 800ae5e + { + errorcode = HAL_BUSY; + 800ae58: 2302 movs r3, #2 + 800ae5a: 75fb strb r3, [r7, #23] + goto error; + 800ae5c: e11a b.n 800b094 + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + 800ae5e: 68fb ldr r3, [r7, #12] + 800ae60: 685b ldr r3, [r3, #4] + 800ae62: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800ae66: d112 bne.n 800ae8e + 800ae68: 68fb ldr r3, [r7, #12] + 800ae6a: 689b ldr r3, [r3, #8] + 800ae6c: 2b00 cmp r3, #0 + 800ae6e: d10e bne.n 800ae8e + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + 800ae70: 68fb ldr r3, [r7, #12] + 800ae72: 2204 movs r2, #4 + 800ae74: f883 205d strb.w r2, [r3, #93] ; 0x5d + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + 800ae78: 88fa ldrh r2, [r7, #6] + 800ae7a: 683b ldr r3, [r7, #0] + 800ae7c: 9300 str r3, [sp, #0] + 800ae7e: 4613 mov r3, r2 + 800ae80: 68ba ldr r2, [r7, #8] + 800ae82: 68b9 ldr r1, [r7, #8] + 800ae84: 68f8 ldr r0, [r7, #12] + 800ae86: f000 f90e bl 800b0a6 + 800ae8a: 4603 mov r3, r0 + 800ae8c: e107 b.n 800b09e + } - /*-------------------------- SWPMI1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) - 8009e4a: 687b ldr r3, [r7, #4] - 8009e4c: 681b ldr r3, [r3, #0] - 8009e4e: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8009e52: 2b00 cmp r3, #0 - 8009e54: d00a beq.n 8009e6c + /* Process Locked */ + __HAL_LOCK(hspi); + 800ae8e: 68fb ldr r3, [r7, #12] + 800ae90: f893 305c ldrb.w r3, [r3, #92] ; 0x5c + 800ae94: 2b01 cmp r3, #1 + 800ae96: d101 bne.n 800ae9c + 800ae98: 2302 movs r3, #2 + 800ae9a: e100 b.n 800b09e + 800ae9c: 68fb ldr r3, [r7, #12] + 800ae9e: 2201 movs r2, #1 + 800aea0: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 800aea4: f7fa f9d4 bl 8005250 + 800aea8: 6138 str r0, [r7, #16] + + if ((pData == NULL) || (Size == 0U)) + 800aeaa: 68bb ldr r3, [r7, #8] + 800aeac: 2b00 cmp r3, #0 + 800aeae: d002 beq.n 800aeb6 + 800aeb0: 88fb ldrh r3, [r7, #6] + 800aeb2: 2b00 cmp r3, #0 + 800aeb4: d102 bne.n 800aebc + { + errorcode = HAL_ERROR; + 800aeb6: 2301 movs r3, #1 + 800aeb8: 75fb strb r3, [r7, #23] + goto error; + 800aeba: e0eb b.n 800b094 + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + 800aebc: 68fb ldr r3, [r7, #12] + 800aebe: 2204 movs r2, #4 + 800aec0: f883 205d strb.w r2, [r3, #93] ; 0x5d + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800aec4: 68fb ldr r3, [r7, #12] + 800aec6: 2200 movs r2, #0 + 800aec8: 661a str r2, [r3, #96] ; 0x60 + hspi->pRxBuffPtr = (uint8_t *)pData; + 800aeca: 68fb ldr r3, [r7, #12] + 800aecc: 68ba ldr r2, [r7, #8] + 800aece: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferSize = Size; + 800aed0: 68fb ldr r3, [r7, #12] + 800aed2: 88fa ldrh r2, [r7, #6] + 800aed4: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + hspi->RxXferCount = Size; + 800aed8: 68fb ldr r3, [r7, #12] + 800aeda: 88fa ldrh r2, [r7, #6] + 800aedc: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + 800aee0: 68fb ldr r3, [r7, #12] + 800aee2: 2200 movs r2, #0 + 800aee4: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferSize = 0U; + 800aee6: 68fb ldr r3, [r7, #12] + 800aee8: 2200 movs r2, #0 + 800aeea: 879a strh r2, [r3, #60] ; 0x3c + hspi->TxXferCount = 0U; + 800aeec: 68fb ldr r3, [r7, #12] + 800aeee: 2200 movs r2, #0 + 800aef0: 87da strh r2, [r3, #62] ; 0x3e + hspi->RxISR = NULL; + 800aef2: 68fb ldr r3, [r7, #12] + 800aef4: 2200 movs r2, #0 + 800aef6: 64da str r2, [r3, #76] ; 0x4c + hspi->TxISR = NULL; + 800aef8: 68fb ldr r3, [r7, #12] + 800aefa: 2200 movs r2, #0 + 800aefc: 651a str r2, [r3, #80] ; 0x50 + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 800aefe: 68fb ldr r3, [r7, #12] + 800af00: 68db ldr r3, [r3, #12] + 800af02: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800af06: d908 bls.n 800af1a + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 800af08: 68fb ldr r3, [r7, #12] + 800af0a: 681b ldr r3, [r3, #0] + 800af0c: 685a ldr r2, [r3, #4] + 800af0e: 68fb ldr r3, [r7, #12] + 800af10: 681b ldr r3, [r3, #0] + 800af12: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 800af16: 605a str r2, [r3, #4] + 800af18: e007 b.n 800af2a + } + else { - /* Check the parameters */ - assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); - - /* Configure the SWPMI1 clock source */ - __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); - 8009e56: 4b08 ldr r3, [pc, #32] ; (8009e78 ) - 8009e58: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8009e5c: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 - 8009e60: 687b ldr r3, [r7, #4] - 8009e62: 6cdb ldr r3, [r3, #76] ; 0x4c - 8009e64: 4904 ldr r1, [pc, #16] ; (8009e78 ) - 8009e66: 4313 orrs r3, r2 - 8009e68: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 800af1a: 68fb ldr r3, [r7, #12] + 800af1c: 681b ldr r3, [r3, #0] + 800af1e: 685a ldr r2, [r3, #4] + 800af20: 68fb ldr r3, [r7, #12] + 800af22: 681b ldr r3, [r3, #0] + 800af24: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 800af28: 605a str r2, [r3, #4] + } + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800af2a: 68fb ldr r3, [r7, #12] + 800af2c: 689b ldr r3, [r3, #8] + 800af2e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800af32: d10f bne.n 800af54 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 800af34: 68fb ldr r3, [r7, #12] + 800af36: 681b ldr r3, [r3, #0] + 800af38: 681a ldr r2, [r3, #0] + 800af3a: 68fb ldr r3, [r7, #12] + 800af3c: 681b ldr r3, [r3, #0] + 800af3e: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800af42: 601a str r2, [r3, #0] + SPI_1LINE_RX(hspi); + 800af44: 68fb ldr r3, [r7, #12] + 800af46: 681b ldr r3, [r3, #0] + 800af48: 681a ldr r2, [r3, #0] + 800af4a: 68fb ldr r3, [r7, #12] + 800af4c: 681b ldr r3, [r3, #0] + 800af4e: f422 4280 bic.w r2, r2, #16384 ; 0x4000 + 800af52: 601a str r2, [r3, #0] + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 800af54: 68fb ldr r3, [r7, #12] + 800af56: 681b ldr r3, [r3, #0] + 800af58: 681b ldr r3, [r3, #0] + 800af5a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800af5e: 2b40 cmp r3, #64 ; 0x40 + 800af60: d007 beq.n 800af72 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 800af62: 68fb ldr r3, [r7, #12] + 800af64: 681b ldr r3, [r3, #0] + 800af66: 681a ldr r2, [r3, #0] + 800af68: 68fb ldr r3, [r7, #12] + 800af6a: 681b ldr r3, [r3, #0] + 800af6c: f042 0240 orr.w r2, r2, #64 ; 0x40 + 800af70: 601a str r2, [r3, #0] + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + 800af72: 68fb ldr r3, [r7, #12] + 800af74: 68db ldr r3, [r3, #12] + 800af76: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800af7a: d86f bhi.n 800b05c + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + 800af7c: e034 b.n 800afe8 + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + 800af7e: 68fb ldr r3, [r7, #12] + 800af80: 681b ldr r3, [r3, #0] + 800af82: 689b ldr r3, [r3, #8] + 800af84: f003 0301 and.w r3, r3, #1 + 800af88: 2b01 cmp r3, #1 + 800af8a: d117 bne.n 800afbc + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + 800af8c: 68fb ldr r3, [r7, #12] + 800af8e: 681b ldr r3, [r3, #0] + 800af90: f103 020c add.w r2, r3, #12 + 800af94: 68fb ldr r3, [r7, #12] + 800af96: 6c1b ldr r3, [r3, #64] ; 0x40 + 800af98: 7812 ldrb r2, [r2, #0] + 800af9a: b2d2 uxtb r2, r2 + 800af9c: 701a strb r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint8_t); + 800af9e: 68fb ldr r3, [r7, #12] + 800afa0: 6c1b ldr r3, [r3, #64] ; 0x40 + 800afa2: 1c5a adds r2, r3, #1 + 800afa4: 68fb ldr r3, [r7, #12] + 800afa6: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 800afa8: 68fb ldr r3, [r7, #12] + 800afaa: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800afae: b29b uxth r3, r3 + 800afb0: 3b01 subs r3, #1 + 800afb2: b29a uxth r2, r3 + 800afb4: 68fb ldr r3, [r7, #12] + 800afb6: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + 800afba: e015 b.n 800afe8 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800afbc: f7fa f948 bl 8005250 + 800afc0: 4602 mov r2, r0 + 800afc2: 693b ldr r3, [r7, #16] + 800afc4: 1ad3 subs r3, r2, r3 + 800afc6: 683a ldr r2, [r7, #0] + 800afc8: 429a cmp r2, r3 + 800afca: d803 bhi.n 800afd4 + 800afcc: 683b ldr r3, [r7, #0] + 800afce: f1b3 3fff cmp.w r3, #4294967295 + 800afd2: d102 bne.n 800afda + 800afd4: 683b ldr r3, [r7, #0] + 800afd6: 2b00 cmp r3, #0 + 800afd8: d106 bne.n 800afe8 + { + errorcode = HAL_TIMEOUT; + 800afda: 2303 movs r3, #3 + 800afdc: 75fb strb r3, [r7, #23] + hspi->State = HAL_SPI_STATE_READY; + 800afde: 68fb ldr r3, [r7, #12] + 800afe0: 2201 movs r2, #1 + 800afe2: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800afe6: e055 b.n 800b094 + while (hspi->RxXferCount > 0U) + 800afe8: 68fb ldr r3, [r7, #12] + 800afea: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800afee: b29b uxth r3, r3 + 800aff0: 2b00 cmp r3, #0 + 800aff2: d1c4 bne.n 800af7e + 800aff4: e038 b.n 800b068 + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + 800aff6: 68fb ldr r3, [r7, #12] + 800aff8: 681b ldr r3, [r3, #0] + 800affa: 689b ldr r3, [r3, #8] + 800affc: f003 0301 and.w r3, r3, #1 + 800b000: 2b01 cmp r3, #1 + 800b002: d115 bne.n 800b030 + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 800b004: 68fb ldr r3, [r7, #12] + 800b006: 681b ldr r3, [r3, #0] + 800b008: 68da ldr r2, [r3, #12] + 800b00a: 68fb ldr r3, [r7, #12] + 800b00c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b00e: b292 uxth r2, r2 + 800b010: 801a strh r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint16_t); + 800b012: 68fb ldr r3, [r7, #12] + 800b014: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b016: 1c9a adds r2, r3, #2 + 800b018: 68fb ldr r3, [r7, #12] + 800b01a: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 800b01c: 68fb ldr r3, [r7, #12] + 800b01e: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b022: b29b uxth r3, r3 + 800b024: 3b01 subs r3, #1 + 800b026: b29a uxth r2, r3 + 800b028: 68fb ldr r3, [r7, #12] + 800b02a: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + 800b02e: e015 b.n 800b05c + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800b030: f7fa f90e bl 8005250 + 800b034: 4602 mov r2, r0 + 800b036: 693b ldr r3, [r7, #16] + 800b038: 1ad3 subs r3, r2, r3 + 800b03a: 683a ldr r2, [r7, #0] + 800b03c: 429a cmp r2, r3 + 800b03e: d803 bhi.n 800b048 + 800b040: 683b ldr r3, [r7, #0] + 800b042: f1b3 3fff cmp.w r3, #4294967295 + 800b046: d102 bne.n 800b04e + 800b048: 683b ldr r3, [r7, #0] + 800b04a: 2b00 cmp r3, #0 + 800b04c: d106 bne.n 800b05c + { + errorcode = HAL_TIMEOUT; + 800b04e: 2303 movs r3, #3 + 800b050: 75fb strb r3, [r7, #23] + hspi->State = HAL_SPI_STATE_READY; + 800b052: 68fb ldr r3, [r7, #12] + 800b054: 2201 movs r2, #1 + 800b056: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800b05a: e01b b.n 800b094 + while (hspi->RxXferCount > 0U) + 800b05c: 68fb ldr r3, [r7, #12] + 800b05e: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b062: b29b uxth r3, r3 + 800b064: 2b00 cmp r3, #0 + 800b066: d1c6 bne.n 800aff6 } } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 800b068: 693a ldr r2, [r7, #16] + 800b06a: 6839 ldr r1, [r7, #0] + 800b06c: 68f8 ldr r0, [r7, #12] + 800b06e: f000 fb5b bl 800b728 + 800b072: 4603 mov r3, r0 + 800b074: 2b00 cmp r3, #0 + 800b076: d002 beq.n 800b07e + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 800b078: 68fb ldr r3, [r7, #12] + 800b07a: 2220 movs r2, #32 + 800b07c: 661a str r2, [r3, #96] ; 0x60 + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 800b07e: 68fb ldr r3, [r7, #12] + 800b080: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b082: 2b00 cmp r3, #0 + 800b084: d002 beq.n 800b08c + { + errorcode = HAL_ERROR; + 800b086: 2301 movs r3, #1 + 800b088: 75fb strb r3, [r7, #23] + 800b08a: e003 b.n 800b094 + } + else + { + hspi->State = HAL_SPI_STATE_READY; + 800b08c: 68fb ldr r3, [r7, #12] + 800b08e: 2201 movs r2, #1 + 800b090: f883 205d strb.w r2, [r3, #93] ; 0x5d + } -#endif /* OCTOSPI1 || OCTOSPI2 */ - - return status; - 8009e6c: 7cbb ldrb r3, [r7, #18] +error : + __HAL_UNLOCK(hspi); + 800b094: 68fb ldr r3, [r7, #12] + 800b096: 2200 movs r2, #0 + 800b098: f883 205c strb.w r2, [r3, #92] ; 0x5c + return errorcode; + 800b09c: 7dfb ldrb r3, [r7, #23] } - 8009e6e: 4618 mov r0, r3 - 8009e70: 3718 adds r7, #24 - 8009e72: 46bd mov sp, r7 - 8009e74: bd80 pop {r7, pc} - 8009e76: bf00 nop - 8009e78: 40021000 .word 0x40021000 + 800b09e: 4618 mov r0, r3 + 800b0a0: 3718 adds r7, #24 + 800b0a2: 46bd mov sp, r7 + 800b0a4: bd80 pop {r7, pc} -08009e7c : - * @note PLLSAI1 is temporary disable to apply new parameters - * +0800b0a6 : + * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) -{ - 8009e7c: b580 push {r7, lr} - 8009e7e: b084 sub sp, #16 - 8009e80: af00 add r7, sp, #0 - 8009e82: 6078 str r0, [r7, #4] - 8009e84: 6039 str r1, [r7, #0] - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - 8009e86: 2300 movs r3, #0 - 8009e88: 73fb strb r3, [r7, #15] - assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); - assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); - assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + 800b0a6: b580 push {r7, lr} + 800b0a8: b08a sub sp, #40 ; 0x28 + 800b0aa: af00 add r7, sp, #0 + 800b0ac: 60f8 str r0, [r7, #12] + 800b0ae: 60b9 str r1, [r7, #8] + 800b0b0: 607a str r2, [r7, #4] + 800b0b2: 807b strh r3, [r7, #2] + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + 800b0b4: 2301 movs r3, #1 + 800b0b6: 627b str r3, [r7, #36] ; 0x24 + HAL_StatusTypeDef errorcode = HAL_OK; + 800b0b8: 2300 movs r3, #0 + 800b0ba: f887 3023 strb.w r3, [r7, #35] ; 0x23 + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Check that PLLSAI1 clock source and divider M can be applied */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) - 8009e8a: 4b74 ldr r3, [pc, #464] ; (800a05c ) - 8009e8c: 68db ldr r3, [r3, #12] - 8009e8e: f003 0303 and.w r3, r3, #3 - 8009e92: 2b00 cmp r3, #0 - 8009e94: d018 beq.n 8009ec8 + /* Process Locked */ + __HAL_LOCK(hspi); + 800b0be: 68fb ldr r3, [r7, #12] + 800b0c0: f893 305c ldrb.w r3, [r3, #92] ; 0x5c + 800b0c4: 2b01 cmp r3, #1 + 800b0c6: d101 bne.n 800b0cc + 800b0c8: 2302 movs r3, #2 + 800b0ca: e20a b.n 800b4e2 + 800b0cc: 68fb ldr r3, [r7, #12] + 800b0ce: 2201 movs r2, #1 + 800b0d0: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 800b0d4: f7fa f8bc bl 8005250 + 800b0d8: 61f8 str r0, [r7, #28] + + /* Init temporary variables */ + tmp_state = hspi->State; + 800b0da: 68fb ldr r3, [r7, #12] + 800b0dc: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 800b0e0: 76fb strb r3, [r7, #27] + tmp_mode = hspi->Init.Mode; + 800b0e2: 68fb ldr r3, [r7, #12] + 800b0e4: 685b ldr r3, [r3, #4] + 800b0e6: 617b str r3, [r7, #20] + initial_TxXferCount = Size; + 800b0e8: 887b ldrh r3, [r7, #2] + 800b0ea: 827b strh r3, [r7, #18] + initial_RxXferCount = Size; + 800b0ec: 887b ldrh r3, [r7, #2] + 800b0ee: 823b strh r3, [r7, #16] +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + 800b0f0: 7efb ldrb r3, [r7, #27] + 800b0f2: 2b01 cmp r3, #1 + 800b0f4: d00e beq.n 800b114 + 800b0f6: 697b ldr r3, [r7, #20] + 800b0f8: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800b0fc: d106 bne.n 800b10c + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + 800b0fe: 68fb ldr r3, [r7, #12] + 800b100: 689b ldr r3, [r3, #8] + 800b102: 2b00 cmp r3, #0 + 800b104: d102 bne.n 800b10c + 800b106: 7efb ldrb r3, [r7, #27] + 800b108: 2b04 cmp r3, #4 + 800b10a: d003 beq.n 800b114 + { + errorcode = HAL_BUSY; + 800b10c: 2302 movs r3, #2 + 800b10e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 800b112: e1e0 b.n 800b4d6 + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + 800b114: 68bb ldr r3, [r7, #8] + 800b116: 2b00 cmp r3, #0 + 800b118: d005 beq.n 800b126 + 800b11a: 687b ldr r3, [r7, #4] + 800b11c: 2b00 cmp r3, #0 + 800b11e: d002 beq.n 800b126 + 800b120: 887b ldrh r3, [r7, #2] + 800b122: 2b00 cmp r3, #0 + 800b124: d103 bne.n 800b12e + { + errorcode = HAL_ERROR; + 800b126: 2301 movs r3, #1 + 800b128: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 800b12c: e1d3 b.n 800b4d6 + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + 800b12e: 68fb ldr r3, [r7, #12] + 800b130: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 800b134: b2db uxtb r3, r3 + 800b136: 2b04 cmp r3, #4 + 800b138: d003 beq.n 800b142 + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 800b13a: 68fb ldr r3, [r7, #12] + 800b13c: 2205 movs r2, #5 + 800b13e: f883 205d strb.w r2, [r3, #93] ; 0x5d + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 800b142: 68fb ldr r3, [r7, #12] + 800b144: 2200 movs r2, #0 + 800b146: 661a str r2, [r3, #96] ; 0x60 + hspi->pRxBuffPtr = (uint8_t *)pRxData; + 800b148: 68fb ldr r3, [r7, #12] + 800b14a: 687a ldr r2, [r7, #4] + 800b14c: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount = Size; + 800b14e: 68fb ldr r3, [r7, #12] + 800b150: 887a ldrh r2, [r7, #2] + 800b152: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + hspi->RxXferSize = Size; + 800b156: 68fb ldr r3, [r7, #12] + 800b158: 887a ldrh r2, [r7, #2] + 800b15a: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + hspi->pTxBuffPtr = (uint8_t *)pTxData; + 800b15e: 68fb ldr r3, [r7, #12] + 800b160: 68ba ldr r2, [r7, #8] + 800b162: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount = Size; + 800b164: 68fb ldr r3, [r7, #12] + 800b166: 887a ldrh r2, [r7, #2] + 800b168: 87da strh r2, [r3, #62] ; 0x3e + hspi->TxXferSize = Size; + 800b16a: 68fb ldr r3, [r7, #12] + 800b16c: 887a ldrh r2, [r7, #2] + 800b16e: 879a strh r2, [r3, #60] ; 0x3c + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + 800b170: 68fb ldr r3, [r7, #12] + 800b172: 2200 movs r2, #0 + 800b174: 64da str r2, [r3, #76] ; 0x4c + hspi->TxISR = NULL; + 800b176: 68fb ldr r3, [r7, #12] + 800b178: 2200 movs r2, #0 + 800b17a: 651a str r2, [r3, #80] ; 0x50 + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + 800b17c: 68fb ldr r3, [r7, #12] + 800b17e: 68db ldr r3, [r3, #12] + 800b180: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800b184: d802 bhi.n 800b18c + 800b186: 8a3b ldrh r3, [r7, #16] + 800b188: 2b01 cmp r3, #1 + 800b18a: d908 bls.n 800b19e + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 800b18c: 68fb ldr r3, [r7, #12] + 800b18e: 681b ldr r3, [r3, #0] + 800b190: 685a ldr r2, [r3, #4] + 800b192: 68fb ldr r3, [r7, #12] + 800b194: 681b ldr r3, [r3, #0] + 800b196: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 800b19a: 605a str r2, [r3, #4] + 800b19c: e007 b.n 800b1ae + } + else { - /* PLL clock source and divider M already set, check that no request for change */ - if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - 8009e96: 4b71 ldr r3, [pc, #452] ; (800a05c ) - 8009e98: 68db ldr r3, [r3, #12] - 8009e9a: f003 0203 and.w r2, r3, #3 - 8009e9e: 687b ldr r3, [r7, #4] - 8009ea0: 681b ldr r3, [r3, #0] - 8009ea2: 429a cmp r2, r3 - 8009ea4: d10d bne.n 8009ec2 - || - (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) - 8009ea6: 687b ldr r3, [r7, #4] - 8009ea8: 681b ldr r3, [r3, #0] - || - 8009eaa: 2b00 cmp r3, #0 - 8009eac: d009 beq.n 8009ec2 -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) - 8009eae: 4b6b ldr r3, [pc, #428] ; (800a05c ) - 8009eb0: 68db ldr r3, [r3, #12] - 8009eb2: 091b lsrs r3, r3, #4 - 8009eb4: f003 0307 and.w r3, r3, #7 - 8009eb8: 1c5a adds r2, r3, #1 - 8009eba: 687b ldr r3, [r7, #4] - 8009ebc: 685b ldr r3, [r3, #4] - || - 8009ebe: 429a cmp r2, r3 - 8009ec0: d047 beq.n 8009f52 -#endif - ) + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 800b19e: 68fb ldr r3, [r7, #12] + 800b1a0: 681b ldr r3, [r3, #0] + 800b1a2: 685a ldr r2, [r3, #4] + 800b1a4: 68fb ldr r3, [r7, #12] + 800b1a6: 681b ldr r3, [r3, #0] + 800b1a8: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 800b1ac: 605a str r2, [r3, #4] + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 800b1ae: 68fb ldr r3, [r7, #12] + 800b1b0: 681b ldr r3, [r3, #0] + 800b1b2: 681b ldr r3, [r3, #0] + 800b1b4: f003 0340 and.w r3, r3, #64 ; 0x40 + 800b1b8: 2b40 cmp r3, #64 ; 0x40 + 800b1ba: d007 beq.n 800b1cc + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 800b1bc: 68fb ldr r3, [r7, #12] + 800b1be: 681b ldr r3, [r3, #0] + 800b1c0: 681a ldr r2, [r3, #0] + 800b1c2: 68fb ldr r3, [r7, #12] + 800b1c4: 681b ldr r3, [r3, #0] + 800b1c6: f042 0240 orr.w r2, r2, #64 ; 0x40 + 800b1ca: 601a str r2, [r3, #0] + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 800b1cc: 68fb ldr r3, [r7, #12] + 800b1ce: 68db ldr r3, [r3, #12] + 800b1d0: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 800b1d4: f240 8081 bls.w 800b2da + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800b1d8: 68fb ldr r3, [r7, #12] + 800b1da: 685b ldr r3, [r3, #4] + 800b1dc: 2b00 cmp r3, #0 + 800b1de: d002 beq.n 800b1e6 + 800b1e0: 8a7b ldrh r3, [r7, #18] + 800b1e2: 2b01 cmp r3, #1 + 800b1e4: d16d bne.n 800b2c2 { - status = HAL_ERROR; - 8009ec2: 2301 movs r3, #1 - 8009ec4: 73fb strb r3, [r7, #15] - 8009ec6: e044 b.n 8009f52 + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800b1e6: 68fb ldr r3, [r7, #12] + 800b1e8: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b1ea: 881a ldrh r2, [r3, #0] + 800b1ec: 68fb ldr r3, [r7, #12] + 800b1ee: 681b ldr r3, [r3, #0] + 800b1f0: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800b1f2: 68fb ldr r3, [r7, #12] + 800b1f4: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b1f6: 1c9a adds r2, r3, #2 + 800b1f8: 68fb ldr r3, [r7, #12] + 800b1fa: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800b1fc: 68fb ldr r3, [r7, #12] + 800b1fe: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b200: b29b uxth r3, r3 + 800b202: 3b01 subs r3, #1 + 800b204: b29a uxth r2, r3 + 800b206: 68fb ldr r3, [r7, #12] + 800b208: 87da strh r2, [r3, #62] ; 0x3e + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 800b20a: e05a b.n 800b2c2 + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + 800b20c: 68fb ldr r3, [r7, #12] + 800b20e: 681b ldr r3, [r3, #0] + 800b210: 689b ldr r3, [r3, #8] + 800b212: f003 0302 and.w r3, r3, #2 + 800b216: 2b02 cmp r3, #2 + 800b218: d11b bne.n 800b252 + 800b21a: 68fb ldr r3, [r7, #12] + 800b21c: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b21e: b29b uxth r3, r3 + 800b220: 2b00 cmp r3, #0 + 800b222: d016 beq.n 800b252 + 800b224: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b226: 2b01 cmp r3, #1 + 800b228: d113 bne.n 800b252 + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800b22a: 68fb ldr r3, [r7, #12] + 800b22c: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b22e: 881a ldrh r2, [r3, #0] + 800b230: 68fb ldr r3, [r7, #12] + 800b232: 681b ldr r3, [r3, #0] + 800b234: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800b236: 68fb ldr r3, [r7, #12] + 800b238: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b23a: 1c9a adds r2, r3, #2 + 800b23c: 68fb ldr r3, [r7, #12] + 800b23e: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800b240: 68fb ldr r3, [r7, #12] + 800b242: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b244: b29b uxth r3, r3 + 800b246: 3b01 subs r3, #1 + 800b248: b29a uxth r2, r3 + 800b24a: 68fb ldr r3, [r7, #12] + 800b24c: 87da strh r2, [r3, #62] ; 0x3e + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + 800b24e: 2300 movs r3, #0 + 800b250: 627b str r3, [r7, #36] ; 0x24 + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 800b252: 68fb ldr r3, [r7, #12] + 800b254: 681b ldr r3, [r3, #0] + 800b256: 689b ldr r3, [r3, #8] + 800b258: f003 0301 and.w r3, r3, #1 + 800b25c: 2b01 cmp r3, #1 + 800b25e: d11c bne.n 800b29a + 800b260: 68fb ldr r3, [r7, #12] + 800b262: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b266: b29b uxth r3, r3 + 800b268: 2b00 cmp r3, #0 + 800b26a: d016 beq.n 800b29a + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 800b26c: 68fb ldr r3, [r7, #12] + 800b26e: 681b ldr r3, [r3, #0] + 800b270: 68da ldr r2, [r3, #12] + 800b272: 68fb ldr r3, [r7, #12] + 800b274: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b276: b292 uxth r2, r2 + 800b278: 801a strh r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint16_t); + 800b27a: 68fb ldr r3, [r7, #12] + 800b27c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b27e: 1c9a adds r2, r3, #2 + 800b280: 68fb ldr r3, [r7, #12] + 800b282: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 800b284: 68fb ldr r3, [r7, #12] + 800b286: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b28a: b29b uxth r3, r3 + 800b28c: 3b01 subs r3, #1 + 800b28e: b29a uxth r2, r3 + 800b290: 68fb ldr r3, [r7, #12] + 800b292: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + 800b296: 2301 movs r3, #1 + 800b298: 627b str r3, [r7, #36] ; 0x24 + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + 800b29a: f7f9 ffd9 bl 8005250 + 800b29e: 4602 mov r2, r0 + 800b2a0: 69fb ldr r3, [r7, #28] + 800b2a2: 1ad3 subs r3, r2, r3 + 800b2a4: 6b3a ldr r2, [r7, #48] ; 0x30 + 800b2a6: 429a cmp r2, r3 + 800b2a8: d80b bhi.n 800b2c2 + 800b2aa: 6b3b ldr r3, [r7, #48] ; 0x30 + 800b2ac: f1b3 3fff cmp.w r3, #4294967295 + 800b2b0: d007 beq.n 800b2c2 + { + errorcode = HAL_TIMEOUT; + 800b2b2: 2303 movs r3, #3 + 800b2b4: f887 3023 strb.w r3, [r7, #35] ; 0x23 + hspi->State = HAL_SPI_STATE_READY; + 800b2b8: 68fb ldr r3, [r7, #12] + 800b2ba: 2201 movs r2, #1 + 800b2bc: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800b2c0: e109 b.n 800b4d6 + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 800b2c2: 68fb ldr r3, [r7, #12] + 800b2c4: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b2c6: b29b uxth r3, r3 + 800b2c8: 2b00 cmp r3, #0 + 800b2ca: d19f bne.n 800b20c + 800b2cc: 68fb ldr r3, [r7, #12] + 800b2ce: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b2d2: b29b uxth r3, r3 + 800b2d4: 2b00 cmp r3, #0 + 800b2d6: d199 bne.n 800b20c + 800b2d8: e0e3 b.n 800b4a2 } } + /* Transmit and Receive data in 8 Bit mode */ else { - /* Check PLLSAI1 clock source availability */ - switch(PllSai1->PLLSAI1Source) - 8009ec8: 687b ldr r3, [r7, #4] - 8009eca: 681b ldr r3, [r3, #0] - 8009ecc: 2b03 cmp r3, #3 - 8009ece: d018 beq.n 8009f02 - 8009ed0: 2b03 cmp r3, #3 - 8009ed2: d825 bhi.n 8009f20 - 8009ed4: 2b01 cmp r3, #1 - 8009ed6: d002 beq.n 8009ede - 8009ed8: 2b02 cmp r3, #2 - 8009eda: d009 beq.n 8009ef0 - 8009edc: e020 b.n 8009f20 - { - case RCC_PLLSOURCE_MSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) - 8009ede: 4b5f ldr r3, [pc, #380] ; (800a05c ) - 8009ee0: 681b ldr r3, [r3, #0] - 8009ee2: f003 0302 and.w r3, r3, #2 - 8009ee6: 2b00 cmp r3, #0 - 8009ee8: d11d bne.n 8009f26 + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800b2da: 68fb ldr r3, [r7, #12] + 800b2dc: 685b ldr r3, [r3, #4] + 800b2de: 2b00 cmp r3, #0 + 800b2e0: d003 beq.n 800b2ea + 800b2e2: 8a7b ldrh r3, [r7, #18] + 800b2e4: 2b01 cmp r3, #1 + 800b2e6: f040 80cf bne.w 800b488 + { + if (hspi->TxXferCount > 1U) + 800b2ea: 68fb ldr r3, [r7, #12] + 800b2ec: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b2ee: b29b uxth r3, r3 + 800b2f0: 2b01 cmp r3, #1 + 800b2f2: d912 bls.n 800b31a { - status = HAL_ERROR; - 8009eea: 2301 movs r3, #1 - 8009eec: 73fb strb r3, [r7, #15] + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800b2f4: 68fb ldr r3, [r7, #12] + 800b2f6: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b2f8: 881a ldrh r2, [r3, #0] + 800b2fa: 68fb ldr r3, [r7, #12] + 800b2fc: 681b ldr r3, [r3, #0] + 800b2fe: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800b300: 68fb ldr r3, [r7, #12] + 800b302: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b304: 1c9a adds r2, r3, #2 + 800b306: 68fb ldr r3, [r7, #12] + 800b308: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 800b30a: 68fb ldr r3, [r7, #12] + 800b30c: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b30e: b29b uxth r3, r3 + 800b310: 3b02 subs r3, #2 + 800b312: b29a uxth r2, r3 + 800b314: 68fb ldr r3, [r7, #12] + 800b316: 87da strh r2, [r3, #62] ; 0x3e + 800b318: e0b6 b.n 800b488 } - break; - 8009eee: e01a b.n 8009f26 - case RCC_PLLSOURCE_HSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) - 8009ef0: 4b5a ldr r3, [pc, #360] ; (800a05c ) - 8009ef2: 681b ldr r3, [r3, #0] - 8009ef4: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8009ef8: 2b00 cmp r3, #0 - 8009efa: d116 bne.n 8009f2a + else { - status = HAL_ERROR; - 8009efc: 2301 movs r3, #1 - 8009efe: 73fb strb r3, [r7, #15] + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 800b31a: 68fb ldr r3, [r7, #12] + 800b31c: 6b9a ldr r2, [r3, #56] ; 0x38 + 800b31e: 68fb ldr r3, [r7, #12] + 800b320: 681b ldr r3, [r3, #0] + 800b322: 330c adds r3, #12 + 800b324: 7812 ldrb r2, [r2, #0] + 800b326: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 800b328: 68fb ldr r3, [r7, #12] + 800b32a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b32c: 1c5a adds r2, r3, #1 + 800b32e: 68fb ldr r3, [r7, #12] + 800b330: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800b332: 68fb ldr r3, [r7, #12] + 800b334: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b336: b29b uxth r3, r3 + 800b338: 3b01 subs r3, #1 + 800b33a: b29a uxth r2, r3 + 800b33c: 68fb ldr r3, [r7, #12] + 800b33e: 87da strh r2, [r3, #62] ; 0x3e + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } - break; - 8009f00: e013 b.n 8009f2a - case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY)) - 8009f02: 4b56 ldr r3, [pc, #344] ; (800a05c ) - 8009f04: 681b ldr r3, [r3, #0] - 8009f06: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8009f0a: 2b00 cmp r3, #0 - 8009f0c: d10f bne.n 8009f2e + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 800b340: e0a2 b.n 800b488 + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + 800b342: 68fb ldr r3, [r7, #12] + 800b344: 681b ldr r3, [r3, #0] + 800b346: 689b ldr r3, [r3, #8] + 800b348: f003 0302 and.w r3, r3, #2 + 800b34c: 2b02 cmp r3, #2 + 800b34e: d134 bne.n 800b3ba + 800b350: 68fb ldr r3, [r7, #12] + 800b352: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b354: b29b uxth r3, r3 + 800b356: 2b00 cmp r3, #0 + 800b358: d02f beq.n 800b3ba + 800b35a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b35c: 2b01 cmp r3, #1 + 800b35e: d12c bne.n 800b3ba { - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) - 8009f0e: 4b53 ldr r3, [pc, #332] ; (800a05c ) - 8009f10: 681b ldr r3, [r3, #0] - 8009f12: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 8009f16: 2b00 cmp r3, #0 - 8009f18: d109 bne.n 8009f2e + if (hspi->TxXferCount > 1U) + 800b360: 68fb ldr r3, [r7, #12] + 800b362: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b364: b29b uxth r3, r3 + 800b366: 2b01 cmp r3, #1 + 800b368: d912 bls.n 800b390 { - status = HAL_ERROR; - 8009f1a: 2301 movs r3, #1 - 8009f1c: 73fb strb r3, [r7, #15] + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800b36a: 68fb ldr r3, [r7, #12] + 800b36c: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b36e: 881a ldrh r2, [r3, #0] + 800b370: 68fb ldr r3, [r7, #12] + 800b372: 681b ldr r3, [r3, #0] + 800b374: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 800b376: 68fb ldr r3, [r7, #12] + 800b378: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b37a: 1c9a adds r2, r3, #2 + 800b37c: 68fb ldr r3, [r7, #12] + 800b37e: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 800b380: 68fb ldr r3, [r7, #12] + 800b382: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b384: b29b uxth r3, r3 + 800b386: 3b02 subs r3, #2 + 800b388: b29a uxth r2, r3 + 800b38a: 68fb ldr r3, [r7, #12] + 800b38c: 87da strh r2, [r3, #62] ; 0x3e + 800b38e: e012 b.n 800b3b6 + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 800b390: 68fb ldr r3, [r7, #12] + 800b392: 6b9a ldr r2, [r3, #56] ; 0x38 + 800b394: 68fb ldr r3, [r7, #12] + 800b396: 681b ldr r3, [r3, #0] + 800b398: 330c adds r3, #12 + 800b39a: 7812 ldrb r2, [r2, #0] + 800b39c: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 800b39e: 68fb ldr r3, [r7, #12] + 800b3a0: 6b9b ldr r3, [r3, #56] ; 0x38 + 800b3a2: 1c5a adds r2, r3, #1 + 800b3a4: 68fb ldr r3, [r7, #12] + 800b3a6: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800b3a8: 68fb ldr r3, [r7, #12] + 800b3aa: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b3ac: b29b uxth r3, r3 + 800b3ae: 3b01 subs r3, #1 + 800b3b0: b29a uxth r2, r3 + 800b3b2: 68fb ldr r3, [r7, #12] + 800b3b4: 87da strh r2, [r3, #62] ; 0x3e } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + 800b3b6: 2300 movs r3, #0 + 800b3b8: 627b str r3, [r7, #36] ; 0x24 + } +#endif /* USE_SPI_CRC */ } - break; - 8009f1e: e006 b.n 8009f2e - default: - status = HAL_ERROR; - 8009f20: 2301 movs r3, #1 - 8009f22: 73fb strb r3, [r7, #15] - break; - 8009f24: e004 b.n 8009f30 - break; - 8009f26: bf00 nop - 8009f28: e002 b.n 8009f30 - break; - 8009f2a: bf00 nop - 8009f2c: e000 b.n 8009f30 - break; - 8009f2e: bf00 nop - } - if(status == HAL_OK) - 8009f30: 7bfb ldrb r3, [r7, #15] - 8009f32: 2b00 cmp r3, #0 - 8009f34: d10d bne.n 8009f52 -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Set PLLSAI1 clock source */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); -#else - /* Set PLLSAI1 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); - 8009f36: 4b49 ldr r3, [pc, #292] ; (800a05c ) - 8009f38: 68db ldr r3, [r3, #12] - 8009f3a: f023 0273 bic.w r2, r3, #115 ; 0x73 - 8009f3e: 687b ldr r3, [r7, #4] - 8009f40: 6819 ldr r1, [r3, #0] - 8009f42: 687b ldr r3, [r7, #4] - 8009f44: 685b ldr r3, [r3, #4] - 8009f46: 3b01 subs r3, #1 - 8009f48: 011b lsls r3, r3, #4 - 8009f4a: 430b orrs r3, r1 - 8009f4c: 4943 ldr r1, [pc, #268] ; (800a05c ) - 8009f4e: 4313 orrs r3, r2 - 8009f50: 60cb str r3, [r1, #12] -#endif - } + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 800b3ba: 68fb ldr r3, [r7, #12] + 800b3bc: 681b ldr r3, [r3, #0] + 800b3be: 689b ldr r3, [r3, #8] + 800b3c0: f003 0301 and.w r3, r3, #1 + 800b3c4: 2b01 cmp r3, #1 + 800b3c6: d148 bne.n 800b45a + 800b3c8: 68fb ldr r3, [r7, #12] + 800b3ca: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b3ce: b29b uxth r3, r3 + 800b3d0: 2b00 cmp r3, #0 + 800b3d2: d042 beq.n 800b45a + { + if (hspi->RxXferCount > 1U) + 800b3d4: 68fb ldr r3, [r7, #12] + 800b3d6: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b3da: b29b uxth r3, r3 + 800b3dc: 2b01 cmp r3, #1 + 800b3de: d923 bls.n 800b428 + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 800b3e0: 68fb ldr r3, [r7, #12] + 800b3e2: 681b ldr r3, [r3, #0] + 800b3e4: 68da ldr r2, [r3, #12] + 800b3e6: 68fb ldr r3, [r7, #12] + 800b3e8: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b3ea: b292 uxth r2, r2 + 800b3ec: 801a strh r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint16_t); + 800b3ee: 68fb ldr r3, [r7, #12] + 800b3f0: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b3f2: 1c9a adds r2, r3, #2 + 800b3f4: 68fb ldr r3, [r7, #12] + 800b3f6: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount -= 2U; + 800b3f8: 68fb ldr r3, [r7, #12] + 800b3fa: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b3fe: b29b uxth r3, r3 + 800b400: 3b02 subs r3, #2 + 800b402: b29a uxth r2, r3 + 800b404: 68fb ldr r3, [r7, #12] + 800b406: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + if (hspi->RxXferCount <= 1U) + 800b40a: 68fb ldr r3, [r7, #12] + 800b40c: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b410: b29b uxth r3, r3 + 800b412: 2b01 cmp r3, #1 + 800b414: d81f bhi.n 800b456 + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 800b416: 68fb ldr r3, [r7, #12] + 800b418: 681b ldr r3, [r3, #0] + 800b41a: 685a ldr r2, [r3, #4] + 800b41c: 68fb ldr r3, [r7, #12] + 800b41e: 681b ldr r3, [r3, #0] + 800b420: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 800b424: 605a str r2, [r3, #4] + 800b426: e016 b.n 800b456 + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + 800b428: 68fb ldr r3, [r7, #12] + 800b42a: 681b ldr r3, [r3, #0] + 800b42c: f103 020c add.w r2, r3, #12 + 800b430: 68fb ldr r3, [r7, #12] + 800b432: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b434: 7812 ldrb r2, [r2, #0] + 800b436: b2d2 uxtb r2, r2 + 800b438: 701a strb r2, [r3, #0] + hspi->pRxBuffPtr++; + 800b43a: 68fb ldr r3, [r7, #12] + 800b43c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800b43e: 1c5a adds r2, r3, #1 + 800b440: 68fb ldr r3, [r7, #12] + 800b442: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 800b444: 68fb ldr r3, [r7, #12] + 800b446: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b44a: b29b uxth r3, r3 + 800b44c: 3b01 subs r3, #1 + 800b44e: b29a uxth r2, r3 + 800b450: 68fb ldr r3, [r7, #12] + 800b452: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + 800b456: 2301 movs r3, #1 + 800b458: 627b str r3, [r7, #36] ; 0x24 + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + 800b45a: f7f9 fef9 bl 8005250 + 800b45e: 4602 mov r2, r0 + 800b460: 69fb ldr r3, [r7, #28] + 800b462: 1ad3 subs r3, r2, r3 + 800b464: 6b3a ldr r2, [r7, #48] ; 0x30 + 800b466: 429a cmp r2, r3 + 800b468: d803 bhi.n 800b472 + 800b46a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800b46c: f1b3 3fff cmp.w r3, #4294967295 + 800b470: d102 bne.n 800b478 + 800b472: 6b3b ldr r3, [r7, #48] ; 0x30 + 800b474: 2b00 cmp r3, #0 + 800b476: d107 bne.n 800b488 + { + errorcode = HAL_TIMEOUT; + 800b478: 2303 movs r3, #3 + 800b47a: f887 3023 strb.w r3, [r7, #35] ; 0x23 + hspi->State = HAL_SPI_STATE_READY; + 800b47e: 68fb ldr r3, [r7, #12] + 800b480: 2201 movs r2, #1 + 800b482: f883 205d strb.w r2, [r3, #93] ; 0x5d + goto error; + 800b486: e026 b.n 800b4d6 + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 800b488: 68fb ldr r3, [r7, #12] + 800b48a: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800b48c: b29b uxth r3, r3 + 800b48e: 2b00 cmp r3, #0 + 800b490: f47f af57 bne.w 800b342 + 800b494: 68fb ldr r3, [r7, #12] + 800b496: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800b49a: b29b uxth r3, r3 + 800b49c: 2b00 cmp r3, #0 + 800b49e: f47f af50 bne.w 800b342 + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 800b4a2: 69fa ldr r2, [r7, #28] + 800b4a4: 6b39 ldr r1, [r7, #48] ; 0x30 + 800b4a6: 68f8 ldr r0, [r7, #12] + 800b4a8: f000 f996 bl 800b7d8 + 800b4ac: 4603 mov r3, r0 + 800b4ae: 2b00 cmp r3, #0 + 800b4b0: d005 beq.n 800b4be + { + errorcode = HAL_ERROR; + 800b4b2: 2301 movs r3, #1 + 800b4b4: f887 3023 strb.w r3, [r7, #35] ; 0x23 + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 800b4b8: 68fb ldr r3, [r7, #12] + 800b4ba: 2220 movs r2, #32 + 800b4bc: 661a str r2, [r3, #96] ; 0x60 + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 800b4be: 68fb ldr r3, [r7, #12] + 800b4c0: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b4c2: 2b00 cmp r3, #0 + 800b4c4: d003 beq.n 800b4ce + { + errorcode = HAL_ERROR; + 800b4c6: 2301 movs r3, #1 + 800b4c8: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800b4cc: e003 b.n 800b4d6 + } + else + { + hspi->State = HAL_SPI_STATE_READY; + 800b4ce: 68fb ldr r3, [r7, #12] + 800b4d0: 2201 movs r2, #1 + 800b4d2: f883 205d strb.w r2, [r3, #93] ; 0x5d } + +error : + __HAL_UNLOCK(hspi); + 800b4d6: 68fb ldr r3, [r7, #12] + 800b4d8: 2200 movs r2, #0 + 800b4da: f883 205c strb.w r2, [r3, #92] ; 0x5c + return errorcode; + 800b4de: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 +} + 800b4e2: 4618 mov r0, r3 + 800b4e4: 3728 adds r7, #40 ; 0x28 + 800b4e6: 46bd mov sp, r7 + 800b4e8: bd80 pop {r7, pc} + ... - if(status == HAL_OK) - 8009f52: 7bfb ldrb r3, [r7, #15] - 8009f54: 2b00 cmp r3, #0 - 8009f56: d17c bne.n 800a052 +0800b4ec : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 800b4ec: b580 push {r7, lr} + 800b4ee: b088 sub sp, #32 + 800b4f0: af00 add r7, sp, #0 + 800b4f2: 60f8 str r0, [r7, #12] + 800b4f4: 60b9 str r1, [r7, #8] + 800b4f6: 603b str r3, [r7, #0] + 800b4f8: 4613 mov r3, r2 + 800b4fa: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 800b4fc: f7f9 fea8 bl 8005250 + 800b500: 4602 mov r2, r0 + 800b502: 6abb ldr r3, [r7, #40] ; 0x28 + 800b504: 1a9b subs r3, r3, r2 + 800b506: 683a ldr r2, [r7, #0] + 800b508: 4413 add r3, r2 + 800b50a: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 800b50c: f7f9 fea0 bl 8005250 + 800b510: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 800b512: 4b39 ldr r3, [pc, #228] ; (800b5f8 ) + 800b514: 681b ldr r3, [r3, #0] + 800b516: 015b lsls r3, r3, #5 + 800b518: 0d1b lsrs r3, r3, #20 + 800b51a: 69fa ldr r2, [r7, #28] + 800b51c: fb02 f303 mul.w r3, r2, r3 + 800b520: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800b522: e054 b.n 800b5ce { - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - 8009f58: 4b40 ldr r3, [pc, #256] ; (800a05c ) - 8009f5a: 681b ldr r3, [r3, #0] - 8009f5c: 4a3f ldr r2, [pc, #252] ; (800a05c ) - 8009f5e: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 - 8009f62: 6013 str r3, [r2, #0] + if (Timeout != HAL_MAX_DELAY) + 800b524: 683b ldr r3, [r7, #0] + 800b526: f1b3 3fff cmp.w r3, #4294967295 + 800b52a: d050 beq.n 800b5ce + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 800b52c: f7f9 fe90 bl 8005250 + 800b530: 4602 mov r2, r0 + 800b532: 69bb ldr r3, [r7, #24] + 800b534: 1ad3 subs r3, r2, r3 + 800b536: 69fa ldr r2, [r7, #28] + 800b538: 429a cmp r2, r3 + 800b53a: d902 bls.n 800b542 + 800b53c: 69fb ldr r3, [r7, #28] + 800b53e: 2b00 cmp r3, #0 + 800b540: d13d bne.n 800b5be + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 800b542: 68fb ldr r3, [r7, #12] + 800b544: 681b ldr r3, [r3, #0] + 800b546: 685a ldr r2, [r3, #4] + 800b548: 68fb ldr r3, [r7, #12] + 800b54a: 681b ldr r3, [r3, #0] + 800b54c: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 800b550: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800b552: 68fb ldr r3, [r7, #12] + 800b554: 685b ldr r3, [r3, #4] + 800b556: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800b55a: d111 bne.n 800b580 + 800b55c: 68fb ldr r3, [r7, #12] + 800b55e: 689b ldr r3, [r3, #8] + 800b560: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800b564: d004 beq.n 800b570 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800b566: 68fb ldr r3, [r7, #12] + 800b568: 689b ldr r3, [r3, #8] + 800b56a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800b56e: d107 bne.n 800b580 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800b570: 68fb ldr r3, [r7, #12] + 800b572: 681b ldr r3, [r3, #0] + 800b574: 681a ldr r2, [r3, #0] + 800b576: 68fb ldr r3, [r7, #12] + 800b578: 681b ldr r3, [r3, #0] + 800b57a: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800b57e: 601a str r2, [r3, #0] + } - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 8009f64: f7fa fb2a bl 80045bc - 8009f68: 60b8 str r0, [r7, #8] + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 800b580: 68fb ldr r3, [r7, #12] + 800b582: 6a9b ldr r3, [r3, #40] ; 0x28 + 800b584: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800b588: d10f bne.n 800b5aa + { + SPI_RESET_CRC(hspi); + 800b58a: 68fb ldr r3, [r7, #12] + 800b58c: 681b ldr r3, [r3, #0] + 800b58e: 681a ldr r2, [r3, #0] + 800b590: 68fb ldr r3, [r7, #12] + 800b592: 681b ldr r3, [r3, #0] + 800b594: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 800b598: 601a str r2, [r3, #0] + 800b59a: 68fb ldr r3, [r7, #12] + 800b59c: 681b ldr r3, [r3, #0] + 800b59e: 681a ldr r2, [r3, #0] + 800b5a0: 68fb ldr r3, [r7, #12] + 800b5a2: 681b ldr r3, [r3, #0] + 800b5a4: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 800b5a8: 601a str r2, [r3, #0] + } - /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) - 8009f6a: e009 b.n 8009f80 - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - 8009f6c: f7fa fb26 bl 80045bc - 8009f70: 4602 mov r2, r0 - 8009f72: 68bb ldr r3, [r7, #8] - 8009f74: 1ad3 subs r3, r2, r3 - 8009f76: 2b02 cmp r3, #2 - 8009f78: d902 bls.n 8009f80 + hspi->State = HAL_SPI_STATE_READY; + 800b5aa: 68fb ldr r3, [r7, #12] + 800b5ac: 2201 movs r2, #1 + 800b5ae: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 800b5b2: 68fb ldr r3, [r7, #12] + 800b5b4: 2200 movs r2, #0 + 800b5b6: f883 205c strb.w r2, [r3, #92] ; 0x5c + + return HAL_TIMEOUT; + 800b5ba: 2303 movs r3, #3 + 800b5bc: e017 b.n 800b5ee + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 800b5be: 697b ldr r3, [r7, #20] + 800b5c0: 2b00 cmp r3, #0 + 800b5c2: d101 bne.n 800b5c8 { - status = HAL_TIMEOUT; - 8009f7a: 2303 movs r3, #3 - 8009f7c: 73fb strb r3, [r7, #15] - break; - 8009f7e: e005 b.n 8009f8c - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) - 8009f80: 4b36 ldr r3, [pc, #216] ; (800a05c ) - 8009f82: 681b ldr r3, [r3, #0] - 8009f84: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8009f88: 2b00 cmp r3, #0 - 8009f8a: d1ef bne.n 8009f6c + tmp_timeout = 0U; + 800b5c4: 2300 movs r3, #0 + 800b5c6: 61fb str r3, [r7, #28] } + count--; + 800b5c8: 697b ldr r3, [r7, #20] + 800b5ca: 3b01 subs r3, #1 + 800b5cc: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800b5ce: 68fb ldr r3, [r7, #12] + 800b5d0: 681b ldr r3, [r3, #0] + 800b5d2: 689a ldr r2, [r3, #8] + 800b5d4: 68bb ldr r3, [r7, #8] + 800b5d6: 4013 ands r3, r2 + 800b5d8: 68ba ldr r2, [r7, #8] + 800b5da: 429a cmp r2, r3 + 800b5dc: bf0c ite eq + 800b5de: 2301 moveq r3, #1 + 800b5e0: 2300 movne r3, #0 + 800b5e2: b2db uxtb r3, r3 + 800b5e4: 461a mov r2, r3 + 800b5e6: 79fb ldrb r3, [r7, #7] + 800b5e8: 429a cmp r2, r3 + 800b5ea: d19b bne.n 800b524 } + } - if(status == HAL_OK) - 8009f8c: 7bfb ldrb r3, [r7, #15] - 8009f8e: 2b00 cmp r3, #0 - 8009f90: d15f bne.n 800a052 + return HAL_OK; + 800b5ec: 2300 movs r3, #0 +} + 800b5ee: 4618 mov r0, r3 + 800b5f0: 3720 adds r7, #32 + 800b5f2: 46bd mov sp, r7 + 800b5f4: bd80 pop {r7, pc} + 800b5f6: bf00 nop + 800b5f8: 20000020 .word 0x20000020 + +0800b5fc : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + 800b5fc: b580 push {r7, lr} + 800b5fe: b08a sub sp, #40 ; 0x28 + 800b600: af00 add r7, sp, #0 + 800b602: 60f8 str r0, [r7, #12] + 800b604: 60b9 str r1, [r7, #8] + 800b606: 607a str r2, [r7, #4] + 800b608: 603b str r3, [r7, #0] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + 800b60a: 2300 movs r3, #0 + 800b60c: 75fb strb r3, [r7, #23] + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 800b60e: f7f9 fe1f bl 8005250 + 800b612: 4602 mov r2, r0 + 800b614: 6b3b ldr r3, [r7, #48] ; 0x30 + 800b616: 1a9b subs r3, r3, r2 + 800b618: 683a ldr r2, [r7, #0] + 800b61a: 4413 add r3, r2 + 800b61c: 627b str r3, [r7, #36] ; 0x24 + tmp_tickstart = HAL_GetTick(); + 800b61e: f7f9 fe17 bl 8005250 + 800b622: 6238 str r0, [r7, #32] + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + 800b624: 68fb ldr r3, [r7, #12] + 800b626: 681b ldr r3, [r3, #0] + 800b628: 330c adds r3, #12 + 800b62a: 61fb str r3, [r7, #28] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + 800b62c: 4b3d ldr r3, [pc, #244] ; (800b724 ) + 800b62e: 681a ldr r2, [r3, #0] + 800b630: 4613 mov r3, r2 + 800b632: 009b lsls r3, r3, #2 + 800b634: 4413 add r3, r2 + 800b636: 00da lsls r2, r3, #3 + 800b638: 1ad3 subs r3, r2, r3 + 800b63a: 0d1b lsrs r3, r3, #20 + 800b63c: 6a7a ldr r2, [r7, #36] ; 0x24 + 800b63e: fb02 f303 mul.w r3, r2, r3 + 800b642: 61bb str r3, [r7, #24] + + while ((hspi->Instance->SR & Fifo) != State) + 800b644: e060 b.n 800b708 + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + 800b646: 68bb ldr r3, [r7, #8] + 800b648: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 + 800b64c: d107 bne.n 800b65e + 800b64e: 687b ldr r3, [r7, #4] + 800b650: 2b00 cmp r3, #0 + 800b652: d104 bne.n 800b65e { - if(Divider == DIVIDER_P_UPDATE) - 8009f92: 683b ldr r3, [r7, #0] - 8009f94: 2b00 cmp r3, #0 - 8009f96: d110 bne.n 8009fba -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + 800b654: 69fb ldr r3, [r7, #28] + 800b656: 781b ldrb r3, [r3, #0] + 800b658: b2db uxtb r3, r3 + 800b65a: 75fb strb r3, [r7, #23] + /* To avoid GCC warning */ + UNUSED(tmpreg8); + 800b65c: 7dfb ldrb r3, [r7, #23] + } -#else - /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - 8009f98: 4b30 ldr r3, [pc, #192] ; (800a05c ) - 8009f9a: 691b ldr r3, [r3, #16] - 8009f9c: f023 4378 bic.w r3, r3, #4160749568 ; 0xf8000000 - 8009fa0: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 - 8009fa4: 687a ldr r2, [r7, #4] - 8009fa6: 6892 ldr r2, [r2, #8] - 8009fa8: 0211 lsls r1, r2, #8 - 8009faa: 687a ldr r2, [r7, #4] - 8009fac: 68d2 ldr r2, [r2, #12] - 8009fae: 06d2 lsls r2, r2, #27 - 8009fb0: 430a orrs r2, r1 - 8009fb2: 492a ldr r1, [pc, #168] ; (800a05c ) - 8009fb4: 4313 orrs r3, r2 - 8009fb6: 610b str r3, [r1, #16] - 8009fb8: e027 b.n 800a00a - ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ + if (Timeout != HAL_MAX_DELAY) + 800b65e: 683b ldr r3, [r7, #0] + 800b660: f1b3 3fff cmp.w r3, #4294967295 + 800b664: d050 beq.n 800b708 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 800b666: f7f9 fdf3 bl 8005250 + 800b66a: 4602 mov r2, r0 + 800b66c: 6a3b ldr r3, [r7, #32] + 800b66e: 1ad3 subs r3, r2, r3 + 800b670: 6a7a ldr r2, [r7, #36] ; 0x24 + 800b672: 429a cmp r2, r3 + 800b674: d902 bls.n 800b67c + 800b676: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b678: 2b00 cmp r3, #0 + 800b67a: d13d bne.n 800b6f8 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 800b67c: 68fb ldr r3, [r7, #12] + 800b67e: 681b ldr r3, [r3, #0] + 800b680: 685a ldr r2, [r3, #4] + 800b682: 68fb ldr r3, [r7, #12] + 800b684: 681b ldr r3, [r3, #0] + 800b686: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 800b68a: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800b68c: 68fb ldr r3, [r7, #12] + 800b68e: 685b ldr r3, [r3, #4] + 800b690: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800b694: d111 bne.n 800b6ba + 800b696: 68fb ldr r3, [r7, #12] + 800b698: 689b ldr r3, [r3, #8] + 800b69a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800b69e: d004 beq.n 800b6aa + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800b6a0: 68fb ldr r3, [r7, #12] + 800b6a2: 689b ldr r3, [r3, #8] + 800b6a4: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800b6a8: d107 bne.n 800b6ba + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800b6aa: 68fb ldr r3, [r7, #12] + 800b6ac: 681b ldr r3, [r3, #0] + 800b6ae: 681a ldr r2, [r3, #0] + 800b6b0: 68fb ldr r3, [r7, #12] + 800b6b2: 681b ldr r3, [r3, #0] + 800b6b4: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800b6b8: 601a str r2, [r3, #0] + } -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - else if(Divider == DIVIDER_Q_UPDATE) - 8009fba: 683b ldr r3, [r7, #0] - 8009fbc: 2b01 cmp r3, #1 - 8009fbe: d112 bne.n 8009fe6 - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - 8009fc0: 4b26 ldr r3, [pc, #152] ; (800a05c ) - 8009fc2: 691b ldr r3, [r3, #16] - 8009fc4: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000 - 8009fc8: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 - 8009fcc: 687a ldr r2, [r7, #4] - 8009fce: 6892 ldr r2, [r2, #8] - 8009fd0: 0211 lsls r1, r2, #8 - 8009fd2: 687a ldr r2, [r7, #4] - 8009fd4: 6912 ldr r2, [r2, #16] - 8009fd6: 0852 lsrs r2, r2, #1 - 8009fd8: 3a01 subs r2, #1 - 8009fda: 0552 lsls r2, r2, #21 - 8009fdc: 430a orrs r2, r1 - 8009fde: 491f ldr r1, [pc, #124] ; (800a05c ) - 8009fe0: 4313 orrs r3, r2 - 8009fe2: 610b str r3, [r1, #16] - 8009fe4: e011 b.n 800a00a - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - 8009fe6: 4b1d ldr r3, [pc, #116] ; (800a05c ) - 8009fe8: 691b ldr r3, [r3, #16] - 8009fea: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000 - 8009fee: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 - 8009ff2: 687a ldr r2, [r7, #4] - 8009ff4: 6892 ldr r2, [r2, #8] - 8009ff6: 0211 lsls r1, r2, #8 - 8009ff8: 687a ldr r2, [r7, #4] - 8009ffa: 6952 ldr r2, [r2, #20] - 8009ffc: 0852 lsrs r2, r2, #1 - 8009ffe: 3a01 subs r2, #1 - 800a000: 0652 lsls r2, r2, #25 - 800a002: 430a orrs r2, r1 - 800a004: 4915 ldr r1, [pc, #84] ; (800a05c ) - 800a006: 4313 orrs r3, r2 - 800a008: 610b str r3, [r1, #16] - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 800b6ba: 68fb ldr r3, [r7, #12] + 800b6bc: 6a9b ldr r3, [r3, #40] ; 0x28 + 800b6be: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800b6c2: d10f bne.n 800b6e4 + { + SPI_RESET_CRC(hspi); + 800b6c4: 68fb ldr r3, [r7, #12] + 800b6c6: 681b ldr r3, [r3, #0] + 800b6c8: 681a ldr r2, [r3, #0] + 800b6ca: 68fb ldr r3, [r7, #12] + 800b6cc: 681b ldr r3, [r3, #0] + 800b6ce: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 800b6d2: 601a str r2, [r3, #0] + 800b6d4: 68fb ldr r3, [r7, #12] + 800b6d6: 681b ldr r3, [r3, #0] + 800b6d8: 681a ldr r2, [r3, #0] + 800b6da: 68fb ldr r3, [r7, #12] + 800b6dc: 681b ldr r3, [r3, #0] + 800b6de: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 800b6e2: 601a str r2, [r3, #0] + } - /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ - __HAL_RCC_PLLSAI1_ENABLE(); - 800a00a: 4b14 ldr r3, [pc, #80] ; (800a05c ) - 800a00c: 681b ldr r3, [r3, #0] - 800a00e: 4a13 ldr r2, [pc, #76] ; (800a05c ) - 800a010: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 - 800a014: 6013 str r3, [r2, #0] + hspi->State = HAL_SPI_STATE_READY; + 800b6e4: 68fb ldr r3, [r7, #12] + 800b6e6: 2201 movs r2, #1 + 800b6e8: f883 205d strb.w r2, [r3, #93] ; 0x5d - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - 800a016: f7fa fad1 bl 80045bc - 800a01a: 60b8 str r0, [r7, #8] + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 800b6ec: 68fb ldr r3, [r7, #12] + 800b6ee: 2200 movs r2, #0 + 800b6f0: f883 205c strb.w r2, [r3, #92] ; 0x5c - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) - 800a01c: e009 b.n 800a032 - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - 800a01e: f7fa facd bl 80045bc - 800a022: 4602 mov r2, r0 - 800a024: 68bb ldr r3, [r7, #8] - 800a026: 1ad3 subs r3, r2, r3 - 800a028: 2b02 cmp r3, #2 - 800a02a: d902 bls.n 800a032 - { - status = HAL_TIMEOUT; - 800a02c: 2303 movs r3, #3 - 800a02e: 73fb strb r3, [r7, #15] - break; - 800a030: e005 b.n 800a03e - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) - 800a032: 4b0a ldr r3, [pc, #40] ; (800a05c ) - 800a034: 681b ldr r3, [r3, #0] - 800a036: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 800a03a: 2b00 cmp r3, #0 - 800a03c: d0ef beq.n 800a01e - } + return HAL_TIMEOUT; + 800b6f4: 2303 movs r3, #3 + 800b6f6: e010 b.n 800b71a } - - if(status == HAL_OK) - 800a03e: 7bfb ldrb r3, [r7, #15] - 800a040: 2b00 cmp r3, #0 - 800a042: d106 bne.n 800a052 + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 800b6f8: 69bb ldr r3, [r7, #24] + 800b6fa: 2b00 cmp r3, #0 + 800b6fc: d101 bne.n 800b702 { - /* Configure the PLLSAI1 Clock output(s) */ - __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); - 800a044: 4b05 ldr r3, [pc, #20] ; (800a05c ) - 800a046: 691a ldr r2, [r3, #16] - 800a048: 687b ldr r3, [r7, #4] - 800a04a: 699b ldr r3, [r3, #24] - 800a04c: 4903 ldr r1, [pc, #12] ; (800a05c ) - 800a04e: 4313 orrs r3, r2 - 800a050: 610b str r3, [r1, #16] + tmp_timeout = 0U; + 800b6fe: 2300 movs r3, #0 + 800b700: 627b str r3, [r7, #36] ; 0x24 } + count--; + 800b702: 69bb ldr r3, [r7, #24] + 800b704: 3b01 subs r3, #1 + 800b706: 61bb str r3, [r7, #24] + while ((hspi->Instance->SR & Fifo) != State) + 800b708: 68fb ldr r3, [r7, #12] + 800b70a: 681b ldr r3, [r3, #0] + 800b70c: 689a ldr r2, [r3, #8] + 800b70e: 68bb ldr r3, [r7, #8] + 800b710: 4013 ands r3, r2 + 800b712: 687a ldr r2, [r7, #4] + 800b714: 429a cmp r2, r3 + 800b716: d196 bne.n 800b646 } } - return status; - 800a052: 7bfb ldrb r3, [r7, #15] + return HAL_OK; + 800b718: 2300 movs r3, #0 +} + 800b71a: 4618 mov r0, r3 + 800b71c: 3728 adds r7, #40 ; 0x28 + 800b71e: 46bd mov sp, r7 + 800b720: bd80 pop {r7, pc} + 800b722: bf00 nop + 800b724: 20000020 .word 0x20000020 + +0800b728 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800b728: b580 push {r7, lr} + 800b72a: b086 sub sp, #24 + 800b72c: af02 add r7, sp, #8 + 800b72e: 60f8 str r0, [r7, #12] + 800b730: 60b9 str r1, [r7, #8] + 800b732: 607a str r2, [r7, #4] + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800b734: 68fb ldr r3, [r7, #12] + 800b736: 685b ldr r3, [r3, #4] + 800b738: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800b73c: d111 bne.n 800b762 + 800b73e: 68fb ldr r3, [r7, #12] + 800b740: 689b ldr r3, [r3, #8] + 800b742: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800b746: d004 beq.n 800b752 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800b748: 68fb ldr r3, [r7, #12] + 800b74a: 689b ldr r3, [r3, #8] + 800b74c: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800b750: d107 bne.n 800b762 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800b752: 68fb ldr r3, [r7, #12] + 800b754: 681b ldr r3, [r3, #0] + 800b756: 681a ldr r2, [r3, #0] + 800b758: 68fb ldr r3, [r7, #12] + 800b75a: 681b ldr r3, [r3, #0] + 800b75c: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800b760: 601a str r2, [r3, #0] + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 800b762: 687b ldr r3, [r7, #4] + 800b764: 9300 str r3, [sp, #0] + 800b766: 68bb ldr r3, [r7, #8] + 800b768: 2200 movs r2, #0 + 800b76a: 2180 movs r1, #128 ; 0x80 + 800b76c: 68f8 ldr r0, [r7, #12] + 800b76e: f7ff febd bl 800b4ec + 800b772: 4603 mov r3, r0 + 800b774: 2b00 cmp r3, #0 + 800b776: d007 beq.n 800b788 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800b778: 68fb ldr r3, [r7, #12] + 800b77a: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b77c: f043 0220 orr.w r2, r3, #32 + 800b780: 68fb ldr r3, [r7, #12] + 800b782: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800b784: 2303 movs r3, #3 + 800b786: e023 b.n 800b7d0 + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800b788: 68fb ldr r3, [r7, #12] + 800b78a: 685b ldr r3, [r3, #4] + 800b78c: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 800b790: d11d bne.n 800b7ce + 800b792: 68fb ldr r3, [r7, #12] + 800b794: 689b ldr r3, [r3, #8] + 800b796: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800b79a: d004 beq.n 800b7a6 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800b79c: 68fb ldr r3, [r7, #12] + 800b79e: 689b ldr r3, [r3, #8] + 800b7a0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800b7a4: d113 bne.n 800b7ce + { + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 800b7a6: 687b ldr r3, [r7, #4] + 800b7a8: 9300 str r3, [sp, #0] + 800b7aa: 68bb ldr r3, [r7, #8] + 800b7ac: 2200 movs r2, #0 + 800b7ae: f44f 61c0 mov.w r1, #1536 ; 0x600 + 800b7b2: 68f8 ldr r0, [r7, #12] + 800b7b4: f7ff ff22 bl 800b5fc + 800b7b8: 4603 mov r3, r0 + 800b7ba: 2b00 cmp r3, #0 + 800b7bc: d007 beq.n 800b7ce + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800b7be: 68fb ldr r3, [r7, #12] + 800b7c0: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b7c2: f043 0220 orr.w r2, r3, #32 + 800b7c6: 68fb ldr r3, [r7, #12] + 800b7c8: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800b7ca: 2303 movs r3, #3 + 800b7cc: e000 b.n 800b7d0 + } + } + return HAL_OK; + 800b7ce: 2300 movs r3, #0 +} + 800b7d0: 4618 mov r0, r3 + 800b7d2: 3710 adds r7, #16 + 800b7d4: 46bd mov sp, r7 + 800b7d6: bd80 pop {r7, pc} + +0800b7d8 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800b7d8: b580 push {r7, lr} + 800b7da: b086 sub sp, #24 + 800b7dc: af02 add r7, sp, #8 + 800b7de: 60f8 str r0, [r7, #12] + 800b7e0: 60b9 str r1, [r7, #8] + 800b7e2: 607a str r2, [r7, #4] + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 800b7e4: 687b ldr r3, [r7, #4] + 800b7e6: 9300 str r3, [sp, #0] + 800b7e8: 68bb ldr r3, [r7, #8] + 800b7ea: 2200 movs r2, #0 + 800b7ec: f44f 51c0 mov.w r1, #6144 ; 0x1800 + 800b7f0: 68f8 ldr r0, [r7, #12] + 800b7f2: f7ff ff03 bl 800b5fc + 800b7f6: 4603 mov r3, r0 + 800b7f8: 2b00 cmp r3, #0 + 800b7fa: d007 beq.n 800b80c + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800b7fc: 68fb ldr r3, [r7, #12] + 800b7fe: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b800: f043 0220 orr.w r2, r3, #32 + 800b804: 68fb ldr r3, [r7, #12] + 800b806: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800b808: 2303 movs r3, #3 + 800b80a: e027 b.n 800b85c + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 800b80c: 687b ldr r3, [r7, #4] + 800b80e: 9300 str r3, [sp, #0] + 800b810: 68bb ldr r3, [r7, #8] + 800b812: 2200 movs r2, #0 + 800b814: 2180 movs r1, #128 ; 0x80 + 800b816: 68f8 ldr r0, [r7, #12] + 800b818: f7ff fe68 bl 800b4ec + 800b81c: 4603 mov r3, r0 + 800b81e: 2b00 cmp r3, #0 + 800b820: d007 beq.n 800b832 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800b822: 68fb ldr r3, [r7, #12] + 800b824: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b826: f043 0220 orr.w r2, r3, #32 + 800b82a: 68fb ldr r3, [r7, #12] + 800b82c: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800b82e: 2303 movs r3, #3 + 800b830: e014 b.n 800b85c + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 800b832: 687b ldr r3, [r7, #4] + 800b834: 9300 str r3, [sp, #0] + 800b836: 68bb ldr r3, [r7, #8] + 800b838: 2200 movs r2, #0 + 800b83a: f44f 61c0 mov.w r1, #1536 ; 0x600 + 800b83e: 68f8 ldr r0, [r7, #12] + 800b840: f7ff fedc bl 800b5fc + 800b844: 4603 mov r3, r0 + 800b846: 2b00 cmp r3, #0 + 800b848: d007 beq.n 800b85a + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800b84a: 68fb ldr r3, [r7, #12] + 800b84c: 6e1b ldr r3, [r3, #96] ; 0x60 + 800b84e: f043 0220 orr.w r2, r3, #32 + 800b852: 68fb ldr r3, [r7, #12] + 800b854: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800b856: 2303 movs r3, #3 + 800b858: e000 b.n 800b85c + } + + return HAL_OK; + 800b85a: 2300 movs r3, #0 } - 800a054: 4618 mov r0, r3 - 800a056: 3710 adds r7, #16 - 800a058: 46bd mov sp, r7 - 800a05a: bd80 pop {r7, pc} - 800a05c: 40021000 .word 0x40021000 + 800b85c: 4618 mov r0, r3 + 800b85e: 3710 adds r7, #16 + 800b860: 46bd mov sp, r7 + 800b862: bd80 pop {r7, pc} -0800a060 : +0800b864 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 800a060: b580 push {r7, lr} - 800a062: b082 sub sp, #8 - 800a064: af00 add r7, sp, #0 - 800a066: 6078 str r0, [r7, #4] + 800b864: b580 push {r7, lr} + 800b866: b082 sub sp, #8 + 800b868: af00 add r7, sp, #0 + 800b86a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 800a068: 687b ldr r3, [r7, #4] - 800a06a: 2b00 cmp r3, #0 - 800a06c: d101 bne.n 800a072 + 800b86c: 687b ldr r3, [r7, #4] + 800b86e: 2b00 cmp r3, #0 + 800b870: d101 bne.n 800b876 { return HAL_ERROR; - 800a06e: 2301 movs r3, #1 - 800a070: e049 b.n 800a106 + 800b872: 2301 movs r3, #1 + 800b874: e049 b.n 800b90a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 800a072: 687b ldr r3, [r7, #4] - 800a074: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 800a078: b2db uxtb r3, r3 - 800a07a: 2b00 cmp r3, #0 - 800a07c: d106 bne.n 800a08c + 800b876: 687b ldr r3, [r7, #4] + 800b878: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 800b87c: b2db uxtb r3, r3 + 800b87e: 2b00 cmp r3, #0 + 800b880: d106 bne.n 800b890 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 800a07e: 687b ldr r3, [r7, #4] - 800a080: 2200 movs r2, #0 - 800a082: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800b882: 687b ldr r3, [r7, #4] + 800b884: 2200 movs r2, #0 + 800b886: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 800a086: 6878 ldr r0, [r7, #4] - 800a088: f7fa f862 bl 8004150 + 800b88a: 6878 ldr r0, [r7, #4] + 800b88c: f7f9 fa96 bl 8004dbc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 800a08c: 687b ldr r3, [r7, #4] - 800a08e: 2202 movs r2, #2 - 800a090: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800b890: 687b ldr r3, [r7, #4] + 800b892: 2202 movs r2, #2 + 800b894: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 800a094: 687b ldr r3, [r7, #4] - 800a096: 681a ldr r2, [r3, #0] - 800a098: 687b ldr r3, [r7, #4] - 800a09a: 3304 adds r3, #4 - 800a09c: 4619 mov r1, r3 - 800a09e: 4610 mov r0, r2 - 800a0a0: f000 fa80 bl 800a5a4 + 800b898: 687b ldr r3, [r7, #4] + 800b89a: 681a ldr r2, [r3, #0] + 800b89c: 687b ldr r3, [r7, #4] + 800b89e: 3304 adds r3, #4 + 800b8a0: 4619 mov r1, r3 + 800b8a2: 4610 mov r0, r2 + 800b8a4: f000 f94c bl 800bb40 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 800a0a4: 687b ldr r3, [r7, #4] - 800a0a6: 2201 movs r2, #1 - 800a0a8: f883 2048 strb.w r2, [r3, #72] ; 0x48 + 800b8a8: 687b ldr r3, [r7, #4] + 800b8aa: 2201 movs r2, #1 + 800b8ac: f883 2048 strb.w r2, [r3, #72] ; 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 800a0ac: 687b ldr r3, [r7, #4] - 800a0ae: 2201 movs r2, #1 - 800a0b0: f883 203e strb.w r2, [r3, #62] ; 0x3e - 800a0b4: 687b ldr r3, [r7, #4] - 800a0b6: 2201 movs r2, #1 - 800a0b8: f883 203f strb.w r2, [r3, #63] ; 0x3f - 800a0bc: 687b ldr r3, [r7, #4] - 800a0be: 2201 movs r2, #1 - 800a0c0: f883 2040 strb.w r2, [r3, #64] ; 0x40 - 800a0c4: 687b ldr r3, [r7, #4] - 800a0c6: 2201 movs r2, #1 - 800a0c8: f883 2041 strb.w r2, [r3, #65] ; 0x41 - 800a0cc: 687b ldr r3, [r7, #4] - 800a0ce: 2201 movs r2, #1 - 800a0d0: f883 2042 strb.w r2, [r3, #66] ; 0x42 - 800a0d4: 687b ldr r3, [r7, #4] - 800a0d6: 2201 movs r2, #1 - 800a0d8: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 800b8b0: 687b ldr r3, [r7, #4] + 800b8b2: 2201 movs r2, #1 + 800b8b4: f883 203e strb.w r2, [r3, #62] ; 0x3e + 800b8b8: 687b ldr r3, [r7, #4] + 800b8ba: 2201 movs r2, #1 + 800b8bc: f883 203f strb.w r2, [r3, #63] ; 0x3f + 800b8c0: 687b ldr r3, [r7, #4] + 800b8c2: 2201 movs r2, #1 + 800b8c4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 800b8c8: 687b ldr r3, [r7, #4] + 800b8ca: 2201 movs r2, #1 + 800b8cc: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 800b8d0: 687b ldr r3, [r7, #4] + 800b8d2: 2201 movs r2, #1 + 800b8d4: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 800b8d8: 687b ldr r3, [r7, #4] + 800b8da: 2201 movs r2, #1 + 800b8dc: f883 2043 strb.w r2, [r3, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 800a0dc: 687b ldr r3, [r7, #4] - 800a0de: 2201 movs r2, #1 - 800a0e0: f883 2044 strb.w r2, [r3, #68] ; 0x44 - 800a0e4: 687b ldr r3, [r7, #4] - 800a0e6: 2201 movs r2, #1 - 800a0e8: f883 2045 strb.w r2, [r3, #69] ; 0x45 - 800a0ec: 687b ldr r3, [r7, #4] - 800a0ee: 2201 movs r2, #1 - 800a0f0: f883 2046 strb.w r2, [r3, #70] ; 0x46 - 800a0f4: 687b ldr r3, [r7, #4] - 800a0f6: 2201 movs r2, #1 - 800a0f8: f883 2047 strb.w r2, [r3, #71] ; 0x47 + 800b8e0: 687b ldr r3, [r7, #4] + 800b8e2: 2201 movs r2, #1 + 800b8e4: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800b8e8: 687b ldr r3, [r7, #4] + 800b8ea: 2201 movs r2, #1 + 800b8ec: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 800b8f0: 687b ldr r3, [r7, #4] + 800b8f2: 2201 movs r2, #1 + 800b8f4: f883 2046 strb.w r2, [r3, #70] ; 0x46 + 800b8f8: 687b ldr r3, [r7, #4] + 800b8fa: 2201 movs r2, #1 + 800b8fc: f883 2047 strb.w r2, [r3, #71] ; 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 800a0fc: 687b ldr r3, [r7, #4] - 800a0fe: 2201 movs r2, #1 - 800a100: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800b900: 687b ldr r3, [r7, #4] + 800b902: 2201 movs r2, #1 + 800b904: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; - 800a104: 2300 movs r3, #0 + 800b908: 2300 movs r3, #0 } - 800a106: 4618 mov r0, r3 - 800a108: 3708 adds r7, #8 - 800a10a: 46bd mov sp, r7 - 800a10c: bd80 pop {r7, pc} + 800b90a: 4618 mov r0, r3 + 800b90c: 3708 adds r7, #8 + 800b90e: 46bd mov sp, r7 + 800b910: bd80 pop {r7, pc} ... -0800a110 : +0800b914 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { - 800a110: b480 push {r7} - 800a112: b085 sub sp, #20 - 800a114: af00 add r7, sp, #0 - 800a116: 6078 str r0, [r7, #4] + 800b914: b480 push {r7} + 800b916: b085 sub sp, #20 + 800b918: af00 add r7, sp, #0 + 800b91a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - 800a118: 687b ldr r3, [r7, #4] - 800a11a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 800a11e: b2db uxtb r3, r3 - 800a120: 2b01 cmp r3, #1 - 800a122: d001 beq.n 800a128 - { - return HAL_ERROR; - 800a124: 2301 movs r3, #1 - 800a126: e033 b.n 800a190 - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - 800a128: 687b ldr r3, [r7, #4] - 800a12a: 2202 movs r2, #2 - 800a12c: f883 203d strb.w r2, [r3, #61] ; 0x3d - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 800a130: 687b ldr r3, [r7, #4] - 800a132: 681b ldr r3, [r3, #0] - 800a134: 4a19 ldr r2, [pc, #100] ; (800a19c ) - 800a136: 4293 cmp r3, r2 - 800a138: d009 beq.n 800a14e - 800a13a: 687b ldr r3, [r7, #4] - 800a13c: 681b ldr r3, [r3, #0] - 800a13e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 800a142: d004 beq.n 800a14e - 800a144: 687b ldr r3, [r7, #4] - 800a146: 681b ldr r3, [r3, #0] - 800a148: 4a15 ldr r2, [pc, #84] ; (800a1a0 ) - 800a14a: 4293 cmp r3, r2 - 800a14c: d115 bne.n 800a17a - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - 800a14e: 687b ldr r3, [r7, #4] - 800a150: 681b ldr r3, [r3, #0] - 800a152: 689a ldr r2, [r3, #8] - 800a154: 4b13 ldr r3, [pc, #76] ; (800a1a4 ) - 800a156: 4013 ands r3, r2 - 800a158: 60fb str r3, [r7, #12] - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 800a15a: 68fb ldr r3, [r7, #12] - 800a15c: 2b06 cmp r3, #6 - 800a15e: d015 beq.n 800a18c - 800a160: 68fb ldr r3, [r7, #12] - 800a162: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800a166: d011 beq.n 800a18c - { - __HAL_TIM_ENABLE(htim); - 800a168: 687b ldr r3, [r7, #4] - 800a16a: 681b ldr r3, [r3, #0] - 800a16c: 681a ldr r2, [r3, #0] - 800a16e: 687b ldr r3, [r7, #4] - 800a170: 681b ldr r3, [r3, #0] - 800a172: f042 0201 orr.w r2, r2, #1 - 800a176: 601a str r2, [r3, #0] - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 800a178: e008 b.n 800a18c - } - } - else - { - __HAL_TIM_ENABLE(htim); - 800a17a: 687b ldr r3, [r7, #4] - 800a17c: 681b ldr r3, [r3, #0] - 800a17e: 681a ldr r2, [r3, #0] - 800a180: 687b ldr r3, [r7, #4] - 800a182: 681b ldr r3, [r3, #0] - 800a184: f042 0201 orr.w r2, r2, #1 - 800a188: 601a str r2, [r3, #0] - 800a18a: e000 b.n 800a18e - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 800a18c: bf00 nop - } - - /* Return function status */ - return HAL_OK; - 800a18e: 2300 movs r3, #0 -} - 800a190: 4618 mov r0, r3 - 800a192: 3714 adds r7, #20 - 800a194: 46bd mov sp, r7 - 800a196: f85d 7b04 ldr.w r7, [sp], #4 - 800a19a: 4770 bx lr - 800a19c: 40012c00 .word 0x40012c00 - 800a1a0: 40014000 .word 0x40014000 - 800a1a4: 00010007 .word 0x00010007 - -0800a1a8 : - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - 800a1a8: b580 push {r7, lr} - 800a1aa: b084 sub sp, #16 - 800a1ac: af00 add r7, sp, #0 - 800a1ae: 6078 str r0, [r7, #4] - uint32_t itsource = htim->Instance->DIER; - 800a1b0: 687b ldr r3, [r7, #4] - 800a1b2: 681b ldr r3, [r3, #0] - 800a1b4: 68db ldr r3, [r3, #12] - 800a1b6: 60fb str r3, [r7, #12] - uint32_t itflag = htim->Instance->SR; - 800a1b8: 687b ldr r3, [r7, #4] - 800a1ba: 681b ldr r3, [r3, #0] - 800a1bc: 691b ldr r3, [r3, #16] - 800a1be: 60bb str r3, [r7, #8] - - /* Capture compare 1 event */ - if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 800a1c0: 68bb ldr r3, [r7, #8] - 800a1c2: f003 0302 and.w r3, r3, #2 - 800a1c6: 2b00 cmp r3, #0 - 800a1c8: d020 beq.n 800a20c - { - if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 800a1ca: 68fb ldr r3, [r7, #12] - 800a1cc: f003 0302 and.w r3, r3, #2 - 800a1d0: 2b00 cmp r3, #0 - 800a1d2: d01b beq.n 800a20c - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - 800a1d4: 687b ldr r3, [r7, #4] - 800a1d6: 681b ldr r3, [r3, #0] - 800a1d8: f06f 0202 mvn.w r2, #2 - 800a1dc: 611a str r2, [r3, #16] - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 800a1de: 687b ldr r3, [r7, #4] - 800a1e0: 2201 movs r2, #1 - 800a1e2: 771a strb r2, [r3, #28] - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 800a1e4: 687b ldr r3, [r7, #4] - 800a1e6: 681b ldr r3, [r3, #0] - 800a1e8: 699b ldr r3, [r3, #24] - 800a1ea: f003 0303 and.w r3, r3, #3 - 800a1ee: 2b00 cmp r3, #0 - 800a1f0: d003 beq.n 800a1fa - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); - 800a1f2: 6878 ldr r0, [r7, #4] - 800a1f4: f000 f9b7 bl 800a566 - 800a1f8: e005 b.n 800a206 - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - 800a1fa: 6878 ldr r0, [r7, #4] - 800a1fc: f000 f9a9 bl 800a552 - HAL_TIM_PWM_PulseFinishedCallback(htim); - 800a200: 6878 ldr r0, [r7, #4] - 800a202: f000 f9ba bl 800a57a -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800a206: 687b ldr r3, [r7, #4] - 800a208: 2200 movs r2, #0 - 800a20a: 771a strb r2, [r3, #28] - } - } - } - /* Capture compare 2 event */ - if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 800a20c: 68bb ldr r3, [r7, #8] - 800a20e: f003 0304 and.w r3, r3, #4 - 800a212: 2b00 cmp r3, #0 - 800a214: d020 beq.n 800a258 - { - if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 800a216: 68fb ldr r3, [r7, #12] - 800a218: f003 0304 and.w r3, r3, #4 - 800a21c: 2b00 cmp r3, #0 - 800a21e: d01b beq.n 800a258 - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - 800a220: 687b ldr r3, [r7, #4] - 800a222: 681b ldr r3, [r3, #0] - 800a224: f06f 0204 mvn.w r2, #4 - 800a228: 611a str r2, [r3, #16] - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 800a22a: 687b ldr r3, [r7, #4] - 800a22c: 2202 movs r2, #2 - 800a22e: 771a strb r2, [r3, #28] - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 800a230: 687b ldr r3, [r7, #4] - 800a232: 681b ldr r3, [r3, #0] - 800a234: 699b ldr r3, [r3, #24] - 800a236: f403 7340 and.w r3, r3, #768 ; 0x300 - 800a23a: 2b00 cmp r3, #0 - 800a23c: d003 beq.n 800a246 - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); - 800a23e: 6878 ldr r0, [r7, #4] - 800a240: f000 f991 bl 800a566 - 800a244: e005 b.n 800a252 - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - 800a246: 6878 ldr r0, [r7, #4] - 800a248: f000 f983 bl 800a552 - HAL_TIM_PWM_PulseFinishedCallback(htim); - 800a24c: 6878 ldr r0, [r7, #4] - 800a24e: f000 f994 bl 800a57a -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800a252: 687b ldr r3, [r7, #4] - 800a254: 2200 movs r2, #0 - 800a256: 771a strb r2, [r3, #28] - } - } - /* Capture compare 3 event */ - if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 800a258: 68bb ldr r3, [r7, #8] - 800a25a: f003 0308 and.w r3, r3, #8 - 800a25e: 2b00 cmp r3, #0 - 800a260: d020 beq.n 800a2a4 - { - if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 800a262: 68fb ldr r3, [r7, #12] - 800a264: f003 0308 and.w r3, r3, #8 - 800a268: 2b00 cmp r3, #0 - 800a26a: d01b beq.n 800a2a4 - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - 800a26c: 687b ldr r3, [r7, #4] - 800a26e: 681b ldr r3, [r3, #0] - 800a270: f06f 0208 mvn.w r2, #8 - 800a274: 611a str r2, [r3, #16] - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 800a276: 687b ldr r3, [r7, #4] - 800a278: 2204 movs r2, #4 - 800a27a: 771a strb r2, [r3, #28] - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 800a27c: 687b ldr r3, [r7, #4] - 800a27e: 681b ldr r3, [r3, #0] - 800a280: 69db ldr r3, [r3, #28] - 800a282: f003 0303 and.w r3, r3, #3 - 800a286: 2b00 cmp r3, #0 - 800a288: d003 beq.n 800a292 - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); - 800a28a: 6878 ldr r0, [r7, #4] - 800a28c: f000 f96b bl 800a566 - 800a290: e005 b.n 800a29e - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - 800a292: 6878 ldr r0, [r7, #4] - 800a294: f000 f95d bl 800a552 - HAL_TIM_PWM_PulseFinishedCallback(htim); - 800a298: 6878 ldr r0, [r7, #4] - 800a29a: f000 f96e bl 800a57a -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800a29e: 687b ldr r3, [r7, #4] - 800a2a0: 2200 movs r2, #0 - 800a2a2: 771a strb r2, [r3, #28] - } - } - /* Capture compare 4 event */ - if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 800a2a4: 68bb ldr r3, [r7, #8] - 800a2a6: f003 0310 and.w r3, r3, #16 - 800a2aa: 2b00 cmp r3, #0 - 800a2ac: d020 beq.n 800a2f0 - { - if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 800a2ae: 68fb ldr r3, [r7, #12] - 800a2b0: f003 0310 and.w r3, r3, #16 - 800a2b4: 2b00 cmp r3, #0 - 800a2b6: d01b beq.n 800a2f0 - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - 800a2b8: 687b ldr r3, [r7, #4] - 800a2ba: 681b ldr r3, [r3, #0] - 800a2bc: f06f 0210 mvn.w r2, #16 - 800a2c0: 611a str r2, [r3, #16] - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 800a2c2: 687b ldr r3, [r7, #4] - 800a2c4: 2208 movs r2, #8 - 800a2c6: 771a strb r2, [r3, #28] - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 800a2c8: 687b ldr r3, [r7, #4] - 800a2ca: 681b ldr r3, [r3, #0] - 800a2cc: 69db ldr r3, [r3, #28] - 800a2ce: f403 7340 and.w r3, r3, #768 ; 0x300 - 800a2d2: 2b00 cmp r3, #0 - 800a2d4: d003 beq.n 800a2de - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); - 800a2d6: 6878 ldr r0, [r7, #4] - 800a2d8: f000 f945 bl 800a566 - 800a2dc: e005 b.n 800a2ea - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - 800a2de: 6878 ldr r0, [r7, #4] - 800a2e0: f000 f937 bl 800a552 - HAL_TIM_PWM_PulseFinishedCallback(htim); - 800a2e4: 6878 ldr r0, [r7, #4] - 800a2e6: f000 f948 bl 800a57a -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 800a2ea: 687b ldr r3, [r7, #4] - 800a2ec: 2200 movs r2, #0 - 800a2ee: 771a strb r2, [r3, #28] - } - } - /* TIM Update event */ - if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 800a2f0: 68bb ldr r3, [r7, #8] - 800a2f2: f003 0301 and.w r3, r3, #1 - 800a2f6: 2b00 cmp r3, #0 - 800a2f8: d00c beq.n 800a314 - { - if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 800a2fa: 68fb ldr r3, [r7, #12] - 800a2fc: f003 0301 and.w r3, r3, #1 - 800a300: 2b00 cmp r3, #0 - 800a302: d007 beq.n 800a314 - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - 800a304: 687b ldr r3, [r7, #4] - 800a306: 681b ldr r3, [r3, #0] - 800a308: f06f 0201 mvn.w r2, #1 - 800a30c: 611a str r2, [r3, #16] -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); - 800a30e: 6878 ldr r0, [r7, #4] - 800a310: f000 f915 bl 800a53e -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break input event */ - if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) - 800a314: 68bb ldr r3, [r7, #8] - 800a316: f003 0380 and.w r3, r3, #128 ; 0x80 - 800a31a: 2b00 cmp r3, #0 - 800a31c: d00c beq.n 800a338 - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 800a31e: 68fb ldr r3, [r7, #12] - 800a320: f003 0380 and.w r3, r3, #128 ; 0x80 - 800a324: 2b00 cmp r3, #0 - 800a326: d007 beq.n 800a338 - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - 800a328: 687b ldr r3, [r7, #4] - 800a32a: 681b ldr r3, [r3, #0] - 800a32c: f06f 0280 mvn.w r2, #128 ; 0x80 - 800a330: 611a str r2, [r3, #16] -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->BreakCallback(htim); -#else - HAL_TIMEx_BreakCallback(htim); - 800a332: 6878 ldr r0, [r7, #4] - 800a334: f000 faa4 bl 800a880 -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break2 input event */ - if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - 800a338: 68bb ldr r3, [r7, #8] - 800a33a: f403 7380 and.w r3, r3, #256 ; 0x100 - 800a33e: 2b00 cmp r3, #0 - 800a340: d00c beq.n 800a35c - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 800a342: 68fb ldr r3, [r7, #12] - 800a344: f003 0380 and.w r3, r3, #128 ; 0x80 - 800a348: 2b00 cmp r3, #0 - 800a34a: d007 beq.n 800a35c - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 800a34c: 687b ldr r3, [r7, #4] - 800a34e: 681b ldr r3, [r3, #0] - 800a350: f46f 7280 mvn.w r2, #256 ; 0x100 - 800a354: 611a str r2, [r3, #16] -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->Break2Callback(htim); -#else - HAL_TIMEx_Break2Callback(htim); - 800a356: 6878 ldr r0, [r7, #4] - 800a358: f000 fa9c bl 800a894 -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 800b91c: 687b ldr r3, [r7, #4] + 800b91e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 800b922: b2db uxtb r3, r3 + 800b924: 2b01 cmp r3, #1 + 800b926: d001 beq.n 800b92c + { + return HAL_ERROR; + 800b928: 2301 movs r3, #1 + 800b92a: e033 b.n 800b994 } - /* TIM Trigger detection event */ - if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 800a35c: 68bb ldr r3, [r7, #8] - 800a35e: f003 0340 and.w r3, r3, #64 ; 0x40 - 800a362: 2b00 cmp r3, #0 - 800a364: d00c beq.n 800a380 - { - if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 800a366: 68fb ldr r3, [r7, #12] - 800a368: f003 0340 and.w r3, r3, #64 ; 0x40 - 800a36c: 2b00 cmp r3, #0 - 800a36e: d007 beq.n 800a380 + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800b92c: 687b ldr r3, [r7, #4] + 800b92e: 2202 movs r2, #2 + 800b930: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800b934: 687b ldr r3, [r7, #4] + 800b936: 681b ldr r3, [r3, #0] + 800b938: 4a19 ldr r2, [pc, #100] ; (800b9a0 ) + 800b93a: 4293 cmp r3, r2 + 800b93c: d009 beq.n 800b952 + 800b93e: 687b ldr r3, [r7, #4] + 800b940: 681b ldr r3, [r3, #0] + 800b942: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800b946: d004 beq.n 800b952 + 800b948: 687b ldr r3, [r7, #4] + 800b94a: 681b ldr r3, [r3, #0] + 800b94c: 4a15 ldr r2, [pc, #84] ; (800b9a4 ) + 800b94e: 4293 cmp r3, r2 + 800b950: d115 bne.n 800b97e + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 800b952: 687b ldr r3, [r7, #4] + 800b954: 681b ldr r3, [r3, #0] + 800b956: 689a ldr r2, [r3, #8] + 800b958: 4b13 ldr r3, [pc, #76] ; (800b9a8 ) + 800b95a: 4013 ands r3, r2 + 800b95c: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800b95e: 68fb ldr r3, [r7, #12] + 800b960: 2b06 cmp r3, #6 + 800b962: d015 beq.n 800b990 + 800b964: 68fb ldr r3, [r7, #12] + 800b966: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800b96a: d011 beq.n 800b990 { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - 800a370: 687b ldr r3, [r7, #4] - 800a372: 681b ldr r3, [r3, #0] - 800a374: f06f 0240 mvn.w r2, #64 ; 0x40 - 800a378: 611a str r2, [r3, #16] -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); - 800a37a: 6878 ldr r0, [r7, #4] - 800a37c: f000 f907 bl 800a58e -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + __HAL_TIM_ENABLE(htim); + 800b96c: 687b ldr r3, [r7, #4] + 800b96e: 681b ldr r3, [r3, #0] + 800b970: 681a ldr r2, [r3, #0] + 800b972: 687b ldr r3, [r7, #4] + 800b974: 681b ldr r3, [r3, #0] + 800b976: f042 0201 orr.w r2, r2, #1 + 800b97a: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800b97c: e008 b.n 800b990 } } - /* TIM commutation event */ - if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 800a380: 68bb ldr r3, [r7, #8] - 800a382: f003 0320 and.w r3, r3, #32 - 800a386: 2b00 cmp r3, #0 - 800a388: d00c beq.n 800a3a4 - { - if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 800a38a: 68fb ldr r3, [r7, #12] - 800a38c: f003 0320 and.w r3, r3, #32 - 800a390: 2b00 cmp r3, #0 - 800a392: d007 beq.n 800a3a4 - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - 800a394: 687b ldr r3, [r7, #4] - 800a396: 681b ldr r3, [r3, #0] - 800a398: f06f 0220 mvn.w r2, #32 - 800a39c: 611a str r2, [r3, #16] -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); - 800a39e: 6878 ldr r0, [r7, #4] - 800a3a0: f000 fa64 bl 800a86c -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } + else + { + __HAL_TIM_ENABLE(htim); + 800b97e: 687b ldr r3, [r7, #4] + 800b980: 681b ldr r3, [r3, #0] + 800b982: 681a ldr r2, [r3, #0] + 800b984: 687b ldr r3, [r7, #4] + 800b986: 681b ldr r3, [r3, #0] + 800b988: f042 0201 orr.w r2, r2, #1 + 800b98c: 601a str r2, [r3, #0] + 800b98e: e000 b.n 800b992 + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800b990: bf00 nop } -} - 800a3a4: bf00 nop - 800a3a6: 3710 adds r7, #16 - 800a3a8: 46bd mov sp, r7 - 800a3aa: bd80 pop {r7, pc} -0800a3ac : + /* Return function status */ + return HAL_OK; + 800b992: 2300 movs r3, #0 +} + 800b994: 4618 mov r0, r3 + 800b996: 3714 adds r7, #20 + 800b998: 46bd mov sp, r7 + 800b99a: f85d 7b04 ldr.w r7, [sp], #4 + 800b99e: 4770 bx lr + 800b9a0: 40012c00 .word 0x40012c00 + 800b9a4: 40014000 .word 0x40014000 + 800b9a8: 00010007 .word 0x00010007 + +0800b9ac : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { - 800a3ac: b580 push {r7, lr} - 800a3ae: b084 sub sp, #16 - 800a3b0: af00 add r7, sp, #0 - 800a3b2: 6078 str r0, [r7, #4] - 800a3b4: 6039 str r1, [r7, #0] + 800b9ac: b580 push {r7, lr} + 800b9ae: b084 sub sp, #16 + 800b9b0: af00 add r7, sp, #0 + 800b9b2: 6078 str r0, [r7, #4] + 800b9b4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 800a3b6: 2300 movs r3, #0 - 800a3b8: 73fb strb r3, [r7, #15] + 800b9b6: 2300 movs r3, #0 + 800b9b8: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); - 800a3ba: 687b ldr r3, [r7, #4] - 800a3bc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c - 800a3c0: 2b01 cmp r3, #1 - 800a3c2: d101 bne.n 800a3c8 - 800a3c4: 2302 movs r3, #2 - 800a3c6: e0b6 b.n 800a536 - 800a3c8: 687b ldr r3, [r7, #4] - 800a3ca: 2201 movs r2, #1 - 800a3cc: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800b9ba: 687b ldr r3, [r7, #4] + 800b9bc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800b9c0: 2b01 cmp r3, #1 + 800b9c2: d101 bne.n 800b9c8 + 800b9c4: 2302 movs r3, #2 + 800b9c6: e0b6 b.n 800bb36 + 800b9c8: 687b ldr r3, [r7, #4] + 800b9ca: 2201 movs r2, #1 + 800b9cc: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; - 800a3d0: 687b ldr r3, [r7, #4] - 800a3d2: 2202 movs r2, #2 - 800a3d4: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800b9d0: 687b ldr r3, [r7, #4] + 800b9d2: 2202 movs r2, #2 + 800b9d4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; - 800a3d8: 687b ldr r3, [r7, #4] - 800a3da: 681b ldr r3, [r3, #0] - 800a3dc: 689b ldr r3, [r3, #8] - 800a3de: 60bb str r3, [r7, #8] + 800b9d8: 687b ldr r3, [r7, #4] + 800b9da: 681b ldr r3, [r3, #0] + 800b9dc: 689b ldr r3, [r3, #8] + 800b9de: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - 800a3e0: 68bb ldr r3, [r7, #8] - 800a3e2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 800a3e6: f023 0377 bic.w r3, r3, #119 ; 0x77 - 800a3ea: 60bb str r3, [r7, #8] + 800b9e0: 68bb ldr r3, [r7, #8] + 800b9e2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800b9e6: f023 0377 bic.w r3, r3, #119 ; 0x77 + 800b9ea: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 800a3ec: 68bb ldr r3, [r7, #8] - 800a3ee: f423 437f bic.w r3, r3, #65280 ; 0xff00 - 800a3f2: 60bb str r3, [r7, #8] + 800b9ec: 68bb ldr r3, [r7, #8] + 800b9ee: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 800b9f2: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; - 800a3f4: 687b ldr r3, [r7, #4] - 800a3f6: 681b ldr r3, [r3, #0] - 800a3f8: 68ba ldr r2, [r7, #8] - 800a3fa: 609a str r2, [r3, #8] + 800b9f4: 687b ldr r3, [r7, #4] + 800b9f6: 681b ldr r3, [r3, #0] + 800b9f8: 68ba ldr r2, [r7, #8] + 800b9fa: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) - 800a3fc: 683b ldr r3, [r7, #0] - 800a3fe: 681b ldr r3, [r3, #0] - 800a400: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 800a404: d03e beq.n 800a484 - 800a406: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 800a40a: f200 8087 bhi.w 800a51c - 800a40e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 800a412: f000 8086 beq.w 800a522 - 800a416: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 800a41a: d87f bhi.n 800a51c - 800a41c: 2b70 cmp r3, #112 ; 0x70 - 800a41e: d01a beq.n 800a456 - 800a420: 2b70 cmp r3, #112 ; 0x70 - 800a422: d87b bhi.n 800a51c - 800a424: 2b60 cmp r3, #96 ; 0x60 - 800a426: d050 beq.n 800a4ca - 800a428: 2b60 cmp r3, #96 ; 0x60 - 800a42a: d877 bhi.n 800a51c - 800a42c: 2b50 cmp r3, #80 ; 0x50 - 800a42e: d03c beq.n 800a4aa - 800a430: 2b50 cmp r3, #80 ; 0x50 - 800a432: d873 bhi.n 800a51c - 800a434: 2b40 cmp r3, #64 ; 0x40 - 800a436: d058 beq.n 800a4ea - 800a438: 2b40 cmp r3, #64 ; 0x40 - 800a43a: d86f bhi.n 800a51c - 800a43c: 2b30 cmp r3, #48 ; 0x30 - 800a43e: d064 beq.n 800a50a - 800a440: 2b30 cmp r3, #48 ; 0x30 - 800a442: d86b bhi.n 800a51c - 800a444: 2b20 cmp r3, #32 - 800a446: d060 beq.n 800a50a - 800a448: 2b20 cmp r3, #32 - 800a44a: d867 bhi.n 800a51c - 800a44c: 2b00 cmp r3, #0 - 800a44e: d05c beq.n 800a50a - 800a450: 2b10 cmp r3, #16 - 800a452: d05a beq.n 800a50a - 800a454: e062 b.n 800a51c + 800b9fc: 683b ldr r3, [r7, #0] + 800b9fe: 681b ldr r3, [r3, #0] + 800ba00: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800ba04: d03e beq.n 800ba84 + 800ba06: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800ba0a: f200 8087 bhi.w 800bb1c + 800ba0e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800ba12: f000 8086 beq.w 800bb22 + 800ba16: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800ba1a: d87f bhi.n 800bb1c + 800ba1c: 2b70 cmp r3, #112 ; 0x70 + 800ba1e: d01a beq.n 800ba56 + 800ba20: 2b70 cmp r3, #112 ; 0x70 + 800ba22: d87b bhi.n 800bb1c + 800ba24: 2b60 cmp r3, #96 ; 0x60 + 800ba26: d050 beq.n 800baca + 800ba28: 2b60 cmp r3, #96 ; 0x60 + 800ba2a: d877 bhi.n 800bb1c + 800ba2c: 2b50 cmp r3, #80 ; 0x50 + 800ba2e: d03c beq.n 800baaa + 800ba30: 2b50 cmp r3, #80 ; 0x50 + 800ba32: d873 bhi.n 800bb1c + 800ba34: 2b40 cmp r3, #64 ; 0x40 + 800ba36: d058 beq.n 800baea + 800ba38: 2b40 cmp r3, #64 ; 0x40 + 800ba3a: d86f bhi.n 800bb1c + 800ba3c: 2b30 cmp r3, #48 ; 0x30 + 800ba3e: d064 beq.n 800bb0a + 800ba40: 2b30 cmp r3, #48 ; 0x30 + 800ba42: d86b bhi.n 800bb1c + 800ba44: 2b20 cmp r3, #32 + 800ba46: d060 beq.n 800bb0a + 800ba48: 2b20 cmp r3, #32 + 800ba4a: d867 bhi.n 800bb1c + 800ba4c: 2b00 cmp r3, #0 + 800ba4e: d05c beq.n 800bb0a + 800ba50: 2b10 cmp r3, #16 + 800ba52: d05a beq.n 800bb0a + 800ba54: e062 b.n 800bb1c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 800a456: 687b ldr r3, [r7, #4] - 800a458: 6818 ldr r0, [r3, #0] + 800ba56: 687b ldr r3, [r7, #4] + 800ba58: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 800a45a: 683b ldr r3, [r7, #0] - 800a45c: 6899 ldr r1, [r3, #8] + 800ba5a: 683b ldr r3, [r7, #0] + 800ba5c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 800a45e: 683b ldr r3, [r7, #0] - 800a460: 685a ldr r2, [r3, #4] + 800ba5e: 683b ldr r3, [r7, #0] + 800ba60: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 800a462: 683b ldr r3, [r7, #0] - 800a464: 68db ldr r3, [r3, #12] + 800ba62: 683b ldr r3, [r7, #0] + 800ba64: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 800a466: f000 f97b bl 800a760 + 800ba66: f000 f949 bl 800bcfc /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; - 800a46a: 687b ldr r3, [r7, #4] - 800a46c: 681b ldr r3, [r3, #0] - 800a46e: 689b ldr r3, [r3, #8] - 800a470: 60bb str r3, [r7, #8] + 800ba6a: 687b ldr r3, [r7, #4] + 800ba6c: 681b ldr r3, [r3, #0] + 800ba6e: 689b ldr r3, [r3, #8] + 800ba70: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - 800a472: 68bb ldr r3, [r7, #8] - 800a474: f043 0377 orr.w r3, r3, #119 ; 0x77 - 800a478: 60bb str r3, [r7, #8] + 800ba72: 68bb ldr r3, [r7, #8] + 800ba74: f043 0377 orr.w r3, r3, #119 ; 0x77 + 800ba78: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 800a47a: 687b ldr r3, [r7, #4] - 800a47c: 681b ldr r3, [r3, #0] - 800a47e: 68ba ldr r2, [r7, #8] - 800a480: 609a str r2, [r3, #8] + 800ba7a: 687b ldr r3, [r7, #4] + 800ba7c: 681b ldr r3, [r3, #0] + 800ba7e: 68ba ldr r2, [r7, #8] + 800ba80: 609a str r2, [r3, #8] break; - 800a482: e04f b.n 800a524 + 800ba82: e04f b.n 800bb24 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 800a484: 687b ldr r3, [r7, #4] - 800a486: 6818 ldr r0, [r3, #0] + 800ba84: 687b ldr r3, [r7, #4] + 800ba86: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 800a488: 683b ldr r3, [r7, #0] - 800a48a: 6899 ldr r1, [r3, #8] + 800ba88: 683b ldr r3, [r7, #0] + 800ba8a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 800a48c: 683b ldr r3, [r7, #0] - 800a48e: 685a ldr r2, [r3, #4] + 800ba8c: 683b ldr r3, [r7, #0] + 800ba8e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 800a490: 683b ldr r3, [r7, #0] - 800a492: 68db ldr r3, [r3, #12] + 800ba90: 683b ldr r3, [r7, #0] + 800ba92: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 800a494: f000 f964 bl 800a760 + 800ba94: f000 f932 bl 800bcfc /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; - 800a498: 687b ldr r3, [r7, #4] - 800a49a: 681b ldr r3, [r3, #0] - 800a49c: 689a ldr r2, [r3, #8] - 800a49e: 687b ldr r3, [r7, #4] - 800a4a0: 681b ldr r3, [r3, #0] - 800a4a2: f442 4280 orr.w r2, r2, #16384 ; 0x4000 - 800a4a6: 609a str r2, [r3, #8] + 800ba98: 687b ldr r3, [r7, #4] + 800ba9a: 681b ldr r3, [r3, #0] + 800ba9c: 689a ldr r2, [r3, #8] + 800ba9e: 687b ldr r3, [r7, #4] + 800baa0: 681b ldr r3, [r3, #0] + 800baa2: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 800baa6: 609a str r2, [r3, #8] break; - 800a4a8: e03c b.n 800a524 + 800baa8: e03c b.n 800bb24 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 800a4aa: 687b ldr r3, [r7, #4] - 800a4ac: 6818 ldr r0, [r3, #0] + 800baaa: 687b ldr r3, [r7, #4] + 800baac: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 800a4ae: 683b ldr r3, [r7, #0] - 800a4b0: 6859 ldr r1, [r3, #4] + 800baae: 683b ldr r3, [r7, #0] + 800bab0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800a4b2: 683b ldr r3, [r7, #0] - 800a4b4: 68db ldr r3, [r3, #12] + 800bab2: 683b ldr r3, [r7, #0] + 800bab4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 800a4b6: 461a mov r2, r3 - 800a4b8: f000 f8d8 bl 800a66c + 800bab6: 461a mov r2, r3 + 800bab8: f000 f8a6 bl 800bc08 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - 800a4bc: 687b ldr r3, [r7, #4] - 800a4be: 681b ldr r3, [r3, #0] - 800a4c0: 2150 movs r1, #80 ; 0x50 - 800a4c2: 4618 mov r0, r3 - 800a4c4: f000 f931 bl 800a72a + 800babc: 687b ldr r3, [r7, #4] + 800babe: 681b ldr r3, [r3, #0] + 800bac0: 2150 movs r1, #80 ; 0x50 + 800bac2: 4618 mov r0, r3 + 800bac4: f000 f8ff bl 800bcc6 break; - 800a4c8: e02c b.n 800a524 + 800bac8: e02c b.n 800bb24 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, - 800a4ca: 687b ldr r3, [r7, #4] - 800a4cc: 6818 ldr r0, [r3, #0] + 800baca: 687b ldr r3, [r7, #4] + 800bacc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 800a4ce: 683b ldr r3, [r7, #0] - 800a4d0: 6859 ldr r1, [r3, #4] + 800bace: 683b ldr r3, [r7, #0] + 800bad0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800a4d2: 683b ldr r3, [r7, #0] - 800a4d4: 68db ldr r3, [r3, #12] + 800bad2: 683b ldr r3, [r7, #0] + 800bad4: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, - 800a4d6: 461a mov r2, r3 - 800a4d8: f000 f8f7 bl 800a6ca + 800bad6: 461a mov r2, r3 + 800bad8: f000 f8c5 bl 800bc66 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - 800a4dc: 687b ldr r3, [r7, #4] - 800a4de: 681b ldr r3, [r3, #0] - 800a4e0: 2160 movs r1, #96 ; 0x60 - 800a4e2: 4618 mov r0, r3 - 800a4e4: f000 f921 bl 800a72a + 800badc: 687b ldr r3, [r7, #4] + 800bade: 681b ldr r3, [r3, #0] + 800bae0: 2160 movs r1, #96 ; 0x60 + 800bae2: 4618 mov r0, r3 + 800bae4: f000 f8ef bl 800bcc6 break; - 800a4e8: e01c b.n 800a524 + 800bae8: e01c b.n 800bb24 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 800a4ea: 687b ldr r3, [r7, #4] - 800a4ec: 6818 ldr r0, [r3, #0] + 800baea: 687b ldr r3, [r7, #4] + 800baec: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 800a4ee: 683b ldr r3, [r7, #0] - 800a4f0: 6859 ldr r1, [r3, #4] + 800baee: 683b ldr r3, [r7, #0] + 800baf0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 800a4f2: 683b ldr r3, [r7, #0] - 800a4f4: 68db ldr r3, [r3, #12] + 800baf2: 683b ldr r3, [r7, #0] + 800baf4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 800a4f6: 461a mov r2, r3 - 800a4f8: f000 f8b8 bl 800a66c + 800baf6: 461a mov r2, r3 + 800baf8: f000 f886 bl 800bc08 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - 800a4fc: 687b ldr r3, [r7, #4] - 800a4fe: 681b ldr r3, [r3, #0] - 800a500: 2140 movs r1, #64 ; 0x40 - 800a502: 4618 mov r0, r3 - 800a504: f000 f911 bl 800a72a + 800bafc: 687b ldr r3, [r7, #4] + 800bafe: 681b ldr r3, [r3, #0] + 800bb00: 2140 movs r1, #64 ; 0x40 + 800bb02: 4618 mov r0, r3 + 800bb04: f000 f8df bl 800bcc6 break; - 800a508: e00c b.n 800a524 + 800bb08: e00c b.n 800bb24 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - 800a50a: 687b ldr r3, [r7, #4] - 800a50c: 681a ldr r2, [r3, #0] - 800a50e: 683b ldr r3, [r7, #0] - 800a510: 681b ldr r3, [r3, #0] - 800a512: 4619 mov r1, r3 - 800a514: 4610 mov r0, r2 - 800a516: f000 f908 bl 800a72a + 800bb0a: 687b ldr r3, [r7, #4] + 800bb0c: 681a ldr r2, [r3, #0] + 800bb0e: 683b ldr r3, [r7, #0] + 800bb10: 681b ldr r3, [r3, #0] + 800bb12: 4619 mov r1, r3 + 800bb14: 4610 mov r0, r2 + 800bb16: f000 f8d6 bl 800bcc6 break; - 800a51a: e003 b.n 800a524 + 800bb1a: e003 b.n 800bb24 } default: status = HAL_ERROR; - 800a51c: 2301 movs r3, #1 - 800a51e: 73fb strb r3, [r7, #15] + 800bb1c: 2301 movs r3, #1 + 800bb1e: 73fb strb r3, [r7, #15] break; - 800a520: e000 b.n 800a524 + 800bb20: e000 b.n 800bb24 break; - 800a522: bf00 nop + 800bb22: bf00 nop } htim->State = HAL_TIM_STATE_READY; - 800a524: 687b ldr r3, [r7, #4] - 800a526: 2201 movs r2, #1 - 800a528: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800bb24: 687b ldr r3, [r7, #4] + 800bb26: 2201 movs r2, #1 + 800bb28: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); - 800a52c: 687b ldr r3, [r7, #4] - 800a52e: 2200 movs r2, #0 - 800a530: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800bb2c: 687b ldr r3, [r7, #4] + 800bb2e: 2200 movs r2, #0 + 800bb30: f883 203c strb.w r2, [r3, #60] ; 0x3c return status; - 800a534: 7bfb ldrb r3, [r7, #15] -} - 800a536: 4618 mov r0, r3 - 800a538: 3710 adds r7, #16 - 800a53a: 46bd mov sp, r7 - 800a53c: bd80 pop {r7, pc} - -0800a53e : - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - 800a53e: b480 push {r7} - 800a540: b083 sub sp, #12 - 800a542: af00 add r7, sp, #0 - 800a544: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - 800a546: bf00 nop - 800a548: 370c adds r7, #12 - 800a54a: 46bd mov sp, r7 - 800a54c: f85d 7b04 ldr.w r7, [sp], #4 - 800a550: 4770 bx lr - -0800a552 : - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - 800a552: b480 push {r7} - 800a554: b083 sub sp, #12 - 800a556: af00 add r7, sp, #0 - 800a558: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - 800a55a: bf00 nop - 800a55c: 370c adds r7, #12 - 800a55e: 46bd mov sp, r7 - 800a560: f85d 7b04 ldr.w r7, [sp], #4 - 800a564: 4770 bx lr - -0800a566 : - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - 800a566: b480 push {r7} - 800a568: b083 sub sp, #12 - 800a56a: af00 add r7, sp, #0 - 800a56c: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - 800a56e: bf00 nop - 800a570: 370c adds r7, #12 - 800a572: 46bd mov sp, r7 - 800a574: f85d 7b04 ldr.w r7, [sp], #4 - 800a578: 4770 bx lr - -0800a57a : - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - 800a57a: b480 push {r7} - 800a57c: b083 sub sp, #12 - 800a57e: af00 add r7, sp, #0 - 800a580: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - 800a582: bf00 nop - 800a584: 370c adds r7, #12 - 800a586: 46bd mov sp, r7 - 800a588: f85d 7b04 ldr.w r7, [sp], #4 - 800a58c: 4770 bx lr - -0800a58e : - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - 800a58e: b480 push {r7} - 800a590: b083 sub sp, #12 - 800a592: af00 add r7, sp, #0 - 800a594: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ + 800bb34: 7bfb ldrb r3, [r7, #15] } - 800a596: bf00 nop - 800a598: 370c adds r7, #12 - 800a59a: 46bd mov sp, r7 - 800a59c: f85d 7b04 ldr.w r7, [sp], #4 - 800a5a0: 4770 bx lr + 800bb36: 4618 mov r0, r3 + 800bb38: 3710 adds r7, #16 + 800bb3a: 46bd mov sp, r7 + 800bb3c: bd80 pop {r7, pc} ... -0800a5a4 : +0800bb40 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 800a5a4: b480 push {r7} - 800a5a6: b085 sub sp, #20 - 800a5a8: af00 add r7, sp, #0 - 800a5aa: 6078 str r0, [r7, #4] - 800a5ac: 6039 str r1, [r7, #0] + 800bb40: b480 push {r7} + 800bb42: b085 sub sp, #20 + 800bb44: af00 add r7, sp, #0 + 800bb46: 6078 str r0, [r7, #4] + 800bb48: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 800a5ae: 687b ldr r3, [r7, #4] - 800a5b0: 681b ldr r3, [r3, #0] - 800a5b2: 60fb str r3, [r7, #12] + 800bb4a: 687b ldr r3, [r7, #4] + 800bb4c: 681b ldr r3, [r3, #0] + 800bb4e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 800a5b4: 687b ldr r3, [r7, #4] - 800a5b6: 4a2a ldr r2, [pc, #168] ; (800a660 ) - 800a5b8: 4293 cmp r3, r2 - 800a5ba: d003 beq.n 800a5c4 - 800a5bc: 687b ldr r3, [r7, #4] - 800a5be: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 800a5c2: d108 bne.n 800a5d6 + 800bb50: 687b ldr r3, [r7, #4] + 800bb52: 4a2a ldr r2, [pc, #168] ; (800bbfc ) + 800bb54: 4293 cmp r3, r2 + 800bb56: d003 beq.n 800bb60 + 800bb58: 687b ldr r3, [r7, #4] + 800bb5a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800bb5e: d108 bne.n 800bb72 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 800a5c4: 68fb ldr r3, [r7, #12] - 800a5c6: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800a5ca: 60fb str r3, [r7, #12] + 800bb60: 68fb ldr r3, [r7, #12] + 800bb62: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800bb66: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 800a5cc: 683b ldr r3, [r7, #0] - 800a5ce: 685b ldr r3, [r3, #4] - 800a5d0: 68fa ldr r2, [r7, #12] - 800a5d2: 4313 orrs r3, r2 - 800a5d4: 60fb str r3, [r7, #12] + 800bb68: 683b ldr r3, [r7, #0] + 800bb6a: 685b ldr r3, [r3, #4] + 800bb6c: 68fa ldr r2, [r7, #12] + 800bb6e: 4313 orrs r3, r2 + 800bb70: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 800a5d6: 687b ldr r3, [r7, #4] - 800a5d8: 4a21 ldr r2, [pc, #132] ; (800a660 ) - 800a5da: 4293 cmp r3, r2 - 800a5dc: d00b beq.n 800a5f6 - 800a5de: 687b ldr r3, [r7, #4] - 800a5e0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 800a5e4: d007 beq.n 800a5f6 - 800a5e6: 687b ldr r3, [r7, #4] - 800a5e8: 4a1e ldr r2, [pc, #120] ; (800a664 ) - 800a5ea: 4293 cmp r3, r2 - 800a5ec: d003 beq.n 800a5f6 - 800a5ee: 687b ldr r3, [r7, #4] - 800a5f0: 4a1d ldr r2, [pc, #116] ; (800a668 ) - 800a5f2: 4293 cmp r3, r2 - 800a5f4: d108 bne.n 800a608 + 800bb72: 687b ldr r3, [r7, #4] + 800bb74: 4a21 ldr r2, [pc, #132] ; (800bbfc ) + 800bb76: 4293 cmp r3, r2 + 800bb78: d00b beq.n 800bb92 + 800bb7a: 687b ldr r3, [r7, #4] + 800bb7c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800bb80: d007 beq.n 800bb92 + 800bb82: 687b ldr r3, [r7, #4] + 800bb84: 4a1e ldr r2, [pc, #120] ; (800bc00 ) + 800bb86: 4293 cmp r3, r2 + 800bb88: d003 beq.n 800bb92 + 800bb8a: 687b ldr r3, [r7, #4] + 800bb8c: 4a1d ldr r2, [pc, #116] ; (800bc04 ) + 800bb8e: 4293 cmp r3, r2 + 800bb90: d108 bne.n 800bba4 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 800a5f6: 68fb ldr r3, [r7, #12] - 800a5f8: f423 7340 bic.w r3, r3, #768 ; 0x300 - 800a5fc: 60fb str r3, [r7, #12] + 800bb92: 68fb ldr r3, [r7, #12] + 800bb94: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800bb98: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 800a5fe: 683b ldr r3, [r7, #0] - 800a600: 68db ldr r3, [r3, #12] - 800a602: 68fa ldr r2, [r7, #12] - 800a604: 4313 orrs r3, r2 - 800a606: 60fb str r3, [r7, #12] + 800bb9a: 683b ldr r3, [r7, #0] + 800bb9c: 68db ldr r3, [r3, #12] + 800bb9e: 68fa ldr r2, [r7, #12] + 800bba0: 4313 orrs r3, r2 + 800bba2: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 800a608: 68fb ldr r3, [r7, #12] - 800a60a: f023 0280 bic.w r2, r3, #128 ; 0x80 - 800a60e: 683b ldr r3, [r7, #0] - 800a610: 695b ldr r3, [r3, #20] - 800a612: 4313 orrs r3, r2 - 800a614: 60fb str r3, [r7, #12] + 800bba4: 68fb ldr r3, [r7, #12] + 800bba6: f023 0280 bic.w r2, r3, #128 ; 0x80 + 800bbaa: 683b ldr r3, [r7, #0] + 800bbac: 695b ldr r3, [r3, #20] + 800bbae: 4313 orrs r3, r2 + 800bbb0: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; - 800a616: 687b ldr r3, [r7, #4] - 800a618: 68fa ldr r2, [r7, #12] - 800a61a: 601a str r2, [r3, #0] + 800bbb2: 687b ldr r3, [r7, #4] + 800bbb4: 68fa ldr r2, [r7, #12] + 800bbb6: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 800a61c: 683b ldr r3, [r7, #0] - 800a61e: 689a ldr r2, [r3, #8] - 800a620: 687b ldr r3, [r7, #4] - 800a622: 62da str r2, [r3, #44] ; 0x2c + 800bbb8: 683b ldr r3, [r7, #0] + 800bbba: 689a ldr r2, [r3, #8] + 800bbbc: 687b ldr r3, [r7, #4] + 800bbbe: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 800a624: 683b ldr r3, [r7, #0] - 800a626: 681a ldr r2, [r3, #0] - 800a628: 687b ldr r3, [r7, #4] - 800a62a: 629a str r2, [r3, #40] ; 0x28 + 800bbc0: 683b ldr r3, [r7, #0] + 800bbc2: 681a ldr r2, [r3, #0] + 800bbc4: 687b ldr r3, [r7, #4] + 800bbc6: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 800a62c: 687b ldr r3, [r7, #4] - 800a62e: 4a0c ldr r2, [pc, #48] ; (800a660 ) - 800a630: 4293 cmp r3, r2 - 800a632: d007 beq.n 800a644 - 800a634: 687b ldr r3, [r7, #4] - 800a636: 4a0b ldr r2, [pc, #44] ; (800a664 ) - 800a638: 4293 cmp r3, r2 - 800a63a: d003 beq.n 800a644 - 800a63c: 687b ldr r3, [r7, #4] - 800a63e: 4a0a ldr r2, [pc, #40] ; (800a668 ) - 800a640: 4293 cmp r3, r2 - 800a642: d103 bne.n 800a64c + 800bbc8: 687b ldr r3, [r7, #4] + 800bbca: 4a0c ldr r2, [pc, #48] ; (800bbfc ) + 800bbcc: 4293 cmp r3, r2 + 800bbce: d007 beq.n 800bbe0 + 800bbd0: 687b ldr r3, [r7, #4] + 800bbd2: 4a0b ldr r2, [pc, #44] ; (800bc00 ) + 800bbd4: 4293 cmp r3, r2 + 800bbd6: d003 beq.n 800bbe0 + 800bbd8: 687b ldr r3, [r7, #4] + 800bbda: 4a0a ldr r2, [pc, #40] ; (800bc04 ) + 800bbdc: 4293 cmp r3, r2 + 800bbde: d103 bne.n 800bbe8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 800a644: 683b ldr r3, [r7, #0] - 800a646: 691a ldr r2, [r3, #16] - 800a648: 687b ldr r3, [r7, #4] - 800a64a: 631a str r2, [r3, #48] ; 0x30 + 800bbe0: 683b ldr r3, [r7, #0] + 800bbe2: 691a ldr r2, [r3, #16] + 800bbe4: 687b ldr r3, [r7, #4] + 800bbe6: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 800a64c: 687b ldr r3, [r7, #4] - 800a64e: 2201 movs r2, #1 - 800a650: 615a str r2, [r3, #20] -} - 800a652: bf00 nop - 800a654: 3714 adds r7, #20 - 800a656: 46bd mov sp, r7 - 800a658: f85d 7b04 ldr.w r7, [sp], #4 - 800a65c: 4770 bx lr - 800a65e: bf00 nop - 800a660: 40012c00 .word 0x40012c00 - 800a664: 40014000 .word 0x40014000 - 800a668: 40014400 .word 0x40014400 - -0800a66c : + 800bbe8: 687b ldr r3, [r7, #4] + 800bbea: 2201 movs r2, #1 + 800bbec: 615a str r2, [r3, #20] +} + 800bbee: bf00 nop + 800bbf0: 3714 adds r7, #20 + 800bbf2: 46bd mov sp, r7 + 800bbf4: f85d 7b04 ldr.w r7, [sp], #4 + 800bbf8: 4770 bx lr + 800bbfa: bf00 nop + 800bbfc: 40012c00 .word 0x40012c00 + 800bc00: 40014000 .word 0x40014000 + 800bc04: 40014400 .word 0x40014400 + +0800bc08 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 800a66c: b480 push {r7} - 800a66e: b087 sub sp, #28 - 800a670: af00 add r7, sp, #0 - 800a672: 60f8 str r0, [r7, #12] - 800a674: 60b9 str r1, [r7, #8] - 800a676: 607a str r2, [r7, #4] + 800bc08: b480 push {r7} + 800bc0a: b087 sub sp, #28 + 800bc0c: af00 add r7, sp, #0 + 800bc0e: 60f8 str r0, [r7, #12] + 800bc10: 60b9 str r1, [r7, #8] + 800bc12: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; - 800a678: 68fb ldr r3, [r7, #12] - 800a67a: 6a1b ldr r3, [r3, #32] - 800a67c: 617b str r3, [r7, #20] + 800bc14: 68fb ldr r3, [r7, #12] + 800bc16: 6a1b ldr r3, [r3, #32] + 800bc18: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; - 800a67e: 68fb ldr r3, [r7, #12] - 800a680: 6a1b ldr r3, [r3, #32] - 800a682: f023 0201 bic.w r2, r3, #1 - 800a686: 68fb ldr r3, [r7, #12] - 800a688: 621a str r2, [r3, #32] + 800bc1a: 68fb ldr r3, [r7, #12] + 800bc1c: 6a1b ldr r3, [r3, #32] + 800bc1e: f023 0201 bic.w r2, r3, #1 + 800bc22: 68fb ldr r3, [r7, #12] + 800bc24: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 800a68a: 68fb ldr r3, [r7, #12] - 800a68c: 699b ldr r3, [r3, #24] - 800a68e: 613b str r3, [r7, #16] + 800bc26: 68fb ldr r3, [r7, #12] + 800bc28: 699b ldr r3, [r3, #24] + 800bc2a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - 800a690: 693b ldr r3, [r7, #16] - 800a692: f023 03f0 bic.w r3, r3, #240 ; 0xf0 - 800a696: 613b str r3, [r7, #16] + 800bc2c: 693b ldr r3, [r7, #16] + 800bc2e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 800bc32: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); - 800a698: 687b ldr r3, [r7, #4] - 800a69a: 011b lsls r3, r3, #4 - 800a69c: 693a ldr r2, [r7, #16] - 800a69e: 4313 orrs r3, r2 - 800a6a0: 613b str r3, [r7, #16] + 800bc34: 687b ldr r3, [r7, #4] + 800bc36: 011b lsls r3, r3, #4 + 800bc38: 693a ldr r2, [r7, #16] + 800bc3a: 4313 orrs r3, r2 + 800bc3c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - 800a6a2: 697b ldr r3, [r7, #20] - 800a6a4: f023 030a bic.w r3, r3, #10 - 800a6a8: 617b str r3, [r7, #20] + 800bc3e: 697b ldr r3, [r7, #20] + 800bc40: f023 030a bic.w r3, r3, #10 + 800bc44: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; - 800a6aa: 697a ldr r2, [r7, #20] - 800a6ac: 68bb ldr r3, [r7, #8] - 800a6ae: 4313 orrs r3, r2 - 800a6b0: 617b str r3, [r7, #20] + 800bc46: 697a ldr r2, [r7, #20] + 800bc48: 68bb ldr r3, [r7, #8] + 800bc4a: 4313 orrs r3, r2 + 800bc4c: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; - 800a6b2: 68fb ldr r3, [r7, #12] - 800a6b4: 693a ldr r2, [r7, #16] - 800a6b6: 619a str r2, [r3, #24] + 800bc4e: 68fb ldr r3, [r7, #12] + 800bc50: 693a ldr r2, [r7, #16] + 800bc52: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 800a6b8: 68fb ldr r3, [r7, #12] - 800a6ba: 697a ldr r2, [r7, #20] - 800a6bc: 621a str r2, [r3, #32] + 800bc54: 68fb ldr r3, [r7, #12] + 800bc56: 697a ldr r2, [r7, #20] + 800bc58: 621a str r2, [r3, #32] } - 800a6be: bf00 nop - 800a6c0: 371c adds r7, #28 - 800a6c2: 46bd mov sp, r7 - 800a6c4: f85d 7b04 ldr.w r7, [sp], #4 - 800a6c8: 4770 bx lr + 800bc5a: bf00 nop + 800bc5c: 371c adds r7, #28 + 800bc5e: 46bd mov sp, r7 + 800bc60: f85d 7b04 ldr.w r7, [sp], #4 + 800bc64: 4770 bx lr -0800a6ca : +0800bc66 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 800a6ca: b480 push {r7} - 800a6cc: b087 sub sp, #28 - 800a6ce: af00 add r7, sp, #0 - 800a6d0: 60f8 str r0, [r7, #12] - 800a6d2: 60b9 str r1, [r7, #8] - 800a6d4: 607a str r2, [r7, #4] + 800bc66: b480 push {r7} + 800bc68: b087 sub sp, #28 + 800bc6a: af00 add r7, sp, #0 + 800bc6c: 60f8 str r0, [r7, #12] + 800bc6e: 60b9 str r1, [r7, #8] + 800bc70: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; - 800a6d6: 68fb ldr r3, [r7, #12] - 800a6d8: 6a1b ldr r3, [r3, #32] - 800a6da: 617b str r3, [r7, #20] + 800bc72: 68fb ldr r3, [r7, #12] + 800bc74: 6a1b ldr r3, [r3, #32] + 800bc76: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; - 800a6dc: 68fb ldr r3, [r7, #12] - 800a6de: 6a1b ldr r3, [r3, #32] - 800a6e0: f023 0210 bic.w r2, r3, #16 - 800a6e4: 68fb ldr r3, [r7, #12] - 800a6e6: 621a str r2, [r3, #32] + 800bc78: 68fb ldr r3, [r7, #12] + 800bc7a: 6a1b ldr r3, [r3, #32] + 800bc7c: f023 0210 bic.w r2, r3, #16 + 800bc80: 68fb ldr r3, [r7, #12] + 800bc82: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 800a6e8: 68fb ldr r3, [r7, #12] - 800a6ea: 699b ldr r3, [r3, #24] - 800a6ec: 613b str r3, [r7, #16] + 800bc84: 68fb ldr r3, [r7, #12] + 800bc86: 699b ldr r3, [r3, #24] + 800bc88: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - 800a6ee: 693b ldr r3, [r7, #16] - 800a6f0: f423 4370 bic.w r3, r3, #61440 ; 0xf000 - 800a6f4: 613b str r3, [r7, #16] + 800bc8a: 693b ldr r3, [r7, #16] + 800bc8c: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 800bc90: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); - 800a6f6: 687b ldr r3, [r7, #4] - 800a6f8: 031b lsls r3, r3, #12 - 800a6fa: 693a ldr r2, [r7, #16] - 800a6fc: 4313 orrs r3, r2 - 800a6fe: 613b str r3, [r7, #16] + 800bc92: 687b ldr r3, [r7, #4] + 800bc94: 031b lsls r3, r3, #12 + 800bc96: 693a ldr r2, [r7, #16] + 800bc98: 4313 orrs r3, r2 + 800bc9a: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - 800a700: 697b ldr r3, [r7, #20] - 800a702: f023 03a0 bic.w r3, r3, #160 ; 0xa0 - 800a706: 617b str r3, [r7, #20] + 800bc9c: 697b ldr r3, [r7, #20] + 800bc9e: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 800bca2: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); - 800a708: 68bb ldr r3, [r7, #8] - 800a70a: 011b lsls r3, r3, #4 - 800a70c: 697a ldr r2, [r7, #20] - 800a70e: 4313 orrs r3, r2 - 800a710: 617b str r3, [r7, #20] + 800bca4: 68bb ldr r3, [r7, #8] + 800bca6: 011b lsls r3, r3, #4 + 800bca8: 697a ldr r2, [r7, #20] + 800bcaa: 4313 orrs r3, r2 + 800bcac: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; - 800a712: 68fb ldr r3, [r7, #12] - 800a714: 693a ldr r2, [r7, #16] - 800a716: 619a str r2, [r3, #24] + 800bcae: 68fb ldr r3, [r7, #12] + 800bcb0: 693a ldr r2, [r7, #16] + 800bcb2: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 800a718: 68fb ldr r3, [r7, #12] - 800a71a: 697a ldr r2, [r7, #20] - 800a71c: 621a str r2, [r3, #32] + 800bcb4: 68fb ldr r3, [r7, #12] + 800bcb6: 697a ldr r2, [r7, #20] + 800bcb8: 621a str r2, [r3, #32] } - 800a71e: bf00 nop - 800a720: 371c adds r7, #28 - 800a722: 46bd mov sp, r7 - 800a724: f85d 7b04 ldr.w r7, [sp], #4 - 800a728: 4770 bx lr + 800bcba: bf00 nop + 800bcbc: 371c adds r7, #28 + 800bcbe: 46bd mov sp, r7 + 800bcc0: f85d 7b04 ldr.w r7, [sp], #4 + 800bcc4: 4770 bx lr -0800a72a : +0800bcc6 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - 800a72a: b480 push {r7} - 800a72c: b085 sub sp, #20 - 800a72e: af00 add r7, sp, #0 - 800a730: 6078 str r0, [r7, #4] - 800a732: 6039 str r1, [r7, #0] + 800bcc6: b480 push {r7} + 800bcc8: b085 sub sp, #20 + 800bcca: af00 add r7, sp, #0 + 800bccc: 6078 str r0, [r7, #4] + 800bcce: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; - 800a734: 687b ldr r3, [r7, #4] - 800a736: 689b ldr r3, [r3, #8] - 800a738: 60fb str r3, [r7, #12] + 800bcd0: 687b ldr r3, [r7, #4] + 800bcd2: 689b ldr r3, [r3, #8] + 800bcd4: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; - 800a73a: 68fb ldr r3, [r7, #12] - 800a73c: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800a740: 60fb str r3, [r7, #12] + 800bcd6: 68fb ldr r3, [r7, #12] + 800bcd8: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800bcdc: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - 800a742: 683a ldr r2, [r7, #0] - 800a744: 68fb ldr r3, [r7, #12] - 800a746: 4313 orrs r3, r2 - 800a748: f043 0307 orr.w r3, r3, #7 - 800a74c: 60fb str r3, [r7, #12] + 800bcde: 683a ldr r2, [r7, #0] + 800bce0: 68fb ldr r3, [r7, #12] + 800bce2: 4313 orrs r3, r2 + 800bce4: f043 0307 orr.w r3, r3, #7 + 800bce8: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 800a74e: 687b ldr r3, [r7, #4] - 800a750: 68fa ldr r2, [r7, #12] - 800a752: 609a str r2, [r3, #8] + 800bcea: 687b ldr r3, [r7, #4] + 800bcec: 68fa ldr r2, [r7, #12] + 800bcee: 609a str r2, [r3, #8] } - 800a754: bf00 nop - 800a756: 3714 adds r7, #20 - 800a758: 46bd mov sp, r7 - 800a75a: f85d 7b04 ldr.w r7, [sp], #4 - 800a75e: 4770 bx lr + 800bcf0: bf00 nop + 800bcf2: 3714 adds r7, #20 + 800bcf4: 46bd mov sp, r7 + 800bcf6: f85d 7b04 ldr.w r7, [sp], #4 + 800bcfa: 4770 bx lr -0800a760 : +0800bcfc : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - 800a760: b480 push {r7} - 800a762: b087 sub sp, #28 - 800a764: af00 add r7, sp, #0 - 800a766: 60f8 str r0, [r7, #12] - 800a768: 60b9 str r1, [r7, #8] - 800a76a: 607a str r2, [r7, #4] - 800a76c: 603b str r3, [r7, #0] + 800bcfc: b480 push {r7} + 800bcfe: b087 sub sp, #28 + 800bd00: af00 add r7, sp, #0 + 800bd02: 60f8 str r0, [r7, #12] + 800bd04: 60b9 str r1, [r7, #8] + 800bd06: 607a str r2, [r7, #4] + 800bd08: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; - 800a76e: 68fb ldr r3, [r7, #12] - 800a770: 689b ldr r3, [r3, #8] - 800a772: 617b str r3, [r7, #20] + 800bd0a: 68fb ldr r3, [r7, #12] + 800bd0c: 689b ldr r3, [r3, #8] + 800bd0e: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 800a774: 697b ldr r3, [r7, #20] - 800a776: f423 437f bic.w r3, r3, #65280 ; 0xff00 - 800a77a: 617b str r3, [r7, #20] + 800bd10: 697b ldr r3, [r7, #20] + 800bd12: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 800bd16: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - 800a77c: 683b ldr r3, [r7, #0] - 800a77e: 021a lsls r2, r3, #8 - 800a780: 687b ldr r3, [r7, #4] - 800a782: 431a orrs r2, r3 - 800a784: 68bb ldr r3, [r7, #8] - 800a786: 4313 orrs r3, r2 - 800a788: 697a ldr r2, [r7, #20] - 800a78a: 4313 orrs r3, r2 - 800a78c: 617b str r3, [r7, #20] + 800bd18: 683b ldr r3, [r7, #0] + 800bd1a: 021a lsls r2, r3, #8 + 800bd1c: 687b ldr r3, [r7, #4] + 800bd1e: 431a orrs r2, r3 + 800bd20: 68bb ldr r3, [r7, #8] + 800bd22: 4313 orrs r3, r2 + 800bd24: 697a ldr r2, [r7, #20] + 800bd26: 4313 orrs r3, r2 + 800bd28: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 800a78e: 68fb ldr r3, [r7, #12] - 800a790: 697a ldr r2, [r7, #20] - 800a792: 609a str r2, [r3, #8] + 800bd2a: 68fb ldr r3, [r7, #12] + 800bd2c: 697a ldr r2, [r7, #20] + 800bd2e: 609a str r2, [r3, #8] } - 800a794: bf00 nop - 800a796: 371c adds r7, #28 - 800a798: 46bd mov sp, r7 - 800a79a: f85d 7b04 ldr.w r7, [sp], #4 - 800a79e: 4770 bx lr + 800bd30: bf00 nop + 800bd32: 371c adds r7, #28 + 800bd34: 46bd mov sp, r7 + 800bd36: f85d 7b04 ldr.w r7, [sp], #4 + 800bd3a: 4770 bx lr -0800a7a0 : +0800bd3c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 800a7a0: b480 push {r7} - 800a7a2: b085 sub sp, #20 - 800a7a4: af00 add r7, sp, #0 - 800a7a6: 6078 str r0, [r7, #4] - 800a7a8: 6039 str r1, [r7, #0] + 800bd3c: b480 push {r7} + 800bd3e: b085 sub sp, #20 + 800bd40: af00 add r7, sp, #0 + 800bd42: 6078 str r0, [r7, #4] + 800bd44: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 800a7aa: 687b ldr r3, [r7, #4] - 800a7ac: f893 303c ldrb.w r3, [r3, #60] ; 0x3c - 800a7b0: 2b01 cmp r3, #1 - 800a7b2: d101 bne.n 800a7b8 - 800a7b4: 2302 movs r3, #2 - 800a7b6: e04f b.n 800a858 - 800a7b8: 687b ldr r3, [r7, #4] - 800a7ba: 2201 movs r2, #1 - 800a7bc: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800bd46: 687b ldr r3, [r7, #4] + 800bd48: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800bd4c: 2b01 cmp r3, #1 + 800bd4e: d101 bne.n 800bd54 + 800bd50: 2302 movs r3, #2 + 800bd52: e04f b.n 800bdf4 + 800bd54: 687b ldr r3, [r7, #4] + 800bd56: 2201 movs r2, #1 + 800bd58: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 800a7c0: 687b ldr r3, [r7, #4] - 800a7c2: 2202 movs r2, #2 - 800a7c4: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800bd5c: 687b ldr r3, [r7, #4] + 800bd5e: 2202 movs r2, #2 + 800bd60: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 800a7c8: 687b ldr r3, [r7, #4] - 800a7ca: 681b ldr r3, [r3, #0] - 800a7cc: 685b ldr r3, [r3, #4] - 800a7ce: 60fb str r3, [r7, #12] + 800bd64: 687b ldr r3, [r7, #4] + 800bd66: 681b ldr r3, [r3, #0] + 800bd68: 685b ldr r3, [r3, #4] + 800bd6a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 800a7d0: 687b ldr r3, [r7, #4] - 800a7d2: 681b ldr r3, [r3, #0] - 800a7d4: 689b ldr r3, [r3, #8] - 800a7d6: 60bb str r3, [r7, #8] + 800bd6c: 687b ldr r3, [r7, #4] + 800bd6e: 681b ldr r3, [r3, #0] + 800bd70: 689b ldr r3, [r3, #8] + 800bd72: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 800a7d8: 687b ldr r3, [r7, #4] - 800a7da: 681b ldr r3, [r3, #0] - 800a7dc: 4a21 ldr r2, [pc, #132] ; (800a864 ) - 800a7de: 4293 cmp r3, r2 - 800a7e0: d108 bne.n 800a7f4 + 800bd74: 687b ldr r3, [r7, #4] + 800bd76: 681b ldr r3, [r3, #0] + 800bd78: 4a21 ldr r2, [pc, #132] ; (800be00 ) + 800bd7a: 4293 cmp r3, r2 + 800bd7c: d108 bne.n 800bd90 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 800a7e2: 68fb ldr r3, [r7, #12] - 800a7e4: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 - 800a7e8: 60fb str r3, [r7, #12] + 800bd7e: 68fb ldr r3, [r7, #12] + 800bd80: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 800bd84: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 800a7ea: 683b ldr r3, [r7, #0] - 800a7ec: 685b ldr r3, [r3, #4] - 800a7ee: 68fa ldr r2, [r7, #12] - 800a7f0: 4313 orrs r3, r2 - 800a7f2: 60fb str r3, [r7, #12] + 800bd86: 683b ldr r3, [r7, #0] + 800bd88: 685b ldr r3, [r3, #4] + 800bd8a: 68fa ldr r2, [r7, #12] + 800bd8c: 4313 orrs r3, r2 + 800bd8e: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 800a7f4: 68fb ldr r3, [r7, #12] - 800a7f6: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800a7fa: 60fb str r3, [r7, #12] + 800bd90: 68fb ldr r3, [r7, #12] + 800bd92: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800bd96: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 800a7fc: 683b ldr r3, [r7, #0] - 800a7fe: 681b ldr r3, [r3, #0] - 800a800: 68fa ldr r2, [r7, #12] - 800a802: 4313 orrs r3, r2 - 800a804: 60fb str r3, [r7, #12] + 800bd98: 683b ldr r3, [r7, #0] + 800bd9a: 681b ldr r3, [r3, #0] + 800bd9c: 68fa ldr r2, [r7, #12] + 800bd9e: 4313 orrs r3, r2 + 800bda0: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 800a806: 687b ldr r3, [r7, #4] - 800a808: 681b ldr r3, [r3, #0] - 800a80a: 68fa ldr r2, [r7, #12] - 800a80c: 605a str r2, [r3, #4] + 800bda2: 687b ldr r3, [r7, #4] + 800bda4: 681b ldr r3, [r3, #0] + 800bda6: 68fa ldr r2, [r7, #12] + 800bda8: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 800a80e: 687b ldr r3, [r7, #4] - 800a810: 681b ldr r3, [r3, #0] - 800a812: 4a14 ldr r2, [pc, #80] ; (800a864 ) - 800a814: 4293 cmp r3, r2 - 800a816: d009 beq.n 800a82c - 800a818: 687b ldr r3, [r7, #4] - 800a81a: 681b ldr r3, [r3, #0] - 800a81c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 800a820: d004 beq.n 800a82c - 800a822: 687b ldr r3, [r7, #4] - 800a824: 681b ldr r3, [r3, #0] - 800a826: 4a10 ldr r2, [pc, #64] ; (800a868 ) - 800a828: 4293 cmp r3, r2 - 800a82a: d10c bne.n 800a846 + 800bdaa: 687b ldr r3, [r7, #4] + 800bdac: 681b ldr r3, [r3, #0] + 800bdae: 4a14 ldr r2, [pc, #80] ; (800be00 ) + 800bdb0: 4293 cmp r3, r2 + 800bdb2: d009 beq.n 800bdc8 + 800bdb4: 687b ldr r3, [r7, #4] + 800bdb6: 681b ldr r3, [r3, #0] + 800bdb8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800bdbc: d004 beq.n 800bdc8 + 800bdbe: 687b ldr r3, [r7, #4] + 800bdc0: 681b ldr r3, [r3, #0] + 800bdc2: 4a10 ldr r2, [pc, #64] ; (800be04 ) + 800bdc4: 4293 cmp r3, r2 + 800bdc6: d10c bne.n 800bde2 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 800a82c: 68bb ldr r3, [r7, #8] - 800a82e: f023 0380 bic.w r3, r3, #128 ; 0x80 - 800a832: 60bb str r3, [r7, #8] + 800bdc8: 68bb ldr r3, [r7, #8] + 800bdca: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800bdce: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 800a834: 683b ldr r3, [r7, #0] - 800a836: 689b ldr r3, [r3, #8] - 800a838: 68ba ldr r2, [r7, #8] - 800a83a: 4313 orrs r3, r2 - 800a83c: 60bb str r3, [r7, #8] + 800bdd0: 683b ldr r3, [r7, #0] + 800bdd2: 689b ldr r3, [r3, #8] + 800bdd4: 68ba ldr r2, [r7, #8] + 800bdd6: 4313 orrs r3, r2 + 800bdd8: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 800a83e: 687b ldr r3, [r7, #4] - 800a840: 681b ldr r3, [r3, #0] - 800a842: 68ba ldr r2, [r7, #8] - 800a844: 609a str r2, [r3, #8] + 800bdda: 687b ldr r3, [r7, #4] + 800bddc: 681b ldr r3, [r3, #0] + 800bdde: 68ba ldr r2, [r7, #8] + 800bde0: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 800a846: 687b ldr r3, [r7, #4] - 800a848: 2201 movs r2, #1 - 800a84a: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800bde2: 687b ldr r3, [r7, #4] + 800bde4: 2201 movs r2, #1 + 800bde6: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); - 800a84e: 687b ldr r3, [r7, #4] - 800a850: 2200 movs r2, #0 - 800a852: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800bdea: 687b ldr r3, [r7, #4] + 800bdec: 2200 movs r2, #0 + 800bdee: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; - 800a856: 2300 movs r3, #0 -} - 800a858: 4618 mov r0, r3 - 800a85a: 3714 adds r7, #20 - 800a85c: 46bd mov sp, r7 - 800a85e: f85d 7b04 ldr.w r7, [sp], #4 - 800a862: 4770 bx lr - 800a864: 40012c00 .word 0x40012c00 - 800a868: 40014000 .word 0x40014000 - -0800a86c : - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) -{ - 800a86c: b480 push {r7} - 800a86e: b083 sub sp, #12 - 800a870: af00 add r7, sp, #0 - 800a872: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutCallback could be implemented in the user file - */ -} - 800a874: bf00 nop - 800a876: 370c adds r7, #12 - 800a878: 46bd mov sp, r7 - 800a87a: f85d 7b04 ldr.w r7, [sp], #4 - 800a87e: 4770 bx lr - -0800a880 : - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - 800a880: b480 push {r7} - 800a882: b083 sub sp, #12 - 800a884: af00 add r7, sp, #0 - 800a886: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - 800a888: bf00 nop - 800a88a: 370c adds r7, #12 - 800a88c: 46bd mov sp, r7 - 800a88e: f85d 7b04 ldr.w r7, [sp], #4 - 800a892: 4770 bx lr - -0800a894 : - * @brief Hall Break2 detection callback in non blocking mode - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) -{ - 800a894: b480 push {r7} - 800a896: b083 sub sp, #12 - 800a898: af00 add r7, sp, #0 - 800a89a: 6078 str r0, [r7, #4] - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_Break2Callback could be implemented in the user file - */ + 800bdf2: 2300 movs r3, #0 } - 800a89c: bf00 nop - 800a89e: 370c adds r7, #12 - 800a8a0: 46bd mov sp, r7 - 800a8a2: f85d 7b04 ldr.w r7, [sp], #4 - 800a8a6: 4770 bx lr + 800bdf4: 4618 mov r0, r3 + 800bdf6: 3714 adds r7, #20 + 800bdf8: 46bd mov sp, r7 + 800bdfa: f85d 7b04 ldr.w r7, [sp], #4 + 800bdfe: 4770 bx lr + 800be00: 40012c00 .word 0x40012c00 + 800be04: 40014000 .word 0x40014000 -0800a8a8 : +0800be08 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 800a8a8: b580 push {r7, lr} - 800a8aa: b082 sub sp, #8 - 800a8ac: af00 add r7, sp, #0 - 800a8ae: 6078 str r0, [r7, #4] + 800be08: b580 push {r7, lr} + 800be0a: b082 sub sp, #8 + 800be0c: af00 add r7, sp, #0 + 800be0e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 800a8b0: 687b ldr r3, [r7, #4] - 800a8b2: 2b00 cmp r3, #0 - 800a8b4: d101 bne.n 800a8ba + 800be10: 687b ldr r3, [r7, #4] + 800be12: 2b00 cmp r3, #0 + 800be14: d101 bne.n 800be1a { return HAL_ERROR; - 800a8b6: 2301 movs r3, #1 - 800a8b8: e040 b.n 800a93c + 800be16: 2301 movs r3, #1 + 800be18: e040 b.n 800be9c { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) - 800a8ba: 687b ldr r3, [r7, #4] - 800a8bc: 6fdb ldr r3, [r3, #124] ; 0x7c - 800a8be: 2b00 cmp r3, #0 - 800a8c0: d106 bne.n 800a8d0 + 800be1a: 687b ldr r3, [r7, #4] + 800be1c: 6fdb ldr r3, [r3, #124] ; 0x7c + 800be1e: 2b00 cmp r3, #0 + 800be20: d106 bne.n 800be30 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 800a8c2: 687b ldr r3, [r7, #4] - 800a8c4: 2200 movs r2, #0 - 800a8c6: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800be22: 687b ldr r3, [r7, #4] + 800be24: 2200 movs r2, #0 + 800be26: f883 2078 strb.w r2, [r3, #120] ; 0x78 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 800a8ca: 6878 ldr r0, [r7, #4] - 800a8cc: f7f9 fb90 bl 8003ff0 + 800be2a: 6878 ldr r0, [r7, #4] + 800be2c: f7f9 f840 bl 8004eb0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 800a8d0: 687b ldr r3, [r7, #4] - 800a8d2: 2224 movs r2, #36 ; 0x24 - 800a8d4: 67da str r2, [r3, #124] ; 0x7c + 800be30: 687b ldr r3, [r7, #4] + 800be32: 2224 movs r2, #36 ; 0x24 + 800be34: 67da str r2, [r3, #124] ; 0x7c __HAL_UART_DISABLE(huart); - 800a8d6: 687b ldr r3, [r7, #4] - 800a8d8: 681b ldr r3, [r3, #0] - 800a8da: 681a ldr r2, [r3, #0] - 800a8dc: 687b ldr r3, [r7, #4] - 800a8de: 681b ldr r3, [r3, #0] - 800a8e0: f022 0201 bic.w r2, r2, #1 - 800a8e4: 601a str r2, [r3, #0] + 800be36: 687b ldr r3, [r7, #4] + 800be38: 681b ldr r3, [r3, #0] + 800be3a: 681a ldr r2, [r3, #0] + 800be3c: 687b ldr r3, [r7, #4] + 800be3e: 681b ldr r3, [r3, #0] + 800be40: f022 0201 bic.w r2, r2, #1 + 800be44: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 800a8e6: 687b ldr r3, [r7, #4] - 800a8e8: 6a5b ldr r3, [r3, #36] ; 0x24 - 800a8ea: 2b00 cmp r3, #0 - 800a8ec: d002 beq.n 800a8f4 + 800be46: 687b ldr r3, [r7, #4] + 800be48: 6a5b ldr r3, [r3, #36] ; 0x24 + 800be4a: 2b00 cmp r3, #0 + 800be4c: d002 beq.n 800be54 { UART_AdvFeatureConfig(huart); - 800a8ee: 6878 ldr r0, [r7, #4] - 800a8f0: f000 ff4c bl 800b78c + 800be4e: 6878 ldr r0, [r7, #4] + 800be50: f000 feb0 bl 800cbb4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 800a8f4: 6878 ldr r0, [r7, #4] - 800a8f6: f000 fd1d bl 800b334 - 800a8fa: 4603 mov r3, r0 - 800a8fc: 2b01 cmp r3, #1 - 800a8fe: d101 bne.n 800a904 + 800be54: 6878 ldr r0, [r7, #4] + 800be56: f000 fc81 bl 800c75c + 800be5a: 4603 mov r3, r0 + 800be5c: 2b01 cmp r3, #1 + 800be5e: d101 bne.n 800be64 { return HAL_ERROR; - 800a900: 2301 movs r3, #1 - 800a902: e01b b.n 800a93c + 800be60: 2301 movs r3, #1 + 800be62: e01b b.n 800be9c } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 800a904: 687b ldr r3, [r7, #4] - 800a906: 681b ldr r3, [r3, #0] - 800a908: 685a ldr r2, [r3, #4] - 800a90a: 687b ldr r3, [r7, #4] - 800a90c: 681b ldr r3, [r3, #0] - 800a90e: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 800a912: 605a str r2, [r3, #4] + 800be64: 687b ldr r3, [r7, #4] + 800be66: 681b ldr r3, [r3, #0] + 800be68: 685a ldr r2, [r3, #4] + 800be6a: 687b ldr r3, [r7, #4] + 800be6c: 681b ldr r3, [r3, #0] + 800be6e: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 800be72: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 800a914: 687b ldr r3, [r7, #4] - 800a916: 681b ldr r3, [r3, #0] - 800a918: 689a ldr r2, [r3, #8] - 800a91a: 687b ldr r3, [r7, #4] - 800a91c: 681b ldr r3, [r3, #0] - 800a91e: f022 022a bic.w r2, r2, #42 ; 0x2a - 800a922: 609a str r2, [r3, #8] + 800be74: 687b ldr r3, [r7, #4] + 800be76: 681b ldr r3, [r3, #0] + 800be78: 689a ldr r2, [r3, #8] + 800be7a: 687b ldr r3, [r7, #4] + 800be7c: 681b ldr r3, [r3, #0] + 800be7e: f022 022a bic.w r2, r2, #42 ; 0x2a + 800be82: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 800a924: 687b ldr r3, [r7, #4] - 800a926: 681b ldr r3, [r3, #0] - 800a928: 681a ldr r2, [r3, #0] - 800a92a: 687b ldr r3, [r7, #4] - 800a92c: 681b ldr r3, [r3, #0] - 800a92e: f042 0201 orr.w r2, r2, #1 - 800a932: 601a str r2, [r3, #0] + 800be84: 687b ldr r3, [r7, #4] + 800be86: 681b ldr r3, [r3, #0] + 800be88: 681a ldr r2, [r3, #0] + 800be8a: 687b ldr r3, [r7, #4] + 800be8c: 681b ldr r3, [r3, #0] + 800be8e: f042 0201 orr.w r2, r2, #1 + 800be92: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 800a934: 6878 ldr r0, [r7, #4] - 800a936: f000 ffcb bl 800b8d0 - 800a93a: 4603 mov r3, r0 -} - 800a93c: 4618 mov r0, r3 - 800a93e: 3708 adds r7, #8 - 800a940: 46bd mov sp, r7 - 800a942: bd80 pop {r7, pc} - -0800a944 : - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - 800a944: b580 push {r7, lr} - 800a946: b082 sub sp, #8 - 800a948: af00 add r7, sp, #0 - 800a94a: 6078 str r0, [r7, #4] - /* Check the UART handle allocation */ - if (huart == NULL) - 800a94c: 687b ldr r3, [r7, #4] - 800a94e: 2b00 cmp r3, #0 - 800a950: d101 bne.n 800a956 - { - return HAL_ERROR; - 800a952: 2301 movs r3, #1 - 800a954: e02f b.n 800a9b6 - } - - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - - huart->gState = HAL_UART_STATE_BUSY; - 800a956: 687b ldr r3, [r7, #4] - 800a958: 2224 movs r2, #36 ; 0x24 - 800a95a: 67da str r2, [r3, #124] ; 0x7c - - __HAL_UART_DISABLE(huart); - 800a95c: 687b ldr r3, [r7, #4] - 800a95e: 681b ldr r3, [r3, #0] - 800a960: 681a ldr r2, [r3, #0] - 800a962: 687b ldr r3, [r7, #4] - 800a964: 681b ldr r3, [r3, #0] - 800a966: f022 0201 bic.w r2, r2, #1 - 800a96a: 601a str r2, [r3, #0] - - huart->Instance->CR1 = 0x0U; - 800a96c: 687b ldr r3, [r7, #4] - 800a96e: 681b ldr r3, [r3, #0] - 800a970: 2200 movs r2, #0 - 800a972: 601a str r2, [r3, #0] - huart->Instance->CR2 = 0x0U; - 800a974: 687b ldr r3, [r7, #4] - 800a976: 681b ldr r3, [r3, #0] - 800a978: 2200 movs r2, #0 - 800a97a: 605a str r2, [r3, #4] - huart->Instance->CR3 = 0x0U; - 800a97c: 687b ldr r3, [r7, #4] - 800a97e: 681b ldr r3, [r3, #0] - 800a980: 2200 movs r2, #0 - 800a982: 609a str r2, [r3, #8] - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); - 800a984: 6878 ldr r0, [r7, #4] - 800a986: f7f9 fbbf bl 8004108 -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - 800a98a: 687b ldr r3, [r7, #4] - 800a98c: 2200 movs r2, #0 - 800a98e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 - huart->gState = HAL_UART_STATE_RESET; - 800a992: 687b ldr r3, [r7, #4] - 800a994: 2200 movs r2, #0 - 800a996: 67da str r2, [r3, #124] ; 0x7c - huart->RxState = HAL_UART_STATE_RESET; - 800a998: 687b ldr r3, [r7, #4] - 800a99a: 2200 movs r2, #0 - 800a99c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800a9a0: 687b ldr r3, [r7, #4] - 800a9a2: 2200 movs r2, #0 - 800a9a4: 661a str r2, [r3, #96] ; 0x60 - huart->RxEventType = HAL_UART_RXEVENT_TC; - 800a9a6: 687b ldr r3, [r7, #4] - 800a9a8: 2200 movs r2, #0 - 800a9aa: 665a str r2, [r3, #100] ; 0x64 - - __HAL_UNLOCK(huart); - 800a9ac: 687b ldr r3, [r7, #4] - 800a9ae: 2200 movs r2, #0 - 800a9b0: f883 2078 strb.w r2, [r3, #120] ; 0x78 - - return HAL_OK; - 800a9b4: 2300 movs r3, #0 -} - 800a9b6: 4618 mov r0, r3 - 800a9b8: 3708 adds r7, #8 - 800a9ba: 46bd mov sp, r7 - 800a9bc: bd80 pop {r7, pc} - ... - -0800a9c0 : - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) -{ - 800a9c0: b480 push {r7} - 800a9c2: b08b sub sp, #44 ; 0x2c - 800a9c4: af00 add r7, sp, #0 - 800a9c6: 60f8 str r0, [r7, #12] - 800a9c8: 60b9 str r1, [r7, #8] - 800a9ca: 4613 mov r3, r2 - 800a9cc: 80fb strh r3, [r7, #6] - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - 800a9ce: 68fb ldr r3, [r7, #12] - 800a9d0: 6fdb ldr r3, [r3, #124] ; 0x7c - 800a9d2: 2b20 cmp r3, #32 - 800a9d4: d147 bne.n 800aa66 - { - if ((pData == NULL) || (Size == 0U)) - 800a9d6: 68bb ldr r3, [r7, #8] - 800a9d8: 2b00 cmp r3, #0 - 800a9da: d002 beq.n 800a9e2 - 800a9dc: 88fb ldrh r3, [r7, #6] - 800a9de: 2b00 cmp r3, #0 - 800a9e0: d101 bne.n 800a9e6 - { - return HAL_ERROR; - 800a9e2: 2301 movs r3, #1 - 800a9e4: e040 b.n 800aa68 - } - - huart->pTxBuffPtr = pData; - 800a9e6: 68fb ldr r3, [r7, #12] - 800a9e8: 68ba ldr r2, [r7, #8] - 800a9ea: 64da str r2, [r3, #76] ; 0x4c - huart->TxXferSize = Size; - 800a9ec: 68fb ldr r3, [r7, #12] - 800a9ee: 88fa ldrh r2, [r7, #6] - 800a9f0: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 - huart->TxXferCount = Size; - 800a9f4: 68fb ldr r3, [r7, #12] - 800a9f6: 88fa ldrh r2, [r7, #6] - 800a9f8: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 - huart->TxISR = NULL; - 800a9fc: 68fb ldr r3, [r7, #12] - 800a9fe: 2200 movs r2, #0 - 800aa00: 66da str r2, [r3, #108] ; 0x6c - - huart->ErrorCode = HAL_UART_ERROR_NONE; - 800aa02: 68fb ldr r3, [r7, #12] - 800aa04: 2200 movs r2, #0 - 800aa06: f8c3 2084 str.w r2, [r3, #132] ; 0x84 - huart->gState = HAL_UART_STATE_BUSY_TX; - 800aa0a: 68fb ldr r3, [r7, #12] - 800aa0c: 2221 movs r2, #33 ; 0x21 - 800aa0e: 67da str r2, [r3, #124] ; 0x7c - /* Enable the Transmit Data Register Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - } -#else - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 800aa10: 68fb ldr r3, [r7, #12] - 800aa12: 689b ldr r3, [r3, #8] - 800aa14: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 800aa18: d107 bne.n 800aa2a - 800aa1a: 68fb ldr r3, [r7, #12] - 800aa1c: 691b ldr r3, [r3, #16] - 800aa1e: 2b00 cmp r3, #0 - 800aa20: d103 bne.n 800aa2a - { - huart->TxISR = UART_TxISR_16BIT; - 800aa22: 68fb ldr r3, [r7, #12] - 800aa24: 4a13 ldr r2, [pc, #76] ; (800aa74 ) - 800aa26: 66da str r2, [r3, #108] ; 0x6c - 800aa28: e002 b.n 800aa30 - } - else - { - huart->TxISR = UART_TxISR_8BIT; - 800aa2a: 68fb ldr r3, [r7, #12] - 800aa2c: 4a12 ldr r2, [pc, #72] ; (800aa78 ) - 800aa2e: 66da str r2, [r3, #108] ; 0x6c - } - - /* Enable the Transmit Data Register Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - 800aa30: 68fb ldr r3, [r7, #12] - 800aa32: 681b ldr r3, [r3, #0] - 800aa34: 617b str r3, [r7, #20] - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800aa36: 697b ldr r3, [r7, #20] - 800aa38: e853 3f00 ldrex r3, [r3] - 800aa3c: 613b str r3, [r7, #16] - return(result); - 800aa3e: 693b ldr r3, [r7, #16] - 800aa40: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800aa44: 627b str r3, [r7, #36] ; 0x24 - 800aa46: 68fb ldr r3, [r7, #12] - 800aa48: 681b ldr r3, [r3, #0] - 800aa4a: 461a mov r2, r3 - 800aa4c: 6a7b ldr r3, [r7, #36] ; 0x24 - 800aa4e: 623b str r3, [r7, #32] - 800aa50: 61fa str r2, [r7, #28] - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800aa52: 69f9 ldr r1, [r7, #28] - 800aa54: 6a3a ldr r2, [r7, #32] - 800aa56: e841 2300 strex r3, r2, [r1] - 800aa5a: 61bb str r3, [r7, #24] - return(result); - 800aa5c: 69bb ldr r3, [r7, #24] - 800aa5e: 2b00 cmp r3, #0 - 800aa60: d1e6 bne.n 800aa30 -#endif /* USART_CR1_FIFOEN */ - - return HAL_OK; - 800aa62: 2300 movs r3, #0 - 800aa64: e000 b.n 800aa68 - } - else - { - return HAL_BUSY; - 800aa66: 2302 movs r3, #2 - } + 800be94: 6878 ldr r0, [r7, #4] + 800be96: f000 ff2f bl 800ccf8 + 800be9a: 4603 mov r3, r0 } - 800aa68: 4618 mov r0, r3 - 800aa6a: 372c adds r7, #44 ; 0x2c - 800aa6c: 46bd mov sp, r7 - 800aa6e: f85d 7b04 ldr.w r7, [sp], #4 - 800aa72: 4770 bx lr - 800aa74: 0800c011 .word 0x0800c011 - 800aa78: 0800bf59 .word 0x0800bf59 + 800be9c: 4618 mov r0, r3 + 800be9e: 3708 adds r7, #8 + 800bea0: 46bd mov sp, r7 + 800bea2: bd80 pop {r7, pc} -0800aa7c : +0800bea4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 800aa7c: b580 push {r7, lr} - 800aa7e: b08a sub sp, #40 ; 0x28 - 800aa80: af00 add r7, sp, #0 - 800aa82: 60f8 str r0, [r7, #12] - 800aa84: 60b9 str r1, [r7, #8] - 800aa86: 4613 mov r3, r2 - 800aa88: 80fb strh r3, [r7, #6] + 800bea4: b580 push {r7, lr} + 800bea6: b08a sub sp, #40 ; 0x28 + 800bea8: af00 add r7, sp, #0 + 800beaa: 60f8 str r0, [r7, #12] + 800beac: 60b9 str r1, [r7, #8] + 800beae: 4613 mov r3, r2 + 800beb0: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) - 800aa8a: 68fb ldr r3, [r7, #12] - 800aa8c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 - 800aa90: 2b20 cmp r3, #32 - 800aa92: d137 bne.n 800ab04 + 800beb2: 68fb ldr r3, [r7, #12] + 800beb4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 800beb8: 2b20 cmp r3, #32 + 800beba: d137 bne.n 800bf2c { if ((pData == NULL) || (Size == 0U)) - 800aa94: 68bb ldr r3, [r7, #8] - 800aa96: 2b00 cmp r3, #0 - 800aa98: d002 beq.n 800aaa0 - 800aa9a: 88fb ldrh r3, [r7, #6] - 800aa9c: 2b00 cmp r3, #0 - 800aa9e: d101 bne.n 800aaa4 + 800bebc: 68bb ldr r3, [r7, #8] + 800bebe: 2b00 cmp r3, #0 + 800bec0: d002 beq.n 800bec8 + 800bec2: 88fb ldrh r3, [r7, #6] + 800bec4: 2b00 cmp r3, #0 + 800bec6: d101 bne.n 800becc { return HAL_ERROR; - 800aaa0: 2301 movs r3, #1 - 800aaa2: e030 b.n 800ab06 + 800bec8: 2301 movs r3, #1 + 800beca: e030 b.n 800bf2e } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800aaa4: 68fb ldr r3, [r7, #12] - 800aaa6: 2200 movs r2, #0 - 800aaa8: 661a str r2, [r3, #96] ; 0x60 + 800becc: 68fb ldr r3, [r7, #12] + 800bece: 2200 movs r2, #0 + 800bed0: 661a str r2, [r3, #96] ; 0x60 if (!(IS_LPUART_INSTANCE(huart->Instance))) - 800aaaa: 68fb ldr r3, [r7, #12] - 800aaac: 681b ldr r3, [r3, #0] - 800aaae: 4a18 ldr r2, [pc, #96] ; (800ab10 ) - 800aab0: 4293 cmp r3, r2 - 800aab2: d01f beq.n 800aaf4 + 800bed2: 68fb ldr r3, [r7, #12] + 800bed4: 681b ldr r3, [r3, #0] + 800bed6: 4a18 ldr r2, [pc, #96] ; (800bf38 ) + 800bed8: 4293 cmp r3, r2 + 800beda: d01f beq.n 800bf1c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 800aab4: 68fb ldr r3, [r7, #12] - 800aab6: 681b ldr r3, [r3, #0] - 800aab8: 685b ldr r3, [r3, #4] - 800aaba: f403 0300 and.w r3, r3, #8388608 ; 0x800000 - 800aabe: 2b00 cmp r3, #0 - 800aac0: d018 beq.n 800aaf4 + 800bedc: 68fb ldr r3, [r7, #12] + 800bede: 681b ldr r3, [r3, #0] + 800bee0: 685b ldr r3, [r3, #4] + 800bee2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800bee6: 2b00 cmp r3, #0 + 800bee8: d018 beq.n 800bf1c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 800aac2: 68fb ldr r3, [r7, #12] - 800aac4: 681b ldr r3, [r3, #0] - 800aac6: 617b str r3, [r7, #20] + 800beea: 68fb ldr r3, [r7, #12] + 800beec: 681b ldr r3, [r3, #0] + 800beee: 617b str r3, [r7, #20] + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800aac8: 697b ldr r3, [r7, #20] - 800aaca: e853 3f00 ldrex r3, [r3] - 800aace: 613b str r3, [r7, #16] + 800bef0: 697b ldr r3, [r7, #20] + 800bef2: e853 3f00 ldrex r3, [r3] + 800bef6: 613b str r3, [r7, #16] return(result); - 800aad0: 693b ldr r3, [r7, #16] - 800aad2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 - 800aad6: 627b str r3, [r7, #36] ; 0x24 - 800aad8: 68fb ldr r3, [r7, #12] - 800aada: 681b ldr r3, [r3, #0] - 800aadc: 461a mov r2, r3 - 800aade: 6a7b ldr r3, [r7, #36] ; 0x24 - 800aae0: 623b str r3, [r7, #32] - 800aae2: 61fa str r2, [r7, #28] + 800bef8: 693b ldr r3, [r7, #16] + 800befa: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 800befe: 627b str r3, [r7, #36] ; 0x24 + 800bf00: 68fb ldr r3, [r7, #12] + 800bf02: 681b ldr r3, [r3, #0] + 800bf04: 461a mov r2, r3 + 800bf06: 6a7b ldr r3, [r7, #36] ; 0x24 + 800bf08: 623b str r3, [r7, #32] + 800bf0a: 61fa str r2, [r7, #28] + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800aae4: 69f9 ldr r1, [r7, #28] - 800aae6: 6a3a ldr r2, [r7, #32] - 800aae8: e841 2300 strex r3, r2, [r1] - 800aaec: 61bb str r3, [r7, #24] + 800bf0c: 69f9 ldr r1, [r7, #28] + 800bf0e: 6a3a ldr r2, [r7, #32] + 800bf10: e841 2300 strex r3, r2, [r1] + 800bf14: 61bb str r3, [r7, #24] return(result); - 800aaee: 69bb ldr r3, [r7, #24] - 800aaf0: 2b00 cmp r3, #0 - 800aaf2: d1e6 bne.n 800aac2 + 800bf16: 69bb ldr r3, [r7, #24] + 800bf18: 2b00 cmp r3, #0 + 800bf1a: d1e6 bne.n 800beea } } return (UART_Start_Receive_DMA(huart, pData, Size)); - 800aaf4: 88fb ldrh r3, [r7, #6] - 800aaf6: 461a mov r2, r3 - 800aaf8: 68b9 ldr r1, [r7, #8] - 800aafa: 68f8 ldr r0, [r7, #12] - 800aafc: f000 fff8 bl 800baf0 - 800ab00: 4603 mov r3, r0 - 800ab02: e000 b.n 800ab06 + 800bf1c: 88fb ldrh r3, [r7, #6] + 800bf1e: 461a mov r2, r3 + 800bf20: 68b9 ldr r1, [r7, #8] + 800bf22: 68f8 ldr r0, [r7, #12] + 800bf24: f000 fff8 bl 800cf18 + 800bf28: 4603 mov r3, r0 + 800bf2a: e000 b.n 800bf2e } else { return HAL_BUSY; - 800ab04: 2302 movs r3, #2 + 800bf2c: 2302 movs r3, #2 } } - 800ab06: 4618 mov r0, r3 - 800ab08: 3728 adds r7, #40 ; 0x28 - 800ab0a: 46bd mov sp, r7 - 800ab0c: bd80 pop {r7, pc} - 800ab0e: bf00 nop - 800ab10: 40008000 .word 0x40008000 + 800bf2e: 4618 mov r0, r3 + 800bf30: 3728 adds r7, #40 ; 0x28 + 800bf32: 46bd mov sp, r7 + 800bf34: bd80 pop {r7, pc} + 800bf36: bf00 nop + 800bf38: 40008000 .word 0x40008000 -0800ab14 : +0800bf3c : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { - 800ab14: b580 push {r7, lr} - 800ab16: b0a0 sub sp, #128 ; 0x80 - 800ab18: af00 add r7, sp, #0 - 800ab1a: 6078 str r0, [r7, #4] + 800bf3c: b580 push {r7, lr} + 800bf3e: b0a0 sub sp, #128 ; 0x80 + 800bf40: af00 add r7, sp, #0 + 800bf42: 6078 str r0, [r7, #4] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); #else /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - 800ab1c: 687b ldr r3, [r7, #4] - 800ab1e: 681b ldr r3, [r3, #0] - 800ab20: 65fb str r3, [r7, #92] ; 0x5c + 800bf44: 687b ldr r3, [r7, #4] + 800bf46: 681b ldr r3, [r3, #0] + 800bf48: 65fb str r3, [r7, #92] ; 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800ab22: 6dfb ldr r3, [r7, #92] ; 0x5c - 800ab24: e853 3f00 ldrex r3, [r3] - 800ab28: 65bb str r3, [r7, #88] ; 0x58 + 800bf4a: 6dfb ldr r3, [r7, #92] ; 0x5c + 800bf4c: e853 3f00 ldrex r3, [r3] + 800bf50: 65bb str r3, [r7, #88] ; 0x58 return(result); - 800ab2a: 6dbb ldr r3, [r7, #88] ; 0x58 - 800ab2c: f423 73f0 bic.w r3, r3, #480 ; 0x1e0 - 800ab30: 67fb str r3, [r7, #124] ; 0x7c - 800ab32: 687b ldr r3, [r7, #4] - 800ab34: 681b ldr r3, [r3, #0] - 800ab36: 461a mov r2, r3 - 800ab38: 6ffb ldr r3, [r7, #124] ; 0x7c - 800ab3a: 66bb str r3, [r7, #104] ; 0x68 - 800ab3c: 667a str r2, [r7, #100] ; 0x64 + 800bf52: 6dbb ldr r3, [r7, #88] ; 0x58 + 800bf54: f423 73f0 bic.w r3, r3, #480 ; 0x1e0 + 800bf58: 67fb str r3, [r7, #124] ; 0x7c + 800bf5a: 687b ldr r3, [r7, #4] + 800bf5c: 681b ldr r3, [r3, #0] + 800bf5e: 461a mov r2, r3 + 800bf60: 6ffb ldr r3, [r7, #124] ; 0x7c + 800bf62: 66bb str r3, [r7, #104] ; 0x68 + 800bf64: 667a str r2, [r7, #100] ; 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800ab3e: 6e79 ldr r1, [r7, #100] ; 0x64 - 800ab40: 6eba ldr r2, [r7, #104] ; 0x68 - 800ab42: e841 2300 strex r3, r2, [r1] - 800ab46: 663b str r3, [r7, #96] ; 0x60 + 800bf66: 6e79 ldr r1, [r7, #100] ; 0x64 + 800bf68: 6eba ldr r2, [r7, #104] ; 0x68 + 800bf6a: e841 2300 strex r3, r2, [r1] + 800bf6e: 663b str r3, [r7, #96] ; 0x60 return(result); - 800ab48: 6e3b ldr r3, [r7, #96] ; 0x60 - 800ab4a: 2b00 cmp r3, #0 - 800ab4c: d1e6 bne.n 800ab1c + 800bf70: 6e3b ldr r3, [r7, #96] ; 0x60 + 800bf72: 2b00 cmp r3, #0 + 800bf74: d1e6 bne.n 800bf44 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800ab4e: 687b ldr r3, [r7, #4] - 800ab50: 681b ldr r3, [r3, #0] - 800ab52: 3308 adds r3, #8 - 800ab54: 64bb str r3, [r7, #72] ; 0x48 + 800bf76: 687b ldr r3, [r7, #4] + 800bf78: 681b ldr r3, [r3, #0] + 800bf7a: 3308 adds r3, #8 + 800bf7c: 64bb str r3, [r7, #72] ; 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800ab56: 6cbb ldr r3, [r7, #72] ; 0x48 - 800ab58: e853 3f00 ldrex r3, [r3] - 800ab5c: 647b str r3, [r7, #68] ; 0x44 + 800bf7e: 6cbb ldr r3, [r7, #72] ; 0x48 + 800bf80: e853 3f00 ldrex r3, [r3] + 800bf84: 647b str r3, [r7, #68] ; 0x44 return(result); - 800ab5e: 6c7b ldr r3, [r7, #68] ; 0x44 - 800ab60: f023 0301 bic.w r3, r3, #1 - 800ab64: 67bb str r3, [r7, #120] ; 0x78 - 800ab66: 687b ldr r3, [r7, #4] - 800ab68: 681b ldr r3, [r3, #0] - 800ab6a: 3308 adds r3, #8 - 800ab6c: 6fba ldr r2, [r7, #120] ; 0x78 - 800ab6e: 657a str r2, [r7, #84] ; 0x54 - 800ab70: 653b str r3, [r7, #80] ; 0x50 + 800bf86: 6c7b ldr r3, [r7, #68] ; 0x44 + 800bf88: f023 0301 bic.w r3, r3, #1 + 800bf8c: 67bb str r3, [r7, #120] ; 0x78 + 800bf8e: 687b ldr r3, [r7, #4] + 800bf90: 681b ldr r3, [r3, #0] + 800bf92: 3308 adds r3, #8 + 800bf94: 6fba ldr r2, [r7, #120] ; 0x78 + 800bf96: 657a str r2, [r7, #84] ; 0x54 + 800bf98: 653b str r3, [r7, #80] ; 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800ab72: 6d39 ldr r1, [r7, #80] ; 0x50 - 800ab74: 6d7a ldr r2, [r7, #84] ; 0x54 - 800ab76: e841 2300 strex r3, r2, [r1] - 800ab7a: 64fb str r3, [r7, #76] ; 0x4c + 800bf9a: 6d39 ldr r1, [r7, #80] ; 0x50 + 800bf9c: 6d7a ldr r2, [r7, #84] ; 0x54 + 800bf9e: e841 2300 strex r3, r2, [r1] + 800bfa2: 64fb str r3, [r7, #76] ; 0x4c return(result); - 800ab7c: 6cfb ldr r3, [r7, #76] ; 0x4c - 800ab7e: 2b00 cmp r3, #0 - 800ab80: d1e5 bne.n 800ab4e + 800bfa4: 6cfb ldr r3, [r7, #76] ; 0x4c + 800bfa6: 2b00 cmp r3, #0 + 800bfa8: d1e5 bne.n 800bf76 #endif /* USART_CR1_FIFOEN */ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800ab82: 687b ldr r3, [r7, #4] - 800ab84: 6e1b ldr r3, [r3, #96] ; 0x60 - 800ab86: 2b01 cmp r3, #1 - 800ab88: d118 bne.n 800abbc + 800bfaa: 687b ldr r3, [r7, #4] + 800bfac: 6e1b ldr r3, [r3, #96] ; 0x60 + 800bfae: 2b01 cmp r3, #1 + 800bfb0: d118 bne.n 800bfe4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - 800ab8a: 687b ldr r3, [r7, #4] - 800ab8c: 681b ldr r3, [r3, #0] - 800ab8e: 637b str r3, [r7, #52] ; 0x34 + 800bfb2: 687b ldr r3, [r7, #4] + 800bfb4: 681b ldr r3, [r3, #0] + 800bfb6: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800ab90: 6b7b ldr r3, [r7, #52] ; 0x34 - 800ab92: e853 3f00 ldrex r3, [r3] - 800ab96: 633b str r3, [r7, #48] ; 0x30 + 800bfb8: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bfba: e853 3f00 ldrex r3, [r3] + 800bfbe: 633b str r3, [r7, #48] ; 0x30 return(result); - 800ab98: 6b3b ldr r3, [r7, #48] ; 0x30 - 800ab9a: f023 0310 bic.w r3, r3, #16 - 800ab9e: 677b str r3, [r7, #116] ; 0x74 - 800aba0: 687b ldr r3, [r7, #4] - 800aba2: 681b ldr r3, [r3, #0] - 800aba4: 461a mov r2, r3 - 800aba6: 6f7b ldr r3, [r7, #116] ; 0x74 - 800aba8: 643b str r3, [r7, #64] ; 0x40 - 800abaa: 63fa str r2, [r7, #60] ; 0x3c + 800bfc0: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bfc2: f023 0310 bic.w r3, r3, #16 + 800bfc6: 677b str r3, [r7, #116] ; 0x74 + 800bfc8: 687b ldr r3, [r7, #4] + 800bfca: 681b ldr r3, [r3, #0] + 800bfcc: 461a mov r2, r3 + 800bfce: 6f7b ldr r3, [r7, #116] ; 0x74 + 800bfd0: 643b str r3, [r7, #64] ; 0x40 + 800bfd2: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800abac: 6bf9 ldr r1, [r7, #60] ; 0x3c - 800abae: 6c3a ldr r2, [r7, #64] ; 0x40 - 800abb0: e841 2300 strex r3, r2, [r1] - 800abb4: 63bb str r3, [r7, #56] ; 0x38 + 800bfd4: 6bf9 ldr r1, [r7, #60] ; 0x3c + 800bfd6: 6c3a ldr r2, [r7, #64] ; 0x40 + 800bfd8: e841 2300 strex r3, r2, [r1] + 800bfdc: 63bb str r3, [r7, #56] ; 0x38 return(result); - 800abb6: 6bbb ldr r3, [r7, #56] ; 0x38 - 800abb8: 2b00 cmp r3, #0 - 800abba: d1e6 bne.n 800ab8a + 800bfde: 6bbb ldr r3, [r7, #56] ; 0x38 + 800bfe0: 2b00 cmp r3, #0 + 800bfe2: d1e6 bne.n 800bfb2 } /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - 800abbc: 687b ldr r3, [r7, #4] - 800abbe: 681b ldr r3, [r3, #0] - 800abc0: 689b ldr r3, [r3, #8] - 800abc2: f003 0380 and.w r3, r3, #128 ; 0x80 - 800abc6: 2b80 cmp r3, #128 ; 0x80 - 800abc8: d137 bne.n 800ac3a + 800bfe4: 687b ldr r3, [r7, #4] + 800bfe6: 681b ldr r3, [r3, #0] + 800bfe8: 689b ldr r3, [r3, #8] + 800bfea: f003 0380 and.w r3, r3, #128 ; 0x80 + 800bfee: 2b80 cmp r3, #128 ; 0x80 + 800bff0: d137 bne.n 800c062 { /* Disable the UART DMA Tx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - 800abca: 687b ldr r3, [r7, #4] - 800abcc: 681b ldr r3, [r3, #0] - 800abce: 3308 adds r3, #8 - 800abd0: 623b str r3, [r7, #32] + 800bff2: 687b ldr r3, [r7, #4] + 800bff4: 681b ldr r3, [r3, #0] + 800bff6: 3308 adds r3, #8 + 800bff8: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800abd2: 6a3b ldr r3, [r7, #32] - 800abd4: e853 3f00 ldrex r3, [r3] - 800abd8: 61fb str r3, [r7, #28] + 800bffa: 6a3b ldr r3, [r7, #32] + 800bffc: e853 3f00 ldrex r3, [r3] + 800c000: 61fb str r3, [r7, #28] return(result); - 800abda: 69fb ldr r3, [r7, #28] - 800abdc: f023 0380 bic.w r3, r3, #128 ; 0x80 - 800abe0: 673b str r3, [r7, #112] ; 0x70 - 800abe2: 687b ldr r3, [r7, #4] - 800abe4: 681b ldr r3, [r3, #0] - 800abe6: 3308 adds r3, #8 - 800abe8: 6f3a ldr r2, [r7, #112] ; 0x70 - 800abea: 62fa str r2, [r7, #44] ; 0x2c - 800abec: 62bb str r3, [r7, #40] ; 0x28 + 800c002: 69fb ldr r3, [r7, #28] + 800c004: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800c008: 673b str r3, [r7, #112] ; 0x70 + 800c00a: 687b ldr r3, [r7, #4] + 800c00c: 681b ldr r3, [r3, #0] + 800c00e: 3308 adds r3, #8 + 800c010: 6f3a ldr r2, [r7, #112] ; 0x70 + 800c012: 62fa str r2, [r7, #44] ; 0x2c + 800c014: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800abee: 6ab9 ldr r1, [r7, #40] ; 0x28 - 800abf0: 6afa ldr r2, [r7, #44] ; 0x2c - 800abf2: e841 2300 strex r3, r2, [r1] - 800abf6: 627b str r3, [r7, #36] ; 0x24 + 800c016: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800c018: 6afa ldr r2, [r7, #44] ; 0x2c + 800c01a: e841 2300 strex r3, r2, [r1] + 800c01e: 627b str r3, [r7, #36] ; 0x24 return(result); - 800abf8: 6a7b ldr r3, [r7, #36] ; 0x24 - 800abfa: 2b00 cmp r3, #0 - 800abfc: d1e5 bne.n 800abca + 800c020: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c022: 2b00 cmp r3, #0 + 800c024: d1e5 bne.n 800bff2 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) - 800abfe: 687b ldr r3, [r7, #4] - 800ac00: 6f1b ldr r3, [r3, #112] ; 0x70 - 800ac02: 2b00 cmp r3, #0 - 800ac04: d019 beq.n 800ac3a + 800c026: 687b ldr r3, [r7, #4] + 800c028: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c02a: 2b00 cmp r3, #0 + 800c02c: d019 beq.n 800c062 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - 800ac06: 687b ldr r3, [r7, #4] - 800ac08: 6f1b ldr r3, [r3, #112] ; 0x70 - 800ac0a: 2200 movs r2, #0 - 800ac0c: 639a str r2, [r3, #56] ; 0x38 + 800c02e: 687b ldr r3, [r7, #4] + 800c030: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c032: 2200 movs r2, #0 + 800c034: 639a str r2, [r3, #56] ; 0x38 if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - 800ac0e: 687b ldr r3, [r7, #4] - 800ac10: 6f1b ldr r3, [r3, #112] ; 0x70 - 800ac12: 4618 mov r0, r3 - 800ac14: f7fb fa90 bl 8006138 - 800ac18: 4603 mov r3, r0 - 800ac1a: 2b00 cmp r3, #0 - 800ac1c: d00d beq.n 800ac3a + 800c036: 687b ldr r3, [r7, #4] + 800c038: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c03a: 4618 mov r0, r3 + 800c03c: f7fa fe02 bl 8006c44 + 800c040: 4603 mov r3, r0 + 800c042: 2b00 cmp r3, #0 + 800c044: d00d beq.n 800c062 { if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - 800ac1e: 687b ldr r3, [r7, #4] - 800ac20: 6f1b ldr r3, [r3, #112] ; 0x70 - 800ac22: 4618 mov r0, r3 - 800ac24: f7fb fbb6 bl 8006394 - 800ac28: 4603 mov r3, r0 - 800ac2a: 2b20 cmp r3, #32 - 800ac2c: d105 bne.n 800ac3a + 800c046: 687b ldr r3, [r7, #4] + 800c048: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c04a: 4618 mov r0, r3 + 800c04c: f7fa ff28 bl 8006ea0 + 800c050: 4603 mov r3, r0 + 800c052: 2b20 cmp r3, #32 + 800c054: d105 bne.n 800c062 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - 800ac2e: 687b ldr r3, [r7, #4] - 800ac30: 2210 movs r2, #16 - 800ac32: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c056: 687b ldr r3, [r7, #4] + 800c058: 2210 movs r2, #16 + 800c05a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_TIMEOUT; - 800ac36: 2303 movs r3, #3 - 800ac38: e063 b.n 800ad02 + 800c05e: 2303 movs r3, #3 + 800c060: e063 b.n 800c12a } } } /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800ac3a: 687b ldr r3, [r7, #4] - 800ac3c: 681b ldr r3, [r3, #0] - 800ac3e: 689b ldr r3, [r3, #8] - 800ac40: f003 0340 and.w r3, r3, #64 ; 0x40 - 800ac44: 2b40 cmp r3, #64 ; 0x40 - 800ac46: d137 bne.n 800acb8 + 800c062: 687b ldr r3, [r7, #4] + 800c064: 681b ldr r3, [r3, #0] + 800c066: 689b ldr r3, [r3, #8] + 800c068: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c06c: 2b40 cmp r3, #64 ; 0x40 + 800c06e: d137 bne.n 800c0e0 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 800ac48: 687b ldr r3, [r7, #4] - 800ac4a: 681b ldr r3, [r3, #0] - 800ac4c: 3308 adds r3, #8 - 800ac4e: 60fb str r3, [r7, #12] + 800c070: 687b ldr r3, [r7, #4] + 800c072: 681b ldr r3, [r3, #0] + 800c074: 3308 adds r3, #8 + 800c076: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800ac50: 68fb ldr r3, [r7, #12] - 800ac52: e853 3f00 ldrex r3, [r3] - 800ac56: 60bb str r3, [r7, #8] + 800c078: 68fb ldr r3, [r7, #12] + 800c07a: e853 3f00 ldrex r3, [r3] + 800c07e: 60bb str r3, [r7, #8] return(result); - 800ac58: 68bb ldr r3, [r7, #8] - 800ac5a: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800ac5e: 66fb str r3, [r7, #108] ; 0x6c - 800ac60: 687b ldr r3, [r7, #4] - 800ac62: 681b ldr r3, [r3, #0] - 800ac64: 3308 adds r3, #8 - 800ac66: 6efa ldr r2, [r7, #108] ; 0x6c - 800ac68: 61ba str r2, [r7, #24] - 800ac6a: 617b str r3, [r7, #20] + 800c080: 68bb ldr r3, [r7, #8] + 800c082: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800c086: 66fb str r3, [r7, #108] ; 0x6c + 800c088: 687b ldr r3, [r7, #4] + 800c08a: 681b ldr r3, [r3, #0] + 800c08c: 3308 adds r3, #8 + 800c08e: 6efa ldr r2, [r7, #108] ; 0x6c + 800c090: 61ba str r2, [r7, #24] + 800c092: 617b str r3, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800ac6c: 6979 ldr r1, [r7, #20] - 800ac6e: 69ba ldr r2, [r7, #24] - 800ac70: e841 2300 strex r3, r2, [r1] - 800ac74: 613b str r3, [r7, #16] + 800c094: 6979 ldr r1, [r7, #20] + 800c096: 69ba ldr r2, [r7, #24] + 800c098: e841 2300 strex r3, r2, [r1] + 800c09c: 613b str r3, [r7, #16] return(result); - 800ac76: 693b ldr r3, [r7, #16] - 800ac78: 2b00 cmp r3, #0 - 800ac7a: d1e5 bne.n 800ac48 + 800c09e: 693b ldr r3, [r7, #16] + 800c0a0: 2b00 cmp r3, #0 + 800c0a2: d1e5 bne.n 800c070 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) - 800ac7c: 687b ldr r3, [r7, #4] - 800ac7e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800ac80: 2b00 cmp r3, #0 - 800ac82: d019 beq.n 800acb8 + 800c0a4: 687b ldr r3, [r7, #4] + 800c0a6: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c0a8: 2b00 cmp r3, #0 + 800c0aa: d019 beq.n 800c0e0 { /* Set the UART DMA Abort callback to Null. No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - 800ac84: 687b ldr r3, [r7, #4] - 800ac86: 6f5b ldr r3, [r3, #116] ; 0x74 - 800ac88: 2200 movs r2, #0 - 800ac8a: 639a str r2, [r3, #56] ; 0x38 + 800c0ac: 687b ldr r3, [r7, #4] + 800c0ae: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c0b0: 2200 movs r2, #0 + 800c0b2: 639a str r2, [r3, #56] ; 0x38 if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - 800ac8c: 687b ldr r3, [r7, #4] - 800ac8e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800ac90: 4618 mov r0, r3 - 800ac92: f7fb fa51 bl 8006138 - 800ac96: 4603 mov r3, r0 - 800ac98: 2b00 cmp r3, #0 - 800ac9a: d00d beq.n 800acb8 + 800c0b4: 687b ldr r3, [r7, #4] + 800c0b6: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c0b8: 4618 mov r0, r3 + 800c0ba: f7fa fdc3 bl 8006c44 + 800c0be: 4603 mov r3, r0 + 800c0c0: 2b00 cmp r3, #0 + 800c0c2: d00d beq.n 800c0e0 { if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - 800ac9c: 687b ldr r3, [r7, #4] - 800ac9e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800aca0: 4618 mov r0, r3 - 800aca2: f7fb fb77 bl 8006394 - 800aca6: 4603 mov r3, r0 - 800aca8: 2b20 cmp r3, #32 - 800acaa: d105 bne.n 800acb8 + 800c0c4: 687b ldr r3, [r7, #4] + 800c0c6: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c0c8: 4618 mov r0, r3 + 800c0ca: f7fa fee9 bl 8006ea0 + 800c0ce: 4603 mov r3, r0 + 800c0d0: 2b20 cmp r3, #32 + 800c0d2: d105 bne.n 800c0e0 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - 800acac: 687b ldr r3, [r7, #4] - 800acae: 2210 movs r2, #16 - 800acb0: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c0d4: 687b ldr r3, [r7, #4] + 800c0d6: 2210 movs r2, #16 + 800c0d8: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_TIMEOUT; - 800acb4: 2303 movs r3, #3 - 800acb6: e024 b.n 800ad02 + 800c0dc: 2303 movs r3, #3 + 800c0de: e024 b.n 800c12a } } } /* Reset Tx and Rx transfer counters */ huart->TxXferCount = 0U; - 800acb8: 687b ldr r3, [r7, #4] - 800acba: 2200 movs r2, #0 - 800acbc: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 800c0e0: 687b ldr r3, [r7, #4] + 800c0e2: 2200 movs r2, #0 + 800c0e4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 huart->RxXferCount = 0U; - 800acc0: 687b ldr r3, [r7, #4] - 800acc2: 2200 movs r2, #0 - 800acc4: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 800c0e8: 687b ldr r3, [r7, #4] + 800c0ea: 2200 movs r2, #0 + 800c0ec: f8a3 205a strh.w r2, [r3, #90] ; 0x5a /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - 800acc8: 687b ldr r3, [r7, #4] - 800acca: 681b ldr r3, [r3, #0] - 800accc: 220f movs r2, #15 - 800acce: 621a str r2, [r3, #32] + 800c0f0: 687b ldr r3, [r7, #4] + 800c0f2: 681b ldr r3, [r3, #0] + 800c0f4: 220f movs r2, #15 + 800c0f6: 621a str r2, [r3, #32] __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); } #endif /* USART_CR1_FIFOEN */ /* Discard the received data */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - 800acd0: 687b ldr r3, [r7, #4] - 800acd2: 681b ldr r3, [r3, #0] - 800acd4: 8b1b ldrh r3, [r3, #24] - 800acd6: b29a uxth r2, r3 - 800acd8: 687b ldr r3, [r7, #4] - 800acda: 681b ldr r3, [r3, #0] - 800acdc: f042 0208 orr.w r2, r2, #8 - 800ace0: b292 uxth r2, r2 - 800ace2: 831a strh r2, [r3, #24] + 800c0f8: 687b ldr r3, [r7, #4] + 800c0fa: 681b ldr r3, [r3, #0] + 800c0fc: 8b1b ldrh r3, [r3, #24] + 800c0fe: b29a uxth r2, r3 + 800c100: 687b ldr r3, [r7, #4] + 800c102: 681b ldr r3, [r3, #0] + 800c104: f042 0208 orr.w r2, r2, #8 + 800c108: b292 uxth r2, r2 + 800c10a: 831a strh r2, [r3, #24] /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; - 800ace4: 687b ldr r3, [r7, #4] - 800ace6: 2220 movs r2, #32 - 800ace8: 67da str r2, [r3, #124] ; 0x7c + 800c10c: 687b ldr r3, [r7, #4] + 800c10e: 2220 movs r2, #32 + 800c110: 67da str r2, [r3, #124] ; 0x7c huart->RxState = HAL_UART_STATE_READY; - 800acea: 687b ldr r3, [r7, #4] - 800acec: 2220 movs r2, #32 - 800acee: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800c112: 687b ldr r3, [r7, #4] + 800c114: 2220 movs r2, #32 + 800c116: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800acf2: 687b ldr r3, [r7, #4] - 800acf4: 2200 movs r2, #0 - 800acf6: 661a str r2, [r3, #96] ; 0x60 + 800c11a: 687b ldr r3, [r7, #4] + 800c11c: 2200 movs r2, #0 + 800c11e: 661a str r2, [r3, #96] ; 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; - 800acf8: 687b ldr r3, [r7, #4] - 800acfa: 2200 movs r2, #0 - 800acfc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c120: 687b ldr r3, [r7, #4] + 800c122: 2200 movs r2, #0 + 800c124: f8c3 2084 str.w r2, [r3, #132] ; 0x84 return HAL_OK; - 800ad00: 2300 movs r3, #0 + 800c128: 2300 movs r3, #0 } - 800ad02: 4618 mov r0, r3 - 800ad04: 3780 adds r7, #128 ; 0x80 - 800ad06: 46bd mov sp, r7 - 800ad08: bd80 pop {r7, pc} + 800c12a: 4618 mov r0, r3 + 800c12c: 3780 adds r7, #128 ; 0x80 + 800c12e: 46bd mov sp, r7 + 800c130: bd80 pop {r7, pc} ... -0800ad0c : +0800c134 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - 800ad0c: b580 push {r7, lr} - 800ad0e: b0ba sub sp, #232 ; 0xe8 - 800ad10: af00 add r7, sp, #0 - 800ad12: 6078 str r0, [r7, #4] + 800c134: b580 push {r7, lr} + 800c136: b0ba sub sp, #232 ; 0xe8 + 800c138: af00 add r7, sp, #0 + 800c13a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); - 800ad14: 687b ldr r3, [r7, #4] - 800ad16: 681b ldr r3, [r3, #0] - 800ad18: 69db ldr r3, [r3, #28] - 800ad1a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800c13c: 687b ldr r3, [r7, #4] + 800c13e: 681b ldr r3, [r3, #0] + 800c140: 69db ldr r3, [r3, #28] + 800c142: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); - 800ad1e: 687b ldr r3, [r7, #4] - 800ad20: 681b ldr r3, [r3, #0] - 800ad22: 681b ldr r3, [r3, #0] - 800ad24: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 800c146: 687b ldr r3, [r7, #4] + 800c148: 681b ldr r3, [r3, #0] + 800c14a: 681b ldr r3, [r3, #0] + 800c14c: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); - 800ad28: 687b ldr r3, [r7, #4] - 800ad2a: 681b ldr r3, [r3, #0] - 800ad2c: 689b ldr r3, [r3, #8] - 800ad2e: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + 800c150: 687b ldr r3, [r7, #4] + 800c152: 681b ldr r3, [r3, #0] + 800c154: 689b ldr r3, [r3, #8] + 800c156: f8c7 30dc str.w r3, [r7, #220] ; 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - 800ad32: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4 - 800ad36: f640 030f movw r3, #2063 ; 0x80f - 800ad3a: 4013 ands r3, r2 - 800ad3c: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 800c15a: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4 + 800c15e: f640 030f movw r3, #2063 ; 0x80f + 800c162: 4013 ands r3, r2 + 800c164: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 if (errorflags == 0U) - 800ad40: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800ad44: 2b00 cmp r3, #0 - 800ad46: d115 bne.n 800ad74 + 800c168: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800c16c: 2b00 cmp r3, #0 + 800c16e: d115 bne.n 800c19c #if defined(USART_CR1_FIFOEN) if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else if (((isrflags & USART_ISR_RXNE) != 0U) - 800ad48: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ad4c: f003 0320 and.w r3, r3, #32 - 800ad50: 2b00 cmp r3, #0 - 800ad52: d00f beq.n 800ad74 + 800c170: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c174: f003 0320 and.w r3, r3, #32 + 800c178: 2b00 cmp r3, #0 + 800c17a: d00f beq.n 800c19c && ((cr1its & USART_CR1_RXNEIE) != 0U)) - 800ad54: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800ad58: f003 0320 and.w r3, r3, #32 - 800ad5c: 2b00 cmp r3, #0 - 800ad5e: d009 beq.n 800ad74 + 800c17c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c180: f003 0320 and.w r3, r3, #32 + 800c184: 2b00 cmp r3, #0 + 800c186: d009 beq.n 800c19c #endif /* USART_CR1_FIFOEN */ { if (huart->RxISR != NULL) - 800ad60: 687b ldr r3, [r7, #4] - 800ad62: 6e9b ldr r3, [r3, #104] ; 0x68 - 800ad64: 2b00 cmp r3, #0 - 800ad66: f000 82ae beq.w 800b2c6 + 800c188: 687b ldr r3, [r7, #4] + 800c18a: 6e9b ldr r3, [r3, #104] ; 0x68 + 800c18c: 2b00 cmp r3, #0 + 800c18e: f000 82ae beq.w 800c6ee { huart->RxISR(huart); - 800ad6a: 687b ldr r3, [r7, #4] - 800ad6c: 6e9b ldr r3, [r3, #104] ; 0x68 - 800ad6e: 6878 ldr r0, [r7, #4] - 800ad70: 4798 blx r3 + 800c192: 687b ldr r3, [r7, #4] + 800c194: 6e9b ldr r3, [r3, #104] ; 0x68 + 800c196: 6878 ldr r0, [r7, #4] + 800c198: 4798 blx r3 } return; - 800ad72: e2a8 b.n 800b2c6 + 800c19a: e2a8 b.n 800c6ee #if defined(USART_CR1_FIFOEN) if ((errorflags != 0U) && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) #else if ((errorflags != 0U) - 800ad74: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800ad78: 2b00 cmp r3, #0 - 800ad7a: f000 8117 beq.w 800afac + 800c19c: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800c1a0: 2b00 cmp r3, #0 + 800c1a2: f000 8117 beq.w 800c3d4 && (((cr3its & USART_CR3_EIE) != 0U) - 800ad7e: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800ad82: f003 0301 and.w r3, r3, #1 - 800ad86: 2b00 cmp r3, #0 - 800ad88: d106 bne.n 800ad98 + 800c1a6: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800c1aa: f003 0301 and.w r3, r3, #1 + 800c1ae: 2b00 cmp r3, #0 + 800c1b0: d106 bne.n 800c1c0 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) - 800ad8a: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0 - 800ad8e: 4b85 ldr r3, [pc, #532] ; (800afa4 ) - 800ad90: 4013 ands r3, r2 - 800ad92: 2b00 cmp r3, #0 - 800ad94: f000 810a beq.w 800afac + 800c1b2: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0 + 800c1b6: 4b85 ldr r3, [pc, #532] ; (800c3cc ) + 800c1b8: 4013 ands r3, r2 + 800c1ba: 2b00 cmp r3, #0 + 800c1bc: f000 810a beq.w 800c3d4 #endif /* USART_CR1_FIFOEN */ { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - 800ad98: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ad9c: f003 0301 and.w r3, r3, #1 - 800ada0: 2b00 cmp r3, #0 - 800ada2: d011 beq.n 800adc8 - 800ada4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800ada8: f403 7380 and.w r3, r3, #256 ; 0x100 - 800adac: 2b00 cmp r3, #0 - 800adae: d00b beq.n 800adc8 + 800c1c0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c1c4: f003 0301 and.w r3, r3, #1 + 800c1c8: 2b00 cmp r3, #0 + 800c1ca: d011 beq.n 800c1f0 + 800c1cc: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c1d0: f403 7380 and.w r3, r3, #256 ; 0x100 + 800c1d4: 2b00 cmp r3, #0 + 800c1d6: d00b beq.n 800c1f0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - 800adb0: 687b ldr r3, [r7, #4] - 800adb2: 681b ldr r3, [r3, #0] - 800adb4: 2201 movs r2, #1 - 800adb6: 621a str r2, [r3, #32] + 800c1d8: 687b ldr r3, [r7, #4] + 800c1da: 681b ldr r3, [r3, #0] + 800c1dc: 2201 movs r2, #1 + 800c1de: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; - 800adb8: 687b ldr r3, [r7, #4] - 800adba: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800adbe: f043 0201 orr.w r2, r3, #1 - 800adc2: 687b ldr r3, [r7, #4] - 800adc4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c1e0: 687b ldr r3, [r7, #4] + 800c1e2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c1e6: f043 0201 orr.w r2, r3, #1 + 800c1ea: 687b ldr r3, [r7, #4] + 800c1ec: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 800adc8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800adcc: f003 0302 and.w r3, r3, #2 - 800add0: 2b00 cmp r3, #0 - 800add2: d011 beq.n 800adf8 - 800add4: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800add8: f003 0301 and.w r3, r3, #1 - 800addc: 2b00 cmp r3, #0 - 800adde: d00b beq.n 800adf8 + 800c1f0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c1f4: f003 0302 and.w r3, r3, #2 + 800c1f8: 2b00 cmp r3, #0 + 800c1fa: d011 beq.n 800c220 + 800c1fc: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800c200: f003 0301 and.w r3, r3, #1 + 800c204: 2b00 cmp r3, #0 + 800c206: d00b beq.n 800c220 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - 800ade0: 687b ldr r3, [r7, #4] - 800ade2: 681b ldr r3, [r3, #0] - 800ade4: 2202 movs r2, #2 - 800ade6: 621a str r2, [r3, #32] + 800c208: 687b ldr r3, [r7, #4] + 800c20a: 681b ldr r3, [r3, #0] + 800c20c: 2202 movs r2, #2 + 800c20e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; - 800ade8: 687b ldr r3, [r7, #4] - 800adea: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800adee: f043 0204 orr.w r2, r3, #4 - 800adf2: 687b ldr r3, [r7, #4] - 800adf4: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c210: 687b ldr r3, [r7, #4] + 800c212: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c216: f043 0204 orr.w r2, r3, #4 + 800c21a: 687b ldr r3, [r7, #4] + 800c21c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 800adf8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800adfc: f003 0304 and.w r3, r3, #4 - 800ae00: 2b00 cmp r3, #0 - 800ae02: d011 beq.n 800ae28 - 800ae04: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800ae08: f003 0301 and.w r3, r3, #1 - 800ae0c: 2b00 cmp r3, #0 - 800ae0e: d00b beq.n 800ae28 + 800c220: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c224: f003 0304 and.w r3, r3, #4 + 800c228: 2b00 cmp r3, #0 + 800c22a: d011 beq.n 800c250 + 800c22c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800c230: f003 0301 and.w r3, r3, #1 + 800c234: 2b00 cmp r3, #0 + 800c236: d00b beq.n 800c250 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - 800ae10: 687b ldr r3, [r7, #4] - 800ae12: 681b ldr r3, [r3, #0] - 800ae14: 2204 movs r2, #4 - 800ae16: 621a str r2, [r3, #32] + 800c238: 687b ldr r3, [r7, #4] + 800c23a: 681b ldr r3, [r3, #0] + 800c23c: 2204 movs r2, #4 + 800c23e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; - 800ae18: 687b ldr r3, [r7, #4] - 800ae1a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800ae1e: f043 0202 orr.w r2, r3, #2 - 800ae22: 687b ldr r3, [r7, #4] - 800ae24: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c240: 687b ldr r3, [r7, #4] + 800c242: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c246: f043 0202 orr.w r2, r3, #2 + 800c24a: 687b ldr r3, [r7, #4] + 800c24c: f8c3 2084 str.w r2, [r3, #132] ; 0x84 #if defined(USART_CR1_FIFOEN) if (((isrflags & USART_ISR_ORE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) #else if (((isrflags & USART_ISR_ORE) != 0U) - 800ae28: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ae2c: f003 0308 and.w r3, r3, #8 - 800ae30: 2b00 cmp r3, #0 - 800ae32: d017 beq.n 800ae64 + 800c250: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c254: f003 0308 and.w r3, r3, #8 + 800c258: 2b00 cmp r3, #0 + 800c25a: d017 beq.n 800c28c && (((cr1its & USART_CR1_RXNEIE) != 0U) || - 800ae34: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800ae38: f003 0320 and.w r3, r3, #32 - 800ae3c: 2b00 cmp r3, #0 - 800ae3e: d105 bne.n 800ae4c + 800c25c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c260: f003 0320 and.w r3, r3, #32 + 800c264: 2b00 cmp r3, #0 + 800c266: d105 bne.n 800c274 ((cr3its & USART_CR3_EIE) != 0U))) - 800ae40: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800ae44: f003 0301 and.w r3, r3, #1 + 800c268: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800c26c: f003 0301 and.w r3, r3, #1 && (((cr1its & USART_CR1_RXNEIE) != 0U) || - 800ae48: 2b00 cmp r3, #0 - 800ae4a: d00b beq.n 800ae64 + 800c270: 2b00 cmp r3, #0 + 800c272: d00b beq.n 800c28c #endif /* USART_CR1_FIFOEN */ { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 800ae4c: 687b ldr r3, [r7, #4] - 800ae4e: 681b ldr r3, [r3, #0] - 800ae50: 2208 movs r2, #8 - 800ae52: 621a str r2, [r3, #32] + 800c274: 687b ldr r3, [r7, #4] + 800c276: 681b ldr r3, [r3, #0] + 800c278: 2208 movs r2, #8 + 800c27a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; - 800ae54: 687b ldr r3, [r7, #4] - 800ae56: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800ae5a: f043 0208 orr.w r2, r3, #8 - 800ae5e: 687b ldr r3, [r7, #4] - 800ae60: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c27c: 687b ldr r3, [r7, #4] + 800c27e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c282: f043 0208 orr.w r2, r3, #8 + 800c286: 687b ldr r3, [r7, #4] + 800c288: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - 800ae64: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ae68: f403 6300 and.w r3, r3, #2048 ; 0x800 - 800ae6c: 2b00 cmp r3, #0 - 800ae6e: d012 beq.n 800ae96 - 800ae70: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800ae74: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 - 800ae78: 2b00 cmp r3, #0 - 800ae7a: d00c beq.n 800ae96 + 800c28c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c290: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800c294: 2b00 cmp r3, #0 + 800c296: d012 beq.n 800c2be + 800c298: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c29c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 800c2a0: 2b00 cmp r3, #0 + 800c2a2: d00c beq.n 800c2be { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 800ae7c: 687b ldr r3, [r7, #4] - 800ae7e: 681b ldr r3, [r3, #0] - 800ae80: f44f 6200 mov.w r2, #2048 ; 0x800 - 800ae84: 621a str r2, [r3, #32] + 800c2a4: 687b ldr r3, [r7, #4] + 800c2a6: 681b ldr r3, [r3, #0] + 800c2a8: f44f 6200 mov.w r2, #2048 ; 0x800 + 800c2ac: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; - 800ae86: 687b ldr r3, [r7, #4] - 800ae88: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800ae8c: f043 0220 orr.w r2, r3, #32 - 800ae90: 687b ldr r3, [r7, #4] - 800ae92: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c2ae: 687b ldr r3, [r7, #4] + 800c2b0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c2b4: f043 0220 orr.w r2, r3, #32 + 800c2b8: 687b ldr r3, [r7, #4] + 800c2ba: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) - 800ae96: 687b ldr r3, [r7, #4] - 800ae98: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800ae9c: 2b00 cmp r3, #0 - 800ae9e: f000 8214 beq.w 800b2ca + 800c2be: 687b ldr r3, [r7, #4] + 800c2c0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c2c4: 2b00 cmp r3, #0 + 800c2c6: f000 8214 beq.w 800c6f2 #if defined(USART_CR1_FIFOEN) if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) #else if (((isrflags & USART_ISR_RXNE) != 0U) - 800aea2: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800aea6: f003 0320 and.w r3, r3, #32 - 800aeaa: 2b00 cmp r3, #0 - 800aeac: d00d beq.n 800aeca + 800c2ca: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c2ce: f003 0320 and.w r3, r3, #32 + 800c2d2: 2b00 cmp r3, #0 + 800c2d4: d00d beq.n 800c2f2 && ((cr1its & USART_CR1_RXNEIE) != 0U)) - 800aeae: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800aeb2: f003 0320 and.w r3, r3, #32 - 800aeb6: 2b00 cmp r3, #0 - 800aeb8: d007 beq.n 800aeca + 800c2d6: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c2da: f003 0320 and.w r3, r3, #32 + 800c2de: 2b00 cmp r3, #0 + 800c2e0: d007 beq.n 800c2f2 #endif /* USART_CR1_FIFOEN */ { if (huart->RxISR != NULL) - 800aeba: 687b ldr r3, [r7, #4] - 800aebc: 6e9b ldr r3, [r3, #104] ; 0x68 - 800aebe: 2b00 cmp r3, #0 - 800aec0: d003 beq.n 800aeca + 800c2e2: 687b ldr r3, [r7, #4] + 800c2e4: 6e9b ldr r3, [r3, #104] ; 0x68 + 800c2e6: 2b00 cmp r3, #0 + 800c2e8: d003 beq.n 800c2f2 { huart->RxISR(huart); - 800aec2: 687b ldr r3, [r7, #4] - 800aec4: 6e9b ldr r3, [r3, #104] ; 0x68 - 800aec6: 6878 ldr r0, [r7, #4] - 800aec8: 4798 blx r3 + 800c2ea: 687b ldr r3, [r7, #4] + 800c2ec: 6e9b ldr r3, [r3, #104] ; 0x68 + 800c2ee: 6878 ldr r0, [r7, #4] + 800c2f0: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; - 800aeca: 687b ldr r3, [r7, #4] - 800aecc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800aed0: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + 800c2f2: 687b ldr r3, [r7, #4] + 800c2f4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800c2f8: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - 800aed4: 687b ldr r3, [r7, #4] - 800aed6: 681b ldr r3, [r3, #0] - 800aed8: 689b ldr r3, [r3, #8] - 800aeda: f003 0340 and.w r3, r3, #64 ; 0x40 - 800aede: 2b40 cmp r3, #64 ; 0x40 - 800aee0: d005 beq.n 800aeee + 800c2fc: 687b ldr r3, [r7, #4] + 800c2fe: 681b ldr r3, [r3, #0] + 800c300: 689b ldr r3, [r3, #8] + 800c302: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c306: 2b40 cmp r3, #64 ; 0x40 + 800c308: d005 beq.n 800c316 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) - 800aee2: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 800aee6: f003 0328 and.w r3, r3, #40 ; 0x28 + 800c30a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 800c30e: f003 0328 and.w r3, r3, #40 ; 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - 800aeea: 2b00 cmp r3, #0 - 800aeec: d04f beq.n 800af8e + 800c312: 2b00 cmp r3, #0 + 800c314: d04f beq.n 800c3b6 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - 800aeee: 6878 ldr r0, [r7, #4] - 800aef0: f000 fec4 bl 800bc7c + 800c316: 6878 ldr r0, [r7, #4] + 800c318: f000 fec4 bl 800d0a4 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800aef4: 687b ldr r3, [r7, #4] - 800aef6: 681b ldr r3, [r3, #0] - 800aef8: 689b ldr r3, [r3, #8] - 800aefa: f003 0340 and.w r3, r3, #64 ; 0x40 - 800aefe: 2b40 cmp r3, #64 ; 0x40 - 800af00: d141 bne.n 800af86 + 800c31c: 687b ldr r3, [r7, #4] + 800c31e: 681b ldr r3, [r3, #0] + 800c320: 689b ldr r3, [r3, #8] + 800c322: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c326: 2b40 cmp r3, #64 ; 0x40 + 800c328: d141 bne.n 800c3ae { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 800af02: 687b ldr r3, [r7, #4] - 800af04: 681b ldr r3, [r3, #0] - 800af06: 3308 adds r3, #8 - 800af08: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 800c32a: 687b ldr r3, [r7, #4] + 800c32c: 681b ldr r3, [r3, #0] + 800c32e: 3308 adds r3, #8 + 800c330: f8c7 309c str.w r3, [r7, #156] ; 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800af0c: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c - 800af10: e853 3f00 ldrex r3, [r3] - 800af14: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 800c334: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 800c338: e853 3f00 ldrex r3, [r3] + 800c33c: f8c7 3098 str.w r3, [r7, #152] ; 0x98 return(result); - 800af18: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800af1c: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800af20: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 - 800af24: 687b ldr r3, [r7, #4] - 800af26: 681b ldr r3, [r3, #0] - 800af28: 3308 adds r3, #8 - 800af2a: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0 - 800af2e: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8 - 800af32: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 800c340: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800c344: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800c348: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 800c34c: 687b ldr r3, [r7, #4] + 800c34e: 681b ldr r3, [r3, #0] + 800c350: 3308 adds r3, #8 + 800c352: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0 + 800c356: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8 + 800c35a: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800af36: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4 - 800af3a: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 - 800af3e: e841 2300 strex r3, r2, [r1] - 800af42: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 800c35e: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4 + 800c362: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 + 800c366: e841 2300 strex r3, r2, [r1] + 800c36a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 return(result); - 800af46: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 - 800af4a: 2b00 cmp r3, #0 - 800af4c: d1d9 bne.n 800af02 + 800c36e: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 800c372: 2b00 cmp r3, #0 + 800c374: d1d9 bne.n 800c32a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) - 800af4e: 687b ldr r3, [r7, #4] - 800af50: 6f5b ldr r3, [r3, #116] ; 0x74 - 800af52: 2b00 cmp r3, #0 - 800af54: d013 beq.n 800af7e + 800c376: 687b ldr r3, [r7, #4] + 800c378: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c37a: 2b00 cmp r3, #0 + 800c37c: d013 beq.n 800c3a6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - 800af56: 687b ldr r3, [r7, #4] - 800af58: 6f5b ldr r3, [r3, #116] ; 0x74 - 800af5a: 4a13 ldr r2, [pc, #76] ; (800afa8 ) - 800af5c: 639a str r2, [r3, #56] ; 0x38 + 800c37e: 687b ldr r3, [r7, #4] + 800c380: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c382: 4a13 ldr r2, [pc, #76] ; (800c3d0 ) + 800c384: 639a str r2, [r3, #56] ; 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - 800af5e: 687b ldr r3, [r7, #4] - 800af60: 6f5b ldr r3, [r3, #116] ; 0x74 - 800af62: 4618 mov r0, r3 - 800af64: f7fb f926 bl 80061b4 - 800af68: 4603 mov r3, r0 - 800af6a: 2b00 cmp r3, #0 - 800af6c: d017 beq.n 800af9e + 800c386: 687b ldr r3, [r7, #4] + 800c388: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c38a: 4618 mov r0, r3 + 800c38c: f7fa fc98 bl 8006cc0 + 800c390: 4603 mov r3, r0 + 800c392: 2b00 cmp r3, #0 + 800c394: d017 beq.n 800c3c6 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); - 800af6e: 687b ldr r3, [r7, #4] - 800af70: 6f5b ldr r3, [r3, #116] ; 0x74 - 800af72: 6b9b ldr r3, [r3, #56] ; 0x38 - 800af74: 687a ldr r2, [r7, #4] - 800af76: 6f52 ldr r2, [r2, #116] ; 0x74 - 800af78: 4610 mov r0, r2 - 800af7a: 4798 blx r3 + 800c396: 687b ldr r3, [r7, #4] + 800c398: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c39a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800c39c: 687a ldr r2, [r7, #4] + 800c39e: 6f52 ldr r2, [r2, #116] ; 0x74 + 800c3a0: 4610 mov r0, r2 + 800c3a2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800af7c: e00f b.n 800af9e + 800c3a4: e00f b.n 800c3c6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 800af7e: 6878 ldr r0, [r7, #4] - 800af80: f000 f9c2 bl 800b308 + 800c3a6: 6878 ldr r0, [r7, #4] + 800c3a8: f000 f9c2 bl 800c730 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800af84: e00b b.n 800af9e + 800c3ac: e00b b.n 800c3c6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 800af86: 6878 ldr r0, [r7, #4] - 800af88: f000 f9be bl 800b308 + 800c3ae: 6878 ldr r0, [r7, #4] + 800c3b0: f000 f9be bl 800c730 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800af8c: e007 b.n 800af9e + 800c3b4: e007 b.n 800c3c6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 800af8e: 6878 ldr r0, [r7, #4] - 800af90: f000 f9ba bl 800b308 + 800c3b6: 6878 ldr r0, [r7, #4] + 800c3b8: f000 f9ba bl 800c730 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800af94: 687b ldr r3, [r7, #4] - 800af96: 2200 movs r2, #0 - 800af98: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800c3bc: 687b ldr r3, [r7, #4] + 800c3be: 2200 movs r2, #0 + 800c3c0: f8c3 2084 str.w r2, [r3, #132] ; 0x84 } } return; - 800af9c: e195 b.n 800b2ca + 800c3c4: e195 b.n 800c6f2 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800af9e: bf00 nop + 800c3c6: bf00 nop return; - 800afa0: e193 b.n 800b2ca - 800afa2: bf00 nop - 800afa4: 04000120 .word 0x04000120 - 800afa8: 0800bf2d .word 0x0800bf2d + 800c3c8: e193 b.n 800c6f2 + 800c3ca: bf00 nop + 800c3cc: 04000120 .word 0x04000120 + 800c3d0: 0800d355 .word 0x0800d355 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800afac: 687b ldr r3, [r7, #4] - 800afae: 6e1b ldr r3, [r3, #96] ; 0x60 - 800afb0: 2b01 cmp r3, #1 - 800afb2: f040 814e bne.w 800b252 + 800c3d4: 687b ldr r3, [r7, #4] + 800c3d6: 6e1b ldr r3, [r3, #96] ; 0x60 + 800c3d8: 2b01 cmp r3, #1 + 800c3da: f040 814e bne.w 800c67a && ((isrflags & USART_ISR_IDLE) != 0U) - 800afb6: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800afba: f003 0310 and.w r3, r3, #16 - 800afbe: 2b00 cmp r3, #0 - 800afc0: f000 8147 beq.w 800b252 + 800c3de: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c3e2: f003 0310 and.w r3, r3, #16 + 800c3e6: 2b00 cmp r3, #0 + 800c3e8: f000 8147 beq.w 800c67a && ((cr1its & USART_ISR_IDLE) != 0U)) - 800afc4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800afc8: f003 0310 and.w r3, r3, #16 - 800afcc: 2b00 cmp r3, #0 - 800afce: f000 8140 beq.w 800b252 + 800c3ec: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c3f0: f003 0310 and.w r3, r3, #16 + 800c3f4: 2b00 cmp r3, #0 + 800c3f6: f000 8140 beq.w 800c67a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 800afd2: 687b ldr r3, [r7, #4] - 800afd4: 681b ldr r3, [r3, #0] - 800afd6: 2210 movs r2, #16 - 800afd8: 621a str r2, [r3, #32] + 800c3fa: 687b ldr r3, [r7, #4] + 800c3fc: 681b ldr r3, [r3, #0] + 800c3fe: 2210 movs r2, #16 + 800c400: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800afda: 687b ldr r3, [r7, #4] - 800afdc: 681b ldr r3, [r3, #0] - 800afde: 689b ldr r3, [r3, #8] - 800afe0: f003 0340 and.w r3, r3, #64 ; 0x40 - 800afe4: 2b40 cmp r3, #64 ; 0x40 - 800afe6: f040 80b8 bne.w 800b15a + 800c402: 687b ldr r3, [r7, #4] + 800c404: 681b ldr r3, [r3, #0] + 800c406: 689b ldr r3, [r3, #8] + 800c408: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c40c: 2b40 cmp r3, #64 ; 0x40 + 800c40e: f040 80b8 bne.w 800c582 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - 800afea: 687b ldr r3, [r7, #4] - 800afec: 6f5b ldr r3, [r3, #116] ; 0x74 - 800afee: 681b ldr r3, [r3, #0] - 800aff0: 685b ldr r3, [r3, #4] - 800aff2: f8a7 30be strh.w r3, [r7, #190] ; 0xbe + 800c412: 687b ldr r3, [r7, #4] + 800c414: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c416: 681b ldr r3, [r3, #0] + 800c418: 685b ldr r3, [r3, #4] + 800c41a: f8a7 30be strh.w r3, [r7, #190] ; 0xbe if ((nb_remaining_rx_data > 0U) - 800aff6: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe - 800affa: 2b00 cmp r3, #0 - 800affc: f000 8167 beq.w 800b2ce + 800c41e: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe + 800c422: 2b00 cmp r3, #0 + 800c424: f000 8167 beq.w 800c6f6 && (nb_remaining_rx_data < huart->RxXferSize)) - 800b000: 687b ldr r3, [r7, #4] - 800b002: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 - 800b006: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe - 800b00a: 429a cmp r2, r3 - 800b00c: f080 815f bcs.w 800b2ce + 800c428: 687b ldr r3, [r7, #4] + 800c42a: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 + 800c42e: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe + 800c432: 429a cmp r2, r3 + 800c434: f080 815f bcs.w 800c6f6 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; - 800b010: 687b ldr r3, [r7, #4] - 800b012: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe - 800b016: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 800c438: 687b ldr r3, [r7, #4] + 800c43a: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe + 800c43e: f8a3 205a strh.w r2, [r3, #90] ; 0x5a /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) - 800b01a: 687b ldr r3, [r7, #4] - 800b01c: 6f5b ldr r3, [r3, #116] ; 0x74 - 800b01e: 681b ldr r3, [r3, #0] - 800b020: 681b ldr r3, [r3, #0] - 800b022: f003 0320 and.w r3, r3, #32 - 800b026: 2b00 cmp r3, #0 - 800b028: f040 8086 bne.w 800b138 + 800c442: 687b ldr r3, [r7, #4] + 800c444: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c446: 681b ldr r3, [r3, #0] + 800c448: 681b ldr r3, [r3, #0] + 800c44a: f003 0320 and.w r3, r3, #32 + 800c44e: 2b00 cmp r3, #0 + 800c450: f040 8086 bne.w 800c560 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 800b02c: 687b ldr r3, [r7, #4] - 800b02e: 681b ldr r3, [r3, #0] - 800b030: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + 800c454: 687b ldr r3, [r7, #4] + 800c456: 681b ldr r3, [r3, #0] + 800c458: f8c7 3088 str.w r3, [r7, #136] ; 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b034: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 - 800b038: e853 3f00 ldrex r3, [r3] - 800b03c: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 800c45c: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 + 800c460: e853 3f00 ldrex r3, [r3] + 800c464: f8c7 3084 str.w r3, [r7, #132] ; 0x84 return(result); - 800b040: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 800b044: f423 7380 bic.w r3, r3, #256 ; 0x100 - 800b048: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 - 800b04c: 687b ldr r3, [r7, #4] - 800b04e: 681b ldr r3, [r3, #0] - 800b050: 461a mov r2, r3 - 800b052: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800b056: f8c7 3094 str.w r3, [r7, #148] ; 0x94 - 800b05a: f8c7 2090 str.w r2, [r7, #144] ; 0x90 + 800c468: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 800c46c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 800c470: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 800c474: 687b ldr r3, [r7, #4] + 800c476: 681b ldr r3, [r3, #0] + 800c478: 461a mov r2, r3 + 800c47a: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800c47e: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 800c482: f8c7 2090 str.w r2, [r7, #144] ; 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b05e: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90 - 800b062: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94 - 800b066: e841 2300 strex r3, r2, [r1] - 800b06a: f8c7 308c str.w r3, [r7, #140] ; 0x8c + 800c486: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90 + 800c48a: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94 + 800c48e: e841 2300 strex r3, r2, [r1] + 800c492: f8c7 308c str.w r3, [r7, #140] ; 0x8c return(result); - 800b06e: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800b072: 2b00 cmp r3, #0 - 800b074: d1da bne.n 800b02c + 800c496: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800c49a: 2b00 cmp r3, #0 + 800c49c: d1da bne.n 800c454 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800b076: 687b ldr r3, [r7, #4] - 800b078: 681b ldr r3, [r3, #0] - 800b07a: 3308 adds r3, #8 - 800b07c: 677b str r3, [r7, #116] ; 0x74 + 800c49e: 687b ldr r3, [r7, #4] + 800c4a0: 681b ldr r3, [r3, #0] + 800c4a2: 3308 adds r3, #8 + 800c4a4: 677b str r3, [r7, #116] ; 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b07e: 6f7b ldr r3, [r7, #116] ; 0x74 - 800b080: e853 3f00 ldrex r3, [r3] - 800b084: 673b str r3, [r7, #112] ; 0x70 + 800c4a6: 6f7b ldr r3, [r7, #116] ; 0x74 + 800c4a8: e853 3f00 ldrex r3, [r3] + 800c4ac: 673b str r3, [r7, #112] ; 0x70 return(result); - 800b086: 6f3b ldr r3, [r7, #112] ; 0x70 - 800b088: f023 0301 bic.w r3, r3, #1 - 800b08c: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - 800b090: 687b ldr r3, [r7, #4] - 800b092: 681b ldr r3, [r3, #0] - 800b094: 3308 adds r3, #8 - 800b096: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4 - 800b09a: f8c7 2080 str.w r2, [r7, #128] ; 0x80 - 800b09e: 67fb str r3, [r7, #124] ; 0x7c + 800c4ae: 6f3b ldr r3, [r7, #112] ; 0x70 + 800c4b0: f023 0301 bic.w r3, r3, #1 + 800c4b4: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 800c4b8: 687b ldr r3, [r7, #4] + 800c4ba: 681b ldr r3, [r3, #0] + 800c4bc: 3308 adds r3, #8 + 800c4be: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4 + 800c4c2: f8c7 2080 str.w r2, [r7, #128] ; 0x80 + 800c4c6: 67fb str r3, [r7, #124] ; 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b0a0: 6ff9 ldr r1, [r7, #124] ; 0x7c - 800b0a2: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 - 800b0a6: e841 2300 strex r3, r2, [r1] - 800b0aa: 67bb str r3, [r7, #120] ; 0x78 + 800c4c8: 6ff9 ldr r1, [r7, #124] ; 0x7c + 800c4ca: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 + 800c4ce: e841 2300 strex r3, r2, [r1] + 800c4d2: 67bb str r3, [r7, #120] ; 0x78 return(result); - 800b0ac: 6fbb ldr r3, [r7, #120] ; 0x78 - 800b0ae: 2b00 cmp r3, #0 - 800b0b0: d1e1 bne.n 800b076 + 800c4d4: 6fbb ldr r3, [r7, #120] ; 0x78 + 800c4d6: 2b00 cmp r3, #0 + 800c4d8: d1e1 bne.n 800c49e /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 800b0b2: 687b ldr r3, [r7, #4] - 800b0b4: 681b ldr r3, [r3, #0] - 800b0b6: 3308 adds r3, #8 - 800b0b8: 663b str r3, [r7, #96] ; 0x60 + 800c4da: 687b ldr r3, [r7, #4] + 800c4dc: 681b ldr r3, [r3, #0] + 800c4de: 3308 adds r3, #8 + 800c4e0: 663b str r3, [r7, #96] ; 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b0ba: 6e3b ldr r3, [r7, #96] ; 0x60 - 800b0bc: e853 3f00 ldrex r3, [r3] - 800b0c0: 65fb str r3, [r7, #92] ; 0x5c + 800c4e2: 6e3b ldr r3, [r7, #96] ; 0x60 + 800c4e4: e853 3f00 ldrex r3, [r3] + 800c4e8: 65fb str r3, [r7, #92] ; 0x5c return(result); - 800b0c2: 6dfb ldr r3, [r7, #92] ; 0x5c - 800b0c4: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800b0c8: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 - 800b0cc: 687b ldr r3, [r7, #4] - 800b0ce: 681b ldr r3, [r3, #0] - 800b0d0: 3308 adds r3, #8 - 800b0d2: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0 - 800b0d6: 66fa str r2, [r7, #108] ; 0x6c - 800b0d8: 66bb str r3, [r7, #104] ; 0x68 + 800c4ea: 6dfb ldr r3, [r7, #92] ; 0x5c + 800c4ec: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800c4f0: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + 800c4f4: 687b ldr r3, [r7, #4] + 800c4f6: 681b ldr r3, [r3, #0] + 800c4f8: 3308 adds r3, #8 + 800c4fa: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0 + 800c4fe: 66fa str r2, [r7, #108] ; 0x6c + 800c500: 66bb str r3, [r7, #104] ; 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b0da: 6eb9 ldr r1, [r7, #104] ; 0x68 - 800b0dc: 6efa ldr r2, [r7, #108] ; 0x6c - 800b0de: e841 2300 strex r3, r2, [r1] - 800b0e2: 667b str r3, [r7, #100] ; 0x64 + 800c502: 6eb9 ldr r1, [r7, #104] ; 0x68 + 800c504: 6efa ldr r2, [r7, #108] ; 0x6c + 800c506: e841 2300 strex r3, r2, [r1] + 800c50a: 667b str r3, [r7, #100] ; 0x64 return(result); - 800b0e4: 6e7b ldr r3, [r7, #100] ; 0x64 - 800b0e6: 2b00 cmp r3, #0 - 800b0e8: d1e3 bne.n 800b0b2 + 800c50c: 6e7b ldr r3, [r7, #100] ; 0x64 + 800c50e: 2b00 cmp r3, #0 + 800c510: d1e3 bne.n 800c4da /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800b0ea: 687b ldr r3, [r7, #4] - 800b0ec: 2220 movs r2, #32 - 800b0ee: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800c512: 687b ldr r3, [r7, #4] + 800c514: 2220 movs r2, #32 + 800c516: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800b0f2: 687b ldr r3, [r7, #4] - 800b0f4: 2200 movs r2, #0 - 800b0f6: 661a str r2, [r3, #96] ; 0x60 + 800c51a: 687b ldr r3, [r7, #4] + 800c51c: 2200 movs r2, #0 + 800c51e: 661a str r2, [r3, #96] ; 0x60 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 800b0f8: 687b ldr r3, [r7, #4] - 800b0fa: 681b ldr r3, [r3, #0] - 800b0fc: 64fb str r3, [r7, #76] ; 0x4c + 800c520: 687b ldr r3, [r7, #4] + 800c522: 681b ldr r3, [r3, #0] + 800c524: 64fb str r3, [r7, #76] ; 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b0fe: 6cfb ldr r3, [r7, #76] ; 0x4c - 800b100: e853 3f00 ldrex r3, [r3] - 800b104: 64bb str r3, [r7, #72] ; 0x48 + 800c526: 6cfb ldr r3, [r7, #76] ; 0x4c + 800c528: e853 3f00 ldrex r3, [r3] + 800c52c: 64bb str r3, [r7, #72] ; 0x48 return(result); - 800b106: 6cbb ldr r3, [r7, #72] ; 0x48 - 800b108: f023 0310 bic.w r3, r3, #16 - 800b10c: f8c7 30ac str.w r3, [r7, #172] ; 0xac - 800b110: 687b ldr r3, [r7, #4] - 800b112: 681b ldr r3, [r3, #0] - 800b114: 461a mov r2, r3 - 800b116: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800b11a: 65bb str r3, [r7, #88] ; 0x58 - 800b11c: 657a str r2, [r7, #84] ; 0x54 + 800c52e: 6cbb ldr r3, [r7, #72] ; 0x48 + 800c530: f023 0310 bic.w r3, r3, #16 + 800c534: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 800c538: 687b ldr r3, [r7, #4] + 800c53a: 681b ldr r3, [r3, #0] + 800c53c: 461a mov r2, r3 + 800c53e: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800c542: 65bb str r3, [r7, #88] ; 0x58 + 800c544: 657a str r2, [r7, #84] ; 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b11e: 6d79 ldr r1, [r7, #84] ; 0x54 - 800b120: 6dba ldr r2, [r7, #88] ; 0x58 - 800b122: e841 2300 strex r3, r2, [r1] - 800b126: 653b str r3, [r7, #80] ; 0x50 + 800c546: 6d79 ldr r1, [r7, #84] ; 0x54 + 800c548: 6dba ldr r2, [r7, #88] ; 0x58 + 800c54a: e841 2300 strex r3, r2, [r1] + 800c54e: 653b str r3, [r7, #80] ; 0x50 return(result); - 800b128: 6d3b ldr r3, [r7, #80] ; 0x50 - 800b12a: 2b00 cmp r3, #0 - 800b12c: d1e4 bne.n 800b0f8 + 800c550: 6d3b ldr r3, [r7, #80] ; 0x50 + 800c552: 2b00 cmp r3, #0 + 800c554: d1e4 bne.n 800c520 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); - 800b12e: 687b ldr r3, [r7, #4] - 800b130: 6f5b ldr r3, [r3, #116] ; 0x74 - 800b132: 4618 mov r0, r3 - 800b134: f7fb f800 bl 8006138 + 800c556: 687b ldr r3, [r7, #4] + 800c558: 6f5b ldr r3, [r3, #116] ; 0x74 + 800c55a: 4618 mov r0, r3 + 800c55c: f7fa fb72 bl 8006c44 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; - 800b138: 687b ldr r3, [r7, #4] - 800b13a: 2202 movs r2, #2 - 800b13c: 665a str r2, [r3, #100] ; 0x64 + 800c560: 687b ldr r3, [r7, #4] + 800c562: 2202 movs r2, #2 + 800c564: 665a str r2, [r3, #100] ; 0x64 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); - 800b13e: 687b ldr r3, [r7, #4] - 800b140: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58 - 800b144: 687b ldr r3, [r7, #4] - 800b146: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a - 800b14a: b29b uxth r3, r3 - 800b14c: 1ad3 subs r3, r2, r3 - 800b14e: b29b uxth r3, r3 - 800b150: 4619 mov r1, r3 - 800b152: 6878 ldr r0, [r7, #4] - 800b154: f000 f8e2 bl 800b31c + 800c566: 687b ldr r3, [r7, #4] + 800c568: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58 + 800c56c: 687b ldr r3, [r7, #4] + 800c56e: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800c572: b29b uxth r3, r3 + 800c574: 1ad3 subs r3, r2, r3 + 800c576: b29b uxth r3, r3 + 800c578: 4619 mov r1, r3 + 800c57a: 6878 ldr r0, [r7, #4] + 800c57c: f000 f8e2 bl 800c744 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; - 800b158: e0b9 b.n 800b2ce + 800c580: e0b9 b.n 800c6f6 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - 800b15a: 687b ldr r3, [r7, #4] - 800b15c: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58 - 800b160: 687b ldr r3, [r7, #4] - 800b162: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a - 800b166: b29b uxth r3, r3 - 800b168: 1ad3 subs r3, r2, r3 - 800b16a: f8a7 30ce strh.w r3, [r7, #206] ; 0xce + 800c582: 687b ldr r3, [r7, #4] + 800c584: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58 + 800c588: 687b ldr r3, [r7, #4] + 800c58a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800c58e: b29b uxth r3, r3 + 800c590: 1ad3 subs r3, r2, r3 + 800c592: f8a7 30ce strh.w r3, [r7, #206] ; 0xce if ((huart->RxXferCount > 0U) - 800b16e: 687b ldr r3, [r7, #4] - 800b170: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a - 800b174: b29b uxth r3, r3 - 800b176: 2b00 cmp r3, #0 - 800b178: f000 80ab beq.w 800b2d2 + 800c596: 687b ldr r3, [r7, #4] + 800c598: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 800c59c: b29b uxth r3, r3 + 800c59e: 2b00 cmp r3, #0 + 800c5a0: f000 80ab beq.w 800c6fa && (nb_rx_data > 0U)) - 800b17c: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce - 800b180: 2b00 cmp r3, #0 - 800b182: f000 80a6 beq.w 800b2d2 + 800c5a4: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce + 800c5a8: 2b00 cmp r3, #0 + 800c5aa: f000 80a6 beq.w 800c6fa /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 800b186: 687b ldr r3, [r7, #4] - 800b188: 681b ldr r3, [r3, #0] - 800b18a: 63bb str r3, [r7, #56] ; 0x38 + 800c5ae: 687b ldr r3, [r7, #4] + 800c5b0: 681b ldr r3, [r3, #0] + 800c5b2: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b18c: 6bbb ldr r3, [r7, #56] ; 0x38 - 800b18e: e853 3f00 ldrex r3, [r3] - 800b192: 637b str r3, [r7, #52] ; 0x34 + 800c5b4: 6bbb ldr r3, [r7, #56] ; 0x38 + 800c5b6: e853 3f00 ldrex r3, [r3] + 800c5ba: 637b str r3, [r7, #52] ; 0x34 return(result); - 800b194: 6b7b ldr r3, [r7, #52] ; 0x34 - 800b196: f423 7390 bic.w r3, r3, #288 ; 0x120 - 800b19a: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 - 800b19e: 687b ldr r3, [r7, #4] - 800b1a0: 681b ldr r3, [r3, #0] - 800b1a2: 461a mov r2, r3 - 800b1a4: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800b1a8: 647b str r3, [r7, #68] ; 0x44 - 800b1aa: 643a str r2, [r7, #64] ; 0x40 + 800c5bc: 6b7b ldr r3, [r7, #52] ; 0x34 + 800c5be: f423 7390 bic.w r3, r3, #288 ; 0x120 + 800c5c2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 800c5c6: 687b ldr r3, [r7, #4] + 800c5c8: 681b ldr r3, [r3, #0] + 800c5ca: 461a mov r2, r3 + 800c5cc: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800c5d0: 647b str r3, [r7, #68] ; 0x44 + 800c5d2: 643a str r2, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b1ac: 6c39 ldr r1, [r7, #64] ; 0x40 - 800b1ae: 6c7a ldr r2, [r7, #68] ; 0x44 - 800b1b0: e841 2300 strex r3, r2, [r1] - 800b1b4: 63fb str r3, [r7, #60] ; 0x3c + 800c5d4: 6c39 ldr r1, [r7, #64] ; 0x40 + 800c5d6: 6c7a ldr r2, [r7, #68] ; 0x44 + 800c5d8: e841 2300 strex r3, r2, [r1] + 800c5dc: 63fb str r3, [r7, #60] ; 0x3c return(result); - 800b1b6: 6bfb ldr r3, [r7, #60] ; 0x3c - 800b1b8: 2b00 cmp r3, #0 - 800b1ba: d1e4 bne.n 800b186 + 800c5de: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c5e0: 2b00 cmp r3, #0 + 800c5e2: d1e4 bne.n 800c5ae /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800b1bc: 687b ldr r3, [r7, #4] - 800b1be: 681b ldr r3, [r3, #0] - 800b1c0: 3308 adds r3, #8 - 800b1c2: 627b str r3, [r7, #36] ; 0x24 + 800c5e4: 687b ldr r3, [r7, #4] + 800c5e6: 681b ldr r3, [r3, #0] + 800c5e8: 3308 adds r3, #8 + 800c5ea: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b1c4: 6a7b ldr r3, [r7, #36] ; 0x24 - 800b1c6: e853 3f00 ldrex r3, [r3] - 800b1ca: 623b str r3, [r7, #32] + 800c5ec: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c5ee: e853 3f00 ldrex r3, [r3] + 800c5f2: 623b str r3, [r7, #32] return(result); - 800b1cc: 6a3b ldr r3, [r7, #32] - 800b1ce: f023 0301 bic.w r3, r3, #1 - 800b1d2: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 - 800b1d6: 687b ldr r3, [r7, #4] - 800b1d8: 681b ldr r3, [r3, #0] - 800b1da: 3308 adds r3, #8 - 800b1dc: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4 - 800b1e0: 633a str r2, [r7, #48] ; 0x30 - 800b1e2: 62fb str r3, [r7, #44] ; 0x2c + 800c5f4: 6a3b ldr r3, [r7, #32] + 800c5f6: f023 0301 bic.w r3, r3, #1 + 800c5fa: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 800c5fe: 687b ldr r3, [r7, #4] + 800c600: 681b ldr r3, [r3, #0] + 800c602: 3308 adds r3, #8 + 800c604: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4 + 800c608: 633a str r2, [r7, #48] ; 0x30 + 800c60a: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b1e4: 6af9 ldr r1, [r7, #44] ; 0x2c - 800b1e6: 6b3a ldr r2, [r7, #48] ; 0x30 - 800b1e8: e841 2300 strex r3, r2, [r1] - 800b1ec: 62bb str r3, [r7, #40] ; 0x28 + 800c60c: 6af9 ldr r1, [r7, #44] ; 0x2c + 800c60e: 6b3a ldr r2, [r7, #48] ; 0x30 + 800c610: e841 2300 strex r3, r2, [r1] + 800c614: 62bb str r3, [r7, #40] ; 0x28 return(result); - 800b1ee: 6abb ldr r3, [r7, #40] ; 0x28 - 800b1f0: 2b00 cmp r3, #0 - 800b1f2: d1e3 bne.n 800b1bc + 800c616: 6abb ldr r3, [r7, #40] ; 0x28 + 800c618: 2b00 cmp r3, #0 + 800c61a: d1e3 bne.n 800c5e4 #endif /* USART_CR1_FIFOEN */ /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800b1f4: 687b ldr r3, [r7, #4] - 800b1f6: 2220 movs r2, #32 - 800b1f8: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800c61c: 687b ldr r3, [r7, #4] + 800c61e: 2220 movs r2, #32 + 800c620: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800b1fc: 687b ldr r3, [r7, #4] - 800b1fe: 2200 movs r2, #0 - 800b200: 661a str r2, [r3, #96] ; 0x60 + 800c624: 687b ldr r3, [r7, #4] + 800c626: 2200 movs r2, #0 + 800c628: 661a str r2, [r3, #96] ; 0x60 /* Clear RxISR function pointer */ huart->RxISR = NULL; - 800b202: 687b ldr r3, [r7, #4] - 800b204: 2200 movs r2, #0 - 800b206: 669a str r2, [r3, #104] ; 0x68 + 800c62a: 687b ldr r3, [r7, #4] + 800c62c: 2200 movs r2, #0 + 800c62e: 669a str r2, [r3, #104] ; 0x68 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 800b208: 687b ldr r3, [r7, #4] - 800b20a: 681b ldr r3, [r3, #0] - 800b20c: 613b str r3, [r7, #16] + 800c630: 687b ldr r3, [r7, #4] + 800c632: 681b ldr r3, [r3, #0] + 800c634: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b20e: 693b ldr r3, [r7, #16] - 800b210: e853 3f00 ldrex r3, [r3] - 800b214: 60fb str r3, [r7, #12] + 800c636: 693b ldr r3, [r7, #16] + 800c638: e853 3f00 ldrex r3, [r3] + 800c63c: 60fb str r3, [r7, #12] return(result); - 800b216: 68fb ldr r3, [r7, #12] - 800b218: f023 0310 bic.w r3, r3, #16 - 800b21c: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 - 800b220: 687b ldr r3, [r7, #4] - 800b222: 681b ldr r3, [r3, #0] - 800b224: 461a mov r2, r3 - 800b226: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 800b22a: 61fb str r3, [r7, #28] - 800b22c: 61ba str r2, [r7, #24] + 800c63e: 68fb ldr r3, [r7, #12] + 800c640: f023 0310 bic.w r3, r3, #16 + 800c644: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 800c648: 687b ldr r3, [r7, #4] + 800c64a: 681b ldr r3, [r3, #0] + 800c64c: 461a mov r2, r3 + 800c64e: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 800c652: 61fb str r3, [r7, #28] + 800c654: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b22e: 69b9 ldr r1, [r7, #24] - 800b230: 69fa ldr r2, [r7, #28] - 800b232: e841 2300 strex r3, r2, [r1] - 800b236: 617b str r3, [r7, #20] + 800c656: 69b9 ldr r1, [r7, #24] + 800c658: 69fa ldr r2, [r7, #28] + 800c65a: e841 2300 strex r3, r2, [r1] + 800c65e: 617b str r3, [r7, #20] return(result); - 800b238: 697b ldr r3, [r7, #20] - 800b23a: 2b00 cmp r3, #0 - 800b23c: d1e4 bne.n 800b208 + 800c660: 697b ldr r3, [r7, #20] + 800c662: 2b00 cmp r3, #0 + 800c664: d1e4 bne.n 800c630 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; - 800b23e: 687b ldr r3, [r7, #4] - 800b240: 2202 movs r2, #2 - 800b242: 665a str r2, [r3, #100] ; 0x64 + 800c666: 687b ldr r3, [r7, #4] + 800c668: 2202 movs r2, #2 + 800c66a: 665a str r2, [r3, #100] ; 0x64 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); - 800b244: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce - 800b248: 4619 mov r1, r3 - 800b24a: 6878 ldr r0, [r7, #4] - 800b24c: f000 f866 bl 800b31c + 800c66c: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce + 800c670: 4619 mov r1, r3 + 800c672: 6878 ldr r0, [r7, #4] + 800c674: f000 f866 bl 800c744 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; - 800b250: e03f b.n 800b2d2 + 800c678: e03f b.n 800c6fa } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) - 800b252: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800b256: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 800b25a: 2b00 cmp r3, #0 - 800b25c: d00e beq.n 800b27c - 800b25e: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800b262: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 800b266: 2b00 cmp r3, #0 - 800b268: d008 beq.n 800b27c + 800c67a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c67e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800c682: 2b00 cmp r3, #0 + 800c684: d00e beq.n 800c6a4 + 800c686: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800c68a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800c68e: 2b00 cmp r3, #0 + 800c690: d008 beq.n 800c6a4 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - 800b26a: 687b ldr r3, [r7, #4] - 800b26c: 681b ldr r3, [r3, #0] - 800b26e: f44f 1280 mov.w r2, #1048576 ; 0x100000 - 800b272: 621a str r2, [r3, #32] + 800c692: 687b ldr r3, [r7, #4] + 800c694: 681b ldr r3, [r3, #0] + 800c696: f44f 1280 mov.w r2, #1048576 ; 0x100000 + 800c69a: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); - 800b274: 6878 ldr r0, [r7, #4] - 800b276: f000 ff55 bl 800c124 + 800c69c: 6878 ldr r0, [r7, #4] + 800c69e: f000 fe99 bl 800d3d4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; - 800b27a: e02d b.n 800b2d8 + 800c6a2: e02d b.n 800c700 #if defined(USART_CR1_FIFOEN) if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) || ((cr3its & USART_CR3_TXFTIE) != 0U))) #else if (((isrflags & USART_ISR_TXE) != 0U) - 800b27c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800b280: f003 0380 and.w r3, r3, #128 ; 0x80 - 800b284: 2b00 cmp r3, #0 - 800b286: d00e beq.n 800b2a6 + 800c6a4: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c6a8: f003 0380 and.w r3, r3, #128 ; 0x80 + 800c6ac: 2b00 cmp r3, #0 + 800c6ae: d00e beq.n 800c6ce && ((cr1its & USART_CR1_TXEIE) != 0U)) - 800b288: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800b28c: f003 0380 and.w r3, r3, #128 ; 0x80 - 800b290: 2b00 cmp r3, #0 - 800b292: d008 beq.n 800b2a6 + 800c6b0: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c6b4: f003 0380 and.w r3, r3, #128 ; 0x80 + 800c6b8: 2b00 cmp r3, #0 + 800c6ba: d008 beq.n 800c6ce #endif /* USART_CR1_FIFOEN */ { if (huart->TxISR != NULL) - 800b294: 687b ldr r3, [r7, #4] - 800b296: 6edb ldr r3, [r3, #108] ; 0x6c - 800b298: 2b00 cmp r3, #0 - 800b29a: d01c beq.n 800b2d6 + 800c6bc: 687b ldr r3, [r7, #4] + 800c6be: 6edb ldr r3, [r3, #108] ; 0x6c + 800c6c0: 2b00 cmp r3, #0 + 800c6c2: d01c beq.n 800c6fe { huart->TxISR(huart); - 800b29c: 687b ldr r3, [r7, #4] - 800b29e: 6edb ldr r3, [r3, #108] ; 0x6c - 800b2a0: 6878 ldr r0, [r7, #4] - 800b2a2: 4798 blx r3 + 800c6c4: 687b ldr r3, [r7, #4] + 800c6c6: 6edb ldr r3, [r3, #108] ; 0x6c + 800c6c8: 6878 ldr r0, [r7, #4] + 800c6ca: 4798 blx r3 } return; - 800b2a4: e017 b.n 800b2d6 + 800c6cc: e017 b.n 800c6fe } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - 800b2a6: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800b2aa: f003 0340 and.w r3, r3, #64 ; 0x40 - 800b2ae: 2b00 cmp r3, #0 - 800b2b0: d012 beq.n 800b2d8 - 800b2b2: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800b2b6: f003 0340 and.w r3, r3, #64 ; 0x40 - 800b2ba: 2b00 cmp r3, #0 - 800b2bc: d00c beq.n 800b2d8 + 800c6ce: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800c6d2: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c6d6: 2b00 cmp r3, #0 + 800c6d8: d012 beq.n 800c700 + 800c6da: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800c6de: f003 0340 and.w r3, r3, #64 ; 0x40 + 800c6e2: 2b00 cmp r3, #0 + 800c6e4: d00c beq.n 800c700 { UART_EndTransmit_IT(huart); - 800b2be: 6878 ldr r0, [r7, #4] - 800b2c0: f000 ff06 bl 800c0d0 + 800c6e6: 6878 ldr r0, [r7, #4] + 800c6e8: f000 fe4a bl 800d380 return; - 800b2c4: e008 b.n 800b2d8 + 800c6ec: e008 b.n 800c700 return; - 800b2c6: bf00 nop - 800b2c8: e006 b.n 800b2d8 + 800c6ee: bf00 nop + 800c6f0: e006 b.n 800c700 return; - 800b2ca: bf00 nop - 800b2cc: e004 b.n 800b2d8 + 800c6f2: bf00 nop + 800c6f4: e004 b.n 800c700 return; - 800b2ce: bf00 nop - 800b2d0: e002 b.n 800b2d8 + 800c6f6: bf00 nop + 800c6f8: e002 b.n 800c700 return; - 800b2d2: bf00 nop - 800b2d4: e000 b.n 800b2d8 + 800c6fa: bf00 nop + 800c6fc: e000 b.n 800c700 return; - 800b2d6: bf00 nop + 800c6fe: bf00 nop HAL_UARTEx_RxFifoFullCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } #endif /* USART_CR1_FIFOEN */ } - 800b2d8: 37e8 adds r7, #232 ; 0xe8 - 800b2da: 46bd mov sp, r7 - 800b2dc: bd80 pop {r7, pc} - 800b2de: bf00 nop + 800c700: 37e8 adds r7, #232 ; 0xe8 + 800c702: 46bd mov sp, r7 + 800c704: bd80 pop {r7, pc} + 800c706: bf00 nop -0800b2e0 : +0800c708 : * @brief Tx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { - 800b2e0: b480 push {r7} - 800b2e2: b083 sub sp, #12 - 800b2e4: af00 add r7, sp, #0 - 800b2e6: 6078 str r0, [r7, #4] + 800c708: b480 push {r7} + 800c70a: b083 sub sp, #12 + 800c70c: af00 add r7, sp, #0 + 800c70e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file. */ } - 800b2e8: bf00 nop - 800b2ea: 370c adds r7, #12 - 800b2ec: 46bd mov sp, r7 - 800b2ee: f85d 7b04 ldr.w r7, [sp], #4 - 800b2f2: 4770 bx lr + 800c710: bf00 nop + 800c712: 370c adds r7, #12 + 800c714: 46bd mov sp, r7 + 800c716: f85d 7b04 ldr.w r7, [sp], #4 + 800c71a: 4770 bx lr -0800b2f4 : +0800c71c : * @brief Rx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { - 800b2f4: b480 push {r7} - 800b2f6: b083 sub sp, #12 - 800b2f8: af00 add r7, sp, #0 - 800b2fa: 6078 str r0, [r7, #4] + 800c71c: b480 push {r7} + 800c71e: b083 sub sp, #12 + 800c720: af00 add r7, sp, #0 + 800c722: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } - 800b2fc: bf00 nop - 800b2fe: 370c adds r7, #12 - 800b300: 46bd mov sp, r7 - 800b302: f85d 7b04 ldr.w r7, [sp], #4 - 800b306: 4770 bx lr + 800c724: bf00 nop + 800c726: 370c adds r7, #12 + 800c728: 46bd mov sp, r7 + 800c72a: f85d 7b04 ldr.w r7, [sp], #4 + 800c72e: 4770 bx lr -0800b308 : +0800c730 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { - 800b308: b480 push {r7} - 800b30a: b083 sub sp, #12 - 800b30c: af00 add r7, sp, #0 - 800b30e: 6078 str r0, [r7, #4] + 800c730: b480 push {r7} + 800c732: b083 sub sp, #12 + 800c734: af00 add r7, sp, #0 + 800c736: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } - 800b310: bf00 nop - 800b312: 370c adds r7, #12 - 800b314: 46bd mov sp, r7 - 800b316: f85d 7b04 ldr.w r7, [sp], #4 - 800b31a: 4770 bx lr + 800c738: bf00 nop + 800c73a: 370c adds r7, #12 + 800c73c: 46bd mov sp, r7 + 800c73e: f85d 7b04 ldr.w r7, [sp], #4 + 800c742: 4770 bx lr -0800b31c : +0800c744 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { - 800b31c: b480 push {r7} - 800b31e: b083 sub sp, #12 - 800b320: af00 add r7, sp, #0 - 800b322: 6078 str r0, [r7, #4] - 800b324: 460b mov r3, r1 - 800b326: 807b strh r3, [r7, #2] + 800c744: b480 push {r7} + 800c746: b083 sub sp, #12 + 800c748: af00 add r7, sp, #0 + 800c74a: 6078 str r0, [r7, #4] + 800c74c: 460b mov r3, r1 + 800c74e: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } - 800b328: bf00 nop - 800b32a: 370c adds r7, #12 - 800b32c: 46bd mov sp, r7 - 800b32e: f85d 7b04 ldr.w r7, [sp], #4 - 800b332: 4770 bx lr + 800c750: bf00 nop + 800c752: 370c adds r7, #12 + 800c754: 46bd mov sp, r7 + 800c756: f85d 7b04 ldr.w r7, [sp], #4 + 800c75a: 4770 bx lr -0800b334 : +0800c75c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 800b334: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 800b338: b08a sub sp, #40 ; 0x28 - 800b33a: af00 add r7, sp, #0 - 800b33c: 60f8 str r0, [r7, #12] + 800c75c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 800c760: b08a sub sp, #40 ; 0x28 + 800c762: af00 add r7, sp, #0 + 800c764: 60f8 str r0, [r7, #12] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 800b33e: 2300 movs r3, #0 - 800b340: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800c766: 2300 movs r3, #0 + 800c768: f887 3022 strb.w r3, [r7, #34] ; 0x22 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 800b344: 68fb ldr r3, [r7, #12] - 800b346: 689a ldr r2, [r3, #8] - 800b348: 68fb ldr r3, [r7, #12] - 800b34a: 691b ldr r3, [r3, #16] - 800b34c: 431a orrs r2, r3 - 800b34e: 68fb ldr r3, [r7, #12] - 800b350: 695b ldr r3, [r3, #20] - 800b352: 431a orrs r2, r3 - 800b354: 68fb ldr r3, [r7, #12] - 800b356: 69db ldr r3, [r3, #28] - 800b358: 4313 orrs r3, r2 - 800b35a: 627b str r3, [r7, #36] ; 0x24 + 800c76c: 68fb ldr r3, [r7, #12] + 800c76e: 689a ldr r2, [r3, #8] + 800c770: 68fb ldr r3, [r7, #12] + 800c772: 691b ldr r3, [r3, #16] + 800c774: 431a orrs r2, r3 + 800c776: 68fb ldr r3, [r7, #12] + 800c778: 695b ldr r3, [r3, #20] + 800c77a: 431a orrs r2, r3 + 800c77c: 68fb ldr r3, [r7, #12] + 800c77e: 69db ldr r3, [r3, #28] + 800c780: 4313 orrs r3, r2 + 800c782: 627b str r3, [r7, #36] ; 0x24 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 800b35c: 68fb ldr r3, [r7, #12] - 800b35e: 681b ldr r3, [r3, #0] - 800b360: 681a ldr r2, [r3, #0] - 800b362: 4bb4 ldr r3, [pc, #720] ; (800b634 ) - 800b364: 4013 ands r3, r2 - 800b366: 68fa ldr r2, [r7, #12] - 800b368: 6812 ldr r2, [r2, #0] - 800b36a: 6a79 ldr r1, [r7, #36] ; 0x24 - 800b36c: 430b orrs r3, r1 - 800b36e: 6013 str r3, [r2, #0] + 800c784: 68fb ldr r3, [r7, #12] + 800c786: 681b ldr r3, [r3, #0] + 800c788: 681a ldr r2, [r3, #0] + 800c78a: 4bb4 ldr r3, [pc, #720] ; (800ca5c ) + 800c78c: 4013 ands r3, r2 + 800c78e: 68fa ldr r2, [r7, #12] + 800c790: 6812 ldr r2, [r2, #0] + 800c792: 6a79 ldr r1, [r7, #36] ; 0x24 + 800c794: 430b orrs r3, r1 + 800c796: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 800b370: 68fb ldr r3, [r7, #12] - 800b372: 681b ldr r3, [r3, #0] - 800b374: 685b ldr r3, [r3, #4] - 800b376: f423 5140 bic.w r1, r3, #12288 ; 0x3000 - 800b37a: 68fb ldr r3, [r7, #12] - 800b37c: 68da ldr r2, [r3, #12] - 800b37e: 68fb ldr r3, [r7, #12] - 800b380: 681b ldr r3, [r3, #0] - 800b382: 430a orrs r2, r1 - 800b384: 605a str r2, [r3, #4] + 800c798: 68fb ldr r3, [r7, #12] + 800c79a: 681b ldr r3, [r3, #0] + 800c79c: 685b ldr r3, [r3, #4] + 800c79e: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 800c7a2: 68fb ldr r3, [r7, #12] + 800c7a4: 68da ldr r2, [r3, #12] + 800c7a6: 68fb ldr r3, [r7, #12] + 800c7a8: 681b ldr r3, [r3, #0] + 800c7aa: 430a orrs r2, r1 + 800c7ac: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 800b386: 68fb ldr r3, [r7, #12] - 800b388: 699b ldr r3, [r3, #24] - 800b38a: 627b str r3, [r7, #36] ; 0x24 + 800c7ae: 68fb ldr r3, [r7, #12] + 800c7b0: 699b ldr r3, [r3, #24] + 800c7b2: 627b str r3, [r7, #36] ; 0x24 if (!(UART_INSTANCE_LOWPOWER(huart))) - 800b38c: 68fb ldr r3, [r7, #12] - 800b38e: 681b ldr r3, [r3, #0] - 800b390: 4aa9 ldr r2, [pc, #676] ; (800b638 ) - 800b392: 4293 cmp r3, r2 - 800b394: d004 beq.n 800b3a0 + 800c7b4: 68fb ldr r3, [r7, #12] + 800c7b6: 681b ldr r3, [r3, #0] + 800c7b8: 4aa9 ldr r2, [pc, #676] ; (800ca60 ) + 800c7ba: 4293 cmp r3, r2 + 800c7bc: d004 beq.n 800c7c8 { tmpreg |= huart->Init.OneBitSampling; - 800b396: 68fb ldr r3, [r7, #12] - 800b398: 6a1b ldr r3, [r3, #32] - 800b39a: 6a7a ldr r2, [r7, #36] ; 0x24 - 800b39c: 4313 orrs r3, r2 - 800b39e: 627b str r3, [r7, #36] ; 0x24 + 800c7be: 68fb ldr r3, [r7, #12] + 800c7c0: 6a1b ldr r3, [r3, #32] + 800c7c2: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c7c4: 4313 orrs r3, r2 + 800c7c6: 627b str r3, [r7, #36] ; 0x24 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 800b3a0: 68fb ldr r3, [r7, #12] - 800b3a2: 681b ldr r3, [r3, #0] - 800b3a4: 689b ldr r3, [r3, #8] - 800b3a6: f423 6130 bic.w r1, r3, #2816 ; 0xb00 - 800b3aa: 68fb ldr r3, [r7, #12] - 800b3ac: 681b ldr r3, [r3, #0] - 800b3ae: 6a7a ldr r2, [r7, #36] ; 0x24 - 800b3b0: 430a orrs r2, r1 - 800b3b2: 609a str r2, [r3, #8] + 800c7c8: 68fb ldr r3, [r7, #12] + 800c7ca: 681b ldr r3, [r3, #0] + 800c7cc: 689b ldr r3, [r3, #8] + 800c7ce: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 800c7d2: 68fb ldr r3, [r7, #12] + 800c7d4: 681b ldr r3, [r3, #0] + 800c7d6: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c7d8: 430a orrs r2, r1 + 800c7da: 609a str r2, [r3, #8] * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); #endif /* USART_PRESC_PRESCALER */ /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 800b3b4: 68fb ldr r3, [r7, #12] - 800b3b6: 681b ldr r3, [r3, #0] - 800b3b8: 4aa0 ldr r2, [pc, #640] ; (800b63c ) - 800b3ba: 4293 cmp r3, r2 - 800b3bc: d126 bne.n 800b40c - 800b3be: 4ba0 ldr r3, [pc, #640] ; (800b640 ) - 800b3c0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800b3c4: f003 0303 and.w r3, r3, #3 - 800b3c8: 2b03 cmp r3, #3 - 800b3ca: d81b bhi.n 800b404 - 800b3cc: a201 add r2, pc, #4 ; (adr r2, 800b3d4 ) - 800b3ce: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800b3d2: bf00 nop - 800b3d4: 0800b3e5 .word 0x0800b3e5 - 800b3d8: 0800b3f5 .word 0x0800b3f5 - 800b3dc: 0800b3ed .word 0x0800b3ed - 800b3e0: 0800b3fd .word 0x0800b3fd - 800b3e4: 2301 movs r3, #1 - 800b3e6: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b3ea: e080 b.n 800b4ee - 800b3ec: 2302 movs r3, #2 - 800b3ee: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b3f2: e07c b.n 800b4ee - 800b3f4: 2304 movs r3, #4 - 800b3f6: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b3fa: e078 b.n 800b4ee - 800b3fc: 2308 movs r3, #8 - 800b3fe: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b402: e074 b.n 800b4ee - 800b404: 2310 movs r3, #16 - 800b406: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b40a: e070 b.n 800b4ee - 800b40c: 68fb ldr r3, [r7, #12] - 800b40e: 681b ldr r3, [r3, #0] - 800b410: 4a8c ldr r2, [pc, #560] ; (800b644 ) - 800b412: 4293 cmp r3, r2 - 800b414: d138 bne.n 800b488 - 800b416: 4b8a ldr r3, [pc, #552] ; (800b640 ) - 800b418: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800b41c: f003 030c and.w r3, r3, #12 - 800b420: 2b0c cmp r3, #12 - 800b422: d82d bhi.n 800b480 - 800b424: a201 add r2, pc, #4 ; (adr r2, 800b42c ) - 800b426: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800b42a: bf00 nop - 800b42c: 0800b461 .word 0x0800b461 - 800b430: 0800b481 .word 0x0800b481 - 800b434: 0800b481 .word 0x0800b481 - 800b438: 0800b481 .word 0x0800b481 - 800b43c: 0800b471 .word 0x0800b471 - 800b440: 0800b481 .word 0x0800b481 - 800b444: 0800b481 .word 0x0800b481 - 800b448: 0800b481 .word 0x0800b481 - 800b44c: 0800b469 .word 0x0800b469 - 800b450: 0800b481 .word 0x0800b481 - 800b454: 0800b481 .word 0x0800b481 - 800b458: 0800b481 .word 0x0800b481 - 800b45c: 0800b479 .word 0x0800b479 - 800b460: 2300 movs r3, #0 - 800b462: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b466: e042 b.n 800b4ee - 800b468: 2302 movs r3, #2 - 800b46a: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b46e: e03e b.n 800b4ee - 800b470: 2304 movs r3, #4 - 800b472: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b476: e03a b.n 800b4ee - 800b478: 2308 movs r3, #8 - 800b47a: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b47e: e036 b.n 800b4ee - 800b480: 2310 movs r3, #16 - 800b482: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b486: e032 b.n 800b4ee - 800b488: 68fb ldr r3, [r7, #12] - 800b48a: 681b ldr r3, [r3, #0] - 800b48c: 4a6a ldr r2, [pc, #424] ; (800b638 ) - 800b48e: 4293 cmp r3, r2 - 800b490: d12a bne.n 800b4e8 - 800b492: 4b6b ldr r3, [pc, #428] ; (800b640 ) - 800b494: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800b498: f403 6340 and.w r3, r3, #3072 ; 0xc00 - 800b49c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 800b4a0: d01a beq.n 800b4d8 - 800b4a2: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 800b4a6: d81b bhi.n 800b4e0 - 800b4a8: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800b4ac: d00c beq.n 800b4c8 - 800b4ae: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800b4b2: d815 bhi.n 800b4e0 - 800b4b4: 2b00 cmp r3, #0 - 800b4b6: d003 beq.n 800b4c0 - 800b4b8: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 800b4bc: d008 beq.n 800b4d0 - 800b4be: e00f b.n 800b4e0 - 800b4c0: 2300 movs r3, #0 - 800b4c2: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b4c6: e012 b.n 800b4ee - 800b4c8: 2302 movs r3, #2 - 800b4ca: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b4ce: e00e b.n 800b4ee - 800b4d0: 2304 movs r3, #4 - 800b4d2: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b4d6: e00a b.n 800b4ee - 800b4d8: 2308 movs r3, #8 - 800b4da: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b4de: e006 b.n 800b4ee - 800b4e0: 2310 movs r3, #16 - 800b4e2: f887 3023 strb.w r3, [r7, #35] ; 0x23 - 800b4e6: e002 b.n 800b4ee - 800b4e8: 2310 movs r3, #16 - 800b4ea: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c7dc: 68fb ldr r3, [r7, #12] + 800c7de: 681b ldr r3, [r3, #0] + 800c7e0: 4aa0 ldr r2, [pc, #640] ; (800ca64 ) + 800c7e2: 4293 cmp r3, r2 + 800c7e4: d126 bne.n 800c834 + 800c7e6: 4ba0 ldr r3, [pc, #640] ; (800ca68 ) + 800c7e8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800c7ec: f003 0303 and.w r3, r3, #3 + 800c7f0: 2b03 cmp r3, #3 + 800c7f2: d81b bhi.n 800c82c + 800c7f4: a201 add r2, pc, #4 ; (adr r2, 800c7fc ) + 800c7f6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800c7fa: bf00 nop + 800c7fc: 0800c80d .word 0x0800c80d + 800c800: 0800c81d .word 0x0800c81d + 800c804: 0800c815 .word 0x0800c815 + 800c808: 0800c825 .word 0x0800c825 + 800c80c: 2301 movs r3, #1 + 800c80e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c812: e080 b.n 800c916 + 800c814: 2302 movs r3, #2 + 800c816: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c81a: e07c b.n 800c916 + 800c81c: 2304 movs r3, #4 + 800c81e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c822: e078 b.n 800c916 + 800c824: 2308 movs r3, #8 + 800c826: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c82a: e074 b.n 800c916 + 800c82c: 2310 movs r3, #16 + 800c82e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c832: e070 b.n 800c916 + 800c834: 68fb ldr r3, [r7, #12] + 800c836: 681b ldr r3, [r3, #0] + 800c838: 4a8c ldr r2, [pc, #560] ; (800ca6c ) + 800c83a: 4293 cmp r3, r2 + 800c83c: d138 bne.n 800c8b0 + 800c83e: 4b8a ldr r3, [pc, #552] ; (800ca68 ) + 800c840: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800c844: f003 030c and.w r3, r3, #12 + 800c848: 2b0c cmp r3, #12 + 800c84a: d82d bhi.n 800c8a8 + 800c84c: a201 add r2, pc, #4 ; (adr r2, 800c854 ) + 800c84e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800c852: bf00 nop + 800c854: 0800c889 .word 0x0800c889 + 800c858: 0800c8a9 .word 0x0800c8a9 + 800c85c: 0800c8a9 .word 0x0800c8a9 + 800c860: 0800c8a9 .word 0x0800c8a9 + 800c864: 0800c899 .word 0x0800c899 + 800c868: 0800c8a9 .word 0x0800c8a9 + 800c86c: 0800c8a9 .word 0x0800c8a9 + 800c870: 0800c8a9 .word 0x0800c8a9 + 800c874: 0800c891 .word 0x0800c891 + 800c878: 0800c8a9 .word 0x0800c8a9 + 800c87c: 0800c8a9 .word 0x0800c8a9 + 800c880: 0800c8a9 .word 0x0800c8a9 + 800c884: 0800c8a1 .word 0x0800c8a1 + 800c888: 2300 movs r3, #0 + 800c88a: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c88e: e042 b.n 800c916 + 800c890: 2302 movs r3, #2 + 800c892: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c896: e03e b.n 800c916 + 800c898: 2304 movs r3, #4 + 800c89a: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c89e: e03a b.n 800c916 + 800c8a0: 2308 movs r3, #8 + 800c8a2: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c8a6: e036 b.n 800c916 + 800c8a8: 2310 movs r3, #16 + 800c8aa: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c8ae: e032 b.n 800c916 + 800c8b0: 68fb ldr r3, [r7, #12] + 800c8b2: 681b ldr r3, [r3, #0] + 800c8b4: 4a6a ldr r2, [pc, #424] ; (800ca60 ) + 800c8b6: 4293 cmp r3, r2 + 800c8b8: d12a bne.n 800c910 + 800c8ba: 4b6b ldr r3, [pc, #428] ; (800ca68 ) + 800c8bc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800c8c0: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 800c8c4: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 800c8c8: d01a beq.n 800c900 + 800c8ca: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 800c8ce: d81b bhi.n 800c908 + 800c8d0: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800c8d4: d00c beq.n 800c8f0 + 800c8d6: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800c8da: d815 bhi.n 800c908 + 800c8dc: 2b00 cmp r3, #0 + 800c8de: d003 beq.n 800c8e8 + 800c8e0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800c8e4: d008 beq.n 800c8f8 + 800c8e6: e00f b.n 800c908 + 800c8e8: 2300 movs r3, #0 + 800c8ea: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c8ee: e012 b.n 800c916 + 800c8f0: 2302 movs r3, #2 + 800c8f2: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c8f6: e00e b.n 800c916 + 800c8f8: 2304 movs r3, #4 + 800c8fa: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c8fe: e00a b.n 800c916 + 800c900: 2308 movs r3, #8 + 800c902: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c906: e006 b.n 800c916 + 800c908: 2310 movs r3, #16 + 800c90a: f887 3023 strb.w r3, [r7, #35] ; 0x23 + 800c90e: e002 b.n 800c916 + 800c910: 2310 movs r3, #16 + 800c912: f887 3023 strb.w r3, [r7, #35] ; 0x23 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) - 800b4ee: 68fb ldr r3, [r7, #12] - 800b4f0: 681b ldr r3, [r3, #0] - 800b4f2: 4a51 ldr r2, [pc, #324] ; (800b638 ) - 800b4f4: 4293 cmp r3, r2 - 800b4f6: d17a bne.n 800b5ee + 800c916: 68fb ldr r3, [r7, #12] + 800c918: 681b ldr r3, [r3, #0] + 800c91a: 4a51 ldr r2, [pc, #324] ; (800ca60 ) + 800c91c: 4293 cmp r3, r2 + 800c91e: d17a bne.n 800ca16 { /* Retrieve frequency clock */ switch (clocksource) - 800b4f8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 - 800b4fc: 2b08 cmp r3, #8 - 800b4fe: d824 bhi.n 800b54a - 800b500: a201 add r2, pc, #4 ; (adr r2, 800b508 ) - 800b502: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800b506: bf00 nop - 800b508: 0800b52d .word 0x0800b52d - 800b50c: 0800b54b .word 0x0800b54b - 800b510: 0800b535 .word 0x0800b535 - 800b514: 0800b54b .word 0x0800b54b - 800b518: 0800b53b .word 0x0800b53b - 800b51c: 0800b54b .word 0x0800b54b - 800b520: 0800b54b .word 0x0800b54b - 800b524: 0800b54b .word 0x0800b54b - 800b528: 0800b543 .word 0x0800b543 + 800c920: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800c924: 2b08 cmp r3, #8 + 800c926: d824 bhi.n 800c972 + 800c928: a201 add r2, pc, #4 ; (adr r2, 800c930 ) + 800c92a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800c92e: bf00 nop + 800c930: 0800c955 .word 0x0800c955 + 800c934: 0800c973 .word 0x0800c973 + 800c938: 0800c95d .word 0x0800c95d + 800c93c: 0800c973 .word 0x0800c973 + 800c940: 0800c963 .word 0x0800c963 + 800c944: 0800c973 .word 0x0800c973 + 800c948: 0800c973 .word 0x0800c973 + 800c94c: 0800c973 .word 0x0800c973 + 800c950: 0800c96b .word 0x0800c96b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 800b52c: f7fe fa24 bl 8009978 - 800b530: 61f8 str r0, [r7, #28] + 800c954: f7fd fce4 bl 800a320 + 800c958: 61f8 str r0, [r7, #28] break; - 800b532: e010 b.n 800b556 + 800c95a: e010 b.n 800c97e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 800b534: 4b44 ldr r3, [pc, #272] ; (800b648 ) - 800b536: 61fb str r3, [r7, #28] + 800c95c: 4b44 ldr r3, [pc, #272] ; (800ca70 ) + 800c95e: 61fb str r3, [r7, #28] break; - 800b538: e00d b.n 800b556 + 800c960: e00d b.n 800c97e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800b53a: f7fe f985 bl 8009848 - 800b53e: 61f8 str r0, [r7, #28] + 800c962: f7fd fc45 bl 800a1f0 + 800c966: 61f8 str r0, [r7, #28] break; - 800b540: e009 b.n 800b556 + 800c968: e009 b.n 800c97e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800b542: f44f 4300 mov.w r3, #32768 ; 0x8000 - 800b546: 61fb str r3, [r7, #28] + 800c96a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800c96e: 61fb str r3, [r7, #28] break; - 800b548: e005 b.n 800b556 + 800c970: e005 b.n 800c97e default: pclk = 0U; - 800b54a: 2300 movs r3, #0 - 800b54c: 61fb str r3, [r7, #28] + 800c972: 2300 movs r3, #0 + 800c974: 61fb str r3, [r7, #28] ret = HAL_ERROR; - 800b54e: 2301 movs r3, #1 - 800b550: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800c976: 2301 movs r3, #1 + 800c978: f887 3022 strb.w r3, [r7, #34] ; 0x22 break; - 800b554: bf00 nop + 800c97c: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) - 800b556: 69fb ldr r3, [r7, #28] - 800b558: 2b00 cmp r3, #0 - 800b55a: f000 8107 beq.w 800b76c + 800c97e: 69fb ldr r3, [r7, #28] + 800c980: 2b00 cmp r3, #0 + 800c982: f000 8107 beq.w 800cb94 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ #else /* No Prescaler applicable */ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((pclk < (3U * huart->Init.BaudRate)) || - 800b55e: 68fb ldr r3, [r7, #12] - 800b560: 685a ldr r2, [r3, #4] - 800b562: 4613 mov r3, r2 - 800b564: 005b lsls r3, r3, #1 - 800b566: 4413 add r3, r2 - 800b568: 69fa ldr r2, [r7, #28] - 800b56a: 429a cmp r2, r3 - 800b56c: d305 bcc.n 800b57a + 800c986: 68fb ldr r3, [r7, #12] + 800c988: 685a ldr r2, [r3, #4] + 800c98a: 4613 mov r3, r2 + 800c98c: 005b lsls r3, r3, #1 + 800c98e: 4413 add r3, r2 + 800c990: 69fa ldr r2, [r7, #28] + 800c992: 429a cmp r2, r3 + 800c994: d305 bcc.n 800c9a2 (pclk > (4096U * huart->Init.BaudRate))) - 800b56e: 68fb ldr r3, [r7, #12] - 800b570: 685b ldr r3, [r3, #4] - 800b572: 031b lsls r3, r3, #12 + 800c996: 68fb ldr r3, [r7, #12] + 800c998: 685b ldr r3, [r3, #4] + 800c99a: 031b lsls r3, r3, #12 if ((pclk < (3U * huart->Init.BaudRate)) || - 800b574: 69fa ldr r2, [r7, #28] - 800b576: 429a cmp r2, r3 - 800b578: d903 bls.n 800b582 + 800c99c: 69fa ldr r2, [r7, #28] + 800c99e: 429a cmp r2, r3 + 800c9a0: d903 bls.n 800c9aa { ret = HAL_ERROR; - 800b57a: 2301 movs r3, #1 - 800b57c: f887 3022 strb.w r3, [r7, #34] ; 0x22 - 800b580: e0f4 b.n 800b76c + 800c9a2: 2301 movs r3, #1 + 800c9a4: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800c9a8: e0f4 b.n 800cb94 } else { usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate)); - 800b582: 69fb ldr r3, [r7, #28] - 800b584: 2200 movs r2, #0 - 800b586: 461c mov r4, r3 - 800b588: 4615 mov r5, r2 - 800b58a: f04f 0200 mov.w r2, #0 - 800b58e: f04f 0300 mov.w r3, #0 - 800b592: 022b lsls r3, r5, #8 - 800b594: ea43 6314 orr.w r3, r3, r4, lsr #24 - 800b598: 0222 lsls r2, r4, #8 - 800b59a: 68f9 ldr r1, [r7, #12] - 800b59c: 6849 ldr r1, [r1, #4] - 800b59e: 0849 lsrs r1, r1, #1 - 800b5a0: 2000 movs r0, #0 - 800b5a2: 4688 mov r8, r1 - 800b5a4: 4681 mov r9, r0 - 800b5a6: eb12 0a08 adds.w sl, r2, r8 - 800b5aa: eb43 0b09 adc.w fp, r3, r9 - 800b5ae: 68fb ldr r3, [r7, #12] - 800b5b0: 685b ldr r3, [r3, #4] - 800b5b2: 2200 movs r2, #0 - 800b5b4: 603b str r3, [r7, #0] - 800b5b6: 607a str r2, [r7, #4] - 800b5b8: e9d7 2300 ldrd r2, r3, [r7] - 800b5bc: 4650 mov r0, sl - 800b5be: 4659 mov r1, fp - 800b5c0: f7f5 fb62 bl 8000c88 <__aeabi_uldivmod> - 800b5c4: 4602 mov r2, r0 - 800b5c6: 460b mov r3, r1 - 800b5c8: 4613 mov r3, r2 - 800b5ca: 61bb str r3, [r7, #24] + 800c9aa: 69fb ldr r3, [r7, #28] + 800c9ac: 2200 movs r2, #0 + 800c9ae: 461c mov r4, r3 + 800c9b0: 4615 mov r5, r2 + 800c9b2: f04f 0200 mov.w r2, #0 + 800c9b6: f04f 0300 mov.w r3, #0 + 800c9ba: 022b lsls r3, r5, #8 + 800c9bc: ea43 6314 orr.w r3, r3, r4, lsr #24 + 800c9c0: 0222 lsls r2, r4, #8 + 800c9c2: 68f9 ldr r1, [r7, #12] + 800c9c4: 6849 ldr r1, [r1, #4] + 800c9c6: 0849 lsrs r1, r1, #1 + 800c9c8: 2000 movs r0, #0 + 800c9ca: 4688 mov r8, r1 + 800c9cc: 4681 mov r9, r0 + 800c9ce: eb12 0a08 adds.w sl, r2, r8 + 800c9d2: eb43 0b09 adc.w fp, r3, r9 + 800c9d6: 68fb ldr r3, [r7, #12] + 800c9d8: 685b ldr r3, [r3, #4] + 800c9da: 2200 movs r2, #0 + 800c9dc: 603b str r3, [r7, #0] + 800c9de: 607a str r2, [r7, #4] + 800c9e0: e9d7 2300 ldrd r2, r3, [r7] + 800c9e4: 4650 mov r0, sl + 800c9e6: 4659 mov r1, fp + 800c9e8: f7f4 f94e bl 8000c88 <__aeabi_uldivmod> + 800c9ec: 4602 mov r2, r0 + 800c9ee: 460b mov r3, r1 + 800c9f0: 4613 mov r3, r2 + 800c9f2: 61bb str r3, [r7, #24] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - 800b5cc: 69bb ldr r3, [r7, #24] - 800b5ce: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 800b5d2: d308 bcc.n 800b5e6 - 800b5d4: 69bb ldr r3, [r7, #24] - 800b5d6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800b5da: d204 bcs.n 800b5e6 + 800c9f4: 69bb ldr r3, [r7, #24] + 800c9f6: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 800c9fa: d308 bcc.n 800ca0e + 800c9fc: 69bb ldr r3, [r7, #24] + 800c9fe: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800ca02: d204 bcs.n 800ca0e { huart->Instance->BRR = usartdiv; - 800b5dc: 68fb ldr r3, [r7, #12] - 800b5de: 681b ldr r3, [r3, #0] - 800b5e0: 69ba ldr r2, [r7, #24] - 800b5e2: 60da str r2, [r3, #12] - 800b5e4: e0c2 b.n 800b76c + 800ca04: 68fb ldr r3, [r7, #12] + 800ca06: 681b ldr r3, [r3, #0] + 800ca08: 69ba ldr r2, [r7, #24] + 800ca0a: 60da str r2, [r3, #12] + 800ca0c: e0c2 b.n 800cb94 } else { ret = HAL_ERROR; - 800b5e6: 2301 movs r3, #1 - 800b5e8: f887 3022 strb.w r3, [r7, #34] ; 0x22 - 800b5ec: e0be b.n 800b76c + 800ca0e: 2301 movs r3, #1 + 800ca10: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800ca14: e0be b.n 800cb94 } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */ #endif /* USART_PRESC_PRESCALER */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 800b5ee: 68fb ldr r3, [r7, #12] - 800b5f0: 69db ldr r3, [r3, #28] - 800b5f2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 800b5f6: d16a bne.n 800b6ce + 800ca16: 68fb ldr r3, [r7, #12] + 800ca18: 69db ldr r3, [r3, #28] + 800ca1a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800ca1e: d16a bne.n 800caf6 { switch (clocksource) - 800b5f8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 - 800b5fc: 2b08 cmp r3, #8 - 800b5fe: d834 bhi.n 800b66a - 800b600: a201 add r2, pc, #4 ; (adr r2, 800b608 ) - 800b602: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800b606: bf00 nop - 800b608: 0800b62d .word 0x0800b62d - 800b60c: 0800b64d .word 0x0800b64d - 800b610: 0800b655 .word 0x0800b655 - 800b614: 0800b66b .word 0x0800b66b - 800b618: 0800b65b .word 0x0800b65b - 800b61c: 0800b66b .word 0x0800b66b - 800b620: 0800b66b .word 0x0800b66b - 800b624: 0800b66b .word 0x0800b66b - 800b628: 0800b663 .word 0x0800b663 + 800ca20: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800ca24: 2b08 cmp r3, #8 + 800ca26: d834 bhi.n 800ca92 + 800ca28: a201 add r2, pc, #4 ; (adr r2, 800ca30 ) + 800ca2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ca2e: bf00 nop + 800ca30: 0800ca55 .word 0x0800ca55 + 800ca34: 0800ca75 .word 0x0800ca75 + 800ca38: 0800ca7d .word 0x0800ca7d + 800ca3c: 0800ca93 .word 0x0800ca93 + 800ca40: 0800ca83 .word 0x0800ca83 + 800ca44: 0800ca93 .word 0x0800ca93 + 800ca48: 0800ca93 .word 0x0800ca93 + 800ca4c: 0800ca93 .word 0x0800ca93 + 800ca50: 0800ca8b .word 0x0800ca8b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 800b62c: f7fe f9a4 bl 8009978 - 800b630: 61f8 str r0, [r7, #28] + 800ca54: f7fd fc64 bl 800a320 + 800ca58: 61f8 str r0, [r7, #28] break; - 800b632: e020 b.n 800b676 - 800b634: efff69f3 .word 0xefff69f3 - 800b638: 40008000 .word 0x40008000 - 800b63c: 40013800 .word 0x40013800 - 800b640: 40021000 .word 0x40021000 - 800b644: 40004400 .word 0x40004400 - 800b648: 00f42400 .word 0x00f42400 + 800ca5a: e020 b.n 800ca9e + 800ca5c: efff69f3 .word 0xefff69f3 + 800ca60: 40008000 .word 0x40008000 + 800ca64: 40013800 .word 0x40013800 + 800ca68: 40021000 .word 0x40021000 + 800ca6c: 40004400 .word 0x40004400 + 800ca70: 00f42400 .word 0x00f42400 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 800b64c: f7fe f9aa bl 80099a4 - 800b650: 61f8 str r0, [r7, #28] + 800ca74: f7fd fc6a bl 800a34c + 800ca78: 61f8 str r0, [r7, #28] break; - 800b652: e010 b.n 800b676 + 800ca7a: e010 b.n 800ca9e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 800b654: 4b4c ldr r3, [pc, #304] ; (800b788 ) - 800b656: 61fb str r3, [r7, #28] + 800ca7c: 4b4c ldr r3, [pc, #304] ; (800cbb0 ) + 800ca7e: 61fb str r3, [r7, #28] break; - 800b658: e00d b.n 800b676 + 800ca80: e00d b.n 800ca9e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800b65a: f7fe f8f5 bl 8009848 - 800b65e: 61f8 str r0, [r7, #28] + 800ca82: f7fd fbb5 bl 800a1f0 + 800ca86: 61f8 str r0, [r7, #28] break; - 800b660: e009 b.n 800b676 + 800ca88: e009 b.n 800ca9e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800b662: f44f 4300 mov.w r3, #32768 ; 0x8000 - 800b666: 61fb str r3, [r7, #28] + 800ca8a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800ca8e: 61fb str r3, [r7, #28] break; - 800b668: e005 b.n 800b676 + 800ca90: e005 b.n 800ca9e default: pclk = 0U; - 800b66a: 2300 movs r3, #0 - 800b66c: 61fb str r3, [r7, #28] + 800ca92: 2300 movs r3, #0 + 800ca94: 61fb str r3, [r7, #28] ret = HAL_ERROR; - 800b66e: 2301 movs r3, #1 - 800b670: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800ca96: 2301 movs r3, #1 + 800ca98: f887 3022 strb.w r3, [r7, #34] ; 0x22 break; - 800b674: bf00 nop + 800ca9c: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 800b676: 69fb ldr r3, [r7, #28] - 800b678: 2b00 cmp r3, #0 - 800b67a: d077 beq.n 800b76c + 800ca9e: 69fb ldr r3, [r7, #28] + 800caa0: 2b00 cmp r3, #0 + 800caa2: d077 beq.n 800cb94 { #if defined(USART_PRESC_PRESCALER) usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - 800b67c: 69fb ldr r3, [r7, #28] - 800b67e: 005a lsls r2, r3, #1 - 800b680: 68fb ldr r3, [r7, #12] - 800b682: 685b ldr r3, [r3, #4] - 800b684: 085b lsrs r3, r3, #1 - 800b686: 441a add r2, r3 - 800b688: 68fb ldr r3, [r7, #12] - 800b68a: 685b ldr r3, [r3, #4] - 800b68c: fbb2 f3f3 udiv r3, r2, r3 - 800b690: 61bb str r3, [r7, #24] + 800caa4: 69fb ldr r3, [r7, #28] + 800caa6: 005a lsls r2, r3, #1 + 800caa8: 68fb ldr r3, [r7, #12] + 800caaa: 685b ldr r3, [r3, #4] + 800caac: 085b lsrs r3, r3, #1 + 800caae: 441a add r2, r3 + 800cab0: 68fb ldr r3, [r7, #12] + 800cab2: 685b ldr r3, [r3, #4] + 800cab4: fbb2 f3f3 udiv r3, r2, r3 + 800cab8: 61bb str r3, [r7, #24] #endif /* USART_PRESC_PRESCALER */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 800b692: 69bb ldr r3, [r7, #24] - 800b694: 2b0f cmp r3, #15 - 800b696: d916 bls.n 800b6c6 - 800b698: 69bb ldr r3, [r7, #24] - 800b69a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800b69e: d212 bcs.n 800b6c6 + 800caba: 69bb ldr r3, [r7, #24] + 800cabc: 2b0f cmp r3, #15 + 800cabe: d916 bls.n 800caee + 800cac0: 69bb ldr r3, [r7, #24] + 800cac2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800cac6: d212 bcs.n 800caee { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 800b6a0: 69bb ldr r3, [r7, #24] - 800b6a2: b29b uxth r3, r3 - 800b6a4: f023 030f bic.w r3, r3, #15 - 800b6a8: 82fb strh r3, [r7, #22] + 800cac8: 69bb ldr r3, [r7, #24] + 800caca: b29b uxth r3, r3 + 800cacc: f023 030f bic.w r3, r3, #15 + 800cad0: 82fb strh r3, [r7, #22] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 800b6aa: 69bb ldr r3, [r7, #24] - 800b6ac: 085b lsrs r3, r3, #1 - 800b6ae: b29b uxth r3, r3 - 800b6b0: f003 0307 and.w r3, r3, #7 - 800b6b4: b29a uxth r2, r3 - 800b6b6: 8afb ldrh r3, [r7, #22] - 800b6b8: 4313 orrs r3, r2 - 800b6ba: 82fb strh r3, [r7, #22] + 800cad2: 69bb ldr r3, [r7, #24] + 800cad4: 085b lsrs r3, r3, #1 + 800cad6: b29b uxth r3, r3 + 800cad8: f003 0307 and.w r3, r3, #7 + 800cadc: b29a uxth r2, r3 + 800cade: 8afb ldrh r3, [r7, #22] + 800cae0: 4313 orrs r3, r2 + 800cae2: 82fb strh r3, [r7, #22] huart->Instance->BRR = brrtemp; - 800b6bc: 68fb ldr r3, [r7, #12] - 800b6be: 681b ldr r3, [r3, #0] - 800b6c0: 8afa ldrh r2, [r7, #22] - 800b6c2: 60da str r2, [r3, #12] - 800b6c4: e052 b.n 800b76c + 800cae4: 68fb ldr r3, [r7, #12] + 800cae6: 681b ldr r3, [r3, #0] + 800cae8: 8afa ldrh r2, [r7, #22] + 800caea: 60da str r2, [r3, #12] + 800caec: e052 b.n 800cb94 } else { ret = HAL_ERROR; - 800b6c6: 2301 movs r3, #1 - 800b6c8: f887 3022 strb.w r3, [r7, #34] ; 0x22 - 800b6cc: e04e b.n 800b76c + 800caee: 2301 movs r3, #1 + 800caf0: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800caf4: e04e b.n 800cb94 } } } else { switch (clocksource) - 800b6ce: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 - 800b6d2: 2b08 cmp r3, #8 - 800b6d4: d827 bhi.n 800b726 - 800b6d6: a201 add r2, pc, #4 ; (adr r2, 800b6dc ) - 800b6d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800b6dc: 0800b701 .word 0x0800b701 - 800b6e0: 0800b709 .word 0x0800b709 - 800b6e4: 0800b711 .word 0x0800b711 - 800b6e8: 0800b727 .word 0x0800b727 - 800b6ec: 0800b717 .word 0x0800b717 - 800b6f0: 0800b727 .word 0x0800b727 - 800b6f4: 0800b727 .word 0x0800b727 - 800b6f8: 0800b727 .word 0x0800b727 - 800b6fc: 0800b71f .word 0x0800b71f + 800caf6: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800cafa: 2b08 cmp r3, #8 + 800cafc: d827 bhi.n 800cb4e + 800cafe: a201 add r2, pc, #4 ; (adr r2, 800cb04 ) + 800cb00: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800cb04: 0800cb29 .word 0x0800cb29 + 800cb08: 0800cb31 .word 0x0800cb31 + 800cb0c: 0800cb39 .word 0x0800cb39 + 800cb10: 0800cb4f .word 0x0800cb4f + 800cb14: 0800cb3f .word 0x0800cb3f + 800cb18: 0800cb4f .word 0x0800cb4f + 800cb1c: 0800cb4f .word 0x0800cb4f + 800cb20: 0800cb4f .word 0x0800cb4f + 800cb24: 0800cb47 .word 0x0800cb47 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 800b700: f7fe f93a bl 8009978 - 800b704: 61f8 str r0, [r7, #28] + 800cb28: f7fd fbfa bl 800a320 + 800cb2c: 61f8 str r0, [r7, #28] break; - 800b706: e014 b.n 800b732 + 800cb2e: e014 b.n 800cb5a case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 800b708: f7fe f94c bl 80099a4 - 800b70c: 61f8 str r0, [r7, #28] + 800cb30: f7fd fc0c bl 800a34c + 800cb34: 61f8 str r0, [r7, #28] break; - 800b70e: e010 b.n 800b732 + 800cb36: e010 b.n 800cb5a case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 800b710: 4b1d ldr r3, [pc, #116] ; (800b788 ) - 800b712: 61fb str r3, [r7, #28] + 800cb38: 4b1d ldr r3, [pc, #116] ; (800cbb0 ) + 800cb3a: 61fb str r3, [r7, #28] break; - 800b714: e00d b.n 800b732 + 800cb3c: e00d b.n 800cb5a case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800b716: f7fe f897 bl 8009848 - 800b71a: 61f8 str r0, [r7, #28] + 800cb3e: f7fd fb57 bl 800a1f0 + 800cb42: 61f8 str r0, [r7, #28] break; - 800b71c: e009 b.n 800b732 + 800cb44: e009 b.n 800cb5a case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800b71e: f44f 4300 mov.w r3, #32768 ; 0x8000 - 800b722: 61fb str r3, [r7, #28] + 800cb46: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800cb4a: 61fb str r3, [r7, #28] break; - 800b724: e005 b.n 800b732 + 800cb4c: e005 b.n 800cb5a default: pclk = 0U; - 800b726: 2300 movs r3, #0 - 800b728: 61fb str r3, [r7, #28] + 800cb4e: 2300 movs r3, #0 + 800cb50: 61fb str r3, [r7, #28] ret = HAL_ERROR; - 800b72a: 2301 movs r3, #1 - 800b72c: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800cb52: 2301 movs r3, #1 + 800cb54: f887 3022 strb.w r3, [r7, #34] ; 0x22 break; - 800b730: bf00 nop + 800cb58: bf00 nop } if (pclk != 0U) - 800b732: 69fb ldr r3, [r7, #28] - 800b734: 2b00 cmp r3, #0 - 800b736: d019 beq.n 800b76c + 800cb5a: 69fb ldr r3, [r7, #28] + 800cb5c: 2b00 cmp r3, #0 + 800cb5e: d019 beq.n 800cb94 { /* USARTDIV must be greater than or equal to 0d16 */ #if defined(USART_PRESC_PRESCALER) usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); #else usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - 800b738: 68fb ldr r3, [r7, #12] - 800b73a: 685b ldr r3, [r3, #4] - 800b73c: 085a lsrs r2, r3, #1 - 800b73e: 69fb ldr r3, [r7, #28] - 800b740: 441a add r2, r3 - 800b742: 68fb ldr r3, [r7, #12] - 800b744: 685b ldr r3, [r3, #4] - 800b746: fbb2 f3f3 udiv r3, r2, r3 - 800b74a: 61bb str r3, [r7, #24] + 800cb60: 68fb ldr r3, [r7, #12] + 800cb62: 685b ldr r3, [r3, #4] + 800cb64: 085a lsrs r2, r3, #1 + 800cb66: 69fb ldr r3, [r7, #28] + 800cb68: 441a add r2, r3 + 800cb6a: 68fb ldr r3, [r7, #12] + 800cb6c: 685b ldr r3, [r3, #4] + 800cb6e: fbb2 f3f3 udiv r3, r2, r3 + 800cb72: 61bb str r3, [r7, #24] #endif /* USART_PRESC_PRESCALER */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 800b74c: 69bb ldr r3, [r7, #24] - 800b74e: 2b0f cmp r3, #15 - 800b750: d909 bls.n 800b766 - 800b752: 69bb ldr r3, [r7, #24] - 800b754: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800b758: d205 bcs.n 800b766 + 800cb74: 69bb ldr r3, [r7, #24] + 800cb76: 2b0f cmp r3, #15 + 800cb78: d909 bls.n 800cb8e + 800cb7a: 69bb ldr r3, [r7, #24] + 800cb7c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800cb80: d205 bcs.n 800cb8e { huart->Instance->BRR = (uint16_t)usartdiv; - 800b75a: 69bb ldr r3, [r7, #24] - 800b75c: b29a uxth r2, r3 - 800b75e: 68fb ldr r3, [r7, #12] - 800b760: 681b ldr r3, [r3, #0] - 800b762: 60da str r2, [r3, #12] - 800b764: e002 b.n 800b76c + 800cb82: 69bb ldr r3, [r7, #24] + 800cb84: b29a uxth r2, r3 + 800cb86: 68fb ldr r3, [r7, #12] + 800cb88: 681b ldr r3, [r3, #0] + 800cb8a: 60da str r2, [r3, #12] + 800cb8c: e002 b.n 800cb94 } else { ret = HAL_ERROR; - 800b766: 2301 movs r3, #1 - 800b768: f887 3022 strb.w r3, [r7, #34] ; 0x22 + 800cb8e: 2301 movs r3, #1 + 800cb90: f887 3022 strb.w r3, [r7, #34] ; 0x22 huart->NbTxDataToProcess = 1; huart->NbRxDataToProcess = 1; #endif /* USART_CR1_FIFOEN */ /* Clear ISR function pointers */ huart->RxISR = NULL; - 800b76c: 68fb ldr r3, [r7, #12] - 800b76e: 2200 movs r2, #0 - 800b770: 669a str r2, [r3, #104] ; 0x68 + 800cb94: 68fb ldr r3, [r7, #12] + 800cb96: 2200 movs r2, #0 + 800cb98: 669a str r2, [r3, #104] ; 0x68 huart->TxISR = NULL; - 800b772: 68fb ldr r3, [r7, #12] - 800b774: 2200 movs r2, #0 - 800b776: 66da str r2, [r3, #108] ; 0x6c + 800cb9a: 68fb ldr r3, [r7, #12] + 800cb9c: 2200 movs r2, #0 + 800cb9e: 66da str r2, [r3, #108] ; 0x6c return ret; - 800b778: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 + 800cba0: f897 3022 ldrb.w r3, [r7, #34] ; 0x22 } - 800b77c: 4618 mov r0, r3 - 800b77e: 3728 adds r7, #40 ; 0x28 - 800b780: 46bd mov sp, r7 - 800b782: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 800b786: bf00 nop - 800b788: 00f42400 .word 0x00f42400 + 800cba4: 4618 mov r0, r3 + 800cba6: 3728 adds r7, #40 ; 0x28 + 800cba8: 46bd mov sp, r7 + 800cbaa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 800cbae: bf00 nop + 800cbb0: 00f42400 .word 0x00f42400 -0800b78c : +0800cbb4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 800b78c: b480 push {r7} - 800b78e: b083 sub sp, #12 - 800b790: af00 add r7, sp, #0 - 800b792: 6078 str r0, [r7, #4] + 800cbb4: b480 push {r7} + 800cbb6: b083 sub sp, #12 + 800cbb8: af00 add r7, sp, #0 + 800cbba: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 800b794: 687b ldr r3, [r7, #4] - 800b796: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b798: f003 0308 and.w r3, r3, #8 - 800b79c: 2b00 cmp r3, #0 - 800b79e: d00a beq.n 800b7b6 + 800cbbc: 687b ldr r3, [r7, #4] + 800cbbe: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cbc0: f003 0308 and.w r3, r3, #8 + 800cbc4: 2b00 cmp r3, #0 + 800cbc6: d00a beq.n 800cbde { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 800b7a0: 687b ldr r3, [r7, #4] - 800b7a2: 681b ldr r3, [r3, #0] - 800b7a4: 685b ldr r3, [r3, #4] - 800b7a6: f423 4100 bic.w r1, r3, #32768 ; 0x8000 - 800b7aa: 687b ldr r3, [r7, #4] - 800b7ac: 6b5a ldr r2, [r3, #52] ; 0x34 - 800b7ae: 687b ldr r3, [r7, #4] - 800b7b0: 681b ldr r3, [r3, #0] - 800b7b2: 430a orrs r2, r1 - 800b7b4: 605a str r2, [r3, #4] + 800cbc8: 687b ldr r3, [r7, #4] + 800cbca: 681b ldr r3, [r3, #0] + 800cbcc: 685b ldr r3, [r3, #4] + 800cbce: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 800cbd2: 687b ldr r3, [r7, #4] + 800cbd4: 6b5a ldr r2, [r3, #52] ; 0x34 + 800cbd6: 687b ldr r3, [r7, #4] + 800cbd8: 681b ldr r3, [r3, #0] + 800cbda: 430a orrs r2, r1 + 800cbdc: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 800b7b6: 687b ldr r3, [r7, #4] - 800b7b8: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b7ba: f003 0301 and.w r3, r3, #1 - 800b7be: 2b00 cmp r3, #0 - 800b7c0: d00a beq.n 800b7d8 + 800cbde: 687b ldr r3, [r7, #4] + 800cbe0: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cbe2: f003 0301 and.w r3, r3, #1 + 800cbe6: 2b00 cmp r3, #0 + 800cbe8: d00a beq.n 800cc00 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 800b7c2: 687b ldr r3, [r7, #4] - 800b7c4: 681b ldr r3, [r3, #0] - 800b7c6: 685b ldr r3, [r3, #4] - 800b7c8: f423 3100 bic.w r1, r3, #131072 ; 0x20000 - 800b7cc: 687b ldr r3, [r7, #4] - 800b7ce: 6a9a ldr r2, [r3, #40] ; 0x28 - 800b7d0: 687b ldr r3, [r7, #4] - 800b7d2: 681b ldr r3, [r3, #0] - 800b7d4: 430a orrs r2, r1 - 800b7d6: 605a str r2, [r3, #4] + 800cbea: 687b ldr r3, [r7, #4] + 800cbec: 681b ldr r3, [r3, #0] + 800cbee: 685b ldr r3, [r3, #4] + 800cbf0: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 800cbf4: 687b ldr r3, [r7, #4] + 800cbf6: 6a9a ldr r2, [r3, #40] ; 0x28 + 800cbf8: 687b ldr r3, [r7, #4] + 800cbfa: 681b ldr r3, [r3, #0] + 800cbfc: 430a orrs r2, r1 + 800cbfe: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 800b7d8: 687b ldr r3, [r7, #4] - 800b7da: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b7dc: f003 0302 and.w r3, r3, #2 - 800b7e0: 2b00 cmp r3, #0 - 800b7e2: d00a beq.n 800b7fa + 800cc00: 687b ldr r3, [r7, #4] + 800cc02: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cc04: f003 0302 and.w r3, r3, #2 + 800cc08: 2b00 cmp r3, #0 + 800cc0a: d00a beq.n 800cc22 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 800b7e4: 687b ldr r3, [r7, #4] - 800b7e6: 681b ldr r3, [r3, #0] - 800b7e8: 685b ldr r3, [r3, #4] - 800b7ea: f423 3180 bic.w r1, r3, #65536 ; 0x10000 - 800b7ee: 687b ldr r3, [r7, #4] - 800b7f0: 6ada ldr r2, [r3, #44] ; 0x2c - 800b7f2: 687b ldr r3, [r7, #4] - 800b7f4: 681b ldr r3, [r3, #0] - 800b7f6: 430a orrs r2, r1 - 800b7f8: 605a str r2, [r3, #4] + 800cc0c: 687b ldr r3, [r7, #4] + 800cc0e: 681b ldr r3, [r3, #0] + 800cc10: 685b ldr r3, [r3, #4] + 800cc12: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 800cc16: 687b ldr r3, [r7, #4] + 800cc18: 6ada ldr r2, [r3, #44] ; 0x2c + 800cc1a: 687b ldr r3, [r7, #4] + 800cc1c: 681b ldr r3, [r3, #0] + 800cc1e: 430a orrs r2, r1 + 800cc20: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 800b7fa: 687b ldr r3, [r7, #4] - 800b7fc: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b7fe: f003 0304 and.w r3, r3, #4 - 800b802: 2b00 cmp r3, #0 - 800b804: d00a beq.n 800b81c + 800cc22: 687b ldr r3, [r7, #4] + 800cc24: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cc26: f003 0304 and.w r3, r3, #4 + 800cc2a: 2b00 cmp r3, #0 + 800cc2c: d00a beq.n 800cc44 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 800b806: 687b ldr r3, [r7, #4] - 800b808: 681b ldr r3, [r3, #0] - 800b80a: 685b ldr r3, [r3, #4] - 800b80c: f423 2180 bic.w r1, r3, #262144 ; 0x40000 - 800b810: 687b ldr r3, [r7, #4] - 800b812: 6b1a ldr r2, [r3, #48] ; 0x30 - 800b814: 687b ldr r3, [r7, #4] - 800b816: 681b ldr r3, [r3, #0] - 800b818: 430a orrs r2, r1 - 800b81a: 605a str r2, [r3, #4] + 800cc2e: 687b ldr r3, [r7, #4] + 800cc30: 681b ldr r3, [r3, #0] + 800cc32: 685b ldr r3, [r3, #4] + 800cc34: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800cc38: 687b ldr r3, [r7, #4] + 800cc3a: 6b1a ldr r2, [r3, #48] ; 0x30 + 800cc3c: 687b ldr r3, [r7, #4] + 800cc3e: 681b ldr r3, [r3, #0] + 800cc40: 430a orrs r2, r1 + 800cc42: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 800b81c: 687b ldr r3, [r7, #4] - 800b81e: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b820: f003 0310 and.w r3, r3, #16 - 800b824: 2b00 cmp r3, #0 - 800b826: d00a beq.n 800b83e + 800cc44: 687b ldr r3, [r7, #4] + 800cc46: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cc48: f003 0310 and.w r3, r3, #16 + 800cc4c: 2b00 cmp r3, #0 + 800cc4e: d00a beq.n 800cc66 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 800b828: 687b ldr r3, [r7, #4] - 800b82a: 681b ldr r3, [r3, #0] - 800b82c: 689b ldr r3, [r3, #8] - 800b82e: f423 5180 bic.w r1, r3, #4096 ; 0x1000 - 800b832: 687b ldr r3, [r7, #4] - 800b834: 6b9a ldr r2, [r3, #56] ; 0x38 - 800b836: 687b ldr r3, [r7, #4] - 800b838: 681b ldr r3, [r3, #0] - 800b83a: 430a orrs r2, r1 - 800b83c: 609a str r2, [r3, #8] + 800cc50: 687b ldr r3, [r7, #4] + 800cc52: 681b ldr r3, [r3, #0] + 800cc54: 689b ldr r3, [r3, #8] + 800cc56: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 800cc5a: 687b ldr r3, [r7, #4] + 800cc5c: 6b9a ldr r2, [r3, #56] ; 0x38 + 800cc5e: 687b ldr r3, [r7, #4] + 800cc60: 681b ldr r3, [r3, #0] + 800cc62: 430a orrs r2, r1 + 800cc64: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 800b83e: 687b ldr r3, [r7, #4] - 800b840: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b842: f003 0320 and.w r3, r3, #32 - 800b846: 2b00 cmp r3, #0 - 800b848: d00a beq.n 800b860 + 800cc66: 687b ldr r3, [r7, #4] + 800cc68: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cc6a: f003 0320 and.w r3, r3, #32 + 800cc6e: 2b00 cmp r3, #0 + 800cc70: d00a beq.n 800cc88 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 800b84a: 687b ldr r3, [r7, #4] - 800b84c: 681b ldr r3, [r3, #0] - 800b84e: 689b ldr r3, [r3, #8] - 800b850: f423 5100 bic.w r1, r3, #8192 ; 0x2000 - 800b854: 687b ldr r3, [r7, #4] - 800b856: 6bda ldr r2, [r3, #60] ; 0x3c - 800b858: 687b ldr r3, [r7, #4] - 800b85a: 681b ldr r3, [r3, #0] - 800b85c: 430a orrs r2, r1 - 800b85e: 609a str r2, [r3, #8] + 800cc72: 687b ldr r3, [r7, #4] + 800cc74: 681b ldr r3, [r3, #0] + 800cc76: 689b ldr r3, [r3, #8] + 800cc78: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 800cc7c: 687b ldr r3, [r7, #4] + 800cc7e: 6bda ldr r2, [r3, #60] ; 0x3c + 800cc80: 687b ldr r3, [r7, #4] + 800cc82: 681b ldr r3, [r3, #0] + 800cc84: 430a orrs r2, r1 + 800cc86: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 800b860: 687b ldr r3, [r7, #4] - 800b862: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b864: f003 0340 and.w r3, r3, #64 ; 0x40 - 800b868: 2b00 cmp r3, #0 - 800b86a: d01a beq.n 800b8a2 + 800cc88: 687b ldr r3, [r7, #4] + 800cc8a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800cc8c: f003 0340 and.w r3, r3, #64 ; 0x40 + 800cc90: 2b00 cmp r3, #0 + 800cc92: d01a beq.n 800ccca { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 800b86c: 687b ldr r3, [r7, #4] - 800b86e: 681b ldr r3, [r3, #0] - 800b870: 685b ldr r3, [r3, #4] - 800b872: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 - 800b876: 687b ldr r3, [r7, #4] - 800b878: 6c1a ldr r2, [r3, #64] ; 0x40 - 800b87a: 687b ldr r3, [r7, #4] - 800b87c: 681b ldr r3, [r3, #0] - 800b87e: 430a orrs r2, r1 - 800b880: 605a str r2, [r3, #4] + 800cc94: 687b ldr r3, [r7, #4] + 800cc96: 681b ldr r3, [r3, #0] + 800cc98: 685b ldr r3, [r3, #4] + 800cc9a: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 800cc9e: 687b ldr r3, [r7, #4] + 800cca0: 6c1a ldr r2, [r3, #64] ; 0x40 + 800cca2: 687b ldr r3, [r7, #4] + 800cca4: 681b ldr r3, [r3, #0] + 800cca6: 430a orrs r2, r1 + 800cca8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 800b882: 687b ldr r3, [r7, #4] - 800b884: 6c1b ldr r3, [r3, #64] ; 0x40 - 800b886: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800b88a: d10a bne.n 800b8a2 + 800ccaa: 687b ldr r3, [r7, #4] + 800ccac: 6c1b ldr r3, [r3, #64] ; 0x40 + 800ccae: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800ccb2: d10a bne.n 800ccca { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 800b88c: 687b ldr r3, [r7, #4] - 800b88e: 681b ldr r3, [r3, #0] - 800b890: 685b ldr r3, [r3, #4] - 800b892: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 - 800b896: 687b ldr r3, [r7, #4] - 800b898: 6c5a ldr r2, [r3, #68] ; 0x44 - 800b89a: 687b ldr r3, [r7, #4] - 800b89c: 681b ldr r3, [r3, #0] - 800b89e: 430a orrs r2, r1 - 800b8a0: 605a str r2, [r3, #4] + 800ccb4: 687b ldr r3, [r7, #4] + 800ccb6: 681b ldr r3, [r3, #0] + 800ccb8: 685b ldr r3, [r3, #4] + 800ccba: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 800ccbe: 687b ldr r3, [r7, #4] + 800ccc0: 6c5a ldr r2, [r3, #68] ; 0x44 + 800ccc2: 687b ldr r3, [r7, #4] + 800ccc4: 681b ldr r3, [r3, #0] + 800ccc6: 430a orrs r2, r1 + 800ccc8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 800b8a2: 687b ldr r3, [r7, #4] - 800b8a4: 6a5b ldr r3, [r3, #36] ; 0x24 - 800b8a6: f003 0380 and.w r3, r3, #128 ; 0x80 - 800b8aa: 2b00 cmp r3, #0 - 800b8ac: d00a beq.n 800b8c4 + 800ccca: 687b ldr r3, [r7, #4] + 800cccc: 6a5b ldr r3, [r3, #36] ; 0x24 + 800ccce: f003 0380 and.w r3, r3, #128 ; 0x80 + 800ccd2: 2b00 cmp r3, #0 + 800ccd4: d00a beq.n 800ccec { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 800b8ae: 687b ldr r3, [r7, #4] - 800b8b0: 681b ldr r3, [r3, #0] - 800b8b2: 685b ldr r3, [r3, #4] - 800b8b4: f423 2100 bic.w r1, r3, #524288 ; 0x80000 - 800b8b8: 687b ldr r3, [r7, #4] - 800b8ba: 6c9a ldr r2, [r3, #72] ; 0x48 - 800b8bc: 687b ldr r3, [r7, #4] - 800b8be: 681b ldr r3, [r3, #0] - 800b8c0: 430a orrs r2, r1 - 800b8c2: 605a str r2, [r3, #4] - } -} - 800b8c4: bf00 nop - 800b8c6: 370c adds r7, #12 - 800b8c8: 46bd mov sp, r7 - 800b8ca: f85d 7b04 ldr.w r7, [sp], #4 - 800b8ce: 4770 bx lr - -0800b8d0 : + 800ccd6: 687b ldr r3, [r7, #4] + 800ccd8: 681b ldr r3, [r3, #0] + 800ccda: 685b ldr r3, [r3, #4] + 800ccdc: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 800cce0: 687b ldr r3, [r7, #4] + 800cce2: 6c9a ldr r2, [r3, #72] ; 0x48 + 800cce4: 687b ldr r3, [r7, #4] + 800cce6: 681b ldr r3, [r3, #0] + 800cce8: 430a orrs r2, r1 + 800ccea: 605a str r2, [r3, #4] + } +} + 800ccec: bf00 nop + 800ccee: 370c adds r7, #12 + 800ccf0: 46bd mov sp, r7 + 800ccf2: f85d 7b04 ldr.w r7, [sp], #4 + 800ccf6: 4770 bx lr + +0800ccf8 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 800b8d0: b580 push {r7, lr} - 800b8d2: b098 sub sp, #96 ; 0x60 - 800b8d4: af02 add r7, sp, #8 - 800b8d6: 6078 str r0, [r7, #4] + 800ccf8: b580 push {r7, lr} + 800ccfa: b098 sub sp, #96 ; 0x60 + 800ccfc: af02 add r7, sp, #8 + 800ccfe: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800b8d8: 687b ldr r3, [r7, #4] - 800b8da: 2200 movs r2, #0 - 800b8dc: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800cd00: 687b ldr r3, [r7, #4] + 800cd02: 2200 movs r2, #0 + 800cd04: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 800b8e0: f7f8 fe6c bl 80045bc - 800b8e4: 6578 str r0, [r7, #84] ; 0x54 + 800cd08: f7f8 faa2 bl 8005250 + 800cd0c: 6578 str r0, [r7, #84] ; 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 800b8e6: 687b ldr r3, [r7, #4] - 800b8e8: 681b ldr r3, [r3, #0] - 800b8ea: 681b ldr r3, [r3, #0] - 800b8ec: f003 0308 and.w r3, r3, #8 - 800b8f0: 2b08 cmp r3, #8 - 800b8f2: d12e bne.n 800b952 + 800cd0e: 687b ldr r3, [r7, #4] + 800cd10: 681b ldr r3, [r3, #0] + 800cd12: 681b ldr r3, [r3, #0] + 800cd14: f003 0308 and.w r3, r3, #8 + 800cd18: 2b08 cmp r3, #8 + 800cd1a: d12e bne.n 800cd7a { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 800b8f4: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 800b8f8: 9300 str r3, [sp, #0] - 800b8fa: 6d7b ldr r3, [r7, #84] ; 0x54 - 800b8fc: 2200 movs r2, #0 - 800b8fe: f44f 1100 mov.w r1, #2097152 ; 0x200000 - 800b902: 6878 ldr r0, [r7, #4] - 800b904: f000 f88c bl 800ba20 - 800b908: 4603 mov r3, r0 - 800b90a: 2b00 cmp r3, #0 - 800b90c: d021 beq.n 800b952 + 800cd1c: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 800cd20: 9300 str r3, [sp, #0] + 800cd22: 6d7b ldr r3, [r7, #84] ; 0x54 + 800cd24: 2200 movs r2, #0 + 800cd26: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 800cd2a: 6878 ldr r0, [r7, #4] + 800cd2c: f000 f88c bl 800ce48 + 800cd30: 4603 mov r3, r0 + 800cd32: 2b00 cmp r3, #0 + 800cd34: d021 beq.n 800cd7a { /* Disable TXE interrupt for the interrupt process */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); - 800b90e: 687b ldr r3, [r7, #4] - 800b910: 681b ldr r3, [r3, #0] - 800b912: 63bb str r3, [r7, #56] ; 0x38 + 800cd36: 687b ldr r3, [r7, #4] + 800cd38: 681b ldr r3, [r3, #0] + 800cd3a: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b914: 6bbb ldr r3, [r7, #56] ; 0x38 - 800b916: e853 3f00 ldrex r3, [r3] - 800b91a: 637b str r3, [r7, #52] ; 0x34 + 800cd3c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800cd3e: e853 3f00 ldrex r3, [r3] + 800cd42: 637b str r3, [r7, #52] ; 0x34 return(result); - 800b91c: 6b7b ldr r3, [r7, #52] ; 0x34 - 800b91e: f023 0380 bic.w r3, r3, #128 ; 0x80 - 800b922: 653b str r3, [r7, #80] ; 0x50 - 800b924: 687b ldr r3, [r7, #4] - 800b926: 681b ldr r3, [r3, #0] - 800b928: 461a mov r2, r3 - 800b92a: 6d3b ldr r3, [r7, #80] ; 0x50 - 800b92c: 647b str r3, [r7, #68] ; 0x44 - 800b92e: 643a str r2, [r7, #64] ; 0x40 + 800cd44: 6b7b ldr r3, [r7, #52] ; 0x34 + 800cd46: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800cd4a: 653b str r3, [r7, #80] ; 0x50 + 800cd4c: 687b ldr r3, [r7, #4] + 800cd4e: 681b ldr r3, [r3, #0] + 800cd50: 461a mov r2, r3 + 800cd52: 6d3b ldr r3, [r7, #80] ; 0x50 + 800cd54: 647b str r3, [r7, #68] ; 0x44 + 800cd56: 643a str r2, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b930: 6c39 ldr r1, [r7, #64] ; 0x40 - 800b932: 6c7a ldr r2, [r7, #68] ; 0x44 - 800b934: e841 2300 strex r3, r2, [r1] - 800b938: 63fb str r3, [r7, #60] ; 0x3c + 800cd58: 6c39 ldr r1, [r7, #64] ; 0x40 + 800cd5a: 6c7a ldr r2, [r7, #68] ; 0x44 + 800cd5c: e841 2300 strex r3, r2, [r1] + 800cd60: 63fb str r3, [r7, #60] ; 0x3c return(result); - 800b93a: 6bfb ldr r3, [r7, #60] ; 0x3c - 800b93c: 2b00 cmp r3, #0 - 800b93e: d1e6 bne.n 800b90e + 800cd62: 6bfb ldr r3, [r7, #60] ; 0x3c + 800cd64: 2b00 cmp r3, #0 + 800cd66: d1e6 bne.n 800cd36 #endif /* USART_CR1_FIFOEN */ huart->gState = HAL_UART_STATE_READY; - 800b940: 687b ldr r3, [r7, #4] - 800b942: 2220 movs r2, #32 - 800b944: 67da str r2, [r3, #124] ; 0x7c + 800cd68: 687b ldr r3, [r7, #4] + 800cd6a: 2220 movs r2, #32 + 800cd6c: 67da str r2, [r3, #124] ; 0x7c __HAL_UNLOCK(huart); - 800b946: 687b ldr r3, [r7, #4] - 800b948: 2200 movs r2, #0 - 800b94a: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800cd6e: 687b ldr r3, [r7, #4] + 800cd70: 2200 movs r2, #0 + 800cd72: f883 2078 strb.w r2, [r3, #120] ; 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 800b94e: 2303 movs r3, #3 - 800b950: e062 b.n 800ba18 + 800cd76: 2303 movs r3, #3 + 800cd78: e062 b.n 800ce40 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 800b952: 687b ldr r3, [r7, #4] - 800b954: 681b ldr r3, [r3, #0] - 800b956: 681b ldr r3, [r3, #0] - 800b958: f003 0304 and.w r3, r3, #4 - 800b95c: 2b04 cmp r3, #4 - 800b95e: d149 bne.n 800b9f4 + 800cd7a: 687b ldr r3, [r7, #4] + 800cd7c: 681b ldr r3, [r3, #0] + 800cd7e: 681b ldr r3, [r3, #0] + 800cd80: f003 0304 and.w r3, r3, #4 + 800cd84: 2b04 cmp r3, #4 + 800cd86: d149 bne.n 800ce1c { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 800b960: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 800b964: 9300 str r3, [sp, #0] - 800b966: 6d7b ldr r3, [r7, #84] ; 0x54 - 800b968: 2200 movs r2, #0 - 800b96a: f44f 0180 mov.w r1, #4194304 ; 0x400000 - 800b96e: 6878 ldr r0, [r7, #4] - 800b970: f000 f856 bl 800ba20 - 800b974: 4603 mov r3, r0 - 800b976: 2b00 cmp r3, #0 - 800b978: d03c beq.n 800b9f4 + 800cd88: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 800cd8c: 9300 str r3, [sp, #0] + 800cd8e: 6d7b ldr r3, [r7, #84] ; 0x54 + 800cd90: 2200 movs r2, #0 + 800cd92: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 800cd96: 6878 ldr r0, [r7, #4] + 800cd98: f000 f856 bl 800ce48 + 800cd9c: 4603 mov r3, r0 + 800cd9e: 2b00 cmp r3, #0 + 800cda0: d03c beq.n 800ce1c /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 800b97a: 687b ldr r3, [r7, #4] - 800b97c: 681b ldr r3, [r3, #0] - 800b97e: 627b str r3, [r7, #36] ; 0x24 + 800cda2: 687b ldr r3, [r7, #4] + 800cda4: 681b ldr r3, [r3, #0] + 800cda6: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b980: 6a7b ldr r3, [r7, #36] ; 0x24 - 800b982: e853 3f00 ldrex r3, [r3] - 800b986: 623b str r3, [r7, #32] + 800cda8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800cdaa: e853 3f00 ldrex r3, [r3] + 800cdae: 623b str r3, [r7, #32] return(result); - 800b988: 6a3b ldr r3, [r7, #32] - 800b98a: f423 7390 bic.w r3, r3, #288 ; 0x120 - 800b98e: 64fb str r3, [r7, #76] ; 0x4c - 800b990: 687b ldr r3, [r7, #4] - 800b992: 681b ldr r3, [r3, #0] - 800b994: 461a mov r2, r3 - 800b996: 6cfb ldr r3, [r7, #76] ; 0x4c - 800b998: 633b str r3, [r7, #48] ; 0x30 - 800b99a: 62fa str r2, [r7, #44] ; 0x2c + 800cdb0: 6a3b ldr r3, [r7, #32] + 800cdb2: f423 7390 bic.w r3, r3, #288 ; 0x120 + 800cdb6: 64fb str r3, [r7, #76] ; 0x4c + 800cdb8: 687b ldr r3, [r7, #4] + 800cdba: 681b ldr r3, [r3, #0] + 800cdbc: 461a mov r2, r3 + 800cdbe: 6cfb ldr r3, [r7, #76] ; 0x4c + 800cdc0: 633b str r3, [r7, #48] ; 0x30 + 800cdc2: 62fa str r2, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b99c: 6af9 ldr r1, [r7, #44] ; 0x2c - 800b99e: 6b3a ldr r2, [r7, #48] ; 0x30 - 800b9a0: e841 2300 strex r3, r2, [r1] - 800b9a4: 62bb str r3, [r7, #40] ; 0x28 + 800cdc4: 6af9 ldr r1, [r7, #44] ; 0x2c + 800cdc6: 6b3a ldr r2, [r7, #48] ; 0x30 + 800cdc8: e841 2300 strex r3, r2, [r1] + 800cdcc: 62bb str r3, [r7, #40] ; 0x28 return(result); - 800b9a6: 6abb ldr r3, [r7, #40] ; 0x28 - 800b9a8: 2b00 cmp r3, #0 - 800b9aa: d1e6 bne.n 800b97a + 800cdce: 6abb ldr r3, [r7, #40] ; 0x28 + 800cdd0: 2b00 cmp r3, #0 + 800cdd2: d1e6 bne.n 800cda2 #endif /* USART_CR1_FIFOEN */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800b9ac: 687b ldr r3, [r7, #4] - 800b9ae: 681b ldr r3, [r3, #0] - 800b9b0: 3308 adds r3, #8 - 800b9b2: 613b str r3, [r7, #16] + 800cdd4: 687b ldr r3, [r7, #4] + 800cdd6: 681b ldr r3, [r3, #0] + 800cdd8: 3308 adds r3, #8 + 800cdda: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800b9b4: 693b ldr r3, [r7, #16] - 800b9b6: e853 3f00 ldrex r3, [r3] - 800b9ba: 60fb str r3, [r7, #12] + 800cddc: 693b ldr r3, [r7, #16] + 800cdde: e853 3f00 ldrex r3, [r3] + 800cde2: 60fb str r3, [r7, #12] return(result); - 800b9bc: 68fb ldr r3, [r7, #12] - 800b9be: f023 0301 bic.w r3, r3, #1 - 800b9c2: 64bb str r3, [r7, #72] ; 0x48 - 800b9c4: 687b ldr r3, [r7, #4] - 800b9c6: 681b ldr r3, [r3, #0] - 800b9c8: 3308 adds r3, #8 - 800b9ca: 6cba ldr r2, [r7, #72] ; 0x48 - 800b9cc: 61fa str r2, [r7, #28] - 800b9ce: 61bb str r3, [r7, #24] + 800cde4: 68fb ldr r3, [r7, #12] + 800cde6: f023 0301 bic.w r3, r3, #1 + 800cdea: 64bb str r3, [r7, #72] ; 0x48 + 800cdec: 687b ldr r3, [r7, #4] + 800cdee: 681b ldr r3, [r3, #0] + 800cdf0: 3308 adds r3, #8 + 800cdf2: 6cba ldr r2, [r7, #72] ; 0x48 + 800cdf4: 61fa str r2, [r7, #28] + 800cdf6: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800b9d0: 69b9 ldr r1, [r7, #24] - 800b9d2: 69fa ldr r2, [r7, #28] - 800b9d4: e841 2300 strex r3, r2, [r1] - 800b9d8: 617b str r3, [r7, #20] + 800cdf8: 69b9 ldr r1, [r7, #24] + 800cdfa: 69fa ldr r2, [r7, #28] + 800cdfc: e841 2300 strex r3, r2, [r1] + 800ce00: 617b str r3, [r7, #20] return(result); - 800b9da: 697b ldr r3, [r7, #20] - 800b9dc: 2b00 cmp r3, #0 - 800b9de: d1e5 bne.n 800b9ac + 800ce02: 697b ldr r3, [r7, #20] + 800ce04: 2b00 cmp r3, #0 + 800ce06: d1e5 bne.n 800cdd4 huart->RxState = HAL_UART_STATE_READY; - 800b9e0: 687b ldr r3, [r7, #4] - 800b9e2: 2220 movs r2, #32 - 800b9e4: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800ce08: 687b ldr r3, [r7, #4] + 800ce0a: 2220 movs r2, #32 + 800ce0c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 __HAL_UNLOCK(huart); - 800b9e8: 687b ldr r3, [r7, #4] - 800b9ea: 2200 movs r2, #0 - 800b9ec: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800ce10: 687b ldr r3, [r7, #4] + 800ce12: 2200 movs r2, #0 + 800ce14: f883 2078 strb.w r2, [r3, #120] ; 0x78 /* Timeout occurred */ return HAL_TIMEOUT; - 800b9f0: 2303 movs r3, #3 - 800b9f2: e011 b.n 800ba18 + 800ce18: 2303 movs r3, #3 + 800ce1a: e011 b.n 800ce40 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 800b9f4: 687b ldr r3, [r7, #4] - 800b9f6: 2220 movs r2, #32 - 800b9f8: 67da str r2, [r3, #124] ; 0x7c + 800ce1c: 687b ldr r3, [r7, #4] + 800ce1e: 2220 movs r2, #32 + 800ce20: 67da str r2, [r3, #124] ; 0x7c huart->RxState = HAL_UART_STATE_READY; - 800b9fa: 687b ldr r3, [r7, #4] - 800b9fc: 2220 movs r2, #32 - 800b9fe: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800ce22: 687b ldr r3, [r7, #4] + 800ce24: 2220 movs r2, #32 + 800ce26: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800ba02: 687b ldr r3, [r7, #4] - 800ba04: 2200 movs r2, #0 - 800ba06: 661a str r2, [r3, #96] ; 0x60 + 800ce2a: 687b ldr r3, [r7, #4] + 800ce2c: 2200 movs r2, #0 + 800ce2e: 661a str r2, [r3, #96] ; 0x60 huart->RxEventType = HAL_UART_RXEVENT_TC; - 800ba08: 687b ldr r3, [r7, #4] - 800ba0a: 2200 movs r2, #0 - 800ba0c: 665a str r2, [r3, #100] ; 0x64 + 800ce30: 687b ldr r3, [r7, #4] + 800ce32: 2200 movs r2, #0 + 800ce34: 665a str r2, [r3, #100] ; 0x64 __HAL_UNLOCK(huart); - 800ba0e: 687b ldr r3, [r7, #4] - 800ba10: 2200 movs r2, #0 - 800ba12: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800ce36: 687b ldr r3, [r7, #4] + 800ce38: 2200 movs r2, #0 + 800ce3a: f883 2078 strb.w r2, [r3, #120] ; 0x78 return HAL_OK; - 800ba16: 2300 movs r3, #0 + 800ce3e: 2300 movs r3, #0 } - 800ba18: 4618 mov r0, r3 - 800ba1a: 3758 adds r7, #88 ; 0x58 - 800ba1c: 46bd mov sp, r7 - 800ba1e: bd80 pop {r7, pc} + 800ce40: 4618 mov r0, r3 + 800ce42: 3758 adds r7, #88 ; 0x58 + 800ce44: 46bd mov sp, r7 + 800ce46: bd80 pop {r7, pc} -0800ba20 : +0800ce48 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 800ba20: b580 push {r7, lr} - 800ba22: b084 sub sp, #16 - 800ba24: af00 add r7, sp, #0 - 800ba26: 60f8 str r0, [r7, #12] - 800ba28: 60b9 str r1, [r7, #8] - 800ba2a: 603b str r3, [r7, #0] - 800ba2c: 4613 mov r3, r2 - 800ba2e: 71fb strb r3, [r7, #7] + 800ce48: b580 push {r7, lr} + 800ce4a: b084 sub sp, #16 + 800ce4c: af00 add r7, sp, #0 + 800ce4e: 60f8 str r0, [r7, #12] + 800ce50: 60b9 str r1, [r7, #8] + 800ce52: 603b str r3, [r7, #0] + 800ce54: 4613 mov r3, r2 + 800ce56: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800ba30: e049 b.n 800bac6 + 800ce58: e049 b.n 800ceee { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 800ba32: 69bb ldr r3, [r7, #24] - 800ba34: f1b3 3fff cmp.w r3, #4294967295 - 800ba38: d045 beq.n 800bac6 + 800ce5a: 69bb ldr r3, [r7, #24] + 800ce5c: f1b3 3fff cmp.w r3, #4294967295 + 800ce60: d045 beq.n 800ceee { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 800ba3a: f7f8 fdbf bl 80045bc - 800ba3e: 4602 mov r2, r0 - 800ba40: 683b ldr r3, [r7, #0] - 800ba42: 1ad3 subs r3, r2, r3 - 800ba44: 69ba ldr r2, [r7, #24] - 800ba46: 429a cmp r2, r3 - 800ba48: d302 bcc.n 800ba50 - 800ba4a: 69bb ldr r3, [r7, #24] - 800ba4c: 2b00 cmp r3, #0 - 800ba4e: d101 bne.n 800ba54 + 800ce62: f7f8 f9f5 bl 8005250 + 800ce66: 4602 mov r2, r0 + 800ce68: 683b ldr r3, [r7, #0] + 800ce6a: 1ad3 subs r3, r2, r3 + 800ce6c: 69ba ldr r2, [r7, #24] + 800ce6e: 429a cmp r2, r3 + 800ce70: d302 bcc.n 800ce78 + 800ce72: 69bb ldr r3, [r7, #24] + 800ce74: 2b00 cmp r3, #0 + 800ce76: d101 bne.n 800ce7c { return HAL_TIMEOUT; - 800ba50: 2303 movs r3, #3 - 800ba52: e048 b.n 800bae6 + 800ce78: 2303 movs r3, #3 + 800ce7a: e048 b.n 800cf0e } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - 800ba54: 68fb ldr r3, [r7, #12] - 800ba56: 681b ldr r3, [r3, #0] - 800ba58: 681b ldr r3, [r3, #0] - 800ba5a: f003 0304 and.w r3, r3, #4 - 800ba5e: 2b00 cmp r3, #0 - 800ba60: d031 beq.n 800bac6 + 800ce7c: 68fb ldr r3, [r7, #12] + 800ce7e: 681b ldr r3, [r3, #0] + 800ce80: 681b ldr r3, [r3, #0] + 800ce82: f003 0304 and.w r3, r3, #4 + 800ce86: 2b00 cmp r3, #0 + 800ce88: d031 beq.n 800ceee { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 800ba62: 68fb ldr r3, [r7, #12] - 800ba64: 681b ldr r3, [r3, #0] - 800ba66: 69db ldr r3, [r3, #28] - 800ba68: f003 0308 and.w r3, r3, #8 - 800ba6c: 2b08 cmp r3, #8 - 800ba6e: d110 bne.n 800ba92 + 800ce8a: 68fb ldr r3, [r7, #12] + 800ce8c: 681b ldr r3, [r3, #0] + 800ce8e: 69db ldr r3, [r3, #28] + 800ce90: f003 0308 and.w r3, r3, #8 + 800ce94: 2b08 cmp r3, #8 + 800ce96: d110 bne.n 800ceba { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 800ba70: 68fb ldr r3, [r7, #12] - 800ba72: 681b ldr r3, [r3, #0] - 800ba74: 2208 movs r2, #8 - 800ba76: 621a str r2, [r3, #32] + 800ce98: 68fb ldr r3, [r7, #12] + 800ce9a: 681b ldr r3, [r3, #0] + 800ce9c: 2208 movs r2, #8 + 800ce9e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 800ba78: 68f8 ldr r0, [r7, #12] - 800ba7a: f000 f8ff bl 800bc7c + 800cea0: 68f8 ldr r0, [r7, #12] + 800cea2: f000 f8ff bl 800d0a4 huart->ErrorCode = HAL_UART_ERROR_ORE; - 800ba7e: 68fb ldr r3, [r7, #12] - 800ba80: 2208 movs r2, #8 - 800ba82: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800cea6: 68fb ldr r3, [r7, #12] + 800cea8: 2208 movs r2, #8 + 800ceaa: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 800ba86: 68fb ldr r3, [r7, #12] - 800ba88: 2200 movs r2, #0 - 800ba8a: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800ceae: 68fb ldr r3, [r7, #12] + 800ceb0: 2200 movs r2, #0 + 800ceb2: f883 2078 strb.w r2, [r3, #120] ; 0x78 return HAL_ERROR; - 800ba8e: 2301 movs r3, #1 - 800ba90: e029 b.n 800bae6 + 800ceb6: 2301 movs r3, #1 + 800ceb8: e029 b.n 800cf0e } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 800ba92: 68fb ldr r3, [r7, #12] - 800ba94: 681b ldr r3, [r3, #0] - 800ba96: 69db ldr r3, [r3, #28] - 800ba98: f403 6300 and.w r3, r3, #2048 ; 0x800 - 800ba9c: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800baa0: d111 bne.n 800bac6 + 800ceba: 68fb ldr r3, [r7, #12] + 800cebc: 681b ldr r3, [r3, #0] + 800cebe: 69db ldr r3, [r3, #28] + 800cec0: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800cec4: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800cec8: d111 bne.n 800ceee { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 800baa2: 68fb ldr r3, [r7, #12] - 800baa4: 681b ldr r3, [r3, #0] - 800baa6: f44f 6200 mov.w r2, #2048 ; 0x800 - 800baaa: 621a str r2, [r3, #32] + 800ceca: 68fb ldr r3, [r7, #12] + 800cecc: 681b ldr r3, [r3, #0] + 800cece: f44f 6200 mov.w r2, #2048 ; 0x800 + 800ced2: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 800baac: 68f8 ldr r0, [r7, #12] - 800baae: f000 f8e5 bl 800bc7c + 800ced4: 68f8 ldr r0, [r7, #12] + 800ced6: f000 f8e5 bl 800d0a4 huart->ErrorCode = HAL_UART_ERROR_RTO; - 800bab2: 68fb ldr r3, [r7, #12] - 800bab4: 2220 movs r2, #32 - 800bab6: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800ceda: 68fb ldr r3, [r7, #12] + 800cedc: 2220 movs r2, #32 + 800cede: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Process Unlocked */ __HAL_UNLOCK(huart); - 800baba: 68fb ldr r3, [r7, #12] - 800babc: 2200 movs r2, #0 - 800babe: f883 2078 strb.w r2, [r3, #120] ; 0x78 + 800cee2: 68fb ldr r3, [r7, #12] + 800cee4: 2200 movs r2, #0 + 800cee6: f883 2078 strb.w r2, [r3, #120] ; 0x78 return HAL_TIMEOUT; - 800bac2: 2303 movs r3, #3 - 800bac4: e00f b.n 800bae6 + 800ceea: 2303 movs r3, #3 + 800ceec: e00f b.n 800cf0e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800bac6: 68fb ldr r3, [r7, #12] - 800bac8: 681b ldr r3, [r3, #0] - 800baca: 69da ldr r2, [r3, #28] - 800bacc: 68bb ldr r3, [r7, #8] - 800bace: 4013 ands r3, r2 - 800bad0: 68ba ldr r2, [r7, #8] - 800bad2: 429a cmp r2, r3 - 800bad4: bf0c ite eq - 800bad6: 2301 moveq r3, #1 - 800bad8: 2300 movne r3, #0 - 800bada: b2db uxtb r3, r3 - 800badc: 461a mov r2, r3 - 800bade: 79fb ldrb r3, [r7, #7] - 800bae0: 429a cmp r2, r3 - 800bae2: d0a6 beq.n 800ba32 + 800ceee: 68fb ldr r3, [r7, #12] + 800cef0: 681b ldr r3, [r3, #0] + 800cef2: 69da ldr r2, [r3, #28] + 800cef4: 68bb ldr r3, [r7, #8] + 800cef6: 4013 ands r3, r2 + 800cef8: 68ba ldr r2, [r7, #8] + 800cefa: 429a cmp r2, r3 + 800cefc: bf0c ite eq + 800cefe: 2301 moveq r3, #1 + 800cf00: 2300 movne r3, #0 + 800cf02: b2db uxtb r3, r3 + 800cf04: 461a mov r2, r3 + 800cf06: 79fb ldrb r3, [r7, #7] + 800cf08: 429a cmp r2, r3 + 800cf0a: d0a6 beq.n 800ce5a } } } } return HAL_OK; - 800bae4: 2300 movs r3, #0 + 800cf0c: 2300 movs r3, #0 } - 800bae6: 4618 mov r0, r3 - 800bae8: 3710 adds r7, #16 - 800baea: 46bd mov sp, r7 - 800baec: bd80 pop {r7, pc} + 800cf0e: 4618 mov r0, r3 + 800cf10: 3710 adds r7, #16 + 800cf12: 46bd mov sp, r7 + 800cf14: bd80 pop {r7, pc} ... -0800baf0 : +0800cf18 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 800baf0: b580 push {r7, lr} - 800baf2: b096 sub sp, #88 ; 0x58 - 800baf4: af00 add r7, sp, #0 - 800baf6: 60f8 str r0, [r7, #12] - 800baf8: 60b9 str r1, [r7, #8] - 800bafa: 4613 mov r3, r2 - 800bafc: 80fb strh r3, [r7, #6] + 800cf18: b580 push {r7, lr} + 800cf1a: b096 sub sp, #88 ; 0x58 + 800cf1c: af00 add r7, sp, #0 + 800cf1e: 60f8 str r0, [r7, #12] + 800cf20: 60b9 str r1, [r7, #8] + 800cf22: 4613 mov r3, r2 + 800cf24: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; - 800bafe: 68fb ldr r3, [r7, #12] - 800bb00: 68ba ldr r2, [r7, #8] - 800bb02: 655a str r2, [r3, #84] ; 0x54 + 800cf26: 68fb ldr r3, [r7, #12] + 800cf28: 68ba ldr r2, [r7, #8] + 800cf2a: 655a str r2, [r3, #84] ; 0x54 huart->RxXferSize = Size; - 800bb04: 68fb ldr r3, [r7, #12] - 800bb06: 88fa ldrh r2, [r7, #6] - 800bb08: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + 800cf2c: 68fb ldr r3, [r7, #12] + 800cf2e: 88fa ldrh r2, [r7, #6] + 800cf30: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 huart->ErrorCode = HAL_UART_ERROR_NONE; - 800bb0c: 68fb ldr r3, [r7, #12] - 800bb0e: 2200 movs r2, #0 - 800bb10: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800cf34: 68fb ldr r3, [r7, #12] + 800cf36: 2200 movs r2, #0 + 800cf38: f8c3 2084 str.w r2, [r3, #132] ; 0x84 huart->RxState = HAL_UART_STATE_BUSY_RX; - 800bb14: 68fb ldr r3, [r7, #12] - 800bb16: 2222 movs r2, #34 ; 0x22 - 800bb18: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800cf3c: 68fb ldr r3, [r7, #12] + 800cf3e: 2222 movs r2, #34 ; 0x22 + 800cf40: f8c3 2080 str.w r2, [r3, #128] ; 0x80 if (huart->hdmarx != NULL) - 800bb1c: 68fb ldr r3, [r7, #12] - 800bb1e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800bb20: 2b00 cmp r3, #0 - 800bb22: d028 beq.n 800bb76 + 800cf44: 68fb ldr r3, [r7, #12] + 800cf46: 6f5b ldr r3, [r3, #116] ; 0x74 + 800cf48: 2b00 cmp r3, #0 + 800cf4a: d028 beq.n 800cf9e { /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - 800bb24: 68fb ldr r3, [r7, #12] - 800bb26: 6f5b ldr r3, [r3, #116] ; 0x74 - 800bb28: 4a3e ldr r2, [pc, #248] ; (800bc24 ) - 800bb2a: 62da str r2, [r3, #44] ; 0x2c + 800cf4c: 68fb ldr r3, [r7, #12] + 800cf4e: 6f5b ldr r3, [r3, #116] ; 0x74 + 800cf50: 4a3e ldr r2, [pc, #248] ; (800d04c ) + 800cf52: 62da str r2, [r3, #44] ; 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - 800bb2c: 68fb ldr r3, [r7, #12] - 800bb2e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800bb30: 4a3d ldr r2, [pc, #244] ; (800bc28 ) - 800bb32: 631a str r2, [r3, #48] ; 0x30 + 800cf54: 68fb ldr r3, [r7, #12] + 800cf56: 6f5b ldr r3, [r3, #116] ; 0x74 + 800cf58: 4a3d ldr r2, [pc, #244] ; (800d050 ) + 800cf5a: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; - 800bb34: 68fb ldr r3, [r7, #12] - 800bb36: 6f5b ldr r3, [r3, #116] ; 0x74 - 800bb38: 4a3c ldr r2, [pc, #240] ; (800bc2c ) - 800bb3a: 635a str r2, [r3, #52] ; 0x34 + 800cf5c: 68fb ldr r3, [r7, #12] + 800cf5e: 6f5b ldr r3, [r3, #116] ; 0x74 + 800cf60: 4a3c ldr r2, [pc, #240] ; (800d054 ) + 800cf62: 635a str r2, [r3, #52] ; 0x34 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; - 800bb3c: 68fb ldr r3, [r7, #12] - 800bb3e: 6f5b ldr r3, [r3, #116] ; 0x74 - 800bb40: 2200 movs r2, #0 - 800bb42: 639a str r2, [r3, #56] ; 0x38 + 800cf64: 68fb ldr r3, [r7, #12] + 800cf66: 6f5b ldr r3, [r3, #116] ; 0x74 + 800cf68: 2200 movs r2, #0 + 800cf6a: 639a str r2, [r3, #56] ; 0x38 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) - 800bb44: 68fb ldr r3, [r7, #12] - 800bb46: 6f58 ldr r0, [r3, #116] ; 0x74 - 800bb48: 68fb ldr r3, [r7, #12] - 800bb4a: 681b ldr r3, [r3, #0] - 800bb4c: 3324 adds r3, #36 ; 0x24 - 800bb4e: 4619 mov r1, r3 - 800bb50: 68fb ldr r3, [r7, #12] - 800bb52: 6d5b ldr r3, [r3, #84] ; 0x54 - 800bb54: 461a mov r2, r3 - 800bb56: 88fb ldrh r3, [r7, #6] - 800bb58: f7fa fa8e bl 8006078 - 800bb5c: 4603 mov r3, r0 - 800bb5e: 2b00 cmp r3, #0 - 800bb60: d009 beq.n 800bb76 + 800cf6c: 68fb ldr r3, [r7, #12] + 800cf6e: 6f58 ldr r0, [r3, #116] ; 0x74 + 800cf70: 68fb ldr r3, [r7, #12] + 800cf72: 681b ldr r3, [r3, #0] + 800cf74: 3324 adds r3, #36 ; 0x24 + 800cf76: 4619 mov r1, r3 + 800cf78: 68fb ldr r3, [r7, #12] + 800cf7a: 6d5b ldr r3, [r3, #84] ; 0x54 + 800cf7c: 461a mov r2, r3 + 800cf7e: 88fb ldrh r3, [r7, #6] + 800cf80: f7f9 fe00 bl 8006b84 + 800cf84: 4603 mov r3, r0 + 800cf86: 2b00 cmp r3, #0 + 800cf88: d009 beq.n 800cf9e { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - 800bb62: 68fb ldr r3, [r7, #12] - 800bb64: 2210 movs r2, #16 - 800bb66: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 800cf8a: 68fb ldr r3, [r7, #12] + 800cf8c: 2210 movs r2, #16 + 800cf8e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; - 800bb6a: 68fb ldr r3, [r7, #12] - 800bb6c: 2220 movs r2, #32 - 800bb6e: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800cf92: 68fb ldr r3, [r7, #12] + 800cf94: 2220 movs r2, #32 + 800cf96: f8c3 2080 str.w r2, [r3, #128] ; 0x80 return HAL_ERROR; - 800bb72: 2301 movs r3, #1 - 800bb74: e051 b.n 800bc1a + 800cf9a: 2301 movs r3, #1 + 800cf9c: e051 b.n 800d042 } } /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) - 800bb76: 68fb ldr r3, [r7, #12] - 800bb78: 691b ldr r3, [r3, #16] - 800bb7a: 2b00 cmp r3, #0 - 800bb7c: d018 beq.n 800bbb0 + 800cf9e: 68fb ldr r3, [r7, #12] + 800cfa0: 691b ldr r3, [r3, #16] + 800cfa2: 2b00 cmp r3, #0 + 800cfa4: d018 beq.n 800cfd8 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 800bb7e: 68fb ldr r3, [r7, #12] - 800bb80: 681b ldr r3, [r3, #0] - 800bb82: 63fb str r3, [r7, #60] ; 0x3c + 800cfa6: 68fb ldr r3, [r7, #12] + 800cfa8: 681b ldr r3, [r3, #0] + 800cfaa: 63fb str r3, [r7, #60] ; 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bb84: 6bfb ldr r3, [r7, #60] ; 0x3c - 800bb86: e853 3f00 ldrex r3, [r3] - 800bb8a: 63bb str r3, [r7, #56] ; 0x38 + 800cfac: 6bfb ldr r3, [r7, #60] ; 0x3c + 800cfae: e853 3f00 ldrex r3, [r3] + 800cfb2: 63bb str r3, [r7, #56] ; 0x38 return(result); - 800bb8c: 6bbb ldr r3, [r7, #56] ; 0x38 - 800bb8e: f443 7380 orr.w r3, r3, #256 ; 0x100 - 800bb92: 657b str r3, [r7, #84] ; 0x54 - 800bb94: 68fb ldr r3, [r7, #12] - 800bb96: 681b ldr r3, [r3, #0] - 800bb98: 461a mov r2, r3 - 800bb9a: 6d7b ldr r3, [r7, #84] ; 0x54 - 800bb9c: 64bb str r3, [r7, #72] ; 0x48 - 800bb9e: 647a str r2, [r7, #68] ; 0x44 + 800cfb4: 6bbb ldr r3, [r7, #56] ; 0x38 + 800cfb6: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800cfba: 657b str r3, [r7, #84] ; 0x54 + 800cfbc: 68fb ldr r3, [r7, #12] + 800cfbe: 681b ldr r3, [r3, #0] + 800cfc0: 461a mov r2, r3 + 800cfc2: 6d7b ldr r3, [r7, #84] ; 0x54 + 800cfc4: 64bb str r3, [r7, #72] ; 0x48 + 800cfc6: 647a str r2, [r7, #68] ; 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bba0: 6c79 ldr r1, [r7, #68] ; 0x44 - 800bba2: 6cba ldr r2, [r7, #72] ; 0x48 - 800bba4: e841 2300 strex r3, r2, [r1] - 800bba8: 643b str r3, [r7, #64] ; 0x40 + 800cfc8: 6c79 ldr r1, [r7, #68] ; 0x44 + 800cfca: 6cba ldr r2, [r7, #72] ; 0x48 + 800cfcc: e841 2300 strex r3, r2, [r1] + 800cfd0: 643b str r3, [r7, #64] ; 0x40 return(result); - 800bbaa: 6c3b ldr r3, [r7, #64] ; 0x40 - 800bbac: 2b00 cmp r3, #0 - 800bbae: d1e6 bne.n 800bb7e + 800cfd2: 6c3b ldr r3, [r7, #64] ; 0x40 + 800cfd4: 2b00 cmp r3, #0 + 800cfd6: d1e6 bne.n 800cfa6 } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800bbb0: 68fb ldr r3, [r7, #12] - 800bbb2: 681b ldr r3, [r3, #0] - 800bbb4: 3308 adds r3, #8 - 800bbb6: 62bb str r3, [r7, #40] ; 0x28 + 800cfd8: 68fb ldr r3, [r7, #12] + 800cfda: 681b ldr r3, [r3, #0] + 800cfdc: 3308 adds r3, #8 + 800cfde: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bbb8: 6abb ldr r3, [r7, #40] ; 0x28 - 800bbba: e853 3f00 ldrex r3, [r3] - 800bbbe: 627b str r3, [r7, #36] ; 0x24 + 800cfe0: 6abb ldr r3, [r7, #40] ; 0x28 + 800cfe2: e853 3f00 ldrex r3, [r3] + 800cfe6: 627b str r3, [r7, #36] ; 0x24 return(result); - 800bbc0: 6a7b ldr r3, [r7, #36] ; 0x24 - 800bbc2: f043 0301 orr.w r3, r3, #1 - 800bbc6: 653b str r3, [r7, #80] ; 0x50 - 800bbc8: 68fb ldr r3, [r7, #12] - 800bbca: 681b ldr r3, [r3, #0] - 800bbcc: 3308 adds r3, #8 - 800bbce: 6d3a ldr r2, [r7, #80] ; 0x50 - 800bbd0: 637a str r2, [r7, #52] ; 0x34 - 800bbd2: 633b str r3, [r7, #48] ; 0x30 + 800cfe8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800cfea: f043 0301 orr.w r3, r3, #1 + 800cfee: 653b str r3, [r7, #80] ; 0x50 + 800cff0: 68fb ldr r3, [r7, #12] + 800cff2: 681b ldr r3, [r3, #0] + 800cff4: 3308 adds r3, #8 + 800cff6: 6d3a ldr r2, [r7, #80] ; 0x50 + 800cff8: 637a str r2, [r7, #52] ; 0x34 + 800cffa: 633b str r3, [r7, #48] ; 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bbd4: 6b39 ldr r1, [r7, #48] ; 0x30 - 800bbd6: 6b7a ldr r2, [r7, #52] ; 0x34 - 800bbd8: e841 2300 strex r3, r2, [r1] - 800bbdc: 62fb str r3, [r7, #44] ; 0x2c + 800cffc: 6b39 ldr r1, [r7, #48] ; 0x30 + 800cffe: 6b7a ldr r2, [r7, #52] ; 0x34 + 800d000: e841 2300 strex r3, r2, [r1] + 800d004: 62fb str r3, [r7, #44] ; 0x2c return(result); - 800bbde: 6afb ldr r3, [r7, #44] ; 0x2c - 800bbe0: 2b00 cmp r3, #0 - 800bbe2: d1e5 bne.n 800bbb0 + 800d006: 6afb ldr r3, [r7, #44] ; 0x2c + 800d008: 2b00 cmp r3, #0 + 800d00a: d1e5 bne.n 800cfd8 /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 800bbe4: 68fb ldr r3, [r7, #12] - 800bbe6: 681b ldr r3, [r3, #0] - 800bbe8: 3308 adds r3, #8 - 800bbea: 617b str r3, [r7, #20] + 800d00c: 68fb ldr r3, [r7, #12] + 800d00e: 681b ldr r3, [r3, #0] + 800d010: 3308 adds r3, #8 + 800d012: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bbec: 697b ldr r3, [r7, #20] - 800bbee: e853 3f00 ldrex r3, [r3] - 800bbf2: 613b str r3, [r7, #16] + 800d014: 697b ldr r3, [r7, #20] + 800d016: e853 3f00 ldrex r3, [r3] + 800d01a: 613b str r3, [r7, #16] return(result); - 800bbf4: 693b ldr r3, [r7, #16] - 800bbf6: f043 0340 orr.w r3, r3, #64 ; 0x40 - 800bbfa: 64fb str r3, [r7, #76] ; 0x4c - 800bbfc: 68fb ldr r3, [r7, #12] - 800bbfe: 681b ldr r3, [r3, #0] - 800bc00: 3308 adds r3, #8 - 800bc02: 6cfa ldr r2, [r7, #76] ; 0x4c - 800bc04: 623a str r2, [r7, #32] - 800bc06: 61fb str r3, [r7, #28] + 800d01c: 693b ldr r3, [r7, #16] + 800d01e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800d022: 64fb str r3, [r7, #76] ; 0x4c + 800d024: 68fb ldr r3, [r7, #12] + 800d026: 681b ldr r3, [r3, #0] + 800d028: 3308 adds r3, #8 + 800d02a: 6cfa ldr r2, [r7, #76] ; 0x4c + 800d02c: 623a str r2, [r7, #32] + 800d02e: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bc08: 69f9 ldr r1, [r7, #28] - 800bc0a: 6a3a ldr r2, [r7, #32] - 800bc0c: e841 2300 strex r3, r2, [r1] - 800bc10: 61bb str r3, [r7, #24] + 800d030: 69f9 ldr r1, [r7, #28] + 800d032: 6a3a ldr r2, [r7, #32] + 800d034: e841 2300 strex r3, r2, [r1] + 800d038: 61bb str r3, [r7, #24] return(result); - 800bc12: 69bb ldr r3, [r7, #24] - 800bc14: 2b00 cmp r3, #0 - 800bc16: d1e5 bne.n 800bbe4 + 800d03a: 69bb ldr r3, [r7, #24] + 800d03c: 2b00 cmp r3, #0 + 800d03e: d1e5 bne.n 800d00c return HAL_OK; - 800bc18: 2300 movs r3, #0 -} - 800bc1a: 4618 mov r0, r3 - 800bc1c: 3758 adds r7, #88 ; 0x58 - 800bc1e: 46bd mov sp, r7 - 800bc20: bd80 pop {r7, pc} - 800bc22: bf00 nop - 800bc24: 0800bd45 .word 0x0800bd45 - 800bc28: 0800be71 .word 0x0800be71 - 800bc2c: 0800beaf .word 0x0800beaf - -0800bc30 : + 800d040: 2300 movs r3, #0 +} + 800d042: 4618 mov r0, r3 + 800d044: 3758 adds r7, #88 ; 0x58 + 800d046: 46bd mov sp, r7 + 800d048: bd80 pop {r7, pc} + 800d04a: bf00 nop + 800d04c: 0800d16d .word 0x0800d16d + 800d050: 0800d299 .word 0x0800d299 + 800d054: 0800d2d7 .word 0x0800d2d7 + +0800d058 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { - 800bc30: b480 push {r7} - 800bc32: b089 sub sp, #36 ; 0x24 - 800bc34: af00 add r7, sp, #0 - 800bc36: 6078 str r0, [r7, #4] + 800d058: b480 push {r7} + 800d05a: b089 sub sp, #36 ; 0x24 + 800d05c: af00 add r7, sp, #0 + 800d05e: 6078 str r0, [r7, #4] /* Disable TXEIE, TCIE, TXFT interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); #else /* Disable TXEIE and TCIE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - 800bc38: 687b ldr r3, [r7, #4] - 800bc3a: 681b ldr r3, [r3, #0] - 800bc3c: 60fb str r3, [r7, #12] + 800d060: 687b ldr r3, [r7, #4] + 800d062: 681b ldr r3, [r3, #0] + 800d064: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bc3e: 68fb ldr r3, [r7, #12] - 800bc40: e853 3f00 ldrex r3, [r3] - 800bc44: 60bb str r3, [r7, #8] + 800d066: 68fb ldr r3, [r7, #12] + 800d068: e853 3f00 ldrex r3, [r3] + 800d06c: 60bb str r3, [r7, #8] return(result); - 800bc46: 68bb ldr r3, [r7, #8] - 800bc48: f023 03c0 bic.w r3, r3, #192 ; 0xc0 - 800bc4c: 61fb str r3, [r7, #28] - 800bc4e: 687b ldr r3, [r7, #4] - 800bc50: 681b ldr r3, [r3, #0] - 800bc52: 461a mov r2, r3 - 800bc54: 69fb ldr r3, [r7, #28] - 800bc56: 61bb str r3, [r7, #24] - 800bc58: 617a str r2, [r7, #20] + 800d06e: 68bb ldr r3, [r7, #8] + 800d070: f023 03c0 bic.w r3, r3, #192 ; 0xc0 + 800d074: 61fb str r3, [r7, #28] + 800d076: 687b ldr r3, [r7, #4] + 800d078: 681b ldr r3, [r3, #0] + 800d07a: 461a mov r2, r3 + 800d07c: 69fb ldr r3, [r7, #28] + 800d07e: 61bb str r3, [r7, #24] + 800d080: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bc5a: 6979 ldr r1, [r7, #20] - 800bc5c: 69ba ldr r2, [r7, #24] - 800bc5e: e841 2300 strex r3, r2, [r1] - 800bc62: 613b str r3, [r7, #16] + 800d082: 6979 ldr r1, [r7, #20] + 800d084: 69ba ldr r2, [r7, #24] + 800d086: e841 2300 strex r3, r2, [r1] + 800d08a: 613b str r3, [r7, #16] return(result); - 800bc64: 693b ldr r3, [r7, #16] - 800bc66: 2b00 cmp r3, #0 - 800bc68: d1e6 bne.n 800bc38 + 800d08c: 693b ldr r3, [r7, #16] + 800d08e: 2b00 cmp r3, #0 + 800d090: d1e6 bne.n 800d060 #endif /* USART_CR1_FIFOEN */ /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 800bc6a: 687b ldr r3, [r7, #4] - 800bc6c: 2220 movs r2, #32 - 800bc6e: 67da str r2, [r3, #124] ; 0x7c + 800d092: 687b ldr r3, [r7, #4] + 800d094: 2220 movs r2, #32 + 800d096: 67da str r2, [r3, #124] ; 0x7c } - 800bc70: bf00 nop - 800bc72: 3724 adds r7, #36 ; 0x24 - 800bc74: 46bd mov sp, r7 - 800bc76: f85d 7b04 ldr.w r7, [sp], #4 - 800bc7a: 4770 bx lr + 800d098: bf00 nop + 800d09a: 3724 adds r7, #36 ; 0x24 + 800d09c: 46bd mov sp, r7 + 800d09e: f85d 7b04 ldr.w r7, [sp], #4 + 800d0a2: 4770 bx lr -0800bc7c : +0800d0a4 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 800bc7c: b480 push {r7} - 800bc7e: b095 sub sp, #84 ; 0x54 - 800bc80: af00 add r7, sp, #0 - 800bc82: 6078 str r0, [r7, #4] + 800d0a4: b480 push {r7} + 800d0a6: b095 sub sp, #84 ; 0x54 + 800d0a8: af00 add r7, sp, #0 + 800d0aa: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ #if defined(USART_CR1_FIFOEN) ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); #else ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - 800bc84: 687b ldr r3, [r7, #4] - 800bc86: 681b ldr r3, [r3, #0] - 800bc88: 637b str r3, [r7, #52] ; 0x34 + 800d0ac: 687b ldr r3, [r7, #4] + 800d0ae: 681b ldr r3, [r3, #0] + 800d0b0: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bc8a: 6b7b ldr r3, [r7, #52] ; 0x34 - 800bc8c: e853 3f00 ldrex r3, [r3] - 800bc90: 633b str r3, [r7, #48] ; 0x30 + 800d0b2: 6b7b ldr r3, [r7, #52] ; 0x34 + 800d0b4: e853 3f00 ldrex r3, [r3] + 800d0b8: 633b str r3, [r7, #48] ; 0x30 return(result); - 800bc92: 6b3b ldr r3, [r7, #48] ; 0x30 - 800bc94: f423 7390 bic.w r3, r3, #288 ; 0x120 - 800bc98: 64fb str r3, [r7, #76] ; 0x4c - 800bc9a: 687b ldr r3, [r7, #4] - 800bc9c: 681b ldr r3, [r3, #0] - 800bc9e: 461a mov r2, r3 - 800bca0: 6cfb ldr r3, [r7, #76] ; 0x4c - 800bca2: 643b str r3, [r7, #64] ; 0x40 - 800bca4: 63fa str r2, [r7, #60] ; 0x3c + 800d0ba: 6b3b ldr r3, [r7, #48] ; 0x30 + 800d0bc: f423 7390 bic.w r3, r3, #288 ; 0x120 + 800d0c0: 64fb str r3, [r7, #76] ; 0x4c + 800d0c2: 687b ldr r3, [r7, #4] + 800d0c4: 681b ldr r3, [r3, #0] + 800d0c6: 461a mov r2, r3 + 800d0c8: 6cfb ldr r3, [r7, #76] ; 0x4c + 800d0ca: 643b str r3, [r7, #64] ; 0x40 + 800d0cc: 63fa str r2, [r7, #60] ; 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bca6: 6bf9 ldr r1, [r7, #60] ; 0x3c - 800bca8: 6c3a ldr r2, [r7, #64] ; 0x40 - 800bcaa: e841 2300 strex r3, r2, [r1] - 800bcae: 63bb str r3, [r7, #56] ; 0x38 + 800d0ce: 6bf9 ldr r1, [r7, #60] ; 0x3c + 800d0d0: 6c3a ldr r2, [r7, #64] ; 0x40 + 800d0d2: e841 2300 strex r3, r2, [r1] + 800d0d6: 63bb str r3, [r7, #56] ; 0x38 return(result); - 800bcb0: 6bbb ldr r3, [r7, #56] ; 0x38 - 800bcb2: 2b00 cmp r3, #0 - 800bcb4: d1e6 bne.n 800bc84 + 800d0d8: 6bbb ldr r3, [r7, #56] ; 0x38 + 800d0da: 2b00 cmp r3, #0 + 800d0dc: d1e6 bne.n 800d0ac ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800bcb6: 687b ldr r3, [r7, #4] - 800bcb8: 681b ldr r3, [r3, #0] - 800bcba: 3308 adds r3, #8 - 800bcbc: 623b str r3, [r7, #32] + 800d0de: 687b ldr r3, [r7, #4] + 800d0e0: 681b ldr r3, [r3, #0] + 800d0e2: 3308 adds r3, #8 + 800d0e4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bcbe: 6a3b ldr r3, [r7, #32] - 800bcc0: e853 3f00 ldrex r3, [r3] - 800bcc4: 61fb str r3, [r7, #28] + 800d0e6: 6a3b ldr r3, [r7, #32] + 800d0e8: e853 3f00 ldrex r3, [r3] + 800d0ec: 61fb str r3, [r7, #28] return(result); - 800bcc6: 69fb ldr r3, [r7, #28] - 800bcc8: f023 0301 bic.w r3, r3, #1 - 800bccc: 64bb str r3, [r7, #72] ; 0x48 - 800bcce: 687b ldr r3, [r7, #4] - 800bcd0: 681b ldr r3, [r3, #0] - 800bcd2: 3308 adds r3, #8 - 800bcd4: 6cba ldr r2, [r7, #72] ; 0x48 - 800bcd6: 62fa str r2, [r7, #44] ; 0x2c - 800bcd8: 62bb str r3, [r7, #40] ; 0x28 + 800d0ee: 69fb ldr r3, [r7, #28] + 800d0f0: f023 0301 bic.w r3, r3, #1 + 800d0f4: 64bb str r3, [r7, #72] ; 0x48 + 800d0f6: 687b ldr r3, [r7, #4] + 800d0f8: 681b ldr r3, [r3, #0] + 800d0fa: 3308 adds r3, #8 + 800d0fc: 6cba ldr r2, [r7, #72] ; 0x48 + 800d0fe: 62fa str r2, [r7, #44] ; 0x2c + 800d100: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bcda: 6ab9 ldr r1, [r7, #40] ; 0x28 - 800bcdc: 6afa ldr r2, [r7, #44] ; 0x2c - 800bcde: e841 2300 strex r3, r2, [r1] - 800bce2: 627b str r3, [r7, #36] ; 0x24 + 800d102: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800d104: 6afa ldr r2, [r7, #44] ; 0x2c + 800d106: e841 2300 strex r3, r2, [r1] + 800d10a: 627b str r3, [r7, #36] ; 0x24 return(result); - 800bce4: 6a7b ldr r3, [r7, #36] ; 0x24 - 800bce6: 2b00 cmp r3, #0 - 800bce8: d1e5 bne.n 800bcb6 + 800d10c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d10e: 2b00 cmp r3, #0 + 800d110: d1e5 bne.n 800d0de #endif /* USART_CR1_FIFOEN */ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800bcea: 687b ldr r3, [r7, #4] - 800bcec: 6e1b ldr r3, [r3, #96] ; 0x60 - 800bcee: 2b01 cmp r3, #1 - 800bcf0: d118 bne.n 800bd24 + 800d112: 687b ldr r3, [r7, #4] + 800d114: 6e1b ldr r3, [r3, #96] ; 0x60 + 800d116: 2b01 cmp r3, #1 + 800d118: d118 bne.n 800d14c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 800bcf2: 687b ldr r3, [r7, #4] - 800bcf4: 681b ldr r3, [r3, #0] - 800bcf6: 60fb str r3, [r7, #12] + 800d11a: 687b ldr r3, [r7, #4] + 800d11c: 681b ldr r3, [r3, #0] + 800d11e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bcf8: 68fb ldr r3, [r7, #12] - 800bcfa: e853 3f00 ldrex r3, [r3] - 800bcfe: 60bb str r3, [r7, #8] + 800d120: 68fb ldr r3, [r7, #12] + 800d122: e853 3f00 ldrex r3, [r3] + 800d126: 60bb str r3, [r7, #8] return(result); - 800bd00: 68bb ldr r3, [r7, #8] - 800bd02: f023 0310 bic.w r3, r3, #16 - 800bd06: 647b str r3, [r7, #68] ; 0x44 - 800bd08: 687b ldr r3, [r7, #4] - 800bd0a: 681b ldr r3, [r3, #0] - 800bd0c: 461a mov r2, r3 - 800bd0e: 6c7b ldr r3, [r7, #68] ; 0x44 - 800bd10: 61bb str r3, [r7, #24] - 800bd12: 617a str r2, [r7, #20] + 800d128: 68bb ldr r3, [r7, #8] + 800d12a: f023 0310 bic.w r3, r3, #16 + 800d12e: 647b str r3, [r7, #68] ; 0x44 + 800d130: 687b ldr r3, [r7, #4] + 800d132: 681b ldr r3, [r3, #0] + 800d134: 461a mov r2, r3 + 800d136: 6c7b ldr r3, [r7, #68] ; 0x44 + 800d138: 61bb str r3, [r7, #24] + 800d13a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bd14: 6979 ldr r1, [r7, #20] - 800bd16: 69ba ldr r2, [r7, #24] - 800bd18: e841 2300 strex r3, r2, [r1] - 800bd1c: 613b str r3, [r7, #16] + 800d13c: 6979 ldr r1, [r7, #20] + 800d13e: 69ba ldr r2, [r7, #24] + 800d140: e841 2300 strex r3, r2, [r1] + 800d144: 613b str r3, [r7, #16] return(result); - 800bd1e: 693b ldr r3, [r7, #16] - 800bd20: 2b00 cmp r3, #0 - 800bd22: d1e6 bne.n 800bcf2 + 800d146: 693b ldr r3, [r7, #16] + 800d148: 2b00 cmp r3, #0 + 800d14a: d1e6 bne.n 800d11a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800bd24: 687b ldr r3, [r7, #4] - 800bd26: 2220 movs r2, #32 - 800bd28: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800d14c: 687b ldr r3, [r7, #4] + 800d14e: 2220 movs r2, #32 + 800d150: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 800bd2c: 687b ldr r3, [r7, #4] - 800bd2e: 2200 movs r2, #0 - 800bd30: 661a str r2, [r3, #96] ; 0x60 + 800d154: 687b ldr r3, [r7, #4] + 800d156: 2200 movs r2, #0 + 800d158: 661a str r2, [r3, #96] ; 0x60 /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 800bd32: 687b ldr r3, [r7, #4] - 800bd34: 2200 movs r2, #0 - 800bd36: 669a str r2, [r3, #104] ; 0x68 + 800d15a: 687b ldr r3, [r7, #4] + 800d15c: 2200 movs r2, #0 + 800d15e: 669a str r2, [r3, #104] ; 0x68 } - 800bd38: bf00 nop - 800bd3a: 3754 adds r7, #84 ; 0x54 - 800bd3c: 46bd mov sp, r7 - 800bd3e: f85d 7b04 ldr.w r7, [sp], #4 - 800bd42: 4770 bx lr + 800d160: bf00 nop + 800d162: 3754 adds r7, #84 ; 0x54 + 800d164: 46bd mov sp, r7 + 800d166: f85d 7b04 ldr.w r7, [sp], #4 + 800d16a: 4770 bx lr -0800bd44 : +0800d16c : * @brief DMA UART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - 800bd44: b580 push {r7, lr} - 800bd46: b09c sub sp, #112 ; 0x70 - 800bd48: af00 add r7, sp, #0 - 800bd4a: 6078 str r0, [r7, #4] + 800d16c: b580 push {r7, lr} + 800d16e: b09c sub sp, #112 ; 0x70 + 800d170: af00 add r7, sp, #0 + 800d172: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 800bd4c: 687b ldr r3, [r7, #4] - 800bd4e: 6a9b ldr r3, [r3, #40] ; 0x28 - 800bd50: 66fb str r3, [r7, #108] ; 0x6c + 800d174: 687b ldr r3, [r7, #4] + 800d176: 6a9b ldr r3, [r3, #40] ; 0x28 + 800d178: 66fb str r3, [r7, #108] ; 0x6c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) - 800bd52: 687b ldr r3, [r7, #4] - 800bd54: 681b ldr r3, [r3, #0] - 800bd56: 681b ldr r3, [r3, #0] - 800bd58: f003 0320 and.w r3, r3, #32 - 800bd5c: 2b00 cmp r3, #0 - 800bd5e: d171 bne.n 800be44 + 800d17a: 687b ldr r3, [r7, #4] + 800d17c: 681b ldr r3, [r3, #0] + 800d17e: 681b ldr r3, [r3, #0] + 800d180: f003 0320 and.w r3, r3, #32 + 800d184: 2b00 cmp r3, #0 + 800d186: d171 bne.n 800d26c { huart->RxXferCount = 0U; - 800bd60: 6efb ldr r3, [r7, #108] ; 0x6c - 800bd62: 2200 movs r2, #0 - 800bd64: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 800d188: 6efb ldr r3, [r7, #108] ; 0x6c + 800d18a: 2200 movs r2, #0 + 800d18c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 800bd68: 6efb ldr r3, [r7, #108] ; 0x6c - 800bd6a: 681b ldr r3, [r3, #0] - 800bd6c: 64fb str r3, [r7, #76] ; 0x4c + 800d190: 6efb ldr r3, [r7, #108] ; 0x6c + 800d192: 681b ldr r3, [r3, #0] + 800d194: 64fb str r3, [r7, #76] ; 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bd6e: 6cfb ldr r3, [r7, #76] ; 0x4c - 800bd70: e853 3f00 ldrex r3, [r3] - 800bd74: 64bb str r3, [r7, #72] ; 0x48 + 800d196: 6cfb ldr r3, [r7, #76] ; 0x4c + 800d198: e853 3f00 ldrex r3, [r3] + 800d19c: 64bb str r3, [r7, #72] ; 0x48 return(result); - 800bd76: 6cbb ldr r3, [r7, #72] ; 0x48 - 800bd78: f423 7380 bic.w r3, r3, #256 ; 0x100 - 800bd7c: 66bb str r3, [r7, #104] ; 0x68 - 800bd7e: 6efb ldr r3, [r7, #108] ; 0x6c - 800bd80: 681b ldr r3, [r3, #0] - 800bd82: 461a mov r2, r3 - 800bd84: 6ebb ldr r3, [r7, #104] ; 0x68 - 800bd86: 65bb str r3, [r7, #88] ; 0x58 - 800bd88: 657a str r2, [r7, #84] ; 0x54 + 800d19e: 6cbb ldr r3, [r7, #72] ; 0x48 + 800d1a0: f423 7380 bic.w r3, r3, #256 ; 0x100 + 800d1a4: 66bb str r3, [r7, #104] ; 0x68 + 800d1a6: 6efb ldr r3, [r7, #108] ; 0x6c + 800d1a8: 681b ldr r3, [r3, #0] + 800d1aa: 461a mov r2, r3 + 800d1ac: 6ebb ldr r3, [r7, #104] ; 0x68 + 800d1ae: 65bb str r3, [r7, #88] ; 0x58 + 800d1b0: 657a str r2, [r7, #84] ; 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bd8a: 6d79 ldr r1, [r7, #84] ; 0x54 - 800bd8c: 6dba ldr r2, [r7, #88] ; 0x58 - 800bd8e: e841 2300 strex r3, r2, [r1] - 800bd92: 653b str r3, [r7, #80] ; 0x50 + 800d1b2: 6d79 ldr r1, [r7, #84] ; 0x54 + 800d1b4: 6dba ldr r2, [r7, #88] ; 0x58 + 800d1b6: e841 2300 strex r3, r2, [r1] + 800d1ba: 653b str r3, [r7, #80] ; 0x50 return(result); - 800bd94: 6d3b ldr r3, [r7, #80] ; 0x50 - 800bd96: 2b00 cmp r3, #0 - 800bd98: d1e6 bne.n 800bd68 + 800d1bc: 6d3b ldr r3, [r7, #80] ; 0x50 + 800d1be: 2b00 cmp r3, #0 + 800d1c0: d1e6 bne.n 800d190 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800bd9a: 6efb ldr r3, [r7, #108] ; 0x6c - 800bd9c: 681b ldr r3, [r3, #0] - 800bd9e: 3308 adds r3, #8 - 800bda0: 63bb str r3, [r7, #56] ; 0x38 + 800d1c2: 6efb ldr r3, [r7, #108] ; 0x6c + 800d1c4: 681b ldr r3, [r3, #0] + 800d1c6: 3308 adds r3, #8 + 800d1c8: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bda2: 6bbb ldr r3, [r7, #56] ; 0x38 - 800bda4: e853 3f00 ldrex r3, [r3] - 800bda8: 637b str r3, [r7, #52] ; 0x34 + 800d1ca: 6bbb ldr r3, [r7, #56] ; 0x38 + 800d1cc: e853 3f00 ldrex r3, [r3] + 800d1d0: 637b str r3, [r7, #52] ; 0x34 return(result); - 800bdaa: 6b7b ldr r3, [r7, #52] ; 0x34 - 800bdac: f023 0301 bic.w r3, r3, #1 - 800bdb0: 667b str r3, [r7, #100] ; 0x64 - 800bdb2: 6efb ldr r3, [r7, #108] ; 0x6c - 800bdb4: 681b ldr r3, [r3, #0] - 800bdb6: 3308 adds r3, #8 - 800bdb8: 6e7a ldr r2, [r7, #100] ; 0x64 - 800bdba: 647a str r2, [r7, #68] ; 0x44 - 800bdbc: 643b str r3, [r7, #64] ; 0x40 + 800d1d2: 6b7b ldr r3, [r7, #52] ; 0x34 + 800d1d4: f023 0301 bic.w r3, r3, #1 + 800d1d8: 667b str r3, [r7, #100] ; 0x64 + 800d1da: 6efb ldr r3, [r7, #108] ; 0x6c + 800d1dc: 681b ldr r3, [r3, #0] + 800d1de: 3308 adds r3, #8 + 800d1e0: 6e7a ldr r2, [r7, #100] ; 0x64 + 800d1e2: 647a str r2, [r7, #68] ; 0x44 + 800d1e4: 643b str r3, [r7, #64] ; 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bdbe: 6c39 ldr r1, [r7, #64] ; 0x40 - 800bdc0: 6c7a ldr r2, [r7, #68] ; 0x44 - 800bdc2: e841 2300 strex r3, r2, [r1] - 800bdc6: 63fb str r3, [r7, #60] ; 0x3c + 800d1e6: 6c39 ldr r1, [r7, #64] ; 0x40 + 800d1e8: 6c7a ldr r2, [r7, #68] ; 0x44 + 800d1ea: e841 2300 strex r3, r2, [r1] + 800d1ee: 63fb str r3, [r7, #60] ; 0x3c return(result); - 800bdc8: 6bfb ldr r3, [r7, #60] ; 0x3c - 800bdca: 2b00 cmp r3, #0 - 800bdcc: d1e5 bne.n 800bd9a + 800d1f0: 6bfb ldr r3, [r7, #60] ; 0x3c + 800d1f2: 2b00 cmp r3, #0 + 800d1f4: d1e5 bne.n 800d1c2 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 800bdce: 6efb ldr r3, [r7, #108] ; 0x6c - 800bdd0: 681b ldr r3, [r3, #0] - 800bdd2: 3308 adds r3, #8 - 800bdd4: 627b str r3, [r7, #36] ; 0x24 + 800d1f6: 6efb ldr r3, [r7, #108] ; 0x6c + 800d1f8: 681b ldr r3, [r3, #0] + 800d1fa: 3308 adds r3, #8 + 800d1fc: 627b str r3, [r7, #36] ; 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bdd6: 6a7b ldr r3, [r7, #36] ; 0x24 - 800bdd8: e853 3f00 ldrex r3, [r3] - 800bddc: 623b str r3, [r7, #32] + 800d1fe: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d200: e853 3f00 ldrex r3, [r3] + 800d204: 623b str r3, [r7, #32] return(result); - 800bdde: 6a3b ldr r3, [r7, #32] - 800bde0: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800bde4: 663b str r3, [r7, #96] ; 0x60 - 800bde6: 6efb ldr r3, [r7, #108] ; 0x6c - 800bde8: 681b ldr r3, [r3, #0] - 800bdea: 3308 adds r3, #8 - 800bdec: 6e3a ldr r2, [r7, #96] ; 0x60 - 800bdee: 633a str r2, [r7, #48] ; 0x30 - 800bdf0: 62fb str r3, [r7, #44] ; 0x2c + 800d206: 6a3b ldr r3, [r7, #32] + 800d208: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800d20c: 663b str r3, [r7, #96] ; 0x60 + 800d20e: 6efb ldr r3, [r7, #108] ; 0x6c + 800d210: 681b ldr r3, [r3, #0] + 800d212: 3308 adds r3, #8 + 800d214: 6e3a ldr r2, [r7, #96] ; 0x60 + 800d216: 633a str r2, [r7, #48] ; 0x30 + 800d218: 62fb str r3, [r7, #44] ; 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bdf2: 6af9 ldr r1, [r7, #44] ; 0x2c - 800bdf4: 6b3a ldr r2, [r7, #48] ; 0x30 - 800bdf6: e841 2300 strex r3, r2, [r1] - 800bdfa: 62bb str r3, [r7, #40] ; 0x28 + 800d21a: 6af9 ldr r1, [r7, #44] ; 0x2c + 800d21c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800d21e: e841 2300 strex r3, r2, [r1] + 800d222: 62bb str r3, [r7, #40] ; 0x28 return(result); - 800bdfc: 6abb ldr r3, [r7, #40] ; 0x28 - 800bdfe: 2b00 cmp r3, #0 - 800be00: d1e5 bne.n 800bdce + 800d224: 6abb ldr r3, [r7, #40] ; 0x28 + 800d226: 2b00 cmp r3, #0 + 800d228: d1e5 bne.n 800d1f6 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800be02: 6efb ldr r3, [r7, #108] ; 0x6c - 800be04: 2220 movs r2, #32 - 800be06: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800d22a: 6efb ldr r3, [r7, #108] ; 0x6c + 800d22c: 2220 movs r2, #32 + 800d22e: f8c3 2080 str.w r2, [r3, #128] ; 0x80 /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800be0a: 6efb ldr r3, [r7, #108] ; 0x6c - 800be0c: 6e1b ldr r3, [r3, #96] ; 0x60 - 800be0e: 2b01 cmp r3, #1 - 800be10: d118 bne.n 800be44 + 800d232: 6efb ldr r3, [r7, #108] ; 0x6c + 800d234: 6e1b ldr r3, [r3, #96] ; 0x60 + 800d236: 2b01 cmp r3, #1 + 800d238: d118 bne.n 800d26c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 800be12: 6efb ldr r3, [r7, #108] ; 0x6c - 800be14: 681b ldr r3, [r3, #0] - 800be16: 613b str r3, [r7, #16] + 800d23a: 6efb ldr r3, [r7, #108] ; 0x6c + 800d23c: 681b ldr r3, [r3, #0] + 800d23e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800be18: 693b ldr r3, [r7, #16] - 800be1a: e853 3f00 ldrex r3, [r3] - 800be1e: 60fb str r3, [r7, #12] + 800d240: 693b ldr r3, [r7, #16] + 800d242: e853 3f00 ldrex r3, [r3] + 800d246: 60fb str r3, [r7, #12] return(result); - 800be20: 68fb ldr r3, [r7, #12] - 800be22: f023 0310 bic.w r3, r3, #16 - 800be26: 65fb str r3, [r7, #92] ; 0x5c - 800be28: 6efb ldr r3, [r7, #108] ; 0x6c - 800be2a: 681b ldr r3, [r3, #0] - 800be2c: 461a mov r2, r3 - 800be2e: 6dfb ldr r3, [r7, #92] ; 0x5c - 800be30: 61fb str r3, [r7, #28] - 800be32: 61ba str r2, [r7, #24] + 800d248: 68fb ldr r3, [r7, #12] + 800d24a: f023 0310 bic.w r3, r3, #16 + 800d24e: 65fb str r3, [r7, #92] ; 0x5c + 800d250: 6efb ldr r3, [r7, #108] ; 0x6c + 800d252: 681b ldr r3, [r3, #0] + 800d254: 461a mov r2, r3 + 800d256: 6dfb ldr r3, [r7, #92] ; 0x5c + 800d258: 61fb str r3, [r7, #28] + 800d25a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800be34: 69b9 ldr r1, [r7, #24] - 800be36: 69fa ldr r2, [r7, #28] - 800be38: e841 2300 strex r3, r2, [r1] - 800be3c: 617b str r3, [r7, #20] + 800d25c: 69b9 ldr r1, [r7, #24] + 800d25e: 69fa ldr r2, [r7, #28] + 800d260: e841 2300 strex r3, r2, [r1] + 800d264: 617b str r3, [r7, #20] return(result); - 800be3e: 697b ldr r3, [r7, #20] - 800be40: 2b00 cmp r3, #0 - 800be42: d1e6 bne.n 800be12 + 800d266: 697b ldr r3, [r7, #20] + 800d268: 2b00 cmp r3, #0 + 800d26a: d1e6 bne.n 800d23a } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 800be44: 6efb ldr r3, [r7, #108] ; 0x6c - 800be46: 2200 movs r2, #0 - 800be48: 665a str r2, [r3, #100] ; 0x64 + 800d26c: 6efb ldr r3, [r7, #108] ; 0x6c + 800d26e: 2200 movs r2, #0 + 800d270: 665a str r2, [r3, #100] ; 0x64 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800be4a: 6efb ldr r3, [r7, #108] ; 0x6c - 800be4c: 6e1b ldr r3, [r3, #96] ; 0x60 - 800be4e: 2b01 cmp r3, #1 - 800be50: d107 bne.n 800be62 + 800d272: 6efb ldr r3, [r7, #108] ; 0x6c + 800d274: 6e1b ldr r3, [r3, #96] ; 0x60 + 800d276: 2b01 cmp r3, #1 + 800d278: d107 bne.n 800d28a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 800be52: 6efb ldr r3, [r7, #108] ; 0x6c - 800be54: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 - 800be58: 4619 mov r1, r3 - 800be5a: 6ef8 ldr r0, [r7, #108] ; 0x6c - 800be5c: f7ff fa5e bl 800b31c + 800d27a: 6efb ldr r3, [r7, #108] ; 0x6c + 800d27c: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 + 800d280: 4619 mov r1, r3 + 800d282: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800d284: f7ff fa5e bl 800c744 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - 800be60: e002 b.n 800be68 + 800d288: e002 b.n 800d290 HAL_UART_RxCpltCallback(huart); - 800be62: 6ef8 ldr r0, [r7, #108] ; 0x6c - 800be64: f7f5 f8e6 bl 8001034 + 800d28a: 6ef8 ldr r0, [r7, #108] ; 0x6c + 800d28c: f7f7 fedc bl 8005048 } - 800be68: bf00 nop - 800be6a: 3770 adds r7, #112 ; 0x70 - 800be6c: 46bd mov sp, r7 - 800be6e: bd80 pop {r7, pc} + 800d290: bf00 nop + 800d292: 3770 adds r7, #112 ; 0x70 + 800d294: 46bd mov sp, r7 + 800d296: bd80 pop {r7, pc} -0800be70 : +0800d298 : * @brief DMA UART receive process half complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - 800be70: b580 push {r7, lr} - 800be72: b084 sub sp, #16 - 800be74: af00 add r7, sp, #0 - 800be76: 6078 str r0, [r7, #4] + 800d298: b580 push {r7, lr} + 800d29a: b084 sub sp, #16 + 800d29c: af00 add r7, sp, #0 + 800d29e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 800be78: 687b ldr r3, [r7, #4] - 800be7a: 6a9b ldr r3, [r3, #40] ; 0x28 - 800be7c: 60fb str r3, [r7, #12] + 800d2a0: 687b ldr r3, [r7, #4] + 800d2a2: 6a9b ldr r3, [r3, #40] ; 0x28 + 800d2a4: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; - 800be7e: 68fb ldr r3, [r7, #12] - 800be80: 2201 movs r2, #1 - 800be82: 665a str r2, [r3, #100] ; 0x64 + 800d2a6: 68fb ldr r3, [r7, #12] + 800d2a8: 2201 movs r2, #1 + 800d2aa: 665a str r2, [r3, #100] ; 0x64 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 800be84: 68fb ldr r3, [r7, #12] - 800be86: 6e1b ldr r3, [r3, #96] ; 0x60 - 800be88: 2b01 cmp r3, #1 - 800be8a: d109 bne.n 800bea0 + 800d2ac: 68fb ldr r3, [r7, #12] + 800d2ae: 6e1b ldr r3, [r3, #96] ; 0x60 + 800d2b0: 2b01 cmp r3, #1 + 800d2b2: d109 bne.n 800d2c8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); - 800be8c: 68fb ldr r3, [r7, #12] - 800be8e: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 - 800be92: 085b lsrs r3, r3, #1 - 800be94: b29b uxth r3, r3 - 800be96: 4619 mov r1, r3 - 800be98: 68f8 ldr r0, [r7, #12] - 800be9a: f7ff fa3f bl 800b31c + 800d2b4: 68fb ldr r3, [r7, #12] + 800d2b6: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 + 800d2ba: 085b lsrs r3, r3, #1 + 800d2bc: b29b uxth r3, r3 + 800d2be: 4619 mov r1, r3 + 800d2c0: 68f8 ldr r0, [r7, #12] + 800d2c2: f7ff fa3f bl 800c744 #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } - 800be9e: e002 b.n 800bea6 + 800d2c6: e002 b.n 800d2ce HAL_UART_RxHalfCpltCallback(huart); - 800bea0: 68f8 ldr r0, [r7, #12] - 800bea2: f7ff fa27 bl 800b2f4 + 800d2c8: 68f8 ldr r0, [r7, #12] + 800d2ca: f7ff fa27 bl 800c71c } - 800bea6: bf00 nop - 800bea8: 3710 adds r7, #16 - 800beaa: 46bd mov sp, r7 - 800beac: bd80 pop {r7, pc} + 800d2ce: bf00 nop + 800d2d0: 3710 adds r7, #16 + 800d2d2: 46bd mov sp, r7 + 800d2d4: bd80 pop {r7, pc} -0800beae : +0800d2d6 : * @brief DMA UART communication error callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { - 800beae: b580 push {r7, lr} - 800beb0: b086 sub sp, #24 - 800beb2: af00 add r7, sp, #0 - 800beb4: 6078 str r0, [r7, #4] + 800d2d6: b580 push {r7, lr} + 800d2d8: b086 sub sp, #24 + 800d2da: af00 add r7, sp, #0 + 800d2dc: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 800beb6: 687b ldr r3, [r7, #4] - 800beb8: 6a9b ldr r3, [r3, #40] ; 0x28 - 800beba: 617b str r3, [r7, #20] + 800d2de: 687b ldr r3, [r7, #4] + 800d2e0: 6a9b ldr r3, [r3, #40] ; 0x28 + 800d2e2: 617b str r3, [r7, #20] const HAL_UART_StateTypeDef gstate = huart->gState; - 800bebc: 697b ldr r3, [r7, #20] - 800bebe: 6fdb ldr r3, [r3, #124] ; 0x7c - 800bec0: 613b str r3, [r7, #16] + 800d2e4: 697b ldr r3, [r7, #20] + 800d2e6: 6fdb ldr r3, [r3, #124] ; 0x7c + 800d2e8: 613b str r3, [r7, #16] const HAL_UART_StateTypeDef rxstate = huart->RxState; - 800bec2: 697b ldr r3, [r7, #20] - 800bec4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 - 800bec8: 60fb str r3, [r7, #12] + 800d2ea: 697b ldr r3, [r7, #20] + 800d2ec: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 800d2f0: 60fb str r3, [r7, #12] /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - 800beca: 697b ldr r3, [r7, #20] - 800becc: 681b ldr r3, [r3, #0] - 800bece: 689b ldr r3, [r3, #8] - 800bed0: f003 0380 and.w r3, r3, #128 ; 0x80 - 800bed4: 2b80 cmp r3, #128 ; 0x80 - 800bed6: d109 bne.n 800beec - 800bed8: 693b ldr r3, [r7, #16] - 800beda: 2b21 cmp r3, #33 ; 0x21 - 800bedc: d106 bne.n 800beec + 800d2f2: 697b ldr r3, [r7, #20] + 800d2f4: 681b ldr r3, [r3, #0] + 800d2f6: 689b ldr r3, [r3, #8] + 800d2f8: f003 0380 and.w r3, r3, #128 ; 0x80 + 800d2fc: 2b80 cmp r3, #128 ; 0x80 + 800d2fe: d109 bne.n 800d314 + 800d300: 693b ldr r3, [r7, #16] + 800d302: 2b21 cmp r3, #33 ; 0x21 + 800d304: d106 bne.n 800d314 (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; - 800bede: 697b ldr r3, [r7, #20] - 800bee0: 2200 movs r2, #0 - 800bee2: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 800d306: 697b ldr r3, [r7, #20] + 800d308: 2200 movs r2, #0 + 800d30a: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 UART_EndTxTransfer(huart); - 800bee6: 6978 ldr r0, [r7, #20] - 800bee8: f7ff fea2 bl 800bc30 + 800d30e: 6978 ldr r0, [r7, #20] + 800d310: f7ff fea2 bl 800d058 } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - 800beec: 697b ldr r3, [r7, #20] - 800beee: 681b ldr r3, [r3, #0] - 800bef0: 689b ldr r3, [r3, #8] - 800bef2: f003 0340 and.w r3, r3, #64 ; 0x40 - 800bef6: 2b40 cmp r3, #64 ; 0x40 - 800bef8: d109 bne.n 800bf0e - 800befa: 68fb ldr r3, [r7, #12] - 800befc: 2b22 cmp r3, #34 ; 0x22 - 800befe: d106 bne.n 800bf0e + 800d314: 697b ldr r3, [r7, #20] + 800d316: 681b ldr r3, [r3, #0] + 800d318: 689b ldr r3, [r3, #8] + 800d31a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800d31e: 2b40 cmp r3, #64 ; 0x40 + 800d320: d109 bne.n 800d336 + 800d322: 68fb ldr r3, [r7, #12] + 800d324: 2b22 cmp r3, #34 ; 0x22 + 800d326: d106 bne.n 800d336 (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; - 800bf00: 697b ldr r3, [r7, #20] - 800bf02: 2200 movs r2, #0 - 800bf04: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 800d328: 697b ldr r3, [r7, #20] + 800d32a: 2200 movs r2, #0 + 800d32c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a UART_EndRxTransfer(huart); - 800bf08: 6978 ldr r0, [r7, #20] - 800bf0a: f7ff feb7 bl 800bc7c + 800d330: 6978 ldr r0, [r7, #20] + 800d332: f7ff feb7 bl 800d0a4 } huart->ErrorCode |= HAL_UART_ERROR_DMA; - 800bf0e: 697b ldr r3, [r7, #20] - 800bf10: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800bf14: f043 0210 orr.w r2, r3, #16 - 800bf18: 697b ldr r3, [r7, #20] - 800bf1a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 800bf1e: 6978 ldr r0, [r7, #20] - 800bf20: f7ff f9f2 bl 800b308 -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - 800bf24: bf00 nop - 800bf26: 3718 adds r7, #24 - 800bf28: 46bd mov sp, r7 - 800bf2a: bd80 pop {r7, pc} - -0800bf2c : - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - 800bf2c: b580 push {r7, lr} - 800bf2e: b084 sub sp, #16 - 800bf30: af00 add r7, sp, #0 - 800bf32: 6078 str r0, [r7, #4] - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 800bf34: 687b ldr r3, [r7, #4] - 800bf36: 6a9b ldr r3, [r3, #40] ; 0x28 - 800bf38: 60fb str r3, [r7, #12] - huart->RxXferCount = 0U; - 800bf3a: 68fb ldr r3, [r7, #12] - 800bf3c: 2200 movs r2, #0 - 800bf3e: f8a3 205a strh.w r2, [r3, #90] ; 0x5a - huart->TxXferCount = 0U; - 800bf42: 68fb ldr r3, [r7, #12] - 800bf44: 2200 movs r2, #0 - 800bf46: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 800d336: 697b ldr r3, [r7, #20] + 800d338: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800d33c: f043 0210 orr.w r2, r3, #16 + 800d340: 697b ldr r3, [r7, #20] + 800d342: f8c3 2084 str.w r2, [r3, #132] ; 0x84 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); - 800bf4a: 68f8 ldr r0, [r7, #12] - 800bf4c: f7ff f9dc bl 800b308 -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - 800bf50: bf00 nop - 800bf52: 3710 adds r7, #16 - 800bf54: 46bd mov sp, r7 - 800bf56: bd80 pop {r7, pc} - -0800bf58 : - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - 800bf58: b480 push {r7} - 800bf5a: b08f sub sp, #60 ; 0x3c - 800bf5c: af00 add r7, sp, #0 - 800bf5e: 6078 str r0, [r7, #4] - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - 800bf60: 687b ldr r3, [r7, #4] - 800bf62: 6fdb ldr r3, [r3, #124] ; 0x7c - 800bf64: 2b21 cmp r3, #33 ; 0x21 - 800bf66: d14d bne.n 800c004 - { - if (huart->TxXferCount == 0U) - 800bf68: 687b ldr r3, [r7, #4] - 800bf6a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 800bf6e: b29b uxth r3, r3 - 800bf70: 2b00 cmp r3, #0 - 800bf72: d132 bne.n 800bfda - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - 800bf74: 687b ldr r3, [r7, #4] - 800bf76: 681b ldr r3, [r3, #0] - 800bf78: 623b str r3, [r7, #32] - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bf7a: 6a3b ldr r3, [r7, #32] - 800bf7c: e853 3f00 ldrex r3, [r3] - 800bf80: 61fb str r3, [r7, #28] - return(result); - 800bf82: 69fb ldr r3, [r7, #28] - 800bf84: f023 0380 bic.w r3, r3, #128 ; 0x80 - 800bf88: 637b str r3, [r7, #52] ; 0x34 - 800bf8a: 687b ldr r3, [r7, #4] - 800bf8c: 681b ldr r3, [r3, #0] - 800bf8e: 461a mov r2, r3 - 800bf90: 6b7b ldr r3, [r7, #52] ; 0x34 - 800bf92: 62fb str r3, [r7, #44] ; 0x2c - 800bf94: 62ba str r2, [r7, #40] ; 0x28 - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bf96: 6ab9 ldr r1, [r7, #40] ; 0x28 - 800bf98: 6afa ldr r2, [r7, #44] ; 0x2c - 800bf9a: e841 2300 strex r3, r2, [r1] - 800bf9e: 627b str r3, [r7, #36] ; 0x24 - return(result); - 800bfa0: 6a7b ldr r3, [r7, #36] ; 0x24 - 800bfa2: 2b00 cmp r3, #0 - 800bfa4: d1e6 bne.n 800bf74 -#endif /* USART_CR1_FIFOEN */ - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - 800bfa6: 687b ldr r3, [r7, #4] - 800bfa8: 681b ldr r3, [r3, #0] - 800bfaa: 60fb str r3, [r7, #12] - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800bfac: 68fb ldr r3, [r7, #12] - 800bfae: e853 3f00 ldrex r3, [r3] - 800bfb2: 60bb str r3, [r7, #8] - return(result); - 800bfb4: 68bb ldr r3, [r7, #8] - 800bfb6: f043 0340 orr.w r3, r3, #64 ; 0x40 - 800bfba: 633b str r3, [r7, #48] ; 0x30 - 800bfbc: 687b ldr r3, [r7, #4] - 800bfbe: 681b ldr r3, [r3, #0] - 800bfc0: 461a mov r2, r3 - 800bfc2: 6b3b ldr r3, [r7, #48] ; 0x30 - 800bfc4: 61bb str r3, [r7, #24] - 800bfc6: 617a str r2, [r7, #20] - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800bfc8: 6979 ldr r1, [r7, #20] - 800bfca: 69ba ldr r2, [r7, #24] - 800bfcc: e841 2300 strex r3, r2, [r1] - 800bfd0: 613b str r3, [r7, #16] - return(result); - 800bfd2: 693b ldr r3, [r7, #16] - 800bfd4: 2b00 cmp r3, #0 - 800bfd6: d1e6 bne.n 800bfa6 - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - huart->pTxBuffPtr++; - huart->TxXferCount--; - } - } + HAL_UART_ErrorCallback(huart); + 800d346: 6978 ldr r0, [r7, #20] + 800d348: f7ff f9f2 bl 800c730 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 800bfd8: e014 b.n 800c004 - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - 800bfda: 687b ldr r3, [r7, #4] - 800bfdc: 6cdb ldr r3, [r3, #76] ; 0x4c - 800bfde: 781a ldrb r2, [r3, #0] - 800bfe0: 687b ldr r3, [r7, #4] - 800bfe2: 681b ldr r3, [r3, #0] - 800bfe4: b292 uxth r2, r2 - 800bfe6: 851a strh r2, [r3, #40] ; 0x28 - huart->pTxBuffPtr++; - 800bfe8: 687b ldr r3, [r7, #4] - 800bfea: 6cdb ldr r3, [r3, #76] ; 0x4c - 800bfec: 1c5a adds r2, r3, #1 - 800bfee: 687b ldr r3, [r7, #4] - 800bff0: 64da str r2, [r3, #76] ; 0x4c - huart->TxXferCount--; - 800bff2: 687b ldr r3, [r7, #4] - 800bff4: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 800bff8: b29b uxth r3, r3 - 800bffa: 3b01 subs r3, #1 - 800bffc: b29a uxth r2, r3 - 800bffe: 687b ldr r3, [r7, #4] - 800c000: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 -} - 800c004: bf00 nop - 800c006: 373c adds r7, #60 ; 0x3c - 800c008: 46bd mov sp, r7 - 800c00a: f85d 7b04 ldr.w r7, [sp], #4 - 800c00e: 4770 bx lr - -0800c010 : - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. + 800d34c: bf00 nop + 800d34e: 3718 adds r7, #24 + 800d350: 46bd mov sp, r7 + 800d352: bd80 pop {r7, pc} + +0800d354 : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. * @retval None */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - 800c010: b480 push {r7} - 800c012: b091 sub sp, #68 ; 0x44 - 800c014: af00 add r7, sp, #0 - 800c016: 6078 str r0, [r7, #4] - const uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - 800c018: 687b ldr r3, [r7, #4] - 800c01a: 6fdb ldr r3, [r3, #124] ; 0x7c - 800c01c: 2b21 cmp r3, #33 ; 0x21 - 800c01e: d151 bne.n 800c0c4 - { - if (huart->TxXferCount == 0U) - 800c020: 687b ldr r3, [r7, #4] - 800c022: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 800c026: b29b uxth r3, r3 - 800c028: 2b00 cmp r3, #0 - 800c02a: d132 bne.n 800c092 - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 800d354: b580 push {r7, lr} + 800d356: b084 sub sp, #16 + 800d358: af00 add r7, sp, #0 + 800d35a: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 800d35c: 687b ldr r3, [r7, #4] + 800d35e: 6a9b ldr r3, [r3, #40] ; 0x28 + 800d360: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 800d362: 68fb ldr r3, [r7, #12] + 800d364: 2200 movs r2, #0 + 800d366: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + huart->TxXferCount = 0U; + 800d36a: 68fb ldr r3, [r7, #12] + 800d36c: 2200 movs r2, #0 + 800d36e: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); #else - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - 800c02c: 687b ldr r3, [r7, #4] - 800c02e: 681b ldr r3, [r3, #0] - 800c030: 627b str r3, [r7, #36] ; 0x24 - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800c032: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c034: e853 3f00 ldrex r3, [r3] - 800c038: 623b str r3, [r7, #32] - return(result); - 800c03a: 6a3b ldr r3, [r7, #32] - 800c03c: f023 0380 bic.w r3, r3, #128 ; 0x80 - 800c040: 63bb str r3, [r7, #56] ; 0x38 - 800c042: 687b ldr r3, [r7, #4] - 800c044: 681b ldr r3, [r3, #0] - 800c046: 461a mov r2, r3 - 800c048: 6bbb ldr r3, [r7, #56] ; 0x38 - 800c04a: 633b str r3, [r7, #48] ; 0x30 - 800c04c: 62fa str r2, [r7, #44] ; 0x2c - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800c04e: 6af9 ldr r1, [r7, #44] ; 0x2c - 800c050: 6b3a ldr r2, [r7, #48] ; 0x30 - 800c052: e841 2300 strex r3, r2, [r1] - 800c056: 62bb str r3, [r7, #40] ; 0x28 - return(result); - 800c058: 6abb ldr r3, [r7, #40] ; 0x28 - 800c05a: 2b00 cmp r3, #0 - 800c05c: d1e6 bne.n 800c02c -#endif /* USART_CR1_FIFOEN */ - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - 800c05e: 687b ldr r3, [r7, #4] - 800c060: 681b ldr r3, [r3, #0] - 800c062: 613b str r3, [r7, #16] - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800c064: 693b ldr r3, [r7, #16] - 800c066: e853 3f00 ldrex r3, [r3] - 800c06a: 60fb str r3, [r7, #12] - return(result); - 800c06c: 68fb ldr r3, [r7, #12] - 800c06e: f043 0340 orr.w r3, r3, #64 ; 0x40 - 800c072: 637b str r3, [r7, #52] ; 0x34 - 800c074: 687b ldr r3, [r7, #4] - 800c076: 681b ldr r3, [r3, #0] - 800c078: 461a mov r2, r3 - 800c07a: 6b7b ldr r3, [r7, #52] ; 0x34 - 800c07c: 61fb str r3, [r7, #28] - 800c07e: 61ba str r2, [r7, #24] - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800c080: 69b9 ldr r1, [r7, #24] - 800c082: 69fa ldr r2, [r7, #28] - 800c084: e841 2300 strex r3, r2, [r1] - 800c088: 617b str r3, [r7, #20] - return(result); - 800c08a: 697b ldr r3, [r7, #20] - 800c08c: 2b00 cmp r3, #0 - 800c08e: d1e6 bne.n 800c05e - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 800d372: 68f8 ldr r0, [r7, #12] + 800d374: f7ff f9dc bl 800c730 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 800c090: e018 b.n 800c0c4 - tmp = (const uint16_t *) huart->pTxBuffPtr; - 800c092: 687b ldr r3, [r7, #4] - 800c094: 6cdb ldr r3, [r3, #76] ; 0x4c - 800c096: 63fb str r3, [r7, #60] ; 0x3c - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - 800c098: 6bfb ldr r3, [r7, #60] ; 0x3c - 800c09a: 881a ldrh r2, [r3, #0] - 800c09c: 687b ldr r3, [r7, #4] - 800c09e: 681b ldr r3, [r3, #0] - 800c0a0: f3c2 0208 ubfx r2, r2, #0, #9 - 800c0a4: b292 uxth r2, r2 - 800c0a6: 851a strh r2, [r3, #40] ; 0x28 - huart->pTxBuffPtr += 2U; - 800c0a8: 687b ldr r3, [r7, #4] - 800c0aa: 6cdb ldr r3, [r3, #76] ; 0x4c - 800c0ac: 1c9a adds r2, r3, #2 - 800c0ae: 687b ldr r3, [r7, #4] - 800c0b0: 64da str r2, [r3, #76] ; 0x4c - huart->TxXferCount--; - 800c0b2: 687b ldr r3, [r7, #4] - 800c0b4: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 800c0b8: b29b uxth r3, r3 - 800c0ba: 3b01 subs r3, #1 - 800c0bc: b29a uxth r2, r3 - 800c0be: 687b ldr r3, [r7, #4] - 800c0c0: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 -} - 800c0c4: bf00 nop - 800c0c6: 3744 adds r7, #68 ; 0x44 - 800c0c8: 46bd mov sp, r7 - 800c0ca: f85d 7b04 ldr.w r7, [sp], #4 - 800c0ce: 4770 bx lr - -0800c0d0 : + 800d378: bf00 nop + 800d37a: 3710 adds r7, #16 + 800d37c: 46bd mov sp, r7 + 800d37e: bd80 pop {r7, pc} + +0800d380 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { - 800c0d0: b580 push {r7, lr} - 800c0d2: b088 sub sp, #32 - 800c0d4: af00 add r7, sp, #0 - 800c0d6: 6078 str r0, [r7, #4] + 800d380: b580 push {r7, lr} + 800d382: b088 sub sp, #32 + 800d384: af00 add r7, sp, #0 + 800d386: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - 800c0d8: 687b ldr r3, [r7, #4] - 800c0da: 681b ldr r3, [r3, #0] - 800c0dc: 60fb str r3, [r7, #12] + 800d388: 687b ldr r3, [r7, #4] + 800d38a: 681b ldr r3, [r3, #0] + 800d38c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800c0de: 68fb ldr r3, [r7, #12] - 800c0e0: e853 3f00 ldrex r3, [r3] - 800c0e4: 60bb str r3, [r7, #8] + 800d38e: 68fb ldr r3, [r7, #12] + 800d390: e853 3f00 ldrex r3, [r3] + 800d394: 60bb str r3, [r7, #8] return(result); - 800c0e6: 68bb ldr r3, [r7, #8] - 800c0e8: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c0ec: 61fb str r3, [r7, #28] - 800c0ee: 687b ldr r3, [r7, #4] - 800c0f0: 681b ldr r3, [r3, #0] - 800c0f2: 461a mov r2, r3 - 800c0f4: 69fb ldr r3, [r7, #28] - 800c0f6: 61bb str r3, [r7, #24] - 800c0f8: 617a str r2, [r7, #20] + 800d396: 68bb ldr r3, [r7, #8] + 800d398: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800d39c: 61fb str r3, [r7, #28] + 800d39e: 687b ldr r3, [r7, #4] + 800d3a0: 681b ldr r3, [r3, #0] + 800d3a2: 461a mov r2, r3 + 800d3a4: 69fb ldr r3, [r7, #28] + 800d3a6: 61bb str r3, [r7, #24] + 800d3a8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800c0fa: 6979 ldr r1, [r7, #20] - 800c0fc: 69ba ldr r2, [r7, #24] - 800c0fe: e841 2300 strex r3, r2, [r1] - 800c102: 613b str r3, [r7, #16] + 800d3aa: 6979 ldr r1, [r7, #20] + 800d3ac: 69ba ldr r2, [r7, #24] + 800d3ae: e841 2300 strex r3, r2, [r1] + 800d3b2: 613b str r3, [r7, #16] return(result); - 800c104: 693b ldr r3, [r7, #16] - 800c106: 2b00 cmp r3, #0 - 800c108: d1e6 bne.n 800c0d8 + 800d3b4: 693b ldr r3, [r7, #16] + 800d3b6: 2b00 cmp r3, #0 + 800d3b8: d1e6 bne.n 800d388 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 800c10a: 687b ldr r3, [r7, #4] - 800c10c: 2220 movs r2, #32 - 800c10e: 67da str r2, [r3, #124] ; 0x7c + 800d3ba: 687b ldr r3, [r7, #4] + 800d3bc: 2220 movs r2, #32 + 800d3be: 67da str r2, [r3, #124] ; 0x7c /* Cleat TxISR function pointer */ huart->TxISR = NULL; - 800c110: 687b ldr r3, [r7, #4] - 800c112: 2200 movs r2, #0 - 800c114: 66da str r2, [r3, #108] ; 0x6c + 800d3c0: 687b ldr r3, [r7, #4] + 800d3c2: 2200 movs r2, #0 + 800d3c4: 66da str r2, [r3, #108] ; 0x6c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); - 800c116: 6878 ldr r0, [r7, #4] - 800c118: f7ff f8e2 bl 800b2e0 + 800d3c6: 6878 ldr r0, [r7, #4] + 800d3c8: f7ff f99e bl 800c708 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 800c11c: bf00 nop - 800c11e: 3720 adds r7, #32 - 800c120: 46bd mov sp, r7 - 800c122: bd80 pop {r7, pc} + 800d3cc: bf00 nop + 800d3ce: 3720 adds r7, #32 + 800d3d0: 46bd mov sp, r7 + 800d3d2: bd80 pop {r7, pc} -0800c124 : +0800d3d4 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { - 800c124: b480 push {r7} - 800c126: b083 sub sp, #12 - 800c128: af00 add r7, sp, #0 - 800c12a: 6078 str r0, [r7, #4] + 800d3d4: b480 push {r7} + 800d3d6: b083 sub sp, #12 + 800d3d8: af00 add r7, sp, #0 + 800d3da: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } - 800c12c: bf00 nop - 800c12e: 370c adds r7, #12 - 800c130: 46bd mov sp, r7 - 800c132: f85d 7b04 ldr.w r7, [sp], #4 - 800c136: 4770 bx lr + 800d3dc: bf00 nop + 800d3de: 370c adds r7, #12 + 800d3e0: 46bd mov sp, r7 + 800d3e2: f85d 7b04 ldr.w r7, [sp], #4 + 800d3e6: 4770 bx lr -0800c138 : +0800d3e8 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - 800c138: b084 sub sp, #16 - 800c13a: b480 push {r7} - 800c13c: b083 sub sp, #12 - 800c13e: af00 add r7, sp, #0 - 800c140: 6078 str r0, [r7, #4] - 800c142: f107 0014 add.w r0, r7, #20 - 800c146: e880 000e stmia.w r0, {r1, r2, r3} + 800d3e8: b084 sub sp, #16 + 800d3ea: b480 push {r7} + 800d3ec: b083 sub sp, #12 + 800d3ee: af00 add r7, sp, #0 + 800d3f0: 6078 str r0, [r7, #4] + 800d3f2: f107 0014 add.w r0, r7, #20 + 800d3f6: e880 000e stmia.w r0, {r1, r2, r3} /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; - 800c14a: 2300 movs r3, #0 + 800d3fa: 2300 movs r3, #0 } - 800c14c: 4618 mov r0, r3 - 800c14e: 370c adds r7, #12 - 800c150: 46bd mov sp, r7 - 800c152: f85d 7b04 ldr.w r7, [sp], #4 - 800c156: b004 add sp, #16 - 800c158: 4770 bx lr + 800d3fc: 4618 mov r0, r3 + 800d3fe: 370c adds r7, #12 + 800d400: 46bd mov sp, r7 + 800d402: f85d 7b04 ldr.w r7, [sp], #4 + 800d406: b004 add sp, #16 + 800d408: 4770 bx lr -0800c15a : +0800d40a : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - 800c15a: b480 push {r7} - 800c15c: b085 sub sp, #20 - 800c15e: af00 add r7, sp, #0 - 800c160: 6078 str r0, [r7, #4] + 800d40a: b480 push {r7} + 800d40c: b085 sub sp, #20 + 800d40e: af00 add r7, sp, #0 + 800d410: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Clear pending interrupts */ USBx->ISTR = 0U; - 800c162: 687b ldr r3, [r7, #4] - 800c164: 2200 movs r2, #0 - 800c166: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 800d412: 687b ldr r3, [r7, #4] + 800d414: 2200 movs r2, #0 + 800d416: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - 800c16a: f64b 7380 movw r3, #49024 ; 0xbf80 - 800c16e: 60fb str r3, [r7, #12] + 800d41a: f64b 7380 movw r3, #49024 ; 0xbf80 + 800d41e: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ USBx->CNTR = (uint16_t)winterruptmask; - 800c170: 68fb ldr r3, [r7, #12] - 800c172: b29a uxth r2, r3 - 800c174: 687b ldr r3, [r7, #4] - 800c176: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 800d420: 68fb ldr r3, [r7, #12] + 800d422: b29a uxth r2, r3 + 800d424: 687b ldr r3, [r7, #4] + 800d426: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 return HAL_OK; - 800c17a: 2300 movs r3, #0 + 800d42a: 2300 movs r3, #0 } - 800c17c: 4618 mov r0, r3 - 800c17e: 3714 adds r7, #20 - 800c180: 46bd mov sp, r7 - 800c182: f85d 7b04 ldr.w r7, [sp], #4 - 800c186: 4770 bx lr + 800d42c: 4618 mov r0, r3 + 800d42e: 3714 adds r7, #20 + 800d430: 46bd mov sp, r7 + 800d432: f85d 7b04 ldr.w r7, [sp], #4 + 800d436: 4770 bx lr -0800c188 : +0800d438 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - 800c188: b480 push {r7} - 800c18a: b085 sub sp, #20 - 800c18c: af00 add r7, sp, #0 - 800c18e: 6078 str r0, [r7, #4] + 800d438: b480 push {r7} + 800d43a: b085 sub sp, #20 + 800d43c: af00 add r7, sp, #0 + 800d43e: 6078 str r0, [r7, #4] uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - 800c190: f64b 7380 movw r3, #49024 ; 0xbf80 - 800c194: 60fb str r3, [r7, #12] + 800d440: f64b 7380 movw r3, #49024 ; 0xbf80 + 800d444: 60fb str r3, [r7, #12] USB_CNTR_SUSPM | USB_CNTR_ERRM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ USBx->CNTR &= (uint16_t)(~winterruptmask); - 800c196: 687b ldr r3, [r7, #4] - 800c198: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 - 800c19c: b29a uxth r2, r3 - 800c19e: 68fb ldr r3, [r7, #12] - 800c1a0: b29b uxth r3, r3 - 800c1a2: 43db mvns r3, r3 - 800c1a4: b29b uxth r3, r3 - 800c1a6: 4013 ands r3, r2 - 800c1a8: b29a uxth r2, r3 - 800c1aa: 687b ldr r3, [r7, #4] - 800c1ac: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 800d446: 687b ldr r3, [r7, #4] + 800d448: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 + 800d44c: b29a uxth r2, r3 + 800d44e: 68fb ldr r3, [r7, #12] + 800d450: b29b uxth r3, r3 + 800d452: 43db mvns r3, r3 + 800d454: b29b uxth r3, r3 + 800d456: 4013 ands r3, r2 + 800d458: b29a uxth r2, r3 + 800d45a: 687b ldr r3, [r7, #4] + 800d45c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 return HAL_OK; - 800c1b0: 2300 movs r3, #0 + 800d460: 2300 movs r3, #0 } - 800c1b2: 4618 mov r0, r3 - 800c1b4: 3714 adds r7, #20 - 800c1b6: 46bd mov sp, r7 - 800c1b8: f85d 7b04 ldr.w r7, [sp], #4 - 800c1bc: 4770 bx lr + 800d462: 4618 mov r0, r3 + 800d464: 3714 adds r7, #20 + 800d466: 46bd mov sp, r7 + 800d468: f85d 7b04 ldr.w r7, [sp], #4 + 800d46c: 4770 bx lr -0800c1be : +0800d46e : * This parameter can be one of the these values: * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) { - 800c1be: b480 push {r7} - 800c1c0: b083 sub sp, #12 - 800c1c2: af00 add r7, sp, #0 - 800c1c4: 6078 str r0, [r7, #4] - 800c1c6: 460b mov r3, r1 - 800c1c8: 70fb strb r3, [r7, #3] + 800d46e: b480 push {r7} + 800d470: b083 sub sp, #12 + 800d472: af00 add r7, sp, #0 + 800d474: 6078 str r0, [r7, #4] + 800d476: 460b mov r3, r1 + 800d478: 70fb strb r3, [r7, #3] /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; - 800c1ca: 2300 movs r3, #0 + 800d47a: 2300 movs r3, #0 } - 800c1cc: 4618 mov r0, r3 - 800c1ce: 370c adds r7, #12 - 800c1d0: 46bd mov sp, r7 - 800c1d2: f85d 7b04 ldr.w r7, [sp], #4 - 800c1d6: 4770 bx lr + 800d47c: 4618 mov r0, r3 + 800d47e: 370c adds r7, #12 + 800d480: 46bd mov sp, r7 + 800d482: f85d 7b04 ldr.w r7, [sp], #4 + 800d486: 4770 bx lr -0800c1d8 : +0800d488 : * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { - 800c1d8: b084 sub sp, #16 - 800c1da: b480 push {r7} - 800c1dc: b083 sub sp, #12 - 800c1de: af00 add r7, sp, #0 - 800c1e0: 6078 str r0, [r7, #4] - 800c1e2: f107 0014 add.w r0, r7, #20 - 800c1e6: e880 000e stmia.w r0, {r1, r2, r3} + 800d488: b084 sub sp, #16 + 800d48a: b480 push {r7} + 800d48c: b083 sub sp, #12 + 800d48e: af00 add r7, sp, #0 + 800d490: 6078 str r0, [r7, #4] + 800d492: f107 0014 add.w r0, r7, #20 + 800d496: e880 000e stmia.w r0, {r1, r2, r3} /* Prevent unused argument(s) compilation warning */ UNUSED(cfg); /* Init Device */ /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; - 800c1ea: 687b ldr r3, [r7, #4] - 800c1ec: 2201 movs r2, #1 - 800c1ee: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 800d49a: 687b ldr r3, [r7, #4] + 800d49c: 2201 movs r2, #1 + 800d49e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 /* CNTR_FRES = 0 */ USBx->CNTR = 0U; - 800c1f2: 687b ldr r3, [r7, #4] - 800c1f4: 2200 movs r2, #0 - 800c1f6: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + 800d4a2: 687b ldr r3, [r7, #4] + 800d4a4: 2200 movs r2, #0 + 800d4a6: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 /* Clear pending interrupts */ USBx->ISTR = 0U; - 800c1fa: 687b ldr r3, [r7, #4] - 800c1fc: 2200 movs r2, #0 - 800c1fe: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + 800d4aa: 687b ldr r3, [r7, #4] + 800d4ac: 2200 movs r2, #0 + 800d4ae: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - 800c202: 687b ldr r3, [r7, #4] - 800c204: 2200 movs r2, #0 - 800c206: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + 800d4b2: 687b ldr r3, [r7, #4] + 800d4b4: 2200 movs r2, #0 + 800d4b6: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 return HAL_OK; - 800c20a: 2300 movs r3, #0 -} - 800c20c: 4618 mov r0, r3 - 800c20e: 370c adds r7, #12 - 800c210: 46bd mov sp, r7 - 800c212: f85d 7b04 ldr.w r7, [sp], #4 - 800c216: b004 add sp, #16 - 800c218: 4770 bx lr + 800d4ba: 2300 movs r3, #0 +} + 800d4bc: 4618 mov r0, r3 + 800d4be: 370c adds r7, #12 + 800d4c0: 46bd mov sp, r7 + 800d4c2: f85d 7b04 ldr.w r7, [sp], #4 + 800d4c6: b004 add sp, #16 + 800d4c8: 4770 bx lr ... -0800c21c : +0800d4cc : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - 800c21c: b480 push {r7} - 800c21e: b09d sub sp, #116 ; 0x74 - 800c220: af00 add r7, sp, #0 - 800c222: 6078 str r0, [r7, #4] - 800c224: 6039 str r1, [r7, #0] + 800d4cc: b480 push {r7} + 800d4ce: b09d sub sp, #116 ; 0x74 + 800d4d0: af00 add r7, sp, #0 + 800d4d2: 6078 str r0, [r7, #4] + 800d4d4: 6039 str r1, [r7, #0] HAL_StatusTypeDef ret = HAL_OK; - 800c226: 2300 movs r3, #0 - 800c228: f887 306f strb.w r3, [r7, #111] ; 0x6f + 800d4d6: 2300 movs r3, #0 + 800d4d8: f887 306f strb.w r3, [r7, #111] ; 0x6f uint16_t wEpRegVal; wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; - 800c22c: 687a ldr r2, [r7, #4] - 800c22e: 683b ldr r3, [r7, #0] - 800c230: 781b ldrb r3, [r3, #0] - 800c232: 009b lsls r3, r3, #2 - 800c234: 4413 add r3, r2 - 800c236: 881b ldrh r3, [r3, #0] - 800c238: b29b uxth r3, r3 - 800c23a: f423 43ec bic.w r3, r3, #30208 ; 0x7600 - 800c23e: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c242: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + 800d4dc: 687a ldr r2, [r7, #4] + 800d4de: 683b ldr r3, [r7, #0] + 800d4e0: 781b ldrb r3, [r3, #0] + 800d4e2: 009b lsls r3, r3, #2 + 800d4e4: 4413 add r3, r2 + 800d4e6: 881b ldrh r3, [r3, #0] + 800d4e8: b29b uxth r3, r3 + 800d4ea: f423 43ec bic.w r3, r3, #30208 ; 0x7600 + 800d4ee: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d4f2: f8a7 306c strh.w r3, [r7, #108] ; 0x6c /* initialize Endpoint */ switch (ep->type) - 800c246: 683b ldr r3, [r7, #0] - 800c248: 78db ldrb r3, [r3, #3] - 800c24a: 2b03 cmp r3, #3 - 800c24c: d81f bhi.n 800c28e - 800c24e: a201 add r2, pc, #4 ; (adr r2, 800c254 ) - 800c250: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800c254: 0800c265 .word 0x0800c265 - 800c258: 0800c281 .word 0x0800c281 - 800c25c: 0800c297 .word 0x0800c297 - 800c260: 0800c273 .word 0x0800c273 + 800d4f6: 683b ldr r3, [r7, #0] + 800d4f8: 78db ldrb r3, [r3, #3] + 800d4fa: 2b03 cmp r3, #3 + 800d4fc: d81f bhi.n 800d53e + 800d4fe: a201 add r2, pc, #4 ; (adr r2, 800d504 ) + 800d500: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800d504: 0800d515 .word 0x0800d515 + 800d508: 0800d531 .word 0x0800d531 + 800d50c: 0800d547 .word 0x0800d547 + 800d510: 0800d523 .word 0x0800d523 { case EP_TYPE_CTRL: wEpRegVal |= USB_EP_CONTROL; - 800c264: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c - 800c268: f443 7300 orr.w r3, r3, #512 ; 0x200 - 800c26c: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + 800d514: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c + 800d518: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800d51c: f8a7 306c strh.w r3, [r7, #108] ; 0x6c break; - 800c270: e012 b.n 800c298 + 800d520: e012 b.n 800d548 case EP_TYPE_BULK: wEpRegVal |= USB_EP_BULK; break; case EP_TYPE_INTR: wEpRegVal |= USB_EP_INTERRUPT; - 800c272: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c - 800c276: f443 63c0 orr.w r3, r3, #1536 ; 0x600 - 800c27a: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + 800d522: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c + 800d526: f443 63c0 orr.w r3, r3, #1536 ; 0x600 + 800d52a: f8a7 306c strh.w r3, [r7, #108] ; 0x6c break; - 800c27e: e00b b.n 800c298 + 800d52e: e00b b.n 800d548 case EP_TYPE_ISOC: wEpRegVal |= USB_EP_ISOCHRONOUS; - 800c280: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c - 800c284: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 800c288: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + 800d530: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c + 800d534: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 800d538: f8a7 306c strh.w r3, [r7, #108] ; 0x6c break; - 800c28c: e004 b.n 800c298 + 800d53c: e004 b.n 800d548 default: ret = HAL_ERROR; - 800c28e: 2301 movs r3, #1 - 800c290: f887 306f strb.w r3, [r7, #111] ; 0x6f + 800d53e: 2301 movs r3, #1 + 800d540: f887 306f strb.w r3, [r7, #111] ; 0x6f break; - 800c294: e000 b.n 800c298 + 800d544: e000 b.n 800d548 break; - 800c296: bf00 nop + 800d546: bf00 nop } PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); - 800c298: 687a ldr r2, [r7, #4] - 800c29a: 683b ldr r3, [r7, #0] - 800c29c: 781b ldrb r3, [r3, #0] - 800c29e: 009b lsls r3, r3, #2 - 800c2a0: 441a add r2, r3 - 800c2a2: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c - 800c2a6: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c2aa: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c2ae: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c2b2: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c2b6: b29b uxth r3, r3 - 800c2b8: 8013 strh r3, [r2, #0] + 800d548: 687a ldr r2, [r7, #4] + 800d54a: 683b ldr r3, [r7, #0] + 800d54c: 781b ldrb r3, [r3, #0] + 800d54e: 009b lsls r3, r3, #2 + 800d550: 441a add r2, r3 + 800d552: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c + 800d556: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d55a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d55e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d562: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d566: b29b uxth r3, r3 + 800d568: 8013 strh r3, [r2, #0] PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - 800c2ba: 687a ldr r2, [r7, #4] - 800c2bc: 683b ldr r3, [r7, #0] - 800c2be: 781b ldrb r3, [r3, #0] - 800c2c0: 009b lsls r3, r3, #2 - 800c2c2: 4413 add r3, r2 - 800c2c4: 881b ldrh r3, [r3, #0] - 800c2c6: b29b uxth r3, r3 - 800c2c8: b21b sxth r3, r3 - 800c2ca: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c2ce: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c2d2: b21a sxth r2, r3 - 800c2d4: 683b ldr r3, [r7, #0] - 800c2d6: 781b ldrb r3, [r3, #0] - 800c2d8: b21b sxth r3, r3 - 800c2da: 4313 orrs r3, r2 - 800c2dc: b21b sxth r3, r3 - 800c2de: f8a7 3066 strh.w r3, [r7, #102] ; 0x66 - 800c2e2: 687a ldr r2, [r7, #4] - 800c2e4: 683b ldr r3, [r7, #0] - 800c2e6: 781b ldrb r3, [r3, #0] - 800c2e8: 009b lsls r3, r3, #2 - 800c2ea: 441a add r2, r3 - 800c2ec: f8b7 3066 ldrh.w r3, [r7, #102] ; 0x66 - 800c2f0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c2f4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c2f8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c2fc: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c300: b29b uxth r3, r3 - 800c302: 8013 strh r3, [r2, #0] + 800d56a: 687a ldr r2, [r7, #4] + 800d56c: 683b ldr r3, [r7, #0] + 800d56e: 781b ldrb r3, [r3, #0] + 800d570: 009b lsls r3, r3, #2 + 800d572: 4413 add r3, r2 + 800d574: 881b ldrh r3, [r3, #0] + 800d576: b29b uxth r3, r3 + 800d578: b21b sxth r3, r3 + 800d57a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d57e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d582: b21a sxth r2, r3 + 800d584: 683b ldr r3, [r7, #0] + 800d586: 781b ldrb r3, [r3, #0] + 800d588: b21b sxth r3, r3 + 800d58a: 4313 orrs r3, r2 + 800d58c: b21b sxth r3, r3 + 800d58e: f8a7 3066 strh.w r3, [r7, #102] ; 0x66 + 800d592: 687a ldr r2, [r7, #4] + 800d594: 683b ldr r3, [r7, #0] + 800d596: 781b ldrb r3, [r3, #0] + 800d598: 009b lsls r3, r3, #2 + 800d59a: 441a add r2, r3 + 800d59c: f8b7 3066 ldrh.w r3, [r7, #102] ; 0x66 + 800d5a0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d5a4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d5a8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d5ac: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d5b0: b29b uxth r3, r3 + 800d5b2: 8013 strh r3, [r2, #0] if (ep->doublebuffer == 0U) - 800c304: 683b ldr r3, [r7, #0] - 800c306: 7b1b ldrb r3, [r3, #12] - 800c308: 2b00 cmp r3, #0 - 800c30a: f040 8178 bne.w 800c5fe + 800d5b4: 683b ldr r3, [r7, #0] + 800d5b6: 7b1b ldrb r3, [r3, #12] + 800d5b8: 2b00 cmp r3, #0 + 800d5ba: f040 8178 bne.w 800d8ae { if (ep->is_in != 0U) - 800c30e: 683b ldr r3, [r7, #0] - 800c310: 785b ldrb r3, [r3, #1] - 800c312: 2b00 cmp r3, #0 - 800c314: f000 8084 beq.w 800c420 + 800d5be: 683b ldr r3, [r7, #0] + 800d5c0: 785b ldrb r3, [r3, #1] + 800d5c2: 2b00 cmp r3, #0 + 800d5c4: f000 8084 beq.w 800d6d0 { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); - 800c318: 687b ldr r3, [r7, #4] - 800c31a: 61bb str r3, [r7, #24] - 800c31c: 687b ldr r3, [r7, #4] - 800c31e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800c322: b29b uxth r3, r3 - 800c324: 461a mov r2, r3 - 800c326: 69bb ldr r3, [r7, #24] - 800c328: 4413 add r3, r2 - 800c32a: 61bb str r3, [r7, #24] - 800c32c: 683b ldr r3, [r7, #0] - 800c32e: 781b ldrb r3, [r3, #0] - 800c330: 00da lsls r2, r3, #3 - 800c332: 69bb ldr r3, [r7, #24] - 800c334: 4413 add r3, r2 - 800c336: f503 6380 add.w r3, r3, #1024 ; 0x400 - 800c33a: 617b str r3, [r7, #20] - 800c33c: 683b ldr r3, [r7, #0] - 800c33e: 88db ldrh r3, [r3, #6] - 800c340: 085b lsrs r3, r3, #1 - 800c342: b29b uxth r3, r3 - 800c344: 005b lsls r3, r3, #1 - 800c346: b29a uxth r2, r3 - 800c348: 697b ldr r3, [r7, #20] - 800c34a: 801a strh r2, [r3, #0] + 800d5c8: 687b ldr r3, [r7, #4] + 800d5ca: 61bb str r3, [r7, #24] + 800d5cc: 687b ldr r3, [r7, #4] + 800d5ce: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800d5d2: b29b uxth r3, r3 + 800d5d4: 461a mov r2, r3 + 800d5d6: 69bb ldr r3, [r7, #24] + 800d5d8: 4413 add r3, r2 + 800d5da: 61bb str r3, [r7, #24] + 800d5dc: 683b ldr r3, [r7, #0] + 800d5de: 781b ldrb r3, [r3, #0] + 800d5e0: 00da lsls r2, r3, #3 + 800d5e2: 69bb ldr r3, [r7, #24] + 800d5e4: 4413 add r3, r2 + 800d5e6: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800d5ea: 617b str r3, [r7, #20] + 800d5ec: 683b ldr r3, [r7, #0] + 800d5ee: 88db ldrh r3, [r3, #6] + 800d5f0: 085b lsrs r3, r3, #1 + 800d5f2: b29b uxth r3, r3 + 800d5f4: 005b lsls r3, r3, #1 + 800d5f6: b29a uxth r2, r3 + 800d5f8: 697b ldr r3, [r7, #20] + 800d5fa: 801a strh r2, [r3, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800c34c: 687a ldr r2, [r7, #4] - 800c34e: 683b ldr r3, [r7, #0] - 800c350: 781b ldrb r3, [r3, #0] - 800c352: 009b lsls r3, r3, #2 - 800c354: 4413 add r3, r2 - 800c356: 881b ldrh r3, [r3, #0] - 800c358: 827b strh r3, [r7, #18] - 800c35a: 8a7b ldrh r3, [r7, #18] - 800c35c: f003 0340 and.w r3, r3, #64 ; 0x40 - 800c360: 2b00 cmp r3, #0 - 800c362: d01b beq.n 800c39c - 800c364: 687a ldr r2, [r7, #4] - 800c366: 683b ldr r3, [r7, #0] - 800c368: 781b ldrb r3, [r3, #0] - 800c36a: 009b lsls r3, r3, #2 - 800c36c: 4413 add r3, r2 - 800c36e: 881b ldrh r3, [r3, #0] - 800c370: b29b uxth r3, r3 - 800c372: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c376: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c37a: 823b strh r3, [r7, #16] - 800c37c: 687a ldr r2, [r7, #4] - 800c37e: 683b ldr r3, [r7, #0] - 800c380: 781b ldrb r3, [r3, #0] - 800c382: 009b lsls r3, r3, #2 - 800c384: 441a add r2, r3 - 800c386: 8a3b ldrh r3, [r7, #16] - 800c388: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c38c: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c390: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c394: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800c398: b29b uxth r3, r3 - 800c39a: 8013 strh r3, [r2, #0] + 800d5fc: 687a ldr r2, [r7, #4] + 800d5fe: 683b ldr r3, [r7, #0] + 800d600: 781b ldrb r3, [r3, #0] + 800d602: 009b lsls r3, r3, #2 + 800d604: 4413 add r3, r2 + 800d606: 881b ldrh r3, [r3, #0] + 800d608: 827b strh r3, [r7, #18] + 800d60a: 8a7b ldrh r3, [r7, #18] + 800d60c: f003 0340 and.w r3, r3, #64 ; 0x40 + 800d610: 2b00 cmp r3, #0 + 800d612: d01b beq.n 800d64c + 800d614: 687a ldr r2, [r7, #4] + 800d616: 683b ldr r3, [r7, #0] + 800d618: 781b ldrb r3, [r3, #0] + 800d61a: 009b lsls r3, r3, #2 + 800d61c: 4413 add r3, r2 + 800d61e: 881b ldrh r3, [r3, #0] + 800d620: b29b uxth r3, r3 + 800d622: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d626: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d62a: 823b strh r3, [r7, #16] + 800d62c: 687a ldr r2, [r7, #4] + 800d62e: 683b ldr r3, [r7, #0] + 800d630: 781b ldrb r3, [r3, #0] + 800d632: 009b lsls r3, r3, #2 + 800d634: 441a add r2, r3 + 800d636: 8a3b ldrh r3, [r7, #16] + 800d638: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d63c: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d640: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d644: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800d648: b29b uxth r3, r3 + 800d64a: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) - 800c39c: 683b ldr r3, [r7, #0] - 800c39e: 78db ldrb r3, [r3, #3] - 800c3a0: 2b01 cmp r3, #1 - 800c3a2: d020 beq.n 800c3e6 + 800d64c: 683b ldr r3, [r7, #0] + 800d64e: 78db ldrb r3, [r3, #3] + 800d650: 2b01 cmp r3, #1 + 800d652: d020 beq.n 800d696 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - 800c3a4: 687a ldr r2, [r7, #4] - 800c3a6: 683b ldr r3, [r7, #0] - 800c3a8: 781b ldrb r3, [r3, #0] - 800c3aa: 009b lsls r3, r3, #2 - 800c3ac: 4413 add r3, r2 - 800c3ae: 881b ldrh r3, [r3, #0] - 800c3b0: b29b uxth r3, r3 - 800c3b2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c3b6: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c3ba: 81bb strh r3, [r7, #12] - 800c3bc: 89bb ldrh r3, [r7, #12] - 800c3be: f083 0320 eor.w r3, r3, #32 - 800c3c2: 81bb strh r3, [r7, #12] - 800c3c4: 687a ldr r2, [r7, #4] - 800c3c6: 683b ldr r3, [r7, #0] - 800c3c8: 781b ldrb r3, [r3, #0] - 800c3ca: 009b lsls r3, r3, #2 - 800c3cc: 441a add r2, r3 - 800c3ce: 89bb ldrh r3, [r7, #12] - 800c3d0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c3d4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c3d8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c3dc: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c3e0: b29b uxth r3, r3 - 800c3e2: 8013 strh r3, [r2, #0] - 800c3e4: e2d5 b.n 800c992 + 800d654: 687a ldr r2, [r7, #4] + 800d656: 683b ldr r3, [r7, #0] + 800d658: 781b ldrb r3, [r3, #0] + 800d65a: 009b lsls r3, r3, #2 + 800d65c: 4413 add r3, r2 + 800d65e: 881b ldrh r3, [r3, #0] + 800d660: b29b uxth r3, r3 + 800d662: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d666: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800d66a: 81bb strh r3, [r7, #12] + 800d66c: 89bb ldrh r3, [r7, #12] + 800d66e: f083 0320 eor.w r3, r3, #32 + 800d672: 81bb strh r3, [r7, #12] + 800d674: 687a ldr r2, [r7, #4] + 800d676: 683b ldr r3, [r7, #0] + 800d678: 781b ldrb r3, [r3, #0] + 800d67a: 009b lsls r3, r3, #2 + 800d67c: 441a add r2, r3 + 800d67e: 89bb ldrh r3, [r7, #12] + 800d680: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d684: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d688: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d68c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d690: b29b uxth r3, r3 + 800d692: 8013 strh r3, [r2, #0] + 800d694: e2d5 b.n 800dc42 } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800c3e6: 687a ldr r2, [r7, #4] - 800c3e8: 683b ldr r3, [r7, #0] - 800c3ea: 781b ldrb r3, [r3, #0] - 800c3ec: 009b lsls r3, r3, #2 - 800c3ee: 4413 add r3, r2 - 800c3f0: 881b ldrh r3, [r3, #0] - 800c3f2: b29b uxth r3, r3 - 800c3f4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c3f8: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c3fc: 81fb strh r3, [r7, #14] - 800c3fe: 687a ldr r2, [r7, #4] - 800c400: 683b ldr r3, [r7, #0] - 800c402: 781b ldrb r3, [r3, #0] - 800c404: 009b lsls r3, r3, #2 - 800c406: 441a add r2, r3 - 800c408: 89fb ldrh r3, [r7, #14] - 800c40a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c40e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c412: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c416: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c41a: b29b uxth r3, r3 - 800c41c: 8013 strh r3, [r2, #0] - 800c41e: e2b8 b.n 800c992 + 800d696: 687a ldr r2, [r7, #4] + 800d698: 683b ldr r3, [r7, #0] + 800d69a: 781b ldrb r3, [r3, #0] + 800d69c: 009b lsls r3, r3, #2 + 800d69e: 4413 add r3, r2 + 800d6a0: 881b ldrh r3, [r3, #0] + 800d6a2: b29b uxth r3, r3 + 800d6a4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d6a8: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800d6ac: 81fb strh r3, [r7, #14] + 800d6ae: 687a ldr r2, [r7, #4] + 800d6b0: 683b ldr r3, [r7, #0] + 800d6b2: 781b ldrb r3, [r3, #0] + 800d6b4: 009b lsls r3, r3, #2 + 800d6b6: 441a add r2, r3 + 800d6b8: 89fb ldrh r3, [r7, #14] + 800d6ba: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d6be: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d6c2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d6c6: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d6ca: b29b uxth r3, r3 + 800d6cc: 8013 strh r3, [r2, #0] + 800d6ce: e2b8 b.n 800dc42 } } else { /* Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - 800c420: 687b ldr r3, [r7, #4] - 800c422: 633b str r3, [r7, #48] ; 0x30 - 800c424: 687b ldr r3, [r7, #4] - 800c426: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800c42a: b29b uxth r3, r3 - 800c42c: 461a mov r2, r3 - 800c42e: 6b3b ldr r3, [r7, #48] ; 0x30 - 800c430: 4413 add r3, r2 - 800c432: 633b str r3, [r7, #48] ; 0x30 - 800c434: 683b ldr r3, [r7, #0] - 800c436: 781b ldrb r3, [r3, #0] - 800c438: 00da lsls r2, r3, #3 - 800c43a: 6b3b ldr r3, [r7, #48] ; 0x30 - 800c43c: 4413 add r3, r2 - 800c43e: f203 4304 addw r3, r3, #1028 ; 0x404 - 800c442: 62fb str r3, [r7, #44] ; 0x2c - 800c444: 683b ldr r3, [r7, #0] - 800c446: 88db ldrh r3, [r3, #6] - 800c448: 085b lsrs r3, r3, #1 - 800c44a: b29b uxth r3, r3 - 800c44c: 005b lsls r3, r3, #1 - 800c44e: b29a uxth r2, r3 - 800c450: 6afb ldr r3, [r7, #44] ; 0x2c - 800c452: 801a strh r2, [r3, #0] + 800d6d0: 687b ldr r3, [r7, #4] + 800d6d2: 633b str r3, [r7, #48] ; 0x30 + 800d6d4: 687b ldr r3, [r7, #4] + 800d6d6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800d6da: b29b uxth r3, r3 + 800d6dc: 461a mov r2, r3 + 800d6de: 6b3b ldr r3, [r7, #48] ; 0x30 + 800d6e0: 4413 add r3, r2 + 800d6e2: 633b str r3, [r7, #48] ; 0x30 + 800d6e4: 683b ldr r3, [r7, #0] + 800d6e6: 781b ldrb r3, [r3, #0] + 800d6e8: 00da lsls r2, r3, #3 + 800d6ea: 6b3b ldr r3, [r7, #48] ; 0x30 + 800d6ec: 4413 add r3, r2 + 800d6ee: f203 4304 addw r3, r3, #1028 ; 0x404 + 800d6f2: 62fb str r3, [r7, #44] ; 0x2c + 800d6f4: 683b ldr r3, [r7, #0] + 800d6f6: 88db ldrh r3, [r3, #6] + 800d6f8: 085b lsrs r3, r3, #1 + 800d6fa: b29b uxth r3, r3 + 800d6fc: 005b lsls r3, r3, #1 + 800d6fe: b29a uxth r2, r3 + 800d700: 6afb ldr r3, [r7, #44] ; 0x2c + 800d702: 801a strh r2, [r3, #0] /* Set the endpoint Receive buffer counter */ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); - 800c454: 687b ldr r3, [r7, #4] - 800c456: 62bb str r3, [r7, #40] ; 0x28 - 800c458: 687b ldr r3, [r7, #4] - 800c45a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800c45e: b29b uxth r3, r3 - 800c460: 461a mov r2, r3 - 800c462: 6abb ldr r3, [r7, #40] ; 0x28 - 800c464: 4413 add r3, r2 - 800c466: 62bb str r3, [r7, #40] ; 0x28 - 800c468: 683b ldr r3, [r7, #0] - 800c46a: 781b ldrb r3, [r3, #0] - 800c46c: 00da lsls r2, r3, #3 - 800c46e: 6abb ldr r3, [r7, #40] ; 0x28 - 800c470: 4413 add r3, r2 - 800c472: f203 4306 addw r3, r3, #1030 ; 0x406 - 800c476: 627b str r3, [r7, #36] ; 0x24 - 800c478: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c47a: 881b ldrh r3, [r3, #0] - 800c47c: b29b uxth r3, r3 - 800c47e: f3c3 0309 ubfx r3, r3, #0, #10 - 800c482: b29a uxth r2, r3 - 800c484: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c486: 801a strh r2, [r3, #0] - 800c488: 683b ldr r3, [r7, #0] - 800c48a: 691b ldr r3, [r3, #16] - 800c48c: 2b3e cmp r3, #62 ; 0x3e - 800c48e: d91d bls.n 800c4cc - 800c490: 683b ldr r3, [r7, #0] - 800c492: 691b ldr r3, [r3, #16] - 800c494: 095b lsrs r3, r3, #5 - 800c496: 66bb str r3, [r7, #104] ; 0x68 - 800c498: 683b ldr r3, [r7, #0] - 800c49a: 691b ldr r3, [r3, #16] - 800c49c: f003 031f and.w r3, r3, #31 - 800c4a0: 2b00 cmp r3, #0 - 800c4a2: d102 bne.n 800c4aa - 800c4a4: 6ebb ldr r3, [r7, #104] ; 0x68 - 800c4a6: 3b01 subs r3, #1 - 800c4a8: 66bb str r3, [r7, #104] ; 0x68 - 800c4aa: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c4ac: 881b ldrh r3, [r3, #0] - 800c4ae: b29a uxth r2, r3 - 800c4b0: 6ebb ldr r3, [r7, #104] ; 0x68 - 800c4b2: b29b uxth r3, r3 - 800c4b4: 029b lsls r3, r3, #10 - 800c4b6: b29b uxth r3, r3 - 800c4b8: 4313 orrs r3, r2 - 800c4ba: b29b uxth r3, r3 - 800c4bc: ea6f 4343 mvn.w r3, r3, lsl #17 - 800c4c0: ea6f 4353 mvn.w r3, r3, lsr #17 - 800c4c4: b29a uxth r2, r3 - 800c4c6: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c4c8: 801a strh r2, [r3, #0] - 800c4ca: e026 b.n 800c51a - 800c4cc: 683b ldr r3, [r7, #0] - 800c4ce: 691b ldr r3, [r3, #16] - 800c4d0: 2b00 cmp r3, #0 - 800c4d2: d10a bne.n 800c4ea - 800c4d4: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c4d6: 881b ldrh r3, [r3, #0] - 800c4d8: b29b uxth r3, r3 - 800c4da: ea6f 4343 mvn.w r3, r3, lsl #17 - 800c4de: ea6f 4353 mvn.w r3, r3, lsr #17 - 800c4e2: b29a uxth r2, r3 - 800c4e4: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c4e6: 801a strh r2, [r3, #0] - 800c4e8: e017 b.n 800c51a - 800c4ea: 683b ldr r3, [r7, #0] - 800c4ec: 691b ldr r3, [r3, #16] - 800c4ee: 085b lsrs r3, r3, #1 - 800c4f0: 66bb str r3, [r7, #104] ; 0x68 - 800c4f2: 683b ldr r3, [r7, #0] - 800c4f4: 691b ldr r3, [r3, #16] - 800c4f6: f003 0301 and.w r3, r3, #1 - 800c4fa: 2b00 cmp r3, #0 - 800c4fc: d002 beq.n 800c504 - 800c4fe: 6ebb ldr r3, [r7, #104] ; 0x68 - 800c500: 3301 adds r3, #1 - 800c502: 66bb str r3, [r7, #104] ; 0x68 - 800c504: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c506: 881b ldrh r3, [r3, #0] - 800c508: b29a uxth r2, r3 - 800c50a: 6ebb ldr r3, [r7, #104] ; 0x68 - 800c50c: b29b uxth r3, r3 - 800c50e: 029b lsls r3, r3, #10 - 800c510: b29b uxth r3, r3 - 800c512: 4313 orrs r3, r2 - 800c514: b29a uxth r2, r3 - 800c516: 6a7b ldr r3, [r7, #36] ; 0x24 - 800c518: 801a strh r2, [r3, #0] + 800d704: 687b ldr r3, [r7, #4] + 800d706: 62bb str r3, [r7, #40] ; 0x28 + 800d708: 687b ldr r3, [r7, #4] + 800d70a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800d70e: b29b uxth r3, r3 + 800d710: 461a mov r2, r3 + 800d712: 6abb ldr r3, [r7, #40] ; 0x28 + 800d714: 4413 add r3, r2 + 800d716: 62bb str r3, [r7, #40] ; 0x28 + 800d718: 683b ldr r3, [r7, #0] + 800d71a: 781b ldrb r3, [r3, #0] + 800d71c: 00da lsls r2, r3, #3 + 800d71e: 6abb ldr r3, [r7, #40] ; 0x28 + 800d720: 4413 add r3, r2 + 800d722: f203 4306 addw r3, r3, #1030 ; 0x406 + 800d726: 627b str r3, [r7, #36] ; 0x24 + 800d728: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d72a: 881b ldrh r3, [r3, #0] + 800d72c: b29b uxth r3, r3 + 800d72e: f3c3 0309 ubfx r3, r3, #0, #10 + 800d732: b29a uxth r2, r3 + 800d734: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d736: 801a strh r2, [r3, #0] + 800d738: 683b ldr r3, [r7, #0] + 800d73a: 691b ldr r3, [r3, #16] + 800d73c: 2b3e cmp r3, #62 ; 0x3e + 800d73e: d91d bls.n 800d77c + 800d740: 683b ldr r3, [r7, #0] + 800d742: 691b ldr r3, [r3, #16] + 800d744: 095b lsrs r3, r3, #5 + 800d746: 66bb str r3, [r7, #104] ; 0x68 + 800d748: 683b ldr r3, [r7, #0] + 800d74a: 691b ldr r3, [r3, #16] + 800d74c: f003 031f and.w r3, r3, #31 + 800d750: 2b00 cmp r3, #0 + 800d752: d102 bne.n 800d75a + 800d754: 6ebb ldr r3, [r7, #104] ; 0x68 + 800d756: 3b01 subs r3, #1 + 800d758: 66bb str r3, [r7, #104] ; 0x68 + 800d75a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d75c: 881b ldrh r3, [r3, #0] + 800d75e: b29a uxth r2, r3 + 800d760: 6ebb ldr r3, [r7, #104] ; 0x68 + 800d762: b29b uxth r3, r3 + 800d764: 029b lsls r3, r3, #10 + 800d766: b29b uxth r3, r3 + 800d768: 4313 orrs r3, r2 + 800d76a: b29b uxth r3, r3 + 800d76c: ea6f 4343 mvn.w r3, r3, lsl #17 + 800d770: ea6f 4353 mvn.w r3, r3, lsr #17 + 800d774: b29a uxth r2, r3 + 800d776: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d778: 801a strh r2, [r3, #0] + 800d77a: e026 b.n 800d7ca + 800d77c: 683b ldr r3, [r7, #0] + 800d77e: 691b ldr r3, [r3, #16] + 800d780: 2b00 cmp r3, #0 + 800d782: d10a bne.n 800d79a + 800d784: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d786: 881b ldrh r3, [r3, #0] + 800d788: b29b uxth r3, r3 + 800d78a: ea6f 4343 mvn.w r3, r3, lsl #17 + 800d78e: ea6f 4353 mvn.w r3, r3, lsr #17 + 800d792: b29a uxth r2, r3 + 800d794: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d796: 801a strh r2, [r3, #0] + 800d798: e017 b.n 800d7ca + 800d79a: 683b ldr r3, [r7, #0] + 800d79c: 691b ldr r3, [r3, #16] + 800d79e: 085b lsrs r3, r3, #1 + 800d7a0: 66bb str r3, [r7, #104] ; 0x68 + 800d7a2: 683b ldr r3, [r7, #0] + 800d7a4: 691b ldr r3, [r3, #16] + 800d7a6: f003 0301 and.w r3, r3, #1 + 800d7aa: 2b00 cmp r3, #0 + 800d7ac: d002 beq.n 800d7b4 + 800d7ae: 6ebb ldr r3, [r7, #104] ; 0x68 + 800d7b0: 3301 adds r3, #1 + 800d7b2: 66bb str r3, [r7, #104] ; 0x68 + 800d7b4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d7b6: 881b ldrh r3, [r3, #0] + 800d7b8: b29a uxth r2, r3 + 800d7ba: 6ebb ldr r3, [r7, #104] ; 0x68 + 800d7bc: b29b uxth r3, r3 + 800d7be: 029b lsls r3, r3, #10 + 800d7c0: b29b uxth r3, r3 + 800d7c2: 4313 orrs r3, r2 + 800d7c4: b29a uxth r2, r3 + 800d7c6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d7c8: 801a strh r2, [r3, #0] PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800c51a: 687a ldr r2, [r7, #4] - 800c51c: 683b ldr r3, [r7, #0] - 800c51e: 781b ldrb r3, [r3, #0] - 800c520: 009b lsls r3, r3, #2 - 800c522: 4413 add r3, r2 - 800c524: 881b ldrh r3, [r3, #0] - 800c526: 847b strh r3, [r7, #34] ; 0x22 - 800c528: 8c7b ldrh r3, [r7, #34] ; 0x22 - 800c52a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800c52e: 2b00 cmp r3, #0 - 800c530: d01b beq.n 800c56a - 800c532: 687a ldr r2, [r7, #4] - 800c534: 683b ldr r3, [r7, #0] - 800c536: 781b ldrb r3, [r3, #0] - 800c538: 009b lsls r3, r3, #2 - 800c53a: 4413 add r3, r2 - 800c53c: 881b ldrh r3, [r3, #0] - 800c53e: b29b uxth r3, r3 - 800c540: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c544: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c548: 843b strh r3, [r7, #32] - 800c54a: 687a ldr r2, [r7, #4] - 800c54c: 683b ldr r3, [r7, #0] - 800c54e: 781b ldrb r3, [r3, #0] - 800c550: 009b lsls r3, r3, #2 - 800c552: 441a add r2, r3 - 800c554: 8c3b ldrh r3, [r7, #32] - 800c556: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c55a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c55e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800c562: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c566: b29b uxth r3, r3 - 800c568: 8013 strh r3, [r2, #0] + 800d7ca: 687a ldr r2, [r7, #4] + 800d7cc: 683b ldr r3, [r7, #0] + 800d7ce: 781b ldrb r3, [r3, #0] + 800d7d0: 009b lsls r3, r3, #2 + 800d7d2: 4413 add r3, r2 + 800d7d4: 881b ldrh r3, [r3, #0] + 800d7d6: 847b strh r3, [r7, #34] ; 0x22 + 800d7d8: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800d7da: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800d7de: 2b00 cmp r3, #0 + 800d7e0: d01b beq.n 800d81a + 800d7e2: 687a ldr r2, [r7, #4] + 800d7e4: 683b ldr r3, [r7, #0] + 800d7e6: 781b ldrb r3, [r3, #0] + 800d7e8: 009b lsls r3, r3, #2 + 800d7ea: 4413 add r3, r2 + 800d7ec: 881b ldrh r3, [r3, #0] + 800d7ee: b29b uxth r3, r3 + 800d7f0: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d7f4: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d7f8: 843b strh r3, [r7, #32] + 800d7fa: 687a ldr r2, [r7, #4] + 800d7fc: 683b ldr r3, [r7, #0] + 800d7fe: 781b ldrb r3, [r3, #0] + 800d800: 009b lsls r3, r3, #2 + 800d802: 441a add r2, r3 + 800d804: 8c3b ldrh r3, [r7, #32] + 800d806: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d80a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d80e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800d812: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d816: b29b uxth r3, r3 + 800d818: 8013 strh r3, [r2, #0] if (ep->num == 0U) - 800c56a: 683b ldr r3, [r7, #0] - 800c56c: 781b ldrb r3, [r3, #0] - 800c56e: 2b00 cmp r3, #0 - 800c570: d124 bne.n 800c5bc + 800d81a: 683b ldr r3, [r7, #0] + 800d81c: 781b ldrb r3, [r3, #0] + 800d81e: 2b00 cmp r3, #0 + 800d820: d124 bne.n 800d86c { /* Configure VALID status for EP0 */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - 800c572: 687a ldr r2, [r7, #4] - 800c574: 683b ldr r3, [r7, #0] - 800c576: 781b ldrb r3, [r3, #0] - 800c578: 009b lsls r3, r3, #2 - 800c57a: 4413 add r3, r2 - 800c57c: 881b ldrh r3, [r3, #0] - 800c57e: b29b uxth r3, r3 - 800c580: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800c584: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c588: 83bb strh r3, [r7, #28] - 800c58a: 8bbb ldrh r3, [r7, #28] - 800c58c: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 800c590: 83bb strh r3, [r7, #28] - 800c592: 8bbb ldrh r3, [r7, #28] - 800c594: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 800c598: 83bb strh r3, [r7, #28] - 800c59a: 687a ldr r2, [r7, #4] - 800c59c: 683b ldr r3, [r7, #0] - 800c59e: 781b ldrb r3, [r3, #0] - 800c5a0: 009b lsls r3, r3, #2 - 800c5a2: 441a add r2, r3 - 800c5a4: 8bbb ldrh r3, [r7, #28] - 800c5a6: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c5aa: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c5ae: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c5b2: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c5b6: b29b uxth r3, r3 - 800c5b8: 8013 strh r3, [r2, #0] - 800c5ba: e1ea b.n 800c992 + 800d822: 687a ldr r2, [r7, #4] + 800d824: 683b ldr r3, [r7, #0] + 800d826: 781b ldrb r3, [r3, #0] + 800d828: 009b lsls r3, r3, #2 + 800d82a: 4413 add r3, r2 + 800d82c: 881b ldrh r3, [r3, #0] + 800d82e: b29b uxth r3, r3 + 800d830: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800d834: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d838: 83bb strh r3, [r7, #28] + 800d83a: 8bbb ldrh r3, [r7, #28] + 800d83c: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800d840: 83bb strh r3, [r7, #28] + 800d842: 8bbb ldrh r3, [r7, #28] + 800d844: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 800d848: 83bb strh r3, [r7, #28] + 800d84a: 687a ldr r2, [r7, #4] + 800d84c: 683b ldr r3, [r7, #0] + 800d84e: 781b ldrb r3, [r3, #0] + 800d850: 009b lsls r3, r3, #2 + 800d852: 441a add r2, r3 + 800d854: 8bbb ldrh r3, [r7, #28] + 800d856: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d85a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d85e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d862: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d866: b29b uxth r3, r3 + 800d868: 8013 strh r3, [r2, #0] + 800d86a: e1ea b.n 800dc42 } else { /* Configure NAK status for OUT Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); - 800c5bc: 687a ldr r2, [r7, #4] - 800c5be: 683b ldr r3, [r7, #0] - 800c5c0: 781b ldrb r3, [r3, #0] - 800c5c2: 009b lsls r3, r3, #2 - 800c5c4: 4413 add r3, r2 - 800c5c6: 881b ldrh r3, [r3, #0] - 800c5c8: b29b uxth r3, r3 - 800c5ca: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800c5ce: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c5d2: 83fb strh r3, [r7, #30] - 800c5d4: 8bfb ldrh r3, [r7, #30] - 800c5d6: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 800c5da: 83fb strh r3, [r7, #30] - 800c5dc: 687a ldr r2, [r7, #4] - 800c5de: 683b ldr r3, [r7, #0] - 800c5e0: 781b ldrb r3, [r3, #0] - 800c5e2: 009b lsls r3, r3, #2 - 800c5e4: 441a add r2, r3 - 800c5e6: 8bfb ldrh r3, [r7, #30] - 800c5e8: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c5ec: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c5f0: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c5f4: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c5f8: b29b uxth r3, r3 - 800c5fa: 8013 strh r3, [r2, #0] - 800c5fc: e1c9 b.n 800c992 + 800d86c: 687a ldr r2, [r7, #4] + 800d86e: 683b ldr r3, [r7, #0] + 800d870: 781b ldrb r3, [r3, #0] + 800d872: 009b lsls r3, r3, #2 + 800d874: 4413 add r3, r2 + 800d876: 881b ldrh r3, [r3, #0] + 800d878: b29b uxth r3, r3 + 800d87a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800d87e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d882: 83fb strh r3, [r7, #30] + 800d884: 8bfb ldrh r3, [r7, #30] + 800d886: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 800d88a: 83fb strh r3, [r7, #30] + 800d88c: 687a ldr r2, [r7, #4] + 800d88e: 683b ldr r3, [r7, #0] + 800d890: 781b ldrb r3, [r3, #0] + 800d892: 009b lsls r3, r3, #2 + 800d894: 441a add r2, r3 + 800d896: 8bfb ldrh r3, [r7, #30] + 800d898: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d89c: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d8a0: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d8a4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d8a8: b29b uxth r3, r3 + 800d8aa: 8013 strh r3, [r2, #0] + 800d8ac: e1c9 b.n 800dc42 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->type == EP_TYPE_BULK) - 800c5fe: 683b ldr r3, [r7, #0] - 800c600: 78db ldrb r3, [r3, #3] - 800c602: 2b02 cmp r3, #2 - 800c604: d11e bne.n 800c644 + 800d8ae: 683b ldr r3, [r7, #0] + 800d8b0: 78db ldrb r3, [r3, #3] + 800d8b2: 2b02 cmp r3, #2 + 800d8b4: d11e bne.n 800d8f4 { /* Set bulk endpoint as double buffered */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); - 800c606: 687a ldr r2, [r7, #4] - 800c608: 683b ldr r3, [r7, #0] - 800c60a: 781b ldrb r3, [r3, #0] - 800c60c: 009b lsls r3, r3, #2 - 800c60e: 4413 add r3, r2 - 800c610: 881b ldrh r3, [r3, #0] - 800c612: b29b uxth r3, r3 - 800c614: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c618: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c61c: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 - 800c620: 687a ldr r2, [r7, #4] - 800c622: 683b ldr r3, [r7, #0] - 800c624: 781b ldrb r3, [r3, #0] - 800c626: 009b lsls r3, r3, #2 - 800c628: 441a add r2, r3 - 800c62a: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 - 800c62e: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c632: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c636: f443 4301 orr.w r3, r3, #33024 ; 0x8100 - 800c63a: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c63e: b29b uxth r3, r3 - 800c640: 8013 strh r3, [r2, #0] - 800c642: e01d b.n 800c680 + 800d8b6: 687a ldr r2, [r7, #4] + 800d8b8: 683b ldr r3, [r7, #0] + 800d8ba: 781b ldrb r3, [r3, #0] + 800d8bc: 009b lsls r3, r3, #2 + 800d8be: 4413 add r3, r2 + 800d8c0: 881b ldrh r3, [r3, #0] + 800d8c2: b29b uxth r3, r3 + 800d8c4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d8c8: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d8cc: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 + 800d8d0: 687a ldr r2, [r7, #4] + 800d8d2: 683b ldr r3, [r7, #0] + 800d8d4: 781b ldrb r3, [r3, #0] + 800d8d6: 009b lsls r3, r3, #2 + 800d8d8: 441a add r2, r3 + 800d8da: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 + 800d8de: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d8e2: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d8e6: f443 4301 orr.w r3, r3, #33024 ; 0x8100 + 800d8ea: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d8ee: b29b uxth r3, r3 + 800d8f0: 8013 strh r3, [r2, #0] + 800d8f2: e01d b.n 800d930 } else { /* Set the ISOC endpoint in double buffer mode */ PCD_CLEAR_EP_KIND(USBx, ep->num); - 800c644: 687a ldr r2, [r7, #4] - 800c646: 683b ldr r3, [r7, #0] - 800c648: 781b ldrb r3, [r3, #0] - 800c64a: 009b lsls r3, r3, #2 - 800c64c: 4413 add r3, r2 - 800c64e: 881b ldrh r3, [r3, #0] - 800c650: b29b uxth r3, r3 - 800c652: f423 43e2 bic.w r3, r3, #28928 ; 0x7100 - 800c656: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c65a: f8a7 3064 strh.w r3, [r7, #100] ; 0x64 - 800c65e: 687a ldr r2, [r7, #4] - 800c660: 683b ldr r3, [r7, #0] - 800c662: 781b ldrb r3, [r3, #0] - 800c664: 009b lsls r3, r3, #2 - 800c666: 441a add r2, r3 - 800c668: f8b7 3064 ldrh.w r3, [r7, #100] ; 0x64 - 800c66c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c670: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c674: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c678: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c67c: b29b uxth r3, r3 - 800c67e: 8013 strh r3, [r2, #0] + 800d8f4: 687a ldr r2, [r7, #4] + 800d8f6: 683b ldr r3, [r7, #0] + 800d8f8: 781b ldrb r3, [r3, #0] + 800d8fa: 009b lsls r3, r3, #2 + 800d8fc: 4413 add r3, r2 + 800d8fe: 881b ldrh r3, [r3, #0] + 800d900: b29b uxth r3, r3 + 800d902: f423 43e2 bic.w r3, r3, #28928 ; 0x7100 + 800d906: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d90a: f8a7 3064 strh.w r3, [r7, #100] ; 0x64 + 800d90e: 687a ldr r2, [r7, #4] + 800d910: 683b ldr r3, [r7, #0] + 800d912: 781b ldrb r3, [r3, #0] + 800d914: 009b lsls r3, r3, #2 + 800d916: 441a add r2, r3 + 800d918: f8b7 3064 ldrh.w r3, [r7, #100] ; 0x64 + 800d91c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d920: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d924: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800d928: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d92c: b29b uxth r3, r3 + 800d92e: 8013 strh r3, [r2, #0] } /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); - 800c680: 687b ldr r3, [r7, #4] - 800c682: 65fb str r3, [r7, #92] ; 0x5c - 800c684: 687b ldr r3, [r7, #4] - 800c686: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800c68a: b29b uxth r3, r3 - 800c68c: 461a mov r2, r3 - 800c68e: 6dfb ldr r3, [r7, #92] ; 0x5c - 800c690: 4413 add r3, r2 - 800c692: 65fb str r3, [r7, #92] ; 0x5c - 800c694: 683b ldr r3, [r7, #0] - 800c696: 781b ldrb r3, [r3, #0] - 800c698: 00da lsls r2, r3, #3 - 800c69a: 6dfb ldr r3, [r7, #92] ; 0x5c - 800c69c: 4413 add r3, r2 - 800c69e: f503 6380 add.w r3, r3, #1024 ; 0x400 - 800c6a2: 65bb str r3, [r7, #88] ; 0x58 - 800c6a4: 683b ldr r3, [r7, #0] - 800c6a6: 891b ldrh r3, [r3, #8] - 800c6a8: 085b lsrs r3, r3, #1 - 800c6aa: b29b uxth r3, r3 - 800c6ac: 005b lsls r3, r3, #1 - 800c6ae: b29a uxth r2, r3 - 800c6b0: 6dbb ldr r3, [r7, #88] ; 0x58 - 800c6b2: 801a strh r2, [r3, #0] - 800c6b4: 687b ldr r3, [r7, #4] - 800c6b6: 657b str r3, [r7, #84] ; 0x54 - 800c6b8: 687b ldr r3, [r7, #4] - 800c6ba: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800c6be: b29b uxth r3, r3 - 800c6c0: 461a mov r2, r3 - 800c6c2: 6d7b ldr r3, [r7, #84] ; 0x54 - 800c6c4: 4413 add r3, r2 - 800c6c6: 657b str r3, [r7, #84] ; 0x54 - 800c6c8: 683b ldr r3, [r7, #0] - 800c6ca: 781b ldrb r3, [r3, #0] - 800c6cc: 00da lsls r2, r3, #3 - 800c6ce: 6d7b ldr r3, [r7, #84] ; 0x54 - 800c6d0: 4413 add r3, r2 - 800c6d2: f203 4304 addw r3, r3, #1028 ; 0x404 - 800c6d6: 653b str r3, [r7, #80] ; 0x50 - 800c6d8: 683b ldr r3, [r7, #0] - 800c6da: 895b ldrh r3, [r3, #10] - 800c6dc: 085b lsrs r3, r3, #1 - 800c6de: b29b uxth r3, r3 - 800c6e0: 005b lsls r3, r3, #1 - 800c6e2: b29a uxth r2, r3 - 800c6e4: 6d3b ldr r3, [r7, #80] ; 0x50 - 800c6e6: 801a strh r2, [r3, #0] + 800d930: 687b ldr r3, [r7, #4] + 800d932: 65fb str r3, [r7, #92] ; 0x5c + 800d934: 687b ldr r3, [r7, #4] + 800d936: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800d93a: b29b uxth r3, r3 + 800d93c: 461a mov r2, r3 + 800d93e: 6dfb ldr r3, [r7, #92] ; 0x5c + 800d940: 4413 add r3, r2 + 800d942: 65fb str r3, [r7, #92] ; 0x5c + 800d944: 683b ldr r3, [r7, #0] + 800d946: 781b ldrb r3, [r3, #0] + 800d948: 00da lsls r2, r3, #3 + 800d94a: 6dfb ldr r3, [r7, #92] ; 0x5c + 800d94c: 4413 add r3, r2 + 800d94e: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800d952: 65bb str r3, [r7, #88] ; 0x58 + 800d954: 683b ldr r3, [r7, #0] + 800d956: 891b ldrh r3, [r3, #8] + 800d958: 085b lsrs r3, r3, #1 + 800d95a: b29b uxth r3, r3 + 800d95c: 005b lsls r3, r3, #1 + 800d95e: b29a uxth r2, r3 + 800d960: 6dbb ldr r3, [r7, #88] ; 0x58 + 800d962: 801a strh r2, [r3, #0] + 800d964: 687b ldr r3, [r7, #4] + 800d966: 657b str r3, [r7, #84] ; 0x54 + 800d968: 687b ldr r3, [r7, #4] + 800d96a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800d96e: b29b uxth r3, r3 + 800d970: 461a mov r2, r3 + 800d972: 6d7b ldr r3, [r7, #84] ; 0x54 + 800d974: 4413 add r3, r2 + 800d976: 657b str r3, [r7, #84] ; 0x54 + 800d978: 683b ldr r3, [r7, #0] + 800d97a: 781b ldrb r3, [r3, #0] + 800d97c: 00da lsls r2, r3, #3 + 800d97e: 6d7b ldr r3, [r7, #84] ; 0x54 + 800d980: 4413 add r3, r2 + 800d982: f203 4304 addw r3, r3, #1028 ; 0x404 + 800d986: 653b str r3, [r7, #80] ; 0x50 + 800d988: 683b ldr r3, [r7, #0] + 800d98a: 895b ldrh r3, [r3, #10] + 800d98c: 085b lsrs r3, r3, #1 + 800d98e: b29b uxth r3, r3 + 800d990: 005b lsls r3, r3, #1 + 800d992: b29a uxth r2, r3 + 800d994: 6d3b ldr r3, [r7, #80] ; 0x50 + 800d996: 801a strh r2, [r3, #0] if (ep->is_in == 0U) - 800c6e8: 683b ldr r3, [r7, #0] - 800c6ea: 785b ldrb r3, [r3, #1] - 800c6ec: 2b00 cmp r3, #0 - 800c6ee: f040 8093 bne.w 800c818 + 800d998: 683b ldr r3, [r7, #0] + 800d99a: 785b ldrb r3, [r3, #1] + 800d99c: 2b00 cmp r3, #0 + 800d99e: f040 8093 bne.w 800dac8 { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800c6f2: 687a ldr r2, [r7, #4] - 800c6f4: 683b ldr r3, [r7, #0] - 800c6f6: 781b ldrb r3, [r3, #0] - 800c6f8: 009b lsls r3, r3, #2 - 800c6fa: 4413 add r3, r2 - 800c6fc: 881b ldrh r3, [r3, #0] - 800c6fe: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 - 800c702: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 - 800c706: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800c70a: 2b00 cmp r3, #0 - 800c70c: d01b beq.n 800c746 - 800c70e: 687a ldr r2, [r7, #4] - 800c710: 683b ldr r3, [r7, #0] - 800c712: 781b ldrb r3, [r3, #0] - 800c714: 009b lsls r3, r3, #2 - 800c716: 4413 add r3, r2 - 800c718: 881b ldrh r3, [r3, #0] - 800c71a: b29b uxth r3, r3 - 800c71c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c720: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c724: 87fb strh r3, [r7, #62] ; 0x3e - 800c726: 687a ldr r2, [r7, #4] - 800c728: 683b ldr r3, [r7, #0] - 800c72a: 781b ldrb r3, [r3, #0] - 800c72c: 009b lsls r3, r3, #2 - 800c72e: 441a add r2, r3 - 800c730: 8ffb ldrh r3, [r7, #62] ; 0x3e - 800c732: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c736: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c73a: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800c73e: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c742: b29b uxth r3, r3 - 800c744: 8013 strh r3, [r2, #0] + 800d9a2: 687a ldr r2, [r7, #4] + 800d9a4: 683b ldr r3, [r7, #0] + 800d9a6: 781b ldrb r3, [r3, #0] + 800d9a8: 009b lsls r3, r3, #2 + 800d9aa: 4413 add r3, r2 + 800d9ac: 881b ldrh r3, [r3, #0] + 800d9ae: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + 800d9b2: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 800d9b6: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800d9ba: 2b00 cmp r3, #0 + 800d9bc: d01b beq.n 800d9f6 + 800d9be: 687a ldr r2, [r7, #4] + 800d9c0: 683b ldr r3, [r7, #0] + 800d9c2: 781b ldrb r3, [r3, #0] + 800d9c4: 009b lsls r3, r3, #2 + 800d9c6: 4413 add r3, r2 + 800d9c8: 881b ldrh r3, [r3, #0] + 800d9ca: b29b uxth r3, r3 + 800d9cc: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800d9d0: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800d9d4: 87fb strh r3, [r7, #62] ; 0x3e + 800d9d6: 687a ldr r2, [r7, #4] + 800d9d8: 683b ldr r3, [r7, #0] + 800d9da: 781b ldrb r3, [r3, #0] + 800d9dc: 009b lsls r3, r3, #2 + 800d9de: 441a add r2, r3 + 800d9e0: 8ffb ldrh r3, [r7, #62] ; 0x3e + 800d9e2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800d9e6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800d9ea: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800d9ee: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800d9f2: b29b uxth r3, r3 + 800d9f4: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800c746: 687a ldr r2, [r7, #4] - 800c748: 683b ldr r3, [r7, #0] - 800c74a: 781b ldrb r3, [r3, #0] - 800c74c: 009b lsls r3, r3, #2 - 800c74e: 4413 add r3, r2 - 800c750: 881b ldrh r3, [r3, #0] - 800c752: 87bb strh r3, [r7, #60] ; 0x3c - 800c754: 8fbb ldrh r3, [r7, #60] ; 0x3c - 800c756: f003 0340 and.w r3, r3, #64 ; 0x40 - 800c75a: 2b00 cmp r3, #0 - 800c75c: d01b beq.n 800c796 - 800c75e: 687a ldr r2, [r7, #4] - 800c760: 683b ldr r3, [r7, #0] - 800c762: 781b ldrb r3, [r3, #0] - 800c764: 009b lsls r3, r3, #2 - 800c766: 4413 add r3, r2 - 800c768: 881b ldrh r3, [r3, #0] - 800c76a: b29b uxth r3, r3 - 800c76c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c770: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c774: 877b strh r3, [r7, #58] ; 0x3a - 800c776: 687a ldr r2, [r7, #4] - 800c778: 683b ldr r3, [r7, #0] - 800c77a: 781b ldrb r3, [r3, #0] - 800c77c: 009b lsls r3, r3, #2 - 800c77e: 441a add r2, r3 - 800c780: 8f7b ldrh r3, [r7, #58] ; 0x3a - 800c782: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c786: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c78a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c78e: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800c792: b29b uxth r3, r3 - 800c794: 8013 strh r3, [r2, #0] + 800d9f6: 687a ldr r2, [r7, #4] + 800d9f8: 683b ldr r3, [r7, #0] + 800d9fa: 781b ldrb r3, [r3, #0] + 800d9fc: 009b lsls r3, r3, #2 + 800d9fe: 4413 add r3, r2 + 800da00: 881b ldrh r3, [r3, #0] + 800da02: 87bb strh r3, [r7, #60] ; 0x3c + 800da04: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800da06: f003 0340 and.w r3, r3, #64 ; 0x40 + 800da0a: 2b00 cmp r3, #0 + 800da0c: d01b beq.n 800da46 + 800da0e: 687a ldr r2, [r7, #4] + 800da10: 683b ldr r3, [r7, #0] + 800da12: 781b ldrb r3, [r3, #0] + 800da14: 009b lsls r3, r3, #2 + 800da16: 4413 add r3, r2 + 800da18: 881b ldrh r3, [r3, #0] + 800da1a: b29b uxth r3, r3 + 800da1c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800da20: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800da24: 877b strh r3, [r7, #58] ; 0x3a + 800da26: 687a ldr r2, [r7, #4] + 800da28: 683b ldr r3, [r7, #0] + 800da2a: 781b ldrb r3, [r3, #0] + 800da2c: 009b lsls r3, r3, #2 + 800da2e: 441a add r2, r3 + 800da30: 8f7b ldrh r3, [r7, #58] ; 0x3a + 800da32: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800da36: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800da3a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800da3e: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800da42: b29b uxth r3, r3 + 800da44: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - 800c796: 687a ldr r2, [r7, #4] - 800c798: 683b ldr r3, [r7, #0] - 800c79a: 781b ldrb r3, [r3, #0] - 800c79c: 009b lsls r3, r3, #2 - 800c79e: 4413 add r3, r2 - 800c7a0: 881b ldrh r3, [r3, #0] - 800c7a2: b29b uxth r3, r3 - 800c7a4: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800c7a8: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c7ac: 873b strh r3, [r7, #56] ; 0x38 - 800c7ae: 8f3b ldrh r3, [r7, #56] ; 0x38 - 800c7b0: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 800c7b4: 873b strh r3, [r7, #56] ; 0x38 - 800c7b6: 8f3b ldrh r3, [r7, #56] ; 0x38 - 800c7b8: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 800c7bc: 873b strh r3, [r7, #56] ; 0x38 - 800c7be: 687a ldr r2, [r7, #4] - 800c7c0: 683b ldr r3, [r7, #0] - 800c7c2: 781b ldrb r3, [r3, #0] - 800c7c4: 009b lsls r3, r3, #2 - 800c7c6: 441a add r2, r3 - 800c7c8: 8f3b ldrh r3, [r7, #56] ; 0x38 - 800c7ca: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c7ce: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c7d2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c7d6: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c7da: b29b uxth r3, r3 - 800c7dc: 8013 strh r3, [r2, #0] + 800da46: 687a ldr r2, [r7, #4] + 800da48: 683b ldr r3, [r7, #0] + 800da4a: 781b ldrb r3, [r3, #0] + 800da4c: 009b lsls r3, r3, #2 + 800da4e: 4413 add r3, r2 + 800da50: 881b ldrh r3, [r3, #0] + 800da52: b29b uxth r3, r3 + 800da54: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800da58: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800da5c: 873b strh r3, [r7, #56] ; 0x38 + 800da5e: 8f3b ldrh r3, [r7, #56] ; 0x38 + 800da60: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800da64: 873b strh r3, [r7, #56] ; 0x38 + 800da66: 8f3b ldrh r3, [r7, #56] ; 0x38 + 800da68: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 800da6c: 873b strh r3, [r7, #56] ; 0x38 + 800da6e: 687a ldr r2, [r7, #4] + 800da70: 683b ldr r3, [r7, #0] + 800da72: 781b ldrb r3, [r3, #0] + 800da74: 009b lsls r3, r3, #2 + 800da76: 441a add r2, r3 + 800da78: 8f3b ldrh r3, [r7, #56] ; 0x38 + 800da7a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800da7e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800da82: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800da86: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800da8a: b29b uxth r3, r3 + 800da8c: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800c7de: 687a ldr r2, [r7, #4] - 800c7e0: 683b ldr r3, [r7, #0] - 800c7e2: 781b ldrb r3, [r3, #0] - 800c7e4: 009b lsls r3, r3, #2 - 800c7e6: 4413 add r3, r2 - 800c7e8: 881b ldrh r3, [r3, #0] - 800c7ea: b29b uxth r3, r3 - 800c7ec: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c7f0: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c7f4: 86fb strh r3, [r7, #54] ; 0x36 - 800c7f6: 687a ldr r2, [r7, #4] - 800c7f8: 683b ldr r3, [r7, #0] - 800c7fa: 781b ldrb r3, [r3, #0] - 800c7fc: 009b lsls r3, r3, #2 - 800c7fe: 441a add r2, r3 - 800c800: 8efb ldrh r3, [r7, #54] ; 0x36 - 800c802: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c806: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c80a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c80e: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c812: b29b uxth r3, r3 - 800c814: 8013 strh r3, [r2, #0] - 800c816: e0bc b.n 800c992 + 800da8e: 687a ldr r2, [r7, #4] + 800da90: 683b ldr r3, [r7, #0] + 800da92: 781b ldrb r3, [r3, #0] + 800da94: 009b lsls r3, r3, #2 + 800da96: 4413 add r3, r2 + 800da98: 881b ldrh r3, [r3, #0] + 800da9a: b29b uxth r3, r3 + 800da9c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800daa0: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800daa4: 86fb strh r3, [r7, #54] ; 0x36 + 800daa6: 687a ldr r2, [r7, #4] + 800daa8: 683b ldr r3, [r7, #0] + 800daaa: 781b ldrb r3, [r3, #0] + 800daac: 009b lsls r3, r3, #2 + 800daae: 441a add r2, r3 + 800dab0: 8efb ldrh r3, [r7, #54] ; 0x36 + 800dab2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dab6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800daba: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dabe: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dac2: b29b uxth r3, r3 + 800dac4: 8013 strh r3, [r2, #0] + 800dac6: e0bc b.n 800dc42 } else { /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800c818: 687a ldr r2, [r7, #4] - 800c81a: 683b ldr r3, [r7, #0] - 800c81c: 781b ldrb r3, [r3, #0] - 800c81e: 009b lsls r3, r3, #2 - 800c820: 4413 add r3, r2 - 800c822: 881b ldrh r3, [r3, #0] - 800c824: f8a7 304e strh.w r3, [r7, #78] ; 0x4e - 800c828: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e - 800c82c: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800c830: 2b00 cmp r3, #0 - 800c832: d01d beq.n 800c870 - 800c834: 687a ldr r2, [r7, #4] - 800c836: 683b ldr r3, [r7, #0] - 800c838: 781b ldrb r3, [r3, #0] - 800c83a: 009b lsls r3, r3, #2 - 800c83c: 4413 add r3, r2 - 800c83e: 881b ldrh r3, [r3, #0] - 800c840: b29b uxth r3, r3 - 800c842: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c846: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c84a: f8a7 304c strh.w r3, [r7, #76] ; 0x4c - 800c84e: 687a ldr r2, [r7, #4] - 800c850: 683b ldr r3, [r7, #0] - 800c852: 781b ldrb r3, [r3, #0] - 800c854: 009b lsls r3, r3, #2 - 800c856: 441a add r2, r3 - 800c858: f8b7 304c ldrh.w r3, [r7, #76] ; 0x4c - 800c85c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c860: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c864: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800c868: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c86c: b29b uxth r3, r3 - 800c86e: 8013 strh r3, [r2, #0] + 800dac8: 687a ldr r2, [r7, #4] + 800daca: 683b ldr r3, [r7, #0] + 800dacc: 781b ldrb r3, [r3, #0] + 800dace: 009b lsls r3, r3, #2 + 800dad0: 4413 add r3, r2 + 800dad2: 881b ldrh r3, [r3, #0] + 800dad4: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + 800dad8: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 800dadc: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800dae0: 2b00 cmp r3, #0 + 800dae2: d01d beq.n 800db20 + 800dae4: 687a ldr r2, [r7, #4] + 800dae6: 683b ldr r3, [r7, #0] + 800dae8: 781b ldrb r3, [r3, #0] + 800daea: 009b lsls r3, r3, #2 + 800daec: 4413 add r3, r2 + 800daee: 881b ldrh r3, [r3, #0] + 800daf0: b29b uxth r3, r3 + 800daf2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800daf6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dafa: f8a7 304c strh.w r3, [r7, #76] ; 0x4c + 800dafe: 687a ldr r2, [r7, #4] + 800db00: 683b ldr r3, [r7, #0] + 800db02: 781b ldrb r3, [r3, #0] + 800db04: 009b lsls r3, r3, #2 + 800db06: 441a add r2, r3 + 800db08: f8b7 304c ldrh.w r3, [r7, #76] ; 0x4c + 800db0c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800db10: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800db14: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800db18: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800db1c: b29b uxth r3, r3 + 800db1e: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800c870: 687a ldr r2, [r7, #4] - 800c872: 683b ldr r3, [r7, #0] - 800c874: 781b ldrb r3, [r3, #0] - 800c876: 009b lsls r3, r3, #2 - 800c878: 4413 add r3, r2 - 800c87a: 881b ldrh r3, [r3, #0] - 800c87c: f8a7 304a strh.w r3, [r7, #74] ; 0x4a - 800c880: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a - 800c884: f003 0340 and.w r3, r3, #64 ; 0x40 - 800c888: 2b00 cmp r3, #0 - 800c88a: d01d beq.n 800c8c8 - 800c88c: 687a ldr r2, [r7, #4] - 800c88e: 683b ldr r3, [r7, #0] - 800c890: 781b ldrb r3, [r3, #0] - 800c892: 009b lsls r3, r3, #2 - 800c894: 4413 add r3, r2 - 800c896: 881b ldrh r3, [r3, #0] - 800c898: b29b uxth r3, r3 - 800c89a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c89e: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c8a2: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 - 800c8a6: 687a ldr r2, [r7, #4] - 800c8a8: 683b ldr r3, [r7, #0] - 800c8aa: 781b ldrb r3, [r3, #0] - 800c8ac: 009b lsls r3, r3, #2 - 800c8ae: 441a add r2, r3 - 800c8b0: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 - 800c8b4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c8b8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c8bc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c8c0: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800c8c4: b29b uxth r3, r3 - 800c8c6: 8013 strh r3, [r2, #0] + 800db20: 687a ldr r2, [r7, #4] + 800db22: 683b ldr r3, [r7, #0] + 800db24: 781b ldrb r3, [r3, #0] + 800db26: 009b lsls r3, r3, #2 + 800db28: 4413 add r3, r2 + 800db2a: 881b ldrh r3, [r3, #0] + 800db2c: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + 800db30: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800db34: f003 0340 and.w r3, r3, #64 ; 0x40 + 800db38: 2b00 cmp r3, #0 + 800db3a: d01d beq.n 800db78 + 800db3c: 687a ldr r2, [r7, #4] + 800db3e: 683b ldr r3, [r7, #0] + 800db40: 781b ldrb r3, [r3, #0] + 800db42: 009b lsls r3, r3, #2 + 800db44: 4413 add r3, r2 + 800db46: 881b ldrh r3, [r3, #0] + 800db48: b29b uxth r3, r3 + 800db4a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800db4e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800db52: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + 800db56: 687a ldr r2, [r7, #4] + 800db58: 683b ldr r3, [r7, #0] + 800db5a: 781b ldrb r3, [r3, #0] + 800db5c: 009b lsls r3, r3, #2 + 800db5e: 441a add r2, r3 + 800db60: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 + 800db64: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800db68: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800db6c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800db70: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800db74: b29b uxth r3, r3 + 800db76: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) - 800c8c8: 683b ldr r3, [r7, #0] - 800c8ca: 78db ldrb r3, [r3, #3] - 800c8cc: 2b01 cmp r3, #1 - 800c8ce: d024 beq.n 800c91a + 800db78: 683b ldr r3, [r7, #0] + 800db7a: 78db ldrb r3, [r3, #3] + 800db7c: 2b01 cmp r3, #1 + 800db7e: d024 beq.n 800dbca { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - 800c8d0: 687a ldr r2, [r7, #4] - 800c8d2: 683b ldr r3, [r7, #0] - 800c8d4: 781b ldrb r3, [r3, #0] - 800c8d6: 009b lsls r3, r3, #2 - 800c8d8: 4413 add r3, r2 - 800c8da: 881b ldrh r3, [r3, #0] - 800c8dc: b29b uxth r3, r3 - 800c8de: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c8e2: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c8e6: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 - 800c8ea: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 - 800c8ee: f083 0320 eor.w r3, r3, #32 - 800c8f2: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 - 800c8f6: 687a ldr r2, [r7, #4] - 800c8f8: 683b ldr r3, [r7, #0] - 800c8fa: 781b ldrb r3, [r3, #0] - 800c8fc: 009b lsls r3, r3, #2 - 800c8fe: 441a add r2, r3 - 800c900: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 - 800c904: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c908: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c90c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c910: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c914: b29b uxth r3, r3 - 800c916: 8013 strh r3, [r2, #0] - 800c918: e01d b.n 800c956 + 800db80: 687a ldr r2, [r7, #4] + 800db82: 683b ldr r3, [r7, #0] + 800db84: 781b ldrb r3, [r3, #0] + 800db86: 009b lsls r3, r3, #2 + 800db88: 4413 add r3, r2 + 800db8a: 881b ldrh r3, [r3, #0] + 800db8c: b29b uxth r3, r3 + 800db8e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800db92: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800db96: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + 800db9a: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800db9e: f083 0320 eor.w r3, r3, #32 + 800dba2: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + 800dba6: 687a ldr r2, [r7, #4] + 800dba8: 683b ldr r3, [r7, #0] + 800dbaa: 781b ldrb r3, [r3, #0] + 800dbac: 009b lsls r3, r3, #2 + 800dbae: 441a add r2, r3 + 800dbb0: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800dbb4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dbb8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dbbc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dbc0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dbc4: b29b uxth r3, r3 + 800dbc6: 8013 strh r3, [r2, #0] + 800dbc8: e01d b.n 800dc06 } else { /* Configure TX Endpoint to disabled state */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800c91a: 687a ldr r2, [r7, #4] - 800c91c: 683b ldr r3, [r7, #0] - 800c91e: 781b ldrb r3, [r3, #0] - 800c920: 009b lsls r3, r3, #2 - 800c922: 4413 add r3, r2 - 800c924: 881b ldrh r3, [r3, #0] - 800c926: b29b uxth r3, r3 - 800c928: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c92c: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800c930: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 - 800c934: 687a ldr r2, [r7, #4] - 800c936: 683b ldr r3, [r7, #0] - 800c938: 781b ldrb r3, [r3, #0] - 800c93a: 009b lsls r3, r3, #2 - 800c93c: 441a add r2, r3 - 800c93e: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 - 800c942: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c946: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c94a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c94e: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c952: b29b uxth r3, r3 - 800c954: 8013 strh r3, [r2, #0] + 800dbca: 687a ldr r2, [r7, #4] + 800dbcc: 683b ldr r3, [r7, #0] + 800dbce: 781b ldrb r3, [r3, #0] + 800dbd0: 009b lsls r3, r3, #2 + 800dbd2: 4413 add r3, r2 + 800dbd4: 881b ldrh r3, [r3, #0] + 800dbd6: b29b uxth r3, r3 + 800dbd8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800dbdc: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800dbe0: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + 800dbe4: 687a ldr r2, [r7, #4] + 800dbe6: 683b ldr r3, [r7, #0] + 800dbe8: 781b ldrb r3, [r3, #0] + 800dbea: 009b lsls r3, r3, #2 + 800dbec: 441a add r2, r3 + 800dbee: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800dbf2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dbf6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dbfa: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dbfe: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dc02: b29b uxth r3, r3 + 800dc04: 8013 strh r3, [r2, #0] } PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - 800c956: 687a ldr r2, [r7, #4] - 800c958: 683b ldr r3, [r7, #0] - 800c95a: 781b ldrb r3, [r3, #0] - 800c95c: 009b lsls r3, r3, #2 - 800c95e: 4413 add r3, r2 - 800c960: 881b ldrh r3, [r3, #0] - 800c962: b29b uxth r3, r3 - 800c964: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800c968: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c96c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 - 800c970: 687a ldr r2, [r7, #4] - 800c972: 683b ldr r3, [r7, #0] - 800c974: 781b ldrb r3, [r3, #0] - 800c976: 009b lsls r3, r3, #2 - 800c978: 441a add r2, r3 - 800c97a: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 - 800c97e: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800c982: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800c986: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800c98a: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800c98e: b29b uxth r3, r3 - 800c990: 8013 strh r3, [r2, #0] + 800dc06: 687a ldr r2, [r7, #4] + 800dc08: 683b ldr r3, [r7, #0] + 800dc0a: 781b ldrb r3, [r3, #0] + 800dc0c: 009b lsls r3, r3, #2 + 800dc0e: 4413 add r3, r2 + 800dc10: 881b ldrh r3, [r3, #0] + 800dc12: b29b uxth r3, r3 + 800dc14: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800dc18: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dc1c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + 800dc20: 687a ldr r2, [r7, #4] + 800dc22: 683b ldr r3, [r7, #0] + 800dc24: 781b ldrb r3, [r3, #0] + 800dc26: 009b lsls r3, r3, #2 + 800dc28: 441a add r2, r3 + 800dc2a: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 800dc2e: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dc32: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dc36: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dc3a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dc3e: b29b uxth r3, r3 + 800dc40: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return ret; - 800c992: f897 306f ldrb.w r3, [r7, #111] ; 0x6f + 800dc42: f897 306f ldrb.w r3, [r7, #111] ; 0x6f } - 800c996: 4618 mov r0, r3 - 800c998: 3774 adds r7, #116 ; 0x74 - 800c99a: 46bd mov sp, r7 - 800c99c: f85d 7b04 ldr.w r7, [sp], #4 - 800c9a0: 4770 bx lr - 800c9a2: bf00 nop + 800dc46: 4618 mov r0, r3 + 800dc48: 3774 adds r7, #116 ; 0x74 + 800dc4a: 46bd mov sp, r7 + 800dc4c: f85d 7b04 ldr.w r7, [sp], #4 + 800dc50: 4770 bx lr + 800dc52: bf00 nop -0800c9a4 : +0800dc54 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - 800c9a4: b480 push {r7} - 800c9a6: b08d sub sp, #52 ; 0x34 - 800c9a8: af00 add r7, sp, #0 - 800c9aa: 6078 str r0, [r7, #4] - 800c9ac: 6039 str r1, [r7, #0] + 800dc54: b480 push {r7} + 800dc56: b08d sub sp, #52 ; 0x34 + 800dc58: af00 add r7, sp, #0 + 800dc5a: 6078 str r0, [r7, #4] + 800dc5c: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) - 800c9ae: 683b ldr r3, [r7, #0] - 800c9b0: 7b1b ldrb r3, [r3, #12] - 800c9b2: 2b00 cmp r3, #0 - 800c9b4: f040 808e bne.w 800cad4 + 800dc5e: 683b ldr r3, [r7, #0] + 800dc60: 7b1b ldrb r3, [r3, #12] + 800dc62: 2b00 cmp r3, #0 + 800dc64: f040 808e bne.w 800dd84 { if (ep->is_in != 0U) - 800c9b8: 683b ldr r3, [r7, #0] - 800c9ba: 785b ldrb r3, [r3, #1] - 800c9bc: 2b00 cmp r3, #0 - 800c9be: d044 beq.n 800ca4a + 800dc68: 683b ldr r3, [r7, #0] + 800dc6a: 785b ldrb r3, [r3, #1] + 800dc6c: 2b00 cmp r3, #0 + 800dc6e: d044 beq.n 800dcfa { PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800c9c0: 687a ldr r2, [r7, #4] - 800c9c2: 683b ldr r3, [r7, #0] - 800c9c4: 781b ldrb r3, [r3, #0] - 800c9c6: 009b lsls r3, r3, #2 - 800c9c8: 4413 add r3, r2 - 800c9ca: 881b ldrh r3, [r3, #0] - 800c9cc: 81bb strh r3, [r7, #12] - 800c9ce: 89bb ldrh r3, [r7, #12] - 800c9d0: f003 0340 and.w r3, r3, #64 ; 0x40 - 800c9d4: 2b00 cmp r3, #0 - 800c9d6: d01b beq.n 800ca10 - 800c9d8: 687a ldr r2, [r7, #4] - 800c9da: 683b ldr r3, [r7, #0] - 800c9dc: 781b ldrb r3, [r3, #0] - 800c9de: 009b lsls r3, r3, #2 - 800c9e0: 4413 add r3, r2 - 800c9e2: 881b ldrh r3, [r3, #0] - 800c9e4: b29b uxth r3, r3 - 800c9e6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800c9ea: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800c9ee: 817b strh r3, [r7, #10] - 800c9f0: 687a ldr r2, [r7, #4] - 800c9f2: 683b ldr r3, [r7, #0] - 800c9f4: 781b ldrb r3, [r3, #0] - 800c9f6: 009b lsls r3, r3, #2 - 800c9f8: 441a add r2, r3 - 800c9fa: 897b ldrh r3, [r7, #10] - 800c9fc: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ca00: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ca04: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800ca08: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800ca0c: b29b uxth r3, r3 - 800ca0e: 8013 strh r3, [r2, #0] + 800dc70: 687a ldr r2, [r7, #4] + 800dc72: 683b ldr r3, [r7, #0] + 800dc74: 781b ldrb r3, [r3, #0] + 800dc76: 009b lsls r3, r3, #2 + 800dc78: 4413 add r3, r2 + 800dc7a: 881b ldrh r3, [r3, #0] + 800dc7c: 81bb strh r3, [r7, #12] + 800dc7e: 89bb ldrh r3, [r7, #12] + 800dc80: f003 0340 and.w r3, r3, #64 ; 0x40 + 800dc84: 2b00 cmp r3, #0 + 800dc86: d01b beq.n 800dcc0 + 800dc88: 687a ldr r2, [r7, #4] + 800dc8a: 683b ldr r3, [r7, #0] + 800dc8c: 781b ldrb r3, [r3, #0] + 800dc8e: 009b lsls r3, r3, #2 + 800dc90: 4413 add r3, r2 + 800dc92: 881b ldrh r3, [r3, #0] + 800dc94: b29b uxth r3, r3 + 800dc96: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800dc9a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dc9e: 817b strh r3, [r7, #10] + 800dca0: 687a ldr r2, [r7, #4] + 800dca2: 683b ldr r3, [r7, #0] + 800dca4: 781b ldrb r3, [r3, #0] + 800dca6: 009b lsls r3, r3, #2 + 800dca8: 441a add r2, r3 + 800dcaa: 897b ldrh r3, [r7, #10] + 800dcac: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dcb0: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dcb4: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dcb8: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800dcbc: b29b uxth r3, r3 + 800dcbe: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800ca10: 687a ldr r2, [r7, #4] - 800ca12: 683b ldr r3, [r7, #0] - 800ca14: 781b ldrb r3, [r3, #0] - 800ca16: 009b lsls r3, r3, #2 - 800ca18: 4413 add r3, r2 - 800ca1a: 881b ldrh r3, [r3, #0] - 800ca1c: b29b uxth r3, r3 - 800ca1e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800ca22: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800ca26: 813b strh r3, [r7, #8] - 800ca28: 687a ldr r2, [r7, #4] - 800ca2a: 683b ldr r3, [r7, #0] - 800ca2c: 781b ldrb r3, [r3, #0] - 800ca2e: 009b lsls r3, r3, #2 - 800ca30: 441a add r2, r3 - 800ca32: 893b ldrh r3, [r7, #8] - 800ca34: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ca38: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ca3c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800ca40: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800ca44: b29b uxth r3, r3 - 800ca46: 8013 strh r3, [r2, #0] - 800ca48: e192 b.n 800cd70 + 800dcc0: 687a ldr r2, [r7, #4] + 800dcc2: 683b ldr r3, [r7, #0] + 800dcc4: 781b ldrb r3, [r3, #0] + 800dcc6: 009b lsls r3, r3, #2 + 800dcc8: 4413 add r3, r2 + 800dcca: 881b ldrh r3, [r3, #0] + 800dccc: b29b uxth r3, r3 + 800dcce: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800dcd2: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800dcd6: 813b strh r3, [r7, #8] + 800dcd8: 687a ldr r2, [r7, #4] + 800dcda: 683b ldr r3, [r7, #0] + 800dcdc: 781b ldrb r3, [r3, #0] + 800dcde: 009b lsls r3, r3, #2 + 800dce0: 441a add r2, r3 + 800dce2: 893b ldrh r3, [r7, #8] + 800dce4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dce8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dcec: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dcf0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dcf4: b29b uxth r3, r3 + 800dcf6: 8013 strh r3, [r2, #0] + 800dcf8: e192 b.n 800e020 } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800ca4a: 687a ldr r2, [r7, #4] - 800ca4c: 683b ldr r3, [r7, #0] - 800ca4e: 781b ldrb r3, [r3, #0] - 800ca50: 009b lsls r3, r3, #2 - 800ca52: 4413 add r3, r2 - 800ca54: 881b ldrh r3, [r3, #0] - 800ca56: 827b strh r3, [r7, #18] - 800ca58: 8a7b ldrh r3, [r7, #18] - 800ca5a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800ca5e: 2b00 cmp r3, #0 - 800ca60: d01b beq.n 800ca9a - 800ca62: 687a ldr r2, [r7, #4] - 800ca64: 683b ldr r3, [r7, #0] - 800ca66: 781b ldrb r3, [r3, #0] - 800ca68: 009b lsls r3, r3, #2 - 800ca6a: 4413 add r3, r2 - 800ca6c: 881b ldrh r3, [r3, #0] - 800ca6e: b29b uxth r3, r3 - 800ca70: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800ca74: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800ca78: 823b strh r3, [r7, #16] - 800ca7a: 687a ldr r2, [r7, #4] - 800ca7c: 683b ldr r3, [r7, #0] - 800ca7e: 781b ldrb r3, [r3, #0] - 800ca80: 009b lsls r3, r3, #2 - 800ca82: 441a add r2, r3 - 800ca84: 8a3b ldrh r3, [r7, #16] - 800ca86: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ca8a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ca8e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800ca92: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800ca96: b29b uxth r3, r3 - 800ca98: 8013 strh r3, [r2, #0] + 800dcfa: 687a ldr r2, [r7, #4] + 800dcfc: 683b ldr r3, [r7, #0] + 800dcfe: 781b ldrb r3, [r3, #0] + 800dd00: 009b lsls r3, r3, #2 + 800dd02: 4413 add r3, r2 + 800dd04: 881b ldrh r3, [r3, #0] + 800dd06: 827b strh r3, [r7, #18] + 800dd08: 8a7b ldrh r3, [r7, #18] + 800dd0a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800dd0e: 2b00 cmp r3, #0 + 800dd10: d01b beq.n 800dd4a + 800dd12: 687a ldr r2, [r7, #4] + 800dd14: 683b ldr r3, [r7, #0] + 800dd16: 781b ldrb r3, [r3, #0] + 800dd18: 009b lsls r3, r3, #2 + 800dd1a: 4413 add r3, r2 + 800dd1c: 881b ldrh r3, [r3, #0] + 800dd1e: b29b uxth r3, r3 + 800dd20: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800dd24: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dd28: 823b strh r3, [r7, #16] + 800dd2a: 687a ldr r2, [r7, #4] + 800dd2c: 683b ldr r3, [r7, #0] + 800dd2e: 781b ldrb r3, [r3, #0] + 800dd30: 009b lsls r3, r3, #2 + 800dd32: 441a add r2, r3 + 800dd34: 8a3b ldrh r3, [r7, #16] + 800dd36: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dd3a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dd3e: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800dd42: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dd46: b29b uxth r3, r3 + 800dd48: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - 800ca9a: 687a ldr r2, [r7, #4] - 800ca9c: 683b ldr r3, [r7, #0] - 800ca9e: 781b ldrb r3, [r3, #0] - 800caa0: 009b lsls r3, r3, #2 - 800caa2: 4413 add r3, r2 - 800caa4: 881b ldrh r3, [r3, #0] - 800caa6: b29b uxth r3, r3 - 800caa8: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800caac: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cab0: 81fb strh r3, [r7, #14] - 800cab2: 687a ldr r2, [r7, #4] - 800cab4: 683b ldr r3, [r7, #0] - 800cab6: 781b ldrb r3, [r3, #0] - 800cab8: 009b lsls r3, r3, #2 - 800caba: 441a add r2, r3 - 800cabc: 89fb ldrh r3, [r7, #14] - 800cabe: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cac2: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cac6: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800caca: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cace: b29b uxth r3, r3 - 800cad0: 8013 strh r3, [r2, #0] - 800cad2: e14d b.n 800cd70 + 800dd4a: 687a ldr r2, [r7, #4] + 800dd4c: 683b ldr r3, [r7, #0] + 800dd4e: 781b ldrb r3, [r3, #0] + 800dd50: 009b lsls r3, r3, #2 + 800dd52: 4413 add r3, r2 + 800dd54: 881b ldrh r3, [r3, #0] + 800dd56: b29b uxth r3, r3 + 800dd58: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800dd5c: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dd60: 81fb strh r3, [r7, #14] + 800dd62: 687a ldr r2, [r7, #4] + 800dd64: 683b ldr r3, [r7, #0] + 800dd66: 781b ldrb r3, [r3, #0] + 800dd68: 009b lsls r3, r3, #2 + 800dd6a: 441a add r2, r3 + 800dd6c: 89fb ldrh r3, [r7, #14] + 800dd6e: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dd72: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dd76: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dd7a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dd7e: b29b uxth r3, r3 + 800dd80: 8013 strh r3, [r2, #0] + 800dd82: e14d b.n 800e020 } #if (USE_USB_DOUBLE_BUFFER == 1U) /* Double Buffer */ else { if (ep->is_in == 0U) - 800cad4: 683b ldr r3, [r7, #0] - 800cad6: 785b ldrb r3, [r3, #1] - 800cad8: 2b00 cmp r3, #0 - 800cada: f040 80a5 bne.w 800cc28 + 800dd84: 683b ldr r3, [r7, #0] + 800dd86: 785b ldrb r3, [r3, #1] + 800dd88: 2b00 cmp r3, #0 + 800dd8a: f040 80a5 bne.w 800ded8 { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800cade: 687a ldr r2, [r7, #4] - 800cae0: 683b ldr r3, [r7, #0] - 800cae2: 781b ldrb r3, [r3, #0] - 800cae4: 009b lsls r3, r3, #2 - 800cae6: 4413 add r3, r2 - 800cae8: 881b ldrh r3, [r3, #0] - 800caea: 843b strh r3, [r7, #32] - 800caec: 8c3b ldrh r3, [r7, #32] - 800caee: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800caf2: 2b00 cmp r3, #0 - 800caf4: d01b beq.n 800cb2e - 800caf6: 687a ldr r2, [r7, #4] - 800caf8: 683b ldr r3, [r7, #0] - 800cafa: 781b ldrb r3, [r3, #0] - 800cafc: 009b lsls r3, r3, #2 - 800cafe: 4413 add r3, r2 - 800cb00: 881b ldrh r3, [r3, #0] - 800cb02: b29b uxth r3, r3 - 800cb04: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cb08: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cb0c: 83fb strh r3, [r7, #30] - 800cb0e: 687a ldr r2, [r7, #4] - 800cb10: 683b ldr r3, [r7, #0] - 800cb12: 781b ldrb r3, [r3, #0] - 800cb14: 009b lsls r3, r3, #2 - 800cb16: 441a add r2, r3 - 800cb18: 8bfb ldrh r3, [r7, #30] - 800cb1a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cb1e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cb22: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800cb26: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cb2a: b29b uxth r3, r3 - 800cb2c: 8013 strh r3, [r2, #0] + 800dd8e: 687a ldr r2, [r7, #4] + 800dd90: 683b ldr r3, [r7, #0] + 800dd92: 781b ldrb r3, [r3, #0] + 800dd94: 009b lsls r3, r3, #2 + 800dd96: 4413 add r3, r2 + 800dd98: 881b ldrh r3, [r3, #0] + 800dd9a: 843b strh r3, [r7, #32] + 800dd9c: 8c3b ldrh r3, [r7, #32] + 800dd9e: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800dda2: 2b00 cmp r3, #0 + 800dda4: d01b beq.n 800ddde + 800dda6: 687a ldr r2, [r7, #4] + 800dda8: 683b ldr r3, [r7, #0] + 800ddaa: 781b ldrb r3, [r3, #0] + 800ddac: 009b lsls r3, r3, #2 + 800ddae: 4413 add r3, r2 + 800ddb0: 881b ldrh r3, [r3, #0] + 800ddb2: b29b uxth r3, r3 + 800ddb4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800ddb8: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800ddbc: 83fb strh r3, [r7, #30] + 800ddbe: 687a ldr r2, [r7, #4] + 800ddc0: 683b ldr r3, [r7, #0] + 800ddc2: 781b ldrb r3, [r3, #0] + 800ddc4: 009b lsls r3, r3, #2 + 800ddc6: 441a add r2, r3 + 800ddc8: 8bfb ldrh r3, [r7, #30] + 800ddca: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800ddce: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800ddd2: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800ddd6: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800ddda: b29b uxth r3, r3 + 800dddc: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800cb2e: 687a ldr r2, [r7, #4] - 800cb30: 683b ldr r3, [r7, #0] - 800cb32: 781b ldrb r3, [r3, #0] - 800cb34: 009b lsls r3, r3, #2 - 800cb36: 4413 add r3, r2 - 800cb38: 881b ldrh r3, [r3, #0] - 800cb3a: 83bb strh r3, [r7, #28] - 800cb3c: 8bbb ldrh r3, [r7, #28] - 800cb3e: f003 0340 and.w r3, r3, #64 ; 0x40 - 800cb42: 2b00 cmp r3, #0 - 800cb44: d01b beq.n 800cb7e - 800cb46: 687a ldr r2, [r7, #4] - 800cb48: 683b ldr r3, [r7, #0] - 800cb4a: 781b ldrb r3, [r3, #0] - 800cb4c: 009b lsls r3, r3, #2 - 800cb4e: 4413 add r3, r2 - 800cb50: 881b ldrh r3, [r3, #0] - 800cb52: b29b uxth r3, r3 - 800cb54: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cb58: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cb5c: 837b strh r3, [r7, #26] - 800cb5e: 687a ldr r2, [r7, #4] - 800cb60: 683b ldr r3, [r7, #0] - 800cb62: 781b ldrb r3, [r3, #0] - 800cb64: 009b lsls r3, r3, #2 - 800cb66: 441a add r2, r3 - 800cb68: 8b7b ldrh r3, [r7, #26] - 800cb6a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cb6e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cb72: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cb76: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800cb7a: b29b uxth r3, r3 - 800cb7c: 8013 strh r3, [r2, #0] + 800ddde: 687a ldr r2, [r7, #4] + 800dde0: 683b ldr r3, [r7, #0] + 800dde2: 781b ldrb r3, [r3, #0] + 800dde4: 009b lsls r3, r3, #2 + 800dde6: 4413 add r3, r2 + 800dde8: 881b ldrh r3, [r3, #0] + 800ddea: 83bb strh r3, [r7, #28] + 800ddec: 8bbb ldrh r3, [r7, #28] + 800ddee: f003 0340 and.w r3, r3, #64 ; 0x40 + 800ddf2: 2b00 cmp r3, #0 + 800ddf4: d01b beq.n 800de2e + 800ddf6: 687a ldr r2, [r7, #4] + 800ddf8: 683b ldr r3, [r7, #0] + 800ddfa: 781b ldrb r3, [r3, #0] + 800ddfc: 009b lsls r3, r3, #2 + 800ddfe: 4413 add r3, r2 + 800de00: 881b ldrh r3, [r3, #0] + 800de02: b29b uxth r3, r3 + 800de04: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800de08: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800de0c: 837b strh r3, [r7, #26] + 800de0e: 687a ldr r2, [r7, #4] + 800de10: 683b ldr r3, [r7, #0] + 800de12: 781b ldrb r3, [r3, #0] + 800de14: 009b lsls r3, r3, #2 + 800de16: 441a add r2, r3 + 800de18: 8b7b ldrh r3, [r7, #26] + 800de1a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800de1e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800de22: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800de26: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800de2a: b29b uxth r3, r3 + 800de2c: 8013 strh r3, [r2, #0] /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(USBx, ep->num); - 800cb7e: 687a ldr r2, [r7, #4] - 800cb80: 683b ldr r3, [r7, #0] - 800cb82: 781b ldrb r3, [r3, #0] - 800cb84: 009b lsls r3, r3, #2 - 800cb86: 4413 add r3, r2 - 800cb88: 881b ldrh r3, [r3, #0] - 800cb8a: b29b uxth r3, r3 - 800cb8c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cb90: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cb94: 833b strh r3, [r7, #24] - 800cb96: 687a ldr r2, [r7, #4] - 800cb98: 683b ldr r3, [r7, #0] - 800cb9a: 781b ldrb r3, [r3, #0] - 800cb9c: 009b lsls r3, r3, #2 - 800cb9e: 441a add r2, r3 - 800cba0: 8b3b ldrh r3, [r7, #24] - 800cba2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cba6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cbaa: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cbae: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800cbb2: b29b uxth r3, r3 - 800cbb4: 8013 strh r3, [r2, #0] + 800de2e: 687a ldr r2, [r7, #4] + 800de30: 683b ldr r3, [r7, #0] + 800de32: 781b ldrb r3, [r3, #0] + 800de34: 009b lsls r3, r3, #2 + 800de36: 4413 add r3, r2 + 800de38: 881b ldrh r3, [r3, #0] + 800de3a: b29b uxth r3, r3 + 800de3c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800de40: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800de44: 833b strh r3, [r7, #24] + 800de46: 687a ldr r2, [r7, #4] + 800de48: 683b ldr r3, [r7, #0] + 800de4a: 781b ldrb r3, [r3, #0] + 800de4c: 009b lsls r3, r3, #2 + 800de4e: 441a add r2, r3 + 800de50: 8b3b ldrh r3, [r7, #24] + 800de52: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800de56: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800de5a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800de5e: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800de62: b29b uxth r3, r3 + 800de64: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - 800cbb6: 687a ldr r2, [r7, #4] - 800cbb8: 683b ldr r3, [r7, #0] - 800cbba: 781b ldrb r3, [r3, #0] - 800cbbc: 009b lsls r3, r3, #2 - 800cbbe: 4413 add r3, r2 - 800cbc0: 881b ldrh r3, [r3, #0] - 800cbc2: b29b uxth r3, r3 - 800cbc4: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800cbc8: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cbcc: 82fb strh r3, [r7, #22] - 800cbce: 687a ldr r2, [r7, #4] - 800cbd0: 683b ldr r3, [r7, #0] - 800cbd2: 781b ldrb r3, [r3, #0] - 800cbd4: 009b lsls r3, r3, #2 - 800cbd6: 441a add r2, r3 - 800cbd8: 8afb ldrh r3, [r7, #22] - 800cbda: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cbde: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cbe2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cbe6: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cbea: b29b uxth r3, r3 - 800cbec: 8013 strh r3, [r2, #0] + 800de66: 687a ldr r2, [r7, #4] + 800de68: 683b ldr r3, [r7, #0] + 800de6a: 781b ldrb r3, [r3, #0] + 800de6c: 009b lsls r3, r3, #2 + 800de6e: 4413 add r3, r2 + 800de70: 881b ldrh r3, [r3, #0] + 800de72: b29b uxth r3, r3 + 800de74: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800de78: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800de7c: 82fb strh r3, [r7, #22] + 800de7e: 687a ldr r2, [r7, #4] + 800de80: 683b ldr r3, [r7, #0] + 800de82: 781b ldrb r3, [r3, #0] + 800de84: 009b lsls r3, r3, #2 + 800de86: 441a add r2, r3 + 800de88: 8afb ldrh r3, [r7, #22] + 800de8a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800de8e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800de92: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800de96: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800de9a: b29b uxth r3, r3 + 800de9c: 8013 strh r3, [r2, #0] PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800cbee: 687a ldr r2, [r7, #4] - 800cbf0: 683b ldr r3, [r7, #0] - 800cbf2: 781b ldrb r3, [r3, #0] - 800cbf4: 009b lsls r3, r3, #2 - 800cbf6: 4413 add r3, r2 - 800cbf8: 881b ldrh r3, [r3, #0] - 800cbfa: b29b uxth r3, r3 - 800cbfc: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cc00: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800cc04: 82bb strh r3, [r7, #20] - 800cc06: 687a ldr r2, [r7, #4] - 800cc08: 683b ldr r3, [r7, #0] - 800cc0a: 781b ldrb r3, [r3, #0] - 800cc0c: 009b lsls r3, r3, #2 - 800cc0e: 441a add r2, r3 - 800cc10: 8abb ldrh r3, [r7, #20] - 800cc12: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cc16: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cc1a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cc1e: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cc22: b29b uxth r3, r3 - 800cc24: 8013 strh r3, [r2, #0] - 800cc26: e0a3 b.n 800cd70 + 800de9e: 687a ldr r2, [r7, #4] + 800dea0: 683b ldr r3, [r7, #0] + 800dea2: 781b ldrb r3, [r3, #0] + 800dea4: 009b lsls r3, r3, #2 + 800dea6: 4413 add r3, r2 + 800dea8: 881b ldrh r3, [r3, #0] + 800deaa: b29b uxth r3, r3 + 800deac: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800deb0: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800deb4: 82bb strh r3, [r7, #20] + 800deb6: 687a ldr r2, [r7, #4] + 800deb8: 683b ldr r3, [r7, #0] + 800deba: 781b ldrb r3, [r3, #0] + 800debc: 009b lsls r3, r3, #2 + 800debe: 441a add r2, r3 + 800dec0: 8abb ldrh r3, [r7, #20] + 800dec2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dec6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800deca: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dece: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800ded2: b29b uxth r3, r3 + 800ded4: 8013 strh r3, [r2, #0] + 800ded6: e0a3 b.n 800e020 } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800cc28: 687a ldr r2, [r7, #4] - 800cc2a: 683b ldr r3, [r7, #0] - 800cc2c: 781b ldrb r3, [r3, #0] - 800cc2e: 009b lsls r3, r3, #2 - 800cc30: 4413 add r3, r2 - 800cc32: 881b ldrh r3, [r3, #0] - 800cc34: 85fb strh r3, [r7, #46] ; 0x2e - 800cc36: 8dfb ldrh r3, [r7, #46] ; 0x2e - 800cc38: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800cc3c: 2b00 cmp r3, #0 - 800cc3e: d01b beq.n 800cc78 - 800cc40: 687a ldr r2, [r7, #4] - 800cc42: 683b ldr r3, [r7, #0] - 800cc44: 781b ldrb r3, [r3, #0] - 800cc46: 009b lsls r3, r3, #2 - 800cc48: 4413 add r3, r2 - 800cc4a: 881b ldrh r3, [r3, #0] - 800cc4c: b29b uxth r3, r3 - 800cc4e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cc52: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cc56: 85bb strh r3, [r7, #44] ; 0x2c - 800cc58: 687a ldr r2, [r7, #4] - 800cc5a: 683b ldr r3, [r7, #0] - 800cc5c: 781b ldrb r3, [r3, #0] - 800cc5e: 009b lsls r3, r3, #2 - 800cc60: 441a add r2, r3 - 800cc62: 8dbb ldrh r3, [r7, #44] ; 0x2c - 800cc64: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cc68: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cc6c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800cc70: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cc74: b29b uxth r3, r3 - 800cc76: 8013 strh r3, [r2, #0] + 800ded8: 687a ldr r2, [r7, #4] + 800deda: 683b ldr r3, [r7, #0] + 800dedc: 781b ldrb r3, [r3, #0] + 800dede: 009b lsls r3, r3, #2 + 800dee0: 4413 add r3, r2 + 800dee2: 881b ldrh r3, [r3, #0] + 800dee4: 85fb strh r3, [r7, #46] ; 0x2e + 800dee6: 8dfb ldrh r3, [r7, #46] ; 0x2e + 800dee8: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800deec: 2b00 cmp r3, #0 + 800deee: d01b beq.n 800df28 + 800def0: 687a ldr r2, [r7, #4] + 800def2: 683b ldr r3, [r7, #0] + 800def4: 781b ldrb r3, [r3, #0] + 800def6: 009b lsls r3, r3, #2 + 800def8: 4413 add r3, r2 + 800defa: 881b ldrh r3, [r3, #0] + 800defc: b29b uxth r3, r3 + 800defe: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800df02: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800df06: 85bb strh r3, [r7, #44] ; 0x2c + 800df08: 687a ldr r2, [r7, #4] + 800df0a: 683b ldr r3, [r7, #0] + 800df0c: 781b ldrb r3, [r3, #0] + 800df0e: 009b lsls r3, r3, #2 + 800df10: 441a add r2, r3 + 800df12: 8dbb ldrh r3, [r7, #44] ; 0x2c + 800df14: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800df18: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800df1c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800df20: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800df24: b29b uxth r3, r3 + 800df26: 8013 strh r3, [r2, #0] PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800cc78: 687a ldr r2, [r7, #4] - 800cc7a: 683b ldr r3, [r7, #0] - 800cc7c: 781b ldrb r3, [r3, #0] - 800cc7e: 009b lsls r3, r3, #2 - 800cc80: 4413 add r3, r2 - 800cc82: 881b ldrh r3, [r3, #0] - 800cc84: 857b strh r3, [r7, #42] ; 0x2a - 800cc86: 8d7b ldrh r3, [r7, #42] ; 0x2a - 800cc88: f003 0340 and.w r3, r3, #64 ; 0x40 - 800cc8c: 2b00 cmp r3, #0 - 800cc8e: d01b beq.n 800ccc8 - 800cc90: 687a ldr r2, [r7, #4] - 800cc92: 683b ldr r3, [r7, #0] - 800cc94: 781b ldrb r3, [r3, #0] - 800cc96: 009b lsls r3, r3, #2 - 800cc98: 4413 add r3, r2 - 800cc9a: 881b ldrh r3, [r3, #0] - 800cc9c: b29b uxth r3, r3 - 800cc9e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cca2: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cca6: 853b strh r3, [r7, #40] ; 0x28 - 800cca8: 687a ldr r2, [r7, #4] - 800ccaa: 683b ldr r3, [r7, #0] - 800ccac: 781b ldrb r3, [r3, #0] - 800ccae: 009b lsls r3, r3, #2 - 800ccb0: 441a add r2, r3 - 800ccb2: 8d3b ldrh r3, [r7, #40] ; 0x28 - 800ccb4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ccb8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ccbc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800ccc0: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800ccc4: b29b uxth r3, r3 - 800ccc6: 8013 strh r3, [r2, #0] + 800df28: 687a ldr r2, [r7, #4] + 800df2a: 683b ldr r3, [r7, #0] + 800df2c: 781b ldrb r3, [r3, #0] + 800df2e: 009b lsls r3, r3, #2 + 800df30: 4413 add r3, r2 + 800df32: 881b ldrh r3, [r3, #0] + 800df34: 857b strh r3, [r7, #42] ; 0x2a + 800df36: 8d7b ldrh r3, [r7, #42] ; 0x2a + 800df38: f003 0340 and.w r3, r3, #64 ; 0x40 + 800df3c: 2b00 cmp r3, #0 + 800df3e: d01b beq.n 800df78 + 800df40: 687a ldr r2, [r7, #4] + 800df42: 683b ldr r3, [r7, #0] + 800df44: 781b ldrb r3, [r3, #0] + 800df46: 009b lsls r3, r3, #2 + 800df48: 4413 add r3, r2 + 800df4a: 881b ldrh r3, [r3, #0] + 800df4c: b29b uxth r3, r3 + 800df4e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800df52: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800df56: 853b strh r3, [r7, #40] ; 0x28 + 800df58: 687a ldr r2, [r7, #4] + 800df5a: 683b ldr r3, [r7, #0] + 800df5c: 781b ldrb r3, [r3, #0] + 800df5e: 009b lsls r3, r3, #2 + 800df60: 441a add r2, r3 + 800df62: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800df64: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800df68: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800df6c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800df70: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800df74: b29b uxth r3, r3 + 800df76: 8013 strh r3, [r2, #0] PCD_RX_DTOG(USBx, ep->num); - 800ccc8: 687a ldr r2, [r7, #4] - 800ccca: 683b ldr r3, [r7, #0] - 800cccc: 781b ldrb r3, [r3, #0] - 800ccce: 009b lsls r3, r3, #2 - 800ccd0: 4413 add r3, r2 - 800ccd2: 881b ldrh r3, [r3, #0] - 800ccd4: b29b uxth r3, r3 - 800ccd6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800ccda: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800ccde: 84fb strh r3, [r7, #38] ; 0x26 - 800cce0: 687a ldr r2, [r7, #4] - 800cce2: 683b ldr r3, [r7, #0] - 800cce4: 781b ldrb r3, [r3, #0] - 800cce6: 009b lsls r3, r3, #2 - 800cce8: 441a add r2, r3 - 800ccea: 8cfb ldrh r3, [r7, #38] ; 0x26 - 800ccec: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ccf0: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ccf4: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800ccf8: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800ccfc: b29b uxth r3, r3 - 800ccfe: 8013 strh r3, [r2, #0] + 800df78: 687a ldr r2, [r7, #4] + 800df7a: 683b ldr r3, [r7, #0] + 800df7c: 781b ldrb r3, [r3, #0] + 800df7e: 009b lsls r3, r3, #2 + 800df80: 4413 add r3, r2 + 800df82: 881b ldrh r3, [r3, #0] + 800df84: b29b uxth r3, r3 + 800df86: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800df8a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800df8e: 84fb strh r3, [r7, #38] ; 0x26 + 800df90: 687a ldr r2, [r7, #4] + 800df92: 683b ldr r3, [r7, #0] + 800df94: 781b ldrb r3, [r3, #0] + 800df96: 009b lsls r3, r3, #2 + 800df98: 441a add r2, r3 + 800df9a: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800df9c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dfa0: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dfa4: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800dfa8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dfac: b29b uxth r3, r3 + 800dfae: 8013 strh r3, [r2, #0] /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - 800cd00: 687a ldr r2, [r7, #4] - 800cd02: 683b ldr r3, [r7, #0] - 800cd04: 781b ldrb r3, [r3, #0] - 800cd06: 009b lsls r3, r3, #2 - 800cd08: 4413 add r3, r2 - 800cd0a: 881b ldrh r3, [r3, #0] - 800cd0c: b29b uxth r3, r3 - 800cd0e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cd12: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800cd16: 84bb strh r3, [r7, #36] ; 0x24 - 800cd18: 687a ldr r2, [r7, #4] - 800cd1a: 683b ldr r3, [r7, #0] - 800cd1c: 781b ldrb r3, [r3, #0] - 800cd1e: 009b lsls r3, r3, #2 - 800cd20: 441a add r2, r3 - 800cd22: 8cbb ldrh r3, [r7, #36] ; 0x24 - 800cd24: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cd28: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cd2c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cd30: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cd34: b29b uxth r3, r3 - 800cd36: 8013 strh r3, [r2, #0] + 800dfb0: 687a ldr r2, [r7, #4] + 800dfb2: 683b ldr r3, [r7, #0] + 800dfb4: 781b ldrb r3, [r3, #0] + 800dfb6: 009b lsls r3, r3, #2 + 800dfb8: 4413 add r3, r2 + 800dfba: 881b ldrh r3, [r3, #0] + 800dfbc: b29b uxth r3, r3 + 800dfbe: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800dfc2: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800dfc6: 84bb strh r3, [r7, #36] ; 0x24 + 800dfc8: 687a ldr r2, [r7, #4] + 800dfca: 683b ldr r3, [r7, #0] + 800dfcc: 781b ldrb r3, [r3, #0] + 800dfce: 009b lsls r3, r3, #2 + 800dfd0: 441a add r2, r3 + 800dfd2: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800dfd4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800dfd8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800dfdc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800dfe0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800dfe4: b29b uxth r3, r3 + 800dfe6: 8013 strh r3, [r2, #0] PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - 800cd38: 687a ldr r2, [r7, #4] - 800cd3a: 683b ldr r3, [r7, #0] - 800cd3c: 781b ldrb r3, [r3, #0] - 800cd3e: 009b lsls r3, r3, #2 - 800cd40: 4413 add r3, r2 - 800cd42: 881b ldrh r3, [r3, #0] - 800cd44: b29b uxth r3, r3 - 800cd46: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800cd4a: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cd4e: 847b strh r3, [r7, #34] ; 0x22 - 800cd50: 687a ldr r2, [r7, #4] - 800cd52: 683b ldr r3, [r7, #0] - 800cd54: 781b ldrb r3, [r3, #0] - 800cd56: 009b lsls r3, r3, #2 - 800cd58: 441a add r2, r3 - 800cd5a: 8c7b ldrh r3, [r7, #34] ; 0x22 - 800cd5c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800cd60: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800cd64: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800cd68: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cd6c: b29b uxth r3, r3 - 800cd6e: 8013 strh r3, [r2, #0] + 800dfe8: 687a ldr r2, [r7, #4] + 800dfea: 683b ldr r3, [r7, #0] + 800dfec: 781b ldrb r3, [r3, #0] + 800dfee: 009b lsls r3, r3, #2 + 800dff0: 4413 add r3, r2 + 800dff2: 881b ldrh r3, [r3, #0] + 800dff4: b29b uxth r3, r3 + 800dff6: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800dffa: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800dffe: 847b strh r3, [r7, #34] ; 0x22 + 800e000: 687a ldr r2, [r7, #4] + 800e002: 683b ldr r3, [r7, #0] + 800e004: 781b ldrb r3, [r3, #0] + 800e006: 009b lsls r3, r3, #2 + 800e008: 441a add r2, r3 + 800e00a: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800e00c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800e010: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800e014: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800e018: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800e01c: b29b uxth r3, r3 + 800e01e: 8013 strh r3, [r2, #0] } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ return HAL_OK; - 800cd70: 2300 movs r3, #0 + 800e020: 2300 movs r3, #0 } - 800cd72: 4618 mov r0, r3 - 800cd74: 3734 adds r7, #52 ; 0x34 - 800cd76: 46bd mov sp, r7 - 800cd78: f85d 7b04 ldr.w r7, [sp], #4 - 800cd7c: 4770 bx lr + 800e022: 4618 mov r0, r3 + 800e024: 3734 adds r7, #52 ; 0x34 + 800e026: 46bd mov sp, r7 + 800e028: f85d 7b04 ldr.w r7, [sp], #4 + 800e02c: 4770 bx lr -0800cd7e : +0800e02e : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - 800cd7e: b580 push {r7, lr} - 800cd80: b0c2 sub sp, #264 ; 0x108 - 800cd82: af00 add r7, sp, #0 - 800cd84: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cd88: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cd8c: 6018 str r0, [r3, #0] - 800cd8e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cd92: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cd96: 6019 str r1, [r3, #0] + 800e02e: b580 push {r7, lr} + 800e030: b0c2 sub sp, #264 ; 0x108 + 800e032: af00 add r7, sp, #0 + 800e034: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e038: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e03c: 6018 str r0, [r3, #0] + 800e03e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e042: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e046: 6019 str r1, [r3, #0] uint16_t pmabuffer; uint16_t wEPVal; #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ /* IN endpoint */ if (ep->is_in == 1U) - 800cd98: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cd9c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cda0: 681b ldr r3, [r3, #0] - 800cda2: 785b ldrb r3, [r3, #1] - 800cda4: 2b01 cmp r3, #1 - 800cda6: f040 86b7 bne.w 800db18 + 800e048: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e04c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e050: 681b ldr r3, [r3, #0] + 800e052: 785b ldrb r3, [r3, #1] + 800e054: 2b01 cmp r3, #1 + 800e056: f040 86b7 bne.w 800edc8 { /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) - 800cdaa: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cdae: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cdb2: 681b ldr r3, [r3, #0] - 800cdb4: 699a ldr r2, [r3, #24] - 800cdb6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cdba: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cdbe: 681b ldr r3, [r3, #0] - 800cdc0: 691b ldr r3, [r3, #16] - 800cdc2: 429a cmp r2, r3 - 800cdc4: d908 bls.n 800cdd8 + 800e05a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e05e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e062: 681b ldr r3, [r3, #0] + 800e064: 699a ldr r2, [r3, #24] + 800e066: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e06a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e06e: 681b ldr r3, [r3, #0] + 800e070: 691b ldr r3, [r3, #16] + 800e072: 429a cmp r2, r3 + 800e074: d908 bls.n 800e088 { len = ep->maxpacket; - 800cdc6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cdca: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cdce: 681b ldr r3, [r3, #0] - 800cdd0: 691b ldr r3, [r3, #16] - 800cdd2: f8c7 3104 str.w r3, [r7, #260] ; 0x104 - 800cdd6: e007 b.n 800cde8 + 800e076: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e07a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e07e: 681b ldr r3, [r3, #0] + 800e080: 691b ldr r3, [r3, #16] + 800e082: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800e086: e007 b.n 800e098 } else { len = ep->xfer_len; - 800cdd8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cddc: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cde0: 681b ldr r3, [r3, #0] - 800cde2: 699b ldr r3, [r3, #24] - 800cde4: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800e088: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e08c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e090: 681b ldr r3, [r3, #0] + 800e092: 699b ldr r3, [r3, #24] + 800e094: f8c7 3104 str.w r3, [r7, #260] ; 0x104 } /* configure and validate Tx endpoint */ if (ep->doublebuffer == 0U) - 800cde8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cdec: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cdf0: 681b ldr r3, [r3, #0] - 800cdf2: 7b1b ldrb r3, [r3, #12] - 800cdf4: 2b00 cmp r3, #0 - 800cdf6: d13a bne.n 800ce6e + 800e098: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e09c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e0a0: 681b ldr r3, [r3, #0] + 800e0a2: 7b1b ldrb r3, [r3, #12] + 800e0a4: 2b00 cmp r3, #0 + 800e0a6: d13a bne.n 800e11e { USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); - 800cdf8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cdfc: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce00: 681b ldr r3, [r3, #0] - 800ce02: 6959 ldr r1, [r3, #20] - 800ce04: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce08: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce0c: 681b ldr r3, [r3, #0] - 800ce0e: 88da ldrh r2, [r3, #6] - 800ce10: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800ce14: b29b uxth r3, r3 - 800ce16: f507 7084 add.w r0, r7, #264 ; 0x108 - 800ce1a: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800ce1e: 6800 ldr r0, [r0, #0] - 800ce20: f001 fcb9 bl 800e796 + 800e0a8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e0ac: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e0b0: 681b ldr r3, [r3, #0] + 800e0b2: 6959 ldr r1, [r3, #20] + 800e0b4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e0b8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e0bc: 681b ldr r3, [r3, #0] + 800e0be: 88da ldrh r2, [r3, #6] + 800e0c0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e0c4: b29b uxth r3, r3 + 800e0c6: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e0ca: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e0ce: 6800 ldr r0, [r0, #0] + 800e0d0: f001 fcb9 bl 800fa46 PCD_SET_EP_TX_CNT(USBx, ep->num, len); - 800ce24: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce28: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800ce2c: 681b ldr r3, [r3, #0] - 800ce2e: 613b str r3, [r7, #16] - 800ce30: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce34: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800ce38: 681b ldr r3, [r3, #0] - 800ce3a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800ce3e: b29b uxth r3, r3 - 800ce40: 461a mov r2, r3 - 800ce42: 693b ldr r3, [r7, #16] - 800ce44: 4413 add r3, r2 - 800ce46: 613b str r3, [r7, #16] - 800ce48: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce4c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce50: 681b ldr r3, [r3, #0] - 800ce52: 781b ldrb r3, [r3, #0] - 800ce54: 00da lsls r2, r3, #3 - 800ce56: 693b ldr r3, [r7, #16] - 800ce58: 4413 add r3, r2 - 800ce5a: f203 4302 addw r3, r3, #1026 ; 0x402 - 800ce5e: 60fb str r3, [r7, #12] - 800ce60: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800ce64: b29a uxth r2, r3 - 800ce66: 68fb ldr r3, [r7, #12] - 800ce68: 801a strh r2, [r3, #0] - 800ce6a: f000 be1f b.w 800daac + 800e0d4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e0d8: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e0dc: 681b ldr r3, [r3, #0] + 800e0de: 613b str r3, [r7, #16] + 800e0e0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e0e4: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e0e8: 681b ldr r3, [r3, #0] + 800e0ea: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e0ee: b29b uxth r3, r3 + 800e0f0: 461a mov r2, r3 + 800e0f2: 693b ldr r3, [r7, #16] + 800e0f4: 4413 add r3, r2 + 800e0f6: 613b str r3, [r7, #16] + 800e0f8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e0fc: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e100: 681b ldr r3, [r3, #0] + 800e102: 781b ldrb r3, [r3, #0] + 800e104: 00da lsls r2, r3, #3 + 800e106: 693b ldr r3, [r7, #16] + 800e108: 4413 add r3, r2 + 800e10a: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e10e: 60fb str r3, [r7, #12] + 800e110: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e114: b29a uxth r2, r3 + 800e116: 68fb ldr r3, [r7, #12] + 800e118: 801a strh r2, [r3, #0] + 800e11a: f000 be1f b.w 800ed5c } #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* double buffer bulk management */ if (ep->type == EP_TYPE_BULK) - 800ce6e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce72: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce76: 681b ldr r3, [r3, #0] - 800ce78: 78db ldrb r3, [r3, #3] - 800ce7a: 2b02 cmp r3, #2 - 800ce7c: f040 8462 bne.w 800d744 + 800e11e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e122: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e126: 681b ldr r3, [r3, #0] + 800e128: 78db ldrb r3, [r3, #3] + 800e12a: 2b02 cmp r3, #2 + 800e12c: f040 8462 bne.w 800e9f4 { if (ep->xfer_len_db > ep->maxpacket) - 800ce80: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce84: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce88: 681b ldr r3, [r3, #0] - 800ce8a: 6a1a ldr r2, [r3, #32] - 800ce8c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ce90: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ce94: 681b ldr r3, [r3, #0] - 800ce96: 691b ldr r3, [r3, #16] - 800ce98: 429a cmp r2, r3 - 800ce9a: f240 83df bls.w 800d65c + 800e130: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e134: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e138: 681b ldr r3, [r3, #0] + 800e13a: 6a1a ldr r2, [r3, #32] + 800e13c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e140: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e144: 681b ldr r3, [r3, #0] + 800e146: 691b ldr r3, [r3, #16] + 800e148: 429a cmp r2, r3 + 800e14a: f240 83df bls.w 800e90c { /* enable double buffer */ PCD_SET_BULK_EP_DBUF(USBx, ep->num); - 800ce9e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cea2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cea6: 681a ldr r2, [r3, #0] - 800cea8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ceac: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ceb0: 681b ldr r3, [r3, #0] - 800ceb2: 781b ldrb r3, [r3, #0] - 800ceb4: 009b lsls r3, r3, #2 - 800ceb6: 4413 add r3, r2 - 800ceb8: 881b ldrh r3, [r3, #0] - 800ceba: b29b uxth r3, r3 - 800cebc: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800cec0: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800cec4: f8a7 3056 strh.w r3, [r7, #86] ; 0x56 - 800cec8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cecc: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800ced0: 681a ldr r2, [r3, #0] - 800ced2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ced6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ceda: 681b ldr r3, [r3, #0] - 800cedc: 781b ldrb r3, [r3, #0] - 800cede: 009b lsls r3, r3, #2 - 800cee0: 441a add r2, r3 - 800cee2: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56 - 800cee6: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800ceea: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800ceee: f443 4301 orr.w r3, r3, #33024 ; 0x8100 - 800cef2: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800cef6: b29b uxth r3, r3 - 800cef8: 8013 strh r3, [r2, #0] + 800e14e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e152: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e156: 681a ldr r2, [r3, #0] + 800e158: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e15c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e160: 681b ldr r3, [r3, #0] + 800e162: 781b ldrb r3, [r3, #0] + 800e164: 009b lsls r3, r3, #2 + 800e166: 4413 add r3, r2 + 800e168: 881b ldrh r3, [r3, #0] + 800e16a: b29b uxth r3, r3 + 800e16c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800e170: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800e174: f8a7 3056 strh.w r3, [r7, #86] ; 0x56 + 800e178: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e17c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e180: 681a ldr r2, [r3, #0] + 800e182: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e186: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e18a: 681b ldr r3, [r3, #0] + 800e18c: 781b ldrb r3, [r3, #0] + 800e18e: 009b lsls r3, r3, #2 + 800e190: 441a add r2, r3 + 800e192: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56 + 800e196: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800e19a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800e19e: f443 4301 orr.w r3, r3, #33024 ; 0x8100 + 800e1a2: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800e1a6: b29b uxth r3, r3 + 800e1a8: 8013 strh r3, [r2, #0] /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; - 800cefa: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cefe: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cf02: 681b ldr r3, [r3, #0] - 800cf04: 6a1a ldr r2, [r3, #32] - 800cf06: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800cf0a: 1ad2 subs r2, r2, r3 - 800cf0c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf10: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cf14: 681b ldr r3, [r3, #0] - 800cf16: 621a str r2, [r3, #32] + 800e1aa: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e1ae: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e1b2: 681b ldr r3, [r3, #0] + 800e1b4: 6a1a ldr r2, [r3, #32] + 800e1b6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e1ba: 1ad2 subs r2, r2, r3 + 800e1bc: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e1c0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e1c4: 681b ldr r3, [r3, #0] + 800e1c6: 621a str r2, [r3, #32] /* Fill the two first buffer in the Buffer0 & Buffer1 */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - 800cf18: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf1c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cf20: 681a ldr r2, [r3, #0] - 800cf22: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf26: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cf2a: 681b ldr r3, [r3, #0] - 800cf2c: 781b ldrb r3, [r3, #0] - 800cf2e: 009b lsls r3, r3, #2 - 800cf30: 4413 add r3, r2 - 800cf32: 881b ldrh r3, [r3, #0] - 800cf34: b29b uxth r3, r3 - 800cf36: f003 0340 and.w r3, r3, #64 ; 0x40 - 800cf3a: 2b00 cmp r3, #0 - 800cf3c: f000 81c7 beq.w 800d2ce + 800e1c8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e1cc: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e1d0: 681a ldr r2, [r3, #0] + 800e1d2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e1d6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e1da: 681b ldr r3, [r3, #0] + 800e1dc: 781b ldrb r3, [r3, #0] + 800e1de: 009b lsls r3, r3, #2 + 800e1e0: 4413 add r3, r2 + 800e1e2: 881b ldrh r3, [r3, #0] + 800e1e4: b29b uxth r3, r3 + 800e1e6: f003 0340 and.w r3, r3, #64 ; 0x40 + 800e1ea: 2b00 cmp r3, #0 + 800e1ec: f000 81c7 beq.w 800e57e { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - 800cf40: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf44: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cf48: 681b ldr r3, [r3, #0] - 800cf4a: 633b str r3, [r7, #48] ; 0x30 - 800cf4c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf50: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cf54: 681b ldr r3, [r3, #0] - 800cf56: 785b ldrb r3, [r3, #1] - 800cf58: 2b00 cmp r3, #0 - 800cf5a: d177 bne.n 800d04c - 800cf5c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf60: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cf64: 681b ldr r3, [r3, #0] - 800cf66: 62bb str r3, [r7, #40] ; 0x28 - 800cf68: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf6c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800cf70: 681b ldr r3, [r3, #0] - 800cf72: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800cf76: b29b uxth r3, r3 - 800cf78: 461a mov r2, r3 - 800cf7a: 6abb ldr r3, [r7, #40] ; 0x28 - 800cf7c: 4413 add r3, r2 - 800cf7e: 62bb str r3, [r7, #40] ; 0x28 - 800cf80: f507 7384 add.w r3, r7, #264 ; 0x108 - 800cf84: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800cf88: 681b ldr r3, [r3, #0] - 800cf8a: 781b ldrb r3, [r3, #0] - 800cf8c: 00da lsls r2, r3, #3 - 800cf8e: 6abb ldr r3, [r7, #40] ; 0x28 - 800cf90: 4413 add r3, r2 - 800cf92: f203 4306 addw r3, r3, #1030 ; 0x406 - 800cf96: 627b str r3, [r7, #36] ; 0x24 - 800cf98: 6a7b ldr r3, [r7, #36] ; 0x24 - 800cf9a: 881b ldrh r3, [r3, #0] - 800cf9c: b29b uxth r3, r3 - 800cf9e: f3c3 0309 ubfx r3, r3, #0, #10 - 800cfa2: b29a uxth r2, r3 - 800cfa4: 6a7b ldr r3, [r7, #36] ; 0x24 - 800cfa6: 801a strh r2, [r3, #0] - 800cfa8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800cfac: 2b3e cmp r3, #62 ; 0x3e - 800cfae: d921 bls.n 800cff4 - 800cfb0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800cfb4: 095b lsrs r3, r3, #5 - 800cfb6: f8c7 3100 str.w r3, [r7, #256] ; 0x100 - 800cfba: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800cfbe: f003 031f and.w r3, r3, #31 - 800cfc2: 2b00 cmp r3, #0 - 800cfc4: d104 bne.n 800cfd0 - 800cfc6: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 - 800cfca: 3b01 subs r3, #1 - 800cfcc: f8c7 3100 str.w r3, [r7, #256] ; 0x100 - 800cfd0: 6a7b ldr r3, [r7, #36] ; 0x24 - 800cfd2: 881b ldrh r3, [r3, #0] - 800cfd4: b29a uxth r2, r3 - 800cfd6: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 - 800cfda: b29b uxth r3, r3 - 800cfdc: 029b lsls r3, r3, #10 - 800cfde: b29b uxth r3, r3 - 800cfe0: 4313 orrs r3, r2 - 800cfe2: b29b uxth r3, r3 - 800cfe4: ea6f 4343 mvn.w r3, r3, lsl #17 - 800cfe8: ea6f 4353 mvn.w r3, r3, lsr #17 - 800cfec: b29a uxth r2, r3 - 800cfee: 6a7b ldr r3, [r7, #36] ; 0x24 - 800cff0: 801a strh r2, [r3, #0] - 800cff2: e050 b.n 800d096 - 800cff4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800cff8: 2b00 cmp r3, #0 - 800cffa: d10a bne.n 800d012 - 800cffc: 6a7b ldr r3, [r7, #36] ; 0x24 - 800cffe: 881b ldrh r3, [r3, #0] - 800d000: b29b uxth r3, r3 - 800d002: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d006: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d00a: b29a uxth r2, r3 - 800d00c: 6a7b ldr r3, [r7, #36] ; 0x24 - 800d00e: 801a strh r2, [r3, #0] - 800d010: e041 b.n 800d096 - 800d012: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d016: 085b lsrs r3, r3, #1 - 800d018: f8c7 3100 str.w r3, [r7, #256] ; 0x100 - 800d01c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d020: f003 0301 and.w r3, r3, #1 - 800d024: 2b00 cmp r3, #0 - 800d026: d004 beq.n 800d032 - 800d028: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 - 800d02c: 3301 adds r3, #1 - 800d02e: f8c7 3100 str.w r3, [r7, #256] ; 0x100 - 800d032: 6a7b ldr r3, [r7, #36] ; 0x24 - 800d034: 881b ldrh r3, [r3, #0] - 800d036: b29a uxth r2, r3 - 800d038: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 - 800d03c: b29b uxth r3, r3 - 800d03e: 029b lsls r3, r3, #10 - 800d040: b29b uxth r3, r3 - 800d042: 4313 orrs r3, r2 - 800d044: b29a uxth r2, r3 - 800d046: 6a7b ldr r3, [r7, #36] ; 0x24 - 800d048: 801a strh r2, [r3, #0] - 800d04a: e024 b.n 800d096 - 800d04c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d050: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d054: 681b ldr r3, [r3, #0] - 800d056: 785b ldrb r3, [r3, #1] - 800d058: 2b01 cmp r3, #1 - 800d05a: d11c bne.n 800d096 - 800d05c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d060: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d064: 681b ldr r3, [r3, #0] - 800d066: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d06a: b29b uxth r3, r3 - 800d06c: 461a mov r2, r3 - 800d06e: 6b3b ldr r3, [r7, #48] ; 0x30 - 800d070: 4413 add r3, r2 - 800d072: 633b str r3, [r7, #48] ; 0x30 - 800d074: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d078: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d07c: 681b ldr r3, [r3, #0] - 800d07e: 781b ldrb r3, [r3, #0] - 800d080: 00da lsls r2, r3, #3 - 800d082: 6b3b ldr r3, [r7, #48] ; 0x30 - 800d084: 4413 add r3, r2 - 800d086: f203 4306 addw r3, r3, #1030 ; 0x406 - 800d08a: 62fb str r3, [r7, #44] ; 0x2c - 800d08c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d090: b29a uxth r2, r3 - 800d092: 6afb ldr r3, [r7, #44] ; 0x2c - 800d094: 801a strh r2, [r3, #0] + 800e1f0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e1f4: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e1f8: 681b ldr r3, [r3, #0] + 800e1fa: 633b str r3, [r7, #48] ; 0x30 + 800e1fc: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e200: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e204: 681b ldr r3, [r3, #0] + 800e206: 785b ldrb r3, [r3, #1] + 800e208: 2b00 cmp r3, #0 + 800e20a: d177 bne.n 800e2fc + 800e20c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e210: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e214: 681b ldr r3, [r3, #0] + 800e216: 62bb str r3, [r7, #40] ; 0x28 + 800e218: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e21c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e220: 681b ldr r3, [r3, #0] + 800e222: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e226: b29b uxth r3, r3 + 800e228: 461a mov r2, r3 + 800e22a: 6abb ldr r3, [r7, #40] ; 0x28 + 800e22c: 4413 add r3, r2 + 800e22e: 62bb str r3, [r7, #40] ; 0x28 + 800e230: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e234: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e238: 681b ldr r3, [r3, #0] + 800e23a: 781b ldrb r3, [r3, #0] + 800e23c: 00da lsls r2, r3, #3 + 800e23e: 6abb ldr r3, [r7, #40] ; 0x28 + 800e240: 4413 add r3, r2 + 800e242: f203 4306 addw r3, r3, #1030 ; 0x406 + 800e246: 627b str r3, [r7, #36] ; 0x24 + 800e248: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e24a: 881b ldrh r3, [r3, #0] + 800e24c: b29b uxth r3, r3 + 800e24e: f3c3 0309 ubfx r3, r3, #0, #10 + 800e252: b29a uxth r2, r3 + 800e254: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e256: 801a strh r2, [r3, #0] + 800e258: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e25c: 2b3e cmp r3, #62 ; 0x3e + 800e25e: d921 bls.n 800e2a4 + 800e260: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e264: 095b lsrs r3, r3, #5 + 800e266: f8c7 3100 str.w r3, [r7, #256] ; 0x100 + 800e26a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e26e: f003 031f and.w r3, r3, #31 + 800e272: 2b00 cmp r3, #0 + 800e274: d104 bne.n 800e280 + 800e276: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 + 800e27a: 3b01 subs r3, #1 + 800e27c: f8c7 3100 str.w r3, [r7, #256] ; 0x100 + 800e280: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e282: 881b ldrh r3, [r3, #0] + 800e284: b29a uxth r2, r3 + 800e286: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 + 800e28a: b29b uxth r3, r3 + 800e28c: 029b lsls r3, r3, #10 + 800e28e: b29b uxth r3, r3 + 800e290: 4313 orrs r3, r2 + 800e292: b29b uxth r3, r3 + 800e294: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e298: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e29c: b29a uxth r2, r3 + 800e29e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e2a0: 801a strh r2, [r3, #0] + 800e2a2: e050 b.n 800e346 + 800e2a4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e2a8: 2b00 cmp r3, #0 + 800e2aa: d10a bne.n 800e2c2 + 800e2ac: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e2ae: 881b ldrh r3, [r3, #0] + 800e2b0: b29b uxth r3, r3 + 800e2b2: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e2b6: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e2ba: b29a uxth r2, r3 + 800e2bc: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e2be: 801a strh r2, [r3, #0] + 800e2c0: e041 b.n 800e346 + 800e2c2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e2c6: 085b lsrs r3, r3, #1 + 800e2c8: f8c7 3100 str.w r3, [r7, #256] ; 0x100 + 800e2cc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e2d0: f003 0301 and.w r3, r3, #1 + 800e2d4: 2b00 cmp r3, #0 + 800e2d6: d004 beq.n 800e2e2 + 800e2d8: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 + 800e2dc: 3301 adds r3, #1 + 800e2de: f8c7 3100 str.w r3, [r7, #256] ; 0x100 + 800e2e2: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e2e4: 881b ldrh r3, [r3, #0] + 800e2e6: b29a uxth r2, r3 + 800e2e8: f8d7 3100 ldr.w r3, [r7, #256] ; 0x100 + 800e2ec: b29b uxth r3, r3 + 800e2ee: 029b lsls r3, r3, #10 + 800e2f0: b29b uxth r3, r3 + 800e2f2: 4313 orrs r3, r2 + 800e2f4: b29a uxth r2, r3 + 800e2f6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800e2f8: 801a strh r2, [r3, #0] + 800e2fa: e024 b.n 800e346 + 800e2fc: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e300: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e304: 681b ldr r3, [r3, #0] + 800e306: 785b ldrb r3, [r3, #1] + 800e308: 2b01 cmp r3, #1 + 800e30a: d11c bne.n 800e346 + 800e30c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e310: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e314: 681b ldr r3, [r3, #0] + 800e316: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e31a: b29b uxth r3, r3 + 800e31c: 461a mov r2, r3 + 800e31e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e320: 4413 add r3, r2 + 800e322: 633b str r3, [r7, #48] ; 0x30 + 800e324: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e328: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e32c: 681b ldr r3, [r3, #0] + 800e32e: 781b ldrb r3, [r3, #0] + 800e330: 00da lsls r2, r3, #3 + 800e332: 6b3b ldr r3, [r7, #48] ; 0x30 + 800e334: 4413 add r3, r2 + 800e336: f203 4306 addw r3, r3, #1030 ; 0x406 + 800e33a: 62fb str r3, [r7, #44] ; 0x2c + 800e33c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e340: b29a uxth r2, r3 + 800e342: 6afb ldr r3, [r7, #44] ; 0x2c + 800e344: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; - 800d096: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d09a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d09e: 681b ldr r3, [r3, #0] - 800d0a0: 895b ldrh r3, [r3, #10] - 800d0a2: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800e346: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e34a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e34e: 681b ldr r3, [r3, #0] + 800e350: 895b ldrh r3, [r3, #10] + 800e352: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d0a6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d0aa: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d0ae: 681b ldr r3, [r3, #0] - 800d0b0: 6959 ldr r1, [r3, #20] - 800d0b2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d0b6: b29b uxth r3, r3 - 800d0b8: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d0bc: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d0c0: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d0c4: 6800 ldr r0, [r0, #0] - 800d0c6: f001 fb66 bl 800e796 + 800e356: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e35a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e35e: 681b ldr r3, [r3, #0] + 800e360: 6959 ldr r1, [r3, #20] + 800e362: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e366: b29b uxth r3, r3 + 800e368: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800e36c: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e370: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e374: 6800 ldr r0, [r0, #0] + 800e376: f001 fb66 bl 800fa46 ep->xfer_buff += len; - 800d0ca: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d0ce: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d0d2: 681b ldr r3, [r3, #0] - 800d0d4: 695a ldr r2, [r3, #20] - 800d0d6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d0da: 441a add r2, r3 - 800d0dc: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d0e0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d0e4: 681b ldr r3, [r3, #0] - 800d0e6: 615a str r2, [r3, #20] + 800e37a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e37e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e382: 681b ldr r3, [r3, #0] + 800e384: 695a ldr r2, [r3, #20] + 800e386: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e38a: 441a add r2, r3 + 800e38c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e390: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e394: 681b ldr r3, [r3, #0] + 800e396: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) - 800d0e8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d0ec: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d0f0: 681b ldr r3, [r3, #0] - 800d0f2: 6a1a ldr r2, [r3, #32] - 800d0f4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d0f8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d0fc: 681b ldr r3, [r3, #0] - 800d0fe: 691b ldr r3, [r3, #16] - 800d100: 429a cmp r2, r3 - 800d102: d90f bls.n 800d124 + 800e398: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e39c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3a0: 681b ldr r3, [r3, #0] + 800e3a2: 6a1a ldr r2, [r3, #32] + 800e3a4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3a8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3ac: 681b ldr r3, [r3, #0] + 800e3ae: 691b ldr r3, [r3, #16] + 800e3b0: 429a cmp r2, r3 + 800e3b2: d90f bls.n 800e3d4 { ep->xfer_len_db -= len; - 800d104: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d108: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d10c: 681b ldr r3, [r3, #0] - 800d10e: 6a1a ldr r2, [r3, #32] - 800d110: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d114: 1ad2 subs r2, r2, r3 - 800d116: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d11a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d11e: 681b ldr r3, [r3, #0] - 800d120: 621a str r2, [r3, #32] - 800d122: e00e b.n 800d142 + 800e3b4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3b8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3bc: 681b ldr r3, [r3, #0] + 800e3be: 6a1a ldr r2, [r3, #32] + 800e3c0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e3c4: 1ad2 subs r2, r2, r3 + 800e3c6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3ca: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3ce: 681b ldr r3, [r3, #0] + 800e3d0: 621a str r2, [r3, #32] + 800e3d2: e00e b.n 800e3f2 } else { len = ep->xfer_len_db; - 800d124: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d128: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d12c: 681b ldr r3, [r3, #0] - 800d12e: 6a1b ldr r3, [r3, #32] - 800d130: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800e3d4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3d8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3dc: 681b ldr r3, [r3, #0] + 800e3de: 6a1b ldr r3, [r3, #32] + 800e3e0: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len_db = 0U; - 800d134: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d138: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d13c: 681b ldr r3, [r3, #0] - 800d13e: 2200 movs r2, #0 - 800d140: 621a str r2, [r3, #32] + 800e3e4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3e8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3ec: 681b ldr r3, [r3, #0] + 800e3ee: 2200 movs r2, #0 + 800e3f0: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - 800d142: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d146: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d14a: 681b ldr r3, [r3, #0] - 800d14c: 785b ldrb r3, [r3, #1] - 800d14e: 2b00 cmp r3, #0 - 800d150: d177 bne.n 800d242 - 800d152: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d156: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d15a: 681b ldr r3, [r3, #0] - 800d15c: 61bb str r3, [r7, #24] - 800d15e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d162: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d166: 681b ldr r3, [r3, #0] - 800d168: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d16c: b29b uxth r3, r3 - 800d16e: 461a mov r2, r3 - 800d170: 69bb ldr r3, [r7, #24] - 800d172: 4413 add r3, r2 - 800d174: 61bb str r3, [r7, #24] - 800d176: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d17a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d17e: 681b ldr r3, [r3, #0] - 800d180: 781b ldrb r3, [r3, #0] - 800d182: 00da lsls r2, r3, #3 - 800d184: 69bb ldr r3, [r7, #24] - 800d186: 4413 add r3, r2 - 800d188: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d18c: 617b str r3, [r7, #20] - 800d18e: 697b ldr r3, [r7, #20] - 800d190: 881b ldrh r3, [r3, #0] - 800d192: b29b uxth r3, r3 - 800d194: f3c3 0309 ubfx r3, r3, #0, #10 - 800d198: b29a uxth r2, r3 - 800d19a: 697b ldr r3, [r7, #20] - 800d19c: 801a strh r2, [r3, #0] - 800d19e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d1a2: 2b3e cmp r3, #62 ; 0x3e - 800d1a4: d921 bls.n 800d1ea - 800d1a6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d1aa: 095b lsrs r3, r3, #5 - 800d1ac: f8c7 30fc str.w r3, [r7, #252] ; 0xfc - 800d1b0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d1b4: f003 031f and.w r3, r3, #31 - 800d1b8: 2b00 cmp r3, #0 - 800d1ba: d104 bne.n 800d1c6 - 800d1bc: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 800d1c0: 3b01 subs r3, #1 - 800d1c2: f8c7 30fc str.w r3, [r7, #252] ; 0xfc - 800d1c6: 697b ldr r3, [r7, #20] - 800d1c8: 881b ldrh r3, [r3, #0] - 800d1ca: b29a uxth r2, r3 - 800d1cc: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 800d1d0: b29b uxth r3, r3 - 800d1d2: 029b lsls r3, r3, #10 - 800d1d4: b29b uxth r3, r3 - 800d1d6: 4313 orrs r3, r2 - 800d1d8: b29b uxth r3, r3 - 800d1da: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d1de: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d1e2: b29a uxth r2, r3 - 800d1e4: 697b ldr r3, [r7, #20] - 800d1e6: 801a strh r2, [r3, #0] - 800d1e8: e056 b.n 800d298 - 800d1ea: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d1ee: 2b00 cmp r3, #0 - 800d1f0: d10a bne.n 800d208 - 800d1f2: 697b ldr r3, [r7, #20] - 800d1f4: 881b ldrh r3, [r3, #0] - 800d1f6: b29b uxth r3, r3 - 800d1f8: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d1fc: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d200: b29a uxth r2, r3 - 800d202: 697b ldr r3, [r7, #20] - 800d204: 801a strh r2, [r3, #0] - 800d206: e047 b.n 800d298 - 800d208: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d20c: 085b lsrs r3, r3, #1 - 800d20e: f8c7 30fc str.w r3, [r7, #252] ; 0xfc - 800d212: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d216: f003 0301 and.w r3, r3, #1 - 800d21a: 2b00 cmp r3, #0 - 800d21c: d004 beq.n 800d228 - 800d21e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 800d222: 3301 adds r3, #1 - 800d224: f8c7 30fc str.w r3, [r7, #252] ; 0xfc - 800d228: 697b ldr r3, [r7, #20] - 800d22a: 881b ldrh r3, [r3, #0] - 800d22c: b29a uxth r2, r3 - 800d22e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 800d232: b29b uxth r3, r3 - 800d234: 029b lsls r3, r3, #10 - 800d236: b29b uxth r3, r3 - 800d238: 4313 orrs r3, r2 - 800d23a: b29a uxth r2, r3 - 800d23c: 697b ldr r3, [r7, #20] - 800d23e: 801a strh r2, [r3, #0] - 800d240: e02a b.n 800d298 - 800d242: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d246: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d24a: 681b ldr r3, [r3, #0] - 800d24c: 785b ldrb r3, [r3, #1] - 800d24e: 2b01 cmp r3, #1 - 800d250: d122 bne.n 800d298 - 800d252: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d256: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d25a: 681b ldr r3, [r3, #0] - 800d25c: 623b str r3, [r7, #32] - 800d25e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d262: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d266: 681b ldr r3, [r3, #0] - 800d268: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d26c: b29b uxth r3, r3 - 800d26e: 461a mov r2, r3 - 800d270: 6a3b ldr r3, [r7, #32] - 800d272: 4413 add r3, r2 - 800d274: 623b str r3, [r7, #32] - 800d276: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d27a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d27e: 681b ldr r3, [r3, #0] - 800d280: 781b ldrb r3, [r3, #0] - 800d282: 00da lsls r2, r3, #3 - 800d284: 6a3b ldr r3, [r7, #32] - 800d286: 4413 add r3, r2 - 800d288: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d28c: 61fb str r3, [r7, #28] - 800d28e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d292: b29a uxth r2, r3 - 800d294: 69fb ldr r3, [r7, #28] - 800d296: 801a strh r2, [r3, #0] + 800e3f2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e3f6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e3fa: 681b ldr r3, [r3, #0] + 800e3fc: 785b ldrb r3, [r3, #1] + 800e3fe: 2b00 cmp r3, #0 + 800e400: d177 bne.n 800e4f2 + 800e402: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e406: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e40a: 681b ldr r3, [r3, #0] + 800e40c: 61bb str r3, [r7, #24] + 800e40e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e412: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e416: 681b ldr r3, [r3, #0] + 800e418: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e41c: b29b uxth r3, r3 + 800e41e: 461a mov r2, r3 + 800e420: 69bb ldr r3, [r7, #24] + 800e422: 4413 add r3, r2 + 800e424: 61bb str r3, [r7, #24] + 800e426: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e42a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e42e: 681b ldr r3, [r3, #0] + 800e430: 781b ldrb r3, [r3, #0] + 800e432: 00da lsls r2, r3, #3 + 800e434: 69bb ldr r3, [r7, #24] + 800e436: 4413 add r3, r2 + 800e438: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e43c: 617b str r3, [r7, #20] + 800e43e: 697b ldr r3, [r7, #20] + 800e440: 881b ldrh r3, [r3, #0] + 800e442: b29b uxth r3, r3 + 800e444: f3c3 0309 ubfx r3, r3, #0, #10 + 800e448: b29a uxth r2, r3 + 800e44a: 697b ldr r3, [r7, #20] + 800e44c: 801a strh r2, [r3, #0] + 800e44e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e452: 2b3e cmp r3, #62 ; 0x3e + 800e454: d921 bls.n 800e49a + 800e456: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e45a: 095b lsrs r3, r3, #5 + 800e45c: f8c7 30fc str.w r3, [r7, #252] ; 0xfc + 800e460: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e464: f003 031f and.w r3, r3, #31 + 800e468: 2b00 cmp r3, #0 + 800e46a: d104 bne.n 800e476 + 800e46c: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800e470: 3b01 subs r3, #1 + 800e472: f8c7 30fc str.w r3, [r7, #252] ; 0xfc + 800e476: 697b ldr r3, [r7, #20] + 800e478: 881b ldrh r3, [r3, #0] + 800e47a: b29a uxth r2, r3 + 800e47c: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800e480: b29b uxth r3, r3 + 800e482: 029b lsls r3, r3, #10 + 800e484: b29b uxth r3, r3 + 800e486: 4313 orrs r3, r2 + 800e488: b29b uxth r3, r3 + 800e48a: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e48e: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e492: b29a uxth r2, r3 + 800e494: 697b ldr r3, [r7, #20] + 800e496: 801a strh r2, [r3, #0] + 800e498: e056 b.n 800e548 + 800e49a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e49e: 2b00 cmp r3, #0 + 800e4a0: d10a bne.n 800e4b8 + 800e4a2: 697b ldr r3, [r7, #20] + 800e4a4: 881b ldrh r3, [r3, #0] + 800e4a6: b29b uxth r3, r3 + 800e4a8: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e4ac: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e4b0: b29a uxth r2, r3 + 800e4b2: 697b ldr r3, [r7, #20] + 800e4b4: 801a strh r2, [r3, #0] + 800e4b6: e047 b.n 800e548 + 800e4b8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e4bc: 085b lsrs r3, r3, #1 + 800e4be: f8c7 30fc str.w r3, [r7, #252] ; 0xfc + 800e4c2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e4c6: f003 0301 and.w r3, r3, #1 + 800e4ca: 2b00 cmp r3, #0 + 800e4cc: d004 beq.n 800e4d8 + 800e4ce: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800e4d2: 3301 adds r3, #1 + 800e4d4: f8c7 30fc str.w r3, [r7, #252] ; 0xfc + 800e4d8: 697b ldr r3, [r7, #20] + 800e4da: 881b ldrh r3, [r3, #0] + 800e4dc: b29a uxth r2, r3 + 800e4de: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800e4e2: b29b uxth r3, r3 + 800e4e4: 029b lsls r3, r3, #10 + 800e4e6: b29b uxth r3, r3 + 800e4e8: 4313 orrs r3, r2 + 800e4ea: b29a uxth r2, r3 + 800e4ec: 697b ldr r3, [r7, #20] + 800e4ee: 801a strh r2, [r3, #0] + 800e4f0: e02a b.n 800e548 + 800e4f2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e4f6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e4fa: 681b ldr r3, [r3, #0] + 800e4fc: 785b ldrb r3, [r3, #1] + 800e4fe: 2b01 cmp r3, #1 + 800e500: d122 bne.n 800e548 + 800e502: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e506: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e50a: 681b ldr r3, [r3, #0] + 800e50c: 623b str r3, [r7, #32] + 800e50e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e512: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e516: 681b ldr r3, [r3, #0] + 800e518: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e51c: b29b uxth r3, r3 + 800e51e: 461a mov r2, r3 + 800e520: 6a3b ldr r3, [r7, #32] + 800e522: 4413 add r3, r2 + 800e524: 623b str r3, [r7, #32] + 800e526: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e52a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e52e: 681b ldr r3, [r3, #0] + 800e530: 781b ldrb r3, [r3, #0] + 800e532: 00da lsls r2, r3, #3 + 800e534: 6a3b ldr r3, [r7, #32] + 800e536: 4413 add r3, r2 + 800e538: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e53c: 61fb str r3, [r7, #28] + 800e53e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e542: b29a uxth r2, r3 + 800e544: 69fb ldr r3, [r7, #28] + 800e546: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; - 800d298: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d29c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d2a0: 681b ldr r3, [r3, #0] - 800d2a2: 891b ldrh r3, [r3, #8] - 800d2a4: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800e548: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e54c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e550: 681b ldr r3, [r3, #0] + 800e552: 891b ldrh r3, [r3, #8] + 800e554: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d2a8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d2ac: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d2b0: 681b ldr r3, [r3, #0] - 800d2b2: 6959 ldr r1, [r3, #20] - 800d2b4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d2b8: b29b uxth r3, r3 - 800d2ba: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d2be: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d2c2: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d2c6: 6800 ldr r0, [r0, #0] - 800d2c8: f001 fa65 bl 800e796 - 800d2cc: e3ee b.n 800daac + 800e558: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e55c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e560: 681b ldr r3, [r3, #0] + 800e562: 6959 ldr r1, [r3, #20] + 800e564: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e568: b29b uxth r3, r3 + 800e56a: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800e56e: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e572: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e576: 6800 ldr r0, [r0, #0] + 800e578: f001 fa65 bl 800fa46 + 800e57c: e3ee b.n 800ed5c } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - 800d2ce: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d2d2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d2d6: 681b ldr r3, [r3, #0] - 800d2d8: 785b ldrb r3, [r3, #1] - 800d2da: 2b00 cmp r3, #0 - 800d2dc: d177 bne.n 800d3ce - 800d2de: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d2e2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d2e6: 681b ldr r3, [r3, #0] - 800d2e8: 64bb str r3, [r7, #72] ; 0x48 - 800d2ea: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d2ee: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d2f2: 681b ldr r3, [r3, #0] - 800d2f4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d2f8: b29b uxth r3, r3 - 800d2fa: 461a mov r2, r3 - 800d2fc: 6cbb ldr r3, [r7, #72] ; 0x48 - 800d2fe: 4413 add r3, r2 - 800d300: 64bb str r3, [r7, #72] ; 0x48 - 800d302: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d306: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d30a: 681b ldr r3, [r3, #0] - 800d30c: 781b ldrb r3, [r3, #0] - 800d30e: 00da lsls r2, r3, #3 - 800d310: 6cbb ldr r3, [r7, #72] ; 0x48 - 800d312: 4413 add r3, r2 - 800d314: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d318: 647b str r3, [r7, #68] ; 0x44 - 800d31a: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d31c: 881b ldrh r3, [r3, #0] - 800d31e: b29b uxth r3, r3 - 800d320: f3c3 0309 ubfx r3, r3, #0, #10 - 800d324: b29a uxth r2, r3 - 800d326: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d328: 801a strh r2, [r3, #0] - 800d32a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d32e: 2b3e cmp r3, #62 ; 0x3e - 800d330: d921 bls.n 800d376 - 800d332: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d336: 095b lsrs r3, r3, #5 - 800d338: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 - 800d33c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d340: f003 031f and.w r3, r3, #31 - 800d344: 2b00 cmp r3, #0 - 800d346: d104 bne.n 800d352 - 800d348: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 - 800d34c: 3b01 subs r3, #1 - 800d34e: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 - 800d352: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d354: 881b ldrh r3, [r3, #0] - 800d356: b29a uxth r2, r3 - 800d358: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 - 800d35c: b29b uxth r3, r3 - 800d35e: 029b lsls r3, r3, #10 - 800d360: b29b uxth r3, r3 - 800d362: 4313 orrs r3, r2 - 800d364: b29b uxth r3, r3 - 800d366: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d36a: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d36e: b29a uxth r2, r3 - 800d370: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d372: 801a strh r2, [r3, #0] - 800d374: e056 b.n 800d424 - 800d376: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d37a: 2b00 cmp r3, #0 - 800d37c: d10a bne.n 800d394 - 800d37e: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d380: 881b ldrh r3, [r3, #0] - 800d382: b29b uxth r3, r3 - 800d384: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d388: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d38c: b29a uxth r2, r3 - 800d38e: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d390: 801a strh r2, [r3, #0] - 800d392: e047 b.n 800d424 - 800d394: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d398: 085b lsrs r3, r3, #1 - 800d39a: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 - 800d39e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d3a2: f003 0301 and.w r3, r3, #1 - 800d3a6: 2b00 cmp r3, #0 - 800d3a8: d004 beq.n 800d3b4 - 800d3aa: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 - 800d3ae: 3301 adds r3, #1 - 800d3b0: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 - 800d3b4: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d3b6: 881b ldrh r3, [r3, #0] - 800d3b8: b29a uxth r2, r3 - 800d3ba: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 - 800d3be: b29b uxth r3, r3 - 800d3c0: 029b lsls r3, r3, #10 - 800d3c2: b29b uxth r3, r3 - 800d3c4: 4313 orrs r3, r2 - 800d3c6: b29a uxth r2, r3 - 800d3c8: 6c7b ldr r3, [r7, #68] ; 0x44 - 800d3ca: 801a strh r2, [r3, #0] - 800d3cc: e02a b.n 800d424 - 800d3ce: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d3d2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d3d6: 681b ldr r3, [r3, #0] - 800d3d8: 785b ldrb r3, [r3, #1] - 800d3da: 2b01 cmp r3, #1 - 800d3dc: d122 bne.n 800d424 - 800d3de: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d3e2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d3e6: 681b ldr r3, [r3, #0] - 800d3e8: 653b str r3, [r7, #80] ; 0x50 - 800d3ea: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d3ee: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d3f2: 681b ldr r3, [r3, #0] - 800d3f4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d3f8: b29b uxth r3, r3 - 800d3fa: 461a mov r2, r3 - 800d3fc: 6d3b ldr r3, [r7, #80] ; 0x50 - 800d3fe: 4413 add r3, r2 - 800d400: 653b str r3, [r7, #80] ; 0x50 - 800d402: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d406: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d40a: 681b ldr r3, [r3, #0] - 800d40c: 781b ldrb r3, [r3, #0] - 800d40e: 00da lsls r2, r3, #3 - 800d410: 6d3b ldr r3, [r7, #80] ; 0x50 - 800d412: 4413 add r3, r2 - 800d414: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d418: 64fb str r3, [r7, #76] ; 0x4c - 800d41a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d41e: b29a uxth r2, r3 - 800d420: 6cfb ldr r3, [r7, #76] ; 0x4c - 800d422: 801a strh r2, [r3, #0] + 800e57e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e582: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e586: 681b ldr r3, [r3, #0] + 800e588: 785b ldrb r3, [r3, #1] + 800e58a: 2b00 cmp r3, #0 + 800e58c: d177 bne.n 800e67e + 800e58e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e592: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e596: 681b ldr r3, [r3, #0] + 800e598: 64bb str r3, [r7, #72] ; 0x48 + 800e59a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e59e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e5a2: 681b ldr r3, [r3, #0] + 800e5a4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e5a8: b29b uxth r3, r3 + 800e5aa: 461a mov r2, r3 + 800e5ac: 6cbb ldr r3, [r7, #72] ; 0x48 + 800e5ae: 4413 add r3, r2 + 800e5b0: 64bb str r3, [r7, #72] ; 0x48 + 800e5b2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e5b6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e5ba: 681b ldr r3, [r3, #0] + 800e5bc: 781b ldrb r3, [r3, #0] + 800e5be: 00da lsls r2, r3, #3 + 800e5c0: 6cbb ldr r3, [r7, #72] ; 0x48 + 800e5c2: 4413 add r3, r2 + 800e5c4: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e5c8: 647b str r3, [r7, #68] ; 0x44 + 800e5ca: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e5cc: 881b ldrh r3, [r3, #0] + 800e5ce: b29b uxth r3, r3 + 800e5d0: f3c3 0309 ubfx r3, r3, #0, #10 + 800e5d4: b29a uxth r2, r3 + 800e5d6: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e5d8: 801a strh r2, [r3, #0] + 800e5da: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e5de: 2b3e cmp r3, #62 ; 0x3e + 800e5e0: d921 bls.n 800e626 + 800e5e2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e5e6: 095b lsrs r3, r3, #5 + 800e5e8: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 + 800e5ec: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e5f0: f003 031f and.w r3, r3, #31 + 800e5f4: 2b00 cmp r3, #0 + 800e5f6: d104 bne.n 800e602 + 800e5f8: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 + 800e5fc: 3b01 subs r3, #1 + 800e5fe: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 + 800e602: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e604: 881b ldrh r3, [r3, #0] + 800e606: b29a uxth r2, r3 + 800e608: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 + 800e60c: b29b uxth r3, r3 + 800e60e: 029b lsls r3, r3, #10 + 800e610: b29b uxth r3, r3 + 800e612: 4313 orrs r3, r2 + 800e614: b29b uxth r3, r3 + 800e616: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e61a: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e61e: b29a uxth r2, r3 + 800e620: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e622: 801a strh r2, [r3, #0] + 800e624: e056 b.n 800e6d4 + 800e626: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e62a: 2b00 cmp r3, #0 + 800e62c: d10a bne.n 800e644 + 800e62e: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e630: 881b ldrh r3, [r3, #0] + 800e632: b29b uxth r3, r3 + 800e634: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e638: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e63c: b29a uxth r2, r3 + 800e63e: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e640: 801a strh r2, [r3, #0] + 800e642: e047 b.n 800e6d4 + 800e644: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e648: 085b lsrs r3, r3, #1 + 800e64a: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 + 800e64e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e652: f003 0301 and.w r3, r3, #1 + 800e656: 2b00 cmp r3, #0 + 800e658: d004 beq.n 800e664 + 800e65a: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 + 800e65e: 3301 adds r3, #1 + 800e660: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 + 800e664: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e666: 881b ldrh r3, [r3, #0] + 800e668: b29a uxth r2, r3 + 800e66a: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 + 800e66e: b29b uxth r3, r3 + 800e670: 029b lsls r3, r3, #10 + 800e672: b29b uxth r3, r3 + 800e674: 4313 orrs r3, r2 + 800e676: b29a uxth r2, r3 + 800e678: 6c7b ldr r3, [r7, #68] ; 0x44 + 800e67a: 801a strh r2, [r3, #0] + 800e67c: e02a b.n 800e6d4 + 800e67e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e682: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e686: 681b ldr r3, [r3, #0] + 800e688: 785b ldrb r3, [r3, #1] + 800e68a: 2b01 cmp r3, #1 + 800e68c: d122 bne.n 800e6d4 + 800e68e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e692: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e696: 681b ldr r3, [r3, #0] + 800e698: 653b str r3, [r7, #80] ; 0x50 + 800e69a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e69e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e6a2: 681b ldr r3, [r3, #0] + 800e6a4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e6a8: b29b uxth r3, r3 + 800e6aa: 461a mov r2, r3 + 800e6ac: 6d3b ldr r3, [r7, #80] ; 0x50 + 800e6ae: 4413 add r3, r2 + 800e6b0: 653b str r3, [r7, #80] ; 0x50 + 800e6b2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e6b6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e6ba: 681b ldr r3, [r3, #0] + 800e6bc: 781b ldrb r3, [r3, #0] + 800e6be: 00da lsls r2, r3, #3 + 800e6c0: 6d3b ldr r3, [r7, #80] ; 0x50 + 800e6c2: 4413 add r3, r2 + 800e6c4: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e6c8: 64fb str r3, [r7, #76] ; 0x4c + 800e6ca: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e6ce: b29a uxth r2, r3 + 800e6d0: 6cfb ldr r3, [r7, #76] ; 0x4c + 800e6d2: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; - 800d424: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d428: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d42c: 681b ldr r3, [r3, #0] - 800d42e: 891b ldrh r3, [r3, #8] - 800d430: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800e6d4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e6d8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e6dc: 681b ldr r3, [r3, #0] + 800e6de: 891b ldrh r3, [r3, #8] + 800e6e0: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d434: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d438: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d43c: 681b ldr r3, [r3, #0] - 800d43e: 6959 ldr r1, [r3, #20] - 800d440: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d444: b29b uxth r3, r3 - 800d446: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d44a: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d44e: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d452: 6800 ldr r0, [r0, #0] - 800d454: f001 f99f bl 800e796 + 800e6e4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e6e8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e6ec: 681b ldr r3, [r3, #0] + 800e6ee: 6959 ldr r1, [r3, #20] + 800e6f0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e6f4: b29b uxth r3, r3 + 800e6f6: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800e6fa: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e6fe: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e702: 6800 ldr r0, [r0, #0] + 800e704: f001 f99f bl 800fa46 ep->xfer_buff += len; - 800d458: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d45c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d460: 681b ldr r3, [r3, #0] - 800d462: 695a ldr r2, [r3, #20] - 800d464: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d468: 441a add r2, r3 - 800d46a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d46e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d472: 681b ldr r3, [r3, #0] - 800d474: 615a str r2, [r3, #20] + 800e708: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e70c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e710: 681b ldr r3, [r3, #0] + 800e712: 695a ldr r2, [r3, #20] + 800e714: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e718: 441a add r2, r3 + 800e71a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e71e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e722: 681b ldr r3, [r3, #0] + 800e724: 615a str r2, [r3, #20] if (ep->xfer_len_db > ep->maxpacket) - 800d476: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d47a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d47e: 681b ldr r3, [r3, #0] - 800d480: 6a1a ldr r2, [r3, #32] - 800d482: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d486: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d48a: 681b ldr r3, [r3, #0] - 800d48c: 691b ldr r3, [r3, #16] - 800d48e: 429a cmp r2, r3 - 800d490: d90f bls.n 800d4b2 + 800e726: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e72a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e72e: 681b ldr r3, [r3, #0] + 800e730: 6a1a ldr r2, [r3, #32] + 800e732: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e736: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e73a: 681b ldr r3, [r3, #0] + 800e73c: 691b ldr r3, [r3, #16] + 800e73e: 429a cmp r2, r3 + 800e740: d90f bls.n 800e762 { ep->xfer_len_db -= len; - 800d492: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d496: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d49a: 681b ldr r3, [r3, #0] - 800d49c: 6a1a ldr r2, [r3, #32] - 800d49e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d4a2: 1ad2 subs r2, r2, r3 - 800d4a4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4a8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d4ac: 681b ldr r3, [r3, #0] - 800d4ae: 621a str r2, [r3, #32] - 800d4b0: e00e b.n 800d4d0 + 800e742: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e746: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e74a: 681b ldr r3, [r3, #0] + 800e74c: 6a1a ldr r2, [r3, #32] + 800e74e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e752: 1ad2 subs r2, r2, r3 + 800e754: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e758: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e75c: 681b ldr r3, [r3, #0] + 800e75e: 621a str r2, [r3, #32] + 800e760: e00e b.n 800e780 } else { len = ep->xfer_len_db; - 800d4b2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4b6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d4ba: 681b ldr r3, [r3, #0] - 800d4bc: 6a1b ldr r3, [r3, #32] - 800d4be: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800e762: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e766: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e76a: 681b ldr r3, [r3, #0] + 800e76c: 6a1b ldr r3, [r3, #32] + 800e76e: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len_db = 0U; - 800d4c2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4c6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d4ca: 681b ldr r3, [r3, #0] - 800d4cc: 2200 movs r2, #0 - 800d4ce: 621a str r2, [r3, #32] + 800e772: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e776: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e77a: 681b ldr r3, [r3, #0] + 800e77c: 2200 movs r2, #0 + 800e77e: 621a str r2, [r3, #32] } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - 800d4d0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4d4: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d4d8: 681b ldr r3, [r3, #0] - 800d4da: 643b str r3, [r7, #64] ; 0x40 - 800d4dc: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4e0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d4e4: 681b ldr r3, [r3, #0] - 800d4e6: 785b ldrb r3, [r3, #1] - 800d4e8: 2b00 cmp r3, #0 - 800d4ea: d177 bne.n 800d5dc - 800d4ec: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4f0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d4f4: 681b ldr r3, [r3, #0] - 800d4f6: 63bb str r3, [r7, #56] ; 0x38 - 800d4f8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d4fc: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d500: 681b ldr r3, [r3, #0] - 800d502: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d506: b29b uxth r3, r3 - 800d508: 461a mov r2, r3 - 800d50a: 6bbb ldr r3, [r7, #56] ; 0x38 - 800d50c: 4413 add r3, r2 - 800d50e: 63bb str r3, [r7, #56] ; 0x38 - 800d510: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d514: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d518: 681b ldr r3, [r3, #0] - 800d51a: 781b ldrb r3, [r3, #0] - 800d51c: 00da lsls r2, r3, #3 - 800d51e: 6bbb ldr r3, [r7, #56] ; 0x38 - 800d520: 4413 add r3, r2 - 800d522: f203 4306 addw r3, r3, #1030 ; 0x406 - 800d526: 637b str r3, [r7, #52] ; 0x34 - 800d528: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d52a: 881b ldrh r3, [r3, #0] - 800d52c: b29b uxth r3, r3 - 800d52e: f3c3 0309 ubfx r3, r3, #0, #10 - 800d532: b29a uxth r2, r3 - 800d534: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d536: 801a strh r2, [r3, #0] - 800d538: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d53c: 2b3e cmp r3, #62 ; 0x3e - 800d53e: d921 bls.n 800d584 - 800d540: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d544: 095b lsrs r3, r3, #5 - 800d546: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 - 800d54a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d54e: f003 031f and.w r3, r3, #31 - 800d552: 2b00 cmp r3, #0 - 800d554: d104 bne.n 800d560 - 800d556: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800d55a: 3b01 subs r3, #1 - 800d55c: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 - 800d560: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d562: 881b ldrh r3, [r3, #0] - 800d564: b29a uxth r2, r3 - 800d566: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800d56a: b29b uxth r3, r3 - 800d56c: 029b lsls r3, r3, #10 - 800d56e: b29b uxth r3, r3 - 800d570: 4313 orrs r3, r2 - 800d572: b29b uxth r3, r3 - 800d574: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d578: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d57c: b29a uxth r2, r3 - 800d57e: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d580: 801a strh r2, [r3, #0] - 800d582: e050 b.n 800d626 - 800d584: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d588: 2b00 cmp r3, #0 - 800d58a: d10a bne.n 800d5a2 - 800d58c: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d58e: 881b ldrh r3, [r3, #0] - 800d590: b29b uxth r3, r3 - 800d592: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d596: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d59a: b29a uxth r2, r3 - 800d59c: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d59e: 801a strh r2, [r3, #0] - 800d5a0: e041 b.n 800d626 - 800d5a2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d5a6: 085b lsrs r3, r3, #1 - 800d5a8: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 - 800d5ac: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d5b0: f003 0301 and.w r3, r3, #1 - 800d5b4: 2b00 cmp r3, #0 - 800d5b6: d004 beq.n 800d5c2 - 800d5b8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800d5bc: 3301 adds r3, #1 - 800d5be: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 - 800d5c2: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d5c4: 881b ldrh r3, [r3, #0] - 800d5c6: b29a uxth r2, r3 - 800d5c8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800d5cc: b29b uxth r3, r3 - 800d5ce: 029b lsls r3, r3, #10 - 800d5d0: b29b uxth r3, r3 - 800d5d2: 4313 orrs r3, r2 - 800d5d4: b29a uxth r2, r3 - 800d5d6: 6b7b ldr r3, [r7, #52] ; 0x34 - 800d5d8: 801a strh r2, [r3, #0] - 800d5da: e024 b.n 800d626 - 800d5dc: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d5e0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d5e4: 681b ldr r3, [r3, #0] - 800d5e6: 785b ldrb r3, [r3, #1] - 800d5e8: 2b01 cmp r3, #1 - 800d5ea: d11c bne.n 800d626 - 800d5ec: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d5f0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d5f4: 681b ldr r3, [r3, #0] - 800d5f6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d5fa: b29b uxth r3, r3 - 800d5fc: 461a mov r2, r3 - 800d5fe: 6c3b ldr r3, [r7, #64] ; 0x40 - 800d600: 4413 add r3, r2 - 800d602: 643b str r3, [r7, #64] ; 0x40 - 800d604: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d608: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d60c: 681b ldr r3, [r3, #0] - 800d60e: 781b ldrb r3, [r3, #0] - 800d610: 00da lsls r2, r3, #3 - 800d612: 6c3b ldr r3, [r7, #64] ; 0x40 - 800d614: 4413 add r3, r2 - 800d616: f203 4306 addw r3, r3, #1030 ; 0x406 - 800d61a: 63fb str r3, [r7, #60] ; 0x3c - 800d61c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d620: b29a uxth r2, r3 - 800d622: 6bfb ldr r3, [r7, #60] ; 0x3c - 800d624: 801a strh r2, [r3, #0] + 800e780: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e784: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e788: 681b ldr r3, [r3, #0] + 800e78a: 643b str r3, [r7, #64] ; 0x40 + 800e78c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e790: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e794: 681b ldr r3, [r3, #0] + 800e796: 785b ldrb r3, [r3, #1] + 800e798: 2b00 cmp r3, #0 + 800e79a: d177 bne.n 800e88c + 800e79c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e7a0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e7a4: 681b ldr r3, [r3, #0] + 800e7a6: 63bb str r3, [r7, #56] ; 0x38 + 800e7a8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e7ac: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e7b0: 681b ldr r3, [r3, #0] + 800e7b2: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e7b6: b29b uxth r3, r3 + 800e7b8: 461a mov r2, r3 + 800e7ba: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e7bc: 4413 add r3, r2 + 800e7be: 63bb str r3, [r7, #56] ; 0x38 + 800e7c0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e7c4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e7c8: 681b ldr r3, [r3, #0] + 800e7ca: 781b ldrb r3, [r3, #0] + 800e7cc: 00da lsls r2, r3, #3 + 800e7ce: 6bbb ldr r3, [r7, #56] ; 0x38 + 800e7d0: 4413 add r3, r2 + 800e7d2: f203 4306 addw r3, r3, #1030 ; 0x406 + 800e7d6: 637b str r3, [r7, #52] ; 0x34 + 800e7d8: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e7da: 881b ldrh r3, [r3, #0] + 800e7dc: b29b uxth r3, r3 + 800e7de: f3c3 0309 ubfx r3, r3, #0, #10 + 800e7e2: b29a uxth r2, r3 + 800e7e4: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e7e6: 801a strh r2, [r3, #0] + 800e7e8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e7ec: 2b3e cmp r3, #62 ; 0x3e + 800e7ee: d921 bls.n 800e834 + 800e7f0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e7f4: 095b lsrs r3, r3, #5 + 800e7f6: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 + 800e7fa: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e7fe: f003 031f and.w r3, r3, #31 + 800e802: 2b00 cmp r3, #0 + 800e804: d104 bne.n 800e810 + 800e806: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800e80a: 3b01 subs r3, #1 + 800e80c: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 + 800e810: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e812: 881b ldrh r3, [r3, #0] + 800e814: b29a uxth r2, r3 + 800e816: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800e81a: b29b uxth r3, r3 + 800e81c: 029b lsls r3, r3, #10 + 800e81e: b29b uxth r3, r3 + 800e820: 4313 orrs r3, r2 + 800e822: b29b uxth r3, r3 + 800e824: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e828: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e82c: b29a uxth r2, r3 + 800e82e: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e830: 801a strh r2, [r3, #0] + 800e832: e050 b.n 800e8d6 + 800e834: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e838: 2b00 cmp r3, #0 + 800e83a: d10a bne.n 800e852 + 800e83c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e83e: 881b ldrh r3, [r3, #0] + 800e840: b29b uxth r3, r3 + 800e842: ea6f 4343 mvn.w r3, r3, lsl #17 + 800e846: ea6f 4353 mvn.w r3, r3, lsr #17 + 800e84a: b29a uxth r2, r3 + 800e84c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e84e: 801a strh r2, [r3, #0] + 800e850: e041 b.n 800e8d6 + 800e852: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e856: 085b lsrs r3, r3, #1 + 800e858: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 + 800e85c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e860: f003 0301 and.w r3, r3, #1 + 800e864: 2b00 cmp r3, #0 + 800e866: d004 beq.n 800e872 + 800e868: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800e86c: 3301 adds r3, #1 + 800e86e: f8c7 30f4 str.w r3, [r7, #244] ; 0xf4 + 800e872: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e874: 881b ldrh r3, [r3, #0] + 800e876: b29a uxth r2, r3 + 800e878: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800e87c: b29b uxth r3, r3 + 800e87e: 029b lsls r3, r3, #10 + 800e880: b29b uxth r3, r3 + 800e882: 4313 orrs r3, r2 + 800e884: b29a uxth r2, r3 + 800e886: 6b7b ldr r3, [r7, #52] ; 0x34 + 800e888: 801a strh r2, [r3, #0] + 800e88a: e024 b.n 800e8d6 + 800e88c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e890: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e894: 681b ldr r3, [r3, #0] + 800e896: 785b ldrb r3, [r3, #1] + 800e898: 2b01 cmp r3, #1 + 800e89a: d11c bne.n 800e8d6 + 800e89c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e8a0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e8a4: 681b ldr r3, [r3, #0] + 800e8a6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e8aa: b29b uxth r3, r3 + 800e8ac: 461a mov r2, r3 + 800e8ae: 6c3b ldr r3, [r7, #64] ; 0x40 + 800e8b0: 4413 add r3, r2 + 800e8b2: 643b str r3, [r7, #64] ; 0x40 + 800e8b4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e8b8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e8bc: 681b ldr r3, [r3, #0] + 800e8be: 781b ldrb r3, [r3, #0] + 800e8c0: 00da lsls r2, r3, #3 + 800e8c2: 6c3b ldr r3, [r7, #64] ; 0x40 + 800e8c4: 4413 add r3, r2 + 800e8c6: f203 4306 addw r3, r3, #1030 ; 0x406 + 800e8ca: 63fb str r3, [r7, #60] ; 0x3c + 800e8cc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e8d0: b29a uxth r2, r3 + 800e8d2: 6bfb ldr r3, [r7, #60] ; 0x3c + 800e8d4: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; - 800d626: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d62a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d62e: 681b ldr r3, [r3, #0] - 800d630: 895b ldrh r3, [r3, #10] - 800d632: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800e8d6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e8da: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e8de: 681b ldr r3, [r3, #0] + 800e8e0: 895b ldrh r3, [r3, #10] + 800e8e2: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d636: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d63a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d63e: 681b ldr r3, [r3, #0] - 800d640: 6959 ldr r1, [r3, #20] - 800d642: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d646: b29b uxth r3, r3 - 800d648: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d64c: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d650: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d654: 6800 ldr r0, [r0, #0] - 800d656: f001 f89e bl 800e796 - 800d65a: e227 b.n 800daac + 800e8e6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e8ea: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e8ee: 681b ldr r3, [r3, #0] + 800e8f0: 6959 ldr r1, [r3, #20] + 800e8f2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e8f6: b29b uxth r3, r3 + 800e8f8: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800e8fc: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e900: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e904: 6800 ldr r0, [r0, #0] + 800e906: f001 f89e bl 800fa46 + 800e90a: e227 b.n 800ed5c } } /* auto Switch to single buffer mode when transfer xfer_len_db; - 800d65c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d660: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d664: 681b ldr r3, [r3, #0] - 800d666: 6a1b ldr r3, [r3, #32] - 800d668: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800e90c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e910: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e914: 681b ldr r3, [r3, #0] + 800e916: 6a1b ldr r3, [r3, #32] + 800e918: f8c7 3104 str.w r3, [r7, #260] ; 0x104 /* disable double buffer mode for Bulk endpoint */ PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); - 800d66c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d670: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d674: 681a ldr r2, [r3, #0] - 800d676: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d67a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d67e: 681b ldr r3, [r3, #0] - 800d680: 781b ldrb r3, [r3, #0] - 800d682: 009b lsls r3, r3, #2 - 800d684: 4413 add r3, r2 - 800d686: 881b ldrh r3, [r3, #0] - 800d688: b29b uxth r3, r3 - 800d68a: f423 43e2 bic.w r3, r3, #28928 ; 0x7100 - 800d68e: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800d692: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 - 800d696: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d69a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d69e: 681a ldr r2, [r3, #0] - 800d6a0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d6a4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d6a8: 681b ldr r3, [r3, #0] - 800d6aa: 781b ldrb r3, [r3, #0] - 800d6ac: 009b lsls r3, r3, #2 - 800d6ae: 441a add r2, r3 - 800d6b0: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 - 800d6b4: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800d6b8: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800d6bc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800d6c0: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800d6c4: b29b uxth r3, r3 - 800d6c6: 8013 strh r3, [r2, #0] + 800e91c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e920: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e924: 681a ldr r2, [r3, #0] + 800e926: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e92a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e92e: 681b ldr r3, [r3, #0] + 800e930: 781b ldrb r3, [r3, #0] + 800e932: 009b lsls r3, r3, #2 + 800e934: 4413 add r3, r2 + 800e936: 881b ldrh r3, [r3, #0] + 800e938: b29b uxth r3, r3 + 800e93a: f423 43e2 bic.w r3, r3, #28928 ; 0x7100 + 800e93e: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800e942: f8a7 3062 strh.w r3, [r7, #98] ; 0x62 + 800e946: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e94a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e94e: 681a ldr r2, [r3, #0] + 800e950: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e954: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e958: 681b ldr r3, [r3, #0] + 800e95a: 781b ldrb r3, [r3, #0] + 800e95c: 009b lsls r3, r3, #2 + 800e95e: 441a add r2, r3 + 800e960: f8b7 3062 ldrh.w r3, [r7, #98] ; 0x62 + 800e964: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800e968: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800e96c: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800e970: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800e974: b29b uxth r3, r3 + 800e976: 8013 strh r3, [r2, #0] /* Set Tx count with nbre of byte to be transmitted */ PCD_SET_EP_TX_CNT(USBx, ep->num, len); - 800d6c8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d6cc: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d6d0: 681b ldr r3, [r3, #0] - 800d6d2: 65fb str r3, [r7, #92] ; 0x5c - 800d6d4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d6d8: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d6dc: 681b ldr r3, [r3, #0] - 800d6de: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d6e2: b29b uxth r3, r3 - 800d6e4: 461a mov r2, r3 - 800d6e6: 6dfb ldr r3, [r7, #92] ; 0x5c - 800d6e8: 4413 add r3, r2 - 800d6ea: 65fb str r3, [r7, #92] ; 0x5c - 800d6ec: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d6f0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d6f4: 681b ldr r3, [r3, #0] - 800d6f6: 781b ldrb r3, [r3, #0] - 800d6f8: 00da lsls r2, r3, #3 - 800d6fa: 6dfb ldr r3, [r7, #92] ; 0x5c - 800d6fc: 4413 add r3, r2 - 800d6fe: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d702: 65bb str r3, [r7, #88] ; 0x58 - 800d704: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d708: b29a uxth r2, r3 - 800d70a: 6dbb ldr r3, [r7, #88] ; 0x58 - 800d70c: 801a strh r2, [r3, #0] + 800e978: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e97c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e980: 681b ldr r3, [r3, #0] + 800e982: 65fb str r3, [r7, #92] ; 0x5c + 800e984: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e988: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800e98c: 681b ldr r3, [r3, #0] + 800e98e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800e992: b29b uxth r3, r3 + 800e994: 461a mov r2, r3 + 800e996: 6dfb ldr r3, [r7, #92] ; 0x5c + 800e998: 4413 add r3, r2 + 800e99a: 65fb str r3, [r7, #92] ; 0x5c + 800e99c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e9a0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e9a4: 681b ldr r3, [r3, #0] + 800e9a6: 781b ldrb r3, [r3, #0] + 800e9a8: 00da lsls r2, r3, #3 + 800e9aa: 6dfb ldr r3, [r7, #92] ; 0x5c + 800e9ac: 4413 add r3, r2 + 800e9ae: f203 4302 addw r3, r3, #1026 ; 0x402 + 800e9b2: 65bb str r3, [r7, #88] ; 0x58 + 800e9b4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e9b8: b29a uxth r2, r3 + 800e9ba: 6dbb ldr r3, [r7, #88] ; 0x58 + 800e9bc: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; - 800d70e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d712: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d716: 681b ldr r3, [r3, #0] - 800d718: 891b ldrh r3, [r3, #8] - 800d71a: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800e9be: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e9c2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e9c6: 681b ldr r3, [r3, #0] + 800e9c8: 891b ldrh r3, [r3, #8] + 800e9ca: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d71e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d722: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d726: 681b ldr r3, [r3, #0] - 800d728: 6959 ldr r1, [r3, #20] - 800d72a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d72e: b29b uxth r3, r3 - 800d730: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d734: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d738: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d73c: 6800 ldr r0, [r0, #0] - 800d73e: f001 f82a bl 800e796 - 800d742: e1b3 b.n 800daac + 800e9ce: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e9d2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e9d6: 681b ldr r3, [r3, #0] + 800e9d8: 6959 ldr r1, [r3, #20] + 800e9da: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800e9de: b29b uxth r3, r3 + 800e9e0: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800e9e4: f507 7084 add.w r0, r7, #264 ; 0x108 + 800e9e8: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800e9ec: 6800 ldr r0, [r0, #0] + 800e9ee: f001 f82a bl 800fa46 + 800e9f2: e1b3 b.n 800ed5c } } else /* manage isochronous double buffer IN mode */ { /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; - 800d744: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d748: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d74c: 681b ldr r3, [r3, #0] - 800d74e: 6a1a ldr r2, [r3, #32] - 800d750: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d754: 1ad2 subs r2, r2, r3 - 800d756: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d75a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d75e: 681b ldr r3, [r3, #0] - 800d760: 621a str r2, [r3, #32] + 800e9f4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800e9f8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800e9fc: 681b ldr r3, [r3, #0] + 800e9fe: 6a1a ldr r2, [r3, #32] + 800ea00: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ea04: 1ad2 subs r2, r2, r3 + 800ea06: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea0a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ea0e: 681b ldr r3, [r3, #0] + 800ea10: 621a str r2, [r3, #32] /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - 800d762: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d766: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d76a: 681a ldr r2, [r3, #0] - 800d76c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d770: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d774: 681b ldr r3, [r3, #0] - 800d776: 781b ldrb r3, [r3, #0] - 800d778: 009b lsls r3, r3, #2 - 800d77a: 4413 add r3, r2 - 800d77c: 881b ldrh r3, [r3, #0] - 800d77e: b29b uxth r3, r3 - 800d780: f003 0340 and.w r3, r3, #64 ; 0x40 - 800d784: 2b00 cmp r3, #0 - 800d786: f000 80c6 beq.w 800d916 + 800ea12: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea16: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ea1a: 681a ldr r2, [r3, #0] + 800ea1c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea20: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ea24: 681b ldr r3, [r3, #0] + 800ea26: 781b ldrb r3, [r3, #0] + 800ea28: 009b lsls r3, r3, #2 + 800ea2a: 4413 add r3, r2 + 800ea2c: 881b ldrh r3, [r3, #0] + 800ea2e: b29b uxth r3, r3 + 800ea30: f003 0340 and.w r3, r3, #64 ; 0x40 + 800ea34: 2b00 cmp r3, #0 + 800ea36: f000 80c6 beq.w 800ebc6 { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - 800d78a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d78e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d792: 681b ldr r3, [r3, #0] - 800d794: 673b str r3, [r7, #112] ; 0x70 - 800d796: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d79a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d79e: 681b ldr r3, [r3, #0] - 800d7a0: 785b ldrb r3, [r3, #1] - 800d7a2: 2b00 cmp r3, #0 - 800d7a4: d177 bne.n 800d896 - 800d7a6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d7aa: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d7ae: 681b ldr r3, [r3, #0] - 800d7b0: 66bb str r3, [r7, #104] ; 0x68 - 800d7b2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d7b6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d7ba: 681b ldr r3, [r3, #0] - 800d7bc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d7c0: b29b uxth r3, r3 - 800d7c2: 461a mov r2, r3 - 800d7c4: 6ebb ldr r3, [r7, #104] ; 0x68 - 800d7c6: 4413 add r3, r2 - 800d7c8: 66bb str r3, [r7, #104] ; 0x68 - 800d7ca: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d7ce: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d7d2: 681b ldr r3, [r3, #0] - 800d7d4: 781b ldrb r3, [r3, #0] - 800d7d6: 00da lsls r2, r3, #3 - 800d7d8: 6ebb ldr r3, [r7, #104] ; 0x68 - 800d7da: 4413 add r3, r2 - 800d7dc: f203 4306 addw r3, r3, #1030 ; 0x406 - 800d7e0: 667b str r3, [r7, #100] ; 0x64 - 800d7e2: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d7e4: 881b ldrh r3, [r3, #0] - 800d7e6: b29b uxth r3, r3 - 800d7e8: f3c3 0309 ubfx r3, r3, #0, #10 - 800d7ec: b29a uxth r2, r3 - 800d7ee: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d7f0: 801a strh r2, [r3, #0] - 800d7f2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d7f6: 2b3e cmp r3, #62 ; 0x3e - 800d7f8: d921 bls.n 800d83e - 800d7fa: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d7fe: 095b lsrs r3, r3, #5 - 800d800: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 - 800d804: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d808: f003 031f and.w r3, r3, #31 - 800d80c: 2b00 cmp r3, #0 - 800d80e: d104 bne.n 800d81a - 800d810: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 - 800d814: 3b01 subs r3, #1 - 800d816: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 - 800d81a: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d81c: 881b ldrh r3, [r3, #0] - 800d81e: b29a uxth r2, r3 - 800d820: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 - 800d824: b29b uxth r3, r3 - 800d826: 029b lsls r3, r3, #10 - 800d828: b29b uxth r3, r3 - 800d82a: 4313 orrs r3, r2 - 800d82c: b29b uxth r3, r3 - 800d82e: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d832: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d836: b29a uxth r2, r3 - 800d838: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d83a: 801a strh r2, [r3, #0] - 800d83c: e050 b.n 800d8e0 - 800d83e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d842: 2b00 cmp r3, #0 - 800d844: d10a bne.n 800d85c - 800d846: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d848: 881b ldrh r3, [r3, #0] - 800d84a: b29b uxth r3, r3 - 800d84c: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d850: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d854: b29a uxth r2, r3 - 800d856: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d858: 801a strh r2, [r3, #0] - 800d85a: e041 b.n 800d8e0 - 800d85c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d860: 085b lsrs r3, r3, #1 - 800d862: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 - 800d866: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d86a: f003 0301 and.w r3, r3, #1 - 800d86e: 2b00 cmp r3, #0 - 800d870: d004 beq.n 800d87c - 800d872: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 - 800d876: 3301 adds r3, #1 - 800d878: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 - 800d87c: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d87e: 881b ldrh r3, [r3, #0] - 800d880: b29a uxth r2, r3 - 800d882: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 - 800d886: b29b uxth r3, r3 - 800d888: 029b lsls r3, r3, #10 - 800d88a: b29b uxth r3, r3 - 800d88c: 4313 orrs r3, r2 - 800d88e: b29a uxth r2, r3 - 800d890: 6e7b ldr r3, [r7, #100] ; 0x64 - 800d892: 801a strh r2, [r3, #0] - 800d894: e024 b.n 800d8e0 - 800d896: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d89a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d89e: 681b ldr r3, [r3, #0] - 800d8a0: 785b ldrb r3, [r3, #1] - 800d8a2: 2b01 cmp r3, #1 - 800d8a4: d11c bne.n 800d8e0 - 800d8a6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d8aa: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d8ae: 681b ldr r3, [r3, #0] - 800d8b0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d8b4: b29b uxth r3, r3 - 800d8b6: 461a mov r2, r3 - 800d8b8: 6f3b ldr r3, [r7, #112] ; 0x70 - 800d8ba: 4413 add r3, r2 - 800d8bc: 673b str r3, [r7, #112] ; 0x70 - 800d8be: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d8c2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d8c6: 681b ldr r3, [r3, #0] - 800d8c8: 781b ldrb r3, [r3, #0] - 800d8ca: 00da lsls r2, r3, #3 - 800d8cc: 6f3b ldr r3, [r7, #112] ; 0x70 - 800d8ce: 4413 add r3, r2 - 800d8d0: f203 4306 addw r3, r3, #1030 ; 0x406 - 800d8d4: 66fb str r3, [r7, #108] ; 0x6c - 800d8d6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d8da: b29a uxth r2, r3 - 800d8dc: 6efb ldr r3, [r7, #108] ; 0x6c - 800d8de: 801a strh r2, [r3, #0] + 800ea3a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea3e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ea42: 681b ldr r3, [r3, #0] + 800ea44: 673b str r3, [r7, #112] ; 0x70 + 800ea46: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea4a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ea4e: 681b ldr r3, [r3, #0] + 800ea50: 785b ldrb r3, [r3, #1] + 800ea52: 2b00 cmp r3, #0 + 800ea54: d177 bne.n 800eb46 + 800ea56: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea5a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ea5e: 681b ldr r3, [r3, #0] + 800ea60: 66bb str r3, [r7, #104] ; 0x68 + 800ea62: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea66: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ea6a: 681b ldr r3, [r3, #0] + 800ea6c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800ea70: b29b uxth r3, r3 + 800ea72: 461a mov r2, r3 + 800ea74: 6ebb ldr r3, [r7, #104] ; 0x68 + 800ea76: 4413 add r3, r2 + 800ea78: 66bb str r3, [r7, #104] ; 0x68 + 800ea7a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ea7e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ea82: 681b ldr r3, [r3, #0] + 800ea84: 781b ldrb r3, [r3, #0] + 800ea86: 00da lsls r2, r3, #3 + 800ea88: 6ebb ldr r3, [r7, #104] ; 0x68 + 800ea8a: 4413 add r3, r2 + 800ea8c: f203 4306 addw r3, r3, #1030 ; 0x406 + 800ea90: 667b str r3, [r7, #100] ; 0x64 + 800ea92: 6e7b ldr r3, [r7, #100] ; 0x64 + 800ea94: 881b ldrh r3, [r3, #0] + 800ea96: b29b uxth r3, r3 + 800ea98: f3c3 0309 ubfx r3, r3, #0, #10 + 800ea9c: b29a uxth r2, r3 + 800ea9e: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eaa0: 801a strh r2, [r3, #0] + 800eaa2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eaa6: 2b3e cmp r3, #62 ; 0x3e + 800eaa8: d921 bls.n 800eaee + 800eaaa: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eaae: 095b lsrs r3, r3, #5 + 800eab0: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 + 800eab4: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eab8: f003 031f and.w r3, r3, #31 + 800eabc: 2b00 cmp r3, #0 + 800eabe: d104 bne.n 800eaca + 800eac0: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 + 800eac4: 3b01 subs r3, #1 + 800eac6: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 + 800eaca: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eacc: 881b ldrh r3, [r3, #0] + 800eace: b29a uxth r2, r3 + 800ead0: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 + 800ead4: b29b uxth r3, r3 + 800ead6: 029b lsls r3, r3, #10 + 800ead8: b29b uxth r3, r3 + 800eada: 4313 orrs r3, r2 + 800eadc: b29b uxth r3, r3 + 800eade: ea6f 4343 mvn.w r3, r3, lsl #17 + 800eae2: ea6f 4353 mvn.w r3, r3, lsr #17 + 800eae6: b29a uxth r2, r3 + 800eae8: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eaea: 801a strh r2, [r3, #0] + 800eaec: e050 b.n 800eb90 + 800eaee: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eaf2: 2b00 cmp r3, #0 + 800eaf4: d10a bne.n 800eb0c + 800eaf6: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eaf8: 881b ldrh r3, [r3, #0] + 800eafa: b29b uxth r3, r3 + 800eafc: ea6f 4343 mvn.w r3, r3, lsl #17 + 800eb00: ea6f 4353 mvn.w r3, r3, lsr #17 + 800eb04: b29a uxth r2, r3 + 800eb06: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eb08: 801a strh r2, [r3, #0] + 800eb0a: e041 b.n 800eb90 + 800eb0c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eb10: 085b lsrs r3, r3, #1 + 800eb12: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 + 800eb16: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eb1a: f003 0301 and.w r3, r3, #1 + 800eb1e: 2b00 cmp r3, #0 + 800eb20: d004 beq.n 800eb2c + 800eb22: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 + 800eb26: 3301 adds r3, #1 + 800eb28: f8c7 30f0 str.w r3, [r7, #240] ; 0xf0 + 800eb2c: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eb2e: 881b ldrh r3, [r3, #0] + 800eb30: b29a uxth r2, r3 + 800eb32: f8d7 30f0 ldr.w r3, [r7, #240] ; 0xf0 + 800eb36: b29b uxth r3, r3 + 800eb38: 029b lsls r3, r3, #10 + 800eb3a: b29b uxth r3, r3 + 800eb3c: 4313 orrs r3, r2 + 800eb3e: b29a uxth r2, r3 + 800eb40: 6e7b ldr r3, [r7, #100] ; 0x64 + 800eb42: 801a strh r2, [r3, #0] + 800eb44: e024 b.n 800eb90 + 800eb46: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eb4a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eb4e: 681b ldr r3, [r3, #0] + 800eb50: 785b ldrb r3, [r3, #1] + 800eb52: 2b01 cmp r3, #1 + 800eb54: d11c bne.n 800eb90 + 800eb56: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eb5a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800eb5e: 681b ldr r3, [r3, #0] + 800eb60: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800eb64: b29b uxth r3, r3 + 800eb66: 461a mov r2, r3 + 800eb68: 6f3b ldr r3, [r7, #112] ; 0x70 + 800eb6a: 4413 add r3, r2 + 800eb6c: 673b str r3, [r7, #112] ; 0x70 + 800eb6e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eb72: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eb76: 681b ldr r3, [r3, #0] + 800eb78: 781b ldrb r3, [r3, #0] + 800eb7a: 00da lsls r2, r3, #3 + 800eb7c: 6f3b ldr r3, [r7, #112] ; 0x70 + 800eb7e: 4413 add r3, r2 + 800eb80: f203 4306 addw r3, r3, #1030 ; 0x406 + 800eb84: 66fb str r3, [r7, #108] ; 0x6c + 800eb86: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eb8a: b29a uxth r2, r3 + 800eb8c: 6efb ldr r3, [r7, #108] ; 0x6c + 800eb8e: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr1; - 800d8e0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d8e4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d8e8: 681b ldr r3, [r3, #0] - 800d8ea: 895b ldrh r3, [r3, #10] - 800d8ec: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800eb90: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eb94: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eb98: 681b ldr r3, [r3, #0] + 800eb9a: 895b ldrh r3, [r3, #10] + 800eb9c: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800d8f0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d8f4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d8f8: 681b ldr r3, [r3, #0] - 800d8fa: 6959 ldr r1, [r3, #20] - 800d8fc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d900: b29b uxth r3, r3 - 800d902: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800d906: f507 7084 add.w r0, r7, #264 ; 0x108 - 800d90a: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800d90e: 6800 ldr r0, [r0, #0] - 800d910: f000 ff41 bl 800e796 - 800d914: e0ca b.n 800daac + 800eba0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eba4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eba8: 681b ldr r3, [r3, #0] + 800ebaa: 6959 ldr r1, [r3, #20] + 800ebac: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ebb0: b29b uxth r3, r3 + 800ebb2: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800ebb6: f507 7084 add.w r0, r7, #264 ; 0x108 + 800ebba: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800ebbe: 6800 ldr r0, [r0, #0] + 800ebc0: f000 ff41 bl 800fa46 + 800ebc4: e0ca b.n 800ed5c } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - 800d916: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d91a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d91e: 681b ldr r3, [r3, #0] - 800d920: 785b ldrb r3, [r3, #1] - 800d922: 2b00 cmp r3, #0 - 800d924: d177 bne.n 800da16 - 800d926: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d92a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d92e: 681b ldr r3, [r3, #0] - 800d930: 67fb str r3, [r7, #124] ; 0x7c - 800d932: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d936: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800d93a: 681b ldr r3, [r3, #0] - 800d93c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800d940: b29b uxth r3, r3 - 800d942: 461a mov r2, r3 - 800d944: 6ffb ldr r3, [r7, #124] ; 0x7c - 800d946: 4413 add r3, r2 - 800d948: 67fb str r3, [r7, #124] ; 0x7c - 800d94a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800d94e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800d952: 681b ldr r3, [r3, #0] - 800d954: 781b ldrb r3, [r3, #0] - 800d956: 00da lsls r2, r3, #3 - 800d958: 6ffb ldr r3, [r7, #124] ; 0x7c - 800d95a: 4413 add r3, r2 - 800d95c: f203 4302 addw r3, r3, #1026 ; 0x402 - 800d960: 67bb str r3, [r7, #120] ; 0x78 - 800d962: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d964: 881b ldrh r3, [r3, #0] - 800d966: b29b uxth r3, r3 - 800d968: f3c3 0309 ubfx r3, r3, #0, #10 - 800d96c: b29a uxth r2, r3 - 800d96e: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d970: 801a strh r2, [r3, #0] - 800d972: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d976: 2b3e cmp r3, #62 ; 0x3e - 800d978: d921 bls.n 800d9be - 800d97a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d97e: 095b lsrs r3, r3, #5 - 800d980: f8c7 30ec str.w r3, [r7, #236] ; 0xec - 800d984: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d988: f003 031f and.w r3, r3, #31 - 800d98c: 2b00 cmp r3, #0 - 800d98e: d104 bne.n 800d99a - 800d990: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec - 800d994: 3b01 subs r3, #1 - 800d996: f8c7 30ec str.w r3, [r7, #236] ; 0xec - 800d99a: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d99c: 881b ldrh r3, [r3, #0] - 800d99e: b29a uxth r2, r3 - 800d9a0: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec - 800d9a4: b29b uxth r3, r3 - 800d9a6: 029b lsls r3, r3, #10 - 800d9a8: b29b uxth r3, r3 - 800d9aa: 4313 orrs r3, r2 - 800d9ac: b29b uxth r3, r3 - 800d9ae: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d9b2: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d9b6: b29a uxth r2, r3 - 800d9b8: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d9ba: 801a strh r2, [r3, #0] - 800d9bc: e05c b.n 800da78 - 800d9be: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d9c2: 2b00 cmp r3, #0 - 800d9c4: d10a bne.n 800d9dc - 800d9c6: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d9c8: 881b ldrh r3, [r3, #0] - 800d9ca: b29b uxth r3, r3 - 800d9cc: ea6f 4343 mvn.w r3, r3, lsl #17 - 800d9d0: ea6f 4353 mvn.w r3, r3, lsr #17 - 800d9d4: b29a uxth r2, r3 - 800d9d6: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d9d8: 801a strh r2, [r3, #0] - 800d9da: e04d b.n 800da78 - 800d9dc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d9e0: 085b lsrs r3, r3, #1 - 800d9e2: f8c7 30ec str.w r3, [r7, #236] ; 0xec - 800d9e6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800d9ea: f003 0301 and.w r3, r3, #1 - 800d9ee: 2b00 cmp r3, #0 - 800d9f0: d004 beq.n 800d9fc - 800d9f2: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec - 800d9f6: 3301 adds r3, #1 - 800d9f8: f8c7 30ec str.w r3, [r7, #236] ; 0xec - 800d9fc: 6fbb ldr r3, [r7, #120] ; 0x78 - 800d9fe: 881b ldrh r3, [r3, #0] - 800da00: b29a uxth r2, r3 - 800da02: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec - 800da06: b29b uxth r3, r3 - 800da08: 029b lsls r3, r3, #10 - 800da0a: b29b uxth r3, r3 - 800da0c: 4313 orrs r3, r2 - 800da0e: b29a uxth r2, r3 - 800da10: 6fbb ldr r3, [r7, #120] ; 0x78 - 800da12: 801a strh r2, [r3, #0] - 800da14: e030 b.n 800da78 - 800da16: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da1a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800da1e: 681b ldr r3, [r3, #0] - 800da20: 785b ldrb r3, [r3, #1] - 800da22: 2b01 cmp r3, #1 - 800da24: d128 bne.n 800da78 - 800da26: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da2a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800da2e: 681b ldr r3, [r3, #0] - 800da30: f8c7 3084 str.w r3, [r7, #132] ; 0x84 - 800da34: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da38: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800da3c: 681b ldr r3, [r3, #0] - 800da3e: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800da42: b29b uxth r3, r3 - 800da44: 461a mov r2, r3 - 800da46: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 800da4a: 4413 add r3, r2 - 800da4c: f8c7 3084 str.w r3, [r7, #132] ; 0x84 - 800da50: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da54: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800da58: 681b ldr r3, [r3, #0] - 800da5a: 781b ldrb r3, [r3, #0] - 800da5c: 00da lsls r2, r3, #3 - 800da5e: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 - 800da62: 4413 add r3, r2 - 800da64: f203 4302 addw r3, r3, #1026 ; 0x402 - 800da68: f8c7 3080 str.w r3, [r7, #128] ; 0x80 - 800da6c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800da70: b29a uxth r2, r3 - 800da72: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 - 800da76: 801a strh r2, [r3, #0] + 800ebc6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ebca: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ebce: 681b ldr r3, [r3, #0] + 800ebd0: 785b ldrb r3, [r3, #1] + 800ebd2: 2b00 cmp r3, #0 + 800ebd4: d177 bne.n 800ecc6 + 800ebd6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ebda: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ebde: 681b ldr r3, [r3, #0] + 800ebe0: 67fb str r3, [r7, #124] ; 0x7c + 800ebe2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ebe6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ebea: 681b ldr r3, [r3, #0] + 800ebec: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800ebf0: b29b uxth r3, r3 + 800ebf2: 461a mov r2, r3 + 800ebf4: 6ffb ldr r3, [r7, #124] ; 0x7c + 800ebf6: 4413 add r3, r2 + 800ebf8: 67fb str r3, [r7, #124] ; 0x7c + 800ebfa: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ebfe: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ec02: 681b ldr r3, [r3, #0] + 800ec04: 781b ldrb r3, [r3, #0] + 800ec06: 00da lsls r2, r3, #3 + 800ec08: 6ffb ldr r3, [r7, #124] ; 0x7c + 800ec0a: 4413 add r3, r2 + 800ec0c: f203 4302 addw r3, r3, #1026 ; 0x402 + 800ec10: 67bb str r3, [r7, #120] ; 0x78 + 800ec12: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec14: 881b ldrh r3, [r3, #0] + 800ec16: b29b uxth r3, r3 + 800ec18: f3c3 0309 ubfx r3, r3, #0, #10 + 800ec1c: b29a uxth r2, r3 + 800ec1e: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec20: 801a strh r2, [r3, #0] + 800ec22: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec26: 2b3e cmp r3, #62 ; 0x3e + 800ec28: d921 bls.n 800ec6e + 800ec2a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec2e: 095b lsrs r3, r3, #5 + 800ec30: f8c7 30ec str.w r3, [r7, #236] ; 0xec + 800ec34: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec38: f003 031f and.w r3, r3, #31 + 800ec3c: 2b00 cmp r3, #0 + 800ec3e: d104 bne.n 800ec4a + 800ec40: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec + 800ec44: 3b01 subs r3, #1 + 800ec46: f8c7 30ec str.w r3, [r7, #236] ; 0xec + 800ec4a: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec4c: 881b ldrh r3, [r3, #0] + 800ec4e: b29a uxth r2, r3 + 800ec50: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec + 800ec54: b29b uxth r3, r3 + 800ec56: 029b lsls r3, r3, #10 + 800ec58: b29b uxth r3, r3 + 800ec5a: 4313 orrs r3, r2 + 800ec5c: b29b uxth r3, r3 + 800ec5e: ea6f 4343 mvn.w r3, r3, lsl #17 + 800ec62: ea6f 4353 mvn.w r3, r3, lsr #17 + 800ec66: b29a uxth r2, r3 + 800ec68: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec6a: 801a strh r2, [r3, #0] + 800ec6c: e05c b.n 800ed28 + 800ec6e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec72: 2b00 cmp r3, #0 + 800ec74: d10a bne.n 800ec8c + 800ec76: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec78: 881b ldrh r3, [r3, #0] + 800ec7a: b29b uxth r3, r3 + 800ec7c: ea6f 4343 mvn.w r3, r3, lsl #17 + 800ec80: ea6f 4353 mvn.w r3, r3, lsr #17 + 800ec84: b29a uxth r2, r3 + 800ec86: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ec88: 801a strh r2, [r3, #0] + 800ec8a: e04d b.n 800ed28 + 800ec8c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec90: 085b lsrs r3, r3, #1 + 800ec92: f8c7 30ec str.w r3, [r7, #236] ; 0xec + 800ec96: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ec9a: f003 0301 and.w r3, r3, #1 + 800ec9e: 2b00 cmp r3, #0 + 800eca0: d004 beq.n 800ecac + 800eca2: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec + 800eca6: 3301 adds r3, #1 + 800eca8: f8c7 30ec str.w r3, [r7, #236] ; 0xec + 800ecac: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ecae: 881b ldrh r3, [r3, #0] + 800ecb0: b29a uxth r2, r3 + 800ecb2: f8d7 30ec ldr.w r3, [r7, #236] ; 0xec + 800ecb6: b29b uxth r3, r3 + 800ecb8: 029b lsls r3, r3, #10 + 800ecba: b29b uxth r3, r3 + 800ecbc: 4313 orrs r3, r2 + 800ecbe: b29a uxth r2, r3 + 800ecc0: 6fbb ldr r3, [r7, #120] ; 0x78 + 800ecc2: 801a strh r2, [r3, #0] + 800ecc4: e030 b.n 800ed28 + 800ecc6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ecca: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ecce: 681b ldr r3, [r3, #0] + 800ecd0: 785b ldrb r3, [r3, #1] + 800ecd2: 2b01 cmp r3, #1 + 800ecd4: d128 bne.n 800ed28 + 800ecd6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ecda: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ecde: 681b ldr r3, [r3, #0] + 800ece0: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 800ece4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ece8: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ecec: 681b ldr r3, [r3, #0] + 800ecee: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800ecf2: b29b uxth r3, r3 + 800ecf4: 461a mov r2, r3 + 800ecf6: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 800ecfa: 4413 add r3, r2 + 800ecfc: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 800ed00: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed04: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ed08: 681b ldr r3, [r3, #0] + 800ed0a: 781b ldrb r3, [r3, #0] + 800ed0c: 00da lsls r2, r3, #3 + 800ed0e: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 800ed12: 4413 add r3, r2 + 800ed14: f203 4302 addw r3, r3, #1026 ; 0x402 + 800ed18: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 800ed1c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ed20: b29a uxth r2, r3 + 800ed22: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 800ed26: 801a strh r2, [r3, #0] pmabuffer = ep->pmaaddr0; - 800da78: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da7c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800da80: 681b ldr r3, [r3, #0] - 800da82: 891b ldrh r3, [r3, #8] - 800da84: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 + 800ed28: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed2c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ed30: 681b ldr r3, [r3, #0] + 800ed32: 891b ldrh r3, [r3, #8] + 800ed34: f8a7 3076 strh.w r3, [r7, #118] ; 0x76 /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - 800da88: f507 7384 add.w r3, r7, #264 ; 0x108 - 800da8c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800da90: 681b ldr r3, [r3, #0] - 800da92: 6959 ldr r1, [r3, #20] - 800da94: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800da98: b29b uxth r3, r3 - 800da9a: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 - 800da9e: f507 7084 add.w r0, r7, #264 ; 0x108 - 800daa2: f5a0 7082 sub.w r0, r0, #260 ; 0x104 - 800daa6: 6800 ldr r0, [r0, #0] - 800daa8: f000 fe75 bl 800e796 + 800ed38: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed3c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ed40: 681b ldr r3, [r3, #0] + 800ed42: 6959 ldr r1, [r3, #20] + 800ed44: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ed48: b29b uxth r3, r3 + 800ed4a: f8b7 2076 ldrh.w r2, [r7, #118] ; 0x76 + 800ed4e: f507 7084 add.w r0, r7, #264 ; 0x108 + 800ed52: f5a0 7082 sub.w r0, r0, #260 ; 0x104 + 800ed56: 6800 ldr r0, [r0, #0] + 800ed58: f000 fe75 bl 800fa46 } } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - 800daac: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dab0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800dab4: 681a ldr r2, [r3, #0] - 800dab6: f507 7384 add.w r3, r7, #264 ; 0x108 - 800daba: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dabe: 681b ldr r3, [r3, #0] - 800dac0: 781b ldrb r3, [r3, #0] - 800dac2: 009b lsls r3, r3, #2 - 800dac4: 4413 add r3, r2 - 800dac6: 881b ldrh r3, [r3, #0] - 800dac8: b29b uxth r3, r3 - 800daca: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800dace: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800dad2: 817b strh r3, [r7, #10] - 800dad4: 897b ldrh r3, [r7, #10] - 800dad6: f083 0310 eor.w r3, r3, #16 - 800dada: 817b strh r3, [r7, #10] - 800dadc: 897b ldrh r3, [r7, #10] - 800dade: f083 0320 eor.w r3, r3, #32 - 800dae2: 817b strh r3, [r7, #10] - 800dae4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dae8: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800daec: 681a ldr r2, [r3, #0] - 800daee: f507 7384 add.w r3, r7, #264 ; 0x108 - 800daf2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800daf6: 681b ldr r3, [r3, #0] - 800daf8: 781b ldrb r3, [r3, #0] - 800dafa: 009b lsls r3, r3, #2 - 800dafc: 441a add r2, r3 - 800dafe: 897b ldrh r3, [r7, #10] - 800db00: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800db04: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800db08: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800db0c: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800db10: b29b uxth r3, r3 - 800db12: 8013 strh r3, [r2, #0] - 800db14: f000 bcde b.w 800e4d4 + 800ed5c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed60: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ed64: 681a ldr r2, [r3, #0] + 800ed66: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed6a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ed6e: 681b ldr r3, [r3, #0] + 800ed70: 781b ldrb r3, [r3, #0] + 800ed72: 009b lsls r3, r3, #2 + 800ed74: 4413 add r3, r2 + 800ed76: 881b ldrh r3, [r3, #0] + 800ed78: b29b uxth r3, r3 + 800ed7a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800ed7e: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800ed82: 817b strh r3, [r7, #10] + 800ed84: 897b ldrh r3, [r7, #10] + 800ed86: f083 0310 eor.w r3, r3, #16 + 800ed8a: 817b strh r3, [r7, #10] + 800ed8c: 897b ldrh r3, [r7, #10] + 800ed8e: f083 0320 eor.w r3, r3, #32 + 800ed92: 817b strh r3, [r7, #10] + 800ed94: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ed98: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ed9c: 681a ldr r2, [r3, #0] + 800ed9e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eda2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eda6: 681b ldr r3, [r3, #0] + 800eda8: 781b ldrb r3, [r3, #0] + 800edaa: 009b lsls r3, r3, #2 + 800edac: 441a add r2, r3 + 800edae: 897b ldrh r3, [r7, #10] + 800edb0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800edb4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800edb8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800edbc: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800edc0: b29b uxth r3, r3 + 800edc2: 8013 strh r3, [r2, #0] + 800edc4: f000 bcde b.w 800f784 } else /* OUT endpoint */ { if (ep->doublebuffer == 0U) - 800db18: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db1c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db20: 681b ldr r3, [r3, #0] - 800db22: 7b1b ldrb r3, [r3, #12] - 800db24: 2b00 cmp r3, #0 - 800db26: f040 80bb bne.w 800dca0 + 800edc8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800edcc: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800edd0: 681b ldr r3, [r3, #0] + 800edd2: 7b1b ldrb r3, [r3, #12] + 800edd4: 2b00 cmp r3, #0 + 800edd6: f040 80bb bne.w 800ef50 { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) - 800db2a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db2e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db32: 681b ldr r3, [r3, #0] - 800db34: 699a ldr r2, [r3, #24] - 800db36: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db3a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db3e: 681b ldr r3, [r3, #0] - 800db40: 691b ldr r3, [r3, #16] - 800db42: 429a cmp r2, r3 - 800db44: d917 bls.n 800db76 + 800edda: f507 7384 add.w r3, r7, #264 ; 0x108 + 800edde: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ede2: 681b ldr r3, [r3, #0] + 800ede4: 699a ldr r2, [r3, #24] + 800ede6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800edea: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800edee: 681b ldr r3, [r3, #0] + 800edf0: 691b ldr r3, [r3, #16] + 800edf2: 429a cmp r2, r3 + 800edf4: d917 bls.n 800ee26 { len = ep->maxpacket; - 800db46: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db4a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db4e: 681b ldr r3, [r3, #0] - 800db50: 691b ldr r3, [r3, #16] - 800db52: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800edf6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800edfa: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800edfe: 681b ldr r3, [r3, #0] + 800ee00: 691b ldr r3, [r3, #16] + 800ee02: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len -= len; - 800db56: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db5a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db5e: 681b ldr r3, [r3, #0] - 800db60: 699a ldr r2, [r3, #24] - 800db62: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800db66: 1ad2 subs r2, r2, r3 - 800db68: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db6c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db70: 681b ldr r3, [r3, #0] - 800db72: 619a str r2, [r3, #24] - 800db74: e00e b.n 800db94 + 800ee06: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee0a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ee0e: 681b ldr r3, [r3, #0] + 800ee10: 699a ldr r2, [r3, #24] + 800ee12: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ee16: 1ad2 subs r2, r2, r3 + 800ee18: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee1c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ee20: 681b ldr r3, [r3, #0] + 800ee22: 619a str r2, [r3, #24] + 800ee24: e00e b.n 800ee44 } else { len = ep->xfer_len; - 800db76: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db7a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db7e: 681b ldr r3, [r3, #0] - 800db80: 699b ldr r3, [r3, #24] - 800db82: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800ee26: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee2a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ee2e: 681b ldr r3, [r3, #0] + 800ee30: 699b ldr r3, [r3, #24] + 800ee32: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len = 0U; - 800db86: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db8a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800db8e: 681b ldr r3, [r3, #0] - 800db90: 2200 movs r2, #0 - 800db92: 619a str r2, [r3, #24] + 800ee36: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee3a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ee3e: 681b ldr r3, [r3, #0] + 800ee40: 2200 movs r2, #0 + 800ee42: 619a str r2, [r3, #24] } /* configure and validate Rx endpoint */ PCD_SET_EP_RX_CNT(USBx, ep->num, len); - 800db94: f507 7384 add.w r3, r7, #264 ; 0x108 - 800db98: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800db9c: 681b ldr r3, [r3, #0] - 800db9e: f8c7 3090 str.w r3, [r7, #144] ; 0x90 - 800dba2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dba6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800dbaa: 681b ldr r3, [r3, #0] - 800dbac: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800dbb0: b29b uxth r3, r3 - 800dbb2: 461a mov r2, r3 - 800dbb4: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 - 800dbb8: 4413 add r3, r2 - 800dbba: f8c7 3090 str.w r3, [r7, #144] ; 0x90 - 800dbbe: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dbc2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dbc6: 681b ldr r3, [r3, #0] - 800dbc8: 781b ldrb r3, [r3, #0] - 800dbca: 00da lsls r2, r3, #3 - 800dbcc: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 - 800dbd0: 4413 add r3, r2 - 800dbd2: f203 4306 addw r3, r3, #1030 ; 0x406 - 800dbd6: f8c7 308c str.w r3, [r7, #140] ; 0x8c - 800dbda: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dbde: 881b ldrh r3, [r3, #0] - 800dbe0: b29b uxth r3, r3 - 800dbe2: f3c3 0309 ubfx r3, r3, #0, #10 - 800dbe6: b29a uxth r2, r3 - 800dbe8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dbec: 801a strh r2, [r3, #0] - 800dbee: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dbf2: 2b3e cmp r3, #62 ; 0x3e - 800dbf4: d924 bls.n 800dc40 - 800dbf6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dbfa: 095b lsrs r3, r3, #5 - 800dbfc: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 - 800dc00: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dc04: f003 031f and.w r3, r3, #31 - 800dc08: 2b00 cmp r3, #0 - 800dc0a: d104 bne.n 800dc16 - 800dc0c: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 - 800dc10: 3b01 subs r3, #1 - 800dc12: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 - 800dc16: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc1a: 881b ldrh r3, [r3, #0] - 800dc1c: b29a uxth r2, r3 - 800dc1e: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 - 800dc22: b29b uxth r3, r3 - 800dc24: 029b lsls r3, r3, #10 - 800dc26: b29b uxth r3, r3 - 800dc28: 4313 orrs r3, r2 - 800dc2a: b29b uxth r3, r3 - 800dc2c: ea6f 4343 mvn.w r3, r3, lsl #17 - 800dc30: ea6f 4353 mvn.w r3, r3, lsr #17 - 800dc34: b29a uxth r2, r3 - 800dc36: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc3a: 801a strh r2, [r3, #0] - 800dc3c: f000 bc10 b.w 800e460 - 800dc40: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dc44: 2b00 cmp r3, #0 - 800dc46: d10c bne.n 800dc62 - 800dc48: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc4c: 881b ldrh r3, [r3, #0] - 800dc4e: b29b uxth r3, r3 - 800dc50: ea6f 4343 mvn.w r3, r3, lsl #17 - 800dc54: ea6f 4353 mvn.w r3, r3, lsr #17 - 800dc58: b29a uxth r2, r3 - 800dc5a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc5e: 801a strh r2, [r3, #0] - 800dc60: e3fe b.n 800e460 - 800dc62: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dc66: 085b lsrs r3, r3, #1 - 800dc68: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 - 800dc6c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800dc70: f003 0301 and.w r3, r3, #1 - 800dc74: 2b00 cmp r3, #0 - 800dc76: d004 beq.n 800dc82 - 800dc78: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 - 800dc7c: 3301 adds r3, #1 - 800dc7e: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 - 800dc82: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc86: 881b ldrh r3, [r3, #0] - 800dc88: b29a uxth r2, r3 - 800dc8a: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 - 800dc8e: b29b uxth r3, r3 - 800dc90: 029b lsls r3, r3, #10 - 800dc92: b29b uxth r3, r3 - 800dc94: 4313 orrs r3, r2 - 800dc96: b29a uxth r2, r3 - 800dc98: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c - 800dc9c: 801a strh r2, [r3, #0] - 800dc9e: e3df b.n 800e460 + 800ee44: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee48: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ee4c: 681b ldr r3, [r3, #0] + 800ee4e: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 800ee52: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee56: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ee5a: 681b ldr r3, [r3, #0] + 800ee5c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800ee60: b29b uxth r3, r3 + 800ee62: 461a mov r2, r3 + 800ee64: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 800ee68: 4413 add r3, r2 + 800ee6a: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 800ee6e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ee72: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ee76: 681b ldr r3, [r3, #0] + 800ee78: 781b ldrb r3, [r3, #0] + 800ee7a: 00da lsls r2, r3, #3 + 800ee7c: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 800ee80: 4413 add r3, r2 + 800ee82: f203 4306 addw r3, r3, #1030 ; 0x406 + 800ee86: f8c7 308c str.w r3, [r7, #140] ; 0x8c + 800ee8a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800ee8e: 881b ldrh r3, [r3, #0] + 800ee90: b29b uxth r3, r3 + 800ee92: f3c3 0309 ubfx r3, r3, #0, #10 + 800ee96: b29a uxth r2, r3 + 800ee98: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800ee9c: 801a strh r2, [r3, #0] + 800ee9e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eea2: 2b3e cmp r3, #62 ; 0x3e + 800eea4: d924 bls.n 800eef0 + 800eea6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eeaa: 095b lsrs r3, r3, #5 + 800eeac: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 + 800eeb0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eeb4: f003 031f and.w r3, r3, #31 + 800eeb8: 2b00 cmp r3, #0 + 800eeba: d104 bne.n 800eec6 + 800eebc: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 + 800eec0: 3b01 subs r3, #1 + 800eec2: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 + 800eec6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800eeca: 881b ldrh r3, [r3, #0] + 800eecc: b29a uxth r2, r3 + 800eece: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 + 800eed2: b29b uxth r3, r3 + 800eed4: 029b lsls r3, r3, #10 + 800eed6: b29b uxth r3, r3 + 800eed8: 4313 orrs r3, r2 + 800eeda: b29b uxth r3, r3 + 800eedc: ea6f 4343 mvn.w r3, r3, lsl #17 + 800eee0: ea6f 4353 mvn.w r3, r3, lsr #17 + 800eee4: b29a uxth r2, r3 + 800eee6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800eeea: 801a strh r2, [r3, #0] + 800eeec: f000 bc10 b.w 800f710 + 800eef0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800eef4: 2b00 cmp r3, #0 + 800eef6: d10c bne.n 800ef12 + 800eef8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800eefc: 881b ldrh r3, [r3, #0] + 800eefe: b29b uxth r3, r3 + 800ef00: ea6f 4343 mvn.w r3, r3, lsl #17 + 800ef04: ea6f 4353 mvn.w r3, r3, lsr #17 + 800ef08: b29a uxth r2, r3 + 800ef0a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800ef0e: 801a strh r2, [r3, #0] + 800ef10: e3fe b.n 800f710 + 800ef12: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ef16: 085b lsrs r3, r3, #1 + 800ef18: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 + 800ef1c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800ef20: f003 0301 and.w r3, r3, #1 + 800ef24: 2b00 cmp r3, #0 + 800ef26: d004 beq.n 800ef32 + 800ef28: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 + 800ef2c: 3301 adds r3, #1 + 800ef2e: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 + 800ef32: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800ef36: 881b ldrh r3, [r3, #0] + 800ef38: b29a uxth r2, r3 + 800ef3a: f8d7 30e8 ldr.w r3, [r7, #232] ; 0xe8 + 800ef3e: b29b uxth r3, r3 + 800ef40: 029b lsls r3, r3, #10 + 800ef42: b29b uxth r3, r3 + 800ef44: 4313 orrs r3, r2 + 800ef46: b29a uxth r2, r3 + 800ef48: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800ef4c: 801a strh r2, [r3, #0] + 800ef4e: e3df b.n 800f710 #if (USE_USB_DOUBLE_BUFFER == 1U) else { /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) - 800dca0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dca4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dca8: 681b ldr r3, [r3, #0] - 800dcaa: 78db ldrb r3, [r3, #3] - 800dcac: 2b02 cmp r3, #2 - 800dcae: f040 8218 bne.w 800e0e2 + 800ef50: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ef54: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ef58: 681b ldr r3, [r3, #0] + 800ef5a: 78db ldrb r3, [r3, #3] + 800ef5c: 2b02 cmp r3, #2 + 800ef5e: f040 8218 bne.w 800f392 { PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - 800dcb2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dcb6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dcba: 681b ldr r3, [r3, #0] - 800dcbc: 785b ldrb r3, [r3, #1] - 800dcbe: 2b00 cmp r3, #0 - 800dcc0: f040 809d bne.w 800ddfe - 800dcc4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dcc8: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800dccc: 681b ldr r3, [r3, #0] - 800dcce: f8c7 30ac str.w r3, [r7, #172] ; 0xac - 800dcd2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dcd6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800dcda: 681b ldr r3, [r3, #0] - 800dcdc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800dce0: b29b uxth r3, r3 - 800dce2: 461a mov r2, r3 - 800dce4: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800dce8: 4413 add r3, r2 - 800dcea: f8c7 30ac str.w r3, [r7, #172] ; 0xac - 800dcee: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dcf2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dcf6: 681b ldr r3, [r3, #0] - 800dcf8: 781b ldrb r3, [r3, #0] - 800dcfa: 00da lsls r2, r3, #3 - 800dcfc: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac - 800dd00: 4413 add r3, r2 - 800dd02: f203 4302 addw r3, r3, #1026 ; 0x402 - 800dd06: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 - 800dd0a: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dd0e: 881b ldrh r3, [r3, #0] - 800dd10: b29b uxth r3, r3 - 800dd12: f3c3 0309 ubfx r3, r3, #0, #10 - 800dd16: b29a uxth r2, r3 - 800dd18: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dd1c: 801a strh r2, [r3, #0] - 800dd1e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dd22: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dd26: 681b ldr r3, [r3, #0] - 800dd28: 691b ldr r3, [r3, #16] - 800dd2a: 2b3e cmp r3, #62 ; 0x3e - 800dd2c: d92b bls.n 800dd86 - 800dd2e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dd32: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dd36: 681b ldr r3, [r3, #0] - 800dd38: 691b ldr r3, [r3, #16] - 800dd3a: 095b lsrs r3, r3, #5 - 800dd3c: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 - 800dd40: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dd44: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dd48: 681b ldr r3, [r3, #0] - 800dd4a: 691b ldr r3, [r3, #16] - 800dd4c: f003 031f and.w r3, r3, #31 - 800dd50: 2b00 cmp r3, #0 - 800dd52: d104 bne.n 800dd5e - 800dd54: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800dd58: 3b01 subs r3, #1 - 800dd5a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 - 800dd5e: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dd62: 881b ldrh r3, [r3, #0] - 800dd64: b29a uxth r2, r3 - 800dd66: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800dd6a: b29b uxth r3, r3 - 800dd6c: 029b lsls r3, r3, #10 - 800dd6e: b29b uxth r3, r3 - 800dd70: 4313 orrs r3, r2 - 800dd72: b29b uxth r3, r3 - 800dd74: ea6f 4343 mvn.w r3, r3, lsl #17 - 800dd78: ea6f 4353 mvn.w r3, r3, lsr #17 - 800dd7c: b29a uxth r2, r3 - 800dd7e: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dd82: 801a strh r2, [r3, #0] - 800dd84: e070 b.n 800de68 - 800dd86: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dd8a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dd8e: 681b ldr r3, [r3, #0] - 800dd90: 691b ldr r3, [r3, #16] - 800dd92: 2b00 cmp r3, #0 - 800dd94: d10c bne.n 800ddb0 - 800dd96: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dd9a: 881b ldrh r3, [r3, #0] - 800dd9c: b29b uxth r3, r3 - 800dd9e: ea6f 4343 mvn.w r3, r3, lsl #17 - 800dda2: ea6f 4353 mvn.w r3, r3, lsr #17 - 800dda6: b29a uxth r2, r3 - 800dda8: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800ddac: 801a strh r2, [r3, #0] - 800ddae: e05b b.n 800de68 - 800ddb0: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ddb4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ddb8: 681b ldr r3, [r3, #0] - 800ddba: 691b ldr r3, [r3, #16] - 800ddbc: 085b lsrs r3, r3, #1 - 800ddbe: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 - 800ddc2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800ddc6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800ddca: 681b ldr r3, [r3, #0] - 800ddcc: 691b ldr r3, [r3, #16] - 800ddce: f003 0301 and.w r3, r3, #1 - 800ddd2: 2b00 cmp r3, #0 - 800ddd4: d004 beq.n 800dde0 - 800ddd6: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ddda: 3301 adds r3, #1 - 800dddc: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 - 800dde0: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800dde4: 881b ldrh r3, [r3, #0] - 800dde6: b29a uxth r2, r3 - 800dde8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 - 800ddec: b29b uxth r3, r3 - 800ddee: 029b lsls r3, r3, #10 - 800ddf0: b29b uxth r3, r3 - 800ddf2: 4313 orrs r3, r2 - 800ddf4: b29a uxth r2, r3 - 800ddf6: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 - 800ddfa: 801a strh r2, [r3, #0] - 800ddfc: e034 b.n 800de68 - 800ddfe: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de02: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800de06: 681b ldr r3, [r3, #0] - 800de08: 785b ldrb r3, [r3, #1] - 800de0a: 2b01 cmp r3, #1 - 800de0c: d12c bne.n 800de68 - 800de0e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de12: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800de16: 681b ldr r3, [r3, #0] - 800de18: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - 800de1c: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de20: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800de24: 681b ldr r3, [r3, #0] - 800de26: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800de2a: b29b uxth r3, r3 - 800de2c: 461a mov r2, r3 - 800de2e: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 - 800de32: 4413 add r3, r2 - 800de34: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - 800de38: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de3c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800de40: 681b ldr r3, [r3, #0] - 800de42: 781b ldrb r3, [r3, #0] - 800de44: 00da lsls r2, r3, #3 - 800de46: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 - 800de4a: 4413 add r3, r2 - 800de4c: f203 4302 addw r3, r3, #1026 ; 0x402 - 800de50: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 - 800de54: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de58: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800de5c: 681b ldr r3, [r3, #0] - 800de5e: 691b ldr r3, [r3, #16] - 800de60: b29a uxth r2, r3 - 800de62: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 - 800de66: 801a strh r2, [r3, #0] - 800de68: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de6c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800de70: 681b ldr r3, [r3, #0] - 800de72: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 - 800de76: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de7a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800de7e: 681b ldr r3, [r3, #0] - 800de80: 785b ldrb r3, [r3, #1] - 800de82: 2b00 cmp r3, #0 - 800de84: f040 809d bne.w 800dfc2 - 800de88: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de8c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800de90: 681b ldr r3, [r3, #0] - 800de92: f8c7 309c str.w r3, [r7, #156] ; 0x9c - 800de96: f507 7384 add.w r3, r7, #264 ; 0x108 - 800de9a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800de9e: 681b ldr r3, [r3, #0] - 800dea0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800dea4: b29b uxth r3, r3 - 800dea6: 461a mov r2, r3 - 800dea8: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c - 800deac: 4413 add r3, r2 - 800deae: f8c7 309c str.w r3, [r7, #156] ; 0x9c - 800deb2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800deb6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800deba: 681b ldr r3, [r3, #0] - 800debc: 781b ldrb r3, [r3, #0] - 800debe: 00da lsls r2, r3, #3 - 800dec0: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c - 800dec4: 4413 add r3, r2 - 800dec6: f203 4306 addw r3, r3, #1030 ; 0x406 - 800deca: f8c7 3098 str.w r3, [r7, #152] ; 0x98 - 800dece: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800ded2: 881b ldrh r3, [r3, #0] - 800ded4: b29b uxth r3, r3 - 800ded6: f3c3 0309 ubfx r3, r3, #0, #10 - 800deda: b29a uxth r2, r3 - 800dedc: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800dee0: 801a strh r2, [r3, #0] - 800dee2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dee6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800deea: 681b ldr r3, [r3, #0] - 800deec: 691b ldr r3, [r3, #16] - 800deee: 2b3e cmp r3, #62 ; 0x3e - 800def0: d92b bls.n 800df4a - 800def2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800def6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800defa: 681b ldr r3, [r3, #0] - 800defc: 691b ldr r3, [r3, #16] - 800defe: 095b lsrs r3, r3, #5 - 800df00: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 - 800df04: f507 7384 add.w r3, r7, #264 ; 0x108 - 800df08: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800df0c: 681b ldr r3, [r3, #0] - 800df0e: 691b ldr r3, [r3, #16] - 800df10: f003 031f and.w r3, r3, #31 - 800df14: 2b00 cmp r3, #0 - 800df16: d104 bne.n 800df22 - 800df18: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800df1c: 3b01 subs r3, #1 - 800df1e: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 - 800df22: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800df26: 881b ldrh r3, [r3, #0] - 800df28: b29a uxth r2, r3 - 800df2a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800df2e: b29b uxth r3, r3 - 800df30: 029b lsls r3, r3, #10 - 800df32: b29b uxth r3, r3 - 800df34: 4313 orrs r3, r2 - 800df36: b29b uxth r3, r3 - 800df38: ea6f 4343 mvn.w r3, r3, lsl #17 - 800df3c: ea6f 4353 mvn.w r3, r3, lsr #17 - 800df40: b29a uxth r2, r3 - 800df42: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800df46: 801a strh r2, [r3, #0] - 800df48: e069 b.n 800e01e - 800df4a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800df4e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800df52: 681b ldr r3, [r3, #0] - 800df54: 691b ldr r3, [r3, #16] - 800df56: 2b00 cmp r3, #0 - 800df58: d10c bne.n 800df74 - 800df5a: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800df5e: 881b ldrh r3, [r3, #0] - 800df60: b29b uxth r3, r3 - 800df62: ea6f 4343 mvn.w r3, r3, lsl #17 - 800df66: ea6f 4353 mvn.w r3, r3, lsr #17 - 800df6a: b29a uxth r2, r3 - 800df6c: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800df70: 801a strh r2, [r3, #0] - 800df72: e054 b.n 800e01e - 800df74: f507 7384 add.w r3, r7, #264 ; 0x108 - 800df78: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800df7c: 681b ldr r3, [r3, #0] - 800df7e: 691b ldr r3, [r3, #16] - 800df80: 085b lsrs r3, r3, #1 - 800df82: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 - 800df86: f507 7384 add.w r3, r7, #264 ; 0x108 - 800df8a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800df8e: 681b ldr r3, [r3, #0] - 800df90: 691b ldr r3, [r3, #16] - 800df92: f003 0301 and.w r3, r3, #1 - 800df96: 2b00 cmp r3, #0 - 800df98: d004 beq.n 800dfa4 - 800df9a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800df9e: 3301 adds r3, #1 - 800dfa0: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 - 800dfa4: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800dfa8: 881b ldrh r3, [r3, #0] - 800dfaa: b29a uxth r2, r3 - 800dfac: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 - 800dfb0: b29b uxth r3, r3 - 800dfb2: 029b lsls r3, r3, #10 - 800dfb4: b29b uxth r3, r3 - 800dfb6: 4313 orrs r3, r2 - 800dfb8: b29a uxth r2, r3 - 800dfba: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 - 800dfbe: 801a strh r2, [r3, #0] - 800dfc0: e02d b.n 800e01e - 800dfc2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dfc6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dfca: 681b ldr r3, [r3, #0] - 800dfcc: 785b ldrb r3, [r3, #1] - 800dfce: 2b01 cmp r3, #1 - 800dfd0: d125 bne.n 800e01e - 800dfd2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dfd6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800dfda: 681b ldr r3, [r3, #0] - 800dfdc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800dfe0: b29b uxth r3, r3 - 800dfe2: 461a mov r2, r3 - 800dfe4: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 - 800dfe8: 4413 add r3, r2 - 800dfea: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 - 800dfee: f507 7384 add.w r3, r7, #264 ; 0x108 - 800dff2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800dff6: 681b ldr r3, [r3, #0] - 800dff8: 781b ldrb r3, [r3, #0] - 800dffa: 00da lsls r2, r3, #3 - 800dffc: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 - 800e000: 4413 add r3, r2 - 800e002: f203 4306 addw r3, r3, #1030 ; 0x406 - 800e006: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 - 800e00a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e00e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e012: 681b ldr r3, [r3, #0] - 800e014: 691b ldr r3, [r3, #16] - 800e016: b29a uxth r2, r3 - 800e018: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 - 800e01c: 801a strh r2, [r3, #0] + 800ef62: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ef66: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800ef6a: 681b ldr r3, [r3, #0] + 800ef6c: 785b ldrb r3, [r3, #1] + 800ef6e: 2b00 cmp r3, #0 + 800ef70: f040 809d bne.w 800f0ae + 800ef74: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ef78: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ef7c: 681b ldr r3, [r3, #0] + 800ef7e: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 800ef82: f507 7384 add.w r3, r7, #264 ; 0x108 + 800ef86: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800ef8a: 681b ldr r3, [r3, #0] + 800ef8c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800ef90: b29b uxth r3, r3 + 800ef92: 461a mov r2, r3 + 800ef94: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800ef98: 4413 add r3, r2 + 800ef9a: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 800ef9e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800efa2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800efa6: 681b ldr r3, [r3, #0] + 800efa8: 781b ldrb r3, [r3, #0] + 800efaa: 00da lsls r2, r3, #3 + 800efac: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800efb0: 4413 add r3, r2 + 800efb2: f203 4302 addw r3, r3, #1026 ; 0x402 + 800efb6: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + 800efba: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800efbe: 881b ldrh r3, [r3, #0] + 800efc0: b29b uxth r3, r3 + 800efc2: f3c3 0309 ubfx r3, r3, #0, #10 + 800efc6: b29a uxth r2, r3 + 800efc8: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800efcc: 801a strh r2, [r3, #0] + 800efce: f507 7384 add.w r3, r7, #264 ; 0x108 + 800efd2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800efd6: 681b ldr r3, [r3, #0] + 800efd8: 691b ldr r3, [r3, #16] + 800efda: 2b3e cmp r3, #62 ; 0x3e + 800efdc: d92b bls.n 800f036 + 800efde: f507 7384 add.w r3, r7, #264 ; 0x108 + 800efe2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800efe6: 681b ldr r3, [r3, #0] + 800efe8: 691b ldr r3, [r3, #16] + 800efea: 095b lsrs r3, r3, #5 + 800efec: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800eff0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800eff4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800eff8: 681b ldr r3, [r3, #0] + 800effa: 691b ldr r3, [r3, #16] + 800effc: f003 031f and.w r3, r3, #31 + 800f000: 2b00 cmp r3, #0 + 800f002: d104 bne.n 800f00e + 800f004: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800f008: 3b01 subs r3, #1 + 800f00a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800f00e: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f012: 881b ldrh r3, [r3, #0] + 800f014: b29a uxth r2, r3 + 800f016: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800f01a: b29b uxth r3, r3 + 800f01c: 029b lsls r3, r3, #10 + 800f01e: b29b uxth r3, r3 + 800f020: 4313 orrs r3, r2 + 800f022: b29b uxth r3, r3 + 800f024: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f028: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f02c: b29a uxth r2, r3 + 800f02e: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f032: 801a strh r2, [r3, #0] + 800f034: e070 b.n 800f118 + 800f036: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f03a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f03e: 681b ldr r3, [r3, #0] + 800f040: 691b ldr r3, [r3, #16] + 800f042: 2b00 cmp r3, #0 + 800f044: d10c bne.n 800f060 + 800f046: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f04a: 881b ldrh r3, [r3, #0] + 800f04c: b29b uxth r3, r3 + 800f04e: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f052: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f056: b29a uxth r2, r3 + 800f058: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f05c: 801a strh r2, [r3, #0] + 800f05e: e05b b.n 800f118 + 800f060: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f064: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f068: 681b ldr r3, [r3, #0] + 800f06a: 691b ldr r3, [r3, #16] + 800f06c: 085b lsrs r3, r3, #1 + 800f06e: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800f072: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f076: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f07a: 681b ldr r3, [r3, #0] + 800f07c: 691b ldr r3, [r3, #16] + 800f07e: f003 0301 and.w r3, r3, #1 + 800f082: 2b00 cmp r3, #0 + 800f084: d004 beq.n 800f090 + 800f086: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800f08a: 3301 adds r3, #1 + 800f08c: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800f090: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f094: 881b ldrh r3, [r3, #0] + 800f096: b29a uxth r2, r3 + 800f098: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800f09c: b29b uxth r3, r3 + 800f09e: 029b lsls r3, r3, #10 + 800f0a0: b29b uxth r3, r3 + 800f0a2: 4313 orrs r3, r2 + 800f0a4: b29a uxth r2, r3 + 800f0a6: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 800f0aa: 801a strh r2, [r3, #0] + 800f0ac: e034 b.n 800f118 + 800f0ae: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f0b2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f0b6: 681b ldr r3, [r3, #0] + 800f0b8: 785b ldrb r3, [r3, #1] + 800f0ba: 2b01 cmp r3, #1 + 800f0bc: d12c bne.n 800f118 + 800f0be: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f0c2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f0c6: 681b ldr r3, [r3, #0] + 800f0c8: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 800f0cc: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f0d0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f0d4: 681b ldr r3, [r3, #0] + 800f0d6: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f0da: b29b uxth r3, r3 + 800f0dc: 461a mov r2, r3 + 800f0de: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 800f0e2: 4413 add r3, r2 + 800f0e4: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 800f0e8: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f0ec: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f0f0: 681b ldr r3, [r3, #0] + 800f0f2: 781b ldrb r3, [r3, #0] + 800f0f4: 00da lsls r2, r3, #3 + 800f0f6: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 800f0fa: 4413 add r3, r2 + 800f0fc: f203 4302 addw r3, r3, #1026 ; 0x402 + 800f100: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + 800f104: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f108: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f10c: 681b ldr r3, [r3, #0] + 800f10e: 691b ldr r3, [r3, #16] + 800f110: b29a uxth r2, r3 + 800f112: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0 + 800f116: 801a strh r2, [r3, #0] + 800f118: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f11c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f120: 681b ldr r3, [r3, #0] + 800f122: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 800f126: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f12a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f12e: 681b ldr r3, [r3, #0] + 800f130: 785b ldrb r3, [r3, #1] + 800f132: 2b00 cmp r3, #0 + 800f134: f040 809d bne.w 800f272 + 800f138: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f13c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f140: 681b ldr r3, [r3, #0] + 800f142: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 800f146: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f14a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f14e: 681b ldr r3, [r3, #0] + 800f150: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f154: b29b uxth r3, r3 + 800f156: 461a mov r2, r3 + 800f158: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 800f15c: 4413 add r3, r2 + 800f15e: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 800f162: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f166: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f16a: 681b ldr r3, [r3, #0] + 800f16c: 781b ldrb r3, [r3, #0] + 800f16e: 00da lsls r2, r3, #3 + 800f170: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 800f174: 4413 add r3, r2 + 800f176: f203 4306 addw r3, r3, #1030 ; 0x406 + 800f17a: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 800f17e: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f182: 881b ldrh r3, [r3, #0] + 800f184: b29b uxth r3, r3 + 800f186: f3c3 0309 ubfx r3, r3, #0, #10 + 800f18a: b29a uxth r2, r3 + 800f18c: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f190: 801a strh r2, [r3, #0] + 800f192: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f196: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f19a: 681b ldr r3, [r3, #0] + 800f19c: 691b ldr r3, [r3, #16] + 800f19e: 2b3e cmp r3, #62 ; 0x3e + 800f1a0: d92b bls.n 800f1fa + 800f1a2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f1a6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f1aa: 681b ldr r3, [r3, #0] + 800f1ac: 691b ldr r3, [r3, #16] + 800f1ae: 095b lsrs r3, r3, #5 + 800f1b0: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 800f1b4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f1b8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f1bc: 681b ldr r3, [r3, #0] + 800f1be: 691b ldr r3, [r3, #16] + 800f1c0: f003 031f and.w r3, r3, #31 + 800f1c4: 2b00 cmp r3, #0 + 800f1c6: d104 bne.n 800f1d2 + 800f1c8: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800f1cc: 3b01 subs r3, #1 + 800f1ce: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 800f1d2: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f1d6: 881b ldrh r3, [r3, #0] + 800f1d8: b29a uxth r2, r3 + 800f1da: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800f1de: b29b uxth r3, r3 + 800f1e0: 029b lsls r3, r3, #10 + 800f1e2: b29b uxth r3, r3 + 800f1e4: 4313 orrs r3, r2 + 800f1e6: b29b uxth r3, r3 + 800f1e8: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f1ec: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f1f0: b29a uxth r2, r3 + 800f1f2: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f1f6: 801a strh r2, [r3, #0] + 800f1f8: e069 b.n 800f2ce + 800f1fa: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f1fe: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f202: 681b ldr r3, [r3, #0] + 800f204: 691b ldr r3, [r3, #16] + 800f206: 2b00 cmp r3, #0 + 800f208: d10c bne.n 800f224 + 800f20a: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f20e: 881b ldrh r3, [r3, #0] + 800f210: b29b uxth r3, r3 + 800f212: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f216: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f21a: b29a uxth r2, r3 + 800f21c: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f220: 801a strh r2, [r3, #0] + 800f222: e054 b.n 800f2ce + 800f224: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f228: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f22c: 681b ldr r3, [r3, #0] + 800f22e: 691b ldr r3, [r3, #16] + 800f230: 085b lsrs r3, r3, #1 + 800f232: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 800f236: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f23a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f23e: 681b ldr r3, [r3, #0] + 800f240: 691b ldr r3, [r3, #16] + 800f242: f003 0301 and.w r3, r3, #1 + 800f246: 2b00 cmp r3, #0 + 800f248: d004 beq.n 800f254 + 800f24a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800f24e: 3301 adds r3, #1 + 800f250: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 800f254: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f258: 881b ldrh r3, [r3, #0] + 800f25a: b29a uxth r2, r3 + 800f25c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800f260: b29b uxth r3, r3 + 800f262: 029b lsls r3, r3, #10 + 800f264: b29b uxth r3, r3 + 800f266: 4313 orrs r3, r2 + 800f268: b29a uxth r2, r3 + 800f26a: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800f26e: 801a strh r2, [r3, #0] + 800f270: e02d b.n 800f2ce + 800f272: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f276: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f27a: 681b ldr r3, [r3, #0] + 800f27c: 785b ldrb r3, [r3, #1] + 800f27e: 2b01 cmp r3, #1 + 800f280: d125 bne.n 800f2ce + 800f282: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f286: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f28a: 681b ldr r3, [r3, #0] + 800f28c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f290: b29b uxth r3, r3 + 800f292: 461a mov r2, r3 + 800f294: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 + 800f298: 4413 add r3, r2 + 800f29a: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 800f29e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f2a2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f2a6: 681b ldr r3, [r3, #0] + 800f2a8: 781b ldrb r3, [r3, #0] + 800f2aa: 00da lsls r2, r3, #3 + 800f2ac: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 + 800f2b0: 4413 add r3, r2 + 800f2b2: f203 4306 addw r3, r3, #1030 ; 0x406 + 800f2b6: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 800f2ba: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f2be: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f2c2: 681b ldr r3, [r3, #0] + 800f2c4: 691b ldr r3, [r3, #16] + 800f2c6: b29a uxth r2, r3 + 800f2c8: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 800f2cc: 801a strh r2, [r3, #0] /* Coming from ISR */ if (ep->xfer_count != 0U) - 800e01e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e022: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e026: 681b ldr r3, [r3, #0] - 800e028: 69db ldr r3, [r3, #28] - 800e02a: 2b00 cmp r3, #0 - 800e02c: f000 8218 beq.w 800e460 + 800f2ce: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f2d2: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f2d6: 681b ldr r3, [r3, #0] + 800f2d8: 69db ldr r3, [r3, #28] + 800f2da: 2b00 cmp r3, #0 + 800f2dc: f000 8218 beq.w 800f710 { /* update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - 800e030: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e034: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e038: 681a ldr r2, [r3, #0] - 800e03a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e03e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e042: 681b ldr r3, [r3, #0] - 800e044: 781b ldrb r3, [r3, #0] - 800e046: 009b lsls r3, r3, #2 - 800e048: 4413 add r3, r2 - 800e04a: 881b ldrh r3, [r3, #0] - 800e04c: f8a7 3096 strh.w r3, [r7, #150] ; 0x96 + 800f2e0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f2e4: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f2e8: 681a ldr r2, [r3, #0] + 800f2ea: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f2ee: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f2f2: 681b ldr r3, [r3, #0] + 800f2f4: 781b ldrb r3, [r3, #0] + 800f2f6: 009b lsls r3, r3, #2 + 800f2f8: 4413 add r3, r2 + 800f2fa: 881b ldrh r3, [r3, #0] + 800f2fc: f8a7 3096 strh.w r3, [r7, #150] ; 0x96 /*Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || - 800e050: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 - 800e054: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800e058: 2b00 cmp r3, #0 - 800e05a: d005 beq.n 800e068 - 800e05c: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 - 800e060: f003 0340 and.w r3, r3, #64 ; 0x40 - 800e064: 2b00 cmp r3, #0 - 800e066: d10d bne.n 800e084 + 800f300: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 + 800f304: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800f308: 2b00 cmp r3, #0 + 800f30a: d005 beq.n 800f318 + 800f30c: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 + 800f310: f003 0340 and.w r3, r3, #64 ; 0x40 + 800f314: 2b00 cmp r3, #0 + 800f316: d10d bne.n 800f334 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) - 800e068: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 - 800e06c: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800f318: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 + 800f31c: f403 4380 and.w r3, r3, #16384 ; 0x4000 if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || - 800e070: 2b00 cmp r3, #0 - 800e072: f040 81f5 bne.w 800e460 + 800f320: 2b00 cmp r3, #0 + 800f322: f040 81f5 bne.w 800f710 (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) - 800e076: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 - 800e07a: f003 0340 and.w r3, r3, #64 ; 0x40 - 800e07e: 2b00 cmp r3, #0 - 800e080: f040 81ee bne.w 800e460 + 800f326: f8b7 3096 ldrh.w r3, [r7, #150] ; 0x96 + 800f32a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800f32e: 2b00 cmp r3, #0 + 800f330: f040 81ee bne.w 800f710 { PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); - 800e084: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e088: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e08c: 681a ldr r2, [r3, #0] - 800e08e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e092: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e096: 681b ldr r3, [r3, #0] - 800e098: 781b ldrb r3, [r3, #0] - 800e09a: 009b lsls r3, r3, #2 - 800e09c: 4413 add r3, r2 - 800e09e: 881b ldrh r3, [r3, #0] - 800e0a0: b29b uxth r3, r3 - 800e0a2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800e0a6: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e0aa: f8a7 3094 strh.w r3, [r7, #148] ; 0x94 - 800e0ae: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e0b2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e0b6: 681a ldr r2, [r3, #0] - 800e0b8: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e0bc: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e0c0: 681b ldr r3, [r3, #0] - 800e0c2: 781b ldrb r3, [r3, #0] - 800e0c4: 009b lsls r3, r3, #2 - 800e0c6: 441a add r2, r3 - 800e0c8: f8b7 3094 ldrh.w r3, [r7, #148] ; 0x94 - 800e0cc: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e0d0: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e0d4: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e0d8: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800e0dc: b29b uxth r3, r3 - 800e0de: 8013 strh r3, [r2, #0] - 800e0e0: e1be b.n 800e460 + 800f334: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f338: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f33c: 681a ldr r2, [r3, #0] + 800f33e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f342: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f346: 681b ldr r3, [r3, #0] + 800f348: 781b ldrb r3, [r3, #0] + 800f34a: 009b lsls r3, r3, #2 + 800f34c: 4413 add r3, r2 + 800f34e: 881b ldrh r3, [r3, #0] + 800f350: b29b uxth r3, r3 + 800f352: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800f356: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f35a: f8a7 3094 strh.w r3, [r7, #148] ; 0x94 + 800f35e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f362: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f366: 681a ldr r2, [r3, #0] + 800f368: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f36c: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f370: 681b ldr r3, [r3, #0] + 800f372: 781b ldrb r3, [r3, #0] + 800f374: 009b lsls r3, r3, #2 + 800f376: 441a add r2, r3 + 800f378: f8b7 3094 ldrh.w r3, [r7, #148] ; 0x94 + 800f37c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f380: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f384: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f388: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800f38c: b29b uxth r3, r3 + 800f38e: 8013 strh r3, [r2, #0] + 800f390: e1be b.n 800f710 } } } /* iso out double */ else if (ep->type == EP_TYPE_ISOC) - 800e0e2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e0e6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e0ea: 681b ldr r3, [r3, #0] - 800e0ec: 78db ldrb r3, [r3, #3] - 800e0ee: 2b01 cmp r3, #1 - 800e0f0: f040 81b4 bne.w 800e45c + 800f392: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f396: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f39a: 681b ldr r3, [r3, #0] + 800f39c: 78db ldrb r3, [r3, #3] + 800f39e: 2b01 cmp r3, #1 + 800f3a0: f040 81b4 bne.w 800f70c { /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) - 800e0f4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e0f8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e0fc: 681b ldr r3, [r3, #0] - 800e0fe: 699a ldr r2, [r3, #24] - 800e100: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e104: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e108: 681b ldr r3, [r3, #0] - 800e10a: 691b ldr r3, [r3, #16] - 800e10c: 429a cmp r2, r3 - 800e10e: d917 bls.n 800e140 + 800f3a4: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3a8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3ac: 681b ldr r3, [r3, #0] + 800f3ae: 699a ldr r2, [r3, #24] + 800f3b0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3b4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3b8: 681b ldr r3, [r3, #0] + 800f3ba: 691b ldr r3, [r3, #16] + 800f3bc: 429a cmp r2, r3 + 800f3be: d917 bls.n 800f3f0 { len = ep->maxpacket; - 800e110: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e114: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e118: 681b ldr r3, [r3, #0] - 800e11a: 691b ldr r3, [r3, #16] - 800e11c: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800f3c0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3c4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3c8: 681b ldr r3, [r3, #0] + 800f3ca: 691b ldr r3, [r3, #16] + 800f3cc: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len -= len; - 800e120: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e124: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e128: 681b ldr r3, [r3, #0] - 800e12a: 699a ldr r2, [r3, #24] - 800e12c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e130: 1ad2 subs r2, r2, r3 - 800e132: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e136: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e13a: 681b ldr r3, [r3, #0] - 800e13c: 619a str r2, [r3, #24] - 800e13e: e00e b.n 800e15e + 800f3d0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3d4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3d8: 681b ldr r3, [r3, #0] + 800f3da: 699a ldr r2, [r3, #24] + 800f3dc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f3e0: 1ad2 subs r2, r2, r3 + 800f3e2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3e6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3ea: 681b ldr r3, [r3, #0] + 800f3ec: 619a str r2, [r3, #24] + 800f3ee: e00e b.n 800f40e } else { len = ep->xfer_len; - 800e140: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e144: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e148: 681b ldr r3, [r3, #0] - 800e14a: 699b ldr r3, [r3, #24] - 800e14c: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 800f3f0: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f3f4: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f3f8: 681b ldr r3, [r3, #0] + 800f3fa: 699b ldr r3, [r3, #24] + 800f3fc: f8c7 3104 str.w r3, [r7, #260] ; 0x104 ep->xfer_len = 0U; - 800e150: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e154: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e158: 681b ldr r3, [r3, #0] - 800e15a: 2200 movs r2, #0 - 800e15c: 619a str r2, [r3, #24] + 800f400: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f404: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f408: 681b ldr r3, [r3, #0] + 800f40a: 2200 movs r2, #0 + 800f40c: 619a str r2, [r3, #24] } PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); - 800e15e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e162: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e166: 681b ldr r3, [r3, #0] - 800e168: 785b ldrb r3, [r3, #1] - 800e16a: 2b00 cmp r3, #0 - 800e16c: f040 8085 bne.w 800e27a - 800e170: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e174: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e178: 681b ldr r3, [r3, #0] - 800e17a: f8c7 30cc str.w r3, [r7, #204] ; 0xcc - 800e17e: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e182: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e186: 681b ldr r3, [r3, #0] - 800e188: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800e18c: b29b uxth r3, r3 - 800e18e: 461a mov r2, r3 - 800e190: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 800e194: 4413 add r3, r2 - 800e196: f8c7 30cc str.w r3, [r7, #204] ; 0xcc - 800e19a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e19e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e1a2: 681b ldr r3, [r3, #0] - 800e1a4: 781b ldrb r3, [r3, #0] - 800e1a6: 00da lsls r2, r3, #3 - 800e1a8: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc - 800e1ac: 4413 add r3, r2 - 800e1ae: f203 4302 addw r3, r3, #1026 ; 0x402 - 800e1b2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 - 800e1b6: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e1ba: 881b ldrh r3, [r3, #0] - 800e1bc: b29b uxth r3, r3 - 800e1be: f3c3 0309 ubfx r3, r3, #0, #10 - 800e1c2: b29a uxth r2, r3 - 800e1c4: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e1c8: 801a strh r2, [r3, #0] - 800e1ca: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e1ce: 2b3e cmp r3, #62 ; 0x3e - 800e1d0: d923 bls.n 800e21a - 800e1d2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e1d6: 095b lsrs r3, r3, #5 - 800e1d8: f8c7 30dc str.w r3, [r7, #220] ; 0xdc - 800e1dc: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e1e0: f003 031f and.w r3, r3, #31 - 800e1e4: 2b00 cmp r3, #0 - 800e1e6: d104 bne.n 800e1f2 - 800e1e8: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800e1ec: 3b01 subs r3, #1 - 800e1ee: f8c7 30dc str.w r3, [r7, #220] ; 0xdc - 800e1f2: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e1f6: 881b ldrh r3, [r3, #0] - 800e1f8: b29a uxth r2, r3 - 800e1fa: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800e1fe: b29b uxth r3, r3 - 800e200: 029b lsls r3, r3, #10 - 800e202: b29b uxth r3, r3 - 800e204: 4313 orrs r3, r2 - 800e206: b29b uxth r3, r3 - 800e208: ea6f 4343 mvn.w r3, r3, lsl #17 - 800e20c: ea6f 4353 mvn.w r3, r3, lsr #17 - 800e210: b29a uxth r2, r3 - 800e212: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e216: 801a strh r2, [r3, #0] - 800e218: e060 b.n 800e2dc - 800e21a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e21e: 2b00 cmp r3, #0 - 800e220: d10c bne.n 800e23c - 800e222: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e226: 881b ldrh r3, [r3, #0] - 800e228: b29b uxth r3, r3 - 800e22a: ea6f 4343 mvn.w r3, r3, lsl #17 - 800e22e: ea6f 4353 mvn.w r3, r3, lsr #17 - 800e232: b29a uxth r2, r3 - 800e234: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e238: 801a strh r2, [r3, #0] - 800e23a: e04f b.n 800e2dc - 800e23c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e240: 085b lsrs r3, r3, #1 - 800e242: f8c7 30dc str.w r3, [r7, #220] ; 0xdc - 800e246: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e24a: f003 0301 and.w r3, r3, #1 - 800e24e: 2b00 cmp r3, #0 - 800e250: d004 beq.n 800e25c - 800e252: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800e256: 3301 adds r3, #1 - 800e258: f8c7 30dc str.w r3, [r7, #220] ; 0xdc - 800e25c: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e260: 881b ldrh r3, [r3, #0] - 800e262: b29a uxth r2, r3 - 800e264: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc - 800e268: b29b uxth r3, r3 - 800e26a: 029b lsls r3, r3, #10 - 800e26c: b29b uxth r3, r3 - 800e26e: 4313 orrs r3, r2 - 800e270: b29a uxth r2, r3 - 800e272: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 - 800e276: 801a strh r2, [r3, #0] - 800e278: e030 b.n 800e2dc - 800e27a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e27e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e282: 681b ldr r3, [r3, #0] - 800e284: 785b ldrb r3, [r3, #1] - 800e286: 2b01 cmp r3, #1 - 800e288: d128 bne.n 800e2dc - 800e28a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e28e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e292: 681b ldr r3, [r3, #0] - 800e294: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 - 800e298: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e29c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e2a0: 681b ldr r3, [r3, #0] - 800e2a2: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800e2a6: b29b uxth r3, r3 - 800e2a8: 461a mov r2, r3 - 800e2aa: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 800e2ae: 4413 add r3, r2 - 800e2b0: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 - 800e2b4: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e2b8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e2bc: 681b ldr r3, [r3, #0] - 800e2be: 781b ldrb r3, [r3, #0] - 800e2c0: 00da lsls r2, r3, #3 - 800e2c2: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 - 800e2c6: 4413 add r3, r2 - 800e2c8: f203 4302 addw r3, r3, #1026 ; 0x402 - 800e2cc: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 - 800e2d0: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e2d4: b29a uxth r2, r3 - 800e2d6: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0 - 800e2da: 801a strh r2, [r3, #0] - 800e2dc: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e2e0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e2e4: 681b ldr r3, [r3, #0] - 800e2e6: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 - 800e2ea: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e2ee: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e2f2: 681b ldr r3, [r3, #0] - 800e2f4: 785b ldrb r3, [r3, #1] - 800e2f6: 2b00 cmp r3, #0 - 800e2f8: f040 8085 bne.w 800e406 - 800e2fc: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e300: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e304: 681b ldr r3, [r3, #0] - 800e306: f8c7 30bc str.w r3, [r7, #188] ; 0xbc - 800e30a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e30e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e312: 681b ldr r3, [r3, #0] - 800e314: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800e318: b29b uxth r3, r3 - 800e31a: 461a mov r2, r3 - 800e31c: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 800e320: 4413 add r3, r2 - 800e322: f8c7 30bc str.w r3, [r7, #188] ; 0xbc - 800e326: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e32a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e32e: 681b ldr r3, [r3, #0] - 800e330: 781b ldrb r3, [r3, #0] - 800e332: 00da lsls r2, r3, #3 - 800e334: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc - 800e338: 4413 add r3, r2 - 800e33a: f203 4306 addw r3, r3, #1030 ; 0x406 - 800e33e: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 - 800e342: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e346: 881b ldrh r3, [r3, #0] - 800e348: b29b uxth r3, r3 - 800e34a: f3c3 0309 ubfx r3, r3, #0, #10 - 800e34e: b29a uxth r2, r3 - 800e350: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e354: 801a strh r2, [r3, #0] - 800e356: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e35a: 2b3e cmp r3, #62 ; 0x3e - 800e35c: d923 bls.n 800e3a6 - 800e35e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e362: 095b lsrs r3, r3, #5 - 800e364: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 - 800e368: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e36c: f003 031f and.w r3, r3, #31 - 800e370: 2b00 cmp r3, #0 - 800e372: d104 bne.n 800e37e - 800e374: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800e378: 3b01 subs r3, #1 - 800e37a: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 - 800e37e: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e382: 881b ldrh r3, [r3, #0] - 800e384: b29a uxth r2, r3 - 800e386: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800e38a: b29b uxth r3, r3 - 800e38c: 029b lsls r3, r3, #10 - 800e38e: b29b uxth r3, r3 - 800e390: 4313 orrs r3, r2 - 800e392: b29b uxth r3, r3 - 800e394: ea6f 4343 mvn.w r3, r3, lsl #17 - 800e398: ea6f 4353 mvn.w r3, r3, lsr #17 - 800e39c: b29a uxth r2, r3 - 800e39e: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e3a2: 801a strh r2, [r3, #0] - 800e3a4: e05c b.n 800e460 - 800e3a6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e3aa: 2b00 cmp r3, #0 - 800e3ac: d10c bne.n 800e3c8 - 800e3ae: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e3b2: 881b ldrh r3, [r3, #0] - 800e3b4: b29b uxth r3, r3 - 800e3b6: ea6f 4343 mvn.w r3, r3, lsl #17 - 800e3ba: ea6f 4353 mvn.w r3, r3, lsr #17 - 800e3be: b29a uxth r2, r3 - 800e3c0: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e3c4: 801a strh r2, [r3, #0] - 800e3c6: e04b b.n 800e460 - 800e3c8: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e3cc: 085b lsrs r3, r3, #1 - 800e3ce: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 - 800e3d2: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e3d6: f003 0301 and.w r3, r3, #1 - 800e3da: 2b00 cmp r3, #0 - 800e3dc: d004 beq.n 800e3e8 - 800e3de: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800e3e2: 3301 adds r3, #1 - 800e3e4: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 - 800e3e8: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e3ec: 881b ldrh r3, [r3, #0] - 800e3ee: b29a uxth r2, r3 - 800e3f0: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 - 800e3f4: b29b uxth r3, r3 - 800e3f6: 029b lsls r3, r3, #10 - 800e3f8: b29b uxth r3, r3 - 800e3fa: 4313 orrs r3, r2 - 800e3fc: b29a uxth r2, r3 - 800e3fe: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 - 800e402: 801a strh r2, [r3, #0] - 800e404: e02c b.n 800e460 - 800e406: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e40a: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e40e: 681b ldr r3, [r3, #0] - 800e410: 785b ldrb r3, [r3, #1] - 800e412: 2b01 cmp r3, #1 - 800e414: d124 bne.n 800e460 - 800e416: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e41a: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e41e: 681b ldr r3, [r3, #0] - 800e420: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 - 800e424: b29b uxth r3, r3 - 800e426: 461a mov r2, r3 - 800e428: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 800e42c: 4413 add r3, r2 - 800e42e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 - 800e432: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e436: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e43a: 681b ldr r3, [r3, #0] - 800e43c: 781b ldrb r3, [r3, #0] - 800e43e: 00da lsls r2, r3, #3 - 800e440: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 - 800e444: 4413 add r3, r2 - 800e446: f203 4306 addw r3, r3, #1030 ; 0x406 - 800e44a: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 - 800e44e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 - 800e452: b29a uxth r2, r3 - 800e454: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 - 800e458: 801a strh r2, [r3, #0] - 800e45a: e001 b.n 800e460 + 800f40e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f412: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f416: 681b ldr r3, [r3, #0] + 800f418: 785b ldrb r3, [r3, #1] + 800f41a: 2b00 cmp r3, #0 + 800f41c: f040 8085 bne.w 800f52a + 800f420: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f424: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f428: 681b ldr r3, [r3, #0] + 800f42a: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + 800f42e: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f432: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f436: 681b ldr r3, [r3, #0] + 800f438: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f43c: b29b uxth r3, r3 + 800f43e: 461a mov r2, r3 + 800f440: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 800f444: 4413 add r3, r2 + 800f446: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + 800f44a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f44e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f452: 681b ldr r3, [r3, #0] + 800f454: 781b ldrb r3, [r3, #0] + 800f456: 00da lsls r2, r3, #3 + 800f458: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc + 800f45c: 4413 add r3, r2 + 800f45e: f203 4302 addw r3, r3, #1026 ; 0x402 + 800f462: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 800f466: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f46a: 881b ldrh r3, [r3, #0] + 800f46c: b29b uxth r3, r3 + 800f46e: f3c3 0309 ubfx r3, r3, #0, #10 + 800f472: b29a uxth r2, r3 + 800f474: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f478: 801a strh r2, [r3, #0] + 800f47a: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f47e: 2b3e cmp r3, #62 ; 0x3e + 800f480: d923 bls.n 800f4ca + 800f482: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f486: 095b lsrs r3, r3, #5 + 800f488: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + 800f48c: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f490: f003 031f and.w r3, r3, #31 + 800f494: 2b00 cmp r3, #0 + 800f496: d104 bne.n 800f4a2 + 800f498: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800f49c: 3b01 subs r3, #1 + 800f49e: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + 800f4a2: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f4a6: 881b ldrh r3, [r3, #0] + 800f4a8: b29a uxth r2, r3 + 800f4aa: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800f4ae: b29b uxth r3, r3 + 800f4b0: 029b lsls r3, r3, #10 + 800f4b2: b29b uxth r3, r3 + 800f4b4: 4313 orrs r3, r2 + 800f4b6: b29b uxth r3, r3 + 800f4b8: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f4bc: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f4c0: b29a uxth r2, r3 + 800f4c2: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f4c6: 801a strh r2, [r3, #0] + 800f4c8: e060 b.n 800f58c + 800f4ca: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f4ce: 2b00 cmp r3, #0 + 800f4d0: d10c bne.n 800f4ec + 800f4d2: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f4d6: 881b ldrh r3, [r3, #0] + 800f4d8: b29b uxth r3, r3 + 800f4da: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f4de: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f4e2: b29a uxth r2, r3 + 800f4e4: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f4e8: 801a strh r2, [r3, #0] + 800f4ea: e04f b.n 800f58c + 800f4ec: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f4f0: 085b lsrs r3, r3, #1 + 800f4f2: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + 800f4f6: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f4fa: f003 0301 and.w r3, r3, #1 + 800f4fe: 2b00 cmp r3, #0 + 800f500: d004 beq.n 800f50c + 800f502: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800f506: 3301 adds r3, #1 + 800f508: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + 800f50c: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f510: 881b ldrh r3, [r3, #0] + 800f512: b29a uxth r2, r3 + 800f514: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800f518: b29b uxth r3, r3 + 800f51a: 029b lsls r3, r3, #10 + 800f51c: b29b uxth r3, r3 + 800f51e: 4313 orrs r3, r2 + 800f520: b29a uxth r2, r3 + 800f522: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 800f526: 801a strh r2, [r3, #0] + 800f528: e030 b.n 800f58c + 800f52a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f52e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f532: 681b ldr r3, [r3, #0] + 800f534: 785b ldrb r3, [r3, #1] + 800f536: 2b01 cmp r3, #1 + 800f538: d128 bne.n 800f58c + 800f53a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f53e: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f542: 681b ldr r3, [r3, #0] + 800f544: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + 800f548: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f54c: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f550: 681b ldr r3, [r3, #0] + 800f552: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f556: b29b uxth r3, r3 + 800f558: 461a mov r2, r3 + 800f55a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 800f55e: 4413 add r3, r2 + 800f560: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + 800f564: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f568: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f56c: 681b ldr r3, [r3, #0] + 800f56e: 781b ldrb r3, [r3, #0] + 800f570: 00da lsls r2, r3, #3 + 800f572: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 800f576: 4413 add r3, r2 + 800f578: f203 4302 addw r3, r3, #1026 ; 0x402 + 800f57c: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 800f580: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f584: b29a uxth r2, r3 + 800f586: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0 + 800f58a: 801a strh r2, [r3, #0] + 800f58c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f590: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f594: 681b ldr r3, [r3, #0] + 800f596: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 800f59a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f59e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f5a2: 681b ldr r3, [r3, #0] + 800f5a4: 785b ldrb r3, [r3, #1] + 800f5a6: 2b00 cmp r3, #0 + 800f5a8: f040 8085 bne.w 800f6b6 + 800f5ac: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f5b0: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f5b4: 681b ldr r3, [r3, #0] + 800f5b6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 800f5ba: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f5be: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f5c2: 681b ldr r3, [r3, #0] + 800f5c4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f5c8: b29b uxth r3, r3 + 800f5ca: 461a mov r2, r3 + 800f5cc: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 800f5d0: 4413 add r3, r2 + 800f5d2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 800f5d6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f5da: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f5de: 681b ldr r3, [r3, #0] + 800f5e0: 781b ldrb r3, [r3, #0] + 800f5e2: 00da lsls r2, r3, #3 + 800f5e4: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc + 800f5e8: 4413 add r3, r2 + 800f5ea: f203 4306 addw r3, r3, #1030 ; 0x406 + 800f5ee: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 800f5f2: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f5f6: 881b ldrh r3, [r3, #0] + 800f5f8: b29b uxth r3, r3 + 800f5fa: f3c3 0309 ubfx r3, r3, #0, #10 + 800f5fe: b29a uxth r2, r3 + 800f600: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f604: 801a strh r2, [r3, #0] + 800f606: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f60a: 2b3e cmp r3, #62 ; 0x3e + 800f60c: d923 bls.n 800f656 + 800f60e: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f612: 095b lsrs r3, r3, #5 + 800f614: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 800f618: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f61c: f003 031f and.w r3, r3, #31 + 800f620: 2b00 cmp r3, #0 + 800f622: d104 bne.n 800f62e + 800f624: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800f628: 3b01 subs r3, #1 + 800f62a: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 800f62e: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f632: 881b ldrh r3, [r3, #0] + 800f634: b29a uxth r2, r3 + 800f636: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800f63a: b29b uxth r3, r3 + 800f63c: 029b lsls r3, r3, #10 + 800f63e: b29b uxth r3, r3 + 800f640: 4313 orrs r3, r2 + 800f642: b29b uxth r3, r3 + 800f644: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f648: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f64c: b29a uxth r2, r3 + 800f64e: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f652: 801a strh r2, [r3, #0] + 800f654: e05c b.n 800f710 + 800f656: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f65a: 2b00 cmp r3, #0 + 800f65c: d10c bne.n 800f678 + 800f65e: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f662: 881b ldrh r3, [r3, #0] + 800f664: b29b uxth r3, r3 + 800f666: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f66a: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f66e: b29a uxth r2, r3 + 800f670: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f674: 801a strh r2, [r3, #0] + 800f676: e04b b.n 800f710 + 800f678: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f67c: 085b lsrs r3, r3, #1 + 800f67e: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 800f682: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f686: f003 0301 and.w r3, r3, #1 + 800f68a: 2b00 cmp r3, #0 + 800f68c: d004 beq.n 800f698 + 800f68e: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800f692: 3301 adds r3, #1 + 800f694: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 800f698: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f69c: 881b ldrh r3, [r3, #0] + 800f69e: b29a uxth r2, r3 + 800f6a0: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 800f6a4: b29b uxth r3, r3 + 800f6a6: 029b lsls r3, r3, #10 + 800f6a8: b29b uxth r3, r3 + 800f6aa: 4313 orrs r3, r2 + 800f6ac: b29a uxth r2, r3 + 800f6ae: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 800f6b2: 801a strh r2, [r3, #0] + 800f6b4: e02c b.n 800f710 + 800f6b6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f6ba: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f6be: 681b ldr r3, [r3, #0] + 800f6c0: 785b ldrb r3, [r3, #1] + 800f6c2: 2b01 cmp r3, #1 + 800f6c4: d124 bne.n 800f710 + 800f6c6: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f6ca: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f6ce: 681b ldr r3, [r3, #0] + 800f6d0: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50 + 800f6d4: b29b uxth r3, r3 + 800f6d6: 461a mov r2, r3 + 800f6d8: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 800f6dc: 4413 add r3, r2 + 800f6de: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 800f6e2: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f6e6: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f6ea: 681b ldr r3, [r3, #0] + 800f6ec: 781b ldrb r3, [r3, #0] + 800f6ee: 00da lsls r2, r3, #3 + 800f6f0: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4 + 800f6f4: 4413 add r3, r2 + 800f6f6: f203 4306 addw r3, r3, #1030 ; 0x406 + 800f6fa: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 800f6fe: f8d7 3104 ldr.w r3, [r7, #260] ; 0x104 + 800f702: b29a uxth r2, r3 + 800f704: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 800f708: 801a strh r2, [r3, #0] + 800f70a: e001 b.n 800f710 } else { return HAL_ERROR; - 800e45c: 2301 movs r3, #1 - 800e45e: e03a b.n 800e4d6 + 800f70c: 2301 movs r3, #1 + 800f70e: e03a b.n 800f786 } } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - 800e460: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e464: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e468: 681a ldr r2, [r3, #0] - 800e46a: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e46e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e472: 681b ldr r3, [r3, #0] - 800e474: 781b ldrb r3, [r3, #0] - 800e476: 009b lsls r3, r3, #2 - 800e478: 4413 add r3, r2 - 800e47a: 881b ldrh r3, [r3, #0] - 800e47c: b29b uxth r3, r3 - 800e47e: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800e482: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e486: f8a7 308a strh.w r3, [r7, #138] ; 0x8a - 800e48a: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a - 800e48e: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 800e492: f8a7 308a strh.w r3, [r7, #138] ; 0x8a - 800e496: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a - 800e49a: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 800e49e: f8a7 308a strh.w r3, [r7, #138] ; 0x8a - 800e4a2: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e4a6: f5a3 7382 sub.w r3, r3, #260 ; 0x104 - 800e4aa: 681a ldr r2, [r3, #0] - 800e4ac: f507 7384 add.w r3, r7, #264 ; 0x108 - 800e4b0: f5a3 7384 sub.w r3, r3, #264 ; 0x108 - 800e4b4: 681b ldr r3, [r3, #0] - 800e4b6: 781b ldrb r3, [r3, #0] - 800e4b8: 009b lsls r3, r3, #2 - 800e4ba: 441a add r2, r3 - 800e4bc: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a - 800e4c0: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e4c4: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e4c8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e4cc: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e4d0: b29b uxth r3, r3 - 800e4d2: 8013 strh r3, [r2, #0] + 800f710: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f714: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f718: 681a ldr r2, [r3, #0] + 800f71a: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f71e: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f722: 681b ldr r3, [r3, #0] + 800f724: 781b ldrb r3, [r3, #0] + 800f726: 009b lsls r3, r3, #2 + 800f728: 4413 add r3, r2 + 800f72a: 881b ldrh r3, [r3, #0] + 800f72c: b29b uxth r3, r3 + 800f72e: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800f732: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f736: f8a7 308a strh.w r3, [r7, #138] ; 0x8a + 800f73a: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a + 800f73e: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800f742: f8a7 308a strh.w r3, [r7, #138] ; 0x8a + 800f746: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a + 800f74a: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 800f74e: f8a7 308a strh.w r3, [r7, #138] ; 0x8a + 800f752: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f756: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 800f75a: 681a ldr r2, [r3, #0] + 800f75c: f507 7384 add.w r3, r7, #264 ; 0x108 + 800f760: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 800f764: 681b ldr r3, [r3, #0] + 800f766: 781b ldrb r3, [r3, #0] + 800f768: 009b lsls r3, r3, #2 + 800f76a: 441a add r2, r3 + 800f76c: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a + 800f770: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f774: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f778: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f77c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f780: b29b uxth r3, r3 + 800f782: 8013 strh r3, [r2, #0] } return HAL_OK; - 800e4d4: 2300 movs r3, #0 + 800f784: 2300 movs r3, #0 } - 800e4d6: 4618 mov r0, r3 - 800e4d8: f507 7784 add.w r7, r7, #264 ; 0x108 - 800e4dc: 46bd mov sp, r7 - 800e4de: bd80 pop {r7, pc} + 800f786: 4618 mov r0, r3 + 800f788: f507 7784 add.w r7, r7, #264 ; 0x108 + 800f78c: 46bd mov sp, r7 + 800f78e: bd80 pop {r7, pc} -0800e4e0 : +0800f790 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - 800e4e0: b480 push {r7} - 800e4e2: b085 sub sp, #20 - 800e4e4: af00 add r7, sp, #0 - 800e4e6: 6078 str r0, [r7, #4] - 800e4e8: 6039 str r1, [r7, #0] + 800f790: b480 push {r7} + 800f792: b085 sub sp, #20 + 800f794: af00 add r7, sp, #0 + 800f796: 6078 str r0, [r7, #4] + 800f798: 6039 str r1, [r7, #0] if (ep->is_in != 0U) - 800e4ea: 683b ldr r3, [r7, #0] - 800e4ec: 785b ldrb r3, [r3, #1] - 800e4ee: 2b00 cmp r3, #0 - 800e4f0: d020 beq.n 800e534 + 800f79a: 683b ldr r3, [r7, #0] + 800f79c: 785b ldrb r3, [r3, #1] + 800f79e: 2b00 cmp r3, #0 + 800f7a0: d020 beq.n 800f7e4 { PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); - 800e4f2: 687a ldr r2, [r7, #4] - 800e4f4: 683b ldr r3, [r7, #0] - 800e4f6: 781b ldrb r3, [r3, #0] - 800e4f8: 009b lsls r3, r3, #2 - 800e4fa: 4413 add r3, r2 - 800e4fc: 881b ldrh r3, [r3, #0] - 800e4fe: b29b uxth r3, r3 - 800e500: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800e504: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800e508: 81bb strh r3, [r7, #12] - 800e50a: 89bb ldrh r3, [r7, #12] - 800e50c: f083 0310 eor.w r3, r3, #16 - 800e510: 81bb strh r3, [r7, #12] - 800e512: 687a ldr r2, [r7, #4] - 800e514: 683b ldr r3, [r7, #0] - 800e516: 781b ldrb r3, [r3, #0] - 800e518: 009b lsls r3, r3, #2 - 800e51a: 441a add r2, r3 - 800e51c: 89bb ldrh r3, [r7, #12] - 800e51e: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e522: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e526: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e52a: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e52e: b29b uxth r3, r3 - 800e530: 8013 strh r3, [r2, #0] - 800e532: e01f b.n 800e574 + 800f7a2: 687a ldr r2, [r7, #4] + 800f7a4: 683b ldr r3, [r7, #0] + 800f7a6: 781b ldrb r3, [r3, #0] + 800f7a8: 009b lsls r3, r3, #2 + 800f7aa: 4413 add r3, r2 + 800f7ac: 881b ldrh r3, [r3, #0] + 800f7ae: b29b uxth r3, r3 + 800f7b0: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800f7b4: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800f7b8: 81bb strh r3, [r7, #12] + 800f7ba: 89bb ldrh r3, [r7, #12] + 800f7bc: f083 0310 eor.w r3, r3, #16 + 800f7c0: 81bb strh r3, [r7, #12] + 800f7c2: 687a ldr r2, [r7, #4] + 800f7c4: 683b ldr r3, [r7, #0] + 800f7c6: 781b ldrb r3, [r3, #0] + 800f7c8: 009b lsls r3, r3, #2 + 800f7ca: 441a add r2, r3 + 800f7cc: 89bb ldrh r3, [r7, #12] + 800f7ce: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f7d2: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f7d6: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f7da: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f7de: b29b uxth r3, r3 + 800f7e0: 8013 strh r3, [r2, #0] + 800f7e2: e01f b.n 800f824 } else { PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); - 800e534: 687a ldr r2, [r7, #4] - 800e536: 683b ldr r3, [r7, #0] - 800e538: 781b ldrb r3, [r3, #0] - 800e53a: 009b lsls r3, r3, #2 - 800e53c: 4413 add r3, r2 - 800e53e: 881b ldrh r3, [r3, #0] - 800e540: b29b uxth r3, r3 - 800e542: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800e546: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e54a: 81fb strh r3, [r7, #14] - 800e54c: 89fb ldrh r3, [r7, #14] - 800e54e: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 800e552: 81fb strh r3, [r7, #14] - 800e554: 687a ldr r2, [r7, #4] - 800e556: 683b ldr r3, [r7, #0] - 800e558: 781b ldrb r3, [r3, #0] - 800e55a: 009b lsls r3, r3, #2 - 800e55c: 441a add r2, r3 - 800e55e: 89fb ldrh r3, [r7, #14] - 800e560: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e564: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e568: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e56c: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e570: b29b uxth r3, r3 - 800e572: 8013 strh r3, [r2, #0] + 800f7e4: 687a ldr r2, [r7, #4] + 800f7e6: 683b ldr r3, [r7, #0] + 800f7e8: 781b ldrb r3, [r3, #0] + 800f7ea: 009b lsls r3, r3, #2 + 800f7ec: 4413 add r3, r2 + 800f7ee: 881b ldrh r3, [r3, #0] + 800f7f0: b29b uxth r3, r3 + 800f7f2: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800f7f6: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f7fa: 81fb strh r3, [r7, #14] + 800f7fc: 89fb ldrh r3, [r7, #14] + 800f7fe: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800f802: 81fb strh r3, [r7, #14] + 800f804: 687a ldr r2, [r7, #4] + 800f806: 683b ldr r3, [r7, #0] + 800f808: 781b ldrb r3, [r3, #0] + 800f80a: 009b lsls r3, r3, #2 + 800f80c: 441a add r2, r3 + 800f80e: 89fb ldrh r3, [r7, #14] + 800f810: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f814: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f818: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f81c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f820: b29b uxth r3, r3 + 800f822: 8013 strh r3, [r2, #0] } return HAL_OK; - 800e574: 2300 movs r3, #0 + 800f824: 2300 movs r3, #0 } - 800e576: 4618 mov r0, r3 - 800e578: 3714 adds r7, #20 - 800e57a: 46bd mov sp, r7 - 800e57c: f85d 7b04 ldr.w r7, [sp], #4 - 800e580: 4770 bx lr + 800f826: 4618 mov r0, r3 + 800f828: 3714 adds r7, #20 + 800f82a: 46bd mov sp, r7 + 800f82c: f85d 7b04 ldr.w r7, [sp], #4 + 800f830: 4770 bx lr -0800e582 : +0800f832 : * @param USBx Selected device * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - 800e582: b480 push {r7} - 800e584: b087 sub sp, #28 - 800e586: af00 add r7, sp, #0 - 800e588: 6078 str r0, [r7, #4] - 800e58a: 6039 str r1, [r7, #0] + 800f832: b480 push {r7} + 800f834: b087 sub sp, #28 + 800f836: af00 add r7, sp, #0 + 800f838: 6078 str r0, [r7, #4] + 800f83a: 6039 str r1, [r7, #0] if (ep->doublebuffer == 0U) - 800e58c: 683b ldr r3, [r7, #0] - 800e58e: 7b1b ldrb r3, [r3, #12] - 800e590: 2b00 cmp r3, #0 - 800e592: f040 809d bne.w 800e6d0 + 800f83c: 683b ldr r3, [r7, #0] + 800f83e: 7b1b ldrb r3, [r3, #12] + 800f840: 2b00 cmp r3, #0 + 800f842: f040 809d bne.w 800f980 { if (ep->is_in != 0U) - 800e596: 683b ldr r3, [r7, #0] - 800e598: 785b ldrb r3, [r3, #1] - 800e59a: 2b00 cmp r3, #0 - 800e59c: d04c beq.n 800e638 + 800f846: 683b ldr r3, [r7, #0] + 800f848: 785b ldrb r3, [r3, #1] + 800f84a: 2b00 cmp r3, #0 + 800f84c: d04c beq.n 800f8e8 { PCD_CLEAR_TX_DTOG(USBx, ep->num); - 800e59e: 687a ldr r2, [r7, #4] - 800e5a0: 683b ldr r3, [r7, #0] - 800e5a2: 781b ldrb r3, [r3, #0] - 800e5a4: 009b lsls r3, r3, #2 - 800e5a6: 4413 add r3, r2 - 800e5a8: 881b ldrh r3, [r3, #0] - 800e5aa: 823b strh r3, [r7, #16] - 800e5ac: 8a3b ldrh r3, [r7, #16] - 800e5ae: f003 0340 and.w r3, r3, #64 ; 0x40 - 800e5b2: 2b00 cmp r3, #0 - 800e5b4: d01b beq.n 800e5ee - 800e5b6: 687a ldr r2, [r7, #4] - 800e5b8: 683b ldr r3, [r7, #0] - 800e5ba: 781b ldrb r3, [r3, #0] - 800e5bc: 009b lsls r3, r3, #2 - 800e5be: 4413 add r3, r2 - 800e5c0: 881b ldrh r3, [r3, #0] - 800e5c2: b29b uxth r3, r3 - 800e5c4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800e5c8: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e5cc: 81fb strh r3, [r7, #14] - 800e5ce: 687a ldr r2, [r7, #4] - 800e5d0: 683b ldr r3, [r7, #0] - 800e5d2: 781b ldrb r3, [r3, #0] - 800e5d4: 009b lsls r3, r3, #2 - 800e5d6: 441a add r2, r3 - 800e5d8: 89fb ldrh r3, [r7, #14] - 800e5da: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e5de: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e5e2: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e5e6: f043 03c0 orr.w r3, r3, #192 ; 0xc0 - 800e5ea: b29b uxth r3, r3 - 800e5ec: 8013 strh r3, [r2, #0] + 800f84e: 687a ldr r2, [r7, #4] + 800f850: 683b ldr r3, [r7, #0] + 800f852: 781b ldrb r3, [r3, #0] + 800f854: 009b lsls r3, r3, #2 + 800f856: 4413 add r3, r2 + 800f858: 881b ldrh r3, [r3, #0] + 800f85a: 823b strh r3, [r7, #16] + 800f85c: 8a3b ldrh r3, [r7, #16] + 800f85e: f003 0340 and.w r3, r3, #64 ; 0x40 + 800f862: 2b00 cmp r3, #0 + 800f864: d01b beq.n 800f89e + 800f866: 687a ldr r2, [r7, #4] + 800f868: 683b ldr r3, [r7, #0] + 800f86a: 781b ldrb r3, [r3, #0] + 800f86c: 009b lsls r3, r3, #2 + 800f86e: 4413 add r3, r2 + 800f870: 881b ldrh r3, [r3, #0] + 800f872: b29b uxth r3, r3 + 800f874: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800f878: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f87c: 81fb strh r3, [r7, #14] + 800f87e: 687a ldr r2, [r7, #4] + 800f880: 683b ldr r3, [r7, #0] + 800f882: 781b ldrb r3, [r3, #0] + 800f884: 009b lsls r3, r3, #2 + 800f886: 441a add r2, r3 + 800f888: 89fb ldrh r3, [r7, #14] + 800f88a: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f88e: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f892: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f896: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + 800f89a: b29b uxth r3, r3 + 800f89c: 8013 strh r3, [r2, #0] if (ep->type != EP_TYPE_ISOC) - 800e5ee: 683b ldr r3, [r7, #0] - 800e5f0: 78db ldrb r3, [r3, #3] - 800e5f2: 2b01 cmp r3, #1 - 800e5f4: d06c beq.n 800e6d0 + 800f89e: 683b ldr r3, [r7, #0] + 800f8a0: 78db ldrb r3, [r3, #3] + 800f8a2: 2b01 cmp r3, #1 + 800f8a4: d06c beq.n 800f980 { /* Configure NAK status for the Endpoint */ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - 800e5f6: 687a ldr r2, [r7, #4] - 800e5f8: 683b ldr r3, [r7, #0] - 800e5fa: 781b ldrb r3, [r3, #0] - 800e5fc: 009b lsls r3, r3, #2 - 800e5fe: 4413 add r3, r2 - 800e600: 881b ldrh r3, [r3, #0] - 800e602: b29b uxth r3, r3 - 800e604: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800e608: f023 0340 bic.w r3, r3, #64 ; 0x40 - 800e60c: 81bb strh r3, [r7, #12] - 800e60e: 89bb ldrh r3, [r7, #12] - 800e610: f083 0320 eor.w r3, r3, #32 - 800e614: 81bb strh r3, [r7, #12] - 800e616: 687a ldr r2, [r7, #4] - 800e618: 683b ldr r3, [r7, #0] - 800e61a: 781b ldrb r3, [r3, #0] - 800e61c: 009b lsls r3, r3, #2 - 800e61e: 441a add r2, r3 - 800e620: 89bb ldrh r3, [r7, #12] - 800e622: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e626: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e62a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e62e: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e632: b29b uxth r3, r3 - 800e634: 8013 strh r3, [r2, #0] - 800e636: e04b b.n 800e6d0 + 800f8a6: 687a ldr r2, [r7, #4] + 800f8a8: 683b ldr r3, [r7, #0] + 800f8aa: 781b ldrb r3, [r3, #0] + 800f8ac: 009b lsls r3, r3, #2 + 800f8ae: 4413 add r3, r2 + 800f8b0: 881b ldrh r3, [r3, #0] + 800f8b2: b29b uxth r3, r3 + 800f8b4: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800f8b8: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800f8bc: 81bb strh r3, [r7, #12] + 800f8be: 89bb ldrh r3, [r7, #12] + 800f8c0: f083 0320 eor.w r3, r3, #32 + 800f8c4: 81bb strh r3, [r7, #12] + 800f8c6: 687a ldr r2, [r7, #4] + 800f8c8: 683b ldr r3, [r7, #0] + 800f8ca: 781b ldrb r3, [r3, #0] + 800f8cc: 009b lsls r3, r3, #2 + 800f8ce: 441a add r2, r3 + 800f8d0: 89bb ldrh r3, [r7, #12] + 800f8d2: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f8d6: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f8da: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f8de: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f8e2: b29b uxth r3, r3 + 800f8e4: 8013 strh r3, [r2, #0] + 800f8e6: e04b b.n 800f980 } } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); - 800e638: 687a ldr r2, [r7, #4] - 800e63a: 683b ldr r3, [r7, #0] - 800e63c: 781b ldrb r3, [r3, #0] - 800e63e: 009b lsls r3, r3, #2 - 800e640: 4413 add r3, r2 - 800e642: 881b ldrh r3, [r3, #0] - 800e644: 82fb strh r3, [r7, #22] - 800e646: 8afb ldrh r3, [r7, #22] - 800e648: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800e64c: 2b00 cmp r3, #0 - 800e64e: d01b beq.n 800e688 - 800e650: 687a ldr r2, [r7, #4] - 800e652: 683b ldr r3, [r7, #0] - 800e654: 781b ldrb r3, [r3, #0] - 800e656: 009b lsls r3, r3, #2 - 800e658: 4413 add r3, r2 - 800e65a: 881b ldrh r3, [r3, #0] - 800e65c: b29b uxth r3, r3 - 800e65e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 - 800e662: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e666: 82bb strh r3, [r7, #20] - 800e668: 687a ldr r2, [r7, #4] - 800e66a: 683b ldr r3, [r7, #0] - 800e66c: 781b ldrb r3, [r3, #0] - 800e66e: 009b lsls r3, r3, #2 - 800e670: 441a add r2, r3 - 800e672: 8abb ldrh r3, [r7, #20] - 800e674: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e678: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e67c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800e680: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e684: b29b uxth r3, r3 - 800e686: 8013 strh r3, [r2, #0] + 800f8e8: 687a ldr r2, [r7, #4] + 800f8ea: 683b ldr r3, [r7, #0] + 800f8ec: 781b ldrb r3, [r3, #0] + 800f8ee: 009b lsls r3, r3, #2 + 800f8f0: 4413 add r3, r2 + 800f8f2: 881b ldrh r3, [r3, #0] + 800f8f4: 82fb strh r3, [r7, #22] + 800f8f6: 8afb ldrh r3, [r7, #22] + 800f8f8: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800f8fc: 2b00 cmp r3, #0 + 800f8fe: d01b beq.n 800f938 + 800f900: 687a ldr r2, [r7, #4] + 800f902: 683b ldr r3, [r7, #0] + 800f904: 781b ldrb r3, [r3, #0] + 800f906: 009b lsls r3, r3, #2 + 800f908: 4413 add r3, r2 + 800f90a: 881b ldrh r3, [r3, #0] + 800f90c: b29b uxth r3, r3 + 800f90e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 + 800f912: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f916: 82bb strh r3, [r7, #20] + 800f918: 687a ldr r2, [r7, #4] + 800f91a: 683b ldr r3, [r7, #0] + 800f91c: 781b ldrb r3, [r3, #0] + 800f91e: 009b lsls r3, r3, #2 + 800f920: 441a add r2, r3 + 800f922: 8abb ldrh r3, [r7, #20] + 800f924: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f928: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f92c: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800f930: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f934: b29b uxth r3, r3 + 800f936: 8013 strh r3, [r2, #0] /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - 800e688: 687a ldr r2, [r7, #4] - 800e68a: 683b ldr r3, [r7, #0] - 800e68c: 781b ldrb r3, [r3, #0] - 800e68e: 009b lsls r3, r3, #2 - 800e690: 4413 add r3, r2 - 800e692: 881b ldrh r3, [r3, #0] - 800e694: b29b uxth r3, r3 - 800e696: f423 4380 bic.w r3, r3, #16384 ; 0x4000 - 800e69a: f023 0370 bic.w r3, r3, #112 ; 0x70 - 800e69e: 827b strh r3, [r7, #18] - 800e6a0: 8a7b ldrh r3, [r7, #18] - 800e6a2: f483 5380 eor.w r3, r3, #4096 ; 0x1000 - 800e6a6: 827b strh r3, [r7, #18] - 800e6a8: 8a7b ldrh r3, [r7, #18] - 800e6aa: f483 5300 eor.w r3, r3, #8192 ; 0x2000 - 800e6ae: 827b strh r3, [r7, #18] - 800e6b0: 687a ldr r2, [r7, #4] - 800e6b2: 683b ldr r3, [r7, #0] - 800e6b4: 781b ldrb r3, [r3, #0] - 800e6b6: 009b lsls r3, r3, #2 - 800e6b8: 441a add r2, r3 - 800e6ba: 8a7b ldrh r3, [r7, #18] - 800e6bc: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 - 800e6c0: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 - 800e6c4: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 800e6c8: f043 0380 orr.w r3, r3, #128 ; 0x80 - 800e6cc: b29b uxth r3, r3 - 800e6ce: 8013 strh r3, [r2, #0] + 800f938: 687a ldr r2, [r7, #4] + 800f93a: 683b ldr r3, [r7, #0] + 800f93c: 781b ldrb r3, [r3, #0] + 800f93e: 009b lsls r3, r3, #2 + 800f940: 4413 add r3, r2 + 800f942: 881b ldrh r3, [r3, #0] + 800f944: b29b uxth r3, r3 + 800f946: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 800f94a: f023 0370 bic.w r3, r3, #112 ; 0x70 + 800f94e: 827b strh r3, [r7, #18] + 800f950: 8a7b ldrh r3, [r7, #18] + 800f952: f483 5380 eor.w r3, r3, #4096 ; 0x1000 + 800f956: 827b strh r3, [r7, #18] + 800f958: 8a7b ldrh r3, [r7, #18] + 800f95a: f483 5300 eor.w r3, r3, #8192 ; 0x2000 + 800f95e: 827b strh r3, [r7, #18] + 800f960: 687a ldr r2, [r7, #4] + 800f962: 683b ldr r3, [r7, #0] + 800f964: 781b ldrb r3, [r3, #0] + 800f966: 009b lsls r3, r3, #2 + 800f968: 441a add r2, r3 + 800f96a: 8a7b ldrh r3, [r7, #18] + 800f96c: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000 + 800f970: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 800f974: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800f978: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800f97c: b29b uxth r3, r3 + 800f97e: 8013 strh r3, [r2, #0] } } return HAL_OK; - 800e6d0: 2300 movs r3, #0 + 800f980: 2300 movs r3, #0 } - 800e6d2: 4618 mov r0, r3 - 800e6d4: 371c adds r7, #28 - 800e6d6: 46bd mov sp, r7 - 800e6d8: f85d 7b04 ldr.w r7, [sp], #4 - 800e6dc: 4770 bx lr + 800f982: 4618 mov r0, r3 + 800f984: 371c adds r7, #28 + 800f986: 46bd mov sp, r7 + 800f988: f85d 7b04 ldr.w r7, [sp], #4 + 800f98c: 4770 bx lr -0800e6de : +0800f98e : * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) { - 800e6de: b480 push {r7} - 800e6e0: b083 sub sp, #12 - 800e6e2: af00 add r7, sp, #0 - 800e6e4: 6078 str r0, [r7, #4] - 800e6e6: 460b mov r3, r1 - 800e6e8: 70fb strb r3, [r7, #3] + 800f98e: b480 push {r7} + 800f990: b083 sub sp, #12 + 800f992: af00 add r7, sp, #0 + 800f994: 6078 str r0, [r7, #4] + 800f996: 460b mov r3, r1 + 800f998: 70fb strb r3, [r7, #3] if (address == 0U) - 800e6ea: 78fb ldrb r3, [r7, #3] - 800e6ec: 2b00 cmp r3, #0 - 800e6ee: d103 bne.n 800e6f8 + 800f99a: 78fb ldrb r3, [r7, #3] + 800f99c: 2b00 cmp r3, #0 + 800f99e: d103 bne.n 800f9a8 { /* set device address and enable function */ USBx->DADDR = (uint16_t)USB_DADDR_EF; - 800e6f0: 687b ldr r3, [r7, #4] - 800e6f2: 2280 movs r2, #128 ; 0x80 - 800e6f4: f8a3 204c strh.w r2, [r3, #76] ; 0x4c + 800f9a0: 687b ldr r3, [r7, #4] + 800f9a2: 2280 movs r2, #128 ; 0x80 + 800f9a4: f8a3 204c strh.w r2, [r3, #76] ; 0x4c } return HAL_OK; - 800e6f8: 2300 movs r3, #0 + 800f9a8: 2300 movs r3, #0 } - 800e6fa: 4618 mov r0, r3 - 800e6fc: 370c adds r7, #12 - 800e6fe: 46bd mov sp, r7 - 800e700: f85d 7b04 ldr.w r7, [sp], #4 - 800e704: 4770 bx lr + 800f9aa: 4618 mov r0, r3 + 800f9ac: 370c adds r7, #12 + 800f9ae: 46bd mov sp, r7 + 800f9b0: f85d 7b04 ldr.w r7, [sp], #4 + 800f9b4: 4770 bx lr -0800e706 : +0800f9b6 : * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { - 800e706: b480 push {r7} - 800e708: b083 sub sp, #12 - 800e70a: af00 add r7, sp, #0 - 800e70c: 6078 str r0, [r7, #4] + 800f9b6: b480 push {r7} + 800f9b8: b083 sub sp, #12 + 800f9ba: af00 add r7, sp, #0 + 800f9bc: 6078 str r0, [r7, #4] /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; - 800e70e: 687b ldr r3, [r7, #4] - 800e710: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 - 800e714: b29b uxth r3, r3 - 800e716: ea6f 4343 mvn.w r3, r3, lsl #17 - 800e71a: ea6f 4353 mvn.w r3, r3, lsr #17 - 800e71e: b29a uxth r2, r3 - 800e720: 687b ldr r3, [r7, #4] - 800e722: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + 800f9be: 687b ldr r3, [r7, #4] + 800f9c0: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 + 800f9c4: b29b uxth r3, r3 + 800f9c6: ea6f 4343 mvn.w r3, r3, lsl #17 + 800f9ca: ea6f 4353 mvn.w r3, r3, lsr #17 + 800f9ce: b29a uxth r2, r3 + 800f9d0: 687b ldr r3, [r7, #4] + 800f9d2: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 return HAL_OK; - 800e726: 2300 movs r3, #0 + 800f9d6: 2300 movs r3, #0 } - 800e728: 4618 mov r0, r3 - 800e72a: 370c adds r7, #12 - 800e72c: 46bd mov sp, r7 - 800e72e: f85d 7b04 ldr.w r7, [sp], #4 - 800e732: 4770 bx lr + 800f9d8: 4618 mov r0, r3 + 800f9da: 370c adds r7, #12 + 800f9dc: 46bd mov sp, r7 + 800f9de: f85d 7b04 ldr.w r7, [sp], #4 + 800f9e2: 4770 bx lr -0800e734 : +0800f9e4 : * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) { - 800e734: b480 push {r7} - 800e736: b083 sub sp, #12 - 800e738: af00 add r7, sp, #0 - 800e73a: 6078 str r0, [r7, #4] + 800f9e4: b480 push {r7} + 800f9e6: b083 sub sp, #12 + 800f9e8: af00 add r7, sp, #0 + 800f9ea: 6078 str r0, [r7, #4] /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU)); - 800e73c: 687b ldr r3, [r7, #4] - 800e73e: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 - 800e742: b29b uxth r3, r3 - 800e744: f3c3 030e ubfx r3, r3, #0, #15 - 800e748: b29a uxth r2, r3 - 800e74a: 687b ldr r3, [r7, #4] - 800e74c: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + 800f9ec: 687b ldr r3, [r7, #4] + 800f9ee: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58 + 800f9f2: b29b uxth r3, r3 + 800f9f4: f3c3 030e ubfx r3, r3, #0, #15 + 800f9f8: b29a uxth r2, r3 + 800f9fa: 687b ldr r3, [r7, #4] + 800f9fc: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 return HAL_OK; - 800e750: 2300 movs r3, #0 + 800fa00: 2300 movs r3, #0 } - 800e752: 4618 mov r0, r3 - 800e754: 370c adds r7, #12 - 800e756: 46bd mov sp, r7 - 800e758: f85d 7b04 ldr.w r7, [sp], #4 - 800e75c: 4770 bx lr + 800fa02: 4618 mov r0, r3 + 800fa04: 370c adds r7, #12 + 800fa06: 46bd mov sp, r7 + 800fa08: f85d 7b04 ldr.w r7, [sp], #4 + 800fa0c: 4770 bx lr -0800e75e : +0800fa0e : * @brief USB_ReadInterrupts return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { - 800e75e: b480 push {r7} - 800e760: b085 sub sp, #20 - 800e762: af00 add r7, sp, #0 - 800e764: 6078 str r0, [r7, #4] + 800fa0e: b480 push {r7} + 800fa10: b085 sub sp, #20 + 800fa12: af00 add r7, sp, #0 + 800fa14: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->ISTR; - 800e766: 687b ldr r3, [r7, #4] - 800e768: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 - 800e76c: b29b uxth r3, r3 - 800e76e: 60fb str r3, [r7, #12] + 800fa16: 687b ldr r3, [r7, #4] + 800fa18: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 + 800fa1c: b29b uxth r3, r3 + 800fa1e: 60fb str r3, [r7, #12] return tmpreg; - 800e770: 68fb ldr r3, [r7, #12] + 800fa20: 68fb ldr r3, [r7, #12] } - 800e772: 4618 mov r0, r3 - 800e774: 3714 adds r7, #20 - 800e776: 46bd mov sp, r7 - 800e778: f85d 7b04 ldr.w r7, [sp], #4 - 800e77c: 4770 bx lr + 800fa22: 4618 mov r0, r3 + 800fa24: 3714 adds r7, #20 + 800fa26: 46bd mov sp, r7 + 800fa28: f85d 7b04 ldr.w r7, [sp], #4 + 800fa2c: 4770 bx lr -0800e77e : +0800fa2e : * @param USBx Selected device * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { - 800e77e: b480 push {r7} - 800e780: b083 sub sp, #12 - 800e782: af00 add r7, sp, #0 - 800e784: 6078 str r0, [r7, #4] - 800e786: 6039 str r1, [r7, #0] + 800fa2e: b480 push {r7} + 800fa30: b083 sub sp, #12 + 800fa32: af00 add r7, sp, #0 + 800fa34: 6078 str r0, [r7, #4] + 800fa36: 6039 str r1, [r7, #0] UNUSED(psetup); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. */ return HAL_OK; - 800e788: 2300 movs r3, #0 + 800fa38: 2300 movs r3, #0 } - 800e78a: 4618 mov r0, r3 - 800e78c: 370c adds r7, #12 - 800e78e: 46bd mov sp, r7 - 800e790: f85d 7b04 ldr.w r7, [sp], #4 - 800e794: 4770 bx lr + 800fa3a: 4618 mov r0, r3 + 800fa3c: 370c adds r7, #12 + 800fa3e: 46bd mov sp, r7 + 800fa40: f85d 7b04 ldr.w r7, [sp], #4 + 800fa44: 4770 bx lr -0800e796 : +0800fa46 : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - 800e796: b480 push {r7} - 800e798: b08b sub sp, #44 ; 0x2c - 800e79a: af00 add r7, sp, #0 - 800e79c: 60f8 str r0, [r7, #12] - 800e79e: 60b9 str r1, [r7, #8] - 800e7a0: 4611 mov r1, r2 - 800e7a2: 461a mov r2, r3 - 800e7a4: 460b mov r3, r1 - 800e7a6: 80fb strh r3, [r7, #6] - 800e7a8: 4613 mov r3, r2 - 800e7aa: 80bb strh r3, [r7, #4] + 800fa46: b480 push {r7} + 800fa48: b08b sub sp, #44 ; 0x2c + 800fa4a: af00 add r7, sp, #0 + 800fa4c: 60f8 str r0, [r7, #12] + 800fa4e: 60b9 str r1, [r7, #8] + 800fa50: 4611 mov r1, r2 + 800fa52: 461a mov r2, r3 + 800fa54: 460b mov r3, r1 + 800fa56: 80fb strh r3, [r7, #6] + 800fa58: 4613 mov r3, r2 + 800fa5a: 80bb strh r3, [r7, #4] uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; - 800e7ac: 88bb ldrh r3, [r7, #4] - 800e7ae: 3301 adds r3, #1 - 800e7b0: 085b lsrs r3, r3, #1 - 800e7b2: 61bb str r3, [r7, #24] + 800fa5c: 88bb ldrh r3, [r7, #4] + 800fa5e: 3301 adds r3, #1 + 800fa60: 085b lsrs r3, r3, #1 + 800fa62: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; - 800e7b4: 68fb ldr r3, [r7, #12] - 800e7b6: 617b str r3, [r7, #20] + 800fa64: 68fb ldr r3, [r7, #12] + 800fa66: 617b str r3, [r7, #20] uint32_t count; uint16_t WrVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; - 800e7b8: 68bb ldr r3, [r7, #8] - 800e7ba: 61fb str r3, [r7, #28] + 800fa68: 68bb ldr r3, [r7, #8] + 800fa6a: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - 800e7bc: 88fa ldrh r2, [r7, #6] - 800e7be: 697b ldr r3, [r7, #20] - 800e7c0: 4413 add r3, r2 - 800e7c2: f503 6380 add.w r3, r3, #1024 ; 0x400 - 800e7c6: 623b str r3, [r7, #32] + 800fa6c: 88fa ldrh r2, [r7, #6] + 800fa6e: 697b ldr r3, [r7, #20] + 800fa70: 4413 add r3, r2 + 800fa72: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800fa76: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) - 800e7c8: 69bb ldr r3, [r7, #24] - 800e7ca: 627b str r3, [r7, #36] ; 0x24 - 800e7cc: e01b b.n 800e806 + 800fa78: 69bb ldr r3, [r7, #24] + 800fa7a: 627b str r3, [r7, #36] ; 0x24 + 800fa7c: e01b b.n 800fab6 { WrVal = pBuf[0]; - 800e7ce: 69fb ldr r3, [r7, #28] - 800e7d0: 781b ldrb r3, [r3, #0] - 800e7d2: 827b strh r3, [r7, #18] + 800fa7e: 69fb ldr r3, [r7, #28] + 800fa80: 781b ldrb r3, [r3, #0] + 800fa82: 827b strh r3, [r7, #18] WrVal |= (uint16_t)pBuf[1] << 8; - 800e7d4: 69fb ldr r3, [r7, #28] - 800e7d6: 3301 adds r3, #1 - 800e7d8: 781b ldrb r3, [r3, #0] - 800e7da: 021b lsls r3, r3, #8 - 800e7dc: b21a sxth r2, r3 - 800e7de: f9b7 3012 ldrsh.w r3, [r7, #18] - 800e7e2: 4313 orrs r3, r2 - 800e7e4: b21b sxth r3, r3 - 800e7e6: 827b strh r3, [r7, #18] + 800fa84: 69fb ldr r3, [r7, #28] + 800fa86: 3301 adds r3, #1 + 800fa88: 781b ldrb r3, [r3, #0] + 800fa8a: 021b lsls r3, r3, #8 + 800fa8c: b21a sxth r2, r3 + 800fa8e: f9b7 3012 ldrsh.w r3, [r7, #18] + 800fa92: 4313 orrs r3, r2 + 800fa94: b21b sxth r3, r3 + 800fa96: 827b strh r3, [r7, #18] *pdwVal = (WrVal & 0xFFFFU); - 800e7e8: 6a3b ldr r3, [r7, #32] - 800e7ea: 8a7a ldrh r2, [r7, #18] - 800e7ec: 801a strh r2, [r3, #0] + 800fa98: 6a3b ldr r3, [r7, #32] + 800fa9a: 8a7a ldrh r2, [r7, #18] + 800fa9c: 801a strh r2, [r3, #0] pdwVal++; - 800e7ee: 6a3b ldr r3, [r7, #32] - 800e7f0: 3302 adds r3, #2 - 800e7f2: 623b str r3, [r7, #32] + 800fa9e: 6a3b ldr r3, [r7, #32] + 800faa0: 3302 adds r3, #2 + 800faa2: 623b str r3, [r7, #32] #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ pBuf++; - 800e7f4: 69fb ldr r3, [r7, #28] - 800e7f6: 3301 adds r3, #1 - 800e7f8: 61fb str r3, [r7, #28] + 800faa4: 69fb ldr r3, [r7, #28] + 800faa6: 3301 adds r3, #1 + 800faa8: 61fb str r3, [r7, #28] pBuf++; - 800e7fa: 69fb ldr r3, [r7, #28] - 800e7fc: 3301 adds r3, #1 - 800e7fe: 61fb str r3, [r7, #28] + 800faaa: 69fb ldr r3, [r7, #28] + 800faac: 3301 adds r3, #1 + 800faae: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) - 800e800: 6a7b ldr r3, [r7, #36] ; 0x24 - 800e802: 3b01 subs r3, #1 - 800e804: 627b str r3, [r7, #36] ; 0x24 - 800e806: 6a7b ldr r3, [r7, #36] ; 0x24 - 800e808: 2b00 cmp r3, #0 - 800e80a: d1e0 bne.n 800e7ce - } -} - 800e80c: bf00 nop - 800e80e: bf00 nop - 800e810: 372c adds r7, #44 ; 0x2c - 800e812: 46bd mov sp, r7 - 800e814: f85d 7b04 ldr.w r7, [sp], #4 - 800e818: 4770 bx lr - -0800e81a : + 800fab0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fab2: 3b01 subs r3, #1 + 800fab4: 627b str r3, [r7, #36] ; 0x24 + 800fab6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fab8: 2b00 cmp r3, #0 + 800faba: d1e0 bne.n 800fa7e + } +} + 800fabc: bf00 nop + 800fabe: bf00 nop + 800fac0: 372c adds r7, #44 ; 0x2c + 800fac2: 46bd mov sp, r7 + 800fac4: f85d 7b04 ldr.w r7, [sp], #4 + 800fac8: 4770 bx lr + +0800faca : * @param wPMABufAddr address into PMA. * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - 800e81a: b480 push {r7} - 800e81c: b08b sub sp, #44 ; 0x2c - 800e81e: af00 add r7, sp, #0 - 800e820: 60f8 str r0, [r7, #12] - 800e822: 60b9 str r1, [r7, #8] - 800e824: 4611 mov r1, r2 - 800e826: 461a mov r2, r3 - 800e828: 460b mov r3, r1 - 800e82a: 80fb strh r3, [r7, #6] - 800e82c: 4613 mov r3, r2 - 800e82e: 80bb strh r3, [r7, #4] + 800faca: b480 push {r7} + 800facc: b08b sub sp, #44 ; 0x2c + 800face: af00 add r7, sp, #0 + 800fad0: 60f8 str r0, [r7, #12] + 800fad2: 60b9 str r1, [r7, #8] + 800fad4: 4611 mov r1, r2 + 800fad6: 461a mov r2, r3 + 800fad8: 460b mov r3, r1 + 800fada: 80fb strh r3, [r7, #6] + 800fadc: 4613 mov r3, r2 + 800fade: 80bb strh r3, [r7, #4] uint32_t n = (uint32_t)wNBytes >> 1; - 800e830: 88bb ldrh r3, [r7, #4] - 800e832: 085b lsrs r3, r3, #1 - 800e834: b29b uxth r3, r3 - 800e836: 61bb str r3, [r7, #24] + 800fae0: 88bb ldrh r3, [r7, #4] + 800fae2: 085b lsrs r3, r3, #1 + 800fae4: b29b uxth r3, r3 + 800fae6: 61bb str r3, [r7, #24] uint32_t BaseAddr = (uint32_t)USBx; - 800e838: 68fb ldr r3, [r7, #12] - 800e83a: 617b str r3, [r7, #20] + 800fae8: 68fb ldr r3, [r7, #12] + 800faea: 617b str r3, [r7, #20] uint32_t count; uint32_t RdVal; __IO uint16_t *pdwVal; uint8_t *pBuf = pbUsrBuf; - 800e83c: 68bb ldr r3, [r7, #8] - 800e83e: 61fb str r3, [r7, #28] + 800faec: 68bb ldr r3, [r7, #8] + 800faee: 61fb str r3, [r7, #28] pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); - 800e840: 88fa ldrh r2, [r7, #6] - 800e842: 697b ldr r3, [r7, #20] - 800e844: 4413 add r3, r2 - 800e846: f503 6380 add.w r3, r3, #1024 ; 0x400 - 800e84a: 623b str r3, [r7, #32] + 800faf0: 88fa ldrh r2, [r7, #6] + 800faf2: 697b ldr r3, [r7, #20] + 800faf4: 4413 add r3, r2 + 800faf6: f503 6380 add.w r3, r3, #1024 ; 0x400 + 800fafa: 623b str r3, [r7, #32] for (count = n; count != 0U; count--) - 800e84c: 69bb ldr r3, [r7, #24] - 800e84e: 627b str r3, [r7, #36] ; 0x24 - 800e850: e018 b.n 800e884 + 800fafc: 69bb ldr r3, [r7, #24] + 800fafe: 627b str r3, [r7, #36] ; 0x24 + 800fb00: e018 b.n 800fb34 { RdVal = *(__IO uint16_t *)pdwVal; - 800e852: 6a3b ldr r3, [r7, #32] - 800e854: 881b ldrh r3, [r3, #0] - 800e856: b29b uxth r3, r3 - 800e858: 613b str r3, [r7, #16] + 800fb02: 6a3b ldr r3, [r7, #32] + 800fb04: 881b ldrh r3, [r3, #0] + 800fb06: b29b uxth r3, r3 + 800fb08: 613b str r3, [r7, #16] pdwVal++; - 800e85a: 6a3b ldr r3, [r7, #32] - 800e85c: 3302 adds r3, #2 - 800e85e: 623b str r3, [r7, #32] + 800fb0a: 6a3b ldr r3, [r7, #32] + 800fb0c: 3302 adds r3, #2 + 800fb0e: 623b str r3, [r7, #32] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); - 800e860: 693b ldr r3, [r7, #16] - 800e862: b2da uxtb r2, r3 - 800e864: 69fb ldr r3, [r7, #28] - 800e866: 701a strb r2, [r3, #0] + 800fb10: 693b ldr r3, [r7, #16] + 800fb12: b2da uxtb r2, r3 + 800fb14: 69fb ldr r3, [r7, #28] + 800fb16: 701a strb r2, [r3, #0] pBuf++; - 800e868: 69fb ldr r3, [r7, #28] - 800e86a: 3301 adds r3, #1 - 800e86c: 61fb str r3, [r7, #28] + 800fb18: 69fb ldr r3, [r7, #28] + 800fb1a: 3301 adds r3, #1 + 800fb1c: 61fb str r3, [r7, #28] *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); - 800e86e: 693b ldr r3, [r7, #16] - 800e870: 0a1b lsrs r3, r3, #8 - 800e872: b2da uxtb r2, r3 - 800e874: 69fb ldr r3, [r7, #28] - 800e876: 701a strb r2, [r3, #0] + 800fb1e: 693b ldr r3, [r7, #16] + 800fb20: 0a1b lsrs r3, r3, #8 + 800fb22: b2da uxtb r2, r3 + 800fb24: 69fb ldr r3, [r7, #28] + 800fb26: 701a strb r2, [r3, #0] pBuf++; - 800e878: 69fb ldr r3, [r7, #28] - 800e87a: 3301 adds r3, #1 - 800e87c: 61fb str r3, [r7, #28] + 800fb28: 69fb ldr r3, [r7, #28] + 800fb2a: 3301 adds r3, #1 + 800fb2c: 61fb str r3, [r7, #28] for (count = n; count != 0U; count--) - 800e87e: 6a7b ldr r3, [r7, #36] ; 0x24 - 800e880: 3b01 subs r3, #1 - 800e882: 627b str r3, [r7, #36] ; 0x24 - 800e884: 6a7b ldr r3, [r7, #36] ; 0x24 - 800e886: 2b00 cmp r3, #0 - 800e888: d1e3 bne.n 800e852 + 800fb2e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fb30: 3b01 subs r3, #1 + 800fb32: 627b str r3, [r7, #36] ; 0x24 + 800fb34: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fb36: 2b00 cmp r3, #0 + 800fb38: d1e3 bne.n 800fb02 #if PMA_ACCESS > 1U pdwVal++; #endif /* PMA_ACCESS */ } if ((wNBytes % 2U) != 0U) - 800e88a: 88bb ldrh r3, [r7, #4] - 800e88c: f003 0301 and.w r3, r3, #1 - 800e890: b29b uxth r3, r3 - 800e892: 2b00 cmp r3, #0 - 800e894: d007 beq.n 800e8a6 + 800fb3a: 88bb ldrh r3, [r7, #4] + 800fb3c: f003 0301 and.w r3, r3, #1 + 800fb40: b29b uxth r3, r3 + 800fb42: 2b00 cmp r3, #0 + 800fb44: d007 beq.n 800fb56 { RdVal = *pdwVal; - 800e896: 6a3b ldr r3, [r7, #32] - 800e898: 881b ldrh r3, [r3, #0] - 800e89a: b29b uxth r3, r3 - 800e89c: 613b str r3, [r7, #16] + 800fb46: 6a3b ldr r3, [r7, #32] + 800fb48: 881b ldrh r3, [r3, #0] + 800fb4a: b29b uxth r3, r3 + 800fb4c: 613b str r3, [r7, #16] *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); - 800e89e: 693b ldr r3, [r7, #16] - 800e8a0: b2da uxtb r2, r3 - 800e8a2: 69fb ldr r3, [r7, #28] - 800e8a4: 701a strb r2, [r3, #0] + 800fb4e: 693b ldr r3, [r7, #16] + 800fb50: b2da uxtb r2, r3 + 800fb52: 69fb ldr r3, [r7, #28] + 800fb54: 701a strb r2, [r3, #0] } } - 800e8a6: bf00 nop - 800e8a8: 372c adds r7, #44 ; 0x2c - 800e8aa: 46bd mov sp, r7 - 800e8ac: f85d 7b04 ldr.w r7, [sp], #4 - 800e8b0: 4770 bx lr + 800fb56: bf00 nop + 800fb58: 372c adds r7, #44 ; 0x2c + 800fb5a: 46bd mov sp, r7 + 800fb5c: f85d 7b04 ldr.w r7, [sp], #4 + 800fb60: 4770 bx lr ... -0800e8b4 : +0800fb64 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - 800e8b4: b580 push {r7, lr} - 800e8b6: b084 sub sp, #16 - 800e8b8: af00 add r7, sp, #0 - 800e8ba: 6078 str r0, [r7, #4] - 800e8bc: 460b mov r3, r1 - 800e8be: 70fb strb r3, [r7, #3] + 800fb64: b580 push {r7, lr} + 800fb66: b084 sub sp, #16 + 800fb68: af00 add r7, sp, #0 + 800fb6a: 6078 str r0, [r7, #4] + 800fb6c: 460b mov r3, r1 + 800fb6e: 70fb strb r3, [r7, #3] UNUSED(cfgidx); + USBD_CDC_HandleTypeDef *hcdc; - USBD_HID_HandleTypeDef *hhid; + hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + 800fb70: f44f 7007 mov.w r0, #540 ; 0x21c + 800fb74: f003 fa14 bl 8012fa0 + 800fb78: 60f8 str r0, [r7, #12] - hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); - 800e8c0: 2010 movs r0, #16 - 800e8c2: f002 f919 bl 8010af8 - 800e8c6: 60f8 str r0, [r7, #12] - - if (hhid == NULL) - 800e8c8: 68fb ldr r3, [r7, #12] - 800e8ca: 2b00 cmp r3, #0 - 800e8cc: d109 bne.n 800e8e2 + if (hcdc == NULL) + 800fb7a: 68fb ldr r3, [r7, #12] + 800fb7c: 2b00 cmp r3, #0 + 800fb7e: d109 bne.n 800fb94 { pdev->pClassDataCmsit[pdev->classId] = NULL; - 800e8ce: 687b ldr r3, [r7, #4] - 800e8d0: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e8d4: 687b ldr r3, [r7, #4] - 800e8d6: 32b0 adds r2, #176 ; 0xb0 - 800e8d8: 2100 movs r1, #0 - 800e8da: f843 1022 str.w r1, [r3, r2, lsl #2] + 800fb80: 687b ldr r3, [r7, #4] + 800fb82: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fb86: 687b ldr r3, [r7, #4] + 800fb88: 32b0 adds r2, #176 ; 0xb0 + 800fb8a: 2100 movs r1, #0 + 800fb8c: f843 1022 str.w r1, [r3, r2, lsl #2] return (uint8_t)USBD_EMEM; - 800e8de: 2302 movs r3, #2 - 800e8e0: e048 b.n 800e974 - } - - pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; - 800e8e2: 687b ldr r3, [r7, #4] - 800e8e4: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e8e8: 687b ldr r3, [r7, #4] - 800e8ea: 32b0 adds r2, #176 ; 0xb0 - 800e8ec: 68f9 ldr r1, [r7, #12] - 800e8ee: f843 1022 str.w r1, [r3, r2, lsl #2] + 800fb90: 2302 movs r3, #2 + 800fb92: e0d4 b.n 800fd3e + } + + (void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef)); + 800fb94: f44f 7207 mov.w r2, #540 ; 0x21c + 800fb98: 2100 movs r1, #0 + 800fb9a: 68f8 ldr r0, [r7, #12] + 800fb9c: f005 f9b5 bl 8014f0a + + pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc; + 800fba0: 687b ldr r3, [r7, #4] + 800fba2: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fba6: 687b ldr r3, [r7, #4] + 800fba8: 32b0 adds r2, #176 ; 0xb0 + 800fbaa: 68f9 ldr r1, [r7, #12] + 800fbac: f843 1022 str.w r1, [r3, r2, lsl #2] pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; - 800e8f2: 687b ldr r3, [r7, #4] - 800e8f4: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e8f8: 687b ldr r3, [r7, #4] - 800e8fa: 32b0 adds r2, #176 ; 0xb0 - 800e8fc: f853 2022 ldr.w r2, [r3, r2, lsl #2] - 800e900: 687b ldr r3, [r7, #4] - 800e902: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc -#ifdef USE_USBD_COMPOSITE - /* Get the Endpoints addresses allocated for this class instance */ - HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); + 800fbb0: 687b ldr r3, [r7, #4] + 800fbb2: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fbb6: 687b ldr r3, [r7, #4] + 800fbb8: 32b0 adds r2, #176 ; 0xb0 + 800fbba: f853 2022 ldr.w r2, [r3, r2, lsl #2] + 800fbbe: 687b ldr r3, [r7, #4] + 800fbc0: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc + CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ if (pdev->dev_speed == USBD_SPEED_HIGH) - 800e906: 687b ldr r3, [r7, #4] - 800e908: 7c1b ldrb r3, [r3, #16] - 800e90a: 2b00 cmp r3, #0 - 800e90c: d10d bne.n 800e92a - { - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; - 800e90e: 4b1b ldr r3, [pc, #108] ; (800e97c ) - 800e910: 781b ldrb r3, [r3, #0] - 800e912: f003 020f and.w r2, r3, #15 - 800e916: 6879 ldr r1, [r7, #4] - 800e918: 4613 mov r3, r2 - 800e91a: 009b lsls r3, r3, #2 - 800e91c: 4413 add r3, r2 - 800e91e: 009b lsls r3, r3, #2 - 800e920: 440b add r3, r1 - 800e922: 3326 adds r3, #38 ; 0x26 - 800e924: 2207 movs r2, #7 - 800e926: 801a strh r2, [r3, #0] - 800e928: e00c b.n 800e944 - } - else /* LOW and FULL-speed endpoints */ - { - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; - 800e92a: 4b14 ldr r3, [pc, #80] ; (800e97c ) - 800e92c: 781b ldrb r3, [r3, #0] - 800e92e: f003 020f and.w r2, r3, #15 - 800e932: 6879 ldr r1, [r7, #4] - 800e934: 4613 mov r3, r2 - 800e936: 009b lsls r3, r3, #2 - 800e938: 4413 add r3, r2 - 800e93a: 009b lsls r3, r3, #2 - 800e93c: 440b add r3, r1 - 800e93e: 3326 adds r3, #38 ; 0x26 - 800e940: 220a movs r2, #10 - 800e942: 801a strh r2, [r3, #0] - } - - /* Open EP IN */ - (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); - 800e944: 4b0d ldr r3, [pc, #52] ; (800e97c ) - 800e946: 7819 ldrb r1, [r3, #0] - 800e948: 2304 movs r3, #4 - 800e94a: 2203 movs r2, #3 - 800e94c: 6878 ldr r0, [r7, #4] - 800e94e: f001 fee9 bl 8010724 - pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; - 800e952: 4b0a ldr r3, [pc, #40] ; (800e97c ) - 800e954: 781b ldrb r3, [r3, #0] - 800e956: f003 020f and.w r2, r3, #15 - 800e95a: 6879 ldr r1, [r7, #4] - 800e95c: 4613 mov r3, r2 - 800e95e: 009b lsls r3, r3, #2 - 800e960: 4413 add r3, r2 - 800e962: 009b lsls r3, r3, #2 - 800e964: 440b add r3, r1 - 800e966: 3324 adds r3, #36 ; 0x24 - 800e968: 2201 movs r2, #1 - 800e96a: 801a strh r2, [r3, #0] - - hhid->state = USBD_HID_IDLE; - 800e96c: 68fb ldr r3, [r7, #12] - 800e96e: 2200 movs r2, #0 - 800e970: 731a strb r2, [r3, #12] + 800fbc4: 687b ldr r3, [r7, #4] + 800fbc6: 7c1b ldrb r3, [r3, #16] + 800fbc8: 2b00 cmp r3, #0 + 800fbca: d138 bne.n 800fc3e + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, + 800fbcc: 4b5e ldr r3, [pc, #376] ; (800fd48 ) + 800fbce: 7819 ldrb r1, [r3, #0] + 800fbd0: f44f 7300 mov.w r3, #512 ; 0x200 + 800fbd4: 2202 movs r2, #2 + 800fbd6: 6878 ldr r0, [r7, #4] + 800fbd8: f002 ffe4 bl 8012ba4 + CDC_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; + 800fbdc: 4b5a ldr r3, [pc, #360] ; (800fd48 ) + 800fbde: 781b ldrb r3, [r3, #0] + 800fbe0: f003 020f and.w r2, r3, #15 + 800fbe4: 6879 ldr r1, [r7, #4] + 800fbe6: 4613 mov r3, r2 + 800fbe8: 009b lsls r3, r3, #2 + 800fbea: 4413 add r3, r2 + 800fbec: 009b lsls r3, r3, #2 + 800fbee: 440b add r3, r1 + 800fbf0: 3324 adds r3, #36 ; 0x24 + 800fbf2: 2201 movs r2, #1 + 800fbf4: 801a strh r2, [r3, #0] + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, + 800fbf6: 4b55 ldr r3, [pc, #340] ; (800fd4c ) + 800fbf8: 7819 ldrb r1, [r3, #0] + 800fbfa: f44f 7300 mov.w r3, #512 ; 0x200 + 800fbfe: 2202 movs r2, #2 + 800fc00: 6878 ldr r0, [r7, #4] + 800fc02: f002 ffcf bl 8012ba4 + CDC_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; + 800fc06: 4b51 ldr r3, [pc, #324] ; (800fd4c ) + 800fc08: 781b ldrb r3, [r3, #0] + 800fc0a: f003 020f and.w r2, r3, #15 + 800fc0e: 6879 ldr r1, [r7, #4] + 800fc10: 4613 mov r3, r2 + 800fc12: 009b lsls r3, r3, #2 + 800fc14: 4413 add r3, r2 + 800fc16: 009b lsls r3, r3, #2 + 800fc18: 440b add r3, r1 + 800fc1a: f503 73b2 add.w r3, r3, #356 ; 0x164 + 800fc1e: 2201 movs r2, #1 + 800fc20: 801a strh r2, [r3, #0] + + /* Set bInterval for CDC CMD Endpoint */ + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL; + 800fc22: 4b4b ldr r3, [pc, #300] ; (800fd50 ) + 800fc24: 781b ldrb r3, [r3, #0] + 800fc26: f003 020f and.w r2, r3, #15 + 800fc2a: 6879 ldr r1, [r7, #4] + 800fc2c: 4613 mov r3, r2 + 800fc2e: 009b lsls r3, r3, #2 + 800fc30: 4413 add r3, r2 + 800fc32: 009b lsls r3, r3, #2 + 800fc34: 440b add r3, r1 + 800fc36: 3326 adds r3, #38 ; 0x26 + 800fc38: 2210 movs r2, #16 + 800fc3a: 801a strh r2, [r3, #0] + 800fc3c: e035 b.n 800fcaa + } + else + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, + 800fc3e: 4b42 ldr r3, [pc, #264] ; (800fd48 ) + 800fc40: 7819 ldrb r1, [r3, #0] + 800fc42: 2340 movs r3, #64 ; 0x40 + 800fc44: 2202 movs r2, #2 + 800fc46: 6878 ldr r0, [r7, #4] + 800fc48: f002 ffac bl 8012ba4 + CDC_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; + 800fc4c: 4b3e ldr r3, [pc, #248] ; (800fd48 ) + 800fc4e: 781b ldrb r3, [r3, #0] + 800fc50: f003 020f and.w r2, r3, #15 + 800fc54: 6879 ldr r1, [r7, #4] + 800fc56: 4613 mov r3, r2 + 800fc58: 009b lsls r3, r3, #2 + 800fc5a: 4413 add r3, r2 + 800fc5c: 009b lsls r3, r3, #2 + 800fc5e: 440b add r3, r1 + 800fc60: 3324 adds r3, #36 ; 0x24 + 800fc62: 2201 movs r2, #1 + 800fc64: 801a strh r2, [r3, #0] + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, + 800fc66: 4b39 ldr r3, [pc, #228] ; (800fd4c ) + 800fc68: 7819 ldrb r1, [r3, #0] + 800fc6a: 2340 movs r3, #64 ; 0x40 + 800fc6c: 2202 movs r2, #2 + 800fc6e: 6878 ldr r0, [r7, #4] + 800fc70: f002 ff98 bl 8012ba4 + CDC_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; + 800fc74: 4b35 ldr r3, [pc, #212] ; (800fd4c ) + 800fc76: 781b ldrb r3, [r3, #0] + 800fc78: f003 020f and.w r2, r3, #15 + 800fc7c: 6879 ldr r1, [r7, #4] + 800fc7e: 4613 mov r3, r2 + 800fc80: 009b lsls r3, r3, #2 + 800fc82: 4413 add r3, r2 + 800fc84: 009b lsls r3, r3, #2 + 800fc86: 440b add r3, r1 + 800fc88: f503 73b2 add.w r3, r3, #356 ; 0x164 + 800fc8c: 2201 movs r2, #1 + 800fc8e: 801a strh r2, [r3, #0] + + /* Set bInterval for CMD Endpoint */ + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL; + 800fc90: 4b2f ldr r3, [pc, #188] ; (800fd50 ) + 800fc92: 781b ldrb r3, [r3, #0] + 800fc94: f003 020f and.w r2, r3, #15 + 800fc98: 6879 ldr r1, [r7, #4] + 800fc9a: 4613 mov r3, r2 + 800fc9c: 009b lsls r3, r3, #2 + 800fc9e: 4413 add r3, r2 + 800fca0: 009b lsls r3, r3, #2 + 800fca2: 440b add r3, r1 + 800fca4: 3326 adds r3, #38 ; 0x26 + 800fca6: 2210 movs r2, #16 + 800fca8: 801a strh r2, [r3, #0] + } + + /* Open Command IN EP */ + (void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + 800fcaa: 4b29 ldr r3, [pc, #164] ; (800fd50 ) + 800fcac: 7819 ldrb r1, [r3, #0] + 800fcae: 2308 movs r3, #8 + 800fcb0: 2203 movs r2, #3 + 800fcb2: 6878 ldr r0, [r7, #4] + 800fcb4: f002 ff76 bl 8012ba4 + pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U; + 800fcb8: 4b25 ldr r3, [pc, #148] ; (800fd50 ) + 800fcba: 781b ldrb r3, [r3, #0] + 800fcbc: f003 020f and.w r2, r3, #15 + 800fcc0: 6879 ldr r1, [r7, #4] + 800fcc2: 4613 mov r3, r2 + 800fcc4: 009b lsls r3, r3, #2 + 800fcc6: 4413 add r3, r2 + 800fcc8: 009b lsls r3, r3, #2 + 800fcca: 440b add r3, r1 + 800fccc: 3324 adds r3, #36 ; 0x24 + 800fcce: 2201 movs r2, #1 + 800fcd0: 801a strh r2, [r3, #0] + + hcdc->RxBuffer = NULL; + 800fcd2: 68fb ldr r3, [r7, #12] + 800fcd4: 2200 movs r2, #0 + 800fcd6: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init(); + 800fcda: 687b ldr r3, [r7, #4] + 800fcdc: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 800fce0: 687a ldr r2, [r7, #4] + 800fce2: 33b0 adds r3, #176 ; 0xb0 + 800fce4: 009b lsls r3, r3, #2 + 800fce6: 4413 add r3, r2 + 800fce8: 685b ldr r3, [r3, #4] + 800fcea: 681b ldr r3, [r3, #0] + 800fcec: 4798 blx r3 + + /* Init Xfer states */ + hcdc->TxState = 0U; + 800fcee: 68fb ldr r3, [r7, #12] + 800fcf0: 2200 movs r2, #0 + 800fcf2: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + hcdc->RxState = 0U; + 800fcf6: 68fb ldr r3, [r7, #12] + 800fcf8: 2200 movs r2, #0 + 800fcfa: f8c3 2218 str.w r2, [r3, #536] ; 0x218 + + if (hcdc->RxBuffer == NULL) + 800fcfe: 68fb ldr r3, [r7, #12] + 800fd00: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204 + 800fd04: 2b00 cmp r3, #0 + 800fd06: d101 bne.n 800fd0c + { + return (uint8_t)USBD_EMEM; + 800fd08: 2302 movs r3, #2 + 800fd0a: e018 b.n 800fd3e + } - return (uint8_t)USBD_OK; - 800e972: 2300 movs r3, #0 -} - 800e974: 4618 mov r0, r3 - 800e976: 3710 adds r7, #16 - 800e978: 46bd mov sp, r7 - 800e97a: bd80 pop {r7, pc} - 800e97c: 200000ea .word 0x200000ea + if (pdev->dev_speed == USBD_SPEED_HIGH) + 800fd0c: 687b ldr r3, [r7, #4] + 800fd0e: 7c1b ldrb r3, [r3, #16] + 800fd10: 2b00 cmp r3, #0 + 800fd12: d10a bne.n 800fd2a + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + 800fd14: 4b0d ldr r3, [pc, #52] ; (800fd4c ) + 800fd16: 7819 ldrb r1, [r3, #0] + 800fd18: 68fb ldr r3, [r7, #12] + 800fd1a: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 800fd1e: f44f 7300 mov.w r3, #512 ; 0x200 + 800fd22: 6878 ldr r0, [r7, #4] + 800fd24: f003 f8ba bl 8012e9c + 800fd28: e008 b.n 800fd3c + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + 800fd2a: 4b08 ldr r3, [pc, #32] ; (800fd4c ) + 800fd2c: 7819 ldrb r1, [r3, #0] + 800fd2e: 68fb ldr r3, [r7, #12] + 800fd30: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 800fd34: 2340 movs r3, #64 ; 0x40 + 800fd36: 6878 ldr r0, [r7, #4] + 800fd38: f003 f8b0 bl 8012e9c + CDC_DATA_FS_OUT_PACKET_SIZE); + } -0800e980 : + return (uint8_t)USBD_OK; + 800fd3c: 2300 movs r3, #0 +} + 800fd3e: 4618 mov r0, r3 + 800fd40: 3710 adds r7, #16 + 800fd42: 46bd mov sp, r7 + 800fd44: bd80 pop {r7, pc} + 800fd46: bf00 nop + 800fd48: 200000b3 .word 0x200000b3 + 800fd4c: 200000b4 .word 0x200000b4 + 800fd50: 200000b5 .word 0x200000b5 + +0800fd54 : * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - 800e980: b580 push {r7, lr} - 800e982: b082 sub sp, #8 - 800e984: af00 add r7, sp, #0 - 800e986: 6078 str r0, [r7, #4] - 800e988: 460b mov r3, r1 - 800e98a: 70fb strb r3, [r7, #3] - /* Get the Endpoints addresses allocated for this class instance */ - HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); + 800fd54: b580 push {r7, lr} + 800fd56: b082 sub sp, #8 + 800fd58: af00 add r7, sp, #0 + 800fd5a: 6078 str r0, [r7, #4] + 800fd5c: 460b mov r3, r1 + 800fd5e: 70fb strb r3, [r7, #3] + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); #endif /* USE_USBD_COMPOSITE */ - /* Close HID EPs */ - (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); - 800e98c: 4b1f ldr r3, [pc, #124] ; (800ea0c ) - 800e98e: 781b ldrb r3, [r3, #0] - 800e990: 4619 mov r1, r3 - 800e992: 6878 ldr r0, [r7, #4] - 800e994: f001 ff04 bl 80107a0 - pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; - 800e998: 4b1c ldr r3, [pc, #112] ; (800ea0c ) - 800e99a: 781b ldrb r3, [r3, #0] - 800e99c: f003 020f and.w r2, r3, #15 - 800e9a0: 6879 ldr r1, [r7, #4] - 800e9a2: 4613 mov r3, r2 - 800e9a4: 009b lsls r3, r3, #2 - 800e9a6: 4413 add r3, r2 - 800e9a8: 009b lsls r3, r3, #2 - 800e9aa: 440b add r3, r1 - 800e9ac: 3324 adds r3, #36 ; 0x24 - 800e9ae: 2200 movs r2, #0 - 800e9b0: 801a strh r2, [r3, #0] - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; - 800e9b2: 4b16 ldr r3, [pc, #88] ; (800ea0c ) - 800e9b4: 781b ldrb r3, [r3, #0] - 800e9b6: f003 020f and.w r2, r3, #15 - 800e9ba: 6879 ldr r1, [r7, #4] - 800e9bc: 4613 mov r3, r2 - 800e9be: 009b lsls r3, r3, #2 - 800e9c0: 4413 add r3, r2 - 800e9c2: 009b lsls r3, r3, #2 - 800e9c4: 440b add r3, r1 - 800e9c6: 3326 adds r3, #38 ; 0x26 - 800e9c8: 2200 movs r2, #0 - 800e9ca: 801a strh r2, [r3, #0] - - /* Free allocated memory */ + /* Close EP IN */ + (void)USBD_LL_CloseEP(pdev, CDCInEpAdd); + 800fd60: 4b3a ldr r3, [pc, #232] ; (800fe4c ) + 800fd62: 781b ldrb r3, [r3, #0] + 800fd64: 4619 mov r1, r3 + 800fd66: 6878 ldr r0, [r7, #4] + 800fd68: f002 ff5a bl 8012c20 + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U; + 800fd6c: 4b37 ldr r3, [pc, #220] ; (800fe4c ) + 800fd6e: 781b ldrb r3, [r3, #0] + 800fd70: f003 020f and.w r2, r3, #15 + 800fd74: 6879 ldr r1, [r7, #4] + 800fd76: 4613 mov r3, r2 + 800fd78: 009b lsls r3, r3, #2 + 800fd7a: 4413 add r3, r2 + 800fd7c: 009b lsls r3, r3, #2 + 800fd7e: 440b add r3, r1 + 800fd80: 3324 adds r3, #36 ; 0x24 + 800fd82: 2200 movs r2, #0 + 800fd84: 801a strh r2, [r3, #0] + + /* Close EP OUT */ + (void)USBD_LL_CloseEP(pdev, CDCOutEpAdd); + 800fd86: 4b32 ldr r3, [pc, #200] ; (800fe50 ) + 800fd88: 781b ldrb r3, [r3, #0] + 800fd8a: 4619 mov r1, r3 + 800fd8c: 6878 ldr r0, [r7, #4] + 800fd8e: f002 ff47 bl 8012c20 + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U; + 800fd92: 4b2f ldr r3, [pc, #188] ; (800fe50 ) + 800fd94: 781b ldrb r3, [r3, #0] + 800fd96: f003 020f and.w r2, r3, #15 + 800fd9a: 6879 ldr r1, [r7, #4] + 800fd9c: 4613 mov r3, r2 + 800fd9e: 009b lsls r3, r3, #2 + 800fda0: 4413 add r3, r2 + 800fda2: 009b lsls r3, r3, #2 + 800fda4: 440b add r3, r1 + 800fda6: f503 73b2 add.w r3, r3, #356 ; 0x164 + 800fdaa: 2200 movs r2, #0 + 800fdac: 801a strh r2, [r3, #0] + + /* Close Command IN EP */ + (void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd); + 800fdae: 4b29 ldr r3, [pc, #164] ; (800fe54 ) + 800fdb0: 781b ldrb r3, [r3, #0] + 800fdb2: 4619 mov r1, r3 + 800fdb4: 6878 ldr r0, [r7, #4] + 800fdb6: f002 ff33 bl 8012c20 + pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U; + 800fdba: 4b26 ldr r3, [pc, #152] ; (800fe54 ) + 800fdbc: 781b ldrb r3, [r3, #0] + 800fdbe: f003 020f and.w r2, r3, #15 + 800fdc2: 6879 ldr r1, [r7, #4] + 800fdc4: 4613 mov r3, r2 + 800fdc6: 009b lsls r3, r3, #2 + 800fdc8: 4413 add r3, r2 + 800fdca: 009b lsls r3, r3, #2 + 800fdcc: 440b add r3, r1 + 800fdce: 3324 adds r3, #36 ; 0x24 + 800fdd0: 2200 movs r2, #0 + 800fdd2: 801a strh r2, [r3, #0] + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U; + 800fdd4: 4b1f ldr r3, [pc, #124] ; (800fe54 ) + 800fdd6: 781b ldrb r3, [r3, #0] + 800fdd8: f003 020f and.w r2, r3, #15 + 800fddc: 6879 ldr r1, [r7, #4] + 800fdde: 4613 mov r3, r2 + 800fde0: 009b lsls r3, r3, #2 + 800fde2: 4413 add r3, r2 + 800fde4: 009b lsls r3, r3, #2 + 800fde6: 440b add r3, r1 + 800fde8: 3326 adds r3, #38 ; 0x26 + 800fdea: 2200 movs r2, #0 + 800fdec: 801a strh r2, [r3, #0] + + /* DeInit physical Interface components */ if (pdev->pClassDataCmsit[pdev->classId] != NULL) - 800e9cc: 687b ldr r3, [r7, #4] - 800e9ce: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e9d2: 687b ldr r3, [r7, #4] - 800e9d4: 32b0 adds r2, #176 ; 0xb0 - 800e9d6: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800e9da: 2b00 cmp r3, #0 - 800e9dc: d011 beq.n 800ea02 - { + 800fdee: 687b ldr r3, [r7, #4] + 800fdf0: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fdf4: 687b ldr r3, [r7, #4] + 800fdf6: 32b0 adds r2, #176 ; 0xb0 + 800fdf8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800fdfc: 2b00 cmp r3, #0 + 800fdfe: d01f beq.n 800fe40 + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit(); + 800fe00: 687b ldr r3, [r7, #4] + 800fe02: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 800fe06: 687a ldr r2, [r7, #4] + 800fe08: 33b0 adds r3, #176 ; 0xb0 + 800fe0a: 009b lsls r3, r3, #2 + 800fe0c: 4413 add r3, r2 + 800fe0e: 685b ldr r3, [r3, #4] + 800fe10: 685b ldr r3, [r3, #4] + 800fe12: 4798 blx r3 (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); - 800e9de: 687b ldr r3, [r7, #4] - 800e9e0: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e9e4: 687b ldr r3, [r7, #4] - 800e9e6: 32b0 adds r2, #176 ; 0xb0 - 800e9e8: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800e9ec: 4618 mov r0, r3 - 800e9ee: f002 f891 bl 8010b14 + 800fe14: 687b ldr r3, [r7, #4] + 800fe16: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fe1a: 687b ldr r3, [r7, #4] + 800fe1c: 32b0 adds r2, #176 ; 0xb0 + 800fe1e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800fe22: 4618 mov r0, r3 + 800fe24: f003 f8ca bl 8012fbc pdev->pClassDataCmsit[pdev->classId] = NULL; - 800e9f2: 687b ldr r3, [r7, #4] - 800e9f4: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800e9f8: 687b ldr r3, [r7, #4] - 800e9fa: 32b0 adds r2, #176 ; 0xb0 - 800e9fc: 2100 movs r1, #0 - 800e9fe: f843 1022 str.w r1, [r3, r2, lsl #2] + 800fe28: 687b ldr r3, [r7, #4] + 800fe2a: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fe2e: 687b ldr r3, [r7, #4] + 800fe30: 32b0 adds r2, #176 ; 0xb0 + 800fe32: 2100 movs r1, #0 + 800fe34: f843 1022 str.w r1, [r3, r2, lsl #2] + pdev->pClassData = NULL; + 800fe38: 687b ldr r3, [r7, #4] + 800fe3a: 2200 movs r2, #0 + 800fe3c: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc } return (uint8_t)USBD_OK; - 800ea02: 2300 movs r3, #0 -} - 800ea04: 4618 mov r0, r3 - 800ea06: 3708 adds r7, #8 - 800ea08: 46bd mov sp, r7 - 800ea0a: bd80 pop {r7, pc} - 800ea0c: 200000ea .word 0x200000ea - -0800ea10 : - * @param pdev: instance + 800fe40: 2300 movs r3, #0 +} + 800fe42: 4618 mov r0, r3 + 800fe44: 3708 adds r7, #8 + 800fe46: 46bd mov sp, r7 + 800fe48: bd80 pop {r7, pc} + 800fe4a: bf00 nop + 800fe4c: 200000b3 .word 0x200000b3 + 800fe50: 200000b4 .word 0x200000b4 + 800fe54: 200000b5 .word 0x200000b5 + +0800fe58 : * @param req: usb requests * @retval status */ -static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - 800ea10: b580 push {r7, lr} - 800ea12: b086 sub sp, #24 - 800ea14: af00 add r7, sp, #0 - 800ea16: 6078 str r0, [r7, #4] - 800ea18: 6039 str r1, [r7, #0] - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; - 800ea1a: 687b ldr r3, [r7, #4] - 800ea1c: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800ea20: 687b ldr r3, [r7, #4] - 800ea22: 32b0 adds r2, #176 ; 0xb0 - 800ea24: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800ea28: 60fb str r3, [r7, #12] - USBD_StatusTypeDef ret = USBD_OK; - 800ea2a: 2300 movs r3, #0 - 800ea2c: 75fb strb r3, [r7, #23] +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + 800fe58: b580 push {r7, lr} + 800fe5a: b086 sub sp, #24 + 800fe5c: af00 add r7, sp, #0 + 800fe5e: 6078 str r0, [r7, #4] + 800fe60: 6039 str r1, [r7, #0] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 800fe62: 687b ldr r3, [r7, #4] + 800fe64: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 800fe68: 687b ldr r3, [r7, #4] + 800fe6a: 32b0 adds r2, #176 ; 0xb0 + 800fe6c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800fe70: 613b str r3, [r7, #16] uint16_t len; - uint8_t *pbuf; + uint8_t ifalt = 0U; + 800fe72: 2300 movs r3, #0 + 800fe74: 737b strb r3, [r7, #13] uint16_t status_info = 0U; - 800ea2e: 2300 movs r3, #0 - 800ea30: 817b strh r3, [r7, #10] + 800fe76: 2300 movs r3, #0 + 800fe78: 817b strh r3, [r7, #10] + USBD_StatusTypeDef ret = USBD_OK; + 800fe7a: 2300 movs r3, #0 + 800fe7c: 75fb strb r3, [r7, #23] - if (hhid == NULL) - 800ea32: 68fb ldr r3, [r7, #12] - 800ea34: 2b00 cmp r3, #0 - 800ea36: d101 bne.n 800ea3c + if (hcdc == NULL) + 800fe7e: 693b ldr r3, [r7, #16] + 800fe80: 2b00 cmp r3, #0 + 800fe82: d101 bne.n 800fe88 { return (uint8_t)USBD_FAIL; - 800ea38: 2303 movs r3, #3 - 800ea3a: e0e8 b.n 800ec0e + 800fe84: 2303 movs r3, #3 + 800fe86: e0bf b.n 8010008 } switch (req->bmRequest & USB_REQ_TYPE_MASK) - 800ea3c: 683b ldr r3, [r7, #0] - 800ea3e: 781b ldrb r3, [r3, #0] - 800ea40: f003 0360 and.w r3, r3, #96 ; 0x60 - 800ea44: 2b00 cmp r3, #0 - 800ea46: d046 beq.n 800ead6 - 800ea48: 2b20 cmp r3, #32 - 800ea4a: f040 80d8 bne.w 800ebfe - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - 800ea4e: 683b ldr r3, [r7, #0] - 800ea50: 785b ldrb r3, [r3, #1] - 800ea52: 3b02 subs r3, #2 - 800ea54: 2b09 cmp r3, #9 - 800ea56: d836 bhi.n 800eac6 - 800ea58: a201 add r2, pc, #4 ; (adr r2, 800ea60 ) - 800ea5a: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800ea5e: bf00 nop - 800ea60: 0800eab7 .word 0x0800eab7 - 800ea64: 0800ea97 .word 0x0800ea97 - 800ea68: 0800eac7 .word 0x0800eac7 - 800ea6c: 0800eac7 .word 0x0800eac7 - 800ea70: 0800eac7 .word 0x0800eac7 - 800ea74: 0800eac7 .word 0x0800eac7 - 800ea78: 0800eac7 .word 0x0800eac7 - 800ea7c: 0800eac7 .word 0x0800eac7 - 800ea80: 0800eaa5 .word 0x0800eaa5 - 800ea84: 0800ea89 .word 0x0800ea89 + 800fe88: 683b ldr r3, [r7, #0] + 800fe8a: 781b ldrb r3, [r3, #0] + 800fe8c: f003 0360 and.w r3, r3, #96 ; 0x60 + 800fe90: 2b00 cmp r3, #0 + 800fe92: d050 beq.n 800ff36 + 800fe94: 2b20 cmp r3, #32 + 800fe96: f040 80af bne.w 800fff8 + { + case USB_REQ_TYPE_CLASS: + if (req->wLength != 0U) + 800fe9a: 683b ldr r3, [r7, #0] + 800fe9c: 88db ldrh r3, [r3, #6] + 800fe9e: 2b00 cmp r3, #0 + 800fea0: d03a beq.n 800ff18 { - case USBD_HID_REQ_SET_PROTOCOL: - hhid->Protocol = (uint8_t)(req->wValue); - 800ea88: 683b ldr r3, [r7, #0] - 800ea8a: 885b ldrh r3, [r3, #2] - 800ea8c: b2db uxtb r3, r3 - 800ea8e: 461a mov r2, r3 - 800ea90: 68fb ldr r3, [r7, #12] - 800ea92: 601a str r2, [r3, #0] - break; - 800ea94: e01e b.n 800ead4 - - case USBD_HID_REQ_GET_PROTOCOL: - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); - 800ea96: 68fb ldr r3, [r7, #12] - 800ea98: 2201 movs r2, #1 - 800ea9a: 4619 mov r1, r3 - 800ea9c: 6878 ldr r0, [r7, #4] - 800ea9e: f001 fb43 bl 8010128 - break; - 800eaa2: e017 b.n 800ead4 - - case USBD_HID_REQ_SET_IDLE: - hhid->IdleState = (uint8_t)(req->wValue >> 8); - 800eaa4: 683b ldr r3, [r7, #0] - 800eaa6: 885b ldrh r3, [r3, #2] - 800eaa8: 0a1b lsrs r3, r3, #8 - 800eaaa: b29b uxth r3, r3 - 800eaac: b2db uxtb r3, r3 - 800eaae: 461a mov r2, r3 - 800eab0: 68fb ldr r3, [r7, #12] - 800eab2: 605a str r2, [r3, #4] - break; - 800eab4: e00e b.n 800ead4 - - case USBD_HID_REQ_GET_IDLE: - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); - 800eab6: 68fb ldr r3, [r7, #12] - 800eab8: 3304 adds r3, #4 - 800eaba: 2201 movs r2, #1 - 800eabc: 4619 mov r1, r3 - 800eabe: 6878 ldr r0, [r7, #4] - 800eac0: f001 fb32 bl 8010128 - break; - 800eac4: e006 b.n 800ead4 - - default: - USBD_CtlError(pdev, req); - 800eac6: 6839 ldr r1, [r7, #0] - 800eac8: 6878 ldr r0, [r7, #4] - 800eaca: f001 fabc bl 8010046 - ret = USBD_FAIL; - 800eace: 2303 movs r3, #3 - 800ead0: 75fb strb r3, [r7, #23] - break; - 800ead2: bf00 nop + if ((req->bmRequest & 0x80U) != 0U) + 800fea2: 683b ldr r3, [r7, #0] + 800fea4: 781b ldrb r3, [r3, #0] + 800fea6: b25b sxtb r3, r3 + 800fea8: 2b00 cmp r3, #0 + 800feaa: da1b bge.n 800fee4 + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + 800feac: 687b ldr r3, [r7, #4] + 800feae: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 800feb2: 687a ldr r2, [r7, #4] + 800feb4: 33b0 adds r3, #176 ; 0xb0 + 800feb6: 009b lsls r3, r3, #2 + 800feb8: 4413 add r3, r2 + 800feba: 685b ldr r3, [r3, #4] + 800febc: 689b ldr r3, [r3, #8] + 800febe: 683a ldr r2, [r7, #0] + 800fec0: 7850 ldrb r0, [r2, #1] + (uint8_t *)hcdc->data, + 800fec2: 6939 ldr r1, [r7, #16] + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + 800fec4: 683a ldr r2, [r7, #0] + 800fec6: 88d2 ldrh r2, [r2, #6] + 800fec8: 4798 blx r3 + req->wLength); + + len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); + 800feca: 683b ldr r3, [r7, #0] + 800fecc: 88db ldrh r3, [r3, #6] + 800fece: 2b07 cmp r3, #7 + 800fed0: bf28 it cs + 800fed2: 2307 movcs r3, #7 + 800fed4: 81fb strh r3, [r7, #14] + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); + 800fed6: 693b ldr r3, [r7, #16] + 800fed8: 89fa ldrh r2, [r7, #14] + 800feda: 4619 mov r1, r3 + 800fedc: 6878 ldr r0, [r7, #4] + 800fede: f001 fd21 bl 8011924 + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + (uint8_t *)req, 0U); } break; - 800ead4: e09a b.n 800ec0c + 800fee2: e090 b.n 8010006 + hcdc->CmdOpCode = req->bRequest; + 800fee4: 683b ldr r3, [r7, #0] + 800fee6: 785a ldrb r2, [r3, #1] + 800fee8: 693b ldr r3, [r7, #16] + 800feea: f883 2200 strb.w r2, [r3, #512] ; 0x200 + hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE); + 800feee: 683b ldr r3, [r7, #0] + 800fef0: 88db ldrh r3, [r3, #6] + 800fef2: 2b3f cmp r3, #63 ; 0x3f + 800fef4: d803 bhi.n 800fefe + 800fef6: 683b ldr r3, [r7, #0] + 800fef8: 88db ldrh r3, [r3, #6] + 800fefa: b2da uxtb r2, r3 + 800fefc: e000 b.n 800ff00 + 800fefe: 2240 movs r2, #64 ; 0x40 + 800ff00: 693b ldr r3, [r7, #16] + 800ff02: f883 2201 strb.w r2, [r3, #513] ; 0x201 + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength); + 800ff06: 6939 ldr r1, [r7, #16] + 800ff08: 693b ldr r3, [r7, #16] + 800ff0a: f893 3201 ldrb.w r3, [r3, #513] ; 0x201 + 800ff0e: 461a mov r2, r3 + 800ff10: 6878 ldr r0, [r7, #4] + 800ff12: f001 fd33 bl 801197c + break; + 800ff16: e076 b.n 8010006 + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + 800ff18: 687b ldr r3, [r7, #4] + 800ff1a: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 800ff1e: 687a ldr r2, [r7, #4] + 800ff20: 33b0 adds r3, #176 ; 0xb0 + 800ff22: 009b lsls r3, r3, #2 + 800ff24: 4413 add r3, r2 + 800ff26: 685b ldr r3, [r3, #4] + 800ff28: 689b ldr r3, [r3, #8] + 800ff2a: 683a ldr r2, [r7, #0] + 800ff2c: 7850 ldrb r0, [r2, #1] + 800ff2e: 2200 movs r2, #0 + 800ff30: 6839 ldr r1, [r7, #0] + 800ff32: 4798 blx r3 + break; + 800ff34: e067 b.n 8010006 + case USB_REQ_TYPE_STANDARD: switch (req->bRequest) - 800ead6: 683b ldr r3, [r7, #0] - 800ead8: 785b ldrb r3, [r3, #1] - 800eada: 2b0b cmp r3, #11 - 800eadc: f200 8086 bhi.w 800ebec - 800eae0: a201 add r2, pc, #4 ; (adr r2, 800eae8 ) - 800eae2: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800eae6: bf00 nop - 800eae8: 0800eb19 .word 0x0800eb19 - 800eaec: 0800ebfb .word 0x0800ebfb - 800eaf0: 0800ebed .word 0x0800ebed - 800eaf4: 0800ebed .word 0x0800ebed - 800eaf8: 0800ebed .word 0x0800ebed - 800eafc: 0800ebed .word 0x0800ebed - 800eb00: 0800eb43 .word 0x0800eb43 - 800eb04: 0800ebed .word 0x0800ebed - 800eb08: 0800ebed .word 0x0800ebed - 800eb0c: 0800ebed .word 0x0800ebed - 800eb10: 0800eb9b .word 0x0800eb9b - 800eb14: 0800ebc5 .word 0x0800ebc5 + 800ff36: 683b ldr r3, [r7, #0] + 800ff38: 785b ldrb r3, [r3, #1] + 800ff3a: 2b0b cmp r3, #11 + 800ff3c: d851 bhi.n 800ffe2 + 800ff3e: a201 add r2, pc, #4 ; (adr r2, 800ff44 ) + 800ff40: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ff44: 0800ff75 .word 0x0800ff75 + 800ff48: 0800fff1 .word 0x0800fff1 + 800ff4c: 0800ffe3 .word 0x0800ffe3 + 800ff50: 0800ffe3 .word 0x0800ffe3 + 800ff54: 0800ffe3 .word 0x0800ffe3 + 800ff58: 0800ffe3 .word 0x0800ffe3 + 800ff5c: 0800ffe3 .word 0x0800ffe3 + 800ff60: 0800ffe3 .word 0x0800ffe3 + 800ff64: 0800ffe3 .word 0x0800ffe3 + 800ff68: 0800ffe3 .word 0x0800ffe3 + 800ff6c: 0800ff9f .word 0x0800ff9f + 800ff70: 0800ffc9 .word 0x0800ffc9 { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800eb18: 687b ldr r3, [r7, #4] - 800eb1a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800eb1e: b2db uxtb r3, r3 - 800eb20: 2b03 cmp r3, #3 - 800eb22: d107 bne.n 800eb34 + 800ff74: 687b ldr r3, [r7, #4] + 800ff76: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 800ff7a: b2db uxtb r3, r3 + 800ff7c: 2b03 cmp r3, #3 + 800ff7e: d107 bne.n 800ff90 { (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); - 800eb24: f107 030a add.w r3, r7, #10 - 800eb28: 2202 movs r2, #2 - 800eb2a: 4619 mov r1, r3 - 800eb2c: 6878 ldr r0, [r7, #4] - 800eb2e: f001 fafb bl 8010128 + 800ff80: f107 030a add.w r3, r7, #10 + 800ff84: 2202 movs r2, #2 + 800ff86: 4619 mov r1, r3 + 800ff88: 6878 ldr r0, [r7, #4] + 800ff8a: f001 fccb bl 8011924 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; - 800eb32: e063 b.n 800ebfc - USBD_CtlError(pdev, req); - 800eb34: 6839 ldr r1, [r7, #0] - 800eb36: 6878 ldr r0, [r7, #4] - 800eb38: f001 fa85 bl 8010046 - ret = USBD_FAIL; - 800eb3c: 2303 movs r3, #3 - 800eb3e: 75fb strb r3, [r7, #23] - break; - 800eb40: e05c b.n 800ebfc - - case USB_REQ_GET_DESCRIPTOR: - if ((req->wValue >> 8) == HID_REPORT_DESC) - 800eb42: 683b ldr r3, [r7, #0] - 800eb44: 885b ldrh r3, [r3, #2] - 800eb46: 0a1b lsrs r3, r3, #8 - 800eb48: b29b uxth r3, r3 - 800eb4a: 2b22 cmp r3, #34 ; 0x22 - 800eb4c: d108 bne.n 800eb60 - { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); - 800eb4e: 683b ldr r3, [r7, #0] - 800eb50: 88db ldrh r3, [r3, #6] - 800eb52: 2b4a cmp r3, #74 ; 0x4a - 800eb54: bf28 it cs - 800eb56: 234a movcs r3, #74 ; 0x4a - 800eb58: 82bb strh r3, [r7, #20] - pbuf = HID_MOUSE_ReportDesc; - 800eb5a: 4b2f ldr r3, [pc, #188] ; (800ec18 ) - 800eb5c: 613b str r3, [r7, #16] - 800eb5e: e015 b.n 800eb8c - } - else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) - 800eb60: 683b ldr r3, [r7, #0] - 800eb62: 885b ldrh r3, [r3, #2] - 800eb64: 0a1b lsrs r3, r3, #8 - 800eb66: b29b uxth r3, r3 - 800eb68: 2b21 cmp r3, #33 ; 0x21 - 800eb6a: d108 bne.n 800eb7e - { - pbuf = USBD_HID_Desc; - 800eb6c: 4b2b ldr r3, [pc, #172] ; (800ec1c ) - 800eb6e: 613b str r3, [r7, #16] - len = MIN(USB_HID_DESC_SIZ, req->wLength); - 800eb70: 683b ldr r3, [r7, #0] - 800eb72: 88db ldrh r3, [r3, #6] - 800eb74: 2b09 cmp r3, #9 - 800eb76: bf28 it cs - 800eb78: 2309 movcs r3, #9 - 800eb7a: 82bb strh r3, [r7, #20] - 800eb7c: e006 b.n 800eb8c - } - else - { + 800ff8e: e032 b.n 800fff6 USBD_CtlError(pdev, req); - 800eb7e: 6839 ldr r1, [r7, #0] - 800eb80: 6878 ldr r0, [r7, #4] - 800eb82: f001 fa60 bl 8010046 + 800ff90: 6839 ldr r1, [r7, #0] + 800ff92: 6878 ldr r0, [r7, #4] + 800ff94: f001 fc55 bl 8011842 ret = USBD_FAIL; - 800eb86: 2303 movs r3, #3 - 800eb88: 75fb strb r3, [r7, #23] - break; - 800eb8a: e037 b.n 800ebfc - } - (void)USBD_CtlSendData(pdev, pbuf, len); - 800eb8c: 8abb ldrh r3, [r7, #20] - 800eb8e: 461a mov r2, r3 - 800eb90: 6939 ldr r1, [r7, #16] - 800eb92: 6878 ldr r0, [r7, #4] - 800eb94: f001 fac8 bl 8010128 + 800ff98: 2303 movs r3, #3 + 800ff9a: 75fb strb r3, [r7, #23] break; - 800eb98: e030 b.n 800ebfc + 800ff9c: e02b b.n 800fff6 - case USB_REQ_GET_INTERFACE : + case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800eb9a: 687b ldr r3, [r7, #4] - 800eb9c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800eba0: b2db uxtb r3, r3 - 800eba2: 2b03 cmp r3, #3 - 800eba4: d107 bne.n 800ebb6 + 800ff9e: 687b ldr r3, [r7, #4] + 800ffa0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 800ffa4: b2db uxtb r3, r3 + 800ffa6: 2b03 cmp r3, #3 + 800ffa8: d107 bne.n 800ffba { - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); - 800eba6: 68fb ldr r3, [r7, #12] - 800eba8: 3308 adds r3, #8 - 800ebaa: 2201 movs r2, #1 - 800ebac: 4619 mov r1, r3 - 800ebae: 6878 ldr r0, [r7, #4] - 800ebb0: f001 faba bl 8010128 + (void)USBD_CtlSendData(pdev, &ifalt, 1U); + 800ffaa: f107 030d add.w r3, r7, #13 + 800ffae: 2201 movs r2, #1 + 800ffb0: 4619 mov r1, r3 + 800ffb2: 6878 ldr r0, [r7, #4] + 800ffb4: f001 fcb6 bl 8011924 else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; - 800ebb4: e022 b.n 800ebfc + 800ffb8: e01d b.n 800fff6 USBD_CtlError(pdev, req); - 800ebb6: 6839 ldr r1, [r7, #0] - 800ebb8: 6878 ldr r0, [r7, #4] - 800ebba: f001 fa44 bl 8010046 + 800ffba: 6839 ldr r1, [r7, #0] + 800ffbc: 6878 ldr r0, [r7, #4] + 800ffbe: f001 fc40 bl 8011842 ret = USBD_FAIL; - 800ebbe: 2303 movs r3, #3 - 800ebc0: 75fb strb r3, [r7, #23] + 800ffc2: 2303 movs r3, #3 + 800ffc4: 75fb strb r3, [r7, #23] break; - 800ebc2: e01b b.n 800ebfc + 800ffc6: e016 b.n 800fff6 case USB_REQ_SET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800ebc4: 687b ldr r3, [r7, #4] - 800ebc6: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800ebca: b2db uxtb r3, r3 - 800ebcc: 2b03 cmp r3, #3 - 800ebce: d106 bne.n 800ebde - { - hhid->AltSetting = (uint8_t)(req->wValue); - 800ebd0: 683b ldr r3, [r7, #0] - 800ebd2: 885b ldrh r3, [r3, #2] - 800ebd4: b2db uxtb r3, r3 - 800ebd6: 461a mov r2, r3 - 800ebd8: 68fb ldr r3, [r7, #12] - 800ebda: 609a str r2, [r3, #8] - else + if (pdev->dev_state != USBD_STATE_CONFIGURED) + 800ffc8: 687b ldr r3, [r7, #4] + 800ffca: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 800ffce: b2db uxtb r3, r3 + 800ffd0: 2b03 cmp r3, #3 + 800ffd2: d00f beq.n 800fff4 { USBD_CtlError(pdev, req); + 800ffd4: 6839 ldr r1, [r7, #0] + 800ffd6: 6878 ldr r0, [r7, #4] + 800ffd8: f001 fc33 bl 8011842 ret = USBD_FAIL; + 800ffdc: 2303 movs r3, #3 + 800ffde: 75fb strb r3, [r7, #23] } break; - 800ebdc: e00e b.n 800ebfc - USBD_CtlError(pdev, req); - 800ebde: 6839 ldr r1, [r7, #0] - 800ebe0: 6878 ldr r0, [r7, #4] - 800ebe2: f001 fa30 bl 8010046 - ret = USBD_FAIL; - 800ebe6: 2303 movs r3, #3 - 800ebe8: 75fb strb r3, [r7, #23] - break; - 800ebea: e007 b.n 800ebfc + 800ffe0: e008 b.n 800fff4 case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); - 800ebec: 6839 ldr r1, [r7, #0] - 800ebee: 6878 ldr r0, [r7, #4] - 800ebf0: f001 fa29 bl 8010046 + 800ffe2: 6839 ldr r1, [r7, #0] + 800ffe4: 6878 ldr r0, [r7, #4] + 800ffe6: f001 fc2c bl 8011842 ret = USBD_FAIL; - 800ebf4: 2303 movs r3, #3 - 800ebf6: 75fb strb r3, [r7, #23] + 800ffea: 2303 movs r3, #3 + 800ffec: 75fb strb r3, [r7, #23] break; - 800ebf8: e000 b.n 800ebfc + 800ffee: e002 b.n 800fff6 break; - 800ebfa: bf00 nop + 800fff0: bf00 nop + 800fff2: e008 b.n 8010006 + break; + 800fff4: bf00 nop } break; - 800ebfc: e006 b.n 800ec0c + 800fff6: e006 b.n 8010006 default: USBD_CtlError(pdev, req); - 800ebfe: 6839 ldr r1, [r7, #0] - 800ec00: 6878 ldr r0, [r7, #4] - 800ec02: f001 fa20 bl 8010046 + 800fff8: 6839 ldr r1, [r7, #0] + 800fffa: 6878 ldr r0, [r7, #4] + 800fffc: f001 fc21 bl 8011842 ret = USBD_FAIL; - 800ec06: 2303 movs r3, #3 - 800ec08: 75fb strb r3, [r7, #23] + 8010000: 2303 movs r3, #3 + 8010002: 75fb strb r3, [r7, #23] break; - 800ec0a: bf00 nop + 8010004: bf00 nop } return (uint8_t)ret; - 800ec0c: 7dfb ldrb r3, [r7, #23] -} - 800ec0e: 4618 mov r0, r3 - 800ec10: 3718 adds r7, #24 - 800ec12: 46bd mov sp, r7 - 800ec14: bd80 pop {r7, pc} - 800ec16: bf00 nop - 800ec18: 200000a0 .word 0x200000a0 - 800ec1c: 20000088 .word 0x20000088 - -0800ec20 : - * @param speed : current device speed + 8010006: 7dfb ldrb r3, [r7, #23] +} + 8010008: 4618 mov r0, r3 + 801000a: 3718 adds r7, #24 + 801000c: 46bd mov sp, r7 + 801000e: bd80 pop {r7, pc} + +08010010 : + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + 8010010: b580 push {r7, lr} + 8010012: b084 sub sp, #16 + 8010014: af00 add r7, sp, #0 + 8010016: 6078 str r0, [r7, #4] + 8010018: 460b mov r3, r1 + 801001a: 70fb strb r3, [r7, #3] + USBD_CDC_HandleTypeDef *hcdc; + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData; + 801001c: 687b ldr r3, [r7, #4] + 801001e: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8010022: 60fb str r3, [r7, #12] + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + 8010024: 687b ldr r3, [r7, #4] + 8010026: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 801002a: 687b ldr r3, [r7, #4] + 801002c: 32b0 adds r2, #176 ; 0xb0 + 801002e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010032: 2b00 cmp r3, #0 + 8010034: d101 bne.n 801003a + { + return (uint8_t)USBD_FAIL; + 8010036: 2303 movs r3, #3 + 8010038: e065 b.n 8010106 + } + + hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 801003a: 687b ldr r3, [r7, #4] + 801003c: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 8010040: 687b ldr r3, [r7, #4] + 8010042: 32b0 adds r2, #176 ; 0xb0 + 8010044: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010048: 60bb str r3, [r7, #8] + + if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && + 801004a: 78fb ldrb r3, [r7, #3] + 801004c: f003 020f and.w r2, r3, #15 + 8010050: 6879 ldr r1, [r7, #4] + 8010052: 4613 mov r3, r2 + 8010054: 009b lsls r3, r3, #2 + 8010056: 4413 add r3, r2 + 8010058: 009b lsls r3, r3, #2 + 801005a: 440b add r3, r1 + 801005c: 3318 adds r3, #24 + 801005e: 681b ldr r3, [r3, #0] + 8010060: 2b00 cmp r3, #0 + 8010062: d02f beq.n 80100c4 + ((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U)) + 8010064: 78fb ldrb r3, [r7, #3] + 8010066: f003 020f and.w r2, r3, #15 + 801006a: 6879 ldr r1, [r7, #4] + 801006c: 4613 mov r3, r2 + 801006e: 009b lsls r3, r3, #2 + 8010070: 4413 add r3, r2 + 8010072: 009b lsls r3, r3, #2 + 8010074: 440b add r3, r1 + 8010076: 3318 adds r3, #24 + 8010078: 681a ldr r2, [r3, #0] + 801007a: 78fb ldrb r3, [r7, #3] + 801007c: f003 010f and.w r1, r3, #15 + 8010080: 68f8 ldr r0, [r7, #12] + 8010082: 460b mov r3, r1 + 8010084: 009b lsls r3, r3, #2 + 8010086: 440b add r3, r1 + 8010088: 00db lsls r3, r3, #3 + 801008a: 4403 add r3, r0 + 801008c: 3338 adds r3, #56 ; 0x38 + 801008e: 681b ldr r3, [r3, #0] + 8010090: fbb2 f1f3 udiv r1, r2, r3 + 8010094: fb01 f303 mul.w r3, r1, r3 + 8010098: 1ad3 subs r3, r2, r3 + if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && + 801009a: 2b00 cmp r3, #0 + 801009c: d112 bne.n 80100c4 + { + /* Update the packet total length */ + pdev->ep_in[epnum & 0xFU].total_length = 0U; + 801009e: 78fb ldrb r3, [r7, #3] + 80100a0: f003 020f and.w r2, r3, #15 + 80100a4: 6879 ldr r1, [r7, #4] + 80100a6: 4613 mov r3, r2 + 80100a8: 009b lsls r3, r3, #2 + 80100aa: 4413 add r3, r2 + 80100ac: 009b lsls r3, r3, #2 + 80100ae: 440b add r3, r1 + 80100b0: 3318 adds r3, #24 + 80100b2: 2200 movs r2, #0 + 80100b4: 601a str r2, [r3, #0] + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); + 80100b6: 78f9 ldrb r1, [r7, #3] + 80100b8: 2300 movs r3, #0 + 80100ba: 2200 movs r2, #0 + 80100bc: 6878 ldr r0, [r7, #4] + 80100be: f002 feb5 bl 8012e2c + 80100c2: e01f b.n 8010104 + } + else + { + hcdc->TxState = 0U; + 80100c4: 68bb ldr r3, [r7, #8] + 80100c6: 2200 movs r2, #0 + 80100c8: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + + if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL) + 80100cc: 687b ldr r3, [r7, #4] + 80100ce: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 80100d2: 687a ldr r2, [r7, #4] + 80100d4: 33b0 adds r3, #176 ; 0xb0 + 80100d6: 009b lsls r3, r3, #2 + 80100d8: 4413 add r3, r2 + 80100da: 685b ldr r3, [r3, #4] + 80100dc: 691b ldr r3, [r3, #16] + 80100de: 2b00 cmp r3, #0 + 80100e0: d010 beq.n 8010104 + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); + 80100e2: 687b ldr r3, [r7, #4] + 80100e4: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 80100e8: 687a ldr r2, [r7, #4] + 80100ea: 33b0 adds r3, #176 ; 0xb0 + 80100ec: 009b lsls r3, r3, #2 + 80100ee: 4413 add r3, r2 + 80100f0: 685b ldr r3, [r3, #4] + 80100f2: 691b ldr r3, [r3, #16] + 80100f4: 68ba ldr r2, [r7, #8] + 80100f6: f8d2 0208 ldr.w r0, [r2, #520] ; 0x208 + 80100fa: 68ba ldr r2, [r7, #8] + 80100fc: f502 7104 add.w r1, r2, #528 ; 0x210 + 8010100: 78fa ldrb r2, [r7, #3] + 8010102: 4798 blx r3 + } + } + + return (uint8_t)USBD_OK; + 8010104: 2300 movs r3, #0 +} + 8010106: 4618 mov r0, r3 + 8010108: 3710 adds r7, #16 + 801010a: 46bd mov sp, r7 + 801010c: bd80 pop {r7, pc} + +0801010e : + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + 801010e: b580 push {r7, lr} + 8010110: b084 sub sp, #16 + 8010112: af00 add r7, sp, #0 + 8010114: 6078 str r0, [r7, #4] + 8010116: 460b mov r3, r1 + 8010118: 70fb strb r3, [r7, #3] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 801011a: 687b ldr r3, [r7, #4] + 801011c: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 8010120: 687b ldr r3, [r7, #4] + 8010122: 32b0 adds r2, #176 ; 0xb0 + 8010124: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010128: 60fb str r3, [r7, #12] + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + 801012a: 687b ldr r3, [r7, #4] + 801012c: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 8010130: 687b ldr r3, [r7, #4] + 8010132: 32b0 adds r2, #176 ; 0xb0 + 8010134: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010138: 2b00 cmp r3, #0 + 801013a: d101 bne.n 8010140 + { + return (uint8_t)USBD_FAIL; + 801013c: 2303 movs r3, #3 + 801013e: e01a b.n 8010176 + } + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); + 8010140: 78fb ldrb r3, [r7, #3] + 8010142: 4619 mov r1, r3 + 8010144: 6878 ldr r0, [r7, #4] + 8010146: f002 fee1 bl 8012f0c + 801014a: 4602 mov r2, r0 + 801014c: 68fb ldr r3, [r7, #12] + 801014e: f8c3 220c str.w r2, [r3, #524] ; 0x20c + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength); + 8010152: 687b ldr r3, [r7, #4] + 8010154: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 8010158: 687a ldr r2, [r7, #4] + 801015a: 33b0 adds r3, #176 ; 0xb0 + 801015c: 009b lsls r3, r3, #2 + 801015e: 4413 add r3, r2 + 8010160: 685b ldr r3, [r3, #4] + 8010162: 68db ldr r3, [r3, #12] + 8010164: 68fa ldr r2, [r7, #12] + 8010166: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204 + 801016a: 68fa ldr r2, [r7, #12] + 801016c: f502 7203 add.w r2, r2, #524 ; 0x20c + 8010170: 4611 mov r1, r2 + 8010172: 4798 blx r3 + + return (uint8_t)USBD_OK; + 8010174: 2300 movs r3, #0 +} + 8010176: 4618 mov r0, r3 + 8010178: 3710 adds r7, #16 + 801017a: 46bd mov sp, r7 + 801017c: bd80 pop {r7, pc} + +0801017e : + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + 801017e: b580 push {r7, lr} + 8010180: b084 sub sp, #16 + 8010182: af00 add r7, sp, #0 + 8010184: 6078 str r0, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 8010186: 687b ldr r3, [r7, #4] + 8010188: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 801018c: 687b ldr r3, [r7, #4] + 801018e: 32b0 adds r2, #176 ; 0xb0 + 8010190: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010194: 60fb str r3, [r7, #12] + + if (hcdc == NULL) + 8010196: 68fb ldr r3, [r7, #12] + 8010198: 2b00 cmp r3, #0 + 801019a: d101 bne.n 80101a0 + { + return (uint8_t)USBD_FAIL; + 801019c: 2303 movs r3, #3 + 801019e: e025 b.n 80101ec + } + + if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU)) + 80101a0: 687b ldr r3, [r7, #4] + 80101a2: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 80101a6: 687a ldr r2, [r7, #4] + 80101a8: 33b0 adds r3, #176 ; 0xb0 + 80101aa: 009b lsls r3, r3, #2 + 80101ac: 4413 add r3, r2 + 80101ae: 685b ldr r3, [r3, #4] + 80101b0: 2b00 cmp r3, #0 + 80101b2: d01a beq.n 80101ea + 80101b4: 68fb ldr r3, [r7, #12] + 80101b6: f893 3200 ldrb.w r3, [r3, #512] ; 0x200 + 80101ba: 2bff cmp r3, #255 ; 0xff + 80101bc: d015 beq.n 80101ea + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, + 80101be: 687b ldr r3, [r7, #4] + 80101c0: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 80101c4: 687a ldr r2, [r7, #4] + 80101c6: 33b0 adds r3, #176 ; 0xb0 + 80101c8: 009b lsls r3, r3, #2 + 80101ca: 4413 add r3, r2 + 80101cc: 685b ldr r3, [r3, #4] + 80101ce: 689b ldr r3, [r3, #8] + 80101d0: 68fa ldr r2, [r7, #12] + 80101d2: f892 0200 ldrb.w r0, [r2, #512] ; 0x200 + (uint8_t *)hcdc->data, + 80101d6: 68f9 ldr r1, [r7, #12] + (uint16_t)hcdc->CmdLength); + 80101d8: 68fa ldr r2, [r7, #12] + 80101da: f892 2201 ldrb.w r2, [r2, #513] ; 0x201 + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, + 80101de: b292 uxth r2, r2 + 80101e0: 4798 blx r3 + hcdc->CmdOpCode = 0xFFU; + 80101e2: 68fb ldr r3, [r7, #12] + 80101e4: 22ff movs r2, #255 ; 0xff + 80101e6: f883 2200 strb.w r2, [r3, #512] ; 0x200 + } + + return (uint8_t)USBD_OK; + 80101ea: 2300 movs r3, #0 +} + 80101ec: 4618 mov r0, r3 + 80101ee: 3710 adds r7, #16 + 80101f0: 46bd mov sp, r7 + 80101f2: bd80 pop {r7, pc} + +080101f4 : + * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) -{ - 800ec20: b580 push {r7, lr} - 800ec22: b084 sub sp, #16 - 800ec24: af00 add r7, sp, #0 - 800ec26: 6078 str r0, [r7, #4] - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - 800ec28: 2181 movs r1, #129 ; 0x81 - 800ec2a: 4809 ldr r0, [pc, #36] ; (800ec50 ) - 800ec2c: f000 fba9 bl 800f382 - 800ec30: 60f8 str r0, [r7, #12] - - if (pEpDesc != NULL) - 800ec32: 68fb ldr r3, [r7, #12] - 800ec34: 2b00 cmp r3, #0 - 800ec36: d002 beq.n 800ec3e - { - pEpDesc->bInterval = HID_FS_BINTERVAL; - 800ec38: 68fb ldr r3, [r7, #12] - 800ec3a: 220a movs r2, #10 - 800ec3c: 719a strb r2, [r3, #6] - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - 800ec3e: 687b ldr r3, [r7, #4] - 800ec40: 2222 movs r2, #34 ; 0x22 - 800ec42: 801a strh r2, [r3, #0] - return USBD_HID_CfgDesc; - 800ec44: 4b02 ldr r3, [pc, #8] ; (800ec50 ) -} - 800ec46: 4618 mov r0, r3 - 800ec48: 3710 adds r7, #16 - 800ec4a: 46bd mov sp, r7 - 800ec4c: bd80 pop {r7, pc} - 800ec4e: bf00 nop - 800ec50: 20000064 .word 0x20000064 - -0800ec54 : - * @param speed : current device speed +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) +{ + 80101f4: b580 push {r7, lr} + 80101f6: b086 sub sp, #24 + 80101f8: af00 add r7, sp, #0 + 80101fa: 6078 str r0, [r7, #4] + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + 80101fc: 2182 movs r1, #130 ; 0x82 + 80101fe: 4818 ldr r0, [pc, #96] ; (8010260 ) + 8010200: f000 fcbd bl 8010b7e + 8010204: 6178 str r0, [r7, #20] + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + 8010206: 2101 movs r1, #1 + 8010208: 4815 ldr r0, [pc, #84] ; (8010260 ) + 801020a: f000 fcb8 bl 8010b7e + 801020e: 6138 str r0, [r7, #16] + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + 8010210: 2181 movs r1, #129 ; 0x81 + 8010212: 4813 ldr r0, [pc, #76] ; (8010260 ) + 8010214: f000 fcb3 bl 8010b7e + 8010218: 60f8 str r0, [r7, #12] + + if (pEpCmdDesc != NULL) + 801021a: 697b ldr r3, [r7, #20] + 801021c: 2b00 cmp r3, #0 + 801021e: d002 beq.n 8010226 + { + pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; + 8010220: 697b ldr r3, [r7, #20] + 8010222: 2210 movs r2, #16 + 8010224: 719a strb r2, [r3, #6] + } + + if (pEpOutDesc != NULL) + 8010226: 693b ldr r3, [r7, #16] + 8010228: 2b00 cmp r3, #0 + 801022a: d006 beq.n 801023a + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + 801022c: 693b ldr r3, [r7, #16] + 801022e: 2200 movs r2, #0 + 8010230: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8010234: 711a strb r2, [r3, #4] + 8010236: 2200 movs r2, #0 + 8010238: 715a strb r2, [r3, #5] + } + + if (pEpInDesc != NULL) + 801023a: 68fb ldr r3, [r7, #12] + 801023c: 2b00 cmp r3, #0 + 801023e: d006 beq.n 801024e + { + pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + 8010240: 68fb ldr r3, [r7, #12] + 8010242: 2200 movs r2, #0 + 8010244: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8010248: 711a strb r2, [r3, #4] + 801024a: 2200 movs r2, #0 + 801024c: 715a strb r2, [r3, #5] + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + 801024e: 687b ldr r3, [r7, #4] + 8010250: 2243 movs r2, #67 ; 0x43 + 8010252: 801a strh r2, [r3, #0] + return USBD_CDC_CfgDesc; + 8010254: 4b02 ldr r3, [pc, #8] ; (8010260 ) +} + 8010256: 4618 mov r0, r3 + 8010258: 3718 adds r7, #24 + 801025a: 46bd mov sp, r7 + 801025c: bd80 pop {r7, pc} + 801025e: bf00 nop + 8010260: 20000070 .word 0x20000070 + +08010264 : + * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) -{ - 800ec54: b580 push {r7, lr} - 800ec56: b084 sub sp, #16 - 800ec58: af00 add r7, sp, #0 - 800ec5a: 6078 str r0, [r7, #4] - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - 800ec5c: 2181 movs r1, #129 ; 0x81 - 800ec5e: 4809 ldr r0, [pc, #36] ; (800ec84 ) - 800ec60: f000 fb8f bl 800f382 - 800ec64: 60f8 str r0, [r7, #12] - - if (pEpDesc != NULL) - 800ec66: 68fb ldr r3, [r7, #12] - 800ec68: 2b00 cmp r3, #0 - 800ec6a: d002 beq.n 800ec72 - { - pEpDesc->bInterval = HID_HS_BINTERVAL; - 800ec6c: 68fb ldr r3, [r7, #12] - 800ec6e: 2207 movs r2, #7 - 800ec70: 719a strb r2, [r3, #6] - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - 800ec72: 687b ldr r3, [r7, #4] - 800ec74: 2222 movs r2, #34 ; 0x22 - 800ec76: 801a strh r2, [r3, #0] - return USBD_HID_CfgDesc; - 800ec78: 4b02 ldr r3, [pc, #8] ; (800ec84 ) -} - 800ec7a: 4618 mov r0, r3 - 800ec7c: 3710 adds r7, #16 - 800ec7e: 46bd mov sp, r7 - 800ec80: bd80 pop {r7, pc} - 800ec82: bf00 nop - 800ec84: 20000064 .word 0x20000064 - -0800ec88 : - * @param speed : current device speed +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) +{ + 8010264: b580 push {r7, lr} + 8010266: b086 sub sp, #24 + 8010268: af00 add r7, sp, #0 + 801026a: 6078 str r0, [r7, #4] + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + 801026c: 2182 movs r1, #130 ; 0x82 + 801026e: 4818 ldr r0, [pc, #96] ; (80102d0 ) + 8010270: f000 fc85 bl 8010b7e + 8010274: 6178 str r0, [r7, #20] + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + 8010276: 2101 movs r1, #1 + 8010278: 4815 ldr r0, [pc, #84] ; (80102d0 ) + 801027a: f000 fc80 bl 8010b7e + 801027e: 6138 str r0, [r7, #16] + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + 8010280: 2181 movs r1, #129 ; 0x81 + 8010282: 4813 ldr r0, [pc, #76] ; (80102d0 ) + 8010284: f000 fc7b bl 8010b7e + 8010288: 60f8 str r0, [r7, #12] + + if (pEpCmdDesc != NULL) + 801028a: 697b ldr r3, [r7, #20] + 801028c: 2b00 cmp r3, #0 + 801028e: d002 beq.n 8010296 + { + pEpCmdDesc->bInterval = CDC_HS_BINTERVAL; + 8010290: 697b ldr r3, [r7, #20] + 8010292: 2210 movs r2, #16 + 8010294: 719a strb r2, [r3, #6] + } + + if (pEpOutDesc != NULL) + 8010296: 693b ldr r3, [r7, #16] + 8010298: 2b00 cmp r3, #0 + 801029a: d006 beq.n 80102aa + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; + 801029c: 693b ldr r3, [r7, #16] + 801029e: 2200 movs r2, #0 + 80102a0: 711a strb r2, [r3, #4] + 80102a2: 2200 movs r2, #0 + 80102a4: f042 0202 orr.w r2, r2, #2 + 80102a8: 715a strb r2, [r3, #5] + } + + if (pEpInDesc != NULL) + 80102aa: 68fb ldr r3, [r7, #12] + 80102ac: 2b00 cmp r3, #0 + 80102ae: d006 beq.n 80102be + { + pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; + 80102b0: 68fb ldr r3, [r7, #12] + 80102b2: 2200 movs r2, #0 + 80102b4: 711a strb r2, [r3, #4] + 80102b6: 2200 movs r2, #0 + 80102b8: f042 0202 orr.w r2, r2, #2 + 80102bc: 715a strb r2, [r3, #5] + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + 80102be: 687b ldr r3, [r7, #4] + 80102c0: 2243 movs r2, #67 ; 0x43 + 80102c2: 801a strh r2, [r3, #0] + return USBD_CDC_CfgDesc; + 80102c4: 4b02 ldr r3, [pc, #8] ; (80102d0 ) +} + 80102c6: 4618 mov r0, r3 + 80102c8: 3718 adds r7, #24 + 80102ca: 46bd mov sp, r7 + 80102cc: bd80 pop {r7, pc} + 80102ce: bf00 nop + 80102d0: 20000070 .word 0x20000070 + +080102d4 : + * Return configuration descriptor * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) -{ - 800ec88: b580 push {r7, lr} - 800ec8a: b084 sub sp, #16 - 800ec8c: af00 add r7, sp, #0 - 800ec8e: 6078 str r0, [r7, #4] - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - 800ec90: 2181 movs r1, #129 ; 0x81 - 800ec92: 4809 ldr r0, [pc, #36] ; (800ecb8 ) - 800ec94: f000 fb75 bl 800f382 - 800ec98: 60f8 str r0, [r7, #12] - - if (pEpDesc != NULL) - 800ec9a: 68fb ldr r3, [r7, #12] - 800ec9c: 2b00 cmp r3, #0 - 800ec9e: d002 beq.n 800eca6 - { - pEpDesc->bInterval = HID_FS_BINTERVAL; - 800eca0: 68fb ldr r3, [r7, #12] - 800eca2: 220a movs r2, #10 - 800eca4: 719a strb r2, [r3, #6] - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - 800eca6: 687b ldr r3, [r7, #4] - 800eca8: 2222 movs r2, #34 ; 0x22 - 800ecaa: 801a strh r2, [r3, #0] - return USBD_HID_CfgDesc; - 800ecac: 4b02 ldr r3, [pc, #8] ; (800ecb8 ) -} - 800ecae: 4618 mov r0, r3 - 800ecb0: 3710 adds r7, #16 - 800ecb2: 46bd mov sp, r7 - 800ecb4: bd80 pop {r7, pc} - 800ecb6: bf00 nop - 800ecb8: 20000064 .word 0x20000064 - -0800ecbc : - * @param pdev: device instance - * @param epnum: endpoint index +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) +{ + 80102d4: b580 push {r7, lr} + 80102d6: b086 sub sp, #24 + 80102d8: af00 add r7, sp, #0 + 80102da: 6078 str r0, [r7, #4] + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + 80102dc: 2182 movs r1, #130 ; 0x82 + 80102de: 4818 ldr r0, [pc, #96] ; (8010340 ) + 80102e0: f000 fc4d bl 8010b7e + 80102e4: 6178 str r0, [r7, #20] + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + 80102e6: 2101 movs r1, #1 + 80102e8: 4815 ldr r0, [pc, #84] ; (8010340 ) + 80102ea: f000 fc48 bl 8010b7e + 80102ee: 6138 str r0, [r7, #16] + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + 80102f0: 2181 movs r1, #129 ; 0x81 + 80102f2: 4813 ldr r0, [pc, #76] ; (8010340 ) + 80102f4: f000 fc43 bl 8010b7e + 80102f8: 60f8 str r0, [r7, #12] + + if (pEpCmdDesc != NULL) + 80102fa: 697b ldr r3, [r7, #20] + 80102fc: 2b00 cmp r3, #0 + 80102fe: d002 beq.n 8010306 + { + pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; + 8010300: 697b ldr r3, [r7, #20] + 8010302: 2210 movs r2, #16 + 8010304: 719a strb r2, [r3, #6] + } + + if (pEpOutDesc != NULL) + 8010306: 693b ldr r3, [r7, #16] + 8010308: 2b00 cmp r3, #0 + 801030a: d006 beq.n 801031a + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + 801030c: 693b ldr r3, [r7, #16] + 801030e: 2200 movs r2, #0 + 8010310: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8010314: 711a strb r2, [r3, #4] + 8010316: 2200 movs r2, #0 + 8010318: 715a strb r2, [r3, #5] + } + + if (pEpInDesc != NULL) + 801031a: 68fb ldr r3, [r7, #12] + 801031c: 2b00 cmp r3, #0 + 801031e: d006 beq.n 801032e + { + pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + 8010320: 68fb ldr r3, [r7, #12] + 8010322: 2200 movs r2, #0 + 8010324: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8010328: 711a strb r2, [r3, #4] + 801032a: 2200 movs r2, #0 + 801032c: 715a strb r2, [r3, #5] + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + 801032e: 687b ldr r3, [r7, #4] + 8010330: 2243 movs r2, #67 ; 0x43 + 8010332: 801a strh r2, [r3, #0] + return USBD_CDC_CfgDesc; + 8010334: 4b02 ldr r3, [pc, #8] ; (8010340 ) +} + 8010336: 4618 mov r0, r3 + 8010338: 3718 adds r7, #24 + 801033a: 46bd mov sp, r7 + 801033c: bd80 pop {r7, pc} + 801033e: bf00 nop + 8010340: 20000070 .word 0x20000070 + +08010344 : + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) +{ + 8010344: b480 push {r7} + 8010346: b083 sub sp, #12 + 8010348: af00 add r7, sp, #0 + 801034a: 6078 str r0, [r7, #4] + *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); + 801034c: 687b ldr r3, [r7, #4] + 801034e: 220a movs r2, #10 + 8010350: 801a strh r2, [r3, #0] + + return USBD_CDC_DeviceQualifierDesc; + 8010352: 4b03 ldr r3, [pc, #12] ; (8010360 ) +} + 8010354: 4618 mov r0, r3 + 8010356: 370c adds r7, #12 + 8010358: 46bd mov sp, r7 + 801035a: f85d 7b04 ldr.w r7, [sp], #4 + 801035e: 4770 bx lr + 8010360: 2000002c .word 0x2000002c + +08010364 : + * @param fops: CD Interface callback * @retval status */ -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) { - 800ecbc: b480 push {r7} - 800ecbe: b083 sub sp, #12 - 800ecc0: af00 add r7, sp, #0 - 800ecc2: 6078 str r0, [r7, #4] - 800ecc4: 460b mov r3, r1 - 800ecc6: 70fb strb r3, [r7, #3] - UNUSED(epnum); - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; - 800ecc8: 687b ldr r3, [r7, #4] - 800ecca: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800ecce: 687b ldr r3, [r7, #4] - 800ecd0: 32b0 adds r2, #176 ; 0xb0 - 800ecd2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800ecd6: 2200 movs r2, #0 - 800ecd8: 731a strb r2, [r3, #12] + 8010364: b480 push {r7} + 8010366: b083 sub sp, #12 + 8010368: af00 add r7, sp, #0 + 801036a: 6078 str r0, [r7, #4] + 801036c: 6039 str r1, [r7, #0] + if (fops == NULL) + 801036e: 683b ldr r3, [r7, #0] + 8010370: 2b00 cmp r3, #0 + 8010372: d101 bne.n 8010378 + { + return (uint8_t)USBD_FAIL; + 8010374: 2303 movs r3, #3 + 8010376: e009 b.n 801038c + } + + pdev->pUserData[pdev->classId] = fops; + 8010378: 687b ldr r3, [r7, #4] + 801037a: f8d3 32d4 ldr.w r3, [r3, #724] ; 0x2d4 + 801037e: 687a ldr r2, [r7, #4] + 8010380: 33b0 adds r3, #176 ; 0xb0 + 8010382: 009b lsls r3, r3, #2 + 8010384: 4413 add r3, r2 + 8010386: 683a ldr r2, [r7, #0] + 8010388: 605a str r2, [r3, #4] return (uint8_t)USBD_OK; - 800ecda: 2300 movs r3, #0 + 801038a: 2300 movs r3, #0 } - 800ecdc: 4618 mov r0, r3 - 800ecde: 370c adds r7, #12 - 800ece0: 46bd mov sp, r7 - 800ece2: f85d 7b04 ldr.w r7, [sp], #4 - 800ece6: 4770 bx lr + 801038c: 4618 mov r0, r3 + 801038e: 370c adds r7, #12 + 8010390: 46bd mov sp, r7 + 8010392: f85d 7b04 ldr.w r7, [sp], #4 + 8010396: 4770 bx lr -0800ece8 : - * return Device Qualifier descriptor - * @param length : pointer data length - * @retval pointer to descriptor buffer +08010398 : +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; +#else +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, uint32_t length) +{ + 8010398: b480 push {r7} + 801039a: b087 sub sp, #28 + 801039c: af00 add r7, sp, #0 + 801039e: 60f8 str r0, [r7, #12] + 80103a0: 60b9 str r1, [r7, #8] + 80103a2: 607a str r2, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 80103a4: 68fb ldr r3, [r7, #12] + 80103a6: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 80103aa: 68fb ldr r3, [r7, #12] + 80103ac: 32b0 adds r2, #176 ; 0xb0 + 80103ae: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80103b2: 617b str r3, [r7, #20] +#endif /* USE_USBD_COMPOSITE */ + + if (hcdc == NULL) + 80103b4: 697b ldr r3, [r7, #20] + 80103b6: 2b00 cmp r3, #0 + 80103b8: d101 bne.n 80103be + { + return (uint8_t)USBD_FAIL; + 80103ba: 2303 movs r3, #3 + 80103bc: e008 b.n 80103d0 + } + + hcdc->TxBuffer = pbuff; + 80103be: 697b ldr r3, [r7, #20] + 80103c0: 68ba ldr r2, [r7, #8] + 80103c2: f8c3 2208 str.w r2, [r3, #520] ; 0x208 + hcdc->TxLength = length; + 80103c6: 697b ldr r3, [r7, #20] + 80103c8: 687a ldr r2, [r7, #4] + 80103ca: f8c3 2210 str.w r2, [r3, #528] ; 0x210 + + return (uint8_t)USBD_OK; + 80103ce: 2300 movs r3, #0 +} + 80103d0: 4618 mov r0, r3 + 80103d2: 371c adds r7, #28 + 80103d4: 46bd mov sp, r7 + 80103d6: f85d 7b04 ldr.w r7, [sp], #4 + 80103da: 4770 bx lr + +080103dc : + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status */ -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) +{ + 80103dc: b480 push {r7} + 80103de: b085 sub sp, #20 + 80103e0: af00 add r7, sp, #0 + 80103e2: 6078 str r0, [r7, #4] + 80103e4: 6039 str r1, [r7, #0] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 80103e6: 687b ldr r3, [r7, #4] + 80103e8: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 80103ec: 687b ldr r3, [r7, #4] + 80103ee: 32b0 adds r2, #176 ; 0xb0 + 80103f0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80103f4: 60fb str r3, [r7, #12] + + if (hcdc == NULL) + 80103f6: 68fb ldr r3, [r7, #12] + 80103f8: 2b00 cmp r3, #0 + 80103fa: d101 bne.n 8010400 + { + return (uint8_t)USBD_FAIL; + 80103fc: 2303 movs r3, #3 + 80103fe: e004 b.n 801040a + } + + hcdc->RxBuffer = pbuff; + 8010400: 68fb ldr r3, [r7, #12] + 8010402: 683a ldr r2, [r7, #0] + 8010404: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + + return (uint8_t)USBD_OK; + 8010408: 2300 movs r3, #0 +} + 801040a: 4618 mov r0, r3 + 801040c: 3714 adds r7, #20 + 801040e: 46bd mov sp, r7 + 8010410: f85d 7b04 ldr.w r7, [sp], #4 + 8010414: 4770 bx lr + ... + +08010418 : +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId) { - 800ece8: b480 push {r7} - 800ecea: b083 sub sp, #12 - 800ecec: af00 add r7, sp, #0 - 800ecee: 6078 str r0, [r7, #4] - *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); - 800ecf0: 687b ldr r3, [r7, #4] - 800ecf2: 220a movs r2, #10 - 800ecf4: 801a strh r2, [r3, #0] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; +#else +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + 8010418: b580 push {r7, lr} + 801041a: b084 sub sp, #16 + 801041c: af00 add r7, sp, #0 + 801041e: 6078 str r0, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 8010420: 687b ldr r3, [r7, #4] + 8010422: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 8010426: 687b ldr r3, [r7, #4] + 8010428: 32b0 adds r2, #176 ; 0xb0 + 801042a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801042e: 60bb str r3, [r7, #8] +#endif /* USE_USBD_COMPOSITE */ + + USBD_StatusTypeDef ret = USBD_BUSY; + 8010430: 2301 movs r3, #1 + 8010432: 73fb strb r3, [r7, #15] +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId); +#endif /* USE_USBD_COMPOSITE */ + + if (hcdc == NULL) + 8010434: 68bb ldr r3, [r7, #8] + 8010436: 2b00 cmp r3, #0 + 8010438: d101 bne.n 801043e + { + return (uint8_t)USBD_FAIL; + 801043a: 2303 movs r3, #3 + 801043c: e025 b.n 801048a + } + + if (hcdc->TxState == 0U) + 801043e: 68bb ldr r3, [r7, #8] + 8010440: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 + 8010444: 2b00 cmp r3, #0 + 8010446: d11f bne.n 8010488 + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; + 8010448: 68bb ldr r3, [r7, #8] + 801044a: 2201 movs r2, #1 + 801044c: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + + /* Update the packet total length */ + pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength; + 8010450: 4b10 ldr r3, [pc, #64] ; (8010494 ) + 8010452: 781b ldrb r3, [r3, #0] + 8010454: f003 020f and.w r2, r3, #15 + 8010458: 68bb ldr r3, [r7, #8] + 801045a: f8d3 1210 ldr.w r1, [r3, #528] ; 0x210 + 801045e: 6878 ldr r0, [r7, #4] + 8010460: 4613 mov r3, r2 + 8010462: 009b lsls r3, r3, #2 + 8010464: 4413 add r3, r2 + 8010466: 009b lsls r3, r3, #2 + 8010468: 4403 add r3, r0 + 801046a: 3318 adds r3, #24 + 801046c: 6019 str r1, [r3, #0] + + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength); + 801046e: 4b09 ldr r3, [pc, #36] ; (8010494 ) + 8010470: 7819 ldrb r1, [r3, #0] + 8010472: 68bb ldr r3, [r7, #8] + 8010474: f8d3 2208 ldr.w r2, [r3, #520] ; 0x208 + 8010478: 68bb ldr r3, [r7, #8] + 801047a: f8d3 3210 ldr.w r3, [r3, #528] ; 0x210 + 801047e: 6878 ldr r0, [r7, #4] + 8010480: f002 fcd4 bl 8012e2c + + ret = USBD_OK; + 8010484: 2300 movs r3, #0 + 8010486: 73fb strb r3, [r7, #15] + } + + return (uint8_t)ret; + 8010488: 7bfb ldrb r3, [r7, #15] +} + 801048a: 4618 mov r0, r3 + 801048c: 3710 adds r7, #16 + 801048e: 46bd mov sp, r7 + 8010490: bd80 pop {r7, pc} + 8010492: bf00 nop + 8010494: 200000b3 .word 0x200000b3 + +08010498 : + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + 8010498: b580 push {r7, lr} + 801049a: b084 sub sp, #16 + 801049c: af00 add r7, sp, #0 + 801049e: 6078 str r0, [r7, #4] + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + 80104a0: 687b ldr r3, [r7, #4] + 80104a2: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 80104a6: 687b ldr r3, [r7, #4] + 80104a8: 32b0 adds r2, #176 ; 0xb0 + 80104aa: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80104ae: 60fb str r3, [r7, #12] +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + 80104b0: 687b ldr r3, [r7, #4] + 80104b2: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 80104b6: 687b ldr r3, [r7, #4] + 80104b8: 32b0 adds r2, #176 ; 0xb0 + 80104ba: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80104be: 2b00 cmp r3, #0 + 80104c0: d101 bne.n 80104c6 + { + return (uint8_t)USBD_FAIL; + 80104c2: 2303 movs r3, #3 + 80104c4: e018 b.n 80104f8 + } + + if (pdev->dev_speed == USBD_SPEED_HIGH) + 80104c6: 687b ldr r3, [r7, #4] + 80104c8: 7c1b ldrb r3, [r3, #16] + 80104ca: 2b00 cmp r3, #0 + 80104cc: d10a bne.n 80104e4 + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + 80104ce: 4b0c ldr r3, [pc, #48] ; (8010500 ) + 80104d0: 7819 ldrb r1, [r3, #0] + 80104d2: 68fb ldr r3, [r7, #12] + 80104d4: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80104d8: f44f 7300 mov.w r3, #512 ; 0x200 + 80104dc: 6878 ldr r0, [r7, #4] + 80104de: f002 fcdd bl 8012e9c + 80104e2: e008 b.n 80104f6 + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + 80104e4: 4b06 ldr r3, [pc, #24] ; (8010500 ) + 80104e6: 7819 ldrb r1, [r3, #0] + 80104e8: 68fb ldr r3, [r7, #12] + 80104ea: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80104ee: 2340 movs r3, #64 ; 0x40 + 80104f0: 6878 ldr r0, [r7, #4] + 80104f2: f002 fcd3 bl 8012e9c + CDC_DATA_FS_OUT_PACKET_SIZE); + } - return USBD_HID_DeviceQualifierDesc; - 800ecf6: 4b03 ldr r3, [pc, #12] ; (800ed04 ) + return (uint8_t)USBD_OK; + 80104f6: 2300 movs r3, #0 } - 800ecf8: 4618 mov r0, r3 - 800ecfa: 370c adds r7, #12 - 800ecfc: 46bd mov sp, r7 - 800ecfe: f85d 7b04 ldr.w r7, [sp], #4 - 800ed02: 4770 bx lr - 800ed04: 20000094 .word 0x20000094 + 80104f8: 4618 mov r0, r3 + 80104fa: 3710 adds r7, #16 + 80104fc: 46bd mov sp, r7 + 80104fe: bd80 pop {r7, pc} + 8010500: 200000b4 .word 0x200000b4 -0800ed08 : +08010504 : * @param id: Low level core index * @retval None */ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { - 800ed08: b580 push {r7, lr} - 800ed0a: b086 sub sp, #24 - 800ed0c: af00 add r7, sp, #0 - 800ed0e: 60f8 str r0, [r7, #12] - 800ed10: 60b9 str r1, [r7, #8] - 800ed12: 4613 mov r3, r2 - 800ed14: 71fb strb r3, [r7, #7] + 8010504: b580 push {r7, lr} + 8010506: b086 sub sp, #24 + 8010508: af00 add r7, sp, #0 + 801050a: 60f8 str r0, [r7, #12] + 801050c: 60b9 str r1, [r7, #8] + 801050e: 4613 mov r3, r2 + 8010510: 71fb strb r3, [r7, #7] USBD_StatusTypeDef ret; /* Check whether the USB Host handle is valid */ if (pdev == NULL) - 800ed16: 68fb ldr r3, [r7, #12] - 800ed18: 2b00 cmp r3, #0 - 800ed1a: d101 bne.n 800ed20 + 8010512: 68fb ldr r3, [r7, #12] + 8010514: 2b00 cmp r3, #0 + 8010516: d101 bne.n 801051c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Device handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; - 800ed1c: 2303 movs r3, #3 - 800ed1e: e01f b.n 800ed60 + 8010518: 2303 movs r3, #3 + 801051a: e01f b.n 801055c pdev->NumClasses = 0; pdev->classId = 0; } #else /* Unlink previous class*/ pdev->pClass[0] = NULL; - 800ed20: 68fb ldr r3, [r7, #12] - 800ed22: 2200 movs r2, #0 - 800ed24: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 + 801051c: 68fb ldr r3, [r7, #12] + 801051e: 2200 movs r2, #0 + 8010520: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 pdev->pUserData[0] = NULL; - 800ed28: 68fb ldr r3, [r7, #12] - 800ed2a: 2200 movs r2, #0 - 800ed2c: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4 + 8010524: 68fb ldr r3, [r7, #12] + 8010526: 2200 movs r2, #0 + 8010528: f8c3 22c4 str.w r2, [r3, #708] ; 0x2c4 #endif /* USE_USBD_COMPOSITE */ pdev->pConfDesc = NULL; - 800ed30: 68fb ldr r3, [r7, #12] - 800ed32: 2200 movs r2, #0 - 800ed34: f8c3 22d0 str.w r2, [r3, #720] ; 0x2d0 + 801052c: 68fb ldr r3, [r7, #12] + 801052e: 2200 movs r2, #0 + 8010530: f8c3 22d0 str.w r2, [r3, #720] ; 0x2d0 /* Assign USBD Descriptors */ if (pdesc != NULL) - 800ed38: 68bb ldr r3, [r7, #8] - 800ed3a: 2b00 cmp r3, #0 - 800ed3c: d003 beq.n 800ed46 + 8010534: 68bb ldr r3, [r7, #8] + 8010536: 2b00 cmp r3, #0 + 8010538: d003 beq.n 8010542 { pdev->pDesc = pdesc; - 800ed3e: 68fb ldr r3, [r7, #12] - 800ed40: 68ba ldr r2, [r7, #8] - 800ed42: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 + 801053a: 68fb ldr r3, [r7, #12] + 801053c: 68ba ldr r2, [r7, #8] + 801053e: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4 } /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; - 800ed46: 68fb ldr r3, [r7, #12] - 800ed48: 2201 movs r2, #1 - 800ed4a: f883 229c strb.w r2, [r3, #668] ; 0x29c + 8010542: 68fb ldr r3, [r7, #12] + 8010544: 2201 movs r2, #1 + 8010546: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->id = id; - 800ed4e: 68fb ldr r3, [r7, #12] - 800ed50: 79fa ldrb r2, [r7, #7] - 800ed52: 701a strb r2, [r3, #0] + 801054a: 68fb ldr r3, [r7, #12] + 801054c: 79fa ldrb r2, [r7, #7] + 801054e: 701a strb r2, [r3, #0] /* Initialize low level driver */ ret = USBD_LL_Init(pdev); - 800ed54: 68f8 ldr r0, [r7, #12] - 800ed56: f001 fc63 bl 8010620 - 800ed5a: 4603 mov r3, r0 - 800ed5c: 75fb strb r3, [r7, #23] + 8010550: 68f8 ldr r0, [r7, #12] + 8010552: f002 fa93 bl 8012a7c + 8010556: 4603 mov r3, r0 + 8010558: 75fb strb r3, [r7, #23] return ret; - 800ed5e: 7dfb ldrb r3, [r7, #23] + 801055a: 7dfb ldrb r3, [r7, #23] } - 800ed60: 4618 mov r0, r3 - 800ed62: 3718 adds r7, #24 - 800ed64: 46bd mov sp, r7 - 800ed66: bd80 pop {r7, pc} + 801055c: 4618 mov r0, r3 + 801055e: 3718 adds r7, #24 + 8010560: 46bd mov sp, r7 + 8010562: bd80 pop {r7, pc} -0800ed68 : +08010564 : * @param pDevice : Device Handle * @param pclass: Class handle * @retval USBD Status */ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { - 800ed68: b580 push {r7, lr} - 800ed6a: b084 sub sp, #16 - 800ed6c: af00 add r7, sp, #0 - 800ed6e: 6078 str r0, [r7, #4] - 800ed70: 6039 str r1, [r7, #0] + 8010564: b580 push {r7, lr} + 8010566: b084 sub sp, #16 + 8010568: af00 add r7, sp, #0 + 801056a: 6078 str r0, [r7, #4] + 801056c: 6039 str r1, [r7, #0] uint16_t len = 0U; - 800ed72: 2300 movs r3, #0 - 800ed74: 81fb strh r3, [r7, #14] + 801056e: 2300 movs r3, #0 + 8010570: 81fb strh r3, [r7, #14] if (pclass == NULL) - 800ed76: 683b ldr r3, [r7, #0] - 800ed78: 2b00 cmp r3, #0 - 800ed7a: d101 bne.n 800ed80 + 8010572: 683b ldr r3, [r7, #0] + 8010574: 2b00 cmp r3, #0 + 8010576: d101 bne.n 801057c { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif /* (USBD_DEBUG_LEVEL > 1U) */ return USBD_FAIL; - 800ed7c: 2303 movs r3, #3 - 800ed7e: e025 b.n 800edcc + 8010578: 2303 movs r3, #3 + 801057a: e025 b.n 80105c8 } /* link the class to the USB Device handle */ pdev->pClass[0] = pclass; - 800ed80: 687b ldr r3, [r7, #4] - 800ed82: 683a ldr r2, [r7, #0] - 800ed84: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 + 801057c: 687b ldr r3, [r7, #4] + 801057e: 683a ldr r2, [r7, #0] + 8010580: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8 if (pdev->pClass[pdev->classId]->GetHSConfigDescriptor != NULL) { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetHSConfigDescriptor(&len); } #else /* Default USE_USB_FS */ if (pdev->pClass[pdev->classId]->GetFSConfigDescriptor != NULL) - 800ed88: 687b ldr r3, [r7, #4] - 800ed8a: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800ed8e: 687b ldr r3, [r7, #4] - 800ed90: 32ae adds r2, #174 ; 0xae - 800ed92: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800ed96: 6adb ldr r3, [r3, #44] ; 0x2c - 800ed98: 2b00 cmp r3, #0 - 800ed9a: d00f beq.n 800edbc + 8010584: 687b ldr r3, [r7, #4] + 8010586: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 801058a: 687b ldr r3, [r7, #4] + 801058c: 32ae adds r2, #174 ; 0xae + 801058e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010592: 6adb ldr r3, [r3, #44] ; 0x2c + 8010594: 2b00 cmp r3, #0 + 8010596: d00f beq.n 80105b8 { pdev->pConfDesc = (void *)pdev->pClass[pdev->classId]->GetFSConfigDescriptor(&len); - 800ed9c: 687b ldr r3, [r7, #4] - 800ed9e: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800eda2: 687b ldr r3, [r7, #4] - 800eda4: 32ae adds r2, #174 ; 0xae - 800eda6: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800edaa: 6adb ldr r3, [r3, #44] ; 0x2c - 800edac: f107 020e add.w r2, r7, #14 - 800edb0: 4610 mov r0, r2 - 800edb2: 4798 blx r3 - 800edb4: 4602 mov r2, r0 - 800edb6: 687b ldr r3, [r7, #4] - 800edb8: f8c3 22d0 str.w r2, [r3, #720] ; 0x2d0 + 8010598: 687b ldr r3, [r7, #4] + 801059a: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 801059e: 687b ldr r3, [r7, #4] + 80105a0: 32ae adds r2, #174 ; 0xae + 80105a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80105a6: 6adb ldr r3, [r3, #44] ; 0x2c + 80105a8: f107 020e add.w r2, r7, #14 + 80105ac: 4610 mov r0, r2 + 80105ae: 4798 blx r3 + 80105b0: 4602 mov r2, r0 + 80105b2: 687b ldr r3, [r7, #4] + 80105b4: f8c3 22d0 str.w r2, [r3, #720] ; 0x2d0 } #endif /* USE_USB_FS */ /* Increment the NumClasses */ pdev->NumClasses ++; - 800edbc: 687b ldr r3, [r7, #4] - 800edbe: f8d3 32d8 ldr.w r3, [r3, #728] ; 0x2d8 - 800edc2: 1c5a adds r2, r3, #1 - 800edc4: 687b ldr r3, [r7, #4] - 800edc6: f8c3 22d8 str.w r2, [r3, #728] ; 0x2d8 + 80105b8: 687b ldr r3, [r7, #4] + 80105ba: f8d3 32d8 ldr.w r3, [r3, #728] ; 0x2d8 + 80105be: 1c5a adds r2, r3, #1 + 80105c0: 687b ldr r3, [r7, #4] + 80105c2: f8c3 22d8 str.w r2, [r3, #728] ; 0x2d8 return USBD_OK; - 800edca: 2300 movs r3, #0 + 80105c6: 2300 movs r3, #0 } - 800edcc: 4618 mov r0, r3 - 800edce: 3710 adds r7, #16 - 800edd0: 46bd mov sp, r7 - 800edd2: bd80 pop {r7, pc} + 80105c8: 4618 mov r0, r3 + 80105ca: 3710 adds r7, #16 + 80105cc: 46bd mov sp, r7 + 80105ce: bd80 pop {r7, pc} -0800edd4 : +080105d0 : * Start the USB Device Core. * @param pdev: Device Handle * @retval USBD Status */ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { - 800edd4: b580 push {r7, lr} - 800edd6: b082 sub sp, #8 - 800edd8: af00 add r7, sp, #0 - 800edda: 6078 str r0, [r7, #4] + 80105d0: b580 push {r7, lr} + 80105d2: b082 sub sp, #8 + 80105d4: af00 add r7, sp, #0 + 80105d6: 6078 str r0, [r7, #4] #ifdef USE_USBD_COMPOSITE pdev->classId = 0U; #endif /* USE_USBD_COMPOSITE */ /* Start the low level driver */ return USBD_LL_Start(pdev); - 800eddc: 6878 ldr r0, [r7, #4] - 800edde: f001 fc6f bl 80106c0 - 800ede2: 4603 mov r3, r0 + 80105d8: 6878 ldr r0, [r7, #4] + 80105da: f002 fab1 bl 8012b40 + 80105de: 4603 mov r3, r0 } - 800ede4: 4618 mov r0, r3 - 800ede6: 3708 adds r7, #8 - 800ede8: 46bd mov sp, r7 - 800edea: bd80 pop {r7, pc} + 80105e0: 4618 mov r0, r3 + 80105e2: 3708 adds r7, #8 + 80105e4: 46bd mov sp, r7 + 80105e6: bd80 pop {r7, pc} -0800edec : +080105e8 : * Launch test mode process * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { - 800edec: b480 push {r7} - 800edee: b083 sub sp, #12 - 800edf0: af00 add r7, sp, #0 - 800edf2: 6078 str r0, [r7, #4] + 80105e8: b480 push {r7} + 80105ea: b083 sub sp, #12 + 80105ec: af00 add r7, sp, #0 + 80105ee: 6078 str r0, [r7, #4] return ret; #else /* Prevent unused argument compilation warning */ UNUSED(pdev); return USBD_OK; - 800edf4: 2300 movs r3, #0 + 80105f0: 2300 movs r3, #0 #endif /* USBD_HS_TESTMODE_ENABLE */ } - 800edf6: 4618 mov r0, r3 - 800edf8: 370c adds r7, #12 - 800edfa: 46bd mov sp, r7 - 800edfc: f85d 7b04 ldr.w r7, [sp], #4 - 800ee00: 4770 bx lr + 80105f2: 4618 mov r0, r3 + 80105f4: 370c adds r7, #12 + 80105f6: 46bd mov sp, r7 + 80105f8: f85d 7b04 ldr.w r7, [sp], #4 + 80105fc: 4770 bx lr -0800ee02 : +080105fe : * @param cfgidx: configuration index * @retval status */ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - 800ee02: b580 push {r7, lr} - 800ee04: b084 sub sp, #16 - 800ee06: af00 add r7, sp, #0 - 800ee08: 6078 str r0, [r7, #4] - 800ee0a: 460b mov r3, r1 - 800ee0c: 70fb strb r3, [r7, #3] + 80105fe: b580 push {r7, lr} + 8010600: b084 sub sp, #16 + 8010602: af00 add r7, sp, #0 + 8010604: 6078 str r0, [r7, #4] + 8010606: 460b mov r3, r1 + 8010608: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; - 800ee0e: 2300 movs r3, #0 - 800ee10: 73fb strb r3, [r7, #15] + 801060a: 2300 movs r3, #0 + 801060c: 73fb strb r3, [r7, #15] } } } } #else if (pdev->pClass[0] != NULL) - 800ee12: 687b ldr r3, [r7, #4] - 800ee14: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800ee18: 2b00 cmp r3, #0 - 800ee1a: d009 beq.n 800ee30 + 801060e: 687b ldr r3, [r7, #4] + 8010610: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010614: 2b00 cmp r3, #0 + 8010616: d009 beq.n 801062c { /* Set configuration and Start the Class */ ret = (USBD_StatusTypeDef)pdev->pClass[0]->Init(pdev, cfgidx); - 800ee1c: 687b ldr r3, [r7, #4] - 800ee1e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800ee22: 681b ldr r3, [r3, #0] - 800ee24: 78fa ldrb r2, [r7, #3] - 800ee26: 4611 mov r1, r2 - 800ee28: 6878 ldr r0, [r7, #4] - 800ee2a: 4798 blx r3 - 800ee2c: 4603 mov r3, r0 - 800ee2e: 73fb strb r3, [r7, #15] + 8010618: 687b ldr r3, [r7, #4] + 801061a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 801061e: 681b ldr r3, [r3, #0] + 8010620: 78fa ldrb r2, [r7, #3] + 8010622: 4611 mov r1, r2 + 8010624: 6878 ldr r0, [r7, #4] + 8010626: 4798 blx r3 + 8010628: 4603 mov r3, r0 + 801062a: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; - 800ee30: 7bfb ldrb r3, [r7, #15] + 801062c: 7bfb ldrb r3, [r7, #15] } - 800ee32: 4618 mov r0, r3 - 800ee34: 3710 adds r7, #16 - 800ee36: 46bd mov sp, r7 - 800ee38: bd80 pop {r7, pc} + 801062e: 4618 mov r0, r3 + 8010630: 3710 adds r7, #16 + 8010632: 46bd mov sp, r7 + 8010634: bd80 pop {r7, pc} -0800ee3a : +08010636 : * @param pdev: device instance * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - 800ee3a: b580 push {r7, lr} - 800ee3c: b084 sub sp, #16 - 800ee3e: af00 add r7, sp, #0 - 800ee40: 6078 str r0, [r7, #4] - 800ee42: 460b mov r3, r1 - 800ee44: 70fb strb r3, [r7, #3] + 8010636: b580 push {r7, lr} + 8010638: b084 sub sp, #16 + 801063a: af00 add r7, sp, #0 + 801063c: 6078 str r0, [r7, #4] + 801063e: 460b mov r3, r1 + 8010640: 70fb strb r3, [r7, #3] USBD_StatusTypeDef ret = USBD_OK; - 800ee46: 2300 movs r3, #0 - 800ee48: 73fb strb r3, [r7, #15] + 8010642: 2300 movs r3, #0 + 8010644: 73fb strb r3, [r7, #15] } } } #else /* Clear configuration and De-initialize the Class process */ if (pdev->pClass[0]->DeInit(pdev, cfgidx) != 0U) - 800ee4a: 687b ldr r3, [r7, #4] - 800ee4c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800ee50: 685b ldr r3, [r3, #4] - 800ee52: 78fa ldrb r2, [r7, #3] - 800ee54: 4611 mov r1, r2 - 800ee56: 6878 ldr r0, [r7, #4] - 800ee58: 4798 blx r3 - 800ee5a: 4603 mov r3, r0 - 800ee5c: 2b00 cmp r3, #0 - 800ee5e: d001 beq.n 800ee64 + 8010646: 687b ldr r3, [r7, #4] + 8010648: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 801064c: 685b ldr r3, [r3, #4] + 801064e: 78fa ldrb r2, [r7, #3] + 8010650: 4611 mov r1, r2 + 8010652: 6878 ldr r0, [r7, #4] + 8010654: 4798 blx r3 + 8010656: 4603 mov r3, r0 + 8010658: 2b00 cmp r3, #0 + 801065a: d001 beq.n 8010660 { ret = USBD_FAIL; - 800ee60: 2303 movs r3, #3 - 800ee62: 73fb strb r3, [r7, #15] + 801065c: 2303 movs r3, #3 + 801065e: 73fb strb r3, [r7, #15] } #endif /* USE_USBD_COMPOSITE */ return ret; - 800ee64: 7bfb ldrb r3, [r7, #15] + 8010660: 7bfb ldrb r3, [r7, #15] } - 800ee66: 4618 mov r0, r3 - 800ee68: 3710 adds r7, #16 - 800ee6a: 46bd mov sp, r7 - 800ee6c: bd80 pop {r7, pc} + 8010662: 4618 mov r0, r3 + 8010664: 3710 adds r7, #16 + 8010666: 46bd mov sp, r7 + 8010668: bd80 pop {r7, pc} -0800ee6e : +0801066a : * Handle the setup stage * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { - 800ee6e: b580 push {r7, lr} - 800ee70: b084 sub sp, #16 - 800ee72: af00 add r7, sp, #0 - 800ee74: 6078 str r0, [r7, #4] - 800ee76: 6039 str r1, [r7, #0] + 801066a: b580 push {r7, lr} + 801066c: b084 sub sp, #16 + 801066e: af00 add r7, sp, #0 + 8010670: 6078 str r0, [r7, #4] + 8010672: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret; USBD_ParseSetupRequest(&pdev->request, psetup); - 800ee78: 687b ldr r3, [r7, #4] - 800ee7a: f203 23aa addw r3, r3, #682 ; 0x2aa - 800ee7e: 6839 ldr r1, [r7, #0] - 800ee80: 4618 mov r0, r3 - 800ee82: f001 f8a6 bl 800ffd2 + 8010674: 687b ldr r3, [r7, #4] + 8010676: f203 23aa addw r3, r3, #682 ; 0x2aa + 801067a: 6839 ldr r1, [r7, #0] + 801067c: 4618 mov r0, r3 + 801067e: f001 f8a6 bl 80117ce pdev->ep0_state = USBD_EP0_SETUP; - 800ee86: 687b ldr r3, [r7, #4] - 800ee88: 2201 movs r2, #1 - 800ee8a: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + 8010682: 687b ldr r3, [r7, #4] + 8010684: 2201 movs r2, #1 + 8010686: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep0_data_len = pdev->request.wLength; - 800ee8e: 687b ldr r3, [r7, #4] - 800ee90: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0 - 800ee94: 461a mov r2, r3 - 800ee96: 687b ldr r3, [r7, #4] - 800ee98: f8c3 2298 str.w r2, [r3, #664] ; 0x298 + 801068a: 687b ldr r3, [r7, #4] + 801068c: f8b3 32b0 ldrh.w r3, [r3, #688] ; 0x2b0 + 8010690: 461a mov r2, r3 + 8010692: 687b ldr r3, [r7, #4] + 8010694: f8c3 2298 str.w r2, [r3, #664] ; 0x298 switch (pdev->request.bmRequest & 0x1FU) - 800ee9c: 687b ldr r3, [r7, #4] - 800ee9e: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa - 800eea2: f003 031f and.w r3, r3, #31 - 800eea6: 2b02 cmp r3, #2 - 800eea8: d01a beq.n 800eee0 - 800eeaa: 2b02 cmp r3, #2 - 800eeac: d822 bhi.n 800eef4 - 800eeae: 2b00 cmp r3, #0 - 800eeb0: d002 beq.n 800eeb8 - 800eeb2: 2b01 cmp r3, #1 - 800eeb4: d00a beq.n 800eecc - 800eeb6: e01d b.n 800eef4 + 8010698: 687b ldr r3, [r7, #4] + 801069a: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa + 801069e: f003 031f and.w r3, r3, #31 + 80106a2: 2b02 cmp r3, #2 + 80106a4: d01a beq.n 80106dc + 80106a6: 2b02 cmp r3, #2 + 80106a8: d822 bhi.n 80106f0 + 80106aa: 2b00 cmp r3, #0 + 80106ac: d002 beq.n 80106b4 + 80106ae: 2b01 cmp r3, #1 + 80106b0: d00a beq.n 80106c8 + 80106b2: e01d b.n 80106f0 { case USB_REQ_RECIPIENT_DEVICE: ret = USBD_StdDevReq(pdev, &pdev->request); - 800eeb8: 687b ldr r3, [r7, #4] - 800eeba: f203 23aa addw r3, r3, #682 ; 0x2aa - 800eebe: 4619 mov r1, r3 - 800eec0: 6878 ldr r0, [r7, #4] - 800eec2: f000 fad3 bl 800f46c - 800eec6: 4603 mov r3, r0 - 800eec8: 73fb strb r3, [r7, #15] + 80106b4: 687b ldr r3, [r7, #4] + 80106b6: f203 23aa addw r3, r3, #682 ; 0x2aa + 80106ba: 4619 mov r1, r3 + 80106bc: 6878 ldr r0, [r7, #4] + 80106be: f000 fad3 bl 8010c68 + 80106c2: 4603 mov r3, r0 + 80106c4: 73fb strb r3, [r7, #15] break; - 800eeca: e020 b.n 800ef0e + 80106c6: e020 b.n 801070a case USB_REQ_RECIPIENT_INTERFACE: ret = USBD_StdItfReq(pdev, &pdev->request); - 800eecc: 687b ldr r3, [r7, #4] - 800eece: f203 23aa addw r3, r3, #682 ; 0x2aa - 800eed2: 4619 mov r1, r3 - 800eed4: 6878 ldr r0, [r7, #4] - 800eed6: f000 fb3b bl 800f550 - 800eeda: 4603 mov r3, r0 - 800eedc: 73fb strb r3, [r7, #15] + 80106c8: 687b ldr r3, [r7, #4] + 80106ca: f203 23aa addw r3, r3, #682 ; 0x2aa + 80106ce: 4619 mov r1, r3 + 80106d0: 6878 ldr r0, [r7, #4] + 80106d2: f000 fb3b bl 8010d4c + 80106d6: 4603 mov r3, r0 + 80106d8: 73fb strb r3, [r7, #15] break; - 800eede: e016 b.n 800ef0e + 80106da: e016 b.n 801070a case USB_REQ_RECIPIENT_ENDPOINT: ret = USBD_StdEPReq(pdev, &pdev->request); - 800eee0: 687b ldr r3, [r7, #4] - 800eee2: f203 23aa addw r3, r3, #682 ; 0x2aa - 800eee6: 4619 mov r1, r3 - 800eee8: 6878 ldr r0, [r7, #4] - 800eeea: f000 fb9d bl 800f628 - 800eeee: 4603 mov r3, r0 - 800eef0: 73fb strb r3, [r7, #15] + 80106dc: 687b ldr r3, [r7, #4] + 80106de: f203 23aa addw r3, r3, #682 ; 0x2aa + 80106e2: 4619 mov r1, r3 + 80106e4: 6878 ldr r0, [r7, #4] + 80106e6: f000 fb9d bl 8010e24 + 80106ea: 4603 mov r3, r0 + 80106ec: 73fb strb r3, [r7, #15] break; - 800eef2: e00c b.n 800ef0e + 80106ee: e00c b.n 801070a default: ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); - 800eef4: 687b ldr r3, [r7, #4] - 800eef6: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa - 800eefa: f023 037f bic.w r3, r3, #127 ; 0x7f - 800eefe: b2db uxtb r3, r3 - 800ef00: 4619 mov r1, r3 - 800ef02: 6878 ldr r0, [r7, #4] - 800ef04: f001 fc82 bl 801080c - 800ef08: 4603 mov r3, r0 - 800ef0a: 73fb strb r3, [r7, #15] + 80106f0: 687b ldr r3, [r7, #4] + 80106f2: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa + 80106f6: f023 037f bic.w r3, r3, #127 ; 0x7f + 80106fa: b2db uxtb r3, r3 + 80106fc: 4619 mov r1, r3 + 80106fe: 6878 ldr r0, [r7, #4] + 8010700: f002 fac4 bl 8012c8c + 8010704: 4603 mov r3, r0 + 8010706: 73fb strb r3, [r7, #15] break; - 800ef0c: bf00 nop + 8010708: bf00 nop } return ret; - 800ef0e: 7bfb ldrb r3, [r7, #15] + 801070a: 7bfb ldrb r3, [r7, #15] } - 800ef10: 4618 mov r0, r3 - 800ef12: 3710 adds r7, #16 - 800ef14: 46bd mov sp, r7 - 800ef16: bd80 pop {r7, pc} + 801070c: 4618 mov r0, r3 + 801070e: 3710 adds r7, #16 + 8010710: 46bd mov sp, r7 + 8010712: bd80 pop {r7, pc} -0800ef18 : +08010714 : * @param pdata: data pointer * @retval status */ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { - 800ef18: b580 push {r7, lr} - 800ef1a: b086 sub sp, #24 - 800ef1c: af00 add r7, sp, #0 - 800ef1e: 60f8 str r0, [r7, #12] - 800ef20: 460b mov r3, r1 - 800ef22: 607a str r2, [r7, #4] - 800ef24: 72fb strb r3, [r7, #11] + 8010714: b580 push {r7, lr} + 8010716: b086 sub sp, #24 + 8010718: af00 add r7, sp, #0 + 801071a: 60f8 str r0, [r7, #12] + 801071c: 460b mov r3, r1 + 801071e: 607a str r2, [r7, #4] + 8010720: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret = USBD_OK; - 800ef26: 2300 movs r3, #0 - 800ef28: 75fb strb r3, [r7, #23] + 8010722: 2300 movs r3, #0 + 8010724: 75fb strb r3, [r7, #23] uint8_t idx; if (epnum == 0U) - 800ef2a: 7afb ldrb r3, [r7, #11] - 800ef2c: 2b00 cmp r3, #0 - 800ef2e: d16e bne.n 800f00e + 8010726: 7afb ldrb r3, [r7, #11] + 8010728: 2b00 cmp r3, #0 + 801072a: d16e bne.n 801080a { pep = &pdev->ep_out[0]; - 800ef30: 68fb ldr r3, [r7, #12] - 800ef32: f503 73aa add.w r3, r3, #340 ; 0x154 - 800ef36: 613b str r3, [r7, #16] + 801072c: 68fb ldr r3, [r7, #12] + 801072e: f503 73aa add.w r3, r3, #340 ; 0x154 + 8010732: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_OUT) - 800ef38: 68fb ldr r3, [r7, #12] - 800ef3a: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 - 800ef3e: 2b03 cmp r3, #3 - 800ef40: f040 8098 bne.w 800f074 + 8010734: 68fb ldr r3, [r7, #12] + 8010736: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 801073a: 2b03 cmp r3, #3 + 801073c: f040 8098 bne.w 8010870 { if (pep->rem_length > pep->maxpacket) - 800ef44: 693b ldr r3, [r7, #16] - 800ef46: 689a ldr r2, [r3, #8] - 800ef48: 693b ldr r3, [r7, #16] - 800ef4a: 68db ldr r3, [r3, #12] - 800ef4c: 429a cmp r2, r3 - 800ef4e: d913 bls.n 800ef78 + 8010740: 693b ldr r3, [r7, #16] + 8010742: 689a ldr r2, [r3, #8] + 8010744: 693b ldr r3, [r7, #16] + 8010746: 68db ldr r3, [r3, #12] + 8010748: 429a cmp r2, r3 + 801074a: d913 bls.n 8010774 { pep->rem_length -= pep->maxpacket; - 800ef50: 693b ldr r3, [r7, #16] - 800ef52: 689a ldr r2, [r3, #8] - 800ef54: 693b ldr r3, [r7, #16] - 800ef56: 68db ldr r3, [r3, #12] - 800ef58: 1ad2 subs r2, r2, r3 - 800ef5a: 693b ldr r3, [r7, #16] - 800ef5c: 609a str r2, [r3, #8] + 801074c: 693b ldr r3, [r7, #16] + 801074e: 689a ldr r2, [r3, #8] + 8010750: 693b ldr r3, [r7, #16] + 8010752: 68db ldr r3, [r3, #12] + 8010754: 1ad2 subs r2, r2, r3 + 8010756: 693b ldr r3, [r7, #16] + 8010758: 609a str r2, [r3, #8] (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); - 800ef5e: 693b ldr r3, [r7, #16] - 800ef60: 68da ldr r2, [r3, #12] - 800ef62: 693b ldr r3, [r7, #16] - 800ef64: 689b ldr r3, [r3, #8] - 800ef66: 4293 cmp r3, r2 - 800ef68: bf28 it cs - 800ef6a: 4613 movcs r3, r2 - 800ef6c: 461a mov r2, r3 - 800ef6e: 6879 ldr r1, [r7, #4] - 800ef70: 68f8 ldr r0, [r7, #12] - 800ef72: f001 f905 bl 8010180 - 800ef76: e07d b.n 800f074 + 801075a: 693b ldr r3, [r7, #16] + 801075c: 68da ldr r2, [r3, #12] + 801075e: 693b ldr r3, [r7, #16] + 8010760: 689b ldr r3, [r3, #8] + 8010762: 4293 cmp r3, r2 + 8010764: bf28 it cs + 8010766: 4613 movcs r3, r2 + 8010768: 461a mov r2, r3 + 801076a: 6879 ldr r1, [r7, #4] + 801076c: 68f8 ldr r0, [r7, #12] + 801076e: f001 f922 bl 80119b6 + 8010772: e07d b.n 8010870 } else { /* Find the class ID relative to the current request */ switch (pdev->request.bmRequest & 0x1FU) - 800ef78: 68fb ldr r3, [r7, #12] - 800ef7a: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa - 800ef7e: f003 031f and.w r3, r3, #31 - 800ef82: 2b02 cmp r3, #2 - 800ef84: d014 beq.n 800efb0 - 800ef86: 2b02 cmp r3, #2 - 800ef88: d81d bhi.n 800efc6 - 800ef8a: 2b00 cmp r3, #0 - 800ef8c: d002 beq.n 800ef94 - 800ef8e: 2b01 cmp r3, #1 - 800ef90: d003 beq.n 800ef9a - 800ef92: e018 b.n 800efc6 + 8010774: 68fb ldr r3, [r7, #12] + 8010776: f893 32aa ldrb.w r3, [r3, #682] ; 0x2aa + 801077a: f003 031f and.w r3, r3, #31 + 801077e: 2b02 cmp r3, #2 + 8010780: d014 beq.n 80107ac + 8010782: 2b02 cmp r3, #2 + 8010784: d81d bhi.n 80107c2 + 8010786: 2b00 cmp r3, #0 + 8010788: d002 beq.n 8010790 + 801078a: 2b01 cmp r3, #1 + 801078c: d003 beq.n 8010796 + 801078e: e018 b.n 80107c2 { case USB_REQ_RECIPIENT_DEVICE: /* Device requests must be managed by the first instantiated class (or duplicated by all classes for simplicity) */ idx = 0U; - 800ef94: 2300 movs r3, #0 - 800ef96: 75bb strb r3, [r7, #22] + 8010790: 2300 movs r3, #0 + 8010792: 75bb strb r3, [r7, #22] break; - 800ef98: e018 b.n 800efcc + 8010794: e018 b.n 80107c8 case USB_REQ_RECIPIENT_INTERFACE: idx = USBD_CoreFindIF(pdev, LOBYTE(pdev->request.wIndex)); - 800ef9a: 68fb ldr r3, [r7, #12] - 800ef9c: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae - 800efa0: b2db uxtb r3, r3 - 800efa2: 4619 mov r1, r3 - 800efa4: 68f8 ldr r0, [r7, #12] - 800efa6: f000 f9d2 bl 800f34e - 800efaa: 4603 mov r3, r0 - 800efac: 75bb strb r3, [r7, #22] + 8010796: 68fb ldr r3, [r7, #12] + 8010798: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae + 801079c: b2db uxtb r3, r3 + 801079e: 4619 mov r1, r3 + 80107a0: 68f8 ldr r0, [r7, #12] + 80107a2: f000 f9d2 bl 8010b4a + 80107a6: 4603 mov r3, r0 + 80107a8: 75bb strb r3, [r7, #22] break; - 800efae: e00d b.n 800efcc + 80107aa: e00d b.n 80107c8 case USB_REQ_RECIPIENT_ENDPOINT: idx = USBD_CoreFindEP(pdev, LOBYTE(pdev->request.wIndex)); - 800efb0: 68fb ldr r3, [r7, #12] - 800efb2: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae - 800efb6: b2db uxtb r3, r3 - 800efb8: 4619 mov r1, r3 - 800efba: 68f8 ldr r0, [r7, #12] - 800efbc: f000 f9d4 bl 800f368 - 800efc0: 4603 mov r3, r0 - 800efc2: 75bb strb r3, [r7, #22] + 80107ac: 68fb ldr r3, [r7, #12] + 80107ae: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae + 80107b2: b2db uxtb r3, r3 + 80107b4: 4619 mov r1, r3 + 80107b6: 68f8 ldr r0, [r7, #12] + 80107b8: f000 f9d4 bl 8010b64 + 80107bc: 4603 mov r3, r0 + 80107be: 75bb strb r3, [r7, #22] break; - 800efc4: e002 b.n 800efcc + 80107c0: e002 b.n 80107c8 default: /* Back to the first class in case of doubt */ idx = 0U; - 800efc6: 2300 movs r3, #0 - 800efc8: 75bb strb r3, [r7, #22] + 80107c2: 2300 movs r3, #0 + 80107c4: 75bb strb r3, [r7, #22] break; - 800efca: bf00 nop + 80107c6: bf00 nop } if (idx < USBD_MAX_SUPPORTED_CLASS) - 800efcc: 7dbb ldrb r3, [r7, #22] - 800efce: 2b00 cmp r3, #0 - 800efd0: d119 bne.n 800f006 + 80107c8: 7dbb ldrb r3, [r7, #22] + 80107ca: 2b00 cmp r3, #0 + 80107cc: d119 bne.n 8010802 { /* Setup the class ID and route the request to the relative class function */ if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800efd2: 68fb ldr r3, [r7, #12] - 800efd4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800efd8: b2db uxtb r3, r3 - 800efda: 2b03 cmp r3, #3 - 800efdc: d113 bne.n 800f006 + 80107ce: 68fb ldr r3, [r7, #12] + 80107d0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80107d4: b2db uxtb r3, r3 + 80107d6: 2b03 cmp r3, #3 + 80107d8: d113 bne.n 8010802 { if (pdev->pClass[idx]->EP0_RxReady != NULL) - 800efde: 7dba ldrb r2, [r7, #22] - 800efe0: 68fb ldr r3, [r7, #12] - 800efe2: 32ae adds r2, #174 ; 0xae - 800efe4: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800efe8: 691b ldr r3, [r3, #16] - 800efea: 2b00 cmp r3, #0 - 800efec: d00b beq.n 800f006 + 80107da: 7dba ldrb r2, [r7, #22] + 80107dc: 68fb ldr r3, [r7, #12] + 80107de: 32ae adds r2, #174 ; 0xae + 80107e0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80107e4: 691b ldr r3, [r3, #16] + 80107e6: 2b00 cmp r3, #0 + 80107e8: d00b beq.n 8010802 { pdev->classId = idx; - 800efee: 7dba ldrb r2, [r7, #22] - 800eff0: 68fb ldr r3, [r7, #12] - 800eff2: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 80107ea: 7dba ldrb r2, [r7, #22] + 80107ec: 68fb ldr r3, [r7, #12] + 80107ee: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 pdev->pClass[idx]->EP0_RxReady(pdev); - 800eff6: 7dba ldrb r2, [r7, #22] - 800eff8: 68fb ldr r3, [r7, #12] - 800effa: 32ae adds r2, #174 ; 0xae - 800effc: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f000: 691b ldr r3, [r3, #16] - 800f002: 68f8 ldr r0, [r7, #12] - 800f004: 4798 blx r3 + 80107f2: 7dba ldrb r2, [r7, #22] + 80107f4: 68fb ldr r3, [r7, #12] + 80107f6: 32ae adds r2, #174 ; 0xae + 80107f8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80107fc: 691b ldr r3, [r3, #16] + 80107fe: 68f8 ldr r0, [r7, #12] + 8010800: 4798 blx r3 } } } (void)USBD_CtlSendStatus(pdev); - 800f006: 68f8 ldr r0, [r7, #12] - 800f008: f001 f8cb bl 80101a2 - 800f00c: e032 b.n 800f074 + 8010802: 68f8 ldr r0, [r7, #12] + 8010804: f001 f8e8 bl 80119d8 + 8010808: e032 b.n 8010870 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, (epnum & 0x7FU)); - 800f00e: 7afb ldrb r3, [r7, #11] - 800f010: f003 037f and.w r3, r3, #127 ; 0x7f - 800f014: b2db uxtb r3, r3 - 800f016: 4619 mov r1, r3 - 800f018: 68f8 ldr r0, [r7, #12] - 800f01a: f000 f9a5 bl 800f368 - 800f01e: 4603 mov r3, r0 - 800f020: 75bb strb r3, [r7, #22] + 801080a: 7afb ldrb r3, [r7, #11] + 801080c: f003 037f and.w r3, r3, #127 ; 0x7f + 8010810: b2db uxtb r3, r3 + 8010812: 4619 mov r1, r3 + 8010814: 68f8 ldr r0, [r7, #12] + 8010816: f000 f9a5 bl 8010b64 + 801081a: 4603 mov r3, r0 + 801081c: 75bb strb r3, [r7, #22] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) - 800f022: 7dbb ldrb r3, [r7, #22] - 800f024: 2bff cmp r3, #255 ; 0xff - 800f026: d025 beq.n 800f074 - 800f028: 7dbb ldrb r3, [r7, #22] - 800f02a: 2b00 cmp r3, #0 - 800f02c: d122 bne.n 800f074 + 801081e: 7dbb ldrb r3, [r7, #22] + 8010820: 2bff cmp r3, #255 ; 0xff + 8010822: d025 beq.n 8010870 + 8010824: 7dbb ldrb r3, [r7, #22] + 8010826: 2b00 cmp r3, #0 + 8010828: d122 bne.n 8010870 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800f02e: 68fb ldr r3, [r7, #12] - 800f030: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f034: b2db uxtb r3, r3 - 800f036: 2b03 cmp r3, #3 - 800f038: d117 bne.n 800f06a + 801082a: 68fb ldr r3, [r7, #12] + 801082c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010830: b2db uxtb r3, r3 + 8010832: 2b03 cmp r3, #3 + 8010834: d117 bne.n 8010866 { if (pdev->pClass[idx]->DataOut != NULL) - 800f03a: 7dba ldrb r2, [r7, #22] - 800f03c: 68fb ldr r3, [r7, #12] - 800f03e: 32ae adds r2, #174 ; 0xae - 800f040: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f044: 699b ldr r3, [r3, #24] - 800f046: 2b00 cmp r3, #0 - 800f048: d00f beq.n 800f06a + 8010836: 7dba ldrb r2, [r7, #22] + 8010838: 68fb ldr r3, [r7, #12] + 801083a: 32ae adds r2, #174 ; 0xae + 801083c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010840: 699b ldr r3, [r3, #24] + 8010842: 2b00 cmp r3, #0 + 8010844: d00f beq.n 8010866 { pdev->classId = idx; - 800f04a: 7dba ldrb r2, [r7, #22] - 800f04c: 68fb ldr r3, [r7, #12] - 800f04e: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 8010846: 7dba ldrb r2, [r7, #22] + 8010848: 68fb ldr r3, [r7, #12] + 801084a: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataOut(pdev, epnum); - 800f052: 7dba ldrb r2, [r7, #22] - 800f054: 68fb ldr r3, [r7, #12] - 800f056: 32ae adds r2, #174 ; 0xae - 800f058: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f05c: 699b ldr r3, [r3, #24] - 800f05e: 7afa ldrb r2, [r7, #11] - 800f060: 4611 mov r1, r2 - 800f062: 68f8 ldr r0, [r7, #12] - 800f064: 4798 blx r3 - 800f066: 4603 mov r3, r0 - 800f068: 75fb strb r3, [r7, #23] + 801084e: 7dba ldrb r2, [r7, #22] + 8010850: 68fb ldr r3, [r7, #12] + 8010852: 32ae adds r2, #174 ; 0xae + 8010854: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010858: 699b ldr r3, [r3, #24] + 801085a: 7afa ldrb r2, [r7, #11] + 801085c: 4611 mov r1, r2 + 801085e: 68f8 ldr r0, [r7, #12] + 8010860: 4798 blx r3 + 8010862: 4603 mov r3, r0 + 8010864: 75fb strb r3, [r7, #23] } } if (ret != USBD_OK) - 800f06a: 7dfb ldrb r3, [r7, #23] - 800f06c: 2b00 cmp r3, #0 - 800f06e: d001 beq.n 800f074 + 8010866: 7dfb ldrb r3, [r7, #23] + 8010868: 2b00 cmp r3, #0 + 801086a: d001 beq.n 8010870 { return ret; - 800f070: 7dfb ldrb r3, [r7, #23] - 800f072: e000 b.n 800f076 + 801086c: 7dfb ldrb r3, [r7, #23] + 801086e: e000 b.n 8010872 } } } return USBD_OK; - 800f074: 2300 movs r3, #0 + 8010870: 2300 movs r3, #0 } - 800f076: 4618 mov r0, r3 - 800f078: 3718 adds r7, #24 - 800f07a: 46bd mov sp, r7 - 800f07c: bd80 pop {r7, pc} + 8010872: 4618 mov r0, r3 + 8010874: 3718 adds r7, #24 + 8010876: 46bd mov sp, r7 + 8010878: bd80 pop {r7, pc} -0800f07e : +0801087a : * @param epnum: endpoint index * @retval status */ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { - 800f07e: b580 push {r7, lr} - 800f080: b086 sub sp, #24 - 800f082: af00 add r7, sp, #0 - 800f084: 60f8 str r0, [r7, #12] - 800f086: 460b mov r3, r1 - 800f088: 607a str r2, [r7, #4] - 800f08a: 72fb strb r3, [r7, #11] + 801087a: b580 push {r7, lr} + 801087c: b086 sub sp, #24 + 801087e: af00 add r7, sp, #0 + 8010880: 60f8 str r0, [r7, #12] + 8010882: 460b mov r3, r1 + 8010884: 607a str r2, [r7, #4] + 8010886: 72fb strb r3, [r7, #11] USBD_EndpointTypeDef *pep; USBD_StatusTypeDef ret; uint8_t idx; if (epnum == 0U) - 800f08c: 7afb ldrb r3, [r7, #11] - 800f08e: 2b00 cmp r3, #0 - 800f090: d16f bne.n 800f172 + 8010888: 7afb ldrb r3, [r7, #11] + 801088a: 2b00 cmp r3, #0 + 801088c: d16f bne.n 801096e { pep = &pdev->ep_in[0]; - 800f092: 68fb ldr r3, [r7, #12] - 800f094: 3314 adds r3, #20 - 800f096: 613b str r3, [r7, #16] + 801088e: 68fb ldr r3, [r7, #12] + 8010890: 3314 adds r3, #20 + 8010892: 613b str r3, [r7, #16] if (pdev->ep0_state == USBD_EP0_DATA_IN) - 800f098: 68fb ldr r3, [r7, #12] - 800f09a: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 - 800f09e: 2b02 cmp r3, #2 - 800f0a0: d15a bne.n 800f158 + 8010894: 68fb ldr r3, [r7, #12] + 8010896: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294 + 801089a: 2b02 cmp r3, #2 + 801089c: d15a bne.n 8010954 { if (pep->rem_length > pep->maxpacket) - 800f0a2: 693b ldr r3, [r7, #16] - 800f0a4: 689a ldr r2, [r3, #8] - 800f0a6: 693b ldr r3, [r7, #16] - 800f0a8: 68db ldr r3, [r3, #12] - 800f0aa: 429a cmp r2, r3 - 800f0ac: d914 bls.n 800f0d8 + 801089e: 693b ldr r3, [r7, #16] + 80108a0: 689a ldr r2, [r3, #8] + 80108a2: 693b ldr r3, [r7, #16] + 80108a4: 68db ldr r3, [r3, #12] + 80108a6: 429a cmp r2, r3 + 80108a8: d914 bls.n 80108d4 { pep->rem_length -= pep->maxpacket; - 800f0ae: 693b ldr r3, [r7, #16] - 800f0b0: 689a ldr r2, [r3, #8] - 800f0b2: 693b ldr r3, [r7, #16] - 800f0b4: 68db ldr r3, [r3, #12] - 800f0b6: 1ad2 subs r2, r2, r3 - 800f0b8: 693b ldr r3, [r7, #16] - 800f0ba: 609a str r2, [r3, #8] + 80108aa: 693b ldr r3, [r7, #16] + 80108ac: 689a ldr r2, [r3, #8] + 80108ae: 693b ldr r3, [r7, #16] + 80108b0: 68db ldr r3, [r3, #12] + 80108b2: 1ad2 subs r2, r2, r3 + 80108b4: 693b ldr r3, [r7, #16] + 80108b6: 609a str r2, [r3, #8] (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); - 800f0bc: 693b ldr r3, [r7, #16] - 800f0be: 689b ldr r3, [r3, #8] - 800f0c0: 461a mov r2, r3 - 800f0c2: 6879 ldr r1, [r7, #4] - 800f0c4: 68f8 ldr r0, [r7, #12] - 800f0c6: f001 f84a bl 801015e + 80108b8: 693b ldr r3, [r7, #16] + 80108ba: 689b ldr r3, [r3, #8] + 80108bc: 461a mov r2, r3 + 80108be: 6879 ldr r1, [r7, #4] + 80108c0: 68f8 ldr r0, [r7, #12] + 80108c2: f001 f84a bl 801195a /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); - 800f0ca: 2300 movs r3, #0 - 800f0cc: 2200 movs r2, #0 - 800f0ce: 2100 movs r1, #0 - 800f0d0: 68f8 ldr r0, [r7, #12] - 800f0d2: f001 fca3 bl 8010a1c - 800f0d6: e03f b.n 800f158 + 80108c6: 2300 movs r3, #0 + 80108c8: 2200 movs r2, #0 + 80108ca: 2100 movs r1, #0 + 80108cc: 68f8 ldr r0, [r7, #12] + 80108ce: f002 fae5 bl 8012e9c + 80108d2: e03f b.n 8010954 } else { /* last packet is MPS multiple, so send ZLP packet */ if ((pep->maxpacket == pep->rem_length) && - 800f0d8: 693b ldr r3, [r7, #16] - 800f0da: 68da ldr r2, [r3, #12] - 800f0dc: 693b ldr r3, [r7, #16] - 800f0de: 689b ldr r3, [r3, #8] - 800f0e0: 429a cmp r2, r3 - 800f0e2: d11c bne.n 800f11e + 80108d4: 693b ldr r3, [r7, #16] + 80108d6: 68da ldr r2, [r3, #12] + 80108d8: 693b ldr r3, [r7, #16] + 80108da: 689b ldr r3, [r3, #8] + 80108dc: 429a cmp r2, r3 + 80108de: d11c bne.n 801091a (pep->total_length >= pep->maxpacket) && - 800f0e4: 693b ldr r3, [r7, #16] - 800f0e6: 685a ldr r2, [r3, #4] - 800f0e8: 693b ldr r3, [r7, #16] - 800f0ea: 68db ldr r3, [r3, #12] + 80108e0: 693b ldr r3, [r7, #16] + 80108e2: 685a ldr r2, [r3, #4] + 80108e4: 693b ldr r3, [r7, #16] + 80108e6: 68db ldr r3, [r3, #12] if ((pep->maxpacket == pep->rem_length) && - 800f0ec: 429a cmp r2, r3 - 800f0ee: d316 bcc.n 800f11e + 80108e8: 429a cmp r2, r3 + 80108ea: d316 bcc.n 801091a (pep->total_length < pdev->ep0_data_len)) - 800f0f0: 693b ldr r3, [r7, #16] - 800f0f2: 685a ldr r2, [r3, #4] - 800f0f4: 68fb ldr r3, [r7, #12] - 800f0f6: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 + 80108ec: 693b ldr r3, [r7, #16] + 80108ee: 685a ldr r2, [r3, #4] + 80108f0: 68fb ldr r3, [r7, #12] + 80108f2: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298 (pep->total_length >= pep->maxpacket) && - 800f0fa: 429a cmp r2, r3 - 800f0fc: d20f bcs.n 800f11e + 80108f6: 429a cmp r2, r3 + 80108f8: d20f bcs.n 801091a { (void)USBD_CtlContinueSendData(pdev, NULL, 0U); - 800f0fe: 2200 movs r2, #0 - 800f100: 2100 movs r1, #0 - 800f102: 68f8 ldr r0, [r7, #12] - 800f104: f001 f82b bl 801015e + 80108fa: 2200 movs r2, #0 + 80108fc: 2100 movs r1, #0 + 80108fe: 68f8 ldr r0, [r7, #12] + 8010900: f001 f82b bl 801195a pdev->ep0_data_len = 0U; - 800f108: 68fb ldr r3, [r7, #12] - 800f10a: 2200 movs r2, #0 - 800f10c: f8c3 2298 str.w r2, [r3, #664] ; 0x298 + 8010904: 68fb ldr r3, [r7, #12] + 8010906: 2200 movs r2, #0 + 8010908: f8c3 2298 str.w r2, [r3, #664] ; 0x298 /* Prepare endpoint for premature end of transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); - 800f110: 2300 movs r3, #0 - 800f112: 2200 movs r2, #0 - 800f114: 2100 movs r1, #0 - 800f116: 68f8 ldr r0, [r7, #12] - 800f118: f001 fc80 bl 8010a1c - 800f11c: e01c b.n 800f158 + 801090c: 2300 movs r3, #0 + 801090e: 2200 movs r2, #0 + 8010910: 2100 movs r1, #0 + 8010912: 68f8 ldr r0, [r7, #12] + 8010914: f002 fac2 bl 8012e9c + 8010918: e01c b.n 8010954 } else { if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800f11e: 68fb ldr r3, [r7, #12] - 800f120: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f124: b2db uxtb r3, r3 - 800f126: 2b03 cmp r3, #3 - 800f128: d10f bne.n 800f14a + 801091a: 68fb ldr r3, [r7, #12] + 801091c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010920: b2db uxtb r3, r3 + 8010922: 2b03 cmp r3, #3 + 8010924: d10f bne.n 8010946 { if (pdev->pClass[0]->EP0_TxSent != NULL) - 800f12a: 68fb ldr r3, [r7, #12] - 800f12c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f130: 68db ldr r3, [r3, #12] - 800f132: 2b00 cmp r3, #0 - 800f134: d009 beq.n 800f14a + 8010926: 68fb ldr r3, [r7, #12] + 8010928: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 801092c: 68db ldr r3, [r3, #12] + 801092e: 2b00 cmp r3, #0 + 8010930: d009 beq.n 8010946 { pdev->classId = 0U; - 800f136: 68fb ldr r3, [r7, #12] - 800f138: 2200 movs r2, #0 - 800f13a: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 8010932: 68fb ldr r3, [r7, #12] + 8010934: 2200 movs r2, #0 + 8010936: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 pdev->pClass[0]->EP0_TxSent(pdev); - 800f13e: 68fb ldr r3, [r7, #12] - 800f140: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f144: 68db ldr r3, [r3, #12] - 800f146: 68f8 ldr r0, [r7, #12] - 800f148: 4798 blx r3 + 801093a: 68fb ldr r3, [r7, #12] + 801093c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010940: 68db ldr r3, [r3, #12] + 8010942: 68f8 ldr r0, [r7, #12] + 8010944: 4798 blx r3 } } (void)USBD_LL_StallEP(pdev, 0x80U); - 800f14a: 2180 movs r1, #128 ; 0x80 - 800f14c: 68f8 ldr r0, [r7, #12] - 800f14e: f001 fb5d bl 801080c + 8010946: 2180 movs r1, #128 ; 0x80 + 8010948: 68f8 ldr r0, [r7, #12] + 801094a: f002 f99f bl 8012c8c (void)USBD_CtlReceiveStatus(pdev); - 800f152: 68f8 ldr r0, [r7, #12] - 800f154: f001 f838 bl 80101c8 + 801094e: 68f8 ldr r0, [r7, #12] + 8010950: f001 f855 bl 80119fe } } } if (pdev->dev_test_mode != 0U) - 800f158: 68fb ldr r3, [r7, #12] - 800f15a: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 - 800f15e: 2b00 cmp r3, #0 - 800f160: d03a beq.n 800f1d8 + 8010954: 68fb ldr r3, [r7, #12] + 8010956: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0 + 801095a: 2b00 cmp r3, #0 + 801095c: d03a beq.n 80109d4 { (void)USBD_RunTestMode(pdev); - 800f162: 68f8 ldr r0, [r7, #12] - 800f164: f7ff fe42 bl 800edec + 801095e: 68f8 ldr r0, [r7, #12] + 8010960: f7ff fe42 bl 80105e8 pdev->dev_test_mode = 0U; - 800f168: 68fb ldr r3, [r7, #12] - 800f16a: 2200 movs r2, #0 - 800f16c: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 - 800f170: e032 b.n 800f1d8 + 8010964: 68fb ldr r3, [r7, #12] + 8010966: 2200 movs r2, #0 + 8010968: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 + 801096c: e032 b.n 80109d4 } } else { /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ((uint8_t)epnum | 0x80U)); - 800f172: 7afb ldrb r3, [r7, #11] - 800f174: f063 037f orn r3, r3, #127 ; 0x7f - 800f178: b2db uxtb r3, r3 - 800f17a: 4619 mov r1, r3 - 800f17c: 68f8 ldr r0, [r7, #12] - 800f17e: f000 f8f3 bl 800f368 - 800f182: 4603 mov r3, r0 - 800f184: 75fb strb r3, [r7, #23] + 801096e: 7afb ldrb r3, [r7, #11] + 8010970: f063 037f orn r3, r3, #127 ; 0x7f + 8010974: b2db uxtb r3, r3 + 8010976: 4619 mov r1, r3 + 8010978: 68f8 ldr r0, [r7, #12] + 801097a: f000 f8f3 bl 8010b64 + 801097e: 4603 mov r3, r0 + 8010980: 75fb strb r3, [r7, #23] if (((uint16_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) - 800f186: 7dfb ldrb r3, [r7, #23] - 800f188: 2bff cmp r3, #255 ; 0xff - 800f18a: d025 beq.n 800f1d8 - 800f18c: 7dfb ldrb r3, [r7, #23] - 800f18e: 2b00 cmp r3, #0 - 800f190: d122 bne.n 800f1d8 + 8010982: 7dfb ldrb r3, [r7, #23] + 8010984: 2bff cmp r3, #255 ; 0xff + 8010986: d025 beq.n 80109d4 + 8010988: 7dfb ldrb r3, [r7, #23] + 801098a: 2b00 cmp r3, #0 + 801098c: d122 bne.n 80109d4 { /* Call the class data out function to manage the request */ if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800f192: 68fb ldr r3, [r7, #12] - 800f194: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f198: b2db uxtb r3, r3 - 800f19a: 2b03 cmp r3, #3 - 800f19c: d11c bne.n 800f1d8 + 801098e: 68fb ldr r3, [r7, #12] + 8010990: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010994: b2db uxtb r3, r3 + 8010996: 2b03 cmp r3, #3 + 8010998: d11c bne.n 80109d4 { if (pdev->pClass[idx]->DataIn != NULL) - 800f19e: 7dfa ldrb r2, [r7, #23] - 800f1a0: 68fb ldr r3, [r7, #12] - 800f1a2: 32ae adds r2, #174 ; 0xae - 800f1a4: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f1a8: 695b ldr r3, [r3, #20] - 800f1aa: 2b00 cmp r3, #0 - 800f1ac: d014 beq.n 800f1d8 + 801099a: 7dfa ldrb r2, [r7, #23] + 801099c: 68fb ldr r3, [r7, #12] + 801099e: 32ae adds r2, #174 ; 0xae + 80109a0: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80109a4: 695b ldr r3, [r3, #20] + 80109a6: 2b00 cmp r3, #0 + 80109a8: d014 beq.n 80109d4 { pdev->classId = idx; - 800f1ae: 7dfa ldrb r2, [r7, #23] - 800f1b0: 68fb ldr r3, [r7, #12] - 800f1b2: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 80109aa: 7dfa ldrb r2, [r7, #23] + 80109ac: 68fb ldr r3, [r7, #12] + 80109ae: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 ret = (USBD_StatusTypeDef)pdev->pClass[idx]->DataIn(pdev, epnum); - 800f1b6: 7dfa ldrb r2, [r7, #23] - 800f1b8: 68fb ldr r3, [r7, #12] - 800f1ba: 32ae adds r2, #174 ; 0xae - 800f1bc: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f1c0: 695b ldr r3, [r3, #20] - 800f1c2: 7afa ldrb r2, [r7, #11] - 800f1c4: 4611 mov r1, r2 - 800f1c6: 68f8 ldr r0, [r7, #12] - 800f1c8: 4798 blx r3 - 800f1ca: 4603 mov r3, r0 - 800f1cc: 75bb strb r3, [r7, #22] + 80109b2: 7dfa ldrb r2, [r7, #23] + 80109b4: 68fb ldr r3, [r7, #12] + 80109b6: 32ae adds r2, #174 ; 0xae + 80109b8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80109bc: 695b ldr r3, [r3, #20] + 80109be: 7afa ldrb r2, [r7, #11] + 80109c0: 4611 mov r1, r2 + 80109c2: 68f8 ldr r0, [r7, #12] + 80109c4: 4798 blx r3 + 80109c6: 4603 mov r3, r0 + 80109c8: 75bb strb r3, [r7, #22] if (ret != USBD_OK) - 800f1ce: 7dbb ldrb r3, [r7, #22] - 800f1d0: 2b00 cmp r3, #0 - 800f1d2: d001 beq.n 800f1d8 + 80109ca: 7dbb ldrb r3, [r7, #22] + 80109cc: 2b00 cmp r3, #0 + 80109ce: d001 beq.n 80109d4 { return ret; - 800f1d4: 7dbb ldrb r3, [r7, #22] - 800f1d6: e000 b.n 800f1da + 80109d0: 7dbb ldrb r3, [r7, #22] + 80109d2: e000 b.n 80109d6 } } } } return USBD_OK; - 800f1d8: 2300 movs r3, #0 + 80109d4: 2300 movs r3, #0 } - 800f1da: 4618 mov r0, r3 - 800f1dc: 3718 adds r7, #24 - 800f1de: 46bd mov sp, r7 - 800f1e0: bd80 pop {r7, pc} + 80109d6: 4618 mov r0, r3 + 80109d8: 3718 adds r7, #24 + 80109da: 46bd mov sp, r7 + 80109dc: bd80 pop {r7, pc} -0800f1e2 : +080109de : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { - 800f1e2: b580 push {r7, lr} - 800f1e4: b084 sub sp, #16 - 800f1e6: af00 add r7, sp, #0 - 800f1e8: 6078 str r0, [r7, #4] + 80109de: b580 push {r7, lr} + 80109e0: b084 sub sp, #16 + 80109e2: af00 add r7, sp, #0 + 80109e4: 6078 str r0, [r7, #4] USBD_StatusTypeDef ret = USBD_OK; - 800f1ea: 2300 movs r3, #0 - 800f1ec: 73fb strb r3, [r7, #15] + 80109e6: 2300 movs r3, #0 + 80109e8: 73fb strb r3, [r7, #15] /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; - 800f1ee: 687b ldr r3, [r7, #4] - 800f1f0: 2201 movs r2, #1 - 800f1f2: f883 229c strb.w r2, [r3, #668] ; 0x29c + 80109ea: 687b ldr r3, [r7, #4] + 80109ec: 2201 movs r2, #1 + 80109ee: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->ep0_state = USBD_EP0_IDLE; - 800f1f6: 687b ldr r3, [r7, #4] - 800f1f8: 2200 movs r2, #0 - 800f1fa: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + 80109f2: 687b ldr r3, [r7, #4] + 80109f4: 2200 movs r2, #0 + 80109f6: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->dev_config = 0U; - 800f1fe: 687b ldr r3, [r7, #4] - 800f200: 2200 movs r2, #0 - 800f202: 605a str r2, [r3, #4] + 80109fa: 687b ldr r3, [r7, #4] + 80109fc: 2200 movs r2, #0 + 80109fe: 605a str r2, [r3, #4] pdev->dev_remote_wakeup = 0U; - 800f204: 687b ldr r3, [r7, #4] - 800f206: 2200 movs r2, #0 - 800f208: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + 8010a00: 687b ldr r3, [r7, #4] + 8010a02: 2200 movs r2, #0 + 8010a04: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 pdev->dev_test_mode = 0U; - 800f20c: 687b ldr r3, [r7, #4] - 800f20e: 2200 movs r2, #0 - 800f210: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 + 8010a08: 687b ldr r3, [r7, #4] + 8010a0a: 2200 movs r2, #0 + 8010a0c: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 } } } #else if (pdev->pClass[0] != NULL) - 800f214: 687b ldr r3, [r7, #4] - 800f216: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f21a: 2b00 cmp r3, #0 - 800f21c: d014 beq.n 800f248 + 8010a10: 687b ldr r3, [r7, #4] + 8010a12: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010a16: 2b00 cmp r3, #0 + 8010a18: d014 beq.n 8010a44 { if (pdev->pClass[0]->DeInit != NULL) - 800f21e: 687b ldr r3, [r7, #4] - 800f220: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f224: 685b ldr r3, [r3, #4] - 800f226: 2b00 cmp r3, #0 - 800f228: d00e beq.n 800f248 + 8010a1a: 687b ldr r3, [r7, #4] + 8010a1c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010a20: 685b ldr r3, [r3, #4] + 8010a22: 2b00 cmp r3, #0 + 8010a24: d00e beq.n 8010a44 { if (pdev->pClass[0]->DeInit(pdev, (uint8_t)pdev->dev_config) != USBD_OK) - 800f22a: 687b ldr r3, [r7, #4] - 800f22c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f230: 685b ldr r3, [r3, #4] - 800f232: 687a ldr r2, [r7, #4] - 800f234: 6852 ldr r2, [r2, #4] - 800f236: b2d2 uxtb r2, r2 - 800f238: 4611 mov r1, r2 - 800f23a: 6878 ldr r0, [r7, #4] - 800f23c: 4798 blx r3 - 800f23e: 4603 mov r3, r0 - 800f240: 2b00 cmp r3, #0 - 800f242: d001 beq.n 800f248 + 8010a26: 687b ldr r3, [r7, #4] + 8010a28: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010a2c: 685b ldr r3, [r3, #4] + 8010a2e: 687a ldr r2, [r7, #4] + 8010a30: 6852 ldr r2, [r2, #4] + 8010a32: b2d2 uxtb r2, r2 + 8010a34: 4611 mov r1, r2 + 8010a36: 6878 ldr r0, [r7, #4] + 8010a38: 4798 blx r3 + 8010a3a: 4603 mov r3, r0 + 8010a3c: 2b00 cmp r3, #0 + 8010a3e: d001 beq.n 8010a44 { ret = USBD_FAIL; - 800f244: 2303 movs r3, #3 - 800f246: 73fb strb r3, [r7, #15] + 8010a40: 2303 movs r3, #3 + 8010a42: 73fb strb r3, [r7, #15] } } #endif /* USE_USBD_COMPOSITE */ /* Open EP0 OUT */ (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - 800f248: 2340 movs r3, #64 ; 0x40 - 800f24a: 2200 movs r2, #0 - 800f24c: 2100 movs r1, #0 - 800f24e: 6878 ldr r0, [r7, #4] - 800f250: f001 fa68 bl 8010724 + 8010a44: 2340 movs r3, #64 ; 0x40 + 8010a46: 2200 movs r2, #0 + 8010a48: 2100 movs r1, #0 + 8010a4a: 6878 ldr r0, [r7, #4] + 8010a4c: f002 f8aa bl 8012ba4 pdev->ep_out[0x00U & 0xFU].is_used = 1U; - 800f254: 687b ldr r3, [r7, #4] - 800f256: 2201 movs r2, #1 - 800f258: f8a3 2164 strh.w r2, [r3, #356] ; 0x164 + 8010a50: 687b ldr r3, [r7, #4] + 8010a52: 2201 movs r2, #1 + 8010a54: f8a3 2164 strh.w r2, [r3, #356] ; 0x164 pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - 800f25c: 687b ldr r3, [r7, #4] - 800f25e: 2240 movs r2, #64 ; 0x40 - 800f260: f8c3 2160 str.w r2, [r3, #352] ; 0x160 + 8010a58: 687b ldr r3, [r7, #4] + 8010a5a: 2240 movs r2, #64 ; 0x40 + 8010a5c: f8c3 2160 str.w r2, [r3, #352] ; 0x160 /* Open EP0 IN */ (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - 800f264: 2340 movs r3, #64 ; 0x40 - 800f266: 2200 movs r2, #0 - 800f268: 2180 movs r1, #128 ; 0x80 - 800f26a: 6878 ldr r0, [r7, #4] - 800f26c: f001 fa5a bl 8010724 + 8010a60: 2340 movs r3, #64 ; 0x40 + 8010a62: 2200 movs r2, #0 + 8010a64: 2180 movs r1, #128 ; 0x80 + 8010a66: 6878 ldr r0, [r7, #4] + 8010a68: f002 f89c bl 8012ba4 pdev->ep_in[0x80U & 0xFU].is_used = 1U; - 800f270: 687b ldr r3, [r7, #4] - 800f272: 2201 movs r2, #1 - 800f274: 849a strh r2, [r3, #36] ; 0x24 + 8010a6c: 687b ldr r3, [r7, #4] + 8010a6e: 2201 movs r2, #1 + 8010a70: 849a strh r2, [r3, #36] ; 0x24 pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - 800f276: 687b ldr r3, [r7, #4] - 800f278: 2240 movs r2, #64 ; 0x40 - 800f27a: 621a str r2, [r3, #32] + 8010a72: 687b ldr r3, [r7, #4] + 8010a74: 2240 movs r2, #64 ; 0x40 + 8010a76: 621a str r2, [r3, #32] return ret; - 800f27c: 7bfb ldrb r3, [r7, #15] + 8010a78: 7bfb ldrb r3, [r7, #15] } - 800f27e: 4618 mov r0, r3 - 800f280: 3710 adds r7, #16 - 800f282: 46bd mov sp, r7 - 800f284: bd80 pop {r7, pc} + 8010a7a: 4618 mov r0, r3 + 8010a7c: 3710 adds r7, #16 + 8010a7e: 46bd mov sp, r7 + 8010a80: bd80 pop {r7, pc} -0800f286 : +08010a82 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) { - 800f286: b480 push {r7} - 800f288: b083 sub sp, #12 - 800f28a: af00 add r7, sp, #0 - 800f28c: 6078 str r0, [r7, #4] - 800f28e: 460b mov r3, r1 - 800f290: 70fb strb r3, [r7, #3] + 8010a82: b480 push {r7} + 8010a84: b083 sub sp, #12 + 8010a86: af00 add r7, sp, #0 + 8010a88: 6078 str r0, [r7, #4] + 8010a8a: 460b mov r3, r1 + 8010a8c: 70fb strb r3, [r7, #3] pdev->dev_speed = speed; - 800f292: 687b ldr r3, [r7, #4] - 800f294: 78fa ldrb r2, [r7, #3] - 800f296: 741a strb r2, [r3, #16] + 8010a8e: 687b ldr r3, [r7, #4] + 8010a90: 78fa ldrb r2, [r7, #3] + 8010a92: 741a strb r2, [r3, #16] return USBD_OK; - 800f298: 2300 movs r3, #0 + 8010a94: 2300 movs r3, #0 } - 800f29a: 4618 mov r0, r3 - 800f29c: 370c adds r7, #12 - 800f29e: 46bd mov sp, r7 - 800f2a0: f85d 7b04 ldr.w r7, [sp], #4 - 800f2a4: 4770 bx lr + 8010a96: 4618 mov r0, r3 + 8010a98: 370c adds r7, #12 + 8010a9a: 46bd mov sp, r7 + 8010a9c: f85d 7b04 ldr.w r7, [sp], #4 + 8010aa0: 4770 bx lr -0800f2a6 : +08010aa2 : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { - 800f2a6: b480 push {r7} - 800f2a8: b083 sub sp, #12 - 800f2aa: af00 add r7, sp, #0 - 800f2ac: 6078 str r0, [r7, #4] + 8010aa2: b480 push {r7} + 8010aa4: b083 sub sp, #12 + 8010aa6: af00 add r7, sp, #0 + 8010aa8: 6078 str r0, [r7, #4] if (pdev->dev_state != USBD_STATE_SUSPENDED) - 800f2ae: 687b ldr r3, [r7, #4] - 800f2b0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f2b4: b2db uxtb r3, r3 - 800f2b6: 2b04 cmp r3, #4 - 800f2b8: d006 beq.n 800f2c8 + 8010aaa: 687b ldr r3, [r7, #4] + 8010aac: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010ab0: b2db uxtb r3, r3 + 8010ab2: 2b04 cmp r3, #4 + 8010ab4: d006 beq.n 8010ac4 { pdev->dev_old_state = pdev->dev_state; - 800f2ba: 687b ldr r3, [r7, #4] - 800f2bc: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f2c0: b2da uxtb r2, r3 - 800f2c2: 687b ldr r3, [r7, #4] - 800f2c4: f883 229d strb.w r2, [r3, #669] ; 0x29d + 8010ab6: 687b ldr r3, [r7, #4] + 8010ab8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010abc: b2da uxtb r2, r3 + 8010abe: 687b ldr r3, [r7, #4] + 8010ac0: f883 229d strb.w r2, [r3, #669] ; 0x29d } pdev->dev_state = USBD_STATE_SUSPENDED; - 800f2c8: 687b ldr r3, [r7, #4] - 800f2ca: 2204 movs r2, #4 - 800f2cc: f883 229c strb.w r2, [r3, #668] ; 0x29c + 8010ac4: 687b ldr r3, [r7, #4] + 8010ac6: 2204 movs r2, #4 + 8010ac8: f883 229c strb.w r2, [r3, #668] ; 0x29c return USBD_OK; - 800f2d0: 2300 movs r3, #0 + 8010acc: 2300 movs r3, #0 } - 800f2d2: 4618 mov r0, r3 - 800f2d4: 370c adds r7, #12 - 800f2d6: 46bd mov sp, r7 - 800f2d8: f85d 7b04 ldr.w r7, [sp], #4 - 800f2dc: 4770 bx lr + 8010ace: 4618 mov r0, r3 + 8010ad0: 370c adds r7, #12 + 8010ad2: 46bd mov sp, r7 + 8010ad4: f85d 7b04 ldr.w r7, [sp], #4 + 8010ad8: 4770 bx lr -0800f2de : +08010ada : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) { - 800f2de: b480 push {r7} - 800f2e0: b083 sub sp, #12 - 800f2e2: af00 add r7, sp, #0 - 800f2e4: 6078 str r0, [r7, #4] + 8010ada: b480 push {r7} + 8010adc: b083 sub sp, #12 + 8010ade: af00 add r7, sp, #0 + 8010ae0: 6078 str r0, [r7, #4] if (pdev->dev_state == USBD_STATE_SUSPENDED) - 800f2e6: 687b ldr r3, [r7, #4] - 800f2e8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f2ec: b2db uxtb r3, r3 - 800f2ee: 2b04 cmp r3, #4 - 800f2f0: d106 bne.n 800f300 + 8010ae2: 687b ldr r3, [r7, #4] + 8010ae4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010ae8: b2db uxtb r3, r3 + 8010aea: 2b04 cmp r3, #4 + 8010aec: d106 bne.n 8010afc { pdev->dev_state = pdev->dev_old_state; - 800f2f2: 687b ldr r3, [r7, #4] - 800f2f4: f893 329d ldrb.w r3, [r3, #669] ; 0x29d - 800f2f8: b2da uxtb r2, r3 - 800f2fa: 687b ldr r3, [r7, #4] - 800f2fc: f883 229c strb.w r2, [r3, #668] ; 0x29c + 8010aee: 687b ldr r3, [r7, #4] + 8010af0: f893 329d ldrb.w r3, [r3, #669] ; 0x29d + 8010af4: b2da uxtb r2, r3 + 8010af6: 687b ldr r3, [r7, #4] + 8010af8: f883 229c strb.w r2, [r3, #668] ; 0x29c } return USBD_OK; - 800f300: 2300 movs r3, #0 + 8010afc: 2300 movs r3, #0 } - 800f302: 4618 mov r0, r3 - 800f304: 370c adds r7, #12 - 800f306: 46bd mov sp, r7 - 800f308: f85d 7b04 ldr.w r7, [sp], #4 - 800f30c: 4770 bx lr + 8010afe: 4618 mov r0, r3 + 8010b00: 370c adds r7, #12 + 8010b02: 46bd mov sp, r7 + 8010b04: f85d 7b04 ldr.w r7, [sp], #4 + 8010b08: 4770 bx lr -0800f30e : +08010b0a : * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) { - 800f30e: b580 push {r7, lr} - 800f310: b082 sub sp, #8 - 800f312: af00 add r7, sp, #0 - 800f314: 6078 str r0, [r7, #4] + 8010b0a: b580 push {r7, lr} + 8010b0c: b082 sub sp, #8 + 8010b0e: af00 add r7, sp, #0 + 8010b10: 6078 str r0, [r7, #4] /* The SOF event can be distributed for all classes that support it */ if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800f316: 687b ldr r3, [r7, #4] - 800f318: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f31c: b2db uxtb r3, r3 - 800f31e: 2b03 cmp r3, #3 - 800f320: d110 bne.n 800f344 + 8010b12: 687b ldr r3, [r7, #4] + 8010b14: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010b18: b2db uxtb r3, r3 + 8010b1a: 2b03 cmp r3, #3 + 8010b1c: d110 bne.n 8010b40 } } } } #else if (pdev->pClass[0] != NULL) - 800f322: 687b ldr r3, [r7, #4] - 800f324: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f328: 2b00 cmp r3, #0 - 800f32a: d00b beq.n 800f344 + 8010b1e: 687b ldr r3, [r7, #4] + 8010b20: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010b24: 2b00 cmp r3, #0 + 8010b26: d00b beq.n 8010b40 { if (pdev->pClass[0]->SOF != NULL) - 800f32c: 687b ldr r3, [r7, #4] - 800f32e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f332: 69db ldr r3, [r3, #28] - 800f334: 2b00 cmp r3, #0 - 800f336: d005 beq.n 800f344 + 8010b28: 687b ldr r3, [r7, #4] + 8010b2a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010b2e: 69db ldr r3, [r3, #28] + 8010b30: 2b00 cmp r3, #0 + 8010b32: d005 beq.n 8010b40 { (void)pdev->pClass[0]->SOF(pdev); - 800f338: 687b ldr r3, [r7, #4] - 800f33a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800f33e: 69db ldr r3, [r3, #28] - 800f340: 6878 ldr r0, [r7, #4] - 800f342: 4798 blx r3 + 8010b34: 687b ldr r3, [r7, #4] + 8010b36: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8010b3a: 69db ldr r3, [r3, #28] + 8010b3c: 6878 ldr r0, [r7, #4] + 8010b3e: 4798 blx r3 } } #endif /* USE_USBD_COMPOSITE */ } return USBD_OK; - 800f344: 2300 movs r3, #0 + 8010b40: 2300 movs r3, #0 } - 800f346: 4618 mov r0, r3 - 800f348: 3708 adds r7, #8 - 800f34a: 46bd mov sp, r7 - 800f34c: bd80 pop {r7, pc} + 8010b42: 4618 mov r0, r3 + 8010b44: 3708 adds r7, #8 + 8010b46: 46bd mov sp, r7 + 8010b48: bd80 pop {r7, pc} -0800f34e : +08010b4a : * @param pdev: device instance * @param index : selected interface number * @retval index of the class using the selected interface number. OxFF if no class found. */ uint8_t USBD_CoreFindIF(USBD_HandleTypeDef *pdev, uint8_t index) { - 800f34e: b480 push {r7} - 800f350: b083 sub sp, #12 - 800f352: af00 add r7, sp, #0 - 800f354: 6078 str r0, [r7, #4] - 800f356: 460b mov r3, r1 - 800f358: 70fb strb r3, [r7, #3] + 8010b4a: b480 push {r7} + 8010b4c: b083 sub sp, #12 + 8010b4e: af00 add r7, sp, #0 + 8010b50: 6078 str r0, [r7, #4] + 8010b52: 460b mov r3, r1 + 8010b54: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; - 800f35a: 2300 movs r3, #0 + 8010b56: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } - 800f35c: 4618 mov r0, r3 - 800f35e: 370c adds r7, #12 - 800f360: 46bd mov sp, r7 - 800f362: f85d 7b04 ldr.w r7, [sp], #4 - 800f366: 4770 bx lr + 8010b58: 4618 mov r0, r3 + 8010b5a: 370c adds r7, #12 + 8010b5c: 46bd mov sp, r7 + 8010b5e: f85d 7b04 ldr.w r7, [sp], #4 + 8010b62: 4770 bx lr -0800f368 : +08010b64 : * @param pdev: device instance * @param index : selected endpoint number * @retval index of the class using the selected endpoint number. 0xFF if no class found. */ uint8_t USBD_CoreFindEP(USBD_HandleTypeDef *pdev, uint8_t index) { - 800f368: b480 push {r7} - 800f36a: b083 sub sp, #12 - 800f36c: af00 add r7, sp, #0 - 800f36e: 6078 str r0, [r7, #4] - 800f370: 460b mov r3, r1 - 800f372: 70fb strb r3, [r7, #3] + 8010b64: b480 push {r7} + 8010b66: b083 sub sp, #12 + 8010b68: af00 add r7, sp, #0 + 8010b6a: 6078 str r0, [r7, #4] + 8010b6c: 460b mov r3, r1 + 8010b6e: 70fb strb r3, [r7, #3] return 0xFFU; #else UNUSED(pdev); UNUSED(index); return 0x00U; - 800f374: 2300 movs r3, #0 + 8010b70: 2300 movs r3, #0 #endif /* USE_USBD_COMPOSITE */ } - 800f376: 4618 mov r0, r3 - 800f378: 370c adds r7, #12 - 800f37a: 46bd mov sp, r7 - 800f37c: f85d 7b04 ldr.w r7, [sp], #4 - 800f380: 4770 bx lr + 8010b72: 4618 mov r0, r3 + 8010b74: 370c adds r7, #12 + 8010b76: 46bd mov sp, r7 + 8010b78: f85d 7b04 ldr.w r7, [sp], #4 + 8010b7c: 4770 bx lr -0800f382 : +08010b7e : * @param pConfDesc: pointer to Bos descriptor * @param EpAddr: endpoint address * @retval pointer to video endpoint descriptor */ void *USBD_GetEpDesc(uint8_t *pConfDesc, uint8_t EpAddr) { - 800f382: b580 push {r7, lr} - 800f384: b086 sub sp, #24 - 800f386: af00 add r7, sp, #0 - 800f388: 6078 str r0, [r7, #4] - 800f38a: 460b mov r3, r1 - 800f38c: 70fb strb r3, [r7, #3] + 8010b7e: b580 push {r7, lr} + 8010b80: b086 sub sp, #24 + 8010b82: af00 add r7, sp, #0 + 8010b84: 6078 str r0, [r7, #4] + 8010b86: 460b mov r3, r1 + 8010b88: 70fb strb r3, [r7, #3] USBD_DescHeaderTypeDef *pdesc = (USBD_DescHeaderTypeDef *)(void *)pConfDesc; - 800f38e: 687b ldr r3, [r7, #4] - 800f390: 617b str r3, [r7, #20] + 8010b8a: 687b ldr r3, [r7, #4] + 8010b8c: 617b str r3, [r7, #20] USBD_ConfigDescTypeDef *desc = (USBD_ConfigDescTypeDef *)(void *)pConfDesc; - 800f392: 687b ldr r3, [r7, #4] - 800f394: 60fb str r3, [r7, #12] + 8010b8e: 687b ldr r3, [r7, #4] + 8010b90: 60fb str r3, [r7, #12] USBD_EpDescTypeDef *pEpDesc = NULL; - 800f396: 2300 movs r3, #0 - 800f398: 613b str r3, [r7, #16] + 8010b92: 2300 movs r3, #0 + 8010b94: 613b str r3, [r7, #16] uint16_t ptr; if (desc->wTotalLength > desc->bLength) - 800f39a: 68fb ldr r3, [r7, #12] - 800f39c: 885b ldrh r3, [r3, #2] - 800f39e: b29a uxth r2, r3 - 800f3a0: 68fb ldr r3, [r7, #12] - 800f3a2: 781b ldrb r3, [r3, #0] - 800f3a4: b29b uxth r3, r3 - 800f3a6: 429a cmp r2, r3 - 800f3a8: d920 bls.n 800f3ec + 8010b96: 68fb ldr r3, [r7, #12] + 8010b98: 885b ldrh r3, [r3, #2] + 8010b9a: b29a uxth r2, r3 + 8010b9c: 68fb ldr r3, [r7, #12] + 8010b9e: 781b ldrb r3, [r3, #0] + 8010ba0: b29b uxth r3, r3 + 8010ba2: 429a cmp r2, r3 + 8010ba4: d920 bls.n 8010be8 { ptr = desc->bLength; - 800f3aa: 68fb ldr r3, [r7, #12] - 800f3ac: 781b ldrb r3, [r3, #0] - 800f3ae: b29b uxth r3, r3 - 800f3b0: 817b strh r3, [r7, #10] + 8010ba6: 68fb ldr r3, [r7, #12] + 8010ba8: 781b ldrb r3, [r3, #0] + 8010baa: b29b uxth r3, r3 + 8010bac: 817b strh r3, [r7, #10] while (ptr < desc->wTotalLength) - 800f3b2: e013 b.n 800f3dc + 8010bae: e013 b.n 8010bd8 { pdesc = USBD_GetNextDesc((uint8_t *)pdesc, &ptr); - 800f3b4: f107 030a add.w r3, r7, #10 - 800f3b8: 4619 mov r1, r3 - 800f3ba: 6978 ldr r0, [r7, #20] - 800f3bc: f000 f81b bl 800f3f6 - 800f3c0: 6178 str r0, [r7, #20] + 8010bb0: f107 030a add.w r3, r7, #10 + 8010bb4: 4619 mov r1, r3 + 8010bb6: 6978 ldr r0, [r7, #20] + 8010bb8: f000 f81b bl 8010bf2 + 8010bbc: 6178 str r0, [r7, #20] if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) - 800f3c2: 697b ldr r3, [r7, #20] - 800f3c4: 785b ldrb r3, [r3, #1] - 800f3c6: 2b05 cmp r3, #5 - 800f3c8: d108 bne.n 800f3dc + 8010bbe: 697b ldr r3, [r7, #20] + 8010bc0: 785b ldrb r3, [r3, #1] + 8010bc2: 2b05 cmp r3, #5 + 8010bc4: d108 bne.n 8010bd8 { pEpDesc = (USBD_EpDescTypeDef *)(void *)pdesc; - 800f3ca: 697b ldr r3, [r7, #20] - 800f3cc: 613b str r3, [r7, #16] + 8010bc6: 697b ldr r3, [r7, #20] + 8010bc8: 613b str r3, [r7, #16] if (pEpDesc->bEndpointAddress == EpAddr) - 800f3ce: 693b ldr r3, [r7, #16] - 800f3d0: 789b ldrb r3, [r3, #2] - 800f3d2: 78fa ldrb r2, [r7, #3] - 800f3d4: 429a cmp r2, r3 - 800f3d6: d008 beq.n 800f3ea + 8010bca: 693b ldr r3, [r7, #16] + 8010bcc: 789b ldrb r3, [r3, #2] + 8010bce: 78fa ldrb r2, [r7, #3] + 8010bd0: 429a cmp r2, r3 + 8010bd2: d008 beq.n 8010be6 { break; } else { pEpDesc = NULL; - 800f3d8: 2300 movs r3, #0 - 800f3da: 613b str r3, [r7, #16] + 8010bd4: 2300 movs r3, #0 + 8010bd6: 613b str r3, [r7, #16] while (ptr < desc->wTotalLength) - 800f3dc: 68fb ldr r3, [r7, #12] - 800f3de: 885b ldrh r3, [r3, #2] - 800f3e0: b29a uxth r2, r3 - 800f3e2: 897b ldrh r3, [r7, #10] - 800f3e4: 429a cmp r2, r3 - 800f3e6: d8e5 bhi.n 800f3b4 - 800f3e8: e000 b.n 800f3ec + 8010bd8: 68fb ldr r3, [r7, #12] + 8010bda: 885b ldrh r3, [r3, #2] + 8010bdc: b29a uxth r2, r3 + 8010bde: 897b ldrh r3, [r7, #10] + 8010be0: 429a cmp r2, r3 + 8010be2: d8e5 bhi.n 8010bb0 + 8010be4: e000 b.n 8010be8 break; - 800f3ea: bf00 nop + 8010be6: bf00 nop } } } } return (void *)pEpDesc; - 800f3ec: 693b ldr r3, [r7, #16] + 8010be8: 693b ldr r3, [r7, #16] } - 800f3ee: 4618 mov r0, r3 - 800f3f0: 3718 adds r7, #24 - 800f3f2: 46bd mov sp, r7 - 800f3f4: bd80 pop {r7, pc} + 8010bea: 4618 mov r0, r3 + 8010bec: 3718 adds r7, #24 + 8010bee: 46bd mov sp, r7 + 8010bf0: bd80 pop {r7, pc} -0800f3f6 : +08010bf2 : * @param buf: Buffer where the descriptor is available * @param ptr: data pointer inside the descriptor * @retval next header */ USBD_DescHeaderTypeDef *USBD_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) { - 800f3f6: b480 push {r7} - 800f3f8: b085 sub sp, #20 - 800f3fa: af00 add r7, sp, #0 - 800f3fc: 6078 str r0, [r7, #4] - 800f3fe: 6039 str r1, [r7, #0] + 8010bf2: b480 push {r7} + 8010bf4: b085 sub sp, #20 + 8010bf6: af00 add r7, sp, #0 + 8010bf8: 6078 str r0, [r7, #4] + 8010bfa: 6039 str r1, [r7, #0] USBD_DescHeaderTypeDef *pnext = (USBD_DescHeaderTypeDef *)(void *)pbuf; - 800f400: 687b ldr r3, [r7, #4] - 800f402: 60fb str r3, [r7, #12] + 8010bfc: 687b ldr r3, [r7, #4] + 8010bfe: 60fb str r3, [r7, #12] *ptr += pnext->bLength; - 800f404: 683b ldr r3, [r7, #0] - 800f406: 881a ldrh r2, [r3, #0] - 800f408: 68fb ldr r3, [r7, #12] - 800f40a: 781b ldrb r3, [r3, #0] - 800f40c: b29b uxth r3, r3 - 800f40e: 4413 add r3, r2 - 800f410: b29a uxth r2, r3 - 800f412: 683b ldr r3, [r7, #0] - 800f414: 801a strh r2, [r3, #0] + 8010c00: 683b ldr r3, [r7, #0] + 8010c02: 881a ldrh r2, [r3, #0] + 8010c04: 68fb ldr r3, [r7, #12] + 8010c06: 781b ldrb r3, [r3, #0] + 8010c08: b29b uxth r3, r3 + 8010c0a: 4413 add r3, r2 + 8010c0c: b29a uxth r2, r3 + 8010c0e: 683b ldr r3, [r7, #0] + 8010c10: 801a strh r2, [r3, #0] pnext = (USBD_DescHeaderTypeDef *)(void *)(pbuf + pnext->bLength); - 800f416: 68fb ldr r3, [r7, #12] - 800f418: 781b ldrb r3, [r3, #0] - 800f41a: 461a mov r2, r3 - 800f41c: 687b ldr r3, [r7, #4] - 800f41e: 4413 add r3, r2 - 800f420: 60fb str r3, [r7, #12] + 8010c12: 68fb ldr r3, [r7, #12] + 8010c14: 781b ldrb r3, [r3, #0] + 8010c16: 461a mov r2, r3 + 8010c18: 687b ldr r3, [r7, #4] + 8010c1a: 4413 add r3, r2 + 8010c1c: 60fb str r3, [r7, #12] return (pnext); - 800f422: 68fb ldr r3, [r7, #12] + 8010c1e: 68fb ldr r3, [r7, #12] } - 800f424: 4618 mov r0, r3 - 800f426: 3714 adds r7, #20 - 800f428: 46bd mov sp, r7 - 800f42a: f85d 7b04 ldr.w r7, [sp], #4 - 800f42e: 4770 bx lr + 8010c20: 4618 mov r0, r3 + 8010c22: 3714 adds r7, #20 + 8010c24: 46bd mov sp, r7 + 8010c26: f85d 7b04 ldr.w r7, [sp], #4 + 8010c2a: 4770 bx lr -0800f430 : +08010c2c : /** @defgroup USBD_DEF_Exported_Macros * @{ */ __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) { - 800f430: b480 push {r7} - 800f432: b087 sub sp, #28 - 800f434: af00 add r7, sp, #0 - 800f436: 6078 str r0, [r7, #4] + 8010c2c: b480 push {r7} + 8010c2e: b087 sub sp, #28 + 8010c30: af00 add r7, sp, #0 + 8010c32: 6078 str r0, [r7, #4] uint16_t _SwapVal; uint16_t _Byte1; uint16_t _Byte2; uint8_t *_pbuff = addr; - 800f438: 687b ldr r3, [r7, #4] - 800f43a: 617b str r3, [r7, #20] + 8010c34: 687b ldr r3, [r7, #4] + 8010c36: 617b str r3, [r7, #20] _Byte1 = *(uint8_t *)_pbuff; - 800f43c: 697b ldr r3, [r7, #20] - 800f43e: 781b ldrb r3, [r3, #0] - 800f440: 827b strh r3, [r7, #18] + 8010c38: 697b ldr r3, [r7, #20] + 8010c3a: 781b ldrb r3, [r3, #0] + 8010c3c: 827b strh r3, [r7, #18] _pbuff++; - 800f442: 697b ldr r3, [r7, #20] - 800f444: 3301 adds r3, #1 - 800f446: 617b str r3, [r7, #20] + 8010c3e: 697b ldr r3, [r7, #20] + 8010c40: 3301 adds r3, #1 + 8010c42: 617b str r3, [r7, #20] _Byte2 = *(uint8_t *)_pbuff; - 800f448: 697b ldr r3, [r7, #20] - 800f44a: 781b ldrb r3, [r3, #0] - 800f44c: 823b strh r3, [r7, #16] + 8010c44: 697b ldr r3, [r7, #20] + 8010c46: 781b ldrb r3, [r3, #0] + 8010c48: 823b strh r3, [r7, #16] _SwapVal = (_Byte2 << 8) | _Byte1; - 800f44e: 8a3b ldrh r3, [r7, #16] - 800f450: 021b lsls r3, r3, #8 - 800f452: b21a sxth r2, r3 - 800f454: f9b7 3012 ldrsh.w r3, [r7, #18] - 800f458: 4313 orrs r3, r2 - 800f45a: b21b sxth r3, r3 - 800f45c: 81fb strh r3, [r7, #14] + 8010c4a: 8a3b ldrh r3, [r7, #16] + 8010c4c: 021b lsls r3, r3, #8 + 8010c4e: b21a sxth r2, r3 + 8010c50: f9b7 3012 ldrsh.w r3, [r7, #18] + 8010c54: 4313 orrs r3, r2 + 8010c56: b21b sxth r3, r3 + 8010c58: 81fb strh r3, [r7, #14] return _SwapVal; - 800f45e: 89fb ldrh r3, [r7, #14] + 8010c5a: 89fb ldrh r3, [r7, #14] } - 800f460: 4618 mov r0, r3 - 800f462: 371c adds r7, #28 - 800f464: 46bd mov sp, r7 - 800f466: f85d 7b04 ldr.w r7, [sp], #4 - 800f46a: 4770 bx lr + 8010c5c: 4618 mov r0, r3 + 8010c5e: 371c adds r7, #28 + 8010c60: 46bd mov sp, r7 + 8010c62: f85d 7b04 ldr.w r7, [sp], #4 + 8010c66: 4770 bx lr -0800f46c : +08010c68 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800f46c: b580 push {r7, lr} - 800f46e: b084 sub sp, #16 - 800f470: af00 add r7, sp, #0 - 800f472: 6078 str r0, [r7, #4] - 800f474: 6039 str r1, [r7, #0] + 8010c68: b580 push {r7, lr} + 8010c6a: b084 sub sp, #16 + 8010c6c: af00 add r7, sp, #0 + 8010c6e: 6078 str r0, [r7, #4] + 8010c70: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; - 800f476: 2300 movs r3, #0 - 800f478: 73fb strb r3, [r7, #15] + 8010c72: 2300 movs r3, #0 + 8010c74: 73fb strb r3, [r7, #15] switch (req->bmRequest & USB_REQ_TYPE_MASK) - 800f47a: 683b ldr r3, [r7, #0] - 800f47c: 781b ldrb r3, [r3, #0] - 800f47e: f003 0360 and.w r3, r3, #96 ; 0x60 - 800f482: 2b40 cmp r3, #64 ; 0x40 - 800f484: d005 beq.n 800f492 - 800f486: 2b40 cmp r3, #64 ; 0x40 - 800f488: d857 bhi.n 800f53a - 800f48a: 2b00 cmp r3, #0 - 800f48c: d00f beq.n 800f4ae - 800f48e: 2b20 cmp r3, #32 - 800f490: d153 bne.n 800f53a + 8010c76: 683b ldr r3, [r7, #0] + 8010c78: 781b ldrb r3, [r3, #0] + 8010c7a: f003 0360 and.w r3, r3, #96 ; 0x60 + 8010c7e: 2b40 cmp r3, #64 ; 0x40 + 8010c80: d005 beq.n 8010c8e + 8010c82: 2b40 cmp r3, #64 ; 0x40 + 8010c84: d857 bhi.n 8010d36 + 8010c86: 2b00 cmp r3, #0 + 8010c88: d00f beq.n 8010caa + 8010c8a: 2b20 cmp r3, #32 + 8010c8c: d153 bne.n 8010d36 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: ret = (USBD_StatusTypeDef)pdev->pClass[pdev->classId]->Setup(pdev, req); - 800f492: 687b ldr r3, [r7, #4] - 800f494: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 - 800f498: 687b ldr r3, [r7, #4] - 800f49a: 32ae adds r2, #174 ; 0xae - 800f49c: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f4a0: 689b ldr r3, [r3, #8] - 800f4a2: 6839 ldr r1, [r7, #0] - 800f4a4: 6878 ldr r0, [r7, #4] - 800f4a6: 4798 blx r3 - 800f4a8: 4603 mov r3, r0 - 800f4aa: 73fb strb r3, [r7, #15] + 8010c8e: 687b ldr r3, [r7, #4] + 8010c90: f8d3 22d4 ldr.w r2, [r3, #724] ; 0x2d4 + 8010c94: 687b ldr r3, [r7, #4] + 8010c96: 32ae adds r2, #174 ; 0xae + 8010c98: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010c9c: 689b ldr r3, [r3, #8] + 8010c9e: 6839 ldr r1, [r7, #0] + 8010ca0: 6878 ldr r0, [r7, #4] + 8010ca2: 4798 blx r3 + 8010ca4: 4603 mov r3, r0 + 8010ca6: 73fb strb r3, [r7, #15] break; - 800f4ac: e04a b.n 800f544 + 8010ca8: e04a b.n 8010d40 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) - 800f4ae: 683b ldr r3, [r7, #0] - 800f4b0: 785b ldrb r3, [r3, #1] - 800f4b2: 2b09 cmp r3, #9 - 800f4b4: d83b bhi.n 800f52e - 800f4b6: a201 add r2, pc, #4 ; (adr r2, 800f4bc ) - 800f4b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800f4bc: 0800f511 .word 0x0800f511 - 800f4c0: 0800f525 .word 0x0800f525 - 800f4c4: 0800f52f .word 0x0800f52f - 800f4c8: 0800f51b .word 0x0800f51b - 800f4cc: 0800f52f .word 0x0800f52f - 800f4d0: 0800f4ef .word 0x0800f4ef - 800f4d4: 0800f4e5 .word 0x0800f4e5 - 800f4d8: 0800f52f .word 0x0800f52f - 800f4dc: 0800f507 .word 0x0800f507 - 800f4e0: 0800f4f9 .word 0x0800f4f9 + 8010caa: 683b ldr r3, [r7, #0] + 8010cac: 785b ldrb r3, [r3, #1] + 8010cae: 2b09 cmp r3, #9 + 8010cb0: d83b bhi.n 8010d2a + 8010cb2: a201 add r2, pc, #4 ; (adr r2, 8010cb8 ) + 8010cb4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8010cb8: 08010d0d .word 0x08010d0d + 8010cbc: 08010d21 .word 0x08010d21 + 8010cc0: 08010d2b .word 0x08010d2b + 8010cc4: 08010d17 .word 0x08010d17 + 8010cc8: 08010d2b .word 0x08010d2b + 8010ccc: 08010ceb .word 0x08010ceb + 8010cd0: 08010ce1 .word 0x08010ce1 + 8010cd4: 08010d2b .word 0x08010d2b + 8010cd8: 08010d03 .word 0x08010d03 + 8010cdc: 08010cf5 .word 0x08010cf5 { case USB_REQ_GET_DESCRIPTOR: USBD_GetDescriptor(pdev, req); - 800f4e4: 6839 ldr r1, [r7, #0] - 800f4e6: 6878 ldr r0, [r7, #4] - 800f4e8: f000 fa3c bl 800f964 + 8010ce0: 6839 ldr r1, [r7, #0] + 8010ce2: 6878 ldr r0, [r7, #4] + 8010ce4: f000 fa3c bl 8011160 break; - 800f4ec: e024 b.n 800f538 + 8010ce8: e024 b.n 8010d34 case USB_REQ_SET_ADDRESS: USBD_SetAddress(pdev, req); - 800f4ee: 6839 ldr r1, [r7, #0] - 800f4f0: 6878 ldr r0, [r7, #4] - 800f4f2: f000 fbcb bl 800fc8c + 8010cea: 6839 ldr r1, [r7, #0] + 8010cec: 6878 ldr r0, [r7, #4] + 8010cee: f000 fbcb bl 8011488 break; - 800f4f6: e01f b.n 800f538 + 8010cf2: e01f b.n 8010d34 case USB_REQ_SET_CONFIGURATION: ret = USBD_SetConfig(pdev, req); - 800f4f8: 6839 ldr r1, [r7, #0] - 800f4fa: 6878 ldr r0, [r7, #4] - 800f4fc: f000 fc0a bl 800fd14 - 800f500: 4603 mov r3, r0 - 800f502: 73fb strb r3, [r7, #15] + 8010cf4: 6839 ldr r1, [r7, #0] + 8010cf6: 6878 ldr r0, [r7, #4] + 8010cf8: f000 fc0a bl 8011510 + 8010cfc: 4603 mov r3, r0 + 8010cfe: 73fb strb r3, [r7, #15] break; - 800f504: e018 b.n 800f538 + 8010d00: e018 b.n 8010d34 case USB_REQ_GET_CONFIGURATION: USBD_GetConfig(pdev, req); - 800f506: 6839 ldr r1, [r7, #0] - 800f508: 6878 ldr r0, [r7, #4] - 800f50a: f000 fcad bl 800fe68 + 8010d02: 6839 ldr r1, [r7, #0] + 8010d04: 6878 ldr r0, [r7, #4] + 8010d06: f000 fcad bl 8011664 break; - 800f50e: e013 b.n 800f538 + 8010d0a: e013 b.n 8010d34 case USB_REQ_GET_STATUS: USBD_GetStatus(pdev, req); - 800f510: 6839 ldr r1, [r7, #0] - 800f512: 6878 ldr r0, [r7, #4] - 800f514: f000 fcde bl 800fed4 + 8010d0c: 6839 ldr r1, [r7, #0] + 8010d0e: 6878 ldr r0, [r7, #4] + 8010d10: f000 fcde bl 80116d0 break; - 800f518: e00e b.n 800f538 + 8010d14: e00e b.n 8010d34 case USB_REQ_SET_FEATURE: USBD_SetFeature(pdev, req); - 800f51a: 6839 ldr r1, [r7, #0] - 800f51c: 6878 ldr r0, [r7, #4] - 800f51e: f000 fd0d bl 800ff3c + 8010d16: 6839 ldr r1, [r7, #0] + 8010d18: 6878 ldr r0, [r7, #4] + 8010d1a: f000 fd0d bl 8011738 break; - 800f522: e009 b.n 800f538 + 8010d1e: e009 b.n 8010d34 case USB_REQ_CLEAR_FEATURE: USBD_ClrFeature(pdev, req); - 800f524: 6839 ldr r1, [r7, #0] - 800f526: 6878 ldr r0, [r7, #4] - 800f528: f000 fd31 bl 800ff8e + 8010d20: 6839 ldr r1, [r7, #0] + 8010d22: 6878 ldr r0, [r7, #4] + 8010d24: f000 fd31 bl 801178a break; - 800f52c: e004 b.n 800f538 + 8010d28: e004 b.n 8010d34 default: USBD_CtlError(pdev, req); - 800f52e: 6839 ldr r1, [r7, #0] - 800f530: 6878 ldr r0, [r7, #4] - 800f532: f000 fd88 bl 8010046 + 8010d2a: 6839 ldr r1, [r7, #0] + 8010d2c: 6878 ldr r0, [r7, #4] + 8010d2e: f000 fd88 bl 8011842 break; - 800f536: bf00 nop + 8010d32: bf00 nop } break; - 800f538: e004 b.n 800f544 + 8010d34: e004 b.n 8010d40 default: USBD_CtlError(pdev, req); - 800f53a: 6839 ldr r1, [r7, #0] - 800f53c: 6878 ldr r0, [r7, #4] - 800f53e: f000 fd82 bl 8010046 + 8010d36: 6839 ldr r1, [r7, #0] + 8010d38: 6878 ldr r0, [r7, #4] + 8010d3a: f000 fd82 bl 8011842 break; - 800f542: bf00 nop + 8010d3e: bf00 nop } return ret; - 800f544: 7bfb ldrb r3, [r7, #15] + 8010d40: 7bfb ldrb r3, [r7, #15] } - 800f546: 4618 mov r0, r3 - 800f548: 3710 adds r7, #16 - 800f54a: 46bd mov sp, r7 - 800f54c: bd80 pop {r7, pc} - 800f54e: bf00 nop + 8010d42: 4618 mov r0, r3 + 8010d44: 3710 adds r7, #16 + 8010d46: 46bd mov sp, r7 + 8010d48: bd80 pop {r7, pc} + 8010d4a: bf00 nop -0800f550 : +08010d4c : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800f550: b580 push {r7, lr} - 800f552: b084 sub sp, #16 - 800f554: af00 add r7, sp, #0 - 800f556: 6078 str r0, [r7, #4] - 800f558: 6039 str r1, [r7, #0] + 8010d4c: b580 push {r7, lr} + 8010d4e: b084 sub sp, #16 + 8010d50: af00 add r7, sp, #0 + 8010d52: 6078 str r0, [r7, #4] + 8010d54: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; - 800f55a: 2300 movs r3, #0 - 800f55c: 73fb strb r3, [r7, #15] + 8010d56: 2300 movs r3, #0 + 8010d58: 73fb strb r3, [r7, #15] uint8_t idx; switch (req->bmRequest & USB_REQ_TYPE_MASK) - 800f55e: 683b ldr r3, [r7, #0] - 800f560: 781b ldrb r3, [r3, #0] - 800f562: f003 0360 and.w r3, r3, #96 ; 0x60 - 800f566: 2b40 cmp r3, #64 ; 0x40 - 800f568: d005 beq.n 800f576 - 800f56a: 2b40 cmp r3, #64 ; 0x40 - 800f56c: d852 bhi.n 800f614 - 800f56e: 2b00 cmp r3, #0 - 800f570: d001 beq.n 800f576 - 800f572: 2b20 cmp r3, #32 - 800f574: d14e bne.n 800f614 + 8010d5a: 683b ldr r3, [r7, #0] + 8010d5c: 781b ldrb r3, [r3, #0] + 8010d5e: f003 0360 and.w r3, r3, #96 ; 0x60 + 8010d62: 2b40 cmp r3, #64 ; 0x40 + 8010d64: d005 beq.n 8010d72 + 8010d66: 2b40 cmp r3, #64 ; 0x40 + 8010d68: d852 bhi.n 8010e10 + 8010d6a: 2b00 cmp r3, #0 + 8010d6c: d001 beq.n 8010d72 + 8010d6e: 2b20 cmp r3, #32 + 8010d70: d14e bne.n 8010e10 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: case USB_REQ_TYPE_STANDARD: switch (pdev->dev_state) - 800f576: 687b ldr r3, [r7, #4] - 800f578: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f57c: b2db uxtb r3, r3 - 800f57e: 3b01 subs r3, #1 - 800f580: 2b02 cmp r3, #2 - 800f582: d840 bhi.n 800f606 + 8010d72: 687b ldr r3, [r7, #4] + 8010d74: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010d78: b2db uxtb r3, r3 + 8010d7a: 3b01 subs r3, #1 + 8010d7c: 2b02 cmp r3, #2 + 8010d7e: d840 bhi.n 8010e02 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) - 800f584: 683b ldr r3, [r7, #0] - 800f586: 889b ldrh r3, [r3, #4] - 800f588: b2db uxtb r3, r3 - 800f58a: 2b01 cmp r3, #1 - 800f58c: d836 bhi.n 800f5fc + 8010d80: 683b ldr r3, [r7, #0] + 8010d82: 889b ldrh r3, [r3, #4] + 8010d84: b2db uxtb r3, r3 + 8010d86: 2b01 cmp r3, #1 + 8010d88: d836 bhi.n 8010df8 { /* Get the class index relative to this interface */ idx = USBD_CoreFindIF(pdev, LOBYTE(req->wIndex)); - 800f58e: 683b ldr r3, [r7, #0] - 800f590: 889b ldrh r3, [r3, #4] - 800f592: b2db uxtb r3, r3 - 800f594: 4619 mov r1, r3 - 800f596: 6878 ldr r0, [r7, #4] - 800f598: f7ff fed9 bl 800f34e - 800f59c: 4603 mov r3, r0 - 800f59e: 73bb strb r3, [r7, #14] + 8010d8a: 683b ldr r3, [r7, #0] + 8010d8c: 889b ldrh r3, [r3, #4] + 8010d8e: b2db uxtb r3, r3 + 8010d90: 4619 mov r1, r3 + 8010d92: 6878 ldr r0, [r7, #4] + 8010d94: f7ff fed9 bl 8010b4a + 8010d98: 4603 mov r3, r0 + 8010d9a: 73bb strb r3, [r7, #14] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) - 800f5a0: 7bbb ldrb r3, [r7, #14] - 800f5a2: 2bff cmp r3, #255 ; 0xff - 800f5a4: d01d beq.n 800f5e2 - 800f5a6: 7bbb ldrb r3, [r7, #14] - 800f5a8: 2b00 cmp r3, #0 - 800f5aa: d11a bne.n 800f5e2 + 8010d9c: 7bbb ldrb r3, [r7, #14] + 8010d9e: 2bff cmp r3, #255 ; 0xff + 8010da0: d01d beq.n 8010dde + 8010da2: 7bbb ldrb r3, [r7, #14] + 8010da4: 2b00 cmp r3, #0 + 8010da6: d11a bne.n 8010dde { /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) - 800f5ac: 7bba ldrb r2, [r7, #14] - 800f5ae: 687b ldr r3, [r7, #4] - 800f5b0: 32ae adds r2, #174 ; 0xae - 800f5b2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f5b6: 689b ldr r3, [r3, #8] - 800f5b8: 2b00 cmp r3, #0 - 800f5ba: d00f beq.n 800f5dc + 8010da8: 7bba ldrb r2, [r7, #14] + 8010daa: 687b ldr r3, [r7, #4] + 8010dac: 32ae adds r2, #174 ; 0xae + 8010dae: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010db2: 689b ldr r3, [r3, #8] + 8010db4: 2b00 cmp r3, #0 + 8010db6: d00f beq.n 8010dd8 { pdev->classId = idx; - 800f5bc: 7bba ldrb r2, [r7, #14] - 800f5be: 687b ldr r3, [r7, #4] - 800f5c0: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 8010db8: 7bba ldrb r2, [r7, #14] + 8010dba: 687b ldr r3, [r7, #4] + 8010dbc: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); - 800f5c4: 7bba ldrb r2, [r7, #14] - 800f5c6: 687b ldr r3, [r7, #4] - 800f5c8: 32ae adds r2, #174 ; 0xae - 800f5ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f5ce: 689b ldr r3, [r3, #8] - 800f5d0: 6839 ldr r1, [r7, #0] - 800f5d2: 6878 ldr r0, [r7, #4] - 800f5d4: 4798 blx r3 - 800f5d6: 4603 mov r3, r0 - 800f5d8: 73fb strb r3, [r7, #15] + 8010dc0: 7bba ldrb r2, [r7, #14] + 8010dc2: 687b ldr r3, [r7, #4] + 8010dc4: 32ae adds r2, #174 ; 0xae + 8010dc6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010dca: 689b ldr r3, [r3, #8] + 8010dcc: 6839 ldr r1, [r7, #0] + 8010dce: 6878 ldr r0, [r7, #4] + 8010dd0: 4798 blx r3 + 8010dd2: 4603 mov r3, r0 + 8010dd4: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) - 800f5da: e004 b.n 800f5e6 + 8010dd6: e004 b.n 8010de2 } else { /* should never reach this condition */ ret = USBD_FAIL; - 800f5dc: 2303 movs r3, #3 - 800f5de: 73fb strb r3, [r7, #15] + 8010dd8: 2303 movs r3, #3 + 8010dda: 73fb strb r3, [r7, #15] if (pdev->pClass[idx]->Setup != NULL) - 800f5e0: e001 b.n 800f5e6 + 8010ddc: e001 b.n 8010de2 } } else { /* No relative interface found */ ret = USBD_FAIL; - 800f5e2: 2303 movs r3, #3 - 800f5e4: 73fb strb r3, [r7, #15] + 8010dde: 2303 movs r3, #3 + 8010de0: 73fb strb r3, [r7, #15] } if ((req->wLength == 0U) && (ret == USBD_OK)) - 800f5e6: 683b ldr r3, [r7, #0] - 800f5e8: 88db ldrh r3, [r3, #6] - 800f5ea: 2b00 cmp r3, #0 - 800f5ec: d110 bne.n 800f610 - 800f5ee: 7bfb ldrb r3, [r7, #15] - 800f5f0: 2b00 cmp r3, #0 - 800f5f2: d10d bne.n 800f610 + 8010de2: 683b ldr r3, [r7, #0] + 8010de4: 88db ldrh r3, [r3, #6] + 8010de6: 2b00 cmp r3, #0 + 8010de8: d110 bne.n 8010e0c + 8010dea: 7bfb ldrb r3, [r7, #15] + 8010dec: 2b00 cmp r3, #0 + 8010dee: d10d bne.n 8010e0c { (void)USBD_CtlSendStatus(pdev); - 800f5f4: 6878 ldr r0, [r7, #4] - 800f5f6: f000 fdd4 bl 80101a2 + 8010df0: 6878 ldr r0, [r7, #4] + 8010df2: f000 fdf1 bl 80119d8 } else { USBD_CtlError(pdev, req); } break; - 800f5fa: e009 b.n 800f610 + 8010df6: e009 b.n 8010e0c USBD_CtlError(pdev, req); - 800f5fc: 6839 ldr r1, [r7, #0] - 800f5fe: 6878 ldr r0, [r7, #4] - 800f600: f000 fd21 bl 8010046 + 8010df8: 6839 ldr r1, [r7, #0] + 8010dfa: 6878 ldr r0, [r7, #4] + 8010dfc: f000 fd21 bl 8011842 break; - 800f604: e004 b.n 800f610 + 8010e00: e004 b.n 8010e0c default: USBD_CtlError(pdev, req); - 800f606: 6839 ldr r1, [r7, #0] - 800f608: 6878 ldr r0, [r7, #4] - 800f60a: f000 fd1c bl 8010046 + 8010e02: 6839 ldr r1, [r7, #0] + 8010e04: 6878 ldr r0, [r7, #4] + 8010e06: f000 fd1c bl 8011842 break; - 800f60e: e000 b.n 800f612 + 8010e0a: e000 b.n 8010e0e break; - 800f610: bf00 nop + 8010e0c: bf00 nop } break; - 800f612: e004 b.n 800f61e + 8010e0e: e004 b.n 8010e1a default: USBD_CtlError(pdev, req); - 800f614: 6839 ldr r1, [r7, #0] - 800f616: 6878 ldr r0, [r7, #4] - 800f618: f000 fd15 bl 8010046 + 8010e10: 6839 ldr r1, [r7, #0] + 8010e12: 6878 ldr r0, [r7, #4] + 8010e14: f000 fd15 bl 8011842 break; - 800f61c: bf00 nop + 8010e18: bf00 nop } return ret; - 800f61e: 7bfb ldrb r3, [r7, #15] + 8010e1a: 7bfb ldrb r3, [r7, #15] } - 800f620: 4618 mov r0, r3 - 800f622: 3710 adds r7, #16 - 800f624: 46bd mov sp, r7 - 800f626: bd80 pop {r7, pc} + 8010e1c: 4618 mov r0, r3 + 8010e1e: 3710 adds r7, #16 + 8010e20: 46bd mov sp, r7 + 8010e22: bd80 pop {r7, pc} -0800f628 : +08010e24 : * @param pdev: device instance * @param req: usb request * @retval status */ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800f628: b580 push {r7, lr} - 800f62a: b084 sub sp, #16 - 800f62c: af00 add r7, sp, #0 - 800f62e: 6078 str r0, [r7, #4] - 800f630: 6039 str r1, [r7, #0] + 8010e24: b580 push {r7, lr} + 8010e26: b084 sub sp, #16 + 8010e28: af00 add r7, sp, #0 + 8010e2a: 6078 str r0, [r7, #4] + 8010e2c: 6039 str r1, [r7, #0] USBD_EndpointTypeDef *pep; uint8_t ep_addr; uint8_t idx; USBD_StatusTypeDef ret = USBD_OK; - 800f632: 2300 movs r3, #0 - 800f634: 73fb strb r3, [r7, #15] + 8010e2e: 2300 movs r3, #0 + 8010e30: 73fb strb r3, [r7, #15] ep_addr = LOBYTE(req->wIndex); - 800f636: 683b ldr r3, [r7, #0] - 800f638: 889b ldrh r3, [r3, #4] - 800f63a: 73bb strb r3, [r7, #14] + 8010e32: 683b ldr r3, [r7, #0] + 8010e34: 889b ldrh r3, [r3, #4] + 8010e36: 73bb strb r3, [r7, #14] switch (req->bmRequest & USB_REQ_TYPE_MASK) - 800f63c: 683b ldr r3, [r7, #0] - 800f63e: 781b ldrb r3, [r3, #0] - 800f640: f003 0360 and.w r3, r3, #96 ; 0x60 - 800f644: 2b40 cmp r3, #64 ; 0x40 - 800f646: d007 beq.n 800f658 - 800f648: 2b40 cmp r3, #64 ; 0x40 - 800f64a: f200 817f bhi.w 800f94c - 800f64e: 2b00 cmp r3, #0 - 800f650: d02a beq.n 800f6a8 - 800f652: 2b20 cmp r3, #32 - 800f654: f040 817a bne.w 800f94c + 8010e38: 683b ldr r3, [r7, #0] + 8010e3a: 781b ldrb r3, [r3, #0] + 8010e3c: f003 0360 and.w r3, r3, #96 ; 0x60 + 8010e40: 2b40 cmp r3, #64 ; 0x40 + 8010e42: d007 beq.n 8010e54 + 8010e44: 2b40 cmp r3, #64 ; 0x40 + 8010e46: f200 817f bhi.w 8011148 + 8010e4a: 2b00 cmp r3, #0 + 8010e4c: d02a beq.n 8010ea4 + 8010e4e: 2b20 cmp r3, #32 + 8010e50: f040 817a bne.w 8011148 { case USB_REQ_TYPE_CLASS: case USB_REQ_TYPE_VENDOR: /* Get the class index relative to this endpoint */ idx = USBD_CoreFindEP(pdev, ep_addr); - 800f658: 7bbb ldrb r3, [r7, #14] - 800f65a: 4619 mov r1, r3 - 800f65c: 6878 ldr r0, [r7, #4] - 800f65e: f7ff fe83 bl 800f368 - 800f662: 4603 mov r3, r0 - 800f664: 737b strb r3, [r7, #13] + 8010e54: 7bbb ldrb r3, [r7, #14] + 8010e56: 4619 mov r1, r3 + 8010e58: 6878 ldr r0, [r7, #4] + 8010e5a: f7ff fe83 bl 8010b64 + 8010e5e: 4603 mov r3, r0 + 8010e60: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) - 800f666: 7b7b ldrb r3, [r7, #13] - 800f668: 2bff cmp r3, #255 ; 0xff - 800f66a: f000 8174 beq.w 800f956 - 800f66e: 7b7b ldrb r3, [r7, #13] - 800f670: 2b00 cmp r3, #0 - 800f672: f040 8170 bne.w 800f956 + 8010e62: 7b7b ldrb r3, [r7, #13] + 8010e64: 2bff cmp r3, #255 ; 0xff + 8010e66: f000 8174 beq.w 8011152 + 8010e6a: 7b7b ldrb r3, [r7, #13] + 8010e6c: 2b00 cmp r3, #0 + 8010e6e: f040 8170 bne.w 8011152 { pdev->classId = idx; - 800f676: 7b7a ldrb r2, [r7, #13] - 800f678: 687b ldr r3, [r7, #4] - 800f67a: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 8010e72: 7b7a ldrb r2, [r7, #13] + 8010e74: 687b ldr r3, [r7, #4] + 8010e76: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) - 800f67e: 7b7a ldrb r2, [r7, #13] - 800f680: 687b ldr r3, [r7, #4] - 800f682: 32ae adds r2, #174 ; 0xae - 800f684: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f688: 689b ldr r3, [r3, #8] - 800f68a: 2b00 cmp r3, #0 - 800f68c: f000 8163 beq.w 800f956 + 8010e7a: 7b7a ldrb r2, [r7, #13] + 8010e7c: 687b ldr r3, [r7, #4] + 8010e7e: 32ae adds r2, #174 ; 0xae + 8010e80: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010e84: 689b ldr r3, [r3, #8] + 8010e86: 2b00 cmp r3, #0 + 8010e88: f000 8163 beq.w 8011152 { ret = (USBD_StatusTypeDef)pdev->pClass[idx]->Setup(pdev, req); - 800f690: 7b7a ldrb r2, [r7, #13] - 800f692: 687b ldr r3, [r7, #4] - 800f694: 32ae adds r2, #174 ; 0xae - 800f696: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f69a: 689b ldr r3, [r3, #8] - 800f69c: 6839 ldr r1, [r7, #0] - 800f69e: 6878 ldr r0, [r7, #4] - 800f6a0: 4798 blx r3 - 800f6a2: 4603 mov r3, r0 - 800f6a4: 73fb strb r3, [r7, #15] + 8010e8c: 7b7a ldrb r2, [r7, #13] + 8010e8e: 687b ldr r3, [r7, #4] + 8010e90: 32ae adds r2, #174 ; 0xae + 8010e92: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010e96: 689b ldr r3, [r3, #8] + 8010e98: 6839 ldr r1, [r7, #0] + 8010e9a: 6878 ldr r0, [r7, #4] + 8010e9c: 4798 blx r3 + 8010e9e: 4603 mov r3, r0 + 8010ea0: 73fb strb r3, [r7, #15] } } break; - 800f6a6: e156 b.n 800f956 + 8010ea2: e156 b.n 8011152 case USB_REQ_TYPE_STANDARD: switch (req->bRequest) - 800f6a8: 683b ldr r3, [r7, #0] - 800f6aa: 785b ldrb r3, [r3, #1] - 800f6ac: 2b03 cmp r3, #3 - 800f6ae: d008 beq.n 800f6c2 - 800f6b0: 2b03 cmp r3, #3 - 800f6b2: f300 8145 bgt.w 800f940 - 800f6b6: 2b00 cmp r3, #0 - 800f6b8: f000 809b beq.w 800f7f2 - 800f6bc: 2b01 cmp r3, #1 - 800f6be: d03c beq.n 800f73a - 800f6c0: e13e b.n 800f940 + 8010ea4: 683b ldr r3, [r7, #0] + 8010ea6: 785b ldrb r3, [r3, #1] + 8010ea8: 2b03 cmp r3, #3 + 8010eaa: d008 beq.n 8010ebe + 8010eac: 2b03 cmp r3, #3 + 8010eae: f300 8145 bgt.w 801113c + 8010eb2: 2b00 cmp r3, #0 + 8010eb4: f000 809b beq.w 8010fee + 8010eb8: 2b01 cmp r3, #1 + 8010eba: d03c beq.n 8010f36 + 8010ebc: e13e b.n 801113c { case USB_REQ_SET_FEATURE: switch (pdev->dev_state) - 800f6c2: 687b ldr r3, [r7, #4] - 800f6c4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f6c8: b2db uxtb r3, r3 - 800f6ca: 2b02 cmp r3, #2 - 800f6cc: d002 beq.n 800f6d4 - 800f6ce: 2b03 cmp r3, #3 - 800f6d0: d016 beq.n 800f700 - 800f6d2: e02c b.n 800f72e + 8010ebe: 687b ldr r3, [r7, #4] + 8010ec0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010ec4: b2db uxtb r3, r3 + 8010ec6: 2b02 cmp r3, #2 + 8010ec8: d002 beq.n 8010ed0 + 8010eca: 2b03 cmp r3, #3 + 8010ecc: d016 beq.n 8010efc + 8010ece: e02c b.n 8010f2a { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - 800f6d4: 7bbb ldrb r3, [r7, #14] - 800f6d6: 2b00 cmp r3, #0 - 800f6d8: d00d beq.n 800f6f6 - 800f6da: 7bbb ldrb r3, [r7, #14] - 800f6dc: 2b80 cmp r3, #128 ; 0x80 - 800f6de: d00a beq.n 800f6f6 + 8010ed0: 7bbb ldrb r3, [r7, #14] + 8010ed2: 2b00 cmp r3, #0 + 8010ed4: d00d beq.n 8010ef2 + 8010ed6: 7bbb ldrb r3, [r7, #14] + 8010ed8: 2b80 cmp r3, #128 ; 0x80 + 8010eda: d00a beq.n 8010ef2 { (void)USBD_LL_StallEP(pdev, ep_addr); - 800f6e0: 7bbb ldrb r3, [r7, #14] - 800f6e2: 4619 mov r1, r3 - 800f6e4: 6878 ldr r0, [r7, #4] - 800f6e6: f001 f891 bl 801080c + 8010edc: 7bbb ldrb r3, [r7, #14] + 8010ede: 4619 mov r1, r3 + 8010ee0: 6878 ldr r0, [r7, #4] + 8010ee2: f001 fed3 bl 8012c8c (void)USBD_LL_StallEP(pdev, 0x80U); - 800f6ea: 2180 movs r1, #128 ; 0x80 - 800f6ec: 6878 ldr r0, [r7, #4] - 800f6ee: f001 f88d bl 801080c - 800f6f2: bf00 nop + 8010ee6: 2180 movs r1, #128 ; 0x80 + 8010ee8: 6878 ldr r0, [r7, #4] + 8010eea: f001 fecf bl 8012c8c + 8010eee: bf00 nop } else { USBD_CtlError(pdev, req); } break; - 800f6f4: e020 b.n 800f738 + 8010ef0: e020 b.n 8010f34 USBD_CtlError(pdev, req); - 800f6f6: 6839 ldr r1, [r7, #0] - 800f6f8: 6878 ldr r0, [r7, #4] - 800f6fa: f000 fca4 bl 8010046 + 8010ef2: 6839 ldr r1, [r7, #0] + 8010ef4: 6878 ldr r0, [r7, #4] + 8010ef6: f000 fca4 bl 8011842 break; - 800f6fe: e01b b.n 800f738 + 8010efa: e01b b.n 8010f34 case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) - 800f700: 683b ldr r3, [r7, #0] - 800f702: 885b ldrh r3, [r3, #2] - 800f704: 2b00 cmp r3, #0 - 800f706: d10e bne.n 800f726 + 8010efc: 683b ldr r3, [r7, #0] + 8010efe: 885b ldrh r3, [r3, #2] + 8010f00: 2b00 cmp r3, #0 + 8010f02: d10e bne.n 8010f22 { if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) - 800f708: 7bbb ldrb r3, [r7, #14] - 800f70a: 2b00 cmp r3, #0 - 800f70c: d00b beq.n 800f726 - 800f70e: 7bbb ldrb r3, [r7, #14] - 800f710: 2b80 cmp r3, #128 ; 0x80 - 800f712: d008 beq.n 800f726 - 800f714: 683b ldr r3, [r7, #0] - 800f716: 88db ldrh r3, [r3, #6] - 800f718: 2b00 cmp r3, #0 - 800f71a: d104 bne.n 800f726 + 8010f04: 7bbb ldrb r3, [r7, #14] + 8010f06: 2b00 cmp r3, #0 + 8010f08: d00b beq.n 8010f22 + 8010f0a: 7bbb ldrb r3, [r7, #14] + 8010f0c: 2b80 cmp r3, #128 ; 0x80 + 8010f0e: d008 beq.n 8010f22 + 8010f10: 683b ldr r3, [r7, #0] + 8010f12: 88db ldrh r3, [r3, #6] + 8010f14: 2b00 cmp r3, #0 + 8010f16: d104 bne.n 8010f22 { (void)USBD_LL_StallEP(pdev, ep_addr); - 800f71c: 7bbb ldrb r3, [r7, #14] - 800f71e: 4619 mov r1, r3 - 800f720: 6878 ldr r0, [r7, #4] - 800f722: f001 f873 bl 801080c + 8010f18: 7bbb ldrb r3, [r7, #14] + 8010f1a: 4619 mov r1, r3 + 8010f1c: 6878 ldr r0, [r7, #4] + 8010f1e: f001 feb5 bl 8012c8c } } (void)USBD_CtlSendStatus(pdev); - 800f726: 6878 ldr r0, [r7, #4] - 800f728: f000 fd3b bl 80101a2 + 8010f22: 6878 ldr r0, [r7, #4] + 8010f24: f000 fd58 bl 80119d8 break; - 800f72c: e004 b.n 800f738 + 8010f28: e004 b.n 8010f34 default: USBD_CtlError(pdev, req); - 800f72e: 6839 ldr r1, [r7, #0] - 800f730: 6878 ldr r0, [r7, #4] - 800f732: f000 fc88 bl 8010046 + 8010f2a: 6839 ldr r1, [r7, #0] + 8010f2c: 6878 ldr r0, [r7, #4] + 8010f2e: f000 fc88 bl 8011842 break; - 800f736: bf00 nop + 8010f32: bf00 nop } break; - 800f738: e107 b.n 800f94a + 8010f34: e107 b.n 8011146 case USB_REQ_CLEAR_FEATURE: switch (pdev->dev_state) - 800f73a: 687b ldr r3, [r7, #4] - 800f73c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f740: b2db uxtb r3, r3 - 800f742: 2b02 cmp r3, #2 - 800f744: d002 beq.n 800f74c - 800f746: 2b03 cmp r3, #3 - 800f748: d016 beq.n 800f778 - 800f74a: e04b b.n 800f7e4 + 8010f36: 687b ldr r3, [r7, #4] + 8010f38: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010f3c: b2db uxtb r3, r3 + 8010f3e: 2b02 cmp r3, #2 + 8010f40: d002 beq.n 8010f48 + 8010f42: 2b03 cmp r3, #3 + 8010f44: d016 beq.n 8010f74 + 8010f46: e04b b.n 8010fe0 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - 800f74c: 7bbb ldrb r3, [r7, #14] - 800f74e: 2b00 cmp r3, #0 - 800f750: d00d beq.n 800f76e - 800f752: 7bbb ldrb r3, [r7, #14] - 800f754: 2b80 cmp r3, #128 ; 0x80 - 800f756: d00a beq.n 800f76e + 8010f48: 7bbb ldrb r3, [r7, #14] + 8010f4a: 2b00 cmp r3, #0 + 8010f4c: d00d beq.n 8010f6a + 8010f4e: 7bbb ldrb r3, [r7, #14] + 8010f50: 2b80 cmp r3, #128 ; 0x80 + 8010f52: d00a beq.n 8010f6a { (void)USBD_LL_StallEP(pdev, ep_addr); - 800f758: 7bbb ldrb r3, [r7, #14] - 800f75a: 4619 mov r1, r3 - 800f75c: 6878 ldr r0, [r7, #4] - 800f75e: f001 f855 bl 801080c + 8010f54: 7bbb ldrb r3, [r7, #14] + 8010f56: 4619 mov r1, r3 + 8010f58: 6878 ldr r0, [r7, #4] + 8010f5a: f001 fe97 bl 8012c8c (void)USBD_LL_StallEP(pdev, 0x80U); - 800f762: 2180 movs r1, #128 ; 0x80 - 800f764: 6878 ldr r0, [r7, #4] - 800f766: f001 f851 bl 801080c - 800f76a: bf00 nop + 8010f5e: 2180 movs r1, #128 ; 0x80 + 8010f60: 6878 ldr r0, [r7, #4] + 8010f62: f001 fe93 bl 8012c8c + 8010f66: bf00 nop } else { USBD_CtlError(pdev, req); } break; - 800f76c: e040 b.n 800f7f0 + 8010f68: e040 b.n 8010fec USBD_CtlError(pdev, req); - 800f76e: 6839 ldr r1, [r7, #0] - 800f770: 6878 ldr r0, [r7, #4] - 800f772: f000 fc68 bl 8010046 + 8010f6a: 6839 ldr r1, [r7, #0] + 8010f6c: 6878 ldr r0, [r7, #4] + 8010f6e: f000 fc68 bl 8011842 break; - 800f776: e03b b.n 800f7f0 + 8010f72: e03b b.n 8010fec case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_EP_HALT) - 800f778: 683b ldr r3, [r7, #0] - 800f77a: 885b ldrh r3, [r3, #2] - 800f77c: 2b00 cmp r3, #0 - 800f77e: d136 bne.n 800f7ee + 8010f74: 683b ldr r3, [r7, #0] + 8010f76: 885b ldrh r3, [r3, #2] + 8010f78: 2b00 cmp r3, #0 + 8010f7a: d136 bne.n 8010fea { if ((ep_addr & 0x7FU) != 0x00U) - 800f780: 7bbb ldrb r3, [r7, #14] - 800f782: f003 037f and.w r3, r3, #127 ; 0x7f - 800f786: 2b00 cmp r3, #0 - 800f788: d004 beq.n 800f794 + 8010f7c: 7bbb ldrb r3, [r7, #14] + 8010f7e: f003 037f and.w r3, r3, #127 ; 0x7f + 8010f82: 2b00 cmp r3, #0 + 8010f84: d004 beq.n 8010f90 { (void)USBD_LL_ClearStallEP(pdev, ep_addr); - 800f78a: 7bbb ldrb r3, [r7, #14] - 800f78c: 4619 mov r1, r3 - 800f78e: 6878 ldr r0, [r7, #4] - 800f790: f001 f872 bl 8010878 + 8010f86: 7bbb ldrb r3, [r7, #14] + 8010f88: 4619 mov r1, r3 + 8010f8a: 6878 ldr r0, [r7, #4] + 8010f8c: f001 feb4 bl 8012cf8 } (void)USBD_CtlSendStatus(pdev); - 800f794: 6878 ldr r0, [r7, #4] - 800f796: f000 fd04 bl 80101a2 + 8010f90: 6878 ldr r0, [r7, #4] + 8010f92: f000 fd21 bl 80119d8 /* Get the class index relative to this interface */ idx = USBD_CoreFindEP(pdev, ep_addr); - 800f79a: 7bbb ldrb r3, [r7, #14] - 800f79c: 4619 mov r1, r3 - 800f79e: 6878 ldr r0, [r7, #4] - 800f7a0: f7ff fde2 bl 800f368 - 800f7a4: 4603 mov r3, r0 - 800f7a6: 737b strb r3, [r7, #13] + 8010f96: 7bbb ldrb r3, [r7, #14] + 8010f98: 4619 mov r1, r3 + 8010f9a: 6878 ldr r0, [r7, #4] + 8010f9c: f7ff fde2 bl 8010b64 + 8010fa0: 4603 mov r3, r0 + 8010fa2: 737b strb r3, [r7, #13] if (((uint8_t)idx != 0xFFU) && (idx < USBD_MAX_SUPPORTED_CLASS)) - 800f7a8: 7b7b ldrb r3, [r7, #13] - 800f7aa: 2bff cmp r3, #255 ; 0xff - 800f7ac: d01f beq.n 800f7ee - 800f7ae: 7b7b ldrb r3, [r7, #13] - 800f7b0: 2b00 cmp r3, #0 - 800f7b2: d11c bne.n 800f7ee + 8010fa4: 7b7b ldrb r3, [r7, #13] + 8010fa6: 2bff cmp r3, #255 ; 0xff + 8010fa8: d01f beq.n 8010fea + 8010faa: 7b7b ldrb r3, [r7, #13] + 8010fac: 2b00 cmp r3, #0 + 8010fae: d11c bne.n 8010fea { pdev->classId = idx; - 800f7b4: 7b7a ldrb r2, [r7, #13] - 800f7b6: 687b ldr r3, [r7, #4] - 800f7b8: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 + 8010fb0: 7b7a ldrb r2, [r7, #13] + 8010fb2: 687b ldr r3, [r7, #4] + 8010fb4: f8c3 22d4 str.w r2, [r3, #724] ; 0x2d4 /* Call the class data out function to manage the request */ if (pdev->pClass[idx]->Setup != NULL) - 800f7bc: 7b7a ldrb r2, [r7, #13] - 800f7be: 687b ldr r3, [r7, #4] - 800f7c0: 32ae adds r2, #174 ; 0xae - 800f7c2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f7c6: 689b ldr r3, [r3, #8] - 800f7c8: 2b00 cmp r3, #0 - 800f7ca: d010 beq.n 800f7ee + 8010fb8: 7b7a ldrb r2, [r7, #13] + 8010fba: 687b ldr r3, [r7, #4] + 8010fbc: 32ae adds r2, #174 ; 0xae + 8010fbe: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010fc2: 689b ldr r3, [r3, #8] + 8010fc4: 2b00 cmp r3, #0 + 8010fc6: d010 beq.n 8010fea { ret = (USBD_StatusTypeDef)(pdev->pClass[idx]->Setup(pdev, req)); - 800f7cc: 7b7a ldrb r2, [r7, #13] - 800f7ce: 687b ldr r3, [r7, #4] - 800f7d0: 32ae adds r2, #174 ; 0xae - 800f7d2: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 800f7d6: 689b ldr r3, [r3, #8] - 800f7d8: 6839 ldr r1, [r7, #0] - 800f7da: 6878 ldr r0, [r7, #4] - 800f7dc: 4798 blx r3 - 800f7de: 4603 mov r3, r0 - 800f7e0: 73fb strb r3, [r7, #15] + 8010fc8: 7b7a ldrb r2, [r7, #13] + 8010fca: 687b ldr r3, [r7, #4] + 8010fcc: 32ae adds r2, #174 ; 0xae + 8010fce: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8010fd2: 689b ldr r3, [r3, #8] + 8010fd4: 6839 ldr r1, [r7, #0] + 8010fd6: 6878 ldr r0, [r7, #4] + 8010fd8: 4798 blx r3 + 8010fda: 4603 mov r3, r0 + 8010fdc: 73fb strb r3, [r7, #15] } } } break; - 800f7e2: e004 b.n 800f7ee + 8010fde: e004 b.n 8010fea default: USBD_CtlError(pdev, req); - 800f7e4: 6839 ldr r1, [r7, #0] - 800f7e6: 6878 ldr r0, [r7, #4] - 800f7e8: f000 fc2d bl 8010046 + 8010fe0: 6839 ldr r1, [r7, #0] + 8010fe2: 6878 ldr r0, [r7, #4] + 8010fe4: f000 fc2d bl 8011842 break; - 800f7ec: e000 b.n 800f7f0 + 8010fe8: e000 b.n 8010fec break; - 800f7ee: bf00 nop + 8010fea: bf00 nop } break; - 800f7f0: e0ab b.n 800f94a + 8010fec: e0ab b.n 8011146 case USB_REQ_GET_STATUS: switch (pdev->dev_state) - 800f7f2: 687b ldr r3, [r7, #4] - 800f7f4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800f7f8: b2db uxtb r3, r3 - 800f7fa: 2b02 cmp r3, #2 - 800f7fc: d002 beq.n 800f804 - 800f7fe: 2b03 cmp r3, #3 - 800f800: d032 beq.n 800f868 - 800f802: e097 b.n 800f934 + 8010fee: 687b ldr r3, [r7, #4] + 8010ff0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8010ff4: b2db uxtb r3, r3 + 8010ff6: 2b02 cmp r3, #2 + 8010ff8: d002 beq.n 8011000 + 8010ffa: 2b03 cmp r3, #3 + 8010ffc: d032 beq.n 8011064 + 8010ffe: e097 b.n 8011130 { case USBD_STATE_ADDRESSED: if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - 800f804: 7bbb ldrb r3, [r7, #14] - 800f806: 2b00 cmp r3, #0 - 800f808: d007 beq.n 800f81a - 800f80a: 7bbb ldrb r3, [r7, #14] - 800f80c: 2b80 cmp r3, #128 ; 0x80 - 800f80e: d004 beq.n 800f81a + 8011000: 7bbb ldrb r3, [r7, #14] + 8011002: 2b00 cmp r3, #0 + 8011004: d007 beq.n 8011016 + 8011006: 7bbb ldrb r3, [r7, #14] + 8011008: 2b80 cmp r3, #128 ; 0x80 + 801100a: d004 beq.n 8011016 { USBD_CtlError(pdev, req); - 800f810: 6839 ldr r1, [r7, #0] - 800f812: 6878 ldr r0, [r7, #4] - 800f814: f000 fc17 bl 8010046 + 801100c: 6839 ldr r1, [r7, #0] + 801100e: 6878 ldr r0, [r7, #4] + 8011010: f000 fc17 bl 8011842 break; - 800f818: e091 b.n 800f93e + 8011014: e091 b.n 801113a } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - 800f81a: f997 300e ldrsb.w r3, [r7, #14] - 800f81e: 2b00 cmp r3, #0 - 800f820: da0b bge.n 800f83a - 800f822: 7bbb ldrb r3, [r7, #14] - 800f824: f003 027f and.w r2, r3, #127 ; 0x7f - 800f828: 4613 mov r3, r2 - 800f82a: 009b lsls r3, r3, #2 - 800f82c: 4413 add r3, r2 - 800f82e: 009b lsls r3, r3, #2 - 800f830: 3310 adds r3, #16 - 800f832: 687a ldr r2, [r7, #4] - 800f834: 4413 add r3, r2 - 800f836: 3304 adds r3, #4 - 800f838: e00b b.n 800f852 + 8011016: f997 300e ldrsb.w r3, [r7, #14] + 801101a: 2b00 cmp r3, #0 + 801101c: da0b bge.n 8011036 + 801101e: 7bbb ldrb r3, [r7, #14] + 8011020: f003 027f and.w r2, r3, #127 ; 0x7f + 8011024: 4613 mov r3, r2 + 8011026: 009b lsls r3, r3, #2 + 8011028: 4413 add r3, r2 + 801102a: 009b lsls r3, r3, #2 + 801102c: 3310 adds r3, #16 + 801102e: 687a ldr r2, [r7, #4] + 8011030: 4413 add r3, r2 + 8011032: 3304 adds r3, #4 + 8011034: e00b b.n 801104e &pdev->ep_out[ep_addr & 0x7FU]; - 800f83a: 7bbb ldrb r3, [r7, #14] - 800f83c: f003 027f and.w r2, r3, #127 ; 0x7f + 8011036: 7bbb ldrb r3, [r7, #14] + 8011038: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - 800f840: 4613 mov r3, r2 - 800f842: 009b lsls r3, r3, #2 - 800f844: 4413 add r3, r2 - 800f846: 009b lsls r3, r3, #2 - 800f848: f503 73a8 add.w r3, r3, #336 ; 0x150 - 800f84c: 687a ldr r2, [r7, #4] - 800f84e: 4413 add r3, r2 - 800f850: 3304 adds r3, #4 - 800f852: 60bb str r3, [r7, #8] + 801103c: 4613 mov r3, r2 + 801103e: 009b lsls r3, r3, #2 + 8011040: 4413 add r3, r2 + 8011042: 009b lsls r3, r3, #2 + 8011044: f503 73a8 add.w r3, r3, #336 ; 0x150 + 8011048: 687a ldr r2, [r7, #4] + 801104a: 4413 add r3, r2 + 801104c: 3304 adds r3, #4 + 801104e: 60bb str r3, [r7, #8] pep->status = 0x0000U; - 800f854: 68bb ldr r3, [r7, #8] - 800f856: 2200 movs r2, #0 - 800f858: 601a str r2, [r3, #0] + 8011050: 68bb ldr r3, [r7, #8] + 8011052: 2200 movs r2, #0 + 8011054: 601a str r2, [r3, #0] (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); - 800f85a: 68bb ldr r3, [r7, #8] - 800f85c: 2202 movs r2, #2 - 800f85e: 4619 mov r1, r3 - 800f860: 6878 ldr r0, [r7, #4] - 800f862: f000 fc61 bl 8010128 + 8011056: 68bb ldr r3, [r7, #8] + 8011058: 2202 movs r2, #2 + 801105a: 4619 mov r1, r3 + 801105c: 6878 ldr r0, [r7, #4] + 801105e: f000 fc61 bl 8011924 break; - 800f866: e06a b.n 800f93e + 8011062: e06a b.n 801113a case USBD_STATE_CONFIGURED: if ((ep_addr & 0x80U) == 0x80U) - 800f868: f997 300e ldrsb.w r3, [r7, #14] - 800f86c: 2b00 cmp r3, #0 - 800f86e: da11 bge.n 800f894 + 8011064: f997 300e ldrsb.w r3, [r7, #14] + 8011068: 2b00 cmp r3, #0 + 801106a: da11 bge.n 8011090 { if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) - 800f870: 7bbb ldrb r3, [r7, #14] - 800f872: f003 020f and.w r2, r3, #15 - 800f876: 6879 ldr r1, [r7, #4] - 800f878: 4613 mov r3, r2 - 800f87a: 009b lsls r3, r3, #2 - 800f87c: 4413 add r3, r2 - 800f87e: 009b lsls r3, r3, #2 - 800f880: 440b add r3, r1 - 800f882: 3324 adds r3, #36 ; 0x24 - 800f884: 881b ldrh r3, [r3, #0] - 800f886: 2b00 cmp r3, #0 - 800f888: d117 bne.n 800f8ba + 801106c: 7bbb ldrb r3, [r7, #14] + 801106e: f003 020f and.w r2, r3, #15 + 8011072: 6879 ldr r1, [r7, #4] + 8011074: 4613 mov r3, r2 + 8011076: 009b lsls r3, r3, #2 + 8011078: 4413 add r3, r2 + 801107a: 009b lsls r3, r3, #2 + 801107c: 440b add r3, r1 + 801107e: 3324 adds r3, #36 ; 0x24 + 8011080: 881b ldrh r3, [r3, #0] + 8011082: 2b00 cmp r3, #0 + 8011084: d117 bne.n 80110b6 { USBD_CtlError(pdev, req); - 800f88a: 6839 ldr r1, [r7, #0] - 800f88c: 6878 ldr r0, [r7, #4] - 800f88e: f000 fbda bl 8010046 + 8011086: 6839 ldr r1, [r7, #0] + 8011088: 6878 ldr r0, [r7, #4] + 801108a: f000 fbda bl 8011842 break; - 800f892: e054 b.n 800f93e + 801108e: e054 b.n 801113a } } else { if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) - 800f894: 7bbb ldrb r3, [r7, #14] - 800f896: f003 020f and.w r2, r3, #15 - 800f89a: 6879 ldr r1, [r7, #4] - 800f89c: 4613 mov r3, r2 - 800f89e: 009b lsls r3, r3, #2 - 800f8a0: 4413 add r3, r2 - 800f8a2: 009b lsls r3, r3, #2 - 800f8a4: 440b add r3, r1 - 800f8a6: f503 73b2 add.w r3, r3, #356 ; 0x164 - 800f8aa: 881b ldrh r3, [r3, #0] - 800f8ac: 2b00 cmp r3, #0 - 800f8ae: d104 bne.n 800f8ba + 8011090: 7bbb ldrb r3, [r7, #14] + 8011092: f003 020f and.w r2, r3, #15 + 8011096: 6879 ldr r1, [r7, #4] + 8011098: 4613 mov r3, r2 + 801109a: 009b lsls r3, r3, #2 + 801109c: 4413 add r3, r2 + 801109e: 009b lsls r3, r3, #2 + 80110a0: 440b add r3, r1 + 80110a2: f503 73b2 add.w r3, r3, #356 ; 0x164 + 80110a6: 881b ldrh r3, [r3, #0] + 80110a8: 2b00 cmp r3, #0 + 80110aa: d104 bne.n 80110b6 { USBD_CtlError(pdev, req); - 800f8b0: 6839 ldr r1, [r7, #0] - 800f8b2: 6878 ldr r0, [r7, #4] - 800f8b4: f000 fbc7 bl 8010046 + 80110ac: 6839 ldr r1, [r7, #0] + 80110ae: 6878 ldr r0, [r7, #4] + 80110b0: f000 fbc7 bl 8011842 break; - 800f8b8: e041 b.n 800f93e + 80110b4: e041 b.n 801113a } } pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - 800f8ba: f997 300e ldrsb.w r3, [r7, #14] - 800f8be: 2b00 cmp r3, #0 - 800f8c0: da0b bge.n 800f8da - 800f8c2: 7bbb ldrb r3, [r7, #14] - 800f8c4: f003 027f and.w r2, r3, #127 ; 0x7f - 800f8c8: 4613 mov r3, r2 - 800f8ca: 009b lsls r3, r3, #2 - 800f8cc: 4413 add r3, r2 - 800f8ce: 009b lsls r3, r3, #2 - 800f8d0: 3310 adds r3, #16 - 800f8d2: 687a ldr r2, [r7, #4] - 800f8d4: 4413 add r3, r2 - 800f8d6: 3304 adds r3, #4 - 800f8d8: e00b b.n 800f8f2 + 80110b6: f997 300e ldrsb.w r3, [r7, #14] + 80110ba: 2b00 cmp r3, #0 + 80110bc: da0b bge.n 80110d6 + 80110be: 7bbb ldrb r3, [r7, #14] + 80110c0: f003 027f and.w r2, r3, #127 ; 0x7f + 80110c4: 4613 mov r3, r2 + 80110c6: 009b lsls r3, r3, #2 + 80110c8: 4413 add r3, r2 + 80110ca: 009b lsls r3, r3, #2 + 80110cc: 3310 adds r3, #16 + 80110ce: 687a ldr r2, [r7, #4] + 80110d0: 4413 add r3, r2 + 80110d2: 3304 adds r3, #4 + 80110d4: e00b b.n 80110ee &pdev->ep_out[ep_addr & 0x7FU]; - 800f8da: 7bbb ldrb r3, [r7, #14] - 800f8dc: f003 027f and.w r2, r3, #127 ; 0x7f + 80110d6: 7bbb ldrb r3, [r7, #14] + 80110d8: f003 027f and.w r2, r3, #127 ; 0x7f pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - 800f8e0: 4613 mov r3, r2 - 800f8e2: 009b lsls r3, r3, #2 - 800f8e4: 4413 add r3, r2 - 800f8e6: 009b lsls r3, r3, #2 - 800f8e8: f503 73a8 add.w r3, r3, #336 ; 0x150 - 800f8ec: 687a ldr r2, [r7, #4] - 800f8ee: 4413 add r3, r2 - 800f8f0: 3304 adds r3, #4 - 800f8f2: 60bb str r3, [r7, #8] + 80110dc: 4613 mov r3, r2 + 80110de: 009b lsls r3, r3, #2 + 80110e0: 4413 add r3, r2 + 80110e2: 009b lsls r3, r3, #2 + 80110e4: f503 73a8 add.w r3, r3, #336 ; 0x150 + 80110e8: 687a ldr r2, [r7, #4] + 80110ea: 4413 add r3, r2 + 80110ec: 3304 adds r3, #4 + 80110ee: 60bb str r3, [r7, #8] if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) - 800f8f4: 7bbb ldrb r3, [r7, #14] - 800f8f6: 2b00 cmp r3, #0 - 800f8f8: d002 beq.n 800f900 - 800f8fa: 7bbb ldrb r3, [r7, #14] - 800f8fc: 2b80 cmp r3, #128 ; 0x80 - 800f8fe: d103 bne.n 800f908 + 80110f0: 7bbb ldrb r3, [r7, #14] + 80110f2: 2b00 cmp r3, #0 + 80110f4: d002 beq.n 80110fc + 80110f6: 7bbb ldrb r3, [r7, #14] + 80110f8: 2b80 cmp r3, #128 ; 0x80 + 80110fa: d103 bne.n 8011104 { pep->status = 0x0000U; - 800f900: 68bb ldr r3, [r7, #8] - 800f902: 2200 movs r2, #0 - 800f904: 601a str r2, [r3, #0] - 800f906: e00e b.n 800f926 + 80110fc: 68bb ldr r3, [r7, #8] + 80110fe: 2200 movs r2, #0 + 8011100: 601a str r2, [r3, #0] + 8011102: e00e b.n 8011122 } else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) - 800f908: 7bbb ldrb r3, [r7, #14] - 800f90a: 4619 mov r1, r3 - 800f90c: 6878 ldr r0, [r7, #4] - 800f90e: f000 ffe9 bl 80108e4 - 800f912: 4603 mov r3, r0 - 800f914: 2b00 cmp r3, #0 - 800f916: d003 beq.n 800f920 + 8011104: 7bbb ldrb r3, [r7, #14] + 8011106: 4619 mov r1, r3 + 8011108: 6878 ldr r0, [r7, #4] + 801110a: f001 fe2b bl 8012d64 + 801110e: 4603 mov r3, r0 + 8011110: 2b00 cmp r3, #0 + 8011112: d003 beq.n 801111c { pep->status = 0x0001U; - 800f918: 68bb ldr r3, [r7, #8] - 800f91a: 2201 movs r2, #1 - 800f91c: 601a str r2, [r3, #0] - 800f91e: e002 b.n 800f926 + 8011114: 68bb ldr r3, [r7, #8] + 8011116: 2201 movs r2, #1 + 8011118: 601a str r2, [r3, #0] + 801111a: e002 b.n 8011122 } else { pep->status = 0x0000U; - 800f920: 68bb ldr r3, [r7, #8] - 800f922: 2200 movs r2, #0 - 800f924: 601a str r2, [r3, #0] + 801111c: 68bb ldr r3, [r7, #8] + 801111e: 2200 movs r2, #0 + 8011120: 601a str r2, [r3, #0] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); - 800f926: 68bb ldr r3, [r7, #8] - 800f928: 2202 movs r2, #2 - 800f92a: 4619 mov r1, r3 - 800f92c: 6878 ldr r0, [r7, #4] - 800f92e: f000 fbfb bl 8010128 + 8011122: 68bb ldr r3, [r7, #8] + 8011124: 2202 movs r2, #2 + 8011126: 4619 mov r1, r3 + 8011128: 6878 ldr r0, [r7, #4] + 801112a: f000 fbfb bl 8011924 break; - 800f932: e004 b.n 800f93e + 801112e: e004 b.n 801113a default: USBD_CtlError(pdev, req); - 800f934: 6839 ldr r1, [r7, #0] - 800f936: 6878 ldr r0, [r7, #4] - 800f938: f000 fb85 bl 8010046 + 8011130: 6839 ldr r1, [r7, #0] + 8011132: 6878 ldr r0, [r7, #4] + 8011134: f000 fb85 bl 8011842 break; - 800f93c: bf00 nop + 8011138: bf00 nop } break; - 800f93e: e004 b.n 800f94a + 801113a: e004 b.n 8011146 default: USBD_CtlError(pdev, req); - 800f940: 6839 ldr r1, [r7, #0] - 800f942: 6878 ldr r0, [r7, #4] - 800f944: f000 fb7f bl 8010046 + 801113c: 6839 ldr r1, [r7, #0] + 801113e: 6878 ldr r0, [r7, #4] + 8011140: f000 fb7f bl 8011842 break; - 800f948: bf00 nop + 8011144: bf00 nop } break; - 800f94a: e005 b.n 800f958 + 8011146: e005 b.n 8011154 default: USBD_CtlError(pdev, req); - 800f94c: 6839 ldr r1, [r7, #0] - 800f94e: 6878 ldr r0, [r7, #4] - 800f950: f000 fb79 bl 8010046 + 8011148: 6839 ldr r1, [r7, #0] + 801114a: 6878 ldr r0, [r7, #4] + 801114c: f000 fb79 bl 8011842 break; - 800f954: e000 b.n 800f958 + 8011150: e000 b.n 8011154 break; - 800f956: bf00 nop + 8011152: bf00 nop } return ret; - 800f958: 7bfb ldrb r3, [r7, #15] + 8011154: 7bfb ldrb r3, [r7, #15] } - 800f95a: 4618 mov r0, r3 - 800f95c: 3710 adds r7, #16 - 800f95e: 46bd mov sp, r7 - 800f960: bd80 pop {r7, pc} + 8011156: 4618 mov r0, r3 + 8011158: 3710 adds r7, #16 + 801115a: 46bd mov sp, r7 + 801115c: bd80 pop {r7, pc} ... -0800f964 : +08011160 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800f964: b580 push {r7, lr} - 800f966: b084 sub sp, #16 - 800f968: af00 add r7, sp, #0 - 800f96a: 6078 str r0, [r7, #4] - 800f96c: 6039 str r1, [r7, #0] + 8011160: b580 push {r7, lr} + 8011162: b084 sub sp, #16 + 8011164: af00 add r7, sp, #0 + 8011166: 6078 str r0, [r7, #4] + 8011168: 6039 str r1, [r7, #0] uint16_t len = 0U; - 800f96e: 2300 movs r3, #0 - 800f970: 813b strh r3, [r7, #8] + 801116a: 2300 movs r3, #0 + 801116c: 813b strh r3, [r7, #8] uint8_t *pbuf = NULL; - 800f972: 2300 movs r3, #0 - 800f974: 60fb str r3, [r7, #12] + 801116e: 2300 movs r3, #0 + 8011170: 60fb str r3, [r7, #12] uint8_t err = 0U; - 800f976: 2300 movs r3, #0 - 800f978: 72fb strb r3, [r7, #11] + 8011172: 2300 movs r3, #0 + 8011174: 72fb strb r3, [r7, #11] switch (req->wValue >> 8) - 800f97a: 683b ldr r3, [r7, #0] - 800f97c: 885b ldrh r3, [r3, #2] - 800f97e: 0a1b lsrs r3, r3, #8 - 800f980: b29b uxth r3, r3 - 800f982: 3b01 subs r3, #1 - 800f984: 2b0e cmp r3, #14 - 800f986: f200 8152 bhi.w 800fc2e - 800f98a: a201 add r2, pc, #4 ; (adr r2, 800f990 ) - 800f98c: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800f990: 0800fa01 .word 0x0800fa01 - 800f994: 0800fa19 .word 0x0800fa19 - 800f998: 0800fa59 .word 0x0800fa59 - 800f99c: 0800fc2f .word 0x0800fc2f - 800f9a0: 0800fc2f .word 0x0800fc2f - 800f9a4: 0800fbcf .word 0x0800fbcf - 800f9a8: 0800fbfb .word 0x0800fbfb - 800f9ac: 0800fc2f .word 0x0800fc2f - 800f9b0: 0800fc2f .word 0x0800fc2f - 800f9b4: 0800fc2f .word 0x0800fc2f - 800f9b8: 0800fc2f .word 0x0800fc2f - 800f9bc: 0800fc2f .word 0x0800fc2f - 800f9c0: 0800fc2f .word 0x0800fc2f - 800f9c4: 0800fc2f .word 0x0800fc2f - 800f9c8: 0800f9cd .word 0x0800f9cd + 8011176: 683b ldr r3, [r7, #0] + 8011178: 885b ldrh r3, [r3, #2] + 801117a: 0a1b lsrs r3, r3, #8 + 801117c: b29b uxth r3, r3 + 801117e: 3b01 subs r3, #1 + 8011180: 2b0e cmp r3, #14 + 8011182: f200 8152 bhi.w 801142a + 8011186: a201 add r2, pc, #4 ; (adr r2, 801118c ) + 8011188: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 801118c: 080111fd .word 0x080111fd + 8011190: 08011215 .word 0x08011215 + 8011194: 08011255 .word 0x08011255 + 8011198: 0801142b .word 0x0801142b + 801119c: 0801142b .word 0x0801142b + 80111a0: 080113cb .word 0x080113cb + 80111a4: 080113f7 .word 0x080113f7 + 80111a8: 0801142b .word 0x0801142b + 80111ac: 0801142b .word 0x0801142b + 80111b0: 0801142b .word 0x0801142b + 80111b4: 0801142b .word 0x0801142b + 80111b8: 0801142b .word 0x0801142b + 80111bc: 0801142b .word 0x0801142b + 80111c0: 0801142b .word 0x0801142b + 80111c4: 080111c9 .word 0x080111c9 { #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) case USB_DESC_TYPE_BOS: if (pdev->pDesc->GetBOSDescriptor != NULL) - 800f9cc: 687b ldr r3, [r7, #4] - 800f9ce: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800f9d2: 69db ldr r3, [r3, #28] - 800f9d4: 2b00 cmp r3, #0 - 800f9d6: d00b beq.n 800f9f0 + 80111c8: 687b ldr r3, [r7, #4] + 80111ca: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80111ce: 69db ldr r3, [r3, #28] + 80111d0: 2b00 cmp r3, #0 + 80111d2: d00b beq.n 80111ec { pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - 800f9d8: 687b ldr r3, [r7, #4] - 800f9da: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800f9de: 69db ldr r3, [r3, #28] - 800f9e0: 687a ldr r2, [r7, #4] - 800f9e2: 7c12 ldrb r2, [r2, #16] - 800f9e4: f107 0108 add.w r1, r7, #8 - 800f9e8: 4610 mov r0, r2 - 800f9ea: 4798 blx r3 - 800f9ec: 60f8 str r0, [r7, #12] + 80111d4: 687b ldr r3, [r7, #4] + 80111d6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80111da: 69db ldr r3, [r3, #28] + 80111dc: 687a ldr r2, [r7, #4] + 80111de: 7c12 ldrb r2, [r2, #16] + 80111e0: f107 0108 add.w r1, r7, #8 + 80111e4: 4610 mov r0, r2 + 80111e6: 4798 blx r3 + 80111e8: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800f9ee: e126 b.n 800fc3e + 80111ea: e126 b.n 801143a USBD_CtlError(pdev, req); - 800f9f0: 6839 ldr r1, [r7, #0] - 800f9f2: 6878 ldr r0, [r7, #4] - 800f9f4: f000 fb27 bl 8010046 + 80111ec: 6839 ldr r1, [r7, #0] + 80111ee: 6878 ldr r0, [r7, #4] + 80111f0: f000 fb27 bl 8011842 err++; - 800f9f8: 7afb ldrb r3, [r7, #11] - 800f9fa: 3301 adds r3, #1 - 800f9fc: 72fb strb r3, [r7, #11] + 80111f4: 7afb ldrb r3, [r7, #11] + 80111f6: 3301 adds r3, #1 + 80111f8: 72fb strb r3, [r7, #11] break; - 800f9fe: e11e b.n 800fc3e + 80111fa: e11e b.n 801143a #endif /* (USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U) */ case USB_DESC_TYPE_DEVICE: pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - 800fa00: 687b ldr r3, [r7, #4] - 800fa02: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fa06: 681b ldr r3, [r3, #0] - 800fa08: 687a ldr r2, [r7, #4] - 800fa0a: 7c12 ldrb r2, [r2, #16] - 800fa0c: f107 0108 add.w r1, r7, #8 - 800fa10: 4610 mov r0, r2 - 800fa12: 4798 blx r3 - 800fa14: 60f8 str r0, [r7, #12] + 80111fc: 687b ldr r3, [r7, #4] + 80111fe: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011202: 681b ldr r3, [r3, #0] + 8011204: 687a ldr r2, [r7, #4] + 8011206: 7c12 ldrb r2, [r2, #16] + 8011208: f107 0108 add.w r1, r7, #8 + 801120c: 4610 mov r0, r2 + 801120e: 4798 blx r3 + 8011210: 60f8 str r0, [r7, #12] break; - 800fa16: e112 b.n 800fc3e + 8011212: e112 b.n 801143a case USB_DESC_TYPE_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) - 800fa18: 687b ldr r3, [r7, #4] - 800fa1a: 7c1b ldrb r3, [r3, #16] - 800fa1c: 2b00 cmp r3, #0 - 800fa1e: d10d bne.n 800fa3c + 8011214: 687b ldr r3, [r7, #4] + 8011216: 7c1b ldrb r3, [r3, #16] + 8011218: 2b00 cmp r3, #0 + 801121a: d10d bne.n 8011238 pbuf = (uint8_t *)USBD_CMPSIT.GetHSConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetHSConfigDescriptor(&len); - 800fa20: 687b ldr r3, [r7, #4] - 800fa22: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800fa26: 6a9b ldr r3, [r3, #40] ; 0x28 - 800fa28: f107 0208 add.w r2, r7, #8 - 800fa2c: 4610 mov r0, r2 - 800fa2e: 4798 blx r3 - 800fa30: 60f8 str r0, [r7, #12] + 801121c: 687b ldr r3, [r7, #4] + 801121e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8011222: 6a9b ldr r3, [r3, #40] ; 0x28 + 8011224: f107 0208 add.w r2, r7, #8 + 8011228: 4610 mov r0, r2 + 801122a: 4798 blx r3 + 801122c: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - 800fa32: 68fb ldr r3, [r7, #12] - 800fa34: 3301 adds r3, #1 - 800fa36: 2202 movs r2, #2 - 800fa38: 701a strb r2, [r3, #0] + 801122e: 68fb ldr r3, [r7, #12] + 8011230: 3301 adds r3, #1 + 8011232: 2202 movs r2, #2 + 8011234: 701a strb r2, [r3, #0] { pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); } pbuf[1] = USB_DESC_TYPE_CONFIGURATION; } break; - 800fa3a: e100 b.n 800fc3e + 8011236: e100 b.n 801143a pbuf = (uint8_t *)pdev->pClass[0]->GetFSConfigDescriptor(&len); - 800fa3c: 687b ldr r3, [r7, #4] - 800fa3e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800fa42: 6adb ldr r3, [r3, #44] ; 0x2c - 800fa44: f107 0208 add.w r2, r7, #8 - 800fa48: 4610 mov r0, r2 - 800fa4a: 4798 blx r3 - 800fa4c: 60f8 str r0, [r7, #12] + 8011238: 687b ldr r3, [r7, #4] + 801123a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 801123e: 6adb ldr r3, [r3, #44] ; 0x2c + 8011240: f107 0208 add.w r2, r7, #8 + 8011244: 4610 mov r0, r2 + 8011246: 4798 blx r3 + 8011248: 60f8 str r0, [r7, #12] pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - 800fa4e: 68fb ldr r3, [r7, #12] - 800fa50: 3301 adds r3, #1 - 800fa52: 2202 movs r2, #2 - 800fa54: 701a strb r2, [r3, #0] + 801124a: 68fb ldr r3, [r7, #12] + 801124c: 3301 adds r3, #1 + 801124e: 2202 movs r2, #2 + 8011250: 701a strb r2, [r3, #0] break; - 800fa56: e0f2 b.n 800fc3e + 8011252: e0f2 b.n 801143a case USB_DESC_TYPE_STRING: switch ((uint8_t)(req->wValue)) - 800fa58: 683b ldr r3, [r7, #0] - 800fa5a: 885b ldrh r3, [r3, #2] - 800fa5c: b2db uxtb r3, r3 - 800fa5e: 2b05 cmp r3, #5 - 800fa60: f200 80ac bhi.w 800fbbc - 800fa64: a201 add r2, pc, #4 ; (adr r2, 800fa6c ) - 800fa66: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800fa6a: bf00 nop - 800fa6c: 0800fa85 .word 0x0800fa85 - 800fa70: 0800fab9 .word 0x0800fab9 - 800fa74: 0800faed .word 0x0800faed - 800fa78: 0800fb21 .word 0x0800fb21 - 800fa7c: 0800fb55 .word 0x0800fb55 - 800fa80: 0800fb89 .word 0x0800fb89 + 8011254: 683b ldr r3, [r7, #0] + 8011256: 885b ldrh r3, [r3, #2] + 8011258: b2db uxtb r3, r3 + 801125a: 2b05 cmp r3, #5 + 801125c: f200 80ac bhi.w 80113b8 + 8011260: a201 add r2, pc, #4 ; (adr r2, 8011268 ) + 8011262: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8011266: bf00 nop + 8011268: 08011281 .word 0x08011281 + 801126c: 080112b5 .word 0x080112b5 + 8011270: 080112e9 .word 0x080112e9 + 8011274: 0801131d .word 0x0801131d + 8011278: 08011351 .word 0x08011351 + 801127c: 08011385 .word 0x08011385 { case USBD_IDX_LANGID_STR: if (pdev->pDesc->GetLangIDStrDescriptor != NULL) - 800fa84: 687b ldr r3, [r7, #4] - 800fa86: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fa8a: 685b ldr r3, [r3, #4] - 800fa8c: 2b00 cmp r3, #0 - 800fa8e: d00b beq.n 800faa8 + 8011280: 687b ldr r3, [r7, #4] + 8011282: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011286: 685b ldr r3, [r3, #4] + 8011288: 2b00 cmp r3, #0 + 801128a: d00b beq.n 80112a4 { pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - 800fa90: 687b ldr r3, [r7, #4] - 800fa92: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fa96: 685b ldr r3, [r3, #4] - 800fa98: 687a ldr r2, [r7, #4] - 800fa9a: 7c12 ldrb r2, [r2, #16] - 800fa9c: f107 0108 add.w r1, r7, #8 - 800faa0: 4610 mov r0, r2 - 800faa2: 4798 blx r3 - 800faa4: 60f8 str r0, [r7, #12] + 801128c: 687b ldr r3, [r7, #4] + 801128e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011292: 685b ldr r3, [r3, #4] + 8011294: 687a ldr r2, [r7, #4] + 8011296: 7c12 ldrb r2, [r2, #16] + 8011298: f107 0108 add.w r1, r7, #8 + 801129c: 4610 mov r0, r2 + 801129e: 4798 blx r3 + 80112a0: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800faa6: e091 b.n 800fbcc + 80112a2: e091 b.n 80113c8 USBD_CtlError(pdev, req); - 800faa8: 6839 ldr r1, [r7, #0] - 800faaa: 6878 ldr r0, [r7, #4] - 800faac: f000 facb bl 8010046 + 80112a4: 6839 ldr r1, [r7, #0] + 80112a6: 6878 ldr r0, [r7, #4] + 80112a8: f000 facb bl 8011842 err++; - 800fab0: 7afb ldrb r3, [r7, #11] - 800fab2: 3301 adds r3, #1 - 800fab4: 72fb strb r3, [r7, #11] + 80112ac: 7afb ldrb r3, [r7, #11] + 80112ae: 3301 adds r3, #1 + 80112b0: 72fb strb r3, [r7, #11] break; - 800fab6: e089 b.n 800fbcc + 80112b2: e089 b.n 80113c8 case USBD_IDX_MFC_STR: if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) - 800fab8: 687b ldr r3, [r7, #4] - 800faba: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fabe: 689b ldr r3, [r3, #8] - 800fac0: 2b00 cmp r3, #0 - 800fac2: d00b beq.n 800fadc + 80112b4: 687b ldr r3, [r7, #4] + 80112b6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80112ba: 689b ldr r3, [r3, #8] + 80112bc: 2b00 cmp r3, #0 + 80112be: d00b beq.n 80112d8 { pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - 800fac4: 687b ldr r3, [r7, #4] - 800fac6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800faca: 689b ldr r3, [r3, #8] - 800facc: 687a ldr r2, [r7, #4] - 800face: 7c12 ldrb r2, [r2, #16] - 800fad0: f107 0108 add.w r1, r7, #8 - 800fad4: 4610 mov r0, r2 - 800fad6: 4798 blx r3 - 800fad8: 60f8 str r0, [r7, #12] + 80112c0: 687b ldr r3, [r7, #4] + 80112c2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80112c6: 689b ldr r3, [r3, #8] + 80112c8: 687a ldr r2, [r7, #4] + 80112ca: 7c12 ldrb r2, [r2, #16] + 80112cc: f107 0108 add.w r1, r7, #8 + 80112d0: 4610 mov r0, r2 + 80112d2: 4798 blx r3 + 80112d4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fada: e077 b.n 800fbcc + 80112d6: e077 b.n 80113c8 USBD_CtlError(pdev, req); - 800fadc: 6839 ldr r1, [r7, #0] - 800fade: 6878 ldr r0, [r7, #4] - 800fae0: f000 fab1 bl 8010046 + 80112d8: 6839 ldr r1, [r7, #0] + 80112da: 6878 ldr r0, [r7, #4] + 80112dc: f000 fab1 bl 8011842 err++; - 800fae4: 7afb ldrb r3, [r7, #11] - 800fae6: 3301 adds r3, #1 - 800fae8: 72fb strb r3, [r7, #11] + 80112e0: 7afb ldrb r3, [r7, #11] + 80112e2: 3301 adds r3, #1 + 80112e4: 72fb strb r3, [r7, #11] break; - 800faea: e06f b.n 800fbcc + 80112e6: e06f b.n 80113c8 case USBD_IDX_PRODUCT_STR: if (pdev->pDesc->GetProductStrDescriptor != NULL) - 800faec: 687b ldr r3, [r7, #4] - 800faee: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800faf2: 68db ldr r3, [r3, #12] - 800faf4: 2b00 cmp r3, #0 - 800faf6: d00b beq.n 800fb10 + 80112e8: 687b ldr r3, [r7, #4] + 80112ea: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80112ee: 68db ldr r3, [r3, #12] + 80112f0: 2b00 cmp r3, #0 + 80112f2: d00b beq.n 801130c { pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - 800faf8: 687b ldr r3, [r7, #4] - 800fafa: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fafe: 68db ldr r3, [r3, #12] - 800fb00: 687a ldr r2, [r7, #4] - 800fb02: 7c12 ldrb r2, [r2, #16] - 800fb04: f107 0108 add.w r1, r7, #8 - 800fb08: 4610 mov r0, r2 - 800fb0a: 4798 blx r3 - 800fb0c: 60f8 str r0, [r7, #12] + 80112f4: 687b ldr r3, [r7, #4] + 80112f6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 80112fa: 68db ldr r3, [r3, #12] + 80112fc: 687a ldr r2, [r7, #4] + 80112fe: 7c12 ldrb r2, [r2, #16] + 8011300: f107 0108 add.w r1, r7, #8 + 8011304: 4610 mov r0, r2 + 8011306: 4798 blx r3 + 8011308: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fb0e: e05d b.n 800fbcc + 801130a: e05d b.n 80113c8 USBD_CtlError(pdev, req); - 800fb10: 6839 ldr r1, [r7, #0] - 800fb12: 6878 ldr r0, [r7, #4] - 800fb14: f000 fa97 bl 8010046 + 801130c: 6839 ldr r1, [r7, #0] + 801130e: 6878 ldr r0, [r7, #4] + 8011310: f000 fa97 bl 8011842 err++; - 800fb18: 7afb ldrb r3, [r7, #11] - 800fb1a: 3301 adds r3, #1 - 800fb1c: 72fb strb r3, [r7, #11] + 8011314: 7afb ldrb r3, [r7, #11] + 8011316: 3301 adds r3, #1 + 8011318: 72fb strb r3, [r7, #11] break; - 800fb1e: e055 b.n 800fbcc + 801131a: e055 b.n 80113c8 case USBD_IDX_SERIAL_STR: if (pdev->pDesc->GetSerialStrDescriptor != NULL) - 800fb20: 687b ldr r3, [r7, #4] - 800fb22: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb26: 691b ldr r3, [r3, #16] - 800fb28: 2b00 cmp r3, #0 - 800fb2a: d00b beq.n 800fb44 + 801131c: 687b ldr r3, [r7, #4] + 801131e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011322: 691b ldr r3, [r3, #16] + 8011324: 2b00 cmp r3, #0 + 8011326: d00b beq.n 8011340 { pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - 800fb2c: 687b ldr r3, [r7, #4] - 800fb2e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb32: 691b ldr r3, [r3, #16] - 800fb34: 687a ldr r2, [r7, #4] - 800fb36: 7c12 ldrb r2, [r2, #16] - 800fb38: f107 0108 add.w r1, r7, #8 - 800fb3c: 4610 mov r0, r2 - 800fb3e: 4798 blx r3 - 800fb40: 60f8 str r0, [r7, #12] + 8011328: 687b ldr r3, [r7, #4] + 801132a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 801132e: 691b ldr r3, [r3, #16] + 8011330: 687a ldr r2, [r7, #4] + 8011332: 7c12 ldrb r2, [r2, #16] + 8011334: f107 0108 add.w r1, r7, #8 + 8011338: 4610 mov r0, r2 + 801133a: 4798 blx r3 + 801133c: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fb42: e043 b.n 800fbcc + 801133e: e043 b.n 80113c8 USBD_CtlError(pdev, req); - 800fb44: 6839 ldr r1, [r7, #0] - 800fb46: 6878 ldr r0, [r7, #4] - 800fb48: f000 fa7d bl 8010046 + 8011340: 6839 ldr r1, [r7, #0] + 8011342: 6878 ldr r0, [r7, #4] + 8011344: f000 fa7d bl 8011842 err++; - 800fb4c: 7afb ldrb r3, [r7, #11] - 800fb4e: 3301 adds r3, #1 - 800fb50: 72fb strb r3, [r7, #11] + 8011348: 7afb ldrb r3, [r7, #11] + 801134a: 3301 adds r3, #1 + 801134c: 72fb strb r3, [r7, #11] break; - 800fb52: e03b b.n 800fbcc + 801134e: e03b b.n 80113c8 case USBD_IDX_CONFIG_STR: if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) - 800fb54: 687b ldr r3, [r7, #4] - 800fb56: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb5a: 695b ldr r3, [r3, #20] - 800fb5c: 2b00 cmp r3, #0 - 800fb5e: d00b beq.n 800fb78 + 8011350: 687b ldr r3, [r7, #4] + 8011352: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011356: 695b ldr r3, [r3, #20] + 8011358: 2b00 cmp r3, #0 + 801135a: d00b beq.n 8011374 { pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - 800fb60: 687b ldr r3, [r7, #4] - 800fb62: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb66: 695b ldr r3, [r3, #20] - 800fb68: 687a ldr r2, [r7, #4] - 800fb6a: 7c12 ldrb r2, [r2, #16] - 800fb6c: f107 0108 add.w r1, r7, #8 - 800fb70: 4610 mov r0, r2 - 800fb72: 4798 blx r3 - 800fb74: 60f8 str r0, [r7, #12] + 801135c: 687b ldr r3, [r7, #4] + 801135e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011362: 695b ldr r3, [r3, #20] + 8011364: 687a ldr r2, [r7, #4] + 8011366: 7c12 ldrb r2, [r2, #16] + 8011368: f107 0108 add.w r1, r7, #8 + 801136c: 4610 mov r0, r2 + 801136e: 4798 blx r3 + 8011370: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fb76: e029 b.n 800fbcc + 8011372: e029 b.n 80113c8 USBD_CtlError(pdev, req); - 800fb78: 6839 ldr r1, [r7, #0] - 800fb7a: 6878 ldr r0, [r7, #4] - 800fb7c: f000 fa63 bl 8010046 + 8011374: 6839 ldr r1, [r7, #0] + 8011376: 6878 ldr r0, [r7, #4] + 8011378: f000 fa63 bl 8011842 err++; - 800fb80: 7afb ldrb r3, [r7, #11] - 800fb82: 3301 adds r3, #1 - 800fb84: 72fb strb r3, [r7, #11] + 801137c: 7afb ldrb r3, [r7, #11] + 801137e: 3301 adds r3, #1 + 8011380: 72fb strb r3, [r7, #11] break; - 800fb86: e021 b.n 800fbcc + 8011382: e021 b.n 80113c8 case USBD_IDX_INTERFACE_STR: if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) - 800fb88: 687b ldr r3, [r7, #4] - 800fb8a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb8e: 699b ldr r3, [r3, #24] - 800fb90: 2b00 cmp r3, #0 - 800fb92: d00b beq.n 800fbac + 8011384: 687b ldr r3, [r7, #4] + 8011386: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 801138a: 699b ldr r3, [r3, #24] + 801138c: 2b00 cmp r3, #0 + 801138e: d00b beq.n 80113a8 { pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - 800fb94: 687b ldr r3, [r7, #4] - 800fb96: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 - 800fb9a: 699b ldr r3, [r3, #24] - 800fb9c: 687a ldr r2, [r7, #4] - 800fb9e: 7c12 ldrb r2, [r2, #16] - 800fba0: f107 0108 add.w r1, r7, #8 - 800fba4: 4610 mov r0, r2 - 800fba6: 4798 blx r3 - 800fba8: 60f8 str r0, [r7, #12] + 8011390: 687b ldr r3, [r7, #4] + 8011392: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4 + 8011396: 699b ldr r3, [r3, #24] + 8011398: 687a ldr r2, [r7, #4] + 801139a: 7c12 ldrb r2, [r2, #16] + 801139c: f107 0108 add.w r1, r7, #8 + 80113a0: 4610 mov r0, r2 + 80113a2: 4798 blx r3 + 80113a4: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fbaa: e00f b.n 800fbcc + 80113a6: e00f b.n 80113c8 USBD_CtlError(pdev, req); - 800fbac: 6839 ldr r1, [r7, #0] - 800fbae: 6878 ldr r0, [r7, #4] - 800fbb0: f000 fa49 bl 8010046 + 80113a8: 6839 ldr r1, [r7, #0] + 80113aa: 6878 ldr r0, [r7, #4] + 80113ac: f000 fa49 bl 8011842 err++; - 800fbb4: 7afb ldrb r3, [r7, #11] - 800fbb6: 3301 adds r3, #1 - 800fbb8: 72fb strb r3, [r7, #11] + 80113b0: 7afb ldrb r3, [r7, #11] + 80113b2: 3301 adds r3, #1 + 80113b4: 72fb strb r3, [r7, #11] break; - 800fbba: e007 b.n 800fbcc + 80113b6: e007 b.n 80113c8 err++; } #endif /* USBD_SUPPORT_USER_STRING_DESC */ #if ((USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U)) USBD_CtlError(pdev, req); - 800fbbc: 6839 ldr r1, [r7, #0] - 800fbbe: 6878 ldr r0, [r7, #4] - 800fbc0: f000 fa41 bl 8010046 + 80113b8: 6839 ldr r1, [r7, #0] + 80113ba: 6878 ldr r0, [r7, #4] + 80113bc: f000 fa41 bl 8011842 err++; - 800fbc4: 7afb ldrb r3, [r7, #11] - 800fbc6: 3301 adds r3, #1 - 800fbc8: 72fb strb r3, [r7, #11] + 80113c0: 7afb ldrb r3, [r7, #11] + 80113c2: 3301 adds r3, #1 + 80113c4: 72fb strb r3, [r7, #11] #endif /* (USBD_CLASS_USER_STRING_DESC == 0U) && (USBD_SUPPORT_USER_STRING_DESC == 0U) */ break; - 800fbca: bf00 nop + 80113c6: bf00 nop } break; - 800fbcc: e037 b.n 800fc3e + 80113c8: e037 b.n 801143a case USB_DESC_TYPE_DEVICE_QUALIFIER: if (pdev->dev_speed == USBD_SPEED_HIGH) - 800fbce: 687b ldr r3, [r7, #4] - 800fbd0: 7c1b ldrb r3, [r3, #16] - 800fbd2: 2b00 cmp r3, #0 - 800fbd4: d109 bne.n 800fbea + 80113ca: 687b ldr r3, [r7, #4] + 80113cc: 7c1b ldrb r3, [r3, #16] + 80113ce: 2b00 cmp r3, #0 + 80113d0: d109 bne.n 80113e6 pbuf = (uint8_t *)USBD_CMPSIT.GetDeviceQualifierDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetDeviceQualifierDescriptor(&len); - 800fbd6: 687b ldr r3, [r7, #4] - 800fbd8: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800fbdc: 6b5b ldr r3, [r3, #52] ; 0x34 - 800fbde: f107 0208 add.w r2, r7, #8 - 800fbe2: 4610 mov r0, r2 - 800fbe4: 4798 blx r3 - 800fbe6: 60f8 str r0, [r7, #12] + 80113d2: 687b ldr r3, [r7, #4] + 80113d4: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 80113d8: 6b5b ldr r3, [r3, #52] ; 0x34 + 80113da: f107 0208 add.w r2, r7, #8 + 80113de: 4610 mov r0, r2 + 80113e0: 4798 blx r3 + 80113e2: 60f8 str r0, [r7, #12] else { USBD_CtlError(pdev, req); err++; } break; - 800fbe8: e029 b.n 800fc3e + 80113e4: e029 b.n 801143a USBD_CtlError(pdev, req); - 800fbea: 6839 ldr r1, [r7, #0] - 800fbec: 6878 ldr r0, [r7, #4] - 800fbee: f000 fa2a bl 8010046 + 80113e6: 6839 ldr r1, [r7, #0] + 80113e8: 6878 ldr r0, [r7, #4] + 80113ea: f000 fa2a bl 8011842 err++; - 800fbf2: 7afb ldrb r3, [r7, #11] - 800fbf4: 3301 adds r3, #1 - 800fbf6: 72fb strb r3, [r7, #11] + 80113ee: 7afb ldrb r3, [r7, #11] + 80113f0: 3301 adds r3, #1 + 80113f2: 72fb strb r3, [r7, #11] break; - 800fbf8: e021 b.n 800fc3e + 80113f4: e021 b.n 801143a case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: if (pdev->dev_speed == USBD_SPEED_HIGH) - 800fbfa: 687b ldr r3, [r7, #4] - 800fbfc: 7c1b ldrb r3, [r3, #16] - 800fbfe: 2b00 cmp r3, #0 - 800fc00: d10d bne.n 800fc1e + 80113f6: 687b ldr r3, [r7, #4] + 80113f8: 7c1b ldrb r3, [r3, #16] + 80113fa: 2b00 cmp r3, #0 + 80113fc: d10d bne.n 801141a pbuf = (uint8_t *)USBD_CMPSIT.GetOtherSpeedConfigDescriptor(&len); } else #endif /* USE_USBD_COMPOSITE */ { pbuf = (uint8_t *)pdev->pClass[0]->GetOtherSpeedConfigDescriptor(&len); - 800fc02: 687b ldr r3, [r7, #4] - 800fc04: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 - 800fc08: 6b1b ldr r3, [r3, #48] ; 0x30 - 800fc0a: f107 0208 add.w r2, r7, #8 - 800fc0e: 4610 mov r0, r2 - 800fc10: 4798 blx r3 - 800fc12: 60f8 str r0, [r7, #12] + 80113fe: 687b ldr r3, [r7, #4] + 8011400: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8 + 8011404: 6b1b ldr r3, [r3, #48] ; 0x30 + 8011406: f107 0208 add.w r2, r7, #8 + 801140a: 4610 mov r0, r2 + 801140c: 4798 blx r3 + 801140e: 60f8 str r0, [r7, #12] } pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - 800fc14: 68fb ldr r3, [r7, #12] - 800fc16: 3301 adds r3, #1 - 800fc18: 2207 movs r2, #7 - 800fc1a: 701a strb r2, [r3, #0] + 8011410: 68fb ldr r3, [r7, #12] + 8011412: 3301 adds r3, #1 + 8011414: 2207 movs r2, #7 + 8011416: 701a strb r2, [r3, #0] else { USBD_CtlError(pdev, req); err++; } break; - 800fc1c: e00f b.n 800fc3e + 8011418: e00f b.n 801143a USBD_CtlError(pdev, req); - 800fc1e: 6839 ldr r1, [r7, #0] - 800fc20: 6878 ldr r0, [r7, #4] - 800fc22: f000 fa10 bl 8010046 + 801141a: 6839 ldr r1, [r7, #0] + 801141c: 6878 ldr r0, [r7, #4] + 801141e: f000 fa10 bl 8011842 err++; - 800fc26: 7afb ldrb r3, [r7, #11] - 800fc28: 3301 adds r3, #1 - 800fc2a: 72fb strb r3, [r7, #11] + 8011422: 7afb ldrb r3, [r7, #11] + 8011424: 3301 adds r3, #1 + 8011426: 72fb strb r3, [r7, #11] break; - 800fc2c: e007 b.n 800fc3e + 8011428: e007 b.n 801143a default: USBD_CtlError(pdev, req); - 800fc2e: 6839 ldr r1, [r7, #0] - 800fc30: 6878 ldr r0, [r7, #4] - 800fc32: f000 fa08 bl 8010046 + 801142a: 6839 ldr r1, [r7, #0] + 801142c: 6878 ldr r0, [r7, #4] + 801142e: f000 fa08 bl 8011842 err++; - 800fc36: 7afb ldrb r3, [r7, #11] - 800fc38: 3301 adds r3, #1 - 800fc3a: 72fb strb r3, [r7, #11] + 8011432: 7afb ldrb r3, [r7, #11] + 8011434: 3301 adds r3, #1 + 8011436: 72fb strb r3, [r7, #11] break; - 800fc3c: bf00 nop + 8011438: bf00 nop } if (err != 0U) - 800fc3e: 7afb ldrb r3, [r7, #11] - 800fc40: 2b00 cmp r3, #0 - 800fc42: d11e bne.n 800fc82 + 801143a: 7afb ldrb r3, [r7, #11] + 801143c: 2b00 cmp r3, #0 + 801143e: d11e bne.n 801147e { return; } if (req->wLength != 0U) - 800fc44: 683b ldr r3, [r7, #0] - 800fc46: 88db ldrh r3, [r3, #6] - 800fc48: 2b00 cmp r3, #0 - 800fc4a: d016 beq.n 800fc7a + 8011440: 683b ldr r3, [r7, #0] + 8011442: 88db ldrh r3, [r3, #6] + 8011444: 2b00 cmp r3, #0 + 8011446: d016 beq.n 8011476 { if (len != 0U) - 800fc4c: 893b ldrh r3, [r7, #8] - 800fc4e: 2b00 cmp r3, #0 - 800fc50: d00e beq.n 800fc70 + 8011448: 893b ldrh r3, [r7, #8] + 801144a: 2b00 cmp r3, #0 + 801144c: d00e beq.n 801146c { len = MIN(len, req->wLength); - 800fc52: 683b ldr r3, [r7, #0] - 800fc54: 88da ldrh r2, [r3, #6] - 800fc56: 893b ldrh r3, [r7, #8] - 800fc58: 4293 cmp r3, r2 - 800fc5a: bf28 it cs - 800fc5c: 4613 movcs r3, r2 - 800fc5e: b29b uxth r3, r3 - 800fc60: 813b strh r3, [r7, #8] + 801144e: 683b ldr r3, [r7, #0] + 8011450: 88da ldrh r2, [r3, #6] + 8011452: 893b ldrh r3, [r7, #8] + 8011454: 4293 cmp r3, r2 + 8011456: bf28 it cs + 8011458: 4613 movcs r3, r2 + 801145a: b29b uxth r3, r3 + 801145c: 813b strh r3, [r7, #8] (void)USBD_CtlSendData(pdev, pbuf, len); - 800fc62: 893b ldrh r3, [r7, #8] - 800fc64: 461a mov r2, r3 - 800fc66: 68f9 ldr r1, [r7, #12] - 800fc68: 6878 ldr r0, [r7, #4] - 800fc6a: f000 fa5d bl 8010128 - 800fc6e: e009 b.n 800fc84 + 801145e: 893b ldrh r3, [r7, #8] + 8011460: 461a mov r2, r3 + 8011462: 68f9 ldr r1, [r7, #12] + 8011464: 6878 ldr r0, [r7, #4] + 8011466: f000 fa5d bl 8011924 + 801146a: e009 b.n 8011480 } else { USBD_CtlError(pdev, req); - 800fc70: 6839 ldr r1, [r7, #0] - 800fc72: 6878 ldr r0, [r7, #4] - 800fc74: f000 f9e7 bl 8010046 - 800fc78: e004 b.n 800fc84 + 801146c: 6839 ldr r1, [r7, #0] + 801146e: 6878 ldr r0, [r7, #4] + 8011470: f000 f9e7 bl 8011842 + 8011474: e004 b.n 8011480 } } else { (void)USBD_CtlSendStatus(pdev); - 800fc7a: 6878 ldr r0, [r7, #4] - 800fc7c: f000 fa91 bl 80101a2 - 800fc80: e000 b.n 800fc84 + 8011476: 6878 ldr r0, [r7, #4] + 8011478: f000 faae bl 80119d8 + 801147c: e000 b.n 8011480 return; - 800fc82: bf00 nop + 801147e: bf00 nop } } - 800fc84: 3710 adds r7, #16 - 800fc86: 46bd mov sp, r7 - 800fc88: bd80 pop {r7, pc} - 800fc8a: bf00 nop + 8011480: 3710 adds r7, #16 + 8011482: 46bd mov sp, r7 + 8011484: bd80 pop {r7, pc} + 8011486: bf00 nop -0800fc8c : +08011488 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800fc8c: b580 push {r7, lr} - 800fc8e: b084 sub sp, #16 - 800fc90: af00 add r7, sp, #0 - 800fc92: 6078 str r0, [r7, #4] - 800fc94: 6039 str r1, [r7, #0] + 8011488: b580 push {r7, lr} + 801148a: b084 sub sp, #16 + 801148c: af00 add r7, sp, #0 + 801148e: 6078 str r0, [r7, #4] + 8011490: 6039 str r1, [r7, #0] uint8_t dev_addr; if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) - 800fc96: 683b ldr r3, [r7, #0] - 800fc98: 889b ldrh r3, [r3, #4] - 800fc9a: 2b00 cmp r3, #0 - 800fc9c: d131 bne.n 800fd02 - 800fc9e: 683b ldr r3, [r7, #0] - 800fca0: 88db ldrh r3, [r3, #6] - 800fca2: 2b00 cmp r3, #0 - 800fca4: d12d bne.n 800fd02 - 800fca6: 683b ldr r3, [r7, #0] - 800fca8: 885b ldrh r3, [r3, #2] - 800fcaa: 2b7f cmp r3, #127 ; 0x7f - 800fcac: d829 bhi.n 800fd02 + 8011492: 683b ldr r3, [r7, #0] + 8011494: 889b ldrh r3, [r3, #4] + 8011496: 2b00 cmp r3, #0 + 8011498: d131 bne.n 80114fe + 801149a: 683b ldr r3, [r7, #0] + 801149c: 88db ldrh r3, [r3, #6] + 801149e: 2b00 cmp r3, #0 + 80114a0: d12d bne.n 80114fe + 80114a2: 683b ldr r3, [r7, #0] + 80114a4: 885b ldrh r3, [r3, #2] + 80114a6: 2b7f cmp r3, #127 ; 0x7f + 80114a8: d829 bhi.n 80114fe { dev_addr = (uint8_t)(req->wValue) & 0x7FU; - 800fcae: 683b ldr r3, [r7, #0] - 800fcb0: 885b ldrh r3, [r3, #2] - 800fcb2: b2db uxtb r3, r3 - 800fcb4: f003 037f and.w r3, r3, #127 ; 0x7f - 800fcb8: 73fb strb r3, [r7, #15] + 80114aa: 683b ldr r3, [r7, #0] + 80114ac: 885b ldrh r3, [r3, #2] + 80114ae: b2db uxtb r3, r3 + 80114b0: f003 037f and.w r3, r3, #127 ; 0x7f + 80114b4: 73fb strb r3, [r7, #15] if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800fcba: 687b ldr r3, [r7, #4] - 800fcbc: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800fcc0: b2db uxtb r3, r3 - 800fcc2: 2b03 cmp r3, #3 - 800fcc4: d104 bne.n 800fcd0 + 80114b6: 687b ldr r3, [r7, #4] + 80114b8: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80114bc: b2db uxtb r3, r3 + 80114be: 2b03 cmp r3, #3 + 80114c0: d104 bne.n 80114cc { USBD_CtlError(pdev, req); - 800fcc6: 6839 ldr r1, [r7, #0] - 800fcc8: 6878 ldr r0, [r7, #4] - 800fcca: f000 f9bc bl 8010046 + 80114c2: 6839 ldr r1, [r7, #0] + 80114c4: 6878 ldr r0, [r7, #4] + 80114c6: f000 f9bc bl 8011842 if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800fcce: e01d b.n 800fd0c + 80114ca: e01d b.n 8011508 } else { pdev->dev_address = dev_addr; - 800fcd0: 687b ldr r3, [r7, #4] - 800fcd2: 7bfa ldrb r2, [r7, #15] - 800fcd4: f883 229e strb.w r2, [r3, #670] ; 0x29e + 80114cc: 687b ldr r3, [r7, #4] + 80114ce: 7bfa ldrb r2, [r7, #15] + 80114d0: f883 229e strb.w r2, [r3, #670] ; 0x29e (void)USBD_LL_SetUSBAddress(pdev, dev_addr); - 800fcd8: 7bfb ldrb r3, [r7, #15] - 800fcda: 4619 mov r1, r3 - 800fcdc: 6878 ldr r0, [r7, #4] - 800fcde: f000 fe2f bl 8010940 + 80114d4: 7bfb ldrb r3, [r7, #15] + 80114d6: 4619 mov r1, r3 + 80114d8: 6878 ldr r0, [r7, #4] + 80114da: f001 fc71 bl 8012dc0 (void)USBD_CtlSendStatus(pdev); - 800fce2: 6878 ldr r0, [r7, #4] - 800fce4: f000 fa5d bl 80101a2 + 80114de: 6878 ldr r0, [r7, #4] + 80114e0: f000 fa7a bl 80119d8 if (dev_addr != 0U) - 800fce8: 7bfb ldrb r3, [r7, #15] - 800fcea: 2b00 cmp r3, #0 - 800fcec: d004 beq.n 800fcf8 + 80114e4: 7bfb ldrb r3, [r7, #15] + 80114e6: 2b00 cmp r3, #0 + 80114e8: d004 beq.n 80114f4 { pdev->dev_state = USBD_STATE_ADDRESSED; - 800fcee: 687b ldr r3, [r7, #4] - 800fcf0: 2202 movs r2, #2 - 800fcf2: f883 229c strb.w r2, [r3, #668] ; 0x29c + 80114ea: 687b ldr r3, [r7, #4] + 80114ec: 2202 movs r2, #2 + 80114ee: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800fcf6: e009 b.n 800fd0c + 80114f2: e009 b.n 8011508 } else { pdev->dev_state = USBD_STATE_DEFAULT; - 800fcf8: 687b ldr r3, [r7, #4] - 800fcfa: 2201 movs r2, #1 - 800fcfc: f883 229c strb.w r2, [r3, #668] ; 0x29c + 80114f4: 687b ldr r3, [r7, #4] + 80114f6: 2201 movs r2, #1 + 80114f8: f883 229c strb.w r2, [r3, #668] ; 0x29c if (pdev->dev_state == USBD_STATE_CONFIGURED) - 800fd00: e004 b.n 800fd0c + 80114fc: e004 b.n 8011508 } } } else { USBD_CtlError(pdev, req); - 800fd02: 6839 ldr r1, [r7, #0] - 800fd04: 6878 ldr r0, [r7, #4] - 800fd06: f000 f99e bl 8010046 + 80114fe: 6839 ldr r1, [r7, #0] + 8011500: 6878 ldr r0, [r7, #4] + 8011502: f000 f99e bl 8011842 } } - 800fd0a: bf00 nop - 800fd0c: bf00 nop - 800fd0e: 3710 adds r7, #16 - 800fd10: 46bd mov sp, r7 - 800fd12: bd80 pop {r7, pc} + 8011506: bf00 nop + 8011508: bf00 nop + 801150a: 3710 adds r7, #16 + 801150c: 46bd mov sp, r7 + 801150e: bd80 pop {r7, pc} -0800fd14 : +08011510 : * @param pdev: device instance * @param req: usb request * @retval status */ static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800fd14: b580 push {r7, lr} - 800fd16: b084 sub sp, #16 - 800fd18: af00 add r7, sp, #0 - 800fd1a: 6078 str r0, [r7, #4] - 800fd1c: 6039 str r1, [r7, #0] + 8011510: b580 push {r7, lr} + 8011512: b084 sub sp, #16 + 8011514: af00 add r7, sp, #0 + 8011516: 6078 str r0, [r7, #4] + 8011518: 6039 str r1, [r7, #0] USBD_StatusTypeDef ret = USBD_OK; - 800fd1e: 2300 movs r3, #0 - 800fd20: 73fb strb r3, [r7, #15] + 801151a: 2300 movs r3, #0 + 801151c: 73fb strb r3, [r7, #15] static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); - 800fd22: 683b ldr r3, [r7, #0] - 800fd24: 885b ldrh r3, [r3, #2] - 800fd26: b2da uxtb r2, r3 - 800fd28: 4b4e ldr r3, [pc, #312] ; (800fe64 ) - 800fd2a: 701a strb r2, [r3, #0] + 801151e: 683b ldr r3, [r7, #0] + 8011520: 885b ldrh r3, [r3, #2] + 8011522: b2da uxtb r2, r3 + 8011524: 4b4e ldr r3, [pc, #312] ; (8011660 ) + 8011526: 701a strb r2, [r3, #0] if (cfgidx > USBD_MAX_NUM_CONFIGURATION) - 800fd2c: 4b4d ldr r3, [pc, #308] ; (800fe64 ) - 800fd2e: 781b ldrb r3, [r3, #0] - 800fd30: 2b01 cmp r3, #1 - 800fd32: d905 bls.n 800fd40 + 8011528: 4b4d ldr r3, [pc, #308] ; (8011660 ) + 801152a: 781b ldrb r3, [r3, #0] + 801152c: 2b01 cmp r3, #1 + 801152e: d905 bls.n 801153c { USBD_CtlError(pdev, req); - 800fd34: 6839 ldr r1, [r7, #0] - 800fd36: 6878 ldr r0, [r7, #4] - 800fd38: f000 f985 bl 8010046 + 8011530: 6839 ldr r1, [r7, #0] + 8011532: 6878 ldr r0, [r7, #4] + 8011534: f000 f985 bl 8011842 return USBD_FAIL; - 800fd3c: 2303 movs r3, #3 - 800fd3e: e08c b.n 800fe5a + 8011538: 2303 movs r3, #3 + 801153a: e08c b.n 8011656 } switch (pdev->dev_state) - 800fd40: 687b ldr r3, [r7, #4] - 800fd42: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800fd46: b2db uxtb r3, r3 - 800fd48: 2b02 cmp r3, #2 - 800fd4a: d002 beq.n 800fd52 - 800fd4c: 2b03 cmp r3, #3 - 800fd4e: d029 beq.n 800fda4 - 800fd50: e075 b.n 800fe3e + 801153c: 687b ldr r3, [r7, #4] + 801153e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8011542: b2db uxtb r3, r3 + 8011544: 2b02 cmp r3, #2 + 8011546: d002 beq.n 801154e + 8011548: 2b03 cmp r3, #3 + 801154a: d029 beq.n 80115a0 + 801154c: e075 b.n 801163a { case USBD_STATE_ADDRESSED: if (cfgidx != 0U) - 800fd52: 4b44 ldr r3, [pc, #272] ; (800fe64 ) - 800fd54: 781b ldrb r3, [r3, #0] - 800fd56: 2b00 cmp r3, #0 - 800fd58: d020 beq.n 800fd9c + 801154e: 4b44 ldr r3, [pc, #272] ; (8011660 ) + 8011550: 781b ldrb r3, [r3, #0] + 8011552: 2b00 cmp r3, #0 + 8011554: d020 beq.n 8011598 { pdev->dev_config = cfgidx; - 800fd5a: 4b42 ldr r3, [pc, #264] ; (800fe64 ) - 800fd5c: 781b ldrb r3, [r3, #0] - 800fd5e: 461a mov r2, r3 - 800fd60: 687b ldr r3, [r7, #4] - 800fd62: 605a str r2, [r3, #4] + 8011556: 4b42 ldr r3, [pc, #264] ; (8011660 ) + 8011558: 781b ldrb r3, [r3, #0] + 801155a: 461a mov r2, r3 + 801155c: 687b ldr r3, [r7, #4] + 801155e: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); - 800fd64: 4b3f ldr r3, [pc, #252] ; (800fe64 ) - 800fd66: 781b ldrb r3, [r3, #0] - 800fd68: 4619 mov r1, r3 - 800fd6a: 6878 ldr r0, [r7, #4] - 800fd6c: f7ff f849 bl 800ee02 - 800fd70: 4603 mov r3, r0 - 800fd72: 73fb strb r3, [r7, #15] + 8011560: 4b3f ldr r3, [pc, #252] ; (8011660 ) + 8011562: 781b ldrb r3, [r3, #0] + 8011564: 4619 mov r1, r3 + 8011566: 6878 ldr r0, [r7, #4] + 8011568: f7ff f849 bl 80105fe + 801156c: 4603 mov r3, r0 + 801156e: 73fb strb r3, [r7, #15] if (ret != USBD_OK) - 800fd74: 7bfb ldrb r3, [r7, #15] - 800fd76: 2b00 cmp r3, #0 - 800fd78: d008 beq.n 800fd8c + 8011570: 7bfb ldrb r3, [r7, #15] + 8011572: 2b00 cmp r3, #0 + 8011574: d008 beq.n 8011588 { USBD_CtlError(pdev, req); - 800fd7a: 6839 ldr r1, [r7, #0] - 800fd7c: 6878 ldr r0, [r7, #4] - 800fd7e: f000 f962 bl 8010046 + 8011576: 6839 ldr r1, [r7, #0] + 8011578: 6878 ldr r0, [r7, #4] + 801157a: f000 f962 bl 8011842 pdev->dev_state = USBD_STATE_ADDRESSED; - 800fd82: 687b ldr r3, [r7, #4] - 800fd84: 2202 movs r2, #2 - 800fd86: f883 229c strb.w r2, [r3, #668] ; 0x29c + 801157e: 687b ldr r3, [r7, #4] + 8011580: 2202 movs r2, #2 + 8011582: f883 229c strb.w r2, [r3, #668] ; 0x29c } else { (void)USBD_CtlSendStatus(pdev); } break; - 800fd8a: e065 b.n 800fe58 + 8011586: e065 b.n 8011654 (void)USBD_CtlSendStatus(pdev); - 800fd8c: 6878 ldr r0, [r7, #4] - 800fd8e: f000 fa08 bl 80101a2 + 8011588: 6878 ldr r0, [r7, #4] + 801158a: f000 fa25 bl 80119d8 pdev->dev_state = USBD_STATE_CONFIGURED; - 800fd92: 687b ldr r3, [r7, #4] - 800fd94: 2203 movs r2, #3 - 800fd96: f883 229c strb.w r2, [r3, #668] ; 0x29c + 801158e: 687b ldr r3, [r7, #4] + 8011590: 2203 movs r2, #3 + 8011592: f883 229c strb.w r2, [r3, #668] ; 0x29c break; - 800fd9a: e05d b.n 800fe58 + 8011596: e05d b.n 8011654 (void)USBD_CtlSendStatus(pdev); - 800fd9c: 6878 ldr r0, [r7, #4] - 800fd9e: f000 fa00 bl 80101a2 + 8011598: 6878 ldr r0, [r7, #4] + 801159a: f000 fa1d bl 80119d8 break; - 800fda2: e059 b.n 800fe58 + 801159e: e059 b.n 8011654 case USBD_STATE_CONFIGURED: if (cfgidx == 0U) - 800fda4: 4b2f ldr r3, [pc, #188] ; (800fe64 ) - 800fda6: 781b ldrb r3, [r3, #0] - 800fda8: 2b00 cmp r3, #0 - 800fdaa: d112 bne.n 800fdd2 + 80115a0: 4b2f ldr r3, [pc, #188] ; (8011660 ) + 80115a2: 781b ldrb r3, [r3, #0] + 80115a4: 2b00 cmp r3, #0 + 80115a6: d112 bne.n 80115ce { pdev->dev_state = USBD_STATE_ADDRESSED; - 800fdac: 687b ldr r3, [r7, #4] - 800fdae: 2202 movs r2, #2 - 800fdb0: f883 229c strb.w r2, [r3, #668] ; 0x29c + 80115a8: 687b ldr r3, [r7, #4] + 80115aa: 2202 movs r2, #2 + 80115ac: f883 229c strb.w r2, [r3, #668] ; 0x29c pdev->dev_config = cfgidx; - 800fdb4: 4b2b ldr r3, [pc, #172] ; (800fe64 ) - 800fdb6: 781b ldrb r3, [r3, #0] - 800fdb8: 461a mov r2, r3 - 800fdba: 687b ldr r3, [r7, #4] - 800fdbc: 605a str r2, [r3, #4] + 80115b0: 4b2b ldr r3, [pc, #172] ; (8011660 ) + 80115b2: 781b ldrb r3, [r3, #0] + 80115b4: 461a mov r2, r3 + 80115b6: 687b ldr r3, [r7, #4] + 80115b8: 605a str r2, [r3, #4] (void)USBD_ClrClassConfig(pdev, cfgidx); - 800fdbe: 4b29 ldr r3, [pc, #164] ; (800fe64 ) - 800fdc0: 781b ldrb r3, [r3, #0] - 800fdc2: 4619 mov r1, r3 - 800fdc4: 6878 ldr r0, [r7, #4] - 800fdc6: f7ff f838 bl 800ee3a + 80115ba: 4b29 ldr r3, [pc, #164] ; (8011660 ) + 80115bc: 781b ldrb r3, [r3, #0] + 80115be: 4619 mov r1, r3 + 80115c0: 6878 ldr r0, [r7, #4] + 80115c2: f7ff f838 bl 8010636 (void)USBD_CtlSendStatus(pdev); - 800fdca: 6878 ldr r0, [r7, #4] - 800fdcc: f000 f9e9 bl 80101a2 + 80115c6: 6878 ldr r0, [r7, #4] + 80115c8: f000 fa06 bl 80119d8 } else { (void)USBD_CtlSendStatus(pdev); } break; - 800fdd0: e042 b.n 800fe58 + 80115cc: e042 b.n 8011654 else if (cfgidx != pdev->dev_config) - 800fdd2: 4b24 ldr r3, [pc, #144] ; (800fe64 ) - 800fdd4: 781b ldrb r3, [r3, #0] - 800fdd6: 461a mov r2, r3 - 800fdd8: 687b ldr r3, [r7, #4] - 800fdda: 685b ldr r3, [r3, #4] - 800fddc: 429a cmp r2, r3 - 800fdde: d02a beq.n 800fe36 + 80115ce: 4b24 ldr r3, [pc, #144] ; (8011660 ) + 80115d0: 781b ldrb r3, [r3, #0] + 80115d2: 461a mov r2, r3 + 80115d4: 687b ldr r3, [r7, #4] + 80115d6: 685b ldr r3, [r3, #4] + 80115d8: 429a cmp r2, r3 + 80115da: d02a beq.n 8011632 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); - 800fde0: 687b ldr r3, [r7, #4] - 800fde2: 685b ldr r3, [r3, #4] - 800fde4: b2db uxtb r3, r3 - 800fde6: 4619 mov r1, r3 - 800fde8: 6878 ldr r0, [r7, #4] - 800fdea: f7ff f826 bl 800ee3a + 80115dc: 687b ldr r3, [r7, #4] + 80115de: 685b ldr r3, [r3, #4] + 80115e0: b2db uxtb r3, r3 + 80115e2: 4619 mov r1, r3 + 80115e4: 6878 ldr r0, [r7, #4] + 80115e6: f7ff f826 bl 8010636 pdev->dev_config = cfgidx; - 800fdee: 4b1d ldr r3, [pc, #116] ; (800fe64 ) - 800fdf0: 781b ldrb r3, [r3, #0] - 800fdf2: 461a mov r2, r3 - 800fdf4: 687b ldr r3, [r7, #4] - 800fdf6: 605a str r2, [r3, #4] + 80115ea: 4b1d ldr r3, [pc, #116] ; (8011660 ) + 80115ec: 781b ldrb r3, [r3, #0] + 80115ee: 461a mov r2, r3 + 80115f0: 687b ldr r3, [r7, #4] + 80115f2: 605a str r2, [r3, #4] ret = USBD_SetClassConfig(pdev, cfgidx); - 800fdf8: 4b1a ldr r3, [pc, #104] ; (800fe64 ) - 800fdfa: 781b ldrb r3, [r3, #0] - 800fdfc: 4619 mov r1, r3 - 800fdfe: 6878 ldr r0, [r7, #4] - 800fe00: f7fe ffff bl 800ee02 - 800fe04: 4603 mov r3, r0 - 800fe06: 73fb strb r3, [r7, #15] + 80115f4: 4b1a ldr r3, [pc, #104] ; (8011660 ) + 80115f6: 781b ldrb r3, [r3, #0] + 80115f8: 4619 mov r1, r3 + 80115fa: 6878 ldr r0, [r7, #4] + 80115fc: f7fe ffff bl 80105fe + 8011600: 4603 mov r3, r0 + 8011602: 73fb strb r3, [r7, #15] if (ret != USBD_OK) - 800fe08: 7bfb ldrb r3, [r7, #15] - 800fe0a: 2b00 cmp r3, #0 - 800fe0c: d00f beq.n 800fe2e + 8011604: 7bfb ldrb r3, [r7, #15] + 8011606: 2b00 cmp r3, #0 + 8011608: d00f beq.n 801162a USBD_CtlError(pdev, req); - 800fe0e: 6839 ldr r1, [r7, #0] - 800fe10: 6878 ldr r0, [r7, #4] - 800fe12: f000 f918 bl 8010046 + 801160a: 6839 ldr r1, [r7, #0] + 801160c: 6878 ldr r0, [r7, #4] + 801160e: f000 f918 bl 8011842 (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); - 800fe16: 687b ldr r3, [r7, #4] - 800fe18: 685b ldr r3, [r3, #4] - 800fe1a: b2db uxtb r3, r3 - 800fe1c: 4619 mov r1, r3 - 800fe1e: 6878 ldr r0, [r7, #4] - 800fe20: f7ff f80b bl 800ee3a + 8011612: 687b ldr r3, [r7, #4] + 8011614: 685b ldr r3, [r3, #4] + 8011616: b2db uxtb r3, r3 + 8011618: 4619 mov r1, r3 + 801161a: 6878 ldr r0, [r7, #4] + 801161c: f7ff f80b bl 8010636 pdev->dev_state = USBD_STATE_ADDRESSED; - 800fe24: 687b ldr r3, [r7, #4] - 800fe26: 2202 movs r2, #2 - 800fe28: f883 229c strb.w r2, [r3, #668] ; 0x29c + 8011620: 687b ldr r3, [r7, #4] + 8011622: 2202 movs r2, #2 + 8011624: f883 229c strb.w r2, [r3, #668] ; 0x29c break; - 800fe2c: e014 b.n 800fe58 + 8011628: e014 b.n 8011654 (void)USBD_CtlSendStatus(pdev); - 800fe2e: 6878 ldr r0, [r7, #4] - 800fe30: f000 f9b7 bl 80101a2 + 801162a: 6878 ldr r0, [r7, #4] + 801162c: f000 f9d4 bl 80119d8 break; - 800fe34: e010 b.n 800fe58 + 8011630: e010 b.n 8011654 (void)USBD_CtlSendStatus(pdev); - 800fe36: 6878 ldr r0, [r7, #4] - 800fe38: f000 f9b3 bl 80101a2 + 8011632: 6878 ldr r0, [r7, #4] + 8011634: f000 f9d0 bl 80119d8 break; - 800fe3c: e00c b.n 800fe58 + 8011638: e00c b.n 8011654 default: USBD_CtlError(pdev, req); - 800fe3e: 6839 ldr r1, [r7, #0] - 800fe40: 6878 ldr r0, [r7, #4] - 800fe42: f000 f900 bl 8010046 + 801163a: 6839 ldr r1, [r7, #0] + 801163c: 6878 ldr r0, [r7, #4] + 801163e: f000 f900 bl 8011842 (void)USBD_ClrClassConfig(pdev, cfgidx); - 800fe46: 4b07 ldr r3, [pc, #28] ; (800fe64 ) - 800fe48: 781b ldrb r3, [r3, #0] - 800fe4a: 4619 mov r1, r3 - 800fe4c: 6878 ldr r0, [r7, #4] - 800fe4e: f7fe fff4 bl 800ee3a + 8011642: 4b07 ldr r3, [pc, #28] ; (8011660 ) + 8011644: 781b ldrb r3, [r3, #0] + 8011646: 4619 mov r1, r3 + 8011648: 6878 ldr r0, [r7, #4] + 801164a: f7fe fff4 bl 8010636 ret = USBD_FAIL; - 800fe52: 2303 movs r3, #3 - 800fe54: 73fb strb r3, [r7, #15] + 801164e: 2303 movs r3, #3 + 8011650: 73fb strb r3, [r7, #15] break; - 800fe56: bf00 nop + 8011652: bf00 nop } return ret; - 800fe58: 7bfb ldrb r3, [r7, #15] + 8011654: 7bfb ldrb r3, [r7, #15] } - 800fe5a: 4618 mov r0, r3 - 800fe5c: 3710 adds r7, #16 - 800fe5e: 46bd mov sp, r7 - 800fe60: bd80 pop {r7, pc} - 800fe62: bf00 nop - 800fe64: 20000ca0 .word 0x20000ca0 + 8011656: 4618 mov r0, r3 + 8011658: 3710 adds r7, #16 + 801165a: 46bd mov sp, r7 + 801165c: bd80 pop {r7, pc} + 801165e: bf00 nop + 8011660: 2000104c .word 0x2000104c -0800fe68 : +08011664 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800fe68: b580 push {r7, lr} - 800fe6a: b082 sub sp, #8 - 800fe6c: af00 add r7, sp, #0 - 800fe6e: 6078 str r0, [r7, #4] - 800fe70: 6039 str r1, [r7, #0] + 8011664: b580 push {r7, lr} + 8011666: b082 sub sp, #8 + 8011668: af00 add r7, sp, #0 + 801166a: 6078 str r0, [r7, #4] + 801166c: 6039 str r1, [r7, #0] if (req->wLength != 1U) - 800fe72: 683b ldr r3, [r7, #0] - 800fe74: 88db ldrh r3, [r3, #6] - 800fe76: 2b01 cmp r3, #1 - 800fe78: d004 beq.n 800fe84 + 801166e: 683b ldr r3, [r7, #0] + 8011670: 88db ldrh r3, [r3, #6] + 8011672: 2b01 cmp r3, #1 + 8011674: d004 beq.n 8011680 { USBD_CtlError(pdev, req); - 800fe7a: 6839 ldr r1, [r7, #0] - 800fe7c: 6878 ldr r0, [r7, #4] - 800fe7e: f000 f8e2 bl 8010046 + 8011676: 6839 ldr r1, [r7, #0] + 8011678: 6878 ldr r0, [r7, #4] + 801167a: f000 f8e2 bl 8011842 default: USBD_CtlError(pdev, req); break; } } } - 800fe82: e023 b.n 800fecc + 801167e: e023 b.n 80116c8 switch (pdev->dev_state) - 800fe84: 687b ldr r3, [r7, #4] - 800fe86: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800fe8a: b2db uxtb r3, r3 - 800fe8c: 2b02 cmp r3, #2 - 800fe8e: dc02 bgt.n 800fe96 - 800fe90: 2b00 cmp r3, #0 - 800fe92: dc03 bgt.n 800fe9c - 800fe94: e015 b.n 800fec2 - 800fe96: 2b03 cmp r3, #3 - 800fe98: d00b beq.n 800feb2 - 800fe9a: e012 b.n 800fec2 + 8011680: 687b ldr r3, [r7, #4] + 8011682: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 8011686: b2db uxtb r3, r3 + 8011688: 2b02 cmp r3, #2 + 801168a: dc02 bgt.n 8011692 + 801168c: 2b00 cmp r3, #0 + 801168e: dc03 bgt.n 8011698 + 8011690: e015 b.n 80116be + 8011692: 2b03 cmp r3, #3 + 8011694: d00b beq.n 80116ae + 8011696: e012 b.n 80116be pdev->dev_default_config = 0U; - 800fe9c: 687b ldr r3, [r7, #4] - 800fe9e: 2200 movs r2, #0 - 800fea0: 609a str r2, [r3, #8] + 8011698: 687b ldr r3, [r7, #4] + 801169a: 2200 movs r2, #0 + 801169c: 609a str r2, [r3, #8] (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); - 800fea2: 687b ldr r3, [r7, #4] - 800fea4: 3308 adds r3, #8 - 800fea6: 2201 movs r2, #1 - 800fea8: 4619 mov r1, r3 - 800feaa: 6878 ldr r0, [r7, #4] - 800feac: f000 f93c bl 8010128 + 801169e: 687b ldr r3, [r7, #4] + 80116a0: 3308 adds r3, #8 + 80116a2: 2201 movs r2, #1 + 80116a4: 4619 mov r1, r3 + 80116a6: 6878 ldr r0, [r7, #4] + 80116a8: f000 f93c bl 8011924 break; - 800feb0: e00c b.n 800fecc + 80116ac: e00c b.n 80116c8 (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); - 800feb2: 687b ldr r3, [r7, #4] - 800feb4: 3304 adds r3, #4 - 800feb6: 2201 movs r2, #1 - 800feb8: 4619 mov r1, r3 - 800feba: 6878 ldr r0, [r7, #4] - 800febc: f000 f934 bl 8010128 + 80116ae: 687b ldr r3, [r7, #4] + 80116b0: 3304 adds r3, #4 + 80116b2: 2201 movs r2, #1 + 80116b4: 4619 mov r1, r3 + 80116b6: 6878 ldr r0, [r7, #4] + 80116b8: f000 f934 bl 8011924 break; - 800fec0: e004 b.n 800fecc + 80116bc: e004 b.n 80116c8 USBD_CtlError(pdev, req); - 800fec2: 6839 ldr r1, [r7, #0] - 800fec4: 6878 ldr r0, [r7, #4] - 800fec6: f000 f8be bl 8010046 + 80116be: 6839 ldr r1, [r7, #0] + 80116c0: 6878 ldr r0, [r7, #4] + 80116c2: f000 f8be bl 8011842 break; - 800feca: bf00 nop + 80116c6: bf00 nop } - 800fecc: bf00 nop - 800fece: 3708 adds r7, #8 - 800fed0: 46bd mov sp, r7 - 800fed2: bd80 pop {r7, pc} + 80116c8: bf00 nop + 80116ca: 3708 adds r7, #8 + 80116cc: 46bd mov sp, r7 + 80116ce: bd80 pop {r7, pc} -0800fed4 : +080116d0 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800fed4: b580 push {r7, lr} - 800fed6: b082 sub sp, #8 - 800fed8: af00 add r7, sp, #0 - 800feda: 6078 str r0, [r7, #4] - 800fedc: 6039 str r1, [r7, #0] + 80116d0: b580 push {r7, lr} + 80116d2: b082 sub sp, #8 + 80116d4: af00 add r7, sp, #0 + 80116d6: 6078 str r0, [r7, #4] + 80116d8: 6039 str r1, [r7, #0] switch (pdev->dev_state) - 800fede: 687b ldr r3, [r7, #4] - 800fee0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800fee4: b2db uxtb r3, r3 - 800fee6: 3b01 subs r3, #1 - 800fee8: 2b02 cmp r3, #2 - 800feea: d81e bhi.n 800ff2a + 80116da: 687b ldr r3, [r7, #4] + 80116dc: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 80116e0: b2db uxtb r3, r3 + 80116e2: 3b01 subs r3, #1 + 80116e4: 2b02 cmp r3, #2 + 80116e6: d81e bhi.n 8011726 { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wLength != 0x2U) - 800feec: 683b ldr r3, [r7, #0] - 800feee: 88db ldrh r3, [r3, #6] - 800fef0: 2b02 cmp r3, #2 - 800fef2: d004 beq.n 800fefe + 80116e8: 683b ldr r3, [r7, #0] + 80116ea: 88db ldrh r3, [r3, #6] + 80116ec: 2b02 cmp r3, #2 + 80116ee: d004 beq.n 80116fa { USBD_CtlError(pdev, req); - 800fef4: 6839 ldr r1, [r7, #0] - 800fef6: 6878 ldr r0, [r7, #4] - 800fef8: f000 f8a5 bl 8010046 + 80116f0: 6839 ldr r1, [r7, #0] + 80116f2: 6878 ldr r0, [r7, #4] + 80116f4: f000 f8a5 bl 8011842 break; - 800fefc: e01a b.n 800ff34 + 80116f8: e01a b.n 8011730 } #if (USBD_SELF_POWERED == 1U) pdev->dev_config_status = USB_CONFIG_SELF_POWERED; - 800fefe: 687b ldr r3, [r7, #4] - 800ff00: 2201 movs r2, #1 - 800ff02: 60da str r2, [r3, #12] + 80116fa: 687b ldr r3, [r7, #4] + 80116fc: 2201 movs r2, #1 + 80116fe: 60da str r2, [r3, #12] #else pdev->dev_config_status = 0U; #endif /* USBD_SELF_POWERED */ if (pdev->dev_remote_wakeup != 0U) - 800ff04: 687b ldr r3, [r7, #4] - 800ff06: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 - 800ff0a: 2b00 cmp r3, #0 - 800ff0c: d005 beq.n 800ff1a + 8011700: 687b ldr r3, [r7, #4] + 8011702: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4 + 8011706: 2b00 cmp r3, #0 + 8011708: d005 beq.n 8011716 { pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - 800ff0e: 687b ldr r3, [r7, #4] - 800ff10: 68db ldr r3, [r3, #12] - 800ff12: f043 0202 orr.w r2, r3, #2 - 800ff16: 687b ldr r3, [r7, #4] - 800ff18: 60da str r2, [r3, #12] + 801170a: 687b ldr r3, [r7, #4] + 801170c: 68db ldr r3, [r3, #12] + 801170e: f043 0202 orr.w r2, r3, #2 + 8011712: 687b ldr r3, [r7, #4] + 8011714: 60da str r2, [r3, #12] } (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); - 800ff1a: 687b ldr r3, [r7, #4] - 800ff1c: 330c adds r3, #12 - 800ff1e: 2202 movs r2, #2 - 800ff20: 4619 mov r1, r3 - 800ff22: 6878 ldr r0, [r7, #4] - 800ff24: f000 f900 bl 8010128 + 8011716: 687b ldr r3, [r7, #4] + 8011718: 330c adds r3, #12 + 801171a: 2202 movs r2, #2 + 801171c: 4619 mov r1, r3 + 801171e: 6878 ldr r0, [r7, #4] + 8011720: f000 f900 bl 8011924 break; - 800ff28: e004 b.n 800ff34 + 8011724: e004 b.n 8011730 default: USBD_CtlError(pdev, req); - 800ff2a: 6839 ldr r1, [r7, #0] - 800ff2c: 6878 ldr r0, [r7, #4] - 800ff2e: f000 f88a bl 8010046 + 8011726: 6839 ldr r1, [r7, #0] + 8011728: 6878 ldr r0, [r7, #4] + 801172a: f000 f88a bl 8011842 break; - 800ff32: bf00 nop + 801172e: bf00 nop } } - 800ff34: bf00 nop - 800ff36: 3708 adds r7, #8 - 800ff38: 46bd mov sp, r7 - 800ff3a: bd80 pop {r7, pc} + 8011730: bf00 nop + 8011732: 3708 adds r7, #8 + 8011734: 46bd mov sp, r7 + 8011736: bd80 pop {r7, pc} -0800ff3c : +08011738 : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800ff3c: b580 push {r7, lr} - 800ff3e: b082 sub sp, #8 - 800ff40: af00 add r7, sp, #0 - 800ff42: 6078 str r0, [r7, #4] - 800ff44: 6039 str r1, [r7, #0] + 8011738: b580 push {r7, lr} + 801173a: b082 sub sp, #8 + 801173c: af00 add r7, sp, #0 + 801173e: 6078 str r0, [r7, #4] + 8011740: 6039 str r1, [r7, #0] if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - 800ff46: 683b ldr r3, [r7, #0] - 800ff48: 885b ldrh r3, [r3, #2] - 800ff4a: 2b01 cmp r3, #1 - 800ff4c: d107 bne.n 800ff5e + 8011742: 683b ldr r3, [r7, #0] + 8011744: 885b ldrh r3, [r3, #2] + 8011746: 2b01 cmp r3, #1 + 8011748: d107 bne.n 801175a { pdev->dev_remote_wakeup = 1U; - 800ff4e: 687b ldr r3, [r7, #4] - 800ff50: 2201 movs r2, #1 - 800ff52: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + 801174a: 687b ldr r3, [r7, #4] + 801174c: 2201 movs r2, #1 + 801174e: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); - 800ff56: 6878 ldr r0, [r7, #4] - 800ff58: f000 f923 bl 80101a2 + 8011752: 6878 ldr r0, [r7, #4] + 8011754: f000 f940 bl 80119d8 } else { USBD_CtlError(pdev, req); } } - 800ff5c: e013 b.n 800ff86 + 8011758: e013 b.n 8011782 else if (req->wValue == USB_FEATURE_TEST_MODE) - 800ff5e: 683b ldr r3, [r7, #0] - 800ff60: 885b ldrh r3, [r3, #2] - 800ff62: 2b02 cmp r3, #2 - 800ff64: d10b bne.n 800ff7e + 801175a: 683b ldr r3, [r7, #0] + 801175c: 885b ldrh r3, [r3, #2] + 801175e: 2b02 cmp r3, #2 + 8011760: d10b bne.n 801177a pdev->dev_test_mode = (uint8_t)(req->wIndex >> 8); - 800ff66: 683b ldr r3, [r7, #0] - 800ff68: 889b ldrh r3, [r3, #4] - 800ff6a: 0a1b lsrs r3, r3, #8 - 800ff6c: b29b uxth r3, r3 - 800ff6e: b2da uxtb r2, r3 - 800ff70: 687b ldr r3, [r7, #4] - 800ff72: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 + 8011762: 683b ldr r3, [r7, #0] + 8011764: 889b ldrh r3, [r3, #4] + 8011766: 0a1b lsrs r3, r3, #8 + 8011768: b29b uxth r3, r3 + 801176a: b2da uxtb r2, r3 + 801176c: 687b ldr r3, [r7, #4] + 801176e: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0 (void)USBD_CtlSendStatus(pdev); - 800ff76: 6878 ldr r0, [r7, #4] - 800ff78: f000 f913 bl 80101a2 + 8011772: 6878 ldr r0, [r7, #4] + 8011774: f000 f930 bl 80119d8 } - 800ff7c: e003 b.n 800ff86 + 8011778: e003 b.n 8011782 USBD_CtlError(pdev, req); - 800ff7e: 6839 ldr r1, [r7, #0] - 800ff80: 6878 ldr r0, [r7, #4] - 800ff82: f000 f860 bl 8010046 + 801177a: 6839 ldr r1, [r7, #0] + 801177c: 6878 ldr r0, [r7, #4] + 801177e: f000 f860 bl 8011842 } - 800ff86: bf00 nop - 800ff88: 3708 adds r7, #8 - 800ff8a: 46bd mov sp, r7 - 800ff8c: bd80 pop {r7, pc} + 8011782: bf00 nop + 8011784: 3708 adds r7, #8 + 8011786: 46bd mov sp, r7 + 8011788: bd80 pop {r7, pc} -0800ff8e : +0801178a : * @param pdev: device instance * @param req: usb request * @retval status */ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 800ff8e: b580 push {r7, lr} - 800ff90: b082 sub sp, #8 - 800ff92: af00 add r7, sp, #0 - 800ff94: 6078 str r0, [r7, #4] - 800ff96: 6039 str r1, [r7, #0] + 801178a: b580 push {r7, lr} + 801178c: b082 sub sp, #8 + 801178e: af00 add r7, sp, #0 + 8011790: 6078 str r0, [r7, #4] + 8011792: 6039 str r1, [r7, #0] switch (pdev->dev_state) - 800ff98: 687b ldr r3, [r7, #4] - 800ff9a: f893 329c ldrb.w r3, [r3, #668] ; 0x29c - 800ff9e: b2db uxtb r3, r3 - 800ffa0: 3b01 subs r3, #1 - 800ffa2: 2b02 cmp r3, #2 - 800ffa4: d80b bhi.n 800ffbe + 8011794: 687b ldr r3, [r7, #4] + 8011796: f893 329c ldrb.w r3, [r3, #668] ; 0x29c + 801179a: b2db uxtb r3, r3 + 801179c: 3b01 subs r3, #1 + 801179e: 2b02 cmp r3, #2 + 80117a0: d80b bhi.n 80117ba { case USBD_STATE_DEFAULT: case USBD_STATE_ADDRESSED: case USBD_STATE_CONFIGURED: if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - 800ffa6: 683b ldr r3, [r7, #0] - 800ffa8: 885b ldrh r3, [r3, #2] - 800ffaa: 2b01 cmp r3, #1 - 800ffac: d10c bne.n 800ffc8 + 80117a2: 683b ldr r3, [r7, #0] + 80117a4: 885b ldrh r3, [r3, #2] + 80117a6: 2b01 cmp r3, #1 + 80117a8: d10c bne.n 80117c4 { pdev->dev_remote_wakeup = 0U; - 800ffae: 687b ldr r3, [r7, #4] - 800ffb0: 2200 movs r2, #0 - 800ffb2: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 + 80117aa: 687b ldr r3, [r7, #4] + 80117ac: 2200 movs r2, #0 + 80117ae: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4 (void)USBD_CtlSendStatus(pdev); - 800ffb6: 6878 ldr r0, [r7, #4] - 800ffb8: f000 f8f3 bl 80101a2 + 80117b2: 6878 ldr r0, [r7, #4] + 80117b4: f000 f910 bl 80119d8 } break; - 800ffbc: e004 b.n 800ffc8 + 80117b8: e004 b.n 80117c4 default: USBD_CtlError(pdev, req); - 800ffbe: 6839 ldr r1, [r7, #0] - 800ffc0: 6878 ldr r0, [r7, #4] - 800ffc2: f000 f840 bl 8010046 + 80117ba: 6839 ldr r1, [r7, #0] + 80117bc: 6878 ldr r0, [r7, #4] + 80117be: f000 f840 bl 8011842 break; - 800ffc6: e000 b.n 800ffca + 80117c2: e000 b.n 80117c6 break; - 800ffc8: bf00 nop + 80117c4: bf00 nop } } - 800ffca: bf00 nop - 800ffcc: 3708 adds r7, #8 - 800ffce: 46bd mov sp, r7 - 800ffd0: bd80 pop {r7, pc} + 80117c6: bf00 nop + 80117c8: 3708 adds r7, #8 + 80117ca: 46bd mov sp, r7 + 80117cc: bd80 pop {r7, pc} -0800ffd2 : +080117ce : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { - 800ffd2: b580 push {r7, lr} - 800ffd4: b084 sub sp, #16 - 800ffd6: af00 add r7, sp, #0 - 800ffd8: 6078 str r0, [r7, #4] - 800ffda: 6039 str r1, [r7, #0] + 80117ce: b580 push {r7, lr} + 80117d0: b084 sub sp, #16 + 80117d2: af00 add r7, sp, #0 + 80117d4: 6078 str r0, [r7, #4] + 80117d6: 6039 str r1, [r7, #0] uint8_t *pbuff = pdata; - 800ffdc: 683b ldr r3, [r7, #0] - 800ffde: 60fb str r3, [r7, #12] + 80117d8: 683b ldr r3, [r7, #0] + 80117da: 60fb str r3, [r7, #12] req->bmRequest = *(uint8_t *)(pbuff); - 800ffe0: 68fb ldr r3, [r7, #12] - 800ffe2: 781a ldrb r2, [r3, #0] - 800ffe4: 687b ldr r3, [r7, #4] - 800ffe6: 701a strb r2, [r3, #0] + 80117dc: 68fb ldr r3, [r7, #12] + 80117de: 781a ldrb r2, [r3, #0] + 80117e0: 687b ldr r3, [r7, #4] + 80117e2: 701a strb r2, [r3, #0] pbuff++; - 800ffe8: 68fb ldr r3, [r7, #12] - 800ffea: 3301 adds r3, #1 - 800ffec: 60fb str r3, [r7, #12] + 80117e4: 68fb ldr r3, [r7, #12] + 80117e6: 3301 adds r3, #1 + 80117e8: 60fb str r3, [r7, #12] req->bRequest = *(uint8_t *)(pbuff); - 800ffee: 68fb ldr r3, [r7, #12] - 800fff0: 781a ldrb r2, [r3, #0] - 800fff2: 687b ldr r3, [r7, #4] - 800fff4: 705a strb r2, [r3, #1] + 80117ea: 68fb ldr r3, [r7, #12] + 80117ec: 781a ldrb r2, [r3, #0] + 80117ee: 687b ldr r3, [r7, #4] + 80117f0: 705a strb r2, [r3, #1] pbuff++; - 800fff6: 68fb ldr r3, [r7, #12] - 800fff8: 3301 adds r3, #1 - 800fffa: 60fb str r3, [r7, #12] + 80117f2: 68fb ldr r3, [r7, #12] + 80117f4: 3301 adds r3, #1 + 80117f6: 60fb str r3, [r7, #12] req->wValue = SWAPBYTE(pbuff); - 800fffc: 68f8 ldr r0, [r7, #12] - 800fffe: f7ff fa17 bl 800f430 - 8010002: 4603 mov r3, r0 - 8010004: 461a mov r2, r3 - 8010006: 687b ldr r3, [r7, #4] - 8010008: 805a strh r2, [r3, #2] + 80117f8: 68f8 ldr r0, [r7, #12] + 80117fa: f7ff fa17 bl 8010c2c + 80117fe: 4603 mov r3, r0 + 8011800: 461a mov r2, r3 + 8011802: 687b ldr r3, [r7, #4] + 8011804: 805a strh r2, [r3, #2] pbuff++; - 801000a: 68fb ldr r3, [r7, #12] - 801000c: 3301 adds r3, #1 - 801000e: 60fb str r3, [r7, #12] + 8011806: 68fb ldr r3, [r7, #12] + 8011808: 3301 adds r3, #1 + 801180a: 60fb str r3, [r7, #12] pbuff++; - 8010010: 68fb ldr r3, [r7, #12] - 8010012: 3301 adds r3, #1 - 8010014: 60fb str r3, [r7, #12] + 801180c: 68fb ldr r3, [r7, #12] + 801180e: 3301 adds r3, #1 + 8011810: 60fb str r3, [r7, #12] req->wIndex = SWAPBYTE(pbuff); - 8010016: 68f8 ldr r0, [r7, #12] - 8010018: f7ff fa0a bl 800f430 - 801001c: 4603 mov r3, r0 - 801001e: 461a mov r2, r3 - 8010020: 687b ldr r3, [r7, #4] - 8010022: 809a strh r2, [r3, #4] + 8011812: 68f8 ldr r0, [r7, #12] + 8011814: f7ff fa0a bl 8010c2c + 8011818: 4603 mov r3, r0 + 801181a: 461a mov r2, r3 + 801181c: 687b ldr r3, [r7, #4] + 801181e: 809a strh r2, [r3, #4] pbuff++; - 8010024: 68fb ldr r3, [r7, #12] - 8010026: 3301 adds r3, #1 - 8010028: 60fb str r3, [r7, #12] + 8011820: 68fb ldr r3, [r7, #12] + 8011822: 3301 adds r3, #1 + 8011824: 60fb str r3, [r7, #12] pbuff++; - 801002a: 68fb ldr r3, [r7, #12] - 801002c: 3301 adds r3, #1 - 801002e: 60fb str r3, [r7, #12] + 8011826: 68fb ldr r3, [r7, #12] + 8011828: 3301 adds r3, #1 + 801182a: 60fb str r3, [r7, #12] req->wLength = SWAPBYTE(pbuff); - 8010030: 68f8 ldr r0, [r7, #12] - 8010032: f7ff f9fd bl 800f430 - 8010036: 4603 mov r3, r0 - 8010038: 461a mov r2, r3 - 801003a: 687b ldr r3, [r7, #4] - 801003c: 80da strh r2, [r3, #6] -} - 801003e: bf00 nop - 8010040: 3710 adds r7, #16 - 8010042: 46bd mov sp, r7 - 8010044: bd80 pop {r7, pc} - -08010046 : + 801182c: 68f8 ldr r0, [r7, #12] + 801182e: f7ff f9fd bl 8010c2c + 8011832: 4603 mov r3, r0 + 8011834: 461a mov r2, r3 + 8011836: 687b ldr r3, [r7, #4] + 8011838: 80da strh r2, [r3, #6] +} + 801183a: bf00 nop + 801183c: 3710 adds r7, #16 + 801183e: 46bd mov sp, r7 + 8011840: bd80 pop {r7, pc} + +08011842 : * @param pdev: device instance * @param req: usb request * @retval None */ void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - 8010046: b580 push {r7, lr} - 8010048: b082 sub sp, #8 - 801004a: af00 add r7, sp, #0 - 801004c: 6078 str r0, [r7, #4] - 801004e: 6039 str r1, [r7, #0] + 8011842: b580 push {r7, lr} + 8011844: b082 sub sp, #8 + 8011846: af00 add r7, sp, #0 + 8011848: 6078 str r0, [r7, #4] + 801184a: 6039 str r1, [r7, #0] UNUSED(req); (void)USBD_LL_StallEP(pdev, 0x80U); - 8010050: 2180 movs r1, #128 ; 0x80 - 8010052: 6878 ldr r0, [r7, #4] - 8010054: f000 fbda bl 801080c + 801184c: 2180 movs r1, #128 ; 0x80 + 801184e: 6878 ldr r0, [r7, #4] + 8011850: f001 fa1c bl 8012c8c (void)USBD_LL_StallEP(pdev, 0U); - 8010058: 2100 movs r1, #0 - 801005a: 6878 ldr r0, [r7, #4] - 801005c: f000 fbd6 bl 801080c + 8011854: 2100 movs r1, #0 + 8011856: 6878 ldr r0, [r7, #4] + 8011858: f001 fa18 bl 8012c8c } - 8010060: bf00 nop - 8010062: 3708 adds r7, #8 - 8010064: 46bd mov sp, r7 - 8010066: bd80 pop {r7, pc} + 801185c: bf00 nop + 801185e: 3708 adds r7, #8 + 8011860: 46bd mov sp, r7 + 8011862: bd80 pop {r7, pc} -08010068 : +08011864 : * @param unicode : Formatted string buffer (unicode) * @param len : descriptor length * @retval None */ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { - 8010068: b580 push {r7, lr} - 801006a: b086 sub sp, #24 - 801006c: af00 add r7, sp, #0 - 801006e: 60f8 str r0, [r7, #12] - 8010070: 60b9 str r1, [r7, #8] - 8010072: 607a str r2, [r7, #4] + 8011864: b580 push {r7, lr} + 8011866: b086 sub sp, #24 + 8011868: af00 add r7, sp, #0 + 801186a: 60f8 str r0, [r7, #12] + 801186c: 60b9 str r1, [r7, #8] + 801186e: 607a str r2, [r7, #4] uint8_t idx = 0U; - 8010074: 2300 movs r3, #0 - 8010076: 75fb strb r3, [r7, #23] + 8011870: 2300 movs r3, #0 + 8011872: 75fb strb r3, [r7, #23] uint8_t *pdesc; if (desc == NULL) - 8010078: 68fb ldr r3, [r7, #12] - 801007a: 2b00 cmp r3, #0 - 801007c: d036 beq.n 80100ec + 8011874: 68fb ldr r3, [r7, #12] + 8011876: 2b00 cmp r3, #0 + 8011878: d036 beq.n 80118e8 { return; } pdesc = desc; - 801007e: 68fb ldr r3, [r7, #12] - 8010080: 613b str r3, [r7, #16] + 801187a: 68fb ldr r3, [r7, #12] + 801187c: 613b str r3, [r7, #16] *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; - 8010082: 6938 ldr r0, [r7, #16] - 8010084: f000 f836 bl 80100f4 - 8010088: 4603 mov r3, r0 - 801008a: 3301 adds r3, #1 - 801008c: b29b uxth r3, r3 - 801008e: 005b lsls r3, r3, #1 - 8010090: b29a uxth r2, r3 - 8010092: 687b ldr r3, [r7, #4] - 8010094: 801a strh r2, [r3, #0] + 801187e: 6938 ldr r0, [r7, #16] + 8011880: f000 f836 bl 80118f0 + 8011884: 4603 mov r3, r0 + 8011886: 3301 adds r3, #1 + 8011888: b29b uxth r3, r3 + 801188a: 005b lsls r3, r3, #1 + 801188c: b29a uxth r2, r3 + 801188e: 687b ldr r3, [r7, #4] + 8011890: 801a strh r2, [r3, #0] unicode[idx] = *(uint8_t *)len; - 8010096: 7dfb ldrb r3, [r7, #23] - 8010098: 68ba ldr r2, [r7, #8] - 801009a: 4413 add r3, r2 - 801009c: 687a ldr r2, [r7, #4] - 801009e: 7812 ldrb r2, [r2, #0] - 80100a0: 701a strb r2, [r3, #0] + 8011892: 7dfb ldrb r3, [r7, #23] + 8011894: 68ba ldr r2, [r7, #8] + 8011896: 4413 add r3, r2 + 8011898: 687a ldr r2, [r7, #4] + 801189a: 7812 ldrb r2, [r2, #0] + 801189c: 701a strb r2, [r3, #0] idx++; - 80100a2: 7dfb ldrb r3, [r7, #23] - 80100a4: 3301 adds r3, #1 - 80100a6: 75fb strb r3, [r7, #23] + 801189e: 7dfb ldrb r3, [r7, #23] + 80118a0: 3301 adds r3, #1 + 80118a2: 75fb strb r3, [r7, #23] unicode[idx] = USB_DESC_TYPE_STRING; - 80100a8: 7dfb ldrb r3, [r7, #23] - 80100aa: 68ba ldr r2, [r7, #8] - 80100ac: 4413 add r3, r2 - 80100ae: 2203 movs r2, #3 - 80100b0: 701a strb r2, [r3, #0] + 80118a4: 7dfb ldrb r3, [r7, #23] + 80118a6: 68ba ldr r2, [r7, #8] + 80118a8: 4413 add r3, r2 + 80118aa: 2203 movs r2, #3 + 80118ac: 701a strb r2, [r3, #0] idx++; - 80100b2: 7dfb ldrb r3, [r7, #23] - 80100b4: 3301 adds r3, #1 - 80100b6: 75fb strb r3, [r7, #23] + 80118ae: 7dfb ldrb r3, [r7, #23] + 80118b0: 3301 adds r3, #1 + 80118b2: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') - 80100b8: e013 b.n 80100e2 + 80118b4: e013 b.n 80118de { unicode[idx] = *pdesc; - 80100ba: 7dfb ldrb r3, [r7, #23] - 80100bc: 68ba ldr r2, [r7, #8] - 80100be: 4413 add r3, r2 - 80100c0: 693a ldr r2, [r7, #16] - 80100c2: 7812 ldrb r2, [r2, #0] - 80100c4: 701a strb r2, [r3, #0] + 80118b6: 7dfb ldrb r3, [r7, #23] + 80118b8: 68ba ldr r2, [r7, #8] + 80118ba: 4413 add r3, r2 + 80118bc: 693a ldr r2, [r7, #16] + 80118be: 7812 ldrb r2, [r2, #0] + 80118c0: 701a strb r2, [r3, #0] pdesc++; - 80100c6: 693b ldr r3, [r7, #16] - 80100c8: 3301 adds r3, #1 - 80100ca: 613b str r3, [r7, #16] + 80118c2: 693b ldr r3, [r7, #16] + 80118c4: 3301 adds r3, #1 + 80118c6: 613b str r3, [r7, #16] idx++; - 80100cc: 7dfb ldrb r3, [r7, #23] - 80100ce: 3301 adds r3, #1 - 80100d0: 75fb strb r3, [r7, #23] + 80118c8: 7dfb ldrb r3, [r7, #23] + 80118ca: 3301 adds r3, #1 + 80118cc: 75fb strb r3, [r7, #23] unicode[idx] = 0U; - 80100d2: 7dfb ldrb r3, [r7, #23] - 80100d4: 68ba ldr r2, [r7, #8] - 80100d6: 4413 add r3, r2 - 80100d8: 2200 movs r2, #0 - 80100da: 701a strb r2, [r3, #0] + 80118ce: 7dfb ldrb r3, [r7, #23] + 80118d0: 68ba ldr r2, [r7, #8] + 80118d2: 4413 add r3, r2 + 80118d4: 2200 movs r2, #0 + 80118d6: 701a strb r2, [r3, #0] idx++; - 80100dc: 7dfb ldrb r3, [r7, #23] - 80100de: 3301 adds r3, #1 - 80100e0: 75fb strb r3, [r7, #23] + 80118d8: 7dfb ldrb r3, [r7, #23] + 80118da: 3301 adds r3, #1 + 80118dc: 75fb strb r3, [r7, #23] while (*pdesc != (uint8_t)'\0') - 80100e2: 693b ldr r3, [r7, #16] - 80100e4: 781b ldrb r3, [r3, #0] - 80100e6: 2b00 cmp r3, #0 - 80100e8: d1e7 bne.n 80100ba - 80100ea: e000 b.n 80100ee + 80118de: 693b ldr r3, [r7, #16] + 80118e0: 781b ldrb r3, [r3, #0] + 80118e2: 2b00 cmp r3, #0 + 80118e4: d1e7 bne.n 80118b6 + 80118e6: e000 b.n 80118ea return; - 80100ec: bf00 nop + 80118e8: bf00 nop } } - 80100ee: 3718 adds r7, #24 - 80100f0: 46bd mov sp, r7 - 80100f2: bd80 pop {r7, pc} + 80118ea: 3718 adds r7, #24 + 80118ec: 46bd mov sp, r7 + 80118ee: bd80 pop {r7, pc} -080100f4 : +080118f0 : * return the string length * @param buf : pointer to the ascii string buffer * @retval string length */ static uint8_t USBD_GetLen(uint8_t *buf) { - 80100f4: b480 push {r7} - 80100f6: b085 sub sp, #20 - 80100f8: af00 add r7, sp, #0 - 80100fa: 6078 str r0, [r7, #4] + 80118f0: b480 push {r7} + 80118f2: b085 sub sp, #20 + 80118f4: af00 add r7, sp, #0 + 80118f6: 6078 str r0, [r7, #4] uint8_t len = 0U; - 80100fc: 2300 movs r3, #0 - 80100fe: 73fb strb r3, [r7, #15] + 80118f8: 2300 movs r3, #0 + 80118fa: 73fb strb r3, [r7, #15] uint8_t *pbuff = buf; - 8010100: 687b ldr r3, [r7, #4] - 8010102: 60bb str r3, [r7, #8] + 80118fc: 687b ldr r3, [r7, #4] + 80118fe: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') - 8010104: e005 b.n 8010112 + 8011900: e005 b.n 801190e { len++; - 8010106: 7bfb ldrb r3, [r7, #15] - 8010108: 3301 adds r3, #1 - 801010a: 73fb strb r3, [r7, #15] + 8011902: 7bfb ldrb r3, [r7, #15] + 8011904: 3301 adds r3, #1 + 8011906: 73fb strb r3, [r7, #15] pbuff++; - 801010c: 68bb ldr r3, [r7, #8] - 801010e: 3301 adds r3, #1 - 8010110: 60bb str r3, [r7, #8] + 8011908: 68bb ldr r3, [r7, #8] + 801190a: 3301 adds r3, #1 + 801190c: 60bb str r3, [r7, #8] while (*pbuff != (uint8_t)'\0') - 8010112: 68bb ldr r3, [r7, #8] - 8010114: 781b ldrb r3, [r3, #0] - 8010116: 2b00 cmp r3, #0 - 8010118: d1f5 bne.n 8010106 + 801190e: 68bb ldr r3, [r7, #8] + 8011910: 781b ldrb r3, [r3, #0] + 8011912: 2b00 cmp r3, #0 + 8011914: d1f5 bne.n 8011902 } return len; - 801011a: 7bfb ldrb r3, [r7, #15] + 8011916: 7bfb ldrb r3, [r7, #15] } - 801011c: 4618 mov r0, r3 - 801011e: 3714 adds r7, #20 - 8010120: 46bd mov sp, r7 - 8010122: f85d 7b04 ldr.w r7, [sp], #4 - 8010126: 4770 bx lr + 8011918: 4618 mov r0, r3 + 801191a: 3714 adds r7, #20 + 801191c: 46bd mov sp, r7 + 801191e: f85d 7b04 ldr.w r7, [sp], #4 + 8011922: 4770 bx lr -08010128 : +08011924 : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { - 8010128: b580 push {r7, lr} - 801012a: b084 sub sp, #16 - 801012c: af00 add r7, sp, #0 - 801012e: 60f8 str r0, [r7, #12] - 8010130: 60b9 str r1, [r7, #8] - 8010132: 607a str r2, [r7, #4] + 8011924: b580 push {r7, lr} + 8011926: b084 sub sp, #16 + 8011928: af00 add r7, sp, #0 + 801192a: 60f8 str r0, [r7, #12] + 801192c: 60b9 str r1, [r7, #8] + 801192e: 607a str r2, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; - 8010134: 68fb ldr r3, [r7, #12] - 8010136: 2202 movs r2, #2 - 8010138: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + 8011930: 68fb ldr r3, [r7, #12] + 8011932: 2202 movs r2, #2 + 8011934: f8c3 2294 str.w r2, [r3, #660] ; 0x294 pdev->ep_in[0].total_length = len; - 801013c: 68fb ldr r3, [r7, #12] - 801013e: 687a ldr r2, [r7, #4] - 8010140: 619a str r2, [r3, #24] + 8011938: 68fb ldr r3, [r7, #12] + 801193a: 687a ldr r2, [r7, #4] + 801193c: 619a str r2, [r3, #24] #ifdef USBD_AVOID_PACKET_SPLIT_MPS pdev->ep_in[0].rem_length = 0U; #else pdev->ep_in[0].rem_length = len; - 8010142: 68fb ldr r3, [r7, #12] - 8010144: 687a ldr r2, [r7, #4] - 8010146: 61da str r2, [r3, #28] + 801193e: 68fb ldr r3, [r7, #12] + 8011940: 687a ldr r2, [r7, #4] + 8011942: 61da str r2, [r3, #28] #endif /* USBD_AVOID_PACKET_SPLIT_MPS */ /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); - 8010148: 687b ldr r3, [r7, #4] - 801014a: 68ba ldr r2, [r7, #8] - 801014c: 2100 movs r1, #0 - 801014e: 68f8 ldr r0, [r7, #12] - 8010150: f000 fc2c bl 80109ac + 8011944: 687b ldr r3, [r7, #4] + 8011946: 68ba ldr r2, [r7, #8] + 8011948: 2100 movs r1, #0 + 801194a: 68f8 ldr r0, [r7, #12] + 801194c: f001 fa6e bl 8012e2c return USBD_OK; - 8010154: 2300 movs r3, #0 + 8011950: 2300 movs r3, #0 } - 8010156: 4618 mov r0, r3 - 8010158: 3710 adds r7, #16 - 801015a: 46bd mov sp, r7 - 801015c: bd80 pop {r7, pc} + 8011952: 4618 mov r0, r3 + 8011954: 3710 adds r7, #16 + 8011956: 46bd mov sp, r7 + 8011958: bd80 pop {r7, pc} -0801015e : +0801195a : * @param len: length of data to be sent * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { - 801015e: b580 push {r7, lr} - 8010160: b084 sub sp, #16 - 8010162: af00 add r7, sp, #0 - 8010164: 60f8 str r0, [r7, #12] - 8010166: 60b9 str r1, [r7, #8] - 8010168: 607a str r2, [r7, #4] + 801195a: b580 push {r7, lr} + 801195c: b084 sub sp, #16 + 801195e: af00 add r7, sp, #0 + 8011960: 60f8 str r0, [r7, #12] + 8011962: 60b9 str r1, [r7, #8] + 8011964: 607a str r2, [r7, #4] /* Start the next transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); - 801016a: 687b ldr r3, [r7, #4] - 801016c: 68ba ldr r2, [r7, #8] - 801016e: 2100 movs r1, #0 - 8010170: 68f8 ldr r0, [r7, #12] - 8010172: f000 fc1b bl 80109ac + 8011966: 687b ldr r3, [r7, #4] + 8011968: 68ba ldr r2, [r7, #8] + 801196a: 2100 movs r1, #0 + 801196c: 68f8 ldr r0, [r7, #12] + 801196e: f001 fa5d bl 8012e2c + + return USBD_OK; + 8011972: 2300 movs r3, #0 +} + 8011974: 4618 mov r0, r3 + 8011976: 3710 adds r7, #16 + 8011978: 46bd mov sp, r7 + 801197a: bd80 pop {r7, pc} + +0801197c : + * @param len: length of data to be received + * @retval status + */ +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len) +{ + 801197c: b580 push {r7, lr} + 801197e: b084 sub sp, #16 + 8011980: af00 add r7, sp, #0 + 8011982: 60f8 str r0, [r7, #12] + 8011984: 60b9 str r1, [r7, #8] + 8011986: 607a str r2, [r7, #4] + /* Set EP0 State */ + pdev->ep0_state = USBD_EP0_DATA_OUT; + 8011988: 68fb ldr r3, [r7, #12] + 801198a: 2203 movs r2, #3 + 801198c: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + pdev->ep_out[0].total_length = len; + 8011990: 68fb ldr r3, [r7, #12] + 8011992: 687a ldr r2, [r7, #4] + 8011994: f8c3 2158 str.w r2, [r3, #344] ; 0x158 + +#ifdef USBD_AVOID_PACKET_SPLIT_MPS + pdev->ep_out[0].rem_length = 0U; +#else + pdev->ep_out[0].rem_length = len; + 8011998: 68fb ldr r3, [r7, #12] + 801199a: 687a ldr r2, [r7, #4] + 801199c: f8c3 215c str.w r2, [r3, #348] ; 0x15c +#endif /* USBD_AVOID_PACKET_SPLIT_MPS */ + + /* Start the transfer */ + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + 80119a0: 687b ldr r3, [r7, #4] + 80119a2: 68ba ldr r2, [r7, #8] + 80119a4: 2100 movs r1, #0 + 80119a6: 68f8 ldr r0, [r7, #12] + 80119a8: f001 fa78 bl 8012e9c return USBD_OK; - 8010176: 2300 movs r3, #0 + 80119ac: 2300 movs r3, #0 } - 8010178: 4618 mov r0, r3 - 801017a: 3710 adds r7, #16 - 801017c: 46bd mov sp, r7 - 801017e: bd80 pop {r7, pc} + 80119ae: 4618 mov r0, r3 + 80119b0: 3710 adds r7, #16 + 80119b2: 46bd mov sp, r7 + 80119b4: bd80 pop {r7, pc} -08010180 : +080119b6 : * @param len: length of data to be received * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { - 8010180: b580 push {r7, lr} - 8010182: b084 sub sp, #16 - 8010184: af00 add r7, sp, #0 - 8010186: 60f8 str r0, [r7, #12] - 8010188: 60b9 str r1, [r7, #8] - 801018a: 607a str r2, [r7, #4] + 80119b6: b580 push {r7, lr} + 80119b8: b084 sub sp, #16 + 80119ba: af00 add r7, sp, #0 + 80119bc: 60f8 str r0, [r7, #12] + 80119be: 60b9 str r1, [r7, #8] + 80119c0: 607a str r2, [r7, #4] (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); - 801018c: 687b ldr r3, [r7, #4] - 801018e: 68ba ldr r2, [r7, #8] - 8010190: 2100 movs r1, #0 - 8010192: 68f8 ldr r0, [r7, #12] - 8010194: f000 fc42 bl 8010a1c + 80119c2: 687b ldr r3, [r7, #4] + 80119c4: 68ba ldr r2, [r7, #8] + 80119c6: 2100 movs r1, #0 + 80119c8: 68f8 ldr r0, [r7, #12] + 80119ca: f001 fa67 bl 8012e9c return USBD_OK; - 8010198: 2300 movs r3, #0 + 80119ce: 2300 movs r3, #0 } - 801019a: 4618 mov r0, r3 - 801019c: 3710 adds r7, #16 - 801019e: 46bd mov sp, r7 - 80101a0: bd80 pop {r7, pc} + 80119d0: 4618 mov r0, r3 + 80119d2: 3710 adds r7, #16 + 80119d4: 46bd mov sp, r7 + 80119d6: bd80 pop {r7, pc} -080101a2 : +080119d8 : * send zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) { - 80101a2: b580 push {r7, lr} - 80101a4: b082 sub sp, #8 - 80101a6: af00 add r7, sp, #0 - 80101a8: 6078 str r0, [r7, #4] + 80119d8: b580 push {r7, lr} + 80119da: b082 sub sp, #8 + 80119dc: af00 add r7, sp, #0 + 80119de: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_IN; - 80101aa: 687b ldr r3, [r7, #4] - 80101ac: 2204 movs r2, #4 - 80101ae: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + 80119e0: 687b ldr r3, [r7, #4] + 80119e2: 2204 movs r2, #4 + 80119e4: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); - 80101b2: 2300 movs r3, #0 - 80101b4: 2200 movs r2, #0 - 80101b6: 2100 movs r1, #0 - 80101b8: 6878 ldr r0, [r7, #4] - 80101ba: f000 fbf7 bl 80109ac + 80119e8: 2300 movs r3, #0 + 80119ea: 2200 movs r2, #0 + 80119ec: 2100 movs r1, #0 + 80119ee: 6878 ldr r0, [r7, #4] + 80119f0: f001 fa1c bl 8012e2c return USBD_OK; - 80101be: 2300 movs r3, #0 + 80119f4: 2300 movs r3, #0 } - 80101c0: 4618 mov r0, r3 - 80101c2: 3708 adds r7, #8 - 80101c4: 46bd mov sp, r7 - 80101c6: bd80 pop {r7, pc} + 80119f6: 4618 mov r0, r3 + 80119f8: 3708 adds r7, #8 + 80119fa: 46bd mov sp, r7 + 80119fc: bd80 pop {r7, pc} -080101c8 : +080119fe : * receive zero lzngth packet on the ctl pipe * @param pdev: device instance * @retval status */ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) { - 80101c8: b580 push {r7, lr} - 80101ca: b082 sub sp, #8 - 80101cc: af00 add r7, sp, #0 - 80101ce: 6078 str r0, [r7, #4] + 80119fe: b580 push {r7, lr} + 8011a00: b082 sub sp, #8 + 8011a02: af00 add r7, sp, #0 + 8011a04: 6078 str r0, [r7, #4] /* Set EP0 State */ pdev->ep0_state = USBD_EP0_STATUS_OUT; - 80101d0: 687b ldr r3, [r7, #4] - 80101d2: 2205 movs r2, #5 - 80101d4: f8c3 2294 str.w r2, [r3, #660] ; 0x294 + 8011a06: 687b ldr r3, [r7, #4] + 8011a08: 2205 movs r2, #5 + 8011a0a: f8c3 2294 str.w r2, [r3, #660] ; 0x294 /* Start the transfer */ (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); - 80101d8: 2300 movs r3, #0 - 80101da: 2200 movs r2, #0 - 80101dc: 2100 movs r1, #0 - 80101de: 6878 ldr r0, [r7, #4] - 80101e0: f000 fc1c bl 8010a1c + 8011a0e: 2300 movs r3, #0 + 8011a10: 2200 movs r2, #0 + 8011a12: 2100 movs r1, #0 + 8011a14: 6878 ldr r0, [r7, #4] + 8011a16: f001 fa41 bl 8012e9c return USBD_OK; - 80101e4: 2300 movs r3, #0 + 8011a1a: 2300 movs r3, #0 +} + 8011a1c: 4618 mov r0, r3 + 8011a1e: 3708 adds r7, #8 + 8011a20: 46bd mov sp, r7 + 8011a22: bd80 pop {r7, pc} + +08011a24 : +bool SPIF_ReadFn(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size); + +/***********************************************************************************************************/ + +void SPIF_Delay(uint32_t Delay) +{ + 8011a24: b580 push {r7, lr} + 8011a26: b082 sub sp, #8 + 8011a28: af00 add r7, sp, #0 + 8011a2a: 6078 str r0, [r7, #4] +#if SPIF_RTOS == SPIF_RTOS_DISABLE + HAL_Delay(Delay); + 8011a2c: 6878 ldr r0, [r7, #4] + 8011a2e: f7f3 fc1b bl 8005268 + uint32_t d = (TX_TIMER_TICKS_PER_SECOND * Delay) / 1000; + if (d == 0) + d = 1; + tx_thread_sleep(d); +#endif +} + 8011a32: bf00 nop + 8011a34: 3708 adds r7, #8 + 8011a36: 46bd mov sp, r7 + 8011a38: bd80 pop {r7, pc} + +08011a3a : + +/***********************************************************************************************************/ + +void SPIF_Lock(SPIF_HandleTypeDef *Handle) +{ + 8011a3a: b580 push {r7, lr} + 8011a3c: b082 sub sp, #8 + 8011a3e: af00 add r7, sp, #0 + 8011a40: 6078 str r0, [r7, #4] + while (Handle->Lock) + 8011a42: e002 b.n 8011a4a + { + SPIF_Delay(1); + 8011a44: 2001 movs r0, #1 + 8011a46: f7ff ffed bl 8011a24 + while (Handle->Lock) + 8011a4a: 687b ldr r3, [r7, #4] + 8011a4c: 7b1b ldrb r3, [r3, #12] + 8011a4e: 2b00 cmp r3, #0 + 8011a50: d1f8 bne.n 8011a44 + } + Handle->Lock = 1; + 8011a52: 687b ldr r3, [r7, #4] + 8011a54: 2201 movs r2, #1 + 8011a56: 731a strb r2, [r3, #12] +} + 8011a58: bf00 nop + 8011a5a: 3708 adds r7, #8 + 8011a5c: 46bd mov sp, r7 + 8011a5e: bd80 pop {r7, pc} + +08011a60 : + +/***********************************************************************************************************/ + +void SPIF_UnLock(SPIF_HandleTypeDef *Handle) +{ + 8011a60: b480 push {r7} + 8011a62: b083 sub sp, #12 + 8011a64: af00 add r7, sp, #0 + 8011a66: 6078 str r0, [r7, #4] + Handle->Lock = 0; + 8011a68: 687b ldr r3, [r7, #4] + 8011a6a: 2200 movs r2, #0 + 8011a6c: 731a strb r2, [r3, #12] +} + 8011a6e: bf00 nop + 8011a70: 370c adds r7, #12 + 8011a72: 46bd mov sp, r7 + 8011a74: f85d 7b04 ldr.w r7, [sp], #4 + 8011a78: 4770 bx lr + +08011a7a : + +/***********************************************************************************************************/ + +void SPIF_CsPin(SPIF_HandleTypeDef *Handle, bool Select) +{ + 8011a7a: b580 push {r7, lr} + 8011a7c: b084 sub sp, #16 + 8011a7e: af00 add r7, sp, #0 + 8011a80: 6078 str r0, [r7, #4] + 8011a82: 460b mov r3, r1 + 8011a84: 70fb strb r3, [r7, #3] + HAL_GPIO_WritePin(Handle->Gpio, Handle->Pin, (GPIO_PinState)Select); + 8011a86: 687b ldr r3, [r7, #4] + 8011a88: 6858 ldr r0, [r3, #4] + 8011a8a: 687b ldr r3, [r7, #4] + 8011a8c: 691b ldr r3, [r3, #16] + 8011a8e: b29b uxth r3, r3 + 8011a90: 78fa ldrb r2, [r7, #3] + 8011a92: 4619 mov r1, r3 + 8011a94: f7f5 fbaa bl 80071ec + for (int i = 0; i < 10; i++); + 8011a98: 2300 movs r3, #0 + 8011a9a: 60fb str r3, [r7, #12] + 8011a9c: e002 b.n 8011aa4 + 8011a9e: 68fb ldr r3, [r7, #12] + 8011aa0: 3301 adds r3, #1 + 8011aa2: 60fb str r3, [r7, #12] + 8011aa4: 68fb ldr r3, [r7, #12] + 8011aa6: 2b09 cmp r3, #9 + 8011aa8: ddf9 ble.n 8011a9e +} + 8011aaa: bf00 nop + 8011aac: bf00 nop + 8011aae: 3710 adds r7, #16 + 8011ab0: 46bd mov sp, r7 + 8011ab2: bd80 pop {r7, pc} + +08011ab4 : + +/***********************************************************************************************************/ + +bool SPIF_TransmitReceive(SPIF_HandleTypeDef *Handle, uint8_t *Tx, uint8_t *Rx, size_t Size, uint32_t Timeout) +{ + 8011ab4: b580 push {r7, lr} + 8011ab6: b088 sub sp, #32 + 8011ab8: af02 add r7, sp, #8 + 8011aba: 60f8 str r0, [r7, #12] + 8011abc: 60b9 str r1, [r7, #8] + 8011abe: 607a str r2, [r7, #4] + 8011ac0: 603b str r3, [r7, #0] + bool retVal = false; + 8011ac2: 2300 movs r3, #0 + 8011ac4: 75fb strb r3, [r7, #23] +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_TransmitReceive(Handle->HSpi, Tx, Rx, Size, Timeout) == HAL_OK) + 8011ac6: 68fb ldr r3, [r7, #12] + 8011ac8: 6818 ldr r0, [r3, #0] + 8011aca: 683b ldr r3, [r7, #0] + 8011acc: b29a uxth r2, r3 + 8011ace: 6a3b ldr r3, [r7, #32] + 8011ad0: 9300 str r3, [sp, #0] + 8011ad2: 4613 mov r3, r2 + 8011ad4: 687a ldr r2, [r7, #4] + 8011ad6: 68b9 ldr r1, [r7, #8] + 8011ad8: f7f9 fae5 bl 800b0a6 + 8011adc: 4603 mov r3, r0 + 8011ade: 2b00 cmp r3, #0 + 8011ae0: d101 bne.n 8011ae6 + { + retVal = true; + 8011ae2: 2301 movs r3, #1 + 8011ae4: 75fb strb r3, [r7, #23] + break; + } + } + } +#endif + return retVal; + 8011ae6: 7dfb ldrb r3, [r7, #23] +} + 8011ae8: 4618 mov r0, r3 + 8011aea: 3718 adds r7, #24 + 8011aec: 46bd mov sp, r7 + 8011aee: bd80 pop {r7, pc} + +08011af0 : + +/***********************************************************************************************************/ + +bool SPIF_Transmit(SPIF_HandleTypeDef *Handle, uint8_t *Tx, size_t Size, uint32_t Timeout) +{ + 8011af0: b580 push {r7, lr} + 8011af2: b086 sub sp, #24 + 8011af4: af00 add r7, sp, #0 + 8011af6: 60f8 str r0, [r7, #12] + 8011af8: 60b9 str r1, [r7, #8] + 8011afa: 607a str r2, [r7, #4] + 8011afc: 603b str r3, [r7, #0] + bool retVal = false; + 8011afe: 2300 movs r3, #0 + 8011b00: 75fb strb r3, [r7, #23] +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_Transmit(Handle->HSpi, Tx, Size, Timeout) == HAL_OK) + 8011b02: 68fb ldr r3, [r7, #12] + 8011b04: 6818 ldr r0, [r3, #0] + 8011b06: 687b ldr r3, [r7, #4] + 8011b08: b29a uxth r2, r3 + 8011b0a: 683b ldr r3, [r7, #0] + 8011b0c: 68b9 ldr r1, [r7, #8] + 8011b0e: f7f9 f81e bl 800ab4e + 8011b12: 4603 mov r3, r0 + 8011b14: 2b00 cmp r3, #0 + 8011b16: d101 bne.n 8011b1c + { + retVal = true; + 8011b18: 2301 movs r3, #1 + 8011b1a: 75fb strb r3, [r7, #23] + break; + } + } + } +#endif + return retVal; + 8011b1c: 7dfb ldrb r3, [r7, #23] +} + 8011b1e: 4618 mov r0, r3 + 8011b20: 3718 adds r7, #24 + 8011b22: 46bd mov sp, r7 + 8011b24: bd80 pop {r7, pc} + +08011b26 : + +/***********************************************************************************************************/ + +bool SPIF_Receive(SPIF_HandleTypeDef *Handle, uint8_t *Rx, size_t Size, uint32_t Timeout) +{ + 8011b26: b580 push {r7, lr} + 8011b28: b086 sub sp, #24 + 8011b2a: af00 add r7, sp, #0 + 8011b2c: 60f8 str r0, [r7, #12] + 8011b2e: 60b9 str r1, [r7, #8] + 8011b30: 607a str r2, [r7, #4] + 8011b32: 603b str r3, [r7, #0] + bool retVal = false; + 8011b34: 2300 movs r3, #0 + 8011b36: 75fb strb r3, [r7, #23] +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_Receive(Handle->HSpi, Rx, Size, Timeout) == HAL_OK) + 8011b38: 68fb ldr r3, [r7, #12] + 8011b3a: 6818 ldr r0, [r3, #0] + 8011b3c: 687b ldr r3, [r7, #4] + 8011b3e: b29a uxth r2, r3 + 8011b40: 683b ldr r3, [r7, #0] + 8011b42: 68b9 ldr r1, [r7, #8] + 8011b44: f7f9 f978 bl 800ae38 + 8011b48: 4603 mov r3, r0 + 8011b4a: 2b00 cmp r3, #0 + 8011b4c: d101 bne.n 8011b52 + { + retVal = true; + 8011b4e: 2301 movs r3, #1 + 8011b50: 75fb strb r3, [r7, #23] + break; + } + } + } +#endif + return retVal; + 8011b52: 7dfb ldrb r3, [r7, #23] +} + 8011b54: 4618 mov r0, r3 + 8011b56: 3718 adds r7, #24 + 8011b58: 46bd mov sp, r7 + 8011b5a: bd80 pop {r7, pc} + +08011b5c : + +/***********************************************************************************************************/ + +bool SPIF_WriteEnable(SPIF_HandleTypeDef *Handle) +{ + 8011b5c: b580 push {r7, lr} + 8011b5e: b084 sub sp, #16 + 8011b60: af00 add r7, sp, #0 + 8011b62: 6078 str r0, [r7, #4] + bool retVal = true; + 8011b64: 2301 movs r3, #1 + 8011b66: 73fb strb r3, [r7, #15] + uint8_t tx[1] = {SPIF_CMD_WRITEENABLE}; + 8011b68: 2306 movs r3, #6 + 8011b6a: 733b strb r3, [r7, #12] + SPIF_CsPin(Handle, 0); + 8011b6c: 2100 movs r1, #0 + 8011b6e: 6878 ldr r0, [r7, #4] + 8011b70: f7ff ff83 bl 8011a7a + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + 8011b74: f107 010c add.w r1, r7, #12 + 8011b78: 2364 movs r3, #100 ; 0x64 + 8011b7a: 2201 movs r2, #1 + 8011b7c: 6878 ldr r0, [r7, #4] + 8011b7e: f7ff ffb7 bl 8011af0 + 8011b82: 4603 mov r3, r0 + 8011b84: f083 0301 eor.w r3, r3, #1 + 8011b88: b2db uxtb r3, r3 + 8011b8a: 2b00 cmp r3, #0 + 8011b8c: d001 beq.n 8011b92 + { + retVal = false; + 8011b8e: 2300 movs r3, #0 + 8011b90: 73fb strb r3, [r7, #15] + dprintf("SPIF_WriteEnable() Error\r\n"); + } + SPIF_CsPin(Handle, 1); + 8011b92: 2101 movs r1, #1 + 8011b94: 6878 ldr r0, [r7, #4] + 8011b96: f7ff ff70 bl 8011a7a + return retVal; + 8011b9a: 7bfb ldrb r3, [r7, #15] +} + 8011b9c: 4618 mov r0, r3 + 8011b9e: 3710 adds r7, #16 + 8011ba0: 46bd mov sp, r7 + 8011ba2: bd80 pop {r7, pc} + +08011ba4 : + +/***********************************************************************************************************/ + +bool SPIF_WriteDisable(SPIF_HandleTypeDef *Handle) +{ + 8011ba4: b580 push {r7, lr} + 8011ba6: b084 sub sp, #16 + 8011ba8: af00 add r7, sp, #0 + 8011baa: 6078 str r0, [r7, #4] + bool retVal = true; + 8011bac: 2301 movs r3, #1 + 8011bae: 73fb strb r3, [r7, #15] + uint8_t tx[1] = {SPIF_CMD_WRITEDISABLE}; + 8011bb0: 2304 movs r3, #4 + 8011bb2: 733b strb r3, [r7, #12] + SPIF_CsPin(Handle, 0); + 8011bb4: 2100 movs r1, #0 + 8011bb6: 6878 ldr r0, [r7, #4] + 8011bb8: f7ff ff5f bl 8011a7a + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + 8011bbc: f107 010c add.w r1, r7, #12 + 8011bc0: 2364 movs r3, #100 ; 0x64 + 8011bc2: 2201 movs r2, #1 + 8011bc4: 6878 ldr r0, [r7, #4] + 8011bc6: f7ff ff93 bl 8011af0 + 8011bca: 4603 mov r3, r0 + 8011bcc: f083 0301 eor.w r3, r3, #1 + 8011bd0: b2db uxtb r3, r3 + 8011bd2: 2b00 cmp r3, #0 + 8011bd4: d001 beq.n 8011bda + { + retVal = false; + 8011bd6: 2300 movs r3, #0 + 8011bd8: 73fb strb r3, [r7, #15] + dprintf("SPIF_WriteDisable() Error\r\n"); + } + SPIF_CsPin(Handle, 1); + 8011bda: 2101 movs r1, #1 + 8011bdc: 6878 ldr r0, [r7, #4] + 8011bde: f7ff ff4c bl 8011a7a + return retVal; + 8011be2: 7bfb ldrb r3, [r7, #15] +} + 8011be4: 4618 mov r0, r3 + 8011be6: 3710 adds r7, #16 + 8011be8: 46bd mov sp, r7 + 8011bea: bd80 pop {r7, pc} + +08011bec : + +/***********************************************************************************************************/ + +uint8_t SPIF_ReadReg1(SPIF_HandleTypeDef *Handle) +{ + 8011bec: b580 push {r7, lr} + 8011bee: b086 sub sp, #24 + 8011bf0: af02 add r7, sp, #8 + 8011bf2: 6078 str r0, [r7, #4] + uint8_t retVal = 0; + 8011bf4: 2300 movs r3, #0 + 8011bf6: 73fb strb r3, [r7, #15] + uint8_t tx[2] = {SPIF_CMD_READSTATUS1, SPIF_DUMMY_BYTE}; + 8011bf8: f24a 5305 movw r3, #42245 ; 0xa505 + 8011bfc: 81bb strh r3, [r7, #12] + uint8_t rx[2]; + SPIF_CsPin(Handle, 0); + 8011bfe: 2100 movs r1, #0 + 8011c00: 6878 ldr r0, [r7, #4] + 8011c02: f7ff ff3a bl 8011a7a + if (SPIF_TransmitReceive(Handle, tx, rx, 2, 100) == true) + 8011c06: f107 0208 add.w r2, r7, #8 + 8011c0a: f107 010c add.w r1, r7, #12 + 8011c0e: 2364 movs r3, #100 ; 0x64 + 8011c10: 9300 str r3, [sp, #0] + 8011c12: 2302 movs r3, #2 + 8011c14: 6878 ldr r0, [r7, #4] + 8011c16: f7ff ff4d bl 8011ab4 + 8011c1a: 4603 mov r3, r0 + 8011c1c: 2b00 cmp r3, #0 + 8011c1e: d001 beq.n 8011c24 + { + retVal = rx[1]; + 8011c20: 7a7b ldrb r3, [r7, #9] + 8011c22: 73fb strb r3, [r7, #15] + } + SPIF_CsPin(Handle, 1); + 8011c24: 2101 movs r1, #1 + 8011c26: 6878 ldr r0, [r7, #4] + 8011c28: f7ff ff27 bl 8011a7a + return retVal; + 8011c2c: 7bfb ldrb r3, [r7, #15] +} + 8011c2e: 4618 mov r0, r3 + 8011c30: 3710 adds r7, #16 + 8011c32: 46bd mov sp, r7 + 8011c34: bd80 pop {r7, pc} + +08011c36 : +} + +/***********************************************************************************************************/ + +bool SPIF_WaitForWriting(SPIF_HandleTypeDef *Handle, uint32_t Timeout) +{ + 8011c36: b580 push {r7, lr} + 8011c38: b084 sub sp, #16 + 8011c3a: af00 add r7, sp, #0 + 8011c3c: 6078 str r0, [r7, #4] + 8011c3e: 6039 str r1, [r7, #0] + bool retVal = false; + 8011c40: 2300 movs r3, #0 + 8011c42: 73fb strb r3, [r7, #15] + uint32_t startTime = HAL_GetTick(); + 8011c44: f7f3 fb04 bl 8005250 + 8011c48: 60b8 str r0, [r7, #8] + while (1) + { + SPIF_Delay(1); + 8011c4a: 2001 movs r0, #1 + 8011c4c: f7ff feea bl 8011a24 + if (HAL_GetTick() - startTime >= Timeout) + 8011c50: f7f3 fafe bl 8005250 + 8011c54: 4602 mov r2, r0 + 8011c56: 68bb ldr r3, [r7, #8] + 8011c58: 1ad3 subs r3, r2, r3 + 8011c5a: 683a ldr r2, [r7, #0] + 8011c5c: 429a cmp r2, r3 + 8011c5e: d90a bls.n 8011c76 + { + dprintf("SPIF_WaitForWriting() TIMEOUT\r\n"); + break; + } + if ((SPIF_ReadReg1(Handle) & SPIF_STATUS1_BUSY) == 0) + 8011c60: 6878 ldr r0, [r7, #4] + 8011c62: f7ff ffc3 bl 8011bec + 8011c66: 4603 mov r3, r0 + 8011c68: f003 0301 and.w r3, r3, #1 + 8011c6c: 2b00 cmp r3, #0 + 8011c6e: d1ec bne.n 8011c4a + { + retVal = true; + 8011c70: 2301 movs r3, #1 + 8011c72: 73fb strb r3, [r7, #15] + break; + 8011c74: e000 b.n 8011c78 + break; + 8011c76: bf00 nop + } + } + return retVal; + 8011c78: 7bfb ldrb r3, [r7, #15] +} + 8011c7a: 4618 mov r0, r3 + 8011c7c: 3710 adds r7, #16 + 8011c7e: 46bd mov sp, r7 + 8011c80: bd80 pop {r7, pc} + ... + +08011c84 : + +/***********************************************************************************************************/ + +bool SPIF_FindChip(SPIF_HandleTypeDef *Handle) +{ + 8011c84: b580 push {r7, lr} + 8011c86: b088 sub sp, #32 + 8011c88: af02 add r7, sp, #8 + 8011c8a: 6078 str r0, [r7, #4] + uint8_t tx[4] = {SPIF_CMD_JEDECID, 0xFF, 0xFF, 0xFF}; + 8011c8c: f06f 0360 mvn.w r3, #96 ; 0x60 + 8011c90: 613b str r3, [r7, #16] + uint8_t rx[4]; + bool retVal = false; + 8011c92: 2300 movs r3, #0 + 8011c94: 75fb strb r3, [r7, #23] + do + { + dprintf("SPIF_FindChip()\r\n"); + SPIF_CsPin(Handle, 0); + 8011c96: 2100 movs r1, #0 + 8011c98: 6878 ldr r0, [r7, #4] + 8011c9a: f7ff feee bl 8011a7a + if (SPIF_TransmitReceive(Handle, tx, rx, 4, 100) == false) + 8011c9e: f107 020c add.w r2, r7, #12 + 8011ca2: f107 0110 add.w r1, r7, #16 + 8011ca6: 2364 movs r3, #100 ; 0x64 + 8011ca8: 9300 str r3, [sp, #0] + 8011caa: 2304 movs r3, #4 + 8011cac: 6878 ldr r0, [r7, #4] + 8011cae: f7ff ff01 bl 8011ab4 + 8011cb2: 4603 mov r3, r0 + 8011cb4: f083 0301 eor.w r3, r3, #1 + 8011cb8: b2db uxtb r3, r3 + 8011cba: 2b00 cmp r3, #0 + 8011cbc: d004 beq.n 8011cc8 + { + SPIF_CsPin(Handle, 1); + 8011cbe: 2101 movs r1, #1 + 8011cc0: 6878 ldr r0, [r7, #4] + 8011cc2: f7ff feda bl 8011a7a + break; + 8011cc6: e16f b.n 8011fa8 + } + SPIF_CsPin(Handle, 1); + 8011cc8: 2101 movs r1, #1 + 8011cca: 6878 ldr r0, [r7, #4] + 8011ccc: f7ff fed5 bl 8011a7a + dprintf("CHIP ID: 0x%02X%02X%02X\r\n", rx[1], rx[2], rx[3]); + Handle->Manufactor = rx[1]; + 8011cd0: 7b7a ldrb r2, [r7, #13] + 8011cd2: 687b ldr r3, [r7, #4] + 8011cd4: 721a strb r2, [r3, #8] + Handle->MemType = rx[2]; + 8011cd6: 7bba ldrb r2, [r7, #14] + 8011cd8: 687b ldr r3, [r7, #4] + 8011cda: 72da strb r2, [r3, #11] + Handle->Size = rx[3]; + 8011cdc: 7bfa ldrb r2, [r7, #15] + 8011cde: 687b ldr r3, [r7, #4] + 8011ce0: 725a strb r2, [r3, #9] + + dprintf("SPIF MANUFACTURE: "); + switch (Handle->Manufactor) + 8011ce2: 687b ldr r3, [r7, #4] + 8011ce4: 7a1b ldrb r3, [r3, #8] + 8011ce6: 2bef cmp r3, #239 ; 0xef + 8011ce8: f000 80f0 beq.w 8011ecc + 8011cec: 2bef cmp r3, #239 ; 0xef + 8011cee: f300 80e9 bgt.w 8011ec4 + 8011cf2: 2bc8 cmp r3, #200 ; 0xc8 + 8011cf4: f300 80e6 bgt.w 8011ec4 + 8011cf8: 2b85 cmp r3, #133 ; 0x85 + 8011cfa: da0c bge.n 8011d16 + 8011cfc: 2b62 cmp r3, #98 ; 0x62 + 8011cfe: f000 80e7 beq.w 8011ed0 + 8011d02: 2b62 cmp r3, #98 ; 0x62 + 8011d04: f300 80de bgt.w 8011ec4 + 8011d08: 2b20 cmp r3, #32 + 8011d0a: f300 80d9 bgt.w 8011ec0 + 8011d0e: 2b00 cmp r3, #0 + 8011d10: f300 8090 bgt.w 8011e34 + 8011d14: e0d6 b.n 8011ec4 + 8011d16: 3b85 subs r3, #133 ; 0x85 + 8011d18: 2b43 cmp r3, #67 ; 0x43 + 8011d1a: f200 80d3 bhi.w 8011ec4 + 8011d1e: a201 add r2, pc, #4 ; (adr r2, 8011d24 ) + 8011d20: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8011d24: 08011ed5 .word 0x08011ed5 + 8011d28: 08011ec5 .word 0x08011ec5 + 8011d2c: 08011ec5 .word 0x08011ec5 + 8011d30: 08011ec5 .word 0x08011ec5 + 8011d34: 08011ed5 .word 0x08011ed5 + 8011d38: 08011ec5 .word 0x08011ec5 + 8011d3c: 08011ec5 .word 0x08011ec5 + 8011d40: 08011ed5 .word 0x08011ed5 + 8011d44: 08011ec5 .word 0x08011ec5 + 8011d48: 08011ec5 .word 0x08011ec5 + 8011d4c: 08011ec5 .word 0x08011ec5 + 8011d50: 08011ec5 .word 0x08011ec5 + 8011d54: 08011ec5 .word 0x08011ec5 + 8011d58: 08011ec5 .word 0x08011ec5 + 8011d5c: 08011ec5 .word 0x08011ec5 + 8011d60: 08011ec5 .word 0x08011ec5 + 8011d64: 08011ec5 .word 0x08011ec5 + 8011d68: 08011ec5 .word 0x08011ec5 + 8011d6c: 08011ec5 .word 0x08011ec5 + 8011d70: 08011ec5 .word 0x08011ec5 + 8011d74: 08011ec5 .word 0x08011ec5 + 8011d78: 08011ec5 .word 0x08011ec5 + 8011d7c: 08011ec5 .word 0x08011ec5 + 8011d80: 08011ec5 .word 0x08011ec5 + 8011d84: 08011ed5 .word 0x08011ed5 + 8011d88: 08011ec5 .word 0x08011ec5 + 8011d8c: 08011ec5 .word 0x08011ec5 + 8011d90: 08011ec5 .word 0x08011ec5 + 8011d94: 08011ed5 .word 0x08011ed5 + 8011d98: 08011ec5 .word 0x08011ec5 + 8011d9c: 08011ec5 .word 0x08011ec5 + 8011da0: 08011ec5 .word 0x08011ec5 + 8011da4: 08011ec5 .word 0x08011ec5 + 8011da8: 08011ec5 .word 0x08011ec5 + 8011dac: 08011ec5 .word 0x08011ec5 + 8011db0: 08011ec5 .word 0x08011ec5 + 8011db4: 08011ec5 .word 0x08011ec5 + 8011db8: 08011ec5 .word 0x08011ec5 + 8011dbc: 08011ec5 .word 0x08011ec5 + 8011dc0: 08011ec5 .word 0x08011ec5 + 8011dc4: 08011ed5 .word 0x08011ed5 + 8011dc8: 08011ec5 .word 0x08011ec5 + 8011dcc: 08011ec5 .word 0x08011ec5 + 8011dd0: 08011ec5 .word 0x08011ec5 + 8011dd4: 08011ec5 .word 0x08011ec5 + 8011dd8: 08011ec5 .word 0x08011ec5 + 8011ddc: 08011ec5 .word 0x08011ec5 + 8011de0: 08011ec5 .word 0x08011ec5 + 8011de4: 08011ec5 .word 0x08011ec5 + 8011de8: 08011ec5 .word 0x08011ec5 + 8011dec: 08011ec5 .word 0x08011ec5 + 8011df0: 08011ec5 .word 0x08011ec5 + 8011df4: 08011ec5 .word 0x08011ec5 + 8011df8: 08011ec5 .word 0x08011ec5 + 8011dfc: 08011ec5 .word 0x08011ec5 + 8011e00: 08011ec5 .word 0x08011ec5 + 8011e04: 08011ec5 .word 0x08011ec5 + 8011e08: 08011ec5 .word 0x08011ec5 + 8011e0c: 08011ed5 .word 0x08011ed5 + 8011e10: 08011ec5 .word 0x08011ec5 + 8011e14: 08011ec5 .word 0x08011ec5 + 8011e18: 08011ed5 .word 0x08011ed5 + 8011e1c: 08011ec5 .word 0x08011ec5 + 8011e20: 08011ec5 .word 0x08011ec5 + 8011e24: 08011ec5 .word 0x08011ec5 + 8011e28: 08011ec5 .word 0x08011ec5 + 8011e2c: 08011ec5 .word 0x08011ec5 + 8011e30: 08011ed5 .word 0x08011ed5 + 8011e34: 3b01 subs r3, #1 + 8011e36: 2b1f cmp r3, #31 + 8011e38: d844 bhi.n 8011ec4 + 8011e3a: a201 add r2, pc, #4 ; (adr r2, 8011e40 ) + 8011e3c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8011e40: 08011ed9 .word 0x08011ed9 + 8011e44: 08011ec5 .word 0x08011ec5 + 8011e48: 08011ec5 .word 0x08011ec5 + 8011e4c: 08011ed9 .word 0x08011ed9 + 8011e50: 08011ec5 .word 0x08011ec5 + 8011e54: 08011ec5 .word 0x08011ec5 + 8011e58: 08011ec5 .word 0x08011ec5 + 8011e5c: 08011ec5 .word 0x08011ec5 + 8011e60: 08011ec5 .word 0x08011ec5 + 8011e64: 08011ec5 .word 0x08011ec5 + 8011e68: 08011ec5 .word 0x08011ec5 + 8011e6c: 08011ec5 .word 0x08011ec5 + 8011e70: 08011ec5 .word 0x08011ec5 + 8011e74: 08011ec5 .word 0x08011ec5 + 8011e78: 08011ec5 .word 0x08011ec5 + 8011e7c: 08011ec5 .word 0x08011ec5 + 8011e80: 08011ec5 .word 0x08011ec5 + 8011e84: 08011ec5 .word 0x08011ec5 + 8011e88: 08011ec5 .word 0x08011ec5 + 8011e8c: 08011ec5 .word 0x08011ec5 + 8011e90: 08011ec5 .word 0x08011ec5 + 8011e94: 08011ec5 .word 0x08011ec5 + 8011e98: 08011ec5 .word 0x08011ec5 + 8011e9c: 08011ec5 .word 0x08011ec5 + 8011ea0: 08011ec5 .word 0x08011ec5 + 8011ea4: 08011ec5 .word 0x08011ec5 + 8011ea8: 08011ec5 .word 0x08011ec5 + 8011eac: 08011ed9 .word 0x08011ed9 + 8011eb0: 08011ec5 .word 0x08011ec5 + 8011eb4: 08011ec5 .word 0x08011ec5 + 8011eb8: 08011ec5 .word 0x08011ec5 + 8011ebc: 08011ed9 .word 0x08011ed9 + 8011ec0: 2b37 cmp r3, #55 ; 0x37 + 8011ec2: d00b beq.n 8011edc + break; + case SPIF_MANUFACTOR_PUYA: + dprintf("PUYA"); + break; + default: + Handle->Manufactor = SPIF_MANUFACTOR_ERROR; + 8011ec4: 687b ldr r3, [r7, #4] + 8011ec6: 2200 movs r2, #0 + 8011ec8: 721a strb r2, [r3, #8] + dprintf("ERROR"); + break; + 8011eca: e008 b.n 8011ede + break; + 8011ecc: bf00 nop + 8011ece: e006 b.n 8011ede + break; + 8011ed0: bf00 nop + 8011ed2: e004 b.n 8011ede + break; + 8011ed4: bf00 nop + 8011ed6: e002 b.n 8011ede + break; + 8011ed8: bf00 nop + 8011eda: e000 b.n 8011ede + break; + 8011edc: bf00 nop + } + dprintf(" - MEMTYPE: 0x%02X", Handle->MemType); + dprintf(" - SIZE: "); + switch (Handle->Size) + 8011ede: 687b ldr r3, [r7, #4] + 8011ee0: 7a5b ldrb r3, [r3, #9] + 8011ee2: 3b11 subs r3, #17 + 8011ee4: 2b0f cmp r3, #15 + 8011ee6: d84e bhi.n 8011f86 + 8011ee8: a201 add r2, pc, #4 ; (adr r2, 8011ef0 ) + 8011eea: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8011eee: bf00 nop + 8011ef0: 08011f31 .word 0x08011f31 + 8011ef4: 08011f39 .word 0x08011f39 + 8011ef8: 08011f41 .word 0x08011f41 + 8011efc: 08011f49 .word 0x08011f49 + 8011f00: 08011f51 .word 0x08011f51 + 8011f04: 08011f59 .word 0x08011f59 + 8011f08: 08011f61 .word 0x08011f61 + 8011f0c: 08011f69 .word 0x08011f69 + 8011f10: 08011f73 .word 0x08011f73 + 8011f14: 08011f87 .word 0x08011f87 + 8011f18: 08011f87 .word 0x08011f87 + 8011f1c: 08011f87 .word 0x08011f87 + 8011f20: 08011f87 .word 0x08011f87 + 8011f24: 08011f87 .word 0x08011f87 + 8011f28: 08011f87 .word 0x08011f87 + 8011f2c: 08011f7d .word 0x08011f7d + { + case SPIF_SIZE_1MBIT: + Handle->BlockCnt = 2; + 8011f30: 687b ldr r3, [r7, #4] + 8011f32: 2202 movs r2, #2 + 8011f34: 61da str r2, [r3, #28] + dprintf("1 MBIT\r\n"); + break; + 8011f36: e02a b.n 8011f8e + case SPIF_SIZE_2MBIT: + Handle->BlockCnt = 4; + 8011f38: 687b ldr r3, [r7, #4] + 8011f3a: 2204 movs r2, #4 + 8011f3c: 61da str r2, [r3, #28] + dprintf("2 MBIT\r\n"); + break; + 8011f3e: e026 b.n 8011f8e + case SPIF_SIZE_4MBIT: + Handle->BlockCnt = 8; + 8011f40: 687b ldr r3, [r7, #4] + 8011f42: 2208 movs r2, #8 + 8011f44: 61da str r2, [r3, #28] + dprintf("4 MBIT\r\n"); + break; + 8011f46: e022 b.n 8011f8e + case SPIF_SIZE_8MBIT: + Handle->BlockCnt = 16; + 8011f48: 687b ldr r3, [r7, #4] + 8011f4a: 2210 movs r2, #16 + 8011f4c: 61da str r2, [r3, #28] + dprintf("8 MBIT\r\n"); + break; + 8011f4e: e01e b.n 8011f8e + case SPIF_SIZE_16MBIT: + Handle->BlockCnt = 32; + 8011f50: 687b ldr r3, [r7, #4] + 8011f52: 2220 movs r2, #32 + 8011f54: 61da str r2, [r3, #28] + dprintf("16 MBIT\r\n"); + break; + 8011f56: e01a b.n 8011f8e + case SPIF_SIZE_32MBIT: + Handle->BlockCnt = 64; + 8011f58: 687b ldr r3, [r7, #4] + 8011f5a: 2240 movs r2, #64 ; 0x40 + 8011f5c: 61da str r2, [r3, #28] + dprintf("32 MBIT\r\n"); + break; + 8011f5e: e016 b.n 8011f8e + case SPIF_SIZE_64MBIT: + Handle->BlockCnt = 128; + 8011f60: 687b ldr r3, [r7, #4] + 8011f62: 2280 movs r2, #128 ; 0x80 + 8011f64: 61da str r2, [r3, #28] + dprintf("64 MBIT\r\n"); + break; + 8011f66: e012 b.n 8011f8e + case SPIF_SIZE_128MBIT: + Handle->BlockCnt = 256; + 8011f68: 687b ldr r3, [r7, #4] + 8011f6a: f44f 7280 mov.w r2, #256 ; 0x100 + 8011f6e: 61da str r2, [r3, #28] + dprintf("128 MBIT\r\n"); + break; + 8011f70: e00d b.n 8011f8e + case SPIF_SIZE_256MBIT: + Handle->BlockCnt = 512; + 8011f72: 687b ldr r3, [r7, #4] + 8011f74: f44f 7200 mov.w r2, #512 ; 0x200 + 8011f78: 61da str r2, [r3, #28] + dprintf("256 MBIT\r\n"); + break; + 8011f7a: e008 b.n 8011f8e + case SPIF_SIZE_512MBIT: + Handle->BlockCnt = 1024; + 8011f7c: 687b ldr r3, [r7, #4] + 8011f7e: f44f 6280 mov.w r2, #1024 ; 0x400 + 8011f82: 61da str r2, [r3, #28] + dprintf("512 MBIT\r\n"); + break; + 8011f84: e003 b.n 8011f8e + default: + Handle->Size = SPIF_SIZE_ERROR; + 8011f86: 687b ldr r3, [r7, #4] + 8011f88: 2200 movs r2, #0 + 8011f8a: 725a strb r2, [r3, #9] + dprintf("ERROR\r\n"); + break; + 8011f8c: bf00 nop + } + + Handle->SectorCnt = Handle->BlockCnt * 16; + 8011f8e: 687b ldr r3, [r7, #4] + 8011f90: 69db ldr r3, [r3, #28] + 8011f92: 011a lsls r2, r3, #4 + 8011f94: 687b ldr r3, [r7, #4] + 8011f96: 619a str r2, [r3, #24] + Handle->PageCnt = (Handle->SectorCnt * SPIF_SECTOR_SIZE) / SPIF_PAGE_SIZE; + 8011f98: 687b ldr r3, [r7, #4] + 8011f9a: 699b ldr r3, [r3, #24] + 8011f9c: 031b lsls r3, r3, #12 + 8011f9e: 0a1a lsrs r2, r3, #8 + 8011fa0: 687b ldr r3, [r7, #4] + 8011fa2: 615a str r2, [r3, #20] + dprintf("SPIF SECTOR CNT: %ld\r\n", Handle->SectorCnt); + dprintf("SPIF PAGE CNT: %ld\r\n", Handle->PageCnt); + dprintf("SPIF STATUS1: 0x%02X\r\n", SPIF_ReadReg1(Handle)); + dprintf("SPIF STATUS2: 0x%02X\r\n", SPIF_ReadReg2(Handle)); + dprintf("SPIF STATUS3: 0x%02X\r\n", SPIF_ReadReg3(Handle)); + retVal = true; + 8011fa4: 2301 movs r3, #1 + 8011fa6: 75fb strb r3, [r7, #23] + + } while (0); + + return retVal; + 8011fa8: 7dfb ldrb r3, [r7, #23] +} + 8011faa: 4618 mov r0, r3 + 8011fac: 3718 adds r7, #24 + 8011fae: 46bd mov sp, r7 + 8011fb0: bd80 pop {r7, pc} + 8011fb2: bf00 nop + +08011fb4 : + +/***********************************************************************************************************/ + +bool SPIF_WriteFn(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + 8011fb4: b580 push {r7, lr} + 8011fb6: b08a sub sp, #40 ; 0x28 + 8011fb8: af00 add r7, sp, #0 + 8011fba: 60f8 str r0, [r7, #12] + 8011fbc: 60b9 str r1, [r7, #8] + 8011fbe: 607a str r2, [r7, #4] + 8011fc0: 603b str r3, [r7, #0] + bool retVal = false; + 8011fc2: 2300 movs r3, #0 + 8011fc4: f887 3027 strb.w r3, [r7, #39] ; 0x27 + uint32_t address = 0, maximum = SPIF_PAGE_SIZE - Offset; + 8011fc8: 2300 movs r3, #0 + 8011fca: 623b str r3, [r7, #32] + 8011fcc: 6b3b ldr r3, [r7, #48] ; 0x30 + 8011fce: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 8011fd2: 61fb str r3, [r7, #28] + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_WritePage() START PAGE %ld\r\n", PageNumber); + if (PageNumber >= Handle->PageCnt) + 8011fd4: 68fb ldr r3, [r7, #12] + 8011fd6: 695b ldr r3, [r3, #20] + 8011fd8: 68ba ldr r2, [r7, #8] + 8011fda: 429a cmp r2, r3 + 8011fdc: f080 8084 bcs.w 80120e8 + { + dprintf("SPIF_WritePage() ERROR PageNumber\r\n"); + break; + } + if (Offset >= SPIF_PAGE_SIZE) + 8011fe0: 6b3b ldr r3, [r7, #48] ; 0x30 + 8011fe2: 2bff cmp r3, #255 ; 0xff + 8011fe4: f200 8082 bhi.w 80120ec + { + dprintf("SPIF_WritePage() ERROR Offset\r\n"); + break; + } + if (Size > maximum) + 8011fe8: 683a ldr r2, [r7, #0] + 8011fea: 69fb ldr r3, [r7, #28] + 8011fec: 429a cmp r2, r3 + 8011fee: d901 bls.n 8011ff4 + { + Size = maximum; + 8011ff0: 69fb ldr r3, [r7, #28] + 8011ff2: 603b str r3, [r7, #0] + } + address = SPIF_PageToAddress(PageNumber) + Offset; + 8011ff4: 68bb ldr r3, [r7, #8] + 8011ff6: 021b lsls r3, r3, #8 + 8011ff8: 6b3a ldr r2, [r7, #48] ; 0x30 + 8011ffa: 4413 add r3, r2 + 8011ffc: 623b str r3, [r7, #32] + } + dprintf(", 0x%02X", Data[i]); + } + dprintf("\r\n}\r\n"); +#endif + if (SPIF_WriteEnable(Handle) == false) + 8011ffe: 68f8 ldr r0, [r7, #12] + 8012000: f7ff fdac bl 8011b5c + 8012004: 4603 mov r3, r0 + 8012006: f083 0301 eor.w r3, r3, #1 + 801200a: b2db uxtb r3, r3 + 801200c: 2b00 cmp r3, #0 + 801200e: d16f bne.n 80120f0 + { + break; + } + SPIF_CsPin(Handle, 0); + 8012010: 2100 movs r1, #0 + 8012012: 68f8 ldr r0, [r7, #12] + 8012014: f7ff fd31 bl 8011a7a + if (Handle->BlockCnt >= 512) + 8012018: 68fb ldr r3, [r7, #12] + 801201a: 69db ldr r3, [r3, #28] + 801201c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8012020: d322 bcc.n 8012068 + { + tx[0] = SPIF_CMD_PAGEPROG4ADD; + 8012022: 2312 movs r3, #18 + 8012024: 753b strb r3, [r7, #20] + tx[1] = (address & 0xFF000000) >> 24; + 8012026: 6a3b ldr r3, [r7, #32] + 8012028: 0e1b lsrs r3, r3, #24 + 801202a: b2db uxtb r3, r3 + 801202c: 757b strb r3, [r7, #21] + tx[2] = (address & 0x00FF0000) >> 16; + 801202e: 6a3b ldr r3, [r7, #32] + 8012030: 0c1b lsrs r3, r3, #16 + 8012032: b2db uxtb r3, r3 + 8012034: 75bb strb r3, [r7, #22] + tx[3] = (address & 0x0000FF00) >> 8; + 8012036: 6a3b ldr r3, [r7, #32] + 8012038: 0a1b lsrs r3, r3, #8 + 801203a: b2db uxtb r3, r3 + 801203c: 75fb strb r3, [r7, #23] + tx[4] = (address & 0x000000FF); + 801203e: 6a3b ldr r3, [r7, #32] + 8012040: b2db uxtb r3, r3 + 8012042: 763b strb r3, [r7, #24] + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + 8012044: f107 0114 add.w r1, r7, #20 + 8012048: 2364 movs r3, #100 ; 0x64 + 801204a: 2205 movs r2, #5 + 801204c: 68f8 ldr r0, [r7, #12] + 801204e: f7ff fd4f bl 8011af0 + 8012052: 4603 mov r3, r0 + 8012054: f083 0301 eor.w r3, r3, #1 + 8012058: b2db uxtb r3, r3 + 801205a: 2b00 cmp r3, #0 + 801205c: d023 beq.n 80120a6 + { + SPIF_CsPin(Handle, 1); + 801205e: 2101 movs r1, #1 + 8012060: 68f8 ldr r0, [r7, #12] + 8012062: f7ff fd0a bl 8011a7a + break; + 8012066: e044 b.n 80120f2 + } + } + else + { + tx[0] = SPIF_CMD_PAGEPROG3ADD; + 8012068: 2302 movs r3, #2 + 801206a: 753b strb r3, [r7, #20] + tx[1] = (address & 0x00FF0000) >> 16; + 801206c: 6a3b ldr r3, [r7, #32] + 801206e: 0c1b lsrs r3, r3, #16 + 8012070: b2db uxtb r3, r3 + 8012072: 757b strb r3, [r7, #21] + tx[2] = (address & 0x0000FF00) >> 8; + 8012074: 6a3b ldr r3, [r7, #32] + 8012076: 0a1b lsrs r3, r3, #8 + 8012078: b2db uxtb r3, r3 + 801207a: 75bb strb r3, [r7, #22] + tx[3] = (address & 0x000000FF); + 801207c: 6a3b ldr r3, [r7, #32] + 801207e: b2db uxtb r3, r3 + 8012080: 75fb strb r3, [r7, #23] + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + 8012082: f107 0114 add.w r1, r7, #20 + 8012086: 2364 movs r3, #100 ; 0x64 + 8012088: 2204 movs r2, #4 + 801208a: 68f8 ldr r0, [r7, #12] + 801208c: f7ff fd30 bl 8011af0 + 8012090: 4603 mov r3, r0 + 8012092: f083 0301 eor.w r3, r3, #1 + 8012096: b2db uxtb r3, r3 + 8012098: 2b00 cmp r3, #0 + 801209a: d004 beq.n 80120a6 + { + SPIF_CsPin(Handle, 1); + 801209c: 2101 movs r1, #1 + 801209e: 68f8 ldr r0, [r7, #12] + 80120a0: f7ff fceb bl 8011a7a + break; + 80120a4: e025 b.n 80120f2 + } + } + if (SPIF_Transmit(Handle, Data, Size, 1000) == false) + 80120a6: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80120aa: 683a ldr r2, [r7, #0] + 80120ac: 6879 ldr r1, [r7, #4] + 80120ae: 68f8 ldr r0, [r7, #12] + 80120b0: f7ff fd1e bl 8011af0 + 80120b4: 4603 mov r3, r0 + 80120b6: f083 0301 eor.w r3, r3, #1 + 80120ba: b2db uxtb r3, r3 + 80120bc: 2b00 cmp r3, #0 + 80120be: d004 beq.n 80120ca + { + SPIF_CsPin(Handle, 1); + 80120c0: 2101 movs r1, #1 + 80120c2: 68f8 ldr r0, [r7, #12] + 80120c4: f7ff fcd9 bl 8011a7a + break; + 80120c8: e013 b.n 80120f2 + } + SPIF_CsPin(Handle, 1); + 80120ca: 2101 movs r1, #1 + 80120cc: 68f8 ldr r0, [r7, #12] + 80120ce: f7ff fcd4 bl 8011a7a + if (SPIF_WaitForWriting(Handle, 100)) + 80120d2: 2164 movs r1, #100 ; 0x64 + 80120d4: 68f8 ldr r0, [r7, #12] + 80120d6: f7ff fdae bl 8011c36 + 80120da: 4603 mov r3, r0 + 80120dc: 2b00 cmp r3, #0 + 80120de: d008 beq.n 80120f2 + { + dprintf("SPIF_WritePage() %d BYTES WITERN DONE AFTER %ld ms\r\n", (uint16_t)Size, HAL_GetTick() - dbgTime); + retVal = true; + 80120e0: 2301 movs r3, #1 + 80120e2: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 80120e6: e004 b.n 80120f2 + break; + 80120e8: bf00 nop + 80120ea: e002 b.n 80120f2 + break; + 80120ec: bf00 nop + 80120ee: e000 b.n 80120f2 + break; + 80120f0: bf00 nop + } + + } while (0); + + SPIF_WriteDisable(Handle); + 80120f2: 68f8 ldr r0, [r7, #12] + 80120f4: f7ff fd56 bl 8011ba4 + return retVal; + 80120f8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } - 80101e6: 4618 mov r0, r3 - 80101e8: 3708 adds r7, #8 - 80101ea: 46bd mov sp, r7 - 80101ec: bd80 pop {r7, pc} + 80120fc: 4618 mov r0, r3 + 80120fe: 3728 adds r7, #40 ; 0x28 + 8012100: 46bd mov sp, r7 + 8012102: bd80 pop {r7, pc} + +08012104 : + +/***********************************************************************************************************/ + +bool SPIF_ReadFn(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size) +{ + 8012104: b580 push {r7, lr} + 8012106: b086 sub sp, #24 + 8012108: af00 add r7, sp, #0 + 801210a: 60f8 str r0, [r7, #12] + 801210c: 60b9 str r1, [r7, #8] + 801210e: 607a str r2, [r7, #4] + 8012110: 603b str r3, [r7, #0] + bool retVal = false; + 8012112: 2300 movs r3, #0 + 8012114: 75fb strb r3, [r7, #23] + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_ReadAddress() START ADDRESS %ld\r\n", Address); + SPIF_CsPin(Handle, 0); + 8012116: 2100 movs r1, #0 + 8012118: 68f8 ldr r0, [r7, #12] + 801211a: f7ff fcae bl 8011a7a + if (Handle->BlockCnt >= 512) + 801211e: 68fb ldr r3, [r7, #12] + 8012120: 69db ldr r3, [r3, #28] + 8012122: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8012126: d322 bcc.n 801216e + { + tx[0] = SPIF_CMD_READDATA4ADD; + 8012128: 2313 movs r3, #19 + 801212a: 743b strb r3, [r7, #16] + tx[1] = (Address & 0xFF000000) >> 24; + 801212c: 68bb ldr r3, [r7, #8] + 801212e: 0e1b lsrs r3, r3, #24 + 8012130: b2db uxtb r3, r3 + 8012132: 747b strb r3, [r7, #17] + tx[2] = (Address & 0x00FF0000) >> 16; + 8012134: 68bb ldr r3, [r7, #8] + 8012136: 0c1b lsrs r3, r3, #16 + 8012138: b2db uxtb r3, r3 + 801213a: 74bb strb r3, [r7, #18] + tx[3] = (Address & 0x0000FF00) >> 8; + 801213c: 68bb ldr r3, [r7, #8] + 801213e: 0a1b lsrs r3, r3, #8 + 8012140: b2db uxtb r3, r3 + 8012142: 74fb strb r3, [r7, #19] + tx[4] = (Address & 0x000000FF); + 8012144: 68bb ldr r3, [r7, #8] + 8012146: b2db uxtb r3, r3 + 8012148: 753b strb r3, [r7, #20] + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + 801214a: f107 0110 add.w r1, r7, #16 + 801214e: 2364 movs r3, #100 ; 0x64 + 8012150: 2205 movs r2, #5 + 8012152: 68f8 ldr r0, [r7, #12] + 8012154: f7ff fccc bl 8011af0 + 8012158: 4603 mov r3, r0 + 801215a: f083 0301 eor.w r3, r3, #1 + 801215e: b2db uxtb r3, r3 + 8012160: 2b00 cmp r3, #0 + 8012162: d023 beq.n 80121ac + { + SPIF_CsPin(Handle, 1); + 8012164: 2101 movs r1, #1 + 8012166: 68f8 ldr r0, [r7, #12] + 8012168: f7ff fc87 bl 8011a7a + break; + 801216c: e036 b.n 80121dc + } + } + else + { + tx[0] = SPIF_CMD_READDATA3ADD; + 801216e: 2303 movs r3, #3 + 8012170: 743b strb r3, [r7, #16] + tx[1] = (Address & 0x00FF0000) >> 16; + 8012172: 68bb ldr r3, [r7, #8] + 8012174: 0c1b lsrs r3, r3, #16 + 8012176: b2db uxtb r3, r3 + 8012178: 747b strb r3, [r7, #17] + tx[2] = (Address & 0x0000FF00) >> 8; + 801217a: 68bb ldr r3, [r7, #8] + 801217c: 0a1b lsrs r3, r3, #8 + 801217e: b2db uxtb r3, r3 + 8012180: 74bb strb r3, [r7, #18] + tx[3] = (Address & 0x000000FF); + 8012182: 68bb ldr r3, [r7, #8] + 8012184: b2db uxtb r3, r3 + 8012186: 74fb strb r3, [r7, #19] + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + 8012188: f107 0110 add.w r1, r7, #16 + 801218c: 2364 movs r3, #100 ; 0x64 + 801218e: 2204 movs r2, #4 + 8012190: 68f8 ldr r0, [r7, #12] + 8012192: f7ff fcad bl 8011af0 + 8012196: 4603 mov r3, r0 + 8012198: f083 0301 eor.w r3, r3, #1 + 801219c: b2db uxtb r3, r3 + 801219e: 2b00 cmp r3, #0 + 80121a0: d004 beq.n 80121ac + { + SPIF_CsPin(Handle, 1); + 80121a2: 2101 movs r1, #1 + 80121a4: 68f8 ldr r0, [r7, #12] + 80121a6: f7ff fc68 bl 8011a7a + break; + 80121aa: e017 b.n 80121dc + } + } + if (SPIF_Receive(Handle, Data, Size, 2000) == false) + 80121ac: f44f 63fa mov.w r3, #2000 ; 0x7d0 + 80121b0: 683a ldr r2, [r7, #0] + 80121b2: 6879 ldr r1, [r7, #4] + 80121b4: 68f8 ldr r0, [r7, #12] + 80121b6: f7ff fcb6 bl 8011b26 + 80121ba: 4603 mov r3, r0 + 80121bc: f083 0301 eor.w r3, r3, #1 + 80121c0: b2db uxtb r3, r3 + 80121c2: 2b00 cmp r3, #0 + 80121c4: d004 beq.n 80121d0 + { + SPIF_CsPin(Handle, 1); + 80121c6: 2101 movs r1, #1 + 80121c8: 68f8 ldr r0, [r7, #12] + 80121ca: f7ff fc56 bl 8011a7a + break; + 80121ce: e005 b.n 80121dc + } + SPIF_CsPin(Handle, 1); + 80121d0: 2101 movs r1, #1 + 80121d2: 68f8 ldr r0, [r7, #12] + 80121d4: f7ff fc51 bl 8011a7a + } + dprintf(", 0x%02X", Data[i]); + } + dprintf("\r\n}\r\n"); +#endif + retVal = true; + 80121d8: 2301 movs r3, #1 + 80121da: 75fb strb r3, [r7, #23] + + } while (0); + + return retVal; + 80121dc: 7dfb ldrb r3, [r7, #23] +} + 80121de: 4618 mov r0, r3 + 80121e0: 3718 adds r7, #24 + 80121e2: 46bd mov sp, r7 + 80121e4: bd80 pop {r7, pc} + +080121e6 : + * @param Pin: Pin of CS + * + * @retval bool: true or false + */ +bool SPIF_Init(SPIF_HandleTypeDef *Handle, SPI_HandleTypeDef *HSpi, GPIO_TypeDef *Gpio, uint16_t Pin) +{ + 80121e6: b580 push {r7, lr} + 80121e8: b086 sub sp, #24 + 80121ea: af00 add r7, sp, #0 + 80121ec: 60f8 str r0, [r7, #12] + 80121ee: 60b9 str r1, [r7, #8] + 80121f0: 607a str r2, [r7, #4] + 80121f2: 807b strh r3, [r7, #2] + bool retVal = false; + 80121f4: 2300 movs r3, #0 + 80121f6: 75fb strb r3, [r7, #23] + do + { + if ((Handle == NULL) || (HSpi == NULL) || (Gpio == NULL) || (Handle->Inited == 1)) + 80121f8: 68fb ldr r3, [r7, #12] + 80121fa: 2b00 cmp r3, #0 + 80121fc: d03a beq.n 8012274 + 80121fe: 68bb ldr r3, [r7, #8] + 8012200: 2b00 cmp r3, #0 + 8012202: d037 beq.n 8012274 + 8012204: 687b ldr r3, [r7, #4] + 8012206: 2b00 cmp r3, #0 + 8012208: d034 beq.n 8012274 + 801220a: 68fb ldr r3, [r7, #12] + 801220c: 7a9b ldrb r3, [r3, #10] + 801220e: 2b01 cmp r3, #1 + 8012210: d030 beq.n 8012274 + { + dprintf("SPIF_Init() Error, Wrong Parameter\r\n"); + break; + } + memset(Handle, 0, sizeof(SPIF_HandleTypeDef)); + 8012212: 2220 movs r2, #32 + 8012214: 2100 movs r1, #0 + 8012216: 68f8 ldr r0, [r7, #12] + 8012218: f002 fe77 bl 8014f0a + Handle->HSpi = HSpi; + 801221c: 68fb ldr r3, [r7, #12] + 801221e: 68ba ldr r2, [r7, #8] + 8012220: 601a str r2, [r3, #0] + Handle->Gpio = Gpio; + 8012222: 68fb ldr r3, [r7, #12] + 8012224: 687a ldr r2, [r7, #4] + 8012226: 605a str r2, [r3, #4] + Handle->Pin = Pin; + 8012228: 887a ldrh r2, [r7, #2] + 801222a: 68fb ldr r3, [r7, #12] + 801222c: 611a str r2, [r3, #16] + SPIF_CsPin(Handle, 1); + 801222e: 2101 movs r1, #1 + 8012230: 68f8 ldr r0, [r7, #12] + 8012232: f7ff fc22 bl 8011a7a + /* wait for stable VCC */ + while (HAL_GetTick() < 20) + 8012236: e002 b.n 801223e + { + SPIF_Delay(1); + 8012238: 2001 movs r0, #1 + 801223a: f7ff fbf3 bl 8011a24 + while (HAL_GetTick() < 20) + 801223e: f7f3 f807 bl 8005250 + 8012242: 4603 mov r3, r0 + 8012244: 2b13 cmp r3, #19 + 8012246: d9f7 bls.n 8012238 + } + if (SPIF_WriteDisable(Handle) == false) + 8012248: 68f8 ldr r0, [r7, #12] + 801224a: f7ff fcab bl 8011ba4 + 801224e: 4603 mov r3, r0 + 8012250: f083 0301 eor.w r3, r3, #1 + 8012254: b2db uxtb r3, r3 + 8012256: 2b00 cmp r3, #0 + 8012258: d10b bne.n 8012272 + { + break; + } + retVal = SPIF_FindChip(Handle); + 801225a: 68f8 ldr r0, [r7, #12] + 801225c: f7ff fd12 bl 8011c84 + 8012260: 4603 mov r3, r0 + 8012262: 75fb strb r3, [r7, #23] + if (retVal) + 8012264: 7dfb ldrb r3, [r7, #23] + 8012266: 2b00 cmp r3, #0 + 8012268: d004 beq.n 8012274 + { + Handle->Inited = 1; + 801226a: 68fb ldr r3, [r7, #12] + 801226c: 2201 movs r2, #1 + 801226e: 729a strb r2, [r3, #10] + 8012270: e000 b.n 8012274 + break; + 8012272: bf00 nop + dprintf("SPIF_Init() Done\r\n"); + } + + } while (0); + + return retVal; + 8012274: 7dfb ldrb r3, [r7, #23] +} + 8012276: 4618 mov r0, r3 + 8012278: 3718 adds r7, #24 + 801227a: 46bd mov sp, r7 + 801227c: bd80 pop {r7, pc} + +0801227e : + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * + * @retval bool: true or false + */ +bool SPIF_EraseChip(SPIF_HandleTypeDef *Handle) +{ + 801227e: b580 push {r7, lr} + 8012280: b084 sub sp, #16 + 8012282: af00 add r7, sp, #0 + 8012284: 6078 str r0, [r7, #4] + SPIF_Lock(Handle); + 8012286: 6878 ldr r0, [r7, #4] + 8012288: f7ff fbd7 bl 8011a3a + bool retVal = false; + 801228c: 2300 movs r3, #0 + 801228e: 73fb strb r3, [r7, #15] + uint8_t tx[1] = {SPIF_CMD_CHIPERASE1}; + 8012290: 2360 movs r3, #96 ; 0x60 + 8012292: 733b strb r3, [r7, #12] + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_EraseChip() START\r\n"); + if (SPIF_WriteEnable(Handle) == false) + 8012294: 6878 ldr r0, [r7, #4] + 8012296: f7ff fc61 bl 8011b5c + 801229a: 4603 mov r3, r0 + 801229c: f083 0301 eor.w r3, r3, #1 + 80122a0: b2db uxtb r3, r3 + 80122a2: 2b00 cmp r3, #0 + 80122a4: d129 bne.n 80122fa + { + break; + } + SPIF_CsPin(Handle, 0); + 80122a6: 2100 movs r1, #0 + 80122a8: 6878 ldr r0, [r7, #4] + 80122aa: f7ff fbe6 bl 8011a7a + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + 80122ae: f107 010c add.w r1, r7, #12 + 80122b2: 2364 movs r3, #100 ; 0x64 + 80122b4: 2201 movs r2, #1 + 80122b6: 6878 ldr r0, [r7, #4] + 80122b8: f7ff fc1a bl 8011af0 + 80122bc: 4603 mov r3, r0 + 80122be: f083 0301 eor.w r3, r3, #1 + 80122c2: b2db uxtb r3, r3 + 80122c4: 2b00 cmp r3, #0 + 80122c6: d004 beq.n 80122d2 + { + SPIF_CsPin(Handle, 1); + 80122c8: 2101 movs r1, #1 + 80122ca: 6878 ldr r0, [r7, #4] + 80122cc: f7ff fbd5 bl 8011a7a + break; + 80122d0: e014 b.n 80122fc + } + SPIF_CsPin(Handle, 1); + 80122d2: 2101 movs r1, #1 + 80122d4: 6878 ldr r0, [r7, #4] + 80122d6: f7ff fbd0 bl 8011a7a + if (SPIF_WaitForWriting(Handle, Handle->BlockCnt * 1000)) + 80122da: 687b ldr r3, [r7, #4] + 80122dc: 69db ldr r3, [r3, #28] + 80122de: f44f 727a mov.w r2, #1000 ; 0x3e8 + 80122e2: fb02 f303 mul.w r3, r2, r3 + 80122e6: 4619 mov r1, r3 + 80122e8: 6878 ldr r0, [r7, #4] + 80122ea: f7ff fca4 bl 8011c36 + 80122ee: 4603 mov r3, r0 + 80122f0: 2b00 cmp r3, #0 + 80122f2: d003 beq.n 80122fc + { + dprintf("SPIF_EraseChip() DONE AFTER %ld ms\r\n", HAL_GetTick() - dbgTime); + retVal = true; + 80122f4: 2301 movs r3, #1 + 80122f6: 73fb strb r3, [r7, #15] + 80122f8: e000 b.n 80122fc + break; + 80122fa: bf00 nop + } + + } while (0); + + SPIF_WriteDisable(Handle); + 80122fc: 6878 ldr r0, [r7, #4] + 80122fe: f7ff fc51 bl 8011ba4 + SPIF_UnLock(Handle); + 8012302: 6878 ldr r0, [r7, #4] + 8012304: f7ff fbac bl 8011a60 + return retVal; + 8012308: 7bfb ldrb r3, [r7, #15] +} + 801230a: 4618 mov r0, r3 + 801230c: 3710 adds r7, #16 + 801230e: 46bd mov sp, r7 + 8012310: bd80 pop {r7, pc} + +08012312 : + * @param Sector: Selected Sector + * + * @retval bool: true or false + */ +bool SPIF_EraseSector(SPIF_HandleTypeDef *Handle, uint32_t Sector) +{ + 8012312: b580 push {r7, lr} + 8012314: b086 sub sp, #24 + 8012316: af00 add r7, sp, #0 + 8012318: 6078 str r0, [r7, #4] + 801231a: 6039 str r1, [r7, #0] + SPIF_Lock(Handle); + 801231c: 6878 ldr r0, [r7, #4] + 801231e: f7ff fb8c bl 8011a3a + bool retVal = false; + 8012322: 2300 movs r3, #0 + 8012324: 75fb strb r3, [r7, #23] + uint32_t address = Sector * SPIF_SECTOR_SIZE; + 8012326: 683b ldr r3, [r7, #0] + 8012328: 031b lsls r3, r3, #12 + 801232a: 613b str r3, [r7, #16] + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_EraseSector() START SECTOR %ld\r\n", Sector); + if (Sector >= Handle->SectorCnt) + 801232c: 687b ldr r3, [r7, #4] + 801232e: 699b ldr r3, [r3, #24] + 8012330: 683a ldr r2, [r7, #0] + 8012332: 429a cmp r2, r3 + 8012334: d262 bcs.n 80123fc + { + dprintf("SPIF_EraseSector() ERROR Sector NUMBER\r\n"); + break; + } + if (SPIF_WriteEnable(Handle) == false) + 8012336: 6878 ldr r0, [r7, #4] + 8012338: f7ff fc10 bl 8011b5c + 801233c: 4603 mov r3, r0 + 801233e: f083 0301 eor.w r3, r3, #1 + 8012342: b2db uxtb r3, r3 + 8012344: 2b00 cmp r3, #0 + 8012346: d15b bne.n 8012400 + { + break; + } + SPIF_CsPin(Handle, 0); + 8012348: 2100 movs r1, #0 + 801234a: 6878 ldr r0, [r7, #4] + 801234c: f7ff fb95 bl 8011a7a + if (Handle->BlockCnt >= 512) + 8012350: 687b ldr r3, [r7, #4] + 8012352: 69db ldr r3, [r3, #28] + 8012354: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8012358: d322 bcc.n 80123a0 + { + tx[0] = SPIF_CMD_SECTORERASE4ADD; + 801235a: 2321 movs r3, #33 ; 0x21 + 801235c: 723b strb r3, [r7, #8] + tx[1] = (address & 0xFF000000) >> 24; + 801235e: 693b ldr r3, [r7, #16] + 8012360: 0e1b lsrs r3, r3, #24 + 8012362: b2db uxtb r3, r3 + 8012364: 727b strb r3, [r7, #9] + tx[2] = (address & 0x00FF0000) >> 16; + 8012366: 693b ldr r3, [r7, #16] + 8012368: 0c1b lsrs r3, r3, #16 + 801236a: b2db uxtb r3, r3 + 801236c: 72bb strb r3, [r7, #10] + tx[3] = (address & 0x0000FF00) >> 8; + 801236e: 693b ldr r3, [r7, #16] + 8012370: 0a1b lsrs r3, r3, #8 + 8012372: b2db uxtb r3, r3 + 8012374: 72fb strb r3, [r7, #11] + tx[4] = (address & 0x000000FF); + 8012376: 693b ldr r3, [r7, #16] + 8012378: b2db uxtb r3, r3 + 801237a: 733b strb r3, [r7, #12] + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + 801237c: f107 0108 add.w r1, r7, #8 + 8012380: 2364 movs r3, #100 ; 0x64 + 8012382: 2205 movs r2, #5 + 8012384: 6878 ldr r0, [r7, #4] + 8012386: f7ff fbb3 bl 8011af0 + 801238a: 4603 mov r3, r0 + 801238c: f083 0301 eor.w r3, r3, #1 + 8012390: b2db uxtb r3, r3 + 8012392: 2b00 cmp r3, #0 + 8012394: d023 beq.n 80123de + { + SPIF_CsPin(Handle, 1); + 8012396: 2101 movs r1, #1 + 8012398: 6878 ldr r0, [r7, #4] + 801239a: f7ff fb6e bl 8011a7a + break; + 801239e: e030 b.n 8012402 + } + } + else + { + tx[0] = SPIF_CMD_SECTORERASE3ADD; + 80123a0: 2320 movs r3, #32 + 80123a2: 723b strb r3, [r7, #8] + tx[1] = (address & 0x00FF0000) >> 16; + 80123a4: 693b ldr r3, [r7, #16] + 80123a6: 0c1b lsrs r3, r3, #16 + 80123a8: b2db uxtb r3, r3 + 80123aa: 727b strb r3, [r7, #9] + tx[2] = (address & 0x0000FF00) >> 8; + 80123ac: 693b ldr r3, [r7, #16] + 80123ae: 0a1b lsrs r3, r3, #8 + 80123b0: b2db uxtb r3, r3 + 80123b2: 72bb strb r3, [r7, #10] + tx[3] = (address & 0x000000FF); + 80123b4: 693b ldr r3, [r7, #16] + 80123b6: b2db uxtb r3, r3 + 80123b8: 72fb strb r3, [r7, #11] + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + 80123ba: f107 0108 add.w r1, r7, #8 + 80123be: 2364 movs r3, #100 ; 0x64 + 80123c0: 2204 movs r2, #4 + 80123c2: 6878 ldr r0, [r7, #4] + 80123c4: f7ff fb94 bl 8011af0 + 80123c8: 4603 mov r3, r0 + 80123ca: f083 0301 eor.w r3, r3, #1 + 80123ce: b2db uxtb r3, r3 + 80123d0: 2b00 cmp r3, #0 + 80123d2: d004 beq.n 80123de + { + SPIF_CsPin(Handle, 1); + 80123d4: 2101 movs r1, #1 + 80123d6: 6878 ldr r0, [r7, #4] + 80123d8: f7ff fb4f bl 8011a7a + break; + 80123dc: e011 b.n 8012402 + } + } + SPIF_CsPin(Handle, 1); + 80123de: 2101 movs r1, #1 + 80123e0: 6878 ldr r0, [r7, #4] + 80123e2: f7ff fb4a bl 8011a7a + if (SPIF_WaitForWriting(Handle, 1000)) + 80123e6: f44f 717a mov.w r1, #1000 ; 0x3e8 + 80123ea: 6878 ldr r0, [r7, #4] + 80123ec: f7ff fc23 bl 8011c36 + 80123f0: 4603 mov r3, r0 + 80123f2: 2b00 cmp r3, #0 + 80123f4: d005 beq.n 8012402 + { + dprintf("SPIF_EraseSector() DONE AFTER %ld ms\r\n", HAL_GetTick() - dbgTime); + retVal = true; + 80123f6: 2301 movs r3, #1 + 80123f8: 75fb strb r3, [r7, #23] + 80123fa: e002 b.n 8012402 + break; + 80123fc: bf00 nop + 80123fe: e000 b.n 8012402 + break; + 8012400: bf00 nop + } + + } while (0); + + SPIF_WriteDisable(Handle); + 8012402: 6878 ldr r0, [r7, #4] + 8012404: f7ff fbce bl 8011ba4 + SPIF_UnLock(Handle); + 8012408: 6878 ldr r0, [r7, #4] + 801240a: f7ff fb29 bl 8011a60 + return retVal; + 801240e: 7dfb ldrb r3, [r7, #23] +} + 8012410: 4618 mov r0, r3 + 8012412: 3718 adds r7, #24 + 8012414: 46bd mov sp, r7 + 8012416: bd80 pop {r7, pc} + +08012418 : + * @param Offset: The start point for writing data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_WritePage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + 8012418: b580 push {r7, lr} + 801241a: b088 sub sp, #32 + 801241c: af02 add r7, sp, #8 + 801241e: 60f8 str r0, [r7, #12] + 8012420: 60b9 str r1, [r7, #8] + 8012422: 607a str r2, [r7, #4] + 8012424: 603b str r3, [r7, #0] + SPIF_Lock(Handle); + 8012426: 68f8 ldr r0, [r7, #12] + 8012428: f7ff fb07 bl 8011a3a + bool retVal = false; + 801242c: 2300 movs r3, #0 + 801242e: 75fb strb r3, [r7, #23] + retVal = SPIF_WriteFn(Handle, PageNumber, Data, Size, Offset); + 8012430: 6a3b ldr r3, [r7, #32] + 8012432: 9300 str r3, [sp, #0] + 8012434: 683b ldr r3, [r7, #0] + 8012436: 687a ldr r2, [r7, #4] + 8012438: 68b9 ldr r1, [r7, #8] + 801243a: 68f8 ldr r0, [r7, #12] + 801243c: f7ff fdba bl 8011fb4 + 8012440: 4603 mov r3, r0 + 8012442: 75fb strb r3, [r7, #23] + SPIF_UnLock(Handle); + 8012444: 68f8 ldr r0, [r7, #12] + 8012446: f7ff fb0b bl 8011a60 + return retVal; + 801244a: 7dfb ldrb r3, [r7, #23] +} + 801244c: 4618 mov r0, r3 + 801244e: 3718 adds r7, #24 + 8012450: 46bd mov sp, r7 + 8012452: bd80 pop {r7, pc} + +08012454 : + * @param Offset: The start point for Reading data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_ReadPage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + 8012454: b580 push {r7, lr} + 8012456: b088 sub sp, #32 + 8012458: af00 add r7, sp, #0 + 801245a: 60f8 str r0, [r7, #12] + 801245c: 60b9 str r1, [r7, #8] + 801245e: 607a str r2, [r7, #4] + 8012460: 603b str r3, [r7, #0] + SPIF_Lock(Handle); + 8012462: 68f8 ldr r0, [r7, #12] + 8012464: f7ff fae9 bl 8011a3a + bool retVal = false; + 8012468: 2300 movs r3, #0 + 801246a: 77fb strb r3, [r7, #31] + uint32_t address = SPIF_PageToAddress(PageNumber) + Offset; + 801246c: 68bb ldr r3, [r7, #8] + 801246e: 021b lsls r3, r3, #8 + 8012470: 6aba ldr r2, [r7, #40] ; 0x28 + 8012472: 4413 add r3, r2 + 8012474: 61bb str r3, [r7, #24] + uint32_t maximum = SPIF_PAGE_SIZE - Offset; + 8012476: 6abb ldr r3, [r7, #40] ; 0x28 + 8012478: f5c3 7380 rsb r3, r3, #256 ; 0x100 + 801247c: 617b str r3, [r7, #20] + if (Size > maximum) + 801247e: 683a ldr r2, [r7, #0] + 8012480: 697b ldr r3, [r7, #20] + 8012482: 429a cmp r2, r3 + 8012484: d901 bls.n 801248a + { + Size = maximum; + 8012486: 697b ldr r3, [r7, #20] + 8012488: 603b str r3, [r7, #0] + } + retVal = SPIF_ReadFn(Handle, address, Data, Size); + 801248a: 683b ldr r3, [r7, #0] + 801248c: 687a ldr r2, [r7, #4] + 801248e: 69b9 ldr r1, [r7, #24] + 8012490: 68f8 ldr r0, [r7, #12] + 8012492: f7ff fe37 bl 8012104 + 8012496: 4603 mov r3, r0 + 8012498: 77fb strb r3, [r7, #31] + SPIF_UnLock(Handle); + 801249a: 68f8 ldr r0, [r7, #12] + 801249c: f7ff fae0 bl 8011a60 + return retVal; + 80124a0: 7ffb ldrb r3, [r7, #31] +} + 80124a2: 4618 mov r0, r3 + 80124a4: 3720 adds r7, #32 + 80124a6: 46bd mov sp, r7 + 80124a8: bd80 pop {r7, pc} ... -080101f0 : +080124ac : /** * Init USB device Library, add supported class and start the library * @retval None */ void MX_USB_DEVICE_Init(void) { - 80101f0: b580 push {r7, lr} - 80101f2: af00 add r7, sp, #0 + 80124ac: b580 push {r7, lr} + 80124ae: af00 add r7, sp, #0 /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) - 80101f4: 2200 movs r2, #0 - 80101f6: 490e ldr r1, [pc, #56] ; (8010230 ) - 80101f8: 480e ldr r0, [pc, #56] ; (8010234 ) - 80101fa: f7fe fd85 bl 800ed08 - 80101fe: 4603 mov r3, r0 - 8010200: 2b00 cmp r3, #0 - 8010202: d001 beq.n 8010208 + 80124b0: 2200 movs r2, #0 + 80124b2: 4912 ldr r1, [pc, #72] ; (80124fc ) + 80124b4: 4812 ldr r0, [pc, #72] ; (8012500 ) + 80124b6: f7fe f825 bl 8010504 + 80124ba: 4603 mov r3, r0 + 80124bc: 2b00 cmp r3, #0 + 80124be: d001 beq.n 80124c4 + { + Error_Handler(); + 80124c0: f7ef fa97 bl 80019f2 + } + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) + 80124c4: 490f ldr r1, [pc, #60] ; (8012504 ) + 80124c6: 480e ldr r0, [pc, #56] ; (8012500 ) + 80124c8: f7fe f84c bl 8010564 + 80124cc: 4603 mov r3, r0 + 80124ce: 2b00 cmp r3, #0 + 80124d0: d001 beq.n 80124d6 { Error_Handler(); - 8010204: f7f1 faf8 bl 80017f8 + 80124d2: f7ef fa8e bl 80019f2 } - if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) - 8010208: 490b ldr r1, [pc, #44] ; (8010238 ) - 801020a: 480a ldr r0, [pc, #40] ; (8010234 ) - 801020c: f7fe fdac bl 800ed68 - 8010210: 4603 mov r3, r0 - 8010212: 2b00 cmp r3, #0 - 8010214: d001 beq.n 801021a + if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) + 80124d6: 490c ldr r1, [pc, #48] ; (8012508 ) + 80124d8: 4809 ldr r0, [pc, #36] ; (8012500 ) + 80124da: f7fd ff43 bl 8010364 + 80124de: 4603 mov r3, r0 + 80124e0: 2b00 cmp r3, #0 + 80124e2: d001 beq.n 80124e8 { Error_Handler(); - 8010216: f7f1 faef bl 80017f8 + 80124e4: f7ef fa85 bl 80019f2 } if (USBD_Start(&hUsbDeviceFS) != USBD_OK) - 801021a: 4806 ldr r0, [pc, #24] ; (8010234 ) - 801021c: f7fe fdda bl 800edd4 - 8010220: 4603 mov r3, r0 - 8010222: 2b00 cmp r3, #0 - 8010224: d001 beq.n 801022a + 80124e8: 4805 ldr r0, [pc, #20] ; (8012500 ) + 80124ea: f7fe f871 bl 80105d0 + 80124ee: 4603 mov r3, r0 + 80124f0: 2b00 cmp r3, #0 + 80124f2: d001 beq.n 80124f8 { Error_Handler(); - 8010226: f7f1 fae7 bl 80017f8 + 80124f4: f7ef fa7d bl 80019f2 } /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ /* USER CODE END USB_DEVICE_Init_PostTreatment */ } - 801022a: bf00 nop - 801022c: bd80 pop {r7, pc} - 801022e: bf00 nop - 8010230: 200000ec .word 0x200000ec - 8010234: 20000ca4 .word 0x20000ca4 - 8010238: 2000002c .word 0x2000002c + 80124f8: bf00 nop + 80124fa: bd80 pop {r7, pc} + 80124fc: 200000cc .word 0x200000cc + 8012500: 20001050 .word 0x20001050 + 8012504: 20000038 .word 0x20000038 + 8012508: 200000b8 .word 0x200000b8 + +0801250c : +/** + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) +{ + 801250c: b580 push {r7, lr} + 801250e: af00 add r7, sp, #0 + /* USER CODE BEGIN 3 */ + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + 8012510: 2200 movs r2, #0 + 8012512: 4905 ldr r1, [pc, #20] ; (8012528 ) + 8012514: 4805 ldr r0, [pc, #20] ; (801252c ) + 8012516: f7fd ff3f bl 8010398 + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + 801251a: 4905 ldr r1, [pc, #20] ; (8012530 ) + 801251c: 4803 ldr r0, [pc, #12] ; (801252c ) + 801251e: f7fd ff5d bl 80103dc + return (USBD_OK); + 8012522: 2300 movs r3, #0 + /* USER CODE END 3 */ +} + 8012524: 4618 mov r0, r3 + 8012526: bd80 pop {r7, pc} + 8012528: 2000172c .word 0x2000172c + 801252c: 20001050 .word 0x20001050 + 8012530: 2000132c .word 0x2000132c + +08012534 : +/** + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) +{ + 8012534: b480 push {r7} + 8012536: af00 add r7, sp, #0 + /* USER CODE BEGIN 4 */ + return (USBD_OK); + 8012538: 2300 movs r3, #0 + /* USER CODE END 4 */ +} + 801253a: 4618 mov r0, r3 + 801253c: 46bd mov sp, r7 + 801253e: f85d 7b04 ldr.w r7, [sp], #4 + 8012542: 4770 bx lr + +08012544 : + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + 8012544: b480 push {r7} + 8012546: b083 sub sp, #12 + 8012548: af00 add r7, sp, #0 + 801254a: 4603 mov r3, r0 + 801254c: 6039 str r1, [r7, #0] + 801254e: 71fb strb r3, [r7, #7] + 8012550: 4613 mov r3, r2 + 8012552: 80bb strh r3, [r7, #4] + /* USER CODE BEGIN 5 */ + switch(cmd) + 8012554: 79fb ldrb r3, [r7, #7] + 8012556: 2b23 cmp r3, #35 ; 0x23 + 8012558: d84a bhi.n 80125f0 + 801255a: a201 add r2, pc, #4 ; (adr r2, 8012560 ) + 801255c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012560: 080125f1 .word 0x080125f1 + 8012564: 080125f1 .word 0x080125f1 + 8012568: 080125f1 .word 0x080125f1 + 801256c: 080125f1 .word 0x080125f1 + 8012570: 080125f1 .word 0x080125f1 + 8012574: 080125f1 .word 0x080125f1 + 8012578: 080125f1 .word 0x080125f1 + 801257c: 080125f1 .word 0x080125f1 + 8012580: 080125f1 .word 0x080125f1 + 8012584: 080125f1 .word 0x080125f1 + 8012588: 080125f1 .word 0x080125f1 + 801258c: 080125f1 .word 0x080125f1 + 8012590: 080125f1 .word 0x080125f1 + 8012594: 080125f1 .word 0x080125f1 + 8012598: 080125f1 .word 0x080125f1 + 801259c: 080125f1 .word 0x080125f1 + 80125a0: 080125f1 .word 0x080125f1 + 80125a4: 080125f1 .word 0x080125f1 + 80125a8: 080125f1 .word 0x080125f1 + 80125ac: 080125f1 .word 0x080125f1 + 80125b0: 080125f1 .word 0x080125f1 + 80125b4: 080125f1 .word 0x080125f1 + 80125b8: 080125f1 .word 0x080125f1 + 80125bc: 080125f1 .word 0x080125f1 + 80125c0: 080125f1 .word 0x080125f1 + 80125c4: 080125f1 .word 0x080125f1 + 80125c8: 080125f1 .word 0x080125f1 + 80125cc: 080125f1 .word 0x080125f1 + 80125d0: 080125f1 .word 0x080125f1 + 80125d4: 080125f1 .word 0x080125f1 + 80125d8: 080125f1 .word 0x080125f1 + 80125dc: 080125f1 .word 0x080125f1 + 80125e0: 080125f1 .word 0x080125f1 + 80125e4: 080125f1 .word 0x080125f1 + 80125e8: 080125f1 .word 0x080125f1 + 80125ec: 080125f1 .word 0x080125f1 + case CDC_SEND_BREAK: + + break; + + default: + break; + 80125f0: bf00 nop + } + + return (USBD_OK); + 80125f2: 2300 movs r3, #0 + /* USER CODE END 5 */ +} + 80125f4: 4618 mov r0, r3 + 80125f6: 370c adds r7, #12 + 80125f8: 46bd mov sp, r7 + 80125fa: f85d 7b04 ldr.w r7, [sp], #4 + 80125fe: 4770 bx lr + +08012600 : + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +{ + 8012600: b580 push {r7, lr} + 8012602: b082 sub sp, #8 + 8012604: af00 add r7, sp, #0 + 8012606: 6078 str r0, [r7, #4] + 8012608: 6039 str r1, [r7, #0] + /* USER CODE BEGIN 6 */ + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + 801260a: 6879 ldr r1, [r7, #4] + 801260c: 4805 ldr r0, [pc, #20] ; (8012624 ) + 801260e: f7fd fee5 bl 80103dc + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + 8012612: 4804 ldr r0, [pc, #16] ; (8012624 ) + 8012614: f7fd ff40 bl 8010498 + return (USBD_OK); + 8012618: 2300 movs r3, #0 + /* USER CODE END 6 */ +} + 801261a: 4618 mov r0, r3 + 801261c: 3708 adds r7, #8 + 801261e: 46bd mov sp, r7 + 8012620: bd80 pop {r7, pc} + 8012622: bf00 nop + 8012624: 20001050 .word 0x20001050 + +08012628 : + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +{ + 8012628: b580 push {r7, lr} + 801262a: b084 sub sp, #16 + 801262c: af00 add r7, sp, #0 + 801262e: 6078 str r0, [r7, #4] + 8012630: 460b mov r3, r1 + 8012632: 807b strh r3, [r7, #2] + uint8_t result = USBD_OK; + 8012634: 2300 movs r3, #0 + 8012636: 73fb strb r3, [r7, #15] + /* USER CODE BEGIN 7 */ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + 8012638: 4b0d ldr r3, [pc, #52] ; (8012670 ) + 801263a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc + 801263e: 60bb str r3, [r7, #8] + if (hcdc->TxState != 0){ + 8012640: 68bb ldr r3, [r7, #8] + 8012642: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214 + 8012646: 2b00 cmp r3, #0 + 8012648: d001 beq.n 801264e + return USBD_BUSY; + 801264a: 2301 movs r3, #1 + 801264c: e00b b.n 8012666 + } + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + 801264e: 887b ldrh r3, [r7, #2] + 8012650: 461a mov r2, r3 + 8012652: 6879 ldr r1, [r7, #4] + 8012654: 4806 ldr r0, [pc, #24] ; (8012670 ) + 8012656: f7fd fe9f bl 8010398 + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + 801265a: 4805 ldr r0, [pc, #20] ; (8012670 ) + 801265c: f7fd fedc bl 8010418 + 8012660: 4603 mov r3, r0 + 8012662: 73fb strb r3, [r7, #15] + /* USER CODE END 7 */ + return result; + 8012664: 7bfb ldrb r3, [r7, #15] +} + 8012666: 4618 mov r0, r3 + 8012668: 3710 adds r7, #16 + 801266a: 46bd mov sp, r7 + 801266c: bd80 pop {r7, pc} + 801266e: bf00 nop + 8012670: 20001050 .word 0x20001050 + +08012674 : + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) +{ + 8012674: b480 push {r7} + 8012676: b087 sub sp, #28 + 8012678: af00 add r7, sp, #0 + 801267a: 60f8 str r0, [r7, #12] + 801267c: 60b9 str r1, [r7, #8] + 801267e: 4613 mov r3, r2 + 8012680: 71fb strb r3, [r7, #7] + uint8_t result = USBD_OK; + 8012682: 2300 movs r3, #0 + 8012684: 75fb strb r3, [r7, #23] + /* USER CODE BEGIN 13 */ + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); + /* USER CODE END 13 */ + return result; + 8012686: f997 3017 ldrsb.w r3, [r7, #23] +} + 801268a: 4618 mov r0, r3 + 801268c: 371c adds r7, #28 + 801268e: 46bd mov sp, r7 + 8012690: f85d 7b04 ldr.w r7, [sp], #4 + 8012694: 4770 bx lr + ... -0801023c : +08012698 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 801023c: b480 push {r7} - 801023e: b083 sub sp, #12 - 8010240: af00 add r7, sp, #0 - 8010242: 4603 mov r3, r0 - 8010244: 6039 str r1, [r7, #0] - 8010246: 71fb strb r3, [r7, #7] + 8012698: b480 push {r7} + 801269a: b083 sub sp, #12 + 801269c: af00 add r7, sp, #0 + 801269e: 4603 mov r3, r0 + 80126a0: 6039 str r1, [r7, #0] + 80126a2: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_DeviceDesc); - 8010248: 683b ldr r3, [r7, #0] - 801024a: 2212 movs r2, #18 - 801024c: 801a strh r2, [r3, #0] + 80126a4: 683b ldr r3, [r7, #0] + 80126a6: 2212 movs r2, #18 + 80126a8: 801a strh r2, [r3, #0] return USBD_FS_DeviceDesc; - 801024e: 4b03 ldr r3, [pc, #12] ; (801025c ) + 80126aa: 4b03 ldr r3, [pc, #12] ; (80126b8 ) } - 8010250: 4618 mov r0, r3 - 8010252: 370c adds r7, #12 - 8010254: 46bd mov sp, r7 - 8010256: f85d 7b04 ldr.w r7, [sp], #4 - 801025a: 4770 bx lr - 801025c: 2000010c .word 0x2000010c + 80126ac: 4618 mov r0, r3 + 80126ae: 370c adds r7, #12 + 80126b0: 46bd mov sp, r7 + 80126b2: f85d 7b04 ldr.w r7, [sp], #4 + 80126b6: 4770 bx lr + 80126b8: 200000ec .word 0x200000ec -08010260 : +080126bc : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 8010260: b480 push {r7} - 8010262: b083 sub sp, #12 - 8010264: af00 add r7, sp, #0 - 8010266: 4603 mov r3, r0 - 8010268: 6039 str r1, [r7, #0] - 801026a: 71fb strb r3, [r7, #7] + 80126bc: b480 push {r7} + 80126be: b083 sub sp, #12 + 80126c0: af00 add r7, sp, #0 + 80126c2: 4603 mov r3, r0 + 80126c4: 6039 str r1, [r7, #0] + 80126c6: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_LangIDDesc); - 801026c: 683b ldr r3, [r7, #0] - 801026e: 2204 movs r2, #4 - 8010270: 801a strh r2, [r3, #0] + 80126c8: 683b ldr r3, [r7, #0] + 80126ca: 2204 movs r2, #4 + 80126cc: 801a strh r2, [r3, #0] return USBD_LangIDDesc; - 8010272: 4b03 ldr r3, [pc, #12] ; (8010280 ) + 80126ce: 4b03 ldr r3, [pc, #12] ; (80126dc ) } - 8010274: 4618 mov r0, r3 - 8010276: 370c adds r7, #12 - 8010278: 46bd mov sp, r7 - 801027a: f85d 7b04 ldr.w r7, [sp], #4 - 801027e: 4770 bx lr - 8010280: 2000012c .word 0x2000012c + 80126d0: 4618 mov r0, r3 + 80126d2: 370c adds r7, #12 + 80126d4: 46bd mov sp, r7 + 80126d6: f85d 7b04 ldr.w r7, [sp], #4 + 80126da: 4770 bx lr + 80126dc: 2000010c .word 0x2000010c -08010284 : +080126e0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 8010284: b580 push {r7, lr} - 8010286: b082 sub sp, #8 - 8010288: af00 add r7, sp, #0 - 801028a: 4603 mov r3, r0 - 801028c: 6039 str r1, [r7, #0] - 801028e: 71fb strb r3, [r7, #7] + 80126e0: b580 push {r7, lr} + 80126e2: b082 sub sp, #8 + 80126e4: af00 add r7, sp, #0 + 80126e6: 4603 mov r3, r0 + 80126e8: 6039 str r1, [r7, #0] + 80126ea: 71fb strb r3, [r7, #7] if(speed == 0) - 8010290: 79fb ldrb r3, [r7, #7] - 8010292: 2b00 cmp r3, #0 - 8010294: d105 bne.n 80102a2 + 80126ec: 79fb ldrb r3, [r7, #7] + 80126ee: 2b00 cmp r3, #0 + 80126f0: d105 bne.n 80126fe { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - 8010296: 683a ldr r2, [r7, #0] - 8010298: 4907 ldr r1, [pc, #28] ; (80102b8 ) - 801029a: 4808 ldr r0, [pc, #32] ; (80102bc ) - 801029c: f7ff fee4 bl 8010068 - 80102a0: e004 b.n 80102ac + 80126f2: 683a ldr r2, [r7, #0] + 80126f4: 4907 ldr r1, [pc, #28] ; (8012714 ) + 80126f6: 4808 ldr r0, [pc, #32] ; (8012718 ) + 80126f8: f7ff f8b4 bl 8011864 + 80126fc: e004 b.n 8012708 } else { USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - 80102a2: 683a ldr r2, [r7, #0] - 80102a4: 4904 ldr r1, [pc, #16] ; (80102b8 ) - 80102a6: 4805 ldr r0, [pc, #20] ; (80102bc ) - 80102a8: f7ff fede bl 8010068 + 80126fe: 683a ldr r2, [r7, #0] + 8012700: 4904 ldr r1, [pc, #16] ; (8012714 ) + 8012702: 4805 ldr r0, [pc, #20] ; (8012718 ) + 8012704: f7ff f8ae bl 8011864 } return USBD_StrDesc; - 80102ac: 4b02 ldr r3, [pc, #8] ; (80102b8 ) + 8012708: 4b02 ldr r3, [pc, #8] ; (8012714 ) } - 80102ae: 4618 mov r0, r3 - 80102b0: 3708 adds r7, #8 - 80102b2: 46bd mov sp, r7 - 80102b4: bd80 pop {r7, pc} - 80102b6: bf00 nop - 80102b8: 20000f80 .word 0x20000f80 - 80102bc: 08016acc .word 0x08016acc + 801270a: 4618 mov r0, r3 + 801270c: 3708 adds r7, #8 + 801270e: 46bd mov sp, r7 + 8012710: bd80 pop {r7, pc} + 8012712: bf00 nop + 8012714: 20001b2c .word 0x20001b2c + 8012718: 08018fb0 .word 0x08018fb0 -080102c0 : +0801271c : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 80102c0: b580 push {r7, lr} - 80102c2: b082 sub sp, #8 - 80102c4: af00 add r7, sp, #0 - 80102c6: 4603 mov r3, r0 - 80102c8: 6039 str r1, [r7, #0] - 80102ca: 71fb strb r3, [r7, #7] + 801271c: b580 push {r7, lr} + 801271e: b082 sub sp, #8 + 8012720: af00 add r7, sp, #0 + 8012722: 4603 mov r3, r0 + 8012724: 6039 str r1, [r7, #0] + 8012726: 71fb strb r3, [r7, #7] UNUSED(speed); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - 80102cc: 683a ldr r2, [r7, #0] - 80102ce: 4904 ldr r1, [pc, #16] ; (80102e0 ) - 80102d0: 4804 ldr r0, [pc, #16] ; (80102e4 ) - 80102d2: f7ff fec9 bl 8010068 + 8012728: 683a ldr r2, [r7, #0] + 801272a: 4904 ldr r1, [pc, #16] ; (801273c ) + 801272c: 4804 ldr r0, [pc, #16] ; (8012740 ) + 801272e: f7ff f899 bl 8011864 return USBD_StrDesc; - 80102d6: 4b02 ldr r3, [pc, #8] ; (80102e0 ) + 8012732: 4b02 ldr r3, [pc, #8] ; (801273c ) } - 80102d8: 4618 mov r0, r3 - 80102da: 3708 adds r7, #8 - 80102dc: 46bd mov sp, r7 - 80102de: bd80 pop {r7, pc} - 80102e0: 20000f80 .word 0x20000f80 - 80102e4: 08016ae4 .word 0x08016ae4 + 8012734: 4618 mov r0, r3 + 8012736: 3708 adds r7, #8 + 8012738: 46bd mov sp, r7 + 801273a: bd80 pop {r7, pc} + 801273c: 20001b2c .word 0x20001b2c + 8012740: 08018fbc .word 0x08018fbc -080102e8 : +08012744 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 80102e8: b580 push {r7, lr} - 80102ea: b082 sub sp, #8 - 80102ec: af00 add r7, sp, #0 - 80102ee: 4603 mov r3, r0 - 80102f0: 6039 str r1, [r7, #0] - 80102f2: 71fb strb r3, [r7, #7] + 8012744: b580 push {r7, lr} + 8012746: b082 sub sp, #8 + 8012748: af00 add r7, sp, #0 + 801274a: 4603 mov r3, r0 + 801274c: 6039 str r1, [r7, #0] + 801274e: 71fb strb r3, [r7, #7] UNUSED(speed); *length = USB_SIZ_STRING_SERIAL; - 80102f4: 683b ldr r3, [r7, #0] - 80102f6: 221a movs r2, #26 - 80102f8: 801a strh r2, [r3, #0] + 8012750: 683b ldr r3, [r7, #0] + 8012752: 221a movs r2, #26 + 8012754: 801a strh r2, [r3, #0] /* Update the serial number string descriptor with the data from the unique * ID */ Get_SerialNum(); - 80102fa: f000 f855 bl 80103a8 + 8012756: f000 f855 bl 8012804 /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ /* USER CODE END USBD_FS_SerialStrDescriptor */ return (uint8_t *) USBD_StringSerial; - 80102fe: 4b02 ldr r3, [pc, #8] ; (8010308 ) + 801275a: 4b02 ldr r3, [pc, #8] ; (8012764 ) } - 8010300: 4618 mov r0, r3 - 8010302: 3708 adds r7, #8 - 8010304: 46bd mov sp, r7 - 8010306: bd80 pop {r7, pc} - 8010308: 20000130 .word 0x20000130 + 801275c: 4618 mov r0, r3 + 801275e: 3708 adds r7, #8 + 8012760: 46bd mov sp, r7 + 8012762: bd80 pop {r7, pc} + 8012764: 20000110 .word 0x20000110 -0801030c : +08012768 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 801030c: b580 push {r7, lr} - 801030e: b082 sub sp, #8 - 8010310: af00 add r7, sp, #0 - 8010312: 4603 mov r3, r0 - 8010314: 6039 str r1, [r7, #0] - 8010316: 71fb strb r3, [r7, #7] + 8012768: b580 push {r7, lr} + 801276a: b082 sub sp, #8 + 801276c: af00 add r7, sp, #0 + 801276e: 4603 mov r3, r0 + 8012770: 6039 str r1, [r7, #0] + 8012772: 71fb strb r3, [r7, #7] if(speed == USBD_SPEED_HIGH) - 8010318: 79fb ldrb r3, [r7, #7] - 801031a: 2b00 cmp r3, #0 - 801031c: d105 bne.n 801032a + 8012774: 79fb ldrb r3, [r7, #7] + 8012776: 2b00 cmp r3, #0 + 8012778: d105 bne.n 8012786 { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - 801031e: 683a ldr r2, [r7, #0] - 8010320: 4907 ldr r1, [pc, #28] ; (8010340 ) - 8010322: 4808 ldr r0, [pc, #32] ; (8010344 ) - 8010324: f7ff fea0 bl 8010068 - 8010328: e004 b.n 8010334 + 801277a: 683a ldr r2, [r7, #0] + 801277c: 4907 ldr r1, [pc, #28] ; (801279c ) + 801277e: 4808 ldr r0, [pc, #32] ; (80127a0 ) + 8012780: f7ff f870 bl 8011864 + 8012784: e004 b.n 8012790 } else { USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - 801032a: 683a ldr r2, [r7, #0] - 801032c: 4904 ldr r1, [pc, #16] ; (8010340 ) - 801032e: 4805 ldr r0, [pc, #20] ; (8010344 ) - 8010330: f7ff fe9a bl 8010068 + 8012786: 683a ldr r2, [r7, #0] + 8012788: 4904 ldr r1, [pc, #16] ; (801279c ) + 801278a: 4805 ldr r0, [pc, #20] ; (80127a0 ) + 801278c: f7ff f86a bl 8011864 } return USBD_StrDesc; - 8010334: 4b02 ldr r3, [pc, #8] ; (8010340 ) + 8012790: 4b02 ldr r3, [pc, #8] ; (801279c ) } - 8010336: 4618 mov r0, r3 - 8010338: 3708 adds r7, #8 - 801033a: 46bd mov sp, r7 - 801033c: bd80 pop {r7, pc} - 801033e: bf00 nop - 8010340: 20000f80 .word 0x20000f80 - 8010344: 08016af8 .word 0x08016af8 + 8012792: 4618 mov r0, r3 + 8012794: 3708 adds r7, #8 + 8012796: 46bd mov sp, r7 + 8012798: bd80 pop {r7, pc} + 801279a: bf00 nop + 801279c: 20001b2c .word 0x20001b2c + 80127a0: 08018fd0 .word 0x08018fd0 -08010348 : +080127a4 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 8010348: b580 push {r7, lr} - 801034a: b082 sub sp, #8 - 801034c: af00 add r7, sp, #0 - 801034e: 4603 mov r3, r0 - 8010350: 6039 str r1, [r7, #0] - 8010352: 71fb strb r3, [r7, #7] + 80127a4: b580 push {r7, lr} + 80127a6: b082 sub sp, #8 + 80127a8: af00 add r7, sp, #0 + 80127aa: 4603 mov r3, r0 + 80127ac: 6039 str r1, [r7, #0] + 80127ae: 71fb strb r3, [r7, #7] if(speed == 0) - 8010354: 79fb ldrb r3, [r7, #7] - 8010356: 2b00 cmp r3, #0 - 8010358: d105 bne.n 8010366 + 80127b0: 79fb ldrb r3, [r7, #7] + 80127b2: 2b00 cmp r3, #0 + 80127b4: d105 bne.n 80127c2 { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - 801035a: 683a ldr r2, [r7, #0] - 801035c: 4907 ldr r1, [pc, #28] ; (801037c ) - 801035e: 4808 ldr r0, [pc, #32] ; (8010380 ) - 8010360: f7ff fe82 bl 8010068 - 8010364: e004 b.n 8010370 + 80127b6: 683a ldr r2, [r7, #0] + 80127b8: 4907 ldr r1, [pc, #28] ; (80127d8 ) + 80127ba: 4808 ldr r0, [pc, #32] ; (80127dc ) + 80127bc: f7ff f852 bl 8011864 + 80127c0: e004 b.n 80127cc } else { USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - 8010366: 683a ldr r2, [r7, #0] - 8010368: 4904 ldr r1, [pc, #16] ; (801037c ) - 801036a: 4805 ldr r0, [pc, #20] ; (8010380 ) - 801036c: f7ff fe7c bl 8010068 + 80127c2: 683a ldr r2, [r7, #0] + 80127c4: 4904 ldr r1, [pc, #16] ; (80127d8 ) + 80127c6: 4805 ldr r0, [pc, #20] ; (80127dc ) + 80127c8: f7ff f84c bl 8011864 } return USBD_StrDesc; - 8010370: 4b02 ldr r3, [pc, #8] ; (801037c ) + 80127cc: 4b02 ldr r3, [pc, #8] ; (80127d8 ) } - 8010372: 4618 mov r0, r3 - 8010374: 3708 adds r7, #8 - 8010376: 46bd mov sp, r7 - 8010378: bd80 pop {r7, pc} - 801037a: bf00 nop - 801037c: 20000f80 .word 0x20000f80 - 8010380: 08016b04 .word 0x08016b04 + 80127ce: 4618 mov r0, r3 + 80127d0: 3708 adds r7, #8 + 80127d2: 46bd mov sp, r7 + 80127d4: bd80 pop {r7, pc} + 80127d6: bf00 nop + 80127d8: 20001b2c .word 0x20001b2c + 80127dc: 08018fdc .word 0x08018fdc -08010384 : +080127e0 : * @param speed : Current device speed * @param length : Pointer to data length variable * @retval Pointer to descriptor buffer */ uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - 8010384: b480 push {r7} - 8010386: b083 sub sp, #12 - 8010388: af00 add r7, sp, #0 - 801038a: 4603 mov r3, r0 - 801038c: 6039 str r1, [r7, #0] - 801038e: 71fb strb r3, [r7, #7] + 80127e0: b480 push {r7} + 80127e2: b083 sub sp, #12 + 80127e4: af00 add r7, sp, #0 + 80127e6: 4603 mov r3, r0 + 80127e8: 6039 str r1, [r7, #0] + 80127ea: 71fb strb r3, [r7, #7] UNUSED(speed); *length = sizeof(USBD_FS_BOSDesc); - 8010390: 683b ldr r3, [r7, #0] - 8010392: 220c movs r2, #12 - 8010394: 801a strh r2, [r3, #0] + 80127ec: 683b ldr r3, [r7, #0] + 80127ee: 220c movs r2, #12 + 80127f0: 801a strh r2, [r3, #0] return (uint8_t*)USBD_FS_BOSDesc; - 8010396: 4b03 ldr r3, [pc, #12] ; (80103a4 ) + 80127f2: 4b03 ldr r3, [pc, #12] ; (8012800 ) } - 8010398: 4618 mov r0, r3 - 801039a: 370c adds r7, #12 - 801039c: 46bd mov sp, r7 - 801039e: f85d 7b04 ldr.w r7, [sp], #4 - 80103a2: 4770 bx lr - 80103a4: 20000120 .word 0x20000120 + 80127f4: 4618 mov r0, r3 + 80127f6: 370c adds r7, #12 + 80127f8: 46bd mov sp, r7 + 80127fa: f85d 7b04 ldr.w r7, [sp], #4 + 80127fe: 4770 bx lr + 8012800: 20000100 .word 0x20000100 -080103a8 : +08012804 : * @brief Create the serial number string descriptor * @param None * @retval None */ static void Get_SerialNum(void) { - 80103a8: b580 push {r7, lr} - 80103aa: b084 sub sp, #16 - 80103ac: af00 add r7, sp, #0 + 8012804: b580 push {r7, lr} + 8012806: b084 sub sp, #16 + 8012808: af00 add r7, sp, #0 uint32_t deviceserial0; uint32_t deviceserial1; uint32_t deviceserial2; deviceserial0 = *(uint32_t *) DEVICE_ID1; - 80103ae: 4b0f ldr r3, [pc, #60] ; (80103ec ) - 80103b0: 681b ldr r3, [r3, #0] - 80103b2: 60fb str r3, [r7, #12] + 801280a: 4b0f ldr r3, [pc, #60] ; (8012848 ) + 801280c: 681b ldr r3, [r3, #0] + 801280e: 60fb str r3, [r7, #12] deviceserial1 = *(uint32_t *) DEVICE_ID2; - 80103b4: 4b0e ldr r3, [pc, #56] ; (80103f0 ) - 80103b6: 681b ldr r3, [r3, #0] - 80103b8: 60bb str r3, [r7, #8] + 8012810: 4b0e ldr r3, [pc, #56] ; (801284c ) + 8012812: 681b ldr r3, [r3, #0] + 8012814: 60bb str r3, [r7, #8] deviceserial2 = *(uint32_t *) DEVICE_ID3; - 80103ba: 4b0e ldr r3, [pc, #56] ; (80103f4 ) - 80103bc: 681b ldr r3, [r3, #0] - 80103be: 607b str r3, [r7, #4] + 8012816: 4b0e ldr r3, [pc, #56] ; (8012850 ) + 8012818: 681b ldr r3, [r3, #0] + 801281a: 607b str r3, [r7, #4] deviceserial0 += deviceserial2; - 80103c0: 68fa ldr r2, [r7, #12] - 80103c2: 687b ldr r3, [r7, #4] - 80103c4: 4413 add r3, r2 - 80103c6: 60fb str r3, [r7, #12] + 801281c: 68fa ldr r2, [r7, #12] + 801281e: 687b ldr r3, [r7, #4] + 8012820: 4413 add r3, r2 + 8012822: 60fb str r3, [r7, #12] if (deviceserial0 != 0) - 80103c8: 68fb ldr r3, [r7, #12] - 80103ca: 2b00 cmp r3, #0 - 80103cc: d009 beq.n 80103e2 + 8012824: 68fb ldr r3, [r7, #12] + 8012826: 2b00 cmp r3, #0 + 8012828: d009 beq.n 801283e { IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); - 80103ce: 2208 movs r2, #8 - 80103d0: 4909 ldr r1, [pc, #36] ; (80103f8 ) - 80103d2: 68f8 ldr r0, [r7, #12] - 80103d4: f000 f814 bl 8010400 + 801282a: 2208 movs r2, #8 + 801282c: 4909 ldr r1, [pc, #36] ; (8012854 ) + 801282e: 68f8 ldr r0, [r7, #12] + 8012830: f000 f814 bl 801285c IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); - 80103d8: 2204 movs r2, #4 - 80103da: 4908 ldr r1, [pc, #32] ; (80103fc ) - 80103dc: 68b8 ldr r0, [r7, #8] - 80103de: f000 f80f bl 8010400 - } -} - 80103e2: bf00 nop - 80103e4: 3710 adds r7, #16 - 80103e6: 46bd mov sp, r7 - 80103e8: bd80 pop {r7, pc} - 80103ea: bf00 nop - 80103ec: 1fff7590 .word 0x1fff7590 - 80103f0: 1fff7594 .word 0x1fff7594 - 80103f4: 1fff7598 .word 0x1fff7598 - 80103f8: 20000132 .word 0x20000132 - 80103fc: 20000142 .word 0x20000142 - -08010400 : + 8012834: 2204 movs r2, #4 + 8012836: 4908 ldr r1, [pc, #32] ; (8012858 ) + 8012838: 68b8 ldr r0, [r7, #8] + 801283a: f000 f80f bl 801285c + } +} + 801283e: bf00 nop + 8012840: 3710 adds r7, #16 + 8012842: 46bd mov sp, r7 + 8012844: bd80 pop {r7, pc} + 8012846: bf00 nop + 8012848: 1fff7590 .word 0x1fff7590 + 801284c: 1fff7594 .word 0x1fff7594 + 8012850: 1fff7598 .word 0x1fff7598 + 8012854: 20000112 .word 0x20000112 + 8012858: 20000122 .word 0x20000122 + +0801285c : * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) { - 8010400: b480 push {r7} - 8010402: b087 sub sp, #28 - 8010404: af00 add r7, sp, #0 - 8010406: 60f8 str r0, [r7, #12] - 8010408: 60b9 str r1, [r7, #8] - 801040a: 4613 mov r3, r2 - 801040c: 71fb strb r3, [r7, #7] + 801285c: b480 push {r7} + 801285e: b087 sub sp, #28 + 8012860: af00 add r7, sp, #0 + 8012862: 60f8 str r0, [r7, #12] + 8012864: 60b9 str r1, [r7, #8] + 8012866: 4613 mov r3, r2 + 8012868: 71fb strb r3, [r7, #7] uint8_t idx = 0; - 801040e: 2300 movs r3, #0 - 8010410: 75fb strb r3, [r7, #23] + 801286a: 2300 movs r3, #0 + 801286c: 75fb strb r3, [r7, #23] for (idx = 0; idx < len; idx++) - 8010412: 2300 movs r3, #0 - 8010414: 75fb strb r3, [r7, #23] - 8010416: e027 b.n 8010468 + 801286e: 2300 movs r3, #0 + 8012870: 75fb strb r3, [r7, #23] + 8012872: e027 b.n 80128c4 { if (((value >> 28)) < 0xA) - 8010418: 68fb ldr r3, [r7, #12] - 801041a: 0f1b lsrs r3, r3, #28 - 801041c: 2b09 cmp r3, #9 - 801041e: d80b bhi.n 8010438 + 8012874: 68fb ldr r3, [r7, #12] + 8012876: 0f1b lsrs r3, r3, #28 + 8012878: 2b09 cmp r3, #9 + 801287a: d80b bhi.n 8012894 { pbuf[2 * idx] = (value >> 28) + '0'; - 8010420: 68fb ldr r3, [r7, #12] - 8010422: 0f1b lsrs r3, r3, #28 - 8010424: b2da uxtb r2, r3 - 8010426: 7dfb ldrb r3, [r7, #23] - 8010428: 005b lsls r3, r3, #1 - 801042a: 4619 mov r1, r3 - 801042c: 68bb ldr r3, [r7, #8] - 801042e: 440b add r3, r1 - 8010430: 3230 adds r2, #48 ; 0x30 - 8010432: b2d2 uxtb r2, r2 - 8010434: 701a strb r2, [r3, #0] - 8010436: e00a b.n 801044e + 801287c: 68fb ldr r3, [r7, #12] + 801287e: 0f1b lsrs r3, r3, #28 + 8012880: b2da uxtb r2, r3 + 8012882: 7dfb ldrb r3, [r7, #23] + 8012884: 005b lsls r3, r3, #1 + 8012886: 4619 mov r1, r3 + 8012888: 68bb ldr r3, [r7, #8] + 801288a: 440b add r3, r1 + 801288c: 3230 adds r2, #48 ; 0x30 + 801288e: b2d2 uxtb r2, r2 + 8012890: 701a strb r2, [r3, #0] + 8012892: e00a b.n 80128aa } else { pbuf[2 * idx] = (value >> 28) + 'A' - 10; - 8010438: 68fb ldr r3, [r7, #12] - 801043a: 0f1b lsrs r3, r3, #28 - 801043c: b2da uxtb r2, r3 - 801043e: 7dfb ldrb r3, [r7, #23] - 8010440: 005b lsls r3, r3, #1 - 8010442: 4619 mov r1, r3 - 8010444: 68bb ldr r3, [r7, #8] - 8010446: 440b add r3, r1 - 8010448: 3237 adds r2, #55 ; 0x37 - 801044a: b2d2 uxtb r2, r2 - 801044c: 701a strb r2, [r3, #0] + 8012894: 68fb ldr r3, [r7, #12] + 8012896: 0f1b lsrs r3, r3, #28 + 8012898: b2da uxtb r2, r3 + 801289a: 7dfb ldrb r3, [r7, #23] + 801289c: 005b lsls r3, r3, #1 + 801289e: 4619 mov r1, r3 + 80128a0: 68bb ldr r3, [r7, #8] + 80128a2: 440b add r3, r1 + 80128a4: 3237 adds r2, #55 ; 0x37 + 80128a6: b2d2 uxtb r2, r2 + 80128a8: 701a strb r2, [r3, #0] } value = value << 4; - 801044e: 68fb ldr r3, [r7, #12] - 8010450: 011b lsls r3, r3, #4 - 8010452: 60fb str r3, [r7, #12] + 80128aa: 68fb ldr r3, [r7, #12] + 80128ac: 011b lsls r3, r3, #4 + 80128ae: 60fb str r3, [r7, #12] pbuf[2 * idx + 1] = 0; - 8010454: 7dfb ldrb r3, [r7, #23] - 8010456: 005b lsls r3, r3, #1 - 8010458: 3301 adds r3, #1 - 801045a: 68ba ldr r2, [r7, #8] - 801045c: 4413 add r3, r2 - 801045e: 2200 movs r2, #0 - 8010460: 701a strb r2, [r3, #0] + 80128b0: 7dfb ldrb r3, [r7, #23] + 80128b2: 005b lsls r3, r3, #1 + 80128b4: 3301 adds r3, #1 + 80128b6: 68ba ldr r2, [r7, #8] + 80128b8: 4413 add r3, r2 + 80128ba: 2200 movs r2, #0 + 80128bc: 701a strb r2, [r3, #0] for (idx = 0; idx < len; idx++) - 8010462: 7dfb ldrb r3, [r7, #23] - 8010464: 3301 adds r3, #1 - 8010466: 75fb strb r3, [r7, #23] - 8010468: 7dfa ldrb r2, [r7, #23] - 801046a: 79fb ldrb r3, [r7, #7] - 801046c: 429a cmp r2, r3 - 801046e: d3d3 bcc.n 8010418 - } -} - 8010470: bf00 nop - 8010472: bf00 nop - 8010474: 371c adds r7, #28 - 8010476: 46bd mov sp, r7 - 8010478: f85d 7b04 ldr.w r7, [sp], #4 - 801047c: 4770 bx lr + 80128be: 7dfb ldrb r3, [r7, #23] + 80128c0: 3301 adds r3, #1 + 80128c2: 75fb strb r3, [r7, #23] + 80128c4: 7dfa ldrb r2, [r7, #23] + 80128c6: 79fb ldrb r3, [r7, #7] + 80128c8: 429a cmp r2, r3 + 80128ca: d3d3 bcc.n 8012874 + } +} + 80128cc: bf00 nop + 80128ce: bf00 nop + 80128d0: 371c adds r7, #28 + 80128d2: 46bd mov sp, r7 + 80128d4: f85d 7b04 ldr.w r7, [sp], #4 + 80128d8: 4770 bx lr ... -08010480 : +080128dc : LL Driver Callbacks (PCD -> USB Device Library) *******************************************************************************/ /* MSP Init */ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) { - 8010480: b580 push {r7, lr} - 8010482: b084 sub sp, #16 - 8010484: af00 add r7, sp, #0 - 8010486: 6078 str r0, [r7, #4] + 80128dc: b580 push {r7, lr} + 80128de: b084 sub sp, #16 + 80128e0: af00 add r7, sp, #0 + 80128e2: 6078 str r0, [r7, #4] if(pcdHandle->Instance==USB) - 8010488: 687b ldr r3, [r7, #4] - 801048a: 681b ldr r3, [r3, #0] - 801048c: 4a0d ldr r2, [pc, #52] ; (80104c4 ) - 801048e: 4293 cmp r3, r2 - 8010490: d113 bne.n 80104ba + 80128e4: 687b ldr r3, [r7, #4] + 80128e6: 681b ldr r3, [r3, #0] + 80128e8: 4a0d ldr r2, [pc, #52] ; (8012920 ) + 80128ea: 4293 cmp r3, r2 + 80128ec: d113 bne.n 8012916 { /* USER CODE BEGIN USB_MspInit 0 */ /* USER CODE END USB_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USB_CLK_ENABLE(); - 8010492: 4b0d ldr r3, [pc, #52] ; (80104c8 ) - 8010494: 6d9b ldr r3, [r3, #88] ; 0x58 - 8010496: 4a0c ldr r2, [pc, #48] ; (80104c8 ) - 8010498: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 - 801049c: 6593 str r3, [r2, #88] ; 0x58 - 801049e: 4b0a ldr r3, [pc, #40] ; (80104c8 ) - 80104a0: 6d9b ldr r3, [r3, #88] ; 0x58 - 80104a2: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 - 80104a6: 60fb str r3, [r7, #12] - 80104a8: 68fb ldr r3, [r7, #12] + 80128ee: 4b0d ldr r3, [pc, #52] ; (8012924 ) + 80128f0: 6d9b ldr r3, [r3, #88] ; 0x58 + 80128f2: 4a0c ldr r2, [pc, #48] ; (8012924 ) + 80128f4: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80128f8: 6593 str r3, [r2, #88] ; 0x58 + 80128fa: 4b0a ldr r3, [pc, #40] ; (8012924 ) + 80128fc: 6d9b ldr r3, [r3, #88] ; 0x58 + 80128fe: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8012902: 60fb str r3, [r7, #12] + 8012904: 68fb ldr r3, [r7, #12] /* Peripheral interrupt init */ HAL_NVIC_SetPriority(USB_IRQn, 0, 0); - 80104aa: 2200 movs r2, #0 - 80104ac: 2100 movs r1, #0 - 80104ae: 2043 movs r0, #67 ; 0x43 - 80104b0: f7f5 fc53 bl 8005d5a + 8012906: 2200 movs r2, #0 + 8012908: 2100 movs r1, #0 + 801290a: 2043 movs r0, #67 ; 0x43 + 801290c: f7f4 f84b bl 80069a6 HAL_NVIC_EnableIRQ(USB_IRQn); - 80104b4: 2043 movs r0, #67 ; 0x43 - 80104b6: f7f5 fc6c bl 8005d92 + 8012910: 2043 movs r0, #67 ; 0x43 + 8012912: f7f4 f864 bl 80069de /* USER CODE BEGIN USB_MspInit 1 */ /* USER CODE END USB_MspInit 1 */ } } - 80104ba: bf00 nop - 80104bc: 3710 adds r7, #16 - 80104be: 46bd mov sp, r7 - 80104c0: bd80 pop {r7, pc} - 80104c2: bf00 nop - 80104c4: 40006800 .word 0x40006800 - 80104c8: 40021000 .word 0x40021000 + 8012916: bf00 nop + 8012918: 3710 adds r7, #16 + 801291a: 46bd mov sp, r7 + 801291c: bd80 pop {r7, pc} + 801291e: bf00 nop + 8012920: 40006800 .word 0x40006800 + 8012924: 40021000 .word 0x40021000 -080104cc : +08012928 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 80104cc: b580 push {r7, lr} - 80104ce: b082 sub sp, #8 - 80104d0: af00 add r7, sp, #0 - 80104d2: 6078 str r0, [r7, #4] + 8012928: b580 push {r7, lr} + 801292a: b082 sub sp, #8 + 801292c: af00 add r7, sp, #0 + 801292e: 6078 str r0, [r7, #4] USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); - 80104d4: 687b ldr r3, [r7, #4] - 80104d6: f8d3 22f4 ldr.w r2, [r3, #756] ; 0x2f4 - 80104da: 687b ldr r3, [r7, #4] - 80104dc: f503 732c add.w r3, r3, #688 ; 0x2b0 - 80104e0: 4619 mov r1, r3 - 80104e2: 4610 mov r0, r2 - 80104e4: f7fe fcc3 bl 800ee6e -} - 80104e8: bf00 nop - 80104ea: 3708 adds r7, #8 - 80104ec: 46bd mov sp, r7 - 80104ee: bd80 pop {r7, pc} - -080104f0 : + 8012930: 687b ldr r3, [r7, #4] + 8012932: f8d3 22f4 ldr.w r2, [r3, #756] ; 0x2f4 + 8012936: 687b ldr r3, [r7, #4] + 8012938: f503 732c add.w r3, r3, #688 ; 0x2b0 + 801293c: 4619 mov r1, r3 + 801293e: 4610 mov r0, r2 + 8012940: f7fd fe93 bl 801066a +} + 8012944: bf00 nop + 8012946: 3708 adds r7, #8 + 8012948: 46bd mov sp, r7 + 801294a: bd80 pop {r7, pc} + +0801294c : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 80104f0: b580 push {r7, lr} - 80104f2: b082 sub sp, #8 - 80104f4: af00 add r7, sp, #0 - 80104f6: 6078 str r0, [r7, #4] - 80104f8: 460b mov r3, r1 - 80104fa: 70fb strb r3, [r7, #3] + 801294c: b580 push {r7, lr} + 801294e: b082 sub sp, #8 + 8012950: af00 add r7, sp, #0 + 8012952: 6078 str r0, [r7, #4] + 8012954: 460b mov r3, r1 + 8012956: 70fb strb r3, [r7, #3] USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); - 80104fc: 687b ldr r3, [r7, #4] - 80104fe: f8d3 02f4 ldr.w r0, [r3, #756] ; 0x2f4 - 8010502: 78fa ldrb r2, [r7, #3] - 8010504: 6879 ldr r1, [r7, #4] - 8010506: 4613 mov r3, r2 - 8010508: 009b lsls r3, r3, #2 - 801050a: 4413 add r3, r2 - 801050c: 00db lsls r3, r3, #3 - 801050e: 440b add r3, r1 - 8010510: f503 73be add.w r3, r3, #380 ; 0x17c - 8010514: 681a ldr r2, [r3, #0] - 8010516: 78fb ldrb r3, [r7, #3] - 8010518: 4619 mov r1, r3 - 801051a: f7fe fcfd bl 800ef18 -} - 801051e: bf00 nop - 8010520: 3708 adds r7, #8 - 8010522: 46bd mov sp, r7 - 8010524: bd80 pop {r7, pc} - -08010526 : + 8012958: 687b ldr r3, [r7, #4] + 801295a: f8d3 02f4 ldr.w r0, [r3, #756] ; 0x2f4 + 801295e: 78fa ldrb r2, [r7, #3] + 8012960: 6879 ldr r1, [r7, #4] + 8012962: 4613 mov r3, r2 + 8012964: 009b lsls r3, r3, #2 + 8012966: 4413 add r3, r2 + 8012968: 00db lsls r3, r3, #3 + 801296a: 440b add r3, r1 + 801296c: f503 73be add.w r3, r3, #380 ; 0x17c + 8012970: 681a ldr r2, [r3, #0] + 8012972: 78fb ldrb r3, [r7, #3] + 8012974: 4619 mov r1, r3 + 8012976: f7fd fecd bl 8010714 +} + 801297a: bf00 nop + 801297c: 3708 adds r7, #8 + 801297e: 46bd mov sp, r7 + 8012980: bd80 pop {r7, pc} + +08012982 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #else void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 8010526: b580 push {r7, lr} - 8010528: b082 sub sp, #8 - 801052a: af00 add r7, sp, #0 - 801052c: 6078 str r0, [r7, #4] - 801052e: 460b mov r3, r1 - 8010530: 70fb strb r3, [r7, #3] + 8012982: b580 push {r7, lr} + 8012984: b082 sub sp, #8 + 8012986: af00 add r7, sp, #0 + 8012988: 6078 str r0, [r7, #4] + 801298a: 460b mov r3, r1 + 801298c: 70fb strb r3, [r7, #3] USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); - 8010532: 687b ldr r3, [r7, #4] - 8010534: f8d3 02f4 ldr.w r0, [r3, #756] ; 0x2f4 - 8010538: 78fa ldrb r2, [r7, #3] - 801053a: 6879 ldr r1, [r7, #4] - 801053c: 4613 mov r3, r2 - 801053e: 009b lsls r3, r3, #2 - 8010540: 4413 add r3, r2 - 8010542: 00db lsls r3, r3, #3 - 8010544: 440b add r3, r1 - 8010546: 333c adds r3, #60 ; 0x3c - 8010548: 681a ldr r2, [r3, #0] - 801054a: 78fb ldrb r3, [r7, #3] - 801054c: 4619 mov r1, r3 - 801054e: f7fe fd96 bl 800f07e -} - 8010552: bf00 nop - 8010554: 3708 adds r7, #8 - 8010556: 46bd mov sp, r7 - 8010558: bd80 pop {r7, pc} - -0801055a : + 801298e: 687b ldr r3, [r7, #4] + 8012990: f8d3 02f4 ldr.w r0, [r3, #756] ; 0x2f4 + 8012994: 78fa ldrb r2, [r7, #3] + 8012996: 6879 ldr r1, [r7, #4] + 8012998: 4613 mov r3, r2 + 801299a: 009b lsls r3, r3, #2 + 801299c: 4413 add r3, r2 + 801299e: 00db lsls r3, r3, #3 + 80129a0: 440b add r3, r1 + 80129a2: 333c adds r3, #60 ; 0x3c + 80129a4: 681a ldr r2, [r3, #0] + 80129a6: 78fb ldrb r3, [r7, #3] + 80129a8: 4619 mov r1, r3 + 80129aa: f7fd ff66 bl 801087a +} + 80129ae: bf00 nop + 80129b0: 3708 adds r7, #8 + 80129b2: 46bd mov sp, r7 + 80129b4: bd80 pop {r7, pc} + +080129b6 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 801055a: b580 push {r7, lr} - 801055c: b082 sub sp, #8 - 801055e: af00 add r7, sp, #0 - 8010560: 6078 str r0, [r7, #4] + 80129b6: b580 push {r7, lr} + 80129b8: b082 sub sp, #8 + 80129ba: af00 add r7, sp, #0 + 80129bc: 6078 str r0, [r7, #4] USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); - 8010562: 687b ldr r3, [r7, #4] - 8010564: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 8010568: 4618 mov r0, r3 - 801056a: f7fe fed0 bl 800f30e + 80129be: 687b ldr r3, [r7, #4] + 80129c0: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 80129c4: 4618 mov r0, r3 + 80129c6: f7fe f8a0 bl 8010b0a } - 801056e: bf00 nop - 8010570: 3708 adds r7, #8 - 8010572: 46bd mov sp, r7 - 8010574: bd80 pop {r7, pc} + 80129ca: bf00 nop + 80129cc: 3708 adds r7, #8 + 80129ce: 46bd mov sp, r7 + 80129d0: bd80 pop {r7, pc} -08010576 : +080129d2 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 8010576: b580 push {r7, lr} - 8010578: b084 sub sp, #16 - 801057a: af00 add r7, sp, #0 - 801057c: 6078 str r0, [r7, #4] + 80129d2: b580 push {r7, lr} + 80129d4: b084 sub sp, #16 + 80129d6: af00 add r7, sp, #0 + 80129d8: 6078 str r0, [r7, #4] USBD_SpeedTypeDef speed = USBD_SPEED_FULL; - 801057e: 2301 movs r3, #1 - 8010580: 73fb strb r3, [r7, #15] + 80129da: 2301 movs r3, #1 + 80129dc: 73fb strb r3, [r7, #15] if ( hpcd->Init.speed != PCD_SPEED_FULL) - 8010582: 687b ldr r3, [r7, #4] - 8010584: 689b ldr r3, [r3, #8] - 8010586: 2b02 cmp r3, #2 - 8010588: d001 beq.n 801058e + 80129de: 687b ldr r3, [r7, #4] + 80129e0: 689b ldr r3, [r3, #8] + 80129e2: 2b02 cmp r3, #2 + 80129e4: d001 beq.n 80129ea { Error_Handler(); - 801058a: f7f1 f935 bl 80017f8 + 80129e6: f7ef f804 bl 80019f2 } /* Set Speed. */ USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); - 801058e: 687b ldr r3, [r7, #4] - 8010590: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 8010594: 7bfa ldrb r2, [r7, #15] - 8010596: 4611 mov r1, r2 - 8010598: 4618 mov r0, r3 - 801059a: f7fe fe74 bl 800f286 + 80129ea: 687b ldr r3, [r7, #4] + 80129ec: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 80129f0: 7bfa ldrb r2, [r7, #15] + 80129f2: 4611 mov r1, r2 + 80129f4: 4618 mov r0, r3 + 80129f6: f7fe f844 bl 8010a82 /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); - 801059e: 687b ldr r3, [r7, #4] - 80105a0: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 80105a4: 4618 mov r0, r3 - 80105a6: f7fe fe1c bl 800f1e2 -} - 80105aa: bf00 nop - 80105ac: 3710 adds r7, #16 - 80105ae: 46bd mov sp, r7 - 80105b0: bd80 pop {r7, pc} + 80129fa: 687b ldr r3, [r7, #4] + 80129fc: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 8012a00: 4618 mov r0, r3 + 8012a02: f7fd ffec bl 80109de +} + 8012a06: bf00 nop + 8012a08: 3710 adds r7, #16 + 8012a0a: 46bd mov sp, r7 + 8012a0c: bd80 pop {r7, pc} ... -080105b4 : +08012a10 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 80105b4: b580 push {r7, lr} - 80105b6: b082 sub sp, #8 - 80105b8: af00 add r7, sp, #0 - 80105ba: 6078 str r0, [r7, #4] + 8012a10: b580 push {r7, lr} + 8012a12: b082 sub sp, #8 + 8012a14: af00 add r7, sp, #0 + 8012a16: 6078 str r0, [r7, #4] /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); - 80105bc: 687b ldr r3, [r7, #4] - 80105be: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 80105c2: 4618 mov r0, r3 - 80105c4: f7fe fe6f bl 800f2a6 + 8012a18: 687b ldr r3, [r7, #4] + 8012a1a: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 8012a1e: 4618 mov r0, r3 + 8012a20: f7fe f83f bl 8010aa2 /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) - 80105c8: 687b ldr r3, [r7, #4] - 80105ca: 699b ldr r3, [r3, #24] - 80105cc: 2b00 cmp r3, #0 - 80105ce: d005 beq.n 80105dc + 8012a24: 687b ldr r3, [r7, #4] + 8012a26: 699b ldr r3, [r3, #24] + 8012a28: 2b00 cmp r3, #0 + 8012a2a: d005 beq.n 8012a38 { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - 80105d0: 4b04 ldr r3, [pc, #16] ; (80105e4 ) - 80105d2: 691b ldr r3, [r3, #16] - 80105d4: 4a03 ldr r2, [pc, #12] ; (80105e4 ) - 80105d6: f043 0306 orr.w r3, r3, #6 - 80105da: 6113 str r3, [r2, #16] + 8012a2c: 4b04 ldr r3, [pc, #16] ; (8012a40 ) + 8012a2e: 691b ldr r3, [r3, #16] + 8012a30: 4a03 ldr r2, [pc, #12] ; (8012a40 ) + 8012a32: f043 0306 orr.w r3, r3, #6 + 8012a36: 6113 str r3, [r2, #16] } /* USER CODE END 2 */ } - 80105dc: bf00 nop - 80105de: 3708 adds r7, #8 - 80105e0: 46bd mov sp, r7 - 80105e2: bd80 pop {r7, pc} - 80105e4: e000ed00 .word 0xe000ed00 + 8012a38: bf00 nop + 8012a3a: 3708 adds r7, #8 + 8012a3c: 46bd mov sp, r7 + 8012a3e: bd80 pop {r7, pc} + 8012a40: e000ed00 .word 0xe000ed00 -080105e8 : +08012a44 : #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - 80105e8: b580 push {r7, lr} - 80105ea: b082 sub sp, #8 - 80105ec: af00 add r7, sp, #0 - 80105ee: 6078 str r0, [r7, #4] + 8012a44: b580 push {r7, lr} + 8012a46: b082 sub sp, #8 + 8012a48: af00 add r7, sp, #0 + 8012a4a: 6078 str r0, [r7, #4] /* USER CODE BEGIN 3 */ if (hpcd->Init.low_power_enable) - 80105f0: 687b ldr r3, [r7, #4] - 80105f2: 699b ldr r3, [r3, #24] - 80105f4: 2b00 cmp r3, #0 - 80105f6: d007 beq.n 8010608 + 8012a4c: 687b ldr r3, [r7, #4] + 8012a4e: 699b ldr r3, [r3, #24] + 8012a50: 2b00 cmp r3, #0 + 8012a52: d007 beq.n 8012a64 { /* Reset SLEEPDEEP bit of Cortex System Control Register. */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - 80105f8: 4b08 ldr r3, [pc, #32] ; (801061c ) - 80105fa: 691b ldr r3, [r3, #16] - 80105fc: 4a07 ldr r2, [pc, #28] ; (801061c ) - 80105fe: f023 0306 bic.w r3, r3, #6 - 8010602: 6113 str r3, [r2, #16] + 8012a54: 4b08 ldr r3, [pc, #32] ; (8012a78 ) + 8012a56: 691b ldr r3, [r3, #16] + 8012a58: 4a07 ldr r2, [pc, #28] ; (8012a78 ) + 8012a5a: f023 0306 bic.w r3, r3, #6 + 8012a5e: 6113 str r3, [r2, #16] SystemClockConfig_Resume(); - 8010604: f000 fa90 bl 8010b28 + 8012a60: f000 fab6 bl 8012fd0 } /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); - 8010608: 687b ldr r3, [r7, #4] - 801060a: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 801060e: 4618 mov r0, r3 - 8010610: f7fe fe65 bl 800f2de -} - 8010614: bf00 nop - 8010616: 3708 adds r7, #8 - 8010618: 46bd mov sp, r7 - 801061a: bd80 pop {r7, pc} - 801061c: e000ed00 .word 0xe000ed00 - -08010620 : + 8012a64: 687b ldr r3, [r7, #4] + 8012a66: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 8012a6a: 4618 mov r0, r3 + 8012a6c: f7fe f835 bl 8010ada +} + 8012a70: bf00 nop + 8012a72: 3708 adds r7, #8 + 8012a74: 46bd mov sp, r7 + 8012a76: bd80 pop {r7, pc} + 8012a78: e000ed00 .word 0xe000ed00 + +08012a7c : * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { - 8010620: b580 push {r7, lr} - 8010622: b082 sub sp, #8 - 8010624: af00 add r7, sp, #0 - 8010626: 6078 str r0, [r7, #4] + 8012a7c: b580 push {r7, lr} + 8012a7e: b082 sub sp, #8 + 8012a80: af00 add r7, sp, #0 + 8012a82: 6078 str r0, [r7, #4] /* Init USB Ip. */ /* Enable USB power on Pwrctrl CR2 register. */ HAL_PWREx_EnableVddUSB(); - 8010628: f7f8 fbea bl 8008e00 + 8012a84: f7f6 fe90 bl 80097a8 /* Link the driver to the stack. */ hpcd_USB_FS.pData = pdev; - 801062c: 4a22 ldr r2, [pc, #136] ; (80106b8 ) - 801062e: 687b ldr r3, [r7, #4] - 8010630: f8c2 32f4 str.w r3, [r2, #756] ; 0x2f4 + 8012a88: 4a2b ldr r2, [pc, #172] ; (8012b38 ) + 8012a8a: 687b ldr r3, [r7, #4] + 8012a8c: f8c2 32f4 str.w r3, [r2, #756] ; 0x2f4 pdev->pData = &hpcd_USB_FS; - 8010634: 687b ldr r3, [r7, #4] - 8010636: 4a20 ldr r2, [pc, #128] ; (80106b8 ) - 8010638: f8c3 22c8 str.w r2, [r3, #712] ; 0x2c8 + 8012a90: 687b ldr r3, [r7, #4] + 8012a92: 4a29 ldr r2, [pc, #164] ; (8012b38 ) + 8012a94: f8c3 22c8 str.w r2, [r3, #712] ; 0x2c8 hpcd_USB_FS.Instance = USB; - 801063c: 4b1e ldr r3, [pc, #120] ; (80106b8 ) - 801063e: 4a1f ldr r2, [pc, #124] ; (80106bc ) - 8010640: 601a str r2, [r3, #0] + 8012a98: 4b27 ldr r3, [pc, #156] ; (8012b38 ) + 8012a9a: 4a28 ldr r2, [pc, #160] ; (8012b3c ) + 8012a9c: 601a str r2, [r3, #0] hpcd_USB_FS.Init.dev_endpoints = 8; - 8010642: 4b1d ldr r3, [pc, #116] ; (80106b8 ) - 8010644: 2208 movs r2, #8 - 8010646: 605a str r2, [r3, #4] + 8012a9e: 4b26 ldr r3, [pc, #152] ; (8012b38 ) + 8012aa0: 2208 movs r2, #8 + 8012aa2: 605a str r2, [r3, #4] hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; - 8010648: 4b1b ldr r3, [pc, #108] ; (80106b8 ) - 801064a: 2202 movs r2, #2 - 801064c: 609a str r2, [r3, #8] + 8012aa4: 4b24 ldr r3, [pc, #144] ; (8012b38 ) + 8012aa6: 2202 movs r2, #2 + 8012aa8: 609a str r2, [r3, #8] hpcd_USB_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - 801064e: 4b1a ldr r3, [pc, #104] ; (80106b8 ) - 8010650: 2202 movs r2, #2 - 8010652: 611a str r2, [r3, #16] + 8012aaa: 4b23 ldr r3, [pc, #140] ; (8012b38 ) + 8012aac: 2202 movs r2, #2 + 8012aae: 611a str r2, [r3, #16] hpcd_USB_FS.Init.Sof_enable = DISABLE; - 8010654: 4b18 ldr r3, [pc, #96] ; (80106b8 ) - 8010656: 2200 movs r2, #0 - 8010658: 615a str r2, [r3, #20] + 8012ab0: 4b21 ldr r3, [pc, #132] ; (8012b38 ) + 8012ab2: 2200 movs r2, #0 + 8012ab4: 615a str r2, [r3, #20] hpcd_USB_FS.Init.low_power_enable = DISABLE; - 801065a: 4b17 ldr r3, [pc, #92] ; (80106b8 ) - 801065c: 2200 movs r2, #0 - 801065e: 619a str r2, [r3, #24] + 8012ab6: 4b20 ldr r3, [pc, #128] ; (8012b38 ) + 8012ab8: 2200 movs r2, #0 + 8012aba: 619a str r2, [r3, #24] hpcd_USB_FS.Init.lpm_enable = DISABLE; - 8010660: 4b15 ldr r3, [pc, #84] ; (80106b8 ) - 8010662: 2200 movs r2, #0 - 8010664: 61da str r2, [r3, #28] + 8012abc: 4b1e ldr r3, [pc, #120] ; (8012b38 ) + 8012abe: 2200 movs r2, #0 + 8012ac0: 61da str r2, [r3, #28] hpcd_USB_FS.Init.battery_charging_enable = DISABLE; - 8010666: 4b14 ldr r3, [pc, #80] ; (80106b8 ) - 8010668: 2200 movs r2, #0 - 801066a: 621a str r2, [r3, #32] + 8012ac2: 4b1d ldr r3, [pc, #116] ; (8012b38 ) + 8012ac4: 2200 movs r2, #0 + 8012ac6: 621a str r2, [r3, #32] if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) - 801066c: 4812 ldr r0, [pc, #72] ; (80106b8 ) - 801066e: f7f6 fdfd bl 800726c - 8010672: 4603 mov r3, r0 - 8010674: 2b00 cmp r3, #0 - 8010676: d001 beq.n 801067c + 8012ac8: 481b ldr r0, [pc, #108] ; (8012b38 ) + 8012aca: f7f5 f88b bl 8007be4 + 8012ace: 4603 mov r3, r0 + 8012ad0: 2b00 cmp r3, #0 + 8012ad2: d001 beq.n 8012ad8 { Error_Handler( ); - 8010678: f7f1 f8be bl 80017f8 + 8012ad4: f7ee ff8d bl 80019f2 HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback); HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback); HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /* USER CODE BEGIN EndPoint_Configuration */ HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); - 801067c: 687b ldr r3, [r7, #4] - 801067e: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 8010682: 2318 movs r3, #24 - 8010684: 2200 movs r2, #0 - 8010686: 2100 movs r1, #0 - 8010688: f7f8 fae9 bl 8008c5e + 8012ad8: 687b ldr r3, [r7, #4] + 8012ada: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012ade: 2318 movs r3, #24 + 8012ae0: 2200 movs r2, #0 + 8012ae2: 2100 movs r1, #0 + 8012ae4: f7f6 fd8f bl 8009606 HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); - 801068c: 687b ldr r3, [r7, #4] - 801068e: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 8010692: 2358 movs r3, #88 ; 0x58 - 8010694: 2200 movs r2, #0 - 8010696: 2180 movs r1, #128 ; 0x80 - 8010698: f7f8 fae1 bl 8008c5e + 8012ae8: 687b ldr r3, [r7, #4] + 8012aea: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012aee: 2358 movs r3, #88 ; 0x58 + 8012af0: 2200 movs r2, #0 + 8012af2: 2180 movs r1, #128 ; 0x80 + 8012af4: f7f6 fd87 bl 8009606 /* USER CODE END EndPoint_Configuration */ - /* USER CODE BEGIN EndPoint_Configuration_HID */ - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0x100); - 801069c: 687b ldr r3, [r7, #4] - 801069e: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 80106a2: f44f 7380 mov.w r3, #256 ; 0x100 - 80106a6: 2200 movs r2, #0 - 80106a8: 2181 movs r1, #129 ; 0x81 - 80106aa: f7f8 fad8 bl 8008c5e - /* USER CODE END EndPoint_Configuration_HID */ + /* USER CODE BEGIN EndPoint_Configuration_CDC */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); + 8012af8: 687b ldr r3, [r7, #4] + 8012afa: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012afe: 23c0 movs r3, #192 ; 0xc0 + 8012b00: 2200 movs r2, #0 + 8012b02: 2181 movs r1, #129 ; 0x81 + 8012b04: f7f6 fd7f bl 8009606 + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); + 8012b08: 687b ldr r3, [r7, #4] + 8012b0a: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012b0e: f44f 7388 mov.w r3, #272 ; 0x110 + 8012b12: 2200 movs r2, #0 + 8012b14: 2101 movs r1, #1 + 8012b16: f7f6 fd76 bl 8009606 + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); + 8012b1a: 687b ldr r3, [r7, #4] + 8012b1c: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012b20: f44f 7380 mov.w r3, #256 ; 0x100 + 8012b24: 2200 movs r2, #0 + 8012b26: 2182 movs r1, #130 ; 0x82 + 8012b28: f7f6 fd6d bl 8009606 + /* USER CODE END EndPoint_Configuration_CDC */ return USBD_OK; - 80106ae: 2300 movs r3, #0 + 8012b2c: 2300 movs r3, #0 } - 80106b0: 4618 mov r0, r3 - 80106b2: 3708 adds r7, #8 - 80106b4: 46bd mov sp, r7 - 80106b6: bd80 pop {r7, pc} - 80106b8: 20001180 .word 0x20001180 - 80106bc: 40006800 .word 0x40006800 + 8012b2e: 4618 mov r0, r3 + 8012b30: 3708 adds r7, #8 + 8012b32: 46bd mov sp, r7 + 8012b34: bd80 pop {r7, pc} + 8012b36: bf00 nop + 8012b38: 20001d2c .word 0x20001d2c + 8012b3c: 40006800 .word 0x40006800 -080106c0 : +08012b40 : * @brief Starts the low level portion of the device driver. * @param pdev: Device handle * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { - 80106c0: b580 push {r7, lr} - 80106c2: b084 sub sp, #16 - 80106c4: af00 add r7, sp, #0 - 80106c6: 6078 str r0, [r7, #4] + 8012b40: b580 push {r7, lr} + 8012b42: b084 sub sp, #16 + 8012b44: af00 add r7, sp, #0 + 8012b46: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; - 80106c8: 2300 movs r3, #0 - 80106ca: 73bb strb r3, [r7, #14] + 8012b48: 2300 movs r3, #0 + 8012b4a: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 80106cc: 2300 movs r3, #0 - 80106ce: 73fb strb r3, [r7, #15] + 8012b4c: 2300 movs r3, #0 + 8012b4e: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_Start(pdev->pData); - 80106d0: 687b ldr r3, [r7, #4] - 80106d2: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 80106d6: 4618 mov r0, r3 - 80106d8: f7f6 fece bl 8007478 - 80106dc: 4603 mov r3, r0 - 80106de: 73bb strb r3, [r7, #14] + 8012b50: 687b ldr r3, [r7, #4] + 8012b52: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012b56: 4618 mov r0, r3 + 8012b58: f7f5 f94a bl 8007df0 + 8012b5c: 4603 mov r3, r0 + 8012b5e: 73bb strb r3, [r7, #14] switch (hal_status) { - 80106e0: 7bbb ldrb r3, [r7, #14] - 80106e2: 2b03 cmp r3, #3 - 80106e4: d816 bhi.n 8010714 - 80106e6: a201 add r2, pc, #4 ; (adr r2, 80106ec ) - 80106e8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80106ec: 080106fd .word 0x080106fd - 80106f0: 08010703 .word 0x08010703 - 80106f4: 08010709 .word 0x08010709 - 80106f8: 0801070f .word 0x0801070f + 8012b60: 7bbb ldrb r3, [r7, #14] + 8012b62: 2b03 cmp r3, #3 + 8012b64: d816 bhi.n 8012b94 + 8012b66: a201 add r2, pc, #4 ; (adr r2, 8012b6c ) + 8012b68: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012b6c: 08012b7d .word 0x08012b7d + 8012b70: 08012b83 .word 0x08012b83 + 8012b74: 08012b89 .word 0x08012b89 + 8012b78: 08012b8f .word 0x08012b8f case HAL_OK : usb_status = USBD_OK; - 80106fc: 2300 movs r3, #0 - 80106fe: 73fb strb r3, [r7, #15] + 8012b7c: 2300 movs r3, #0 + 8012b7e: 73fb strb r3, [r7, #15] break; - 8010700: e00b b.n 801071a + 8012b80: e00b b.n 8012b9a case HAL_ERROR : usb_status = USBD_FAIL; - 8010702: 2303 movs r3, #3 - 8010704: 73fb strb r3, [r7, #15] + 8012b82: 2303 movs r3, #3 + 8012b84: 73fb strb r3, [r7, #15] break; - 8010706: e008 b.n 801071a + 8012b86: e008 b.n 8012b9a case HAL_BUSY : usb_status = USBD_BUSY; - 8010708: 2301 movs r3, #1 - 801070a: 73fb strb r3, [r7, #15] + 8012b88: 2301 movs r3, #1 + 8012b8a: 73fb strb r3, [r7, #15] break; - 801070c: e005 b.n 801071a + 8012b8c: e005 b.n 8012b9a case HAL_TIMEOUT : usb_status = USBD_FAIL; - 801070e: 2303 movs r3, #3 - 8010710: 73fb strb r3, [r7, #15] + 8012b8e: 2303 movs r3, #3 + 8012b90: 73fb strb r3, [r7, #15] break; - 8010712: e002 b.n 801071a + 8012b92: e002 b.n 8012b9a default : usb_status = USBD_FAIL; - 8010714: 2303 movs r3, #3 - 8010716: 73fb strb r3, [r7, #15] + 8012b94: 2303 movs r3, #3 + 8012b96: 73fb strb r3, [r7, #15] break; - 8010718: bf00 nop + 8012b98: bf00 nop } return usb_status; - 801071a: 7bfb ldrb r3, [r7, #15] + 8012b9a: 7bfb ldrb r3, [r7, #15] } - 801071c: 4618 mov r0, r3 - 801071e: 3710 adds r7, #16 - 8010720: 46bd mov sp, r7 - 8010722: bd80 pop {r7, pc} + 8012b9c: 4618 mov r0, r3 + 8012b9e: 3710 adds r7, #16 + 8012ba0: 46bd mov sp, r7 + 8012ba2: bd80 pop {r7, pc} -08010724 : +08012ba4 : * @param ep_type: Endpoint type * @param ep_mps: Endpoint max packet size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { - 8010724: b580 push {r7, lr} - 8010726: b084 sub sp, #16 - 8010728: af00 add r7, sp, #0 - 801072a: 6078 str r0, [r7, #4] - 801072c: 4608 mov r0, r1 - 801072e: 4611 mov r1, r2 - 8010730: 461a mov r2, r3 - 8010732: 4603 mov r3, r0 - 8010734: 70fb strb r3, [r7, #3] - 8010736: 460b mov r3, r1 - 8010738: 70bb strb r3, [r7, #2] - 801073a: 4613 mov r3, r2 - 801073c: 803b strh r3, [r7, #0] + 8012ba4: b580 push {r7, lr} + 8012ba6: b084 sub sp, #16 + 8012ba8: af00 add r7, sp, #0 + 8012baa: 6078 str r0, [r7, #4] + 8012bac: 4608 mov r0, r1 + 8012bae: 4611 mov r1, r2 + 8012bb0: 461a mov r2, r3 + 8012bb2: 4603 mov r3, r0 + 8012bb4: 70fb strb r3, [r7, #3] + 8012bb6: 460b mov r3, r1 + 8012bb8: 70bb strb r3, [r7, #2] + 8012bba: 4613 mov r3, r2 + 8012bbc: 803b strh r3, [r7, #0] HAL_StatusTypeDef hal_status = HAL_OK; - 801073e: 2300 movs r3, #0 - 8010740: 73bb strb r3, [r7, #14] + 8012bbe: 2300 movs r3, #0 + 8012bc0: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 8010742: 2300 movs r3, #0 - 8010744: 73fb strb r3, [r7, #15] + 8012bc2: 2300 movs r3, #0 + 8012bc4: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); - 8010746: 687b ldr r3, [r7, #4] - 8010748: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 801074c: 78bb ldrb r3, [r7, #2] - 801074e: 883a ldrh r2, [r7, #0] - 8010750: 78f9 ldrb r1, [r7, #3] - 8010752: f7f6 ffff bl 8007754 - 8010756: 4603 mov r3, r0 - 8010758: 73bb strb r3, [r7, #14] + 8012bc6: 687b ldr r3, [r7, #4] + 8012bc8: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012bcc: 78bb ldrb r3, [r7, #2] + 8012bce: 883a ldrh r2, [r7, #0] + 8012bd0: 78f9 ldrb r1, [r7, #3] + 8012bd2: f7f5 fa7b bl 80080cc + 8012bd6: 4603 mov r3, r0 + 8012bd8: 73bb strb r3, [r7, #14] switch (hal_status) { - 801075a: 7bbb ldrb r3, [r7, #14] - 801075c: 2b03 cmp r3, #3 - 801075e: d817 bhi.n 8010790 - 8010760: a201 add r2, pc, #4 ; (adr r2, 8010768 ) - 8010762: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8010766: bf00 nop - 8010768: 08010779 .word 0x08010779 - 801076c: 0801077f .word 0x0801077f - 8010770: 08010785 .word 0x08010785 - 8010774: 0801078b .word 0x0801078b + 8012bda: 7bbb ldrb r3, [r7, #14] + 8012bdc: 2b03 cmp r3, #3 + 8012bde: d817 bhi.n 8012c10 + 8012be0: a201 add r2, pc, #4 ; (adr r2, 8012be8 ) + 8012be2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012be6: bf00 nop + 8012be8: 08012bf9 .word 0x08012bf9 + 8012bec: 08012bff .word 0x08012bff + 8012bf0: 08012c05 .word 0x08012c05 + 8012bf4: 08012c0b .word 0x08012c0b case HAL_OK : usb_status = USBD_OK; - 8010778: 2300 movs r3, #0 - 801077a: 73fb strb r3, [r7, #15] + 8012bf8: 2300 movs r3, #0 + 8012bfa: 73fb strb r3, [r7, #15] break; - 801077c: e00b b.n 8010796 + 8012bfc: e00b b.n 8012c16 case HAL_ERROR : usb_status = USBD_FAIL; - 801077e: 2303 movs r3, #3 - 8010780: 73fb strb r3, [r7, #15] + 8012bfe: 2303 movs r3, #3 + 8012c00: 73fb strb r3, [r7, #15] break; - 8010782: e008 b.n 8010796 + 8012c02: e008 b.n 8012c16 case HAL_BUSY : usb_status = USBD_BUSY; - 8010784: 2301 movs r3, #1 - 8010786: 73fb strb r3, [r7, #15] + 8012c04: 2301 movs r3, #1 + 8012c06: 73fb strb r3, [r7, #15] break; - 8010788: e005 b.n 8010796 + 8012c08: e005 b.n 8012c16 case HAL_TIMEOUT : usb_status = USBD_FAIL; - 801078a: 2303 movs r3, #3 - 801078c: 73fb strb r3, [r7, #15] + 8012c0a: 2303 movs r3, #3 + 8012c0c: 73fb strb r3, [r7, #15] break; - 801078e: e002 b.n 8010796 + 8012c0e: e002 b.n 8012c16 default : usb_status = USBD_FAIL; - 8010790: 2303 movs r3, #3 - 8010792: 73fb strb r3, [r7, #15] + 8012c10: 2303 movs r3, #3 + 8012c12: 73fb strb r3, [r7, #15] break; - 8010794: bf00 nop + 8012c14: bf00 nop } return usb_status; - 8010796: 7bfb ldrb r3, [r7, #15] + 8012c16: 7bfb ldrb r3, [r7, #15] } - 8010798: 4618 mov r0, r3 - 801079a: 3710 adds r7, #16 - 801079c: 46bd mov sp, r7 - 801079e: bd80 pop {r7, pc} + 8012c18: 4618 mov r0, r3 + 8012c1a: 3710 adds r7, #16 + 8012c1c: 46bd mov sp, r7 + 8012c1e: bd80 pop {r7, pc} -080107a0 : +08012c20 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { - 80107a0: b580 push {r7, lr} - 80107a2: b084 sub sp, #16 - 80107a4: af00 add r7, sp, #0 - 80107a6: 6078 str r0, [r7, #4] - 80107a8: 460b mov r3, r1 - 80107aa: 70fb strb r3, [r7, #3] + 8012c20: b580 push {r7, lr} + 8012c22: b084 sub sp, #16 + 8012c24: af00 add r7, sp, #0 + 8012c26: 6078 str r0, [r7, #4] + 8012c28: 460b mov r3, r1 + 8012c2a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; - 80107ac: 2300 movs r3, #0 - 80107ae: 73bb strb r3, [r7, #14] + 8012c2c: 2300 movs r3, #0 + 8012c2e: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 80107b0: 2300 movs r3, #0 - 80107b2: 73fb strb r3, [r7, #15] + 8012c30: 2300 movs r3, #0 + 8012c32: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - 80107b4: 687b ldr r3, [r7, #4] - 80107b6: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 80107ba: 78fa ldrb r2, [r7, #3] - 80107bc: 4611 mov r1, r2 - 80107be: 4618 mov r0, r3 - 80107c0: f7f7 f825 bl 800780e - 80107c4: 4603 mov r3, r0 - 80107c6: 73bb strb r3, [r7, #14] + 8012c34: 687b ldr r3, [r7, #4] + 8012c36: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012c3a: 78fa ldrb r2, [r7, #3] + 8012c3c: 4611 mov r1, r2 + 8012c3e: 4618 mov r0, r3 + 8012c40: f7f5 faa1 bl 8008186 + 8012c44: 4603 mov r3, r0 + 8012c46: 73bb strb r3, [r7, #14] switch (hal_status) { - 80107c8: 7bbb ldrb r3, [r7, #14] - 80107ca: 2b03 cmp r3, #3 - 80107cc: d816 bhi.n 80107fc - 80107ce: a201 add r2, pc, #4 ; (adr r2, 80107d4 ) - 80107d0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80107d4: 080107e5 .word 0x080107e5 - 80107d8: 080107eb .word 0x080107eb - 80107dc: 080107f1 .word 0x080107f1 - 80107e0: 080107f7 .word 0x080107f7 + 8012c48: 7bbb ldrb r3, [r7, #14] + 8012c4a: 2b03 cmp r3, #3 + 8012c4c: d816 bhi.n 8012c7c + 8012c4e: a201 add r2, pc, #4 ; (adr r2, 8012c54 ) + 8012c50: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012c54: 08012c65 .word 0x08012c65 + 8012c58: 08012c6b .word 0x08012c6b + 8012c5c: 08012c71 .word 0x08012c71 + 8012c60: 08012c77 .word 0x08012c77 case HAL_OK : usb_status = USBD_OK; - 80107e4: 2300 movs r3, #0 - 80107e6: 73fb strb r3, [r7, #15] + 8012c64: 2300 movs r3, #0 + 8012c66: 73fb strb r3, [r7, #15] break; - 80107e8: e00b b.n 8010802 + 8012c68: e00b b.n 8012c82 case HAL_ERROR : usb_status = USBD_FAIL; - 80107ea: 2303 movs r3, #3 - 80107ec: 73fb strb r3, [r7, #15] + 8012c6a: 2303 movs r3, #3 + 8012c6c: 73fb strb r3, [r7, #15] break; - 80107ee: e008 b.n 8010802 + 8012c6e: e008 b.n 8012c82 case HAL_BUSY : usb_status = USBD_BUSY; - 80107f0: 2301 movs r3, #1 - 80107f2: 73fb strb r3, [r7, #15] + 8012c70: 2301 movs r3, #1 + 8012c72: 73fb strb r3, [r7, #15] break; - 80107f4: e005 b.n 8010802 + 8012c74: e005 b.n 8012c82 case HAL_TIMEOUT : usb_status = USBD_FAIL; - 80107f6: 2303 movs r3, #3 - 80107f8: 73fb strb r3, [r7, #15] + 8012c76: 2303 movs r3, #3 + 8012c78: 73fb strb r3, [r7, #15] break; - 80107fa: e002 b.n 8010802 + 8012c7a: e002 b.n 8012c82 default : usb_status = USBD_FAIL; - 80107fc: 2303 movs r3, #3 - 80107fe: 73fb strb r3, [r7, #15] + 8012c7c: 2303 movs r3, #3 + 8012c7e: 73fb strb r3, [r7, #15] break; - 8010800: bf00 nop + 8012c80: bf00 nop } return usb_status; - 8010802: 7bfb ldrb r3, [r7, #15] + 8012c82: 7bfb ldrb r3, [r7, #15] } - 8010804: 4618 mov r0, r3 - 8010806: 3710 adds r7, #16 - 8010808: 46bd mov sp, r7 - 801080a: bd80 pop {r7, pc} + 8012c84: 4618 mov r0, r3 + 8012c86: 3710 adds r7, #16 + 8012c88: 46bd mov sp, r7 + 8012c8a: bd80 pop {r7, pc} -0801080c : +08012c8c : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { - 801080c: b580 push {r7, lr} - 801080e: b084 sub sp, #16 - 8010810: af00 add r7, sp, #0 - 8010812: 6078 str r0, [r7, #4] - 8010814: 460b mov r3, r1 - 8010816: 70fb strb r3, [r7, #3] + 8012c8c: b580 push {r7, lr} + 8012c8e: b084 sub sp, #16 + 8012c90: af00 add r7, sp, #0 + 8012c92: 6078 str r0, [r7, #4] + 8012c94: 460b mov r3, r1 + 8012c96: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; - 8010818: 2300 movs r3, #0 - 801081a: 73bb strb r3, [r7, #14] + 8012c98: 2300 movs r3, #0 + 8012c9a: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 801081c: 2300 movs r3, #0 - 801081e: 73fb strb r3, [r7, #15] + 8012c9c: 2300 movs r3, #0 + 8012c9e: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); - 8010820: 687b ldr r3, [r7, #4] - 8010822: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 8010826: 78fa ldrb r2, [r7, #3] - 8010828: 4611 mov r1, r2 - 801082a: 4618 mov r0, r3 - 801082c: f7f7 f89f bl 800796e - 8010830: 4603 mov r3, r0 - 8010832: 73bb strb r3, [r7, #14] + 8012ca0: 687b ldr r3, [r7, #4] + 8012ca2: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012ca6: 78fa ldrb r2, [r7, #3] + 8012ca8: 4611 mov r1, r2 + 8012caa: 4618 mov r0, r3 + 8012cac: f7f5 fb33 bl 8008316 + 8012cb0: 4603 mov r3, r0 + 8012cb2: 73bb strb r3, [r7, #14] switch (hal_status) { - 8010834: 7bbb ldrb r3, [r7, #14] - 8010836: 2b03 cmp r3, #3 - 8010838: d816 bhi.n 8010868 - 801083a: a201 add r2, pc, #4 ; (adr r2, 8010840 ) - 801083c: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8010840: 08010851 .word 0x08010851 - 8010844: 08010857 .word 0x08010857 - 8010848: 0801085d .word 0x0801085d - 801084c: 08010863 .word 0x08010863 + 8012cb4: 7bbb ldrb r3, [r7, #14] + 8012cb6: 2b03 cmp r3, #3 + 8012cb8: d816 bhi.n 8012ce8 + 8012cba: a201 add r2, pc, #4 ; (adr r2, 8012cc0 ) + 8012cbc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012cc0: 08012cd1 .word 0x08012cd1 + 8012cc4: 08012cd7 .word 0x08012cd7 + 8012cc8: 08012cdd .word 0x08012cdd + 8012ccc: 08012ce3 .word 0x08012ce3 case HAL_OK : usb_status = USBD_OK; - 8010850: 2300 movs r3, #0 - 8010852: 73fb strb r3, [r7, #15] + 8012cd0: 2300 movs r3, #0 + 8012cd2: 73fb strb r3, [r7, #15] break; - 8010854: e00b b.n 801086e + 8012cd4: e00b b.n 8012cee case HAL_ERROR : usb_status = USBD_FAIL; - 8010856: 2303 movs r3, #3 - 8010858: 73fb strb r3, [r7, #15] + 8012cd6: 2303 movs r3, #3 + 8012cd8: 73fb strb r3, [r7, #15] break; - 801085a: e008 b.n 801086e + 8012cda: e008 b.n 8012cee case HAL_BUSY : usb_status = USBD_BUSY; - 801085c: 2301 movs r3, #1 - 801085e: 73fb strb r3, [r7, #15] + 8012cdc: 2301 movs r3, #1 + 8012cde: 73fb strb r3, [r7, #15] break; - 8010860: e005 b.n 801086e + 8012ce0: e005 b.n 8012cee case HAL_TIMEOUT : usb_status = USBD_FAIL; - 8010862: 2303 movs r3, #3 - 8010864: 73fb strb r3, [r7, #15] + 8012ce2: 2303 movs r3, #3 + 8012ce4: 73fb strb r3, [r7, #15] break; - 8010866: e002 b.n 801086e + 8012ce6: e002 b.n 8012cee default : usb_status = USBD_FAIL; - 8010868: 2303 movs r3, #3 - 801086a: 73fb strb r3, [r7, #15] + 8012ce8: 2303 movs r3, #3 + 8012cea: 73fb strb r3, [r7, #15] break; - 801086c: bf00 nop + 8012cec: bf00 nop } return usb_status; - 801086e: 7bfb ldrb r3, [r7, #15] + 8012cee: 7bfb ldrb r3, [r7, #15] } - 8010870: 4618 mov r0, r3 - 8010872: 3710 adds r7, #16 - 8010874: 46bd mov sp, r7 - 8010876: bd80 pop {r7, pc} + 8012cf0: 4618 mov r0, r3 + 8012cf2: 3710 adds r7, #16 + 8012cf4: 46bd mov sp, r7 + 8012cf6: bd80 pop {r7, pc} -08010878 : +08012cf8 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval USBD status */ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { - 8010878: b580 push {r7, lr} - 801087a: b084 sub sp, #16 - 801087c: af00 add r7, sp, #0 - 801087e: 6078 str r0, [r7, #4] - 8010880: 460b mov r3, r1 - 8010882: 70fb strb r3, [r7, #3] + 8012cf8: b580 push {r7, lr} + 8012cfa: b084 sub sp, #16 + 8012cfc: af00 add r7, sp, #0 + 8012cfe: 6078 str r0, [r7, #4] + 8012d00: 460b mov r3, r1 + 8012d02: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; - 8010884: 2300 movs r3, #0 - 8010886: 73bb strb r3, [r7, #14] + 8012d04: 2300 movs r3, #0 + 8012d06: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 8010888: 2300 movs r3, #0 - 801088a: 73fb strb r3, [r7, #15] + 8012d08: 2300 movs r3, #0 + 8012d0a: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - 801088c: 687b ldr r3, [r7, #4] - 801088e: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 8010892: 78fa ldrb r2, [r7, #3] - 8010894: 4611 mov r1, r2 - 8010896: 4618 mov r0, r3 - 8010898: f7f7 f8c9 bl 8007a2e - 801089c: 4603 mov r3, r0 - 801089e: 73bb strb r3, [r7, #14] + 8012d0c: 687b ldr r3, [r7, #4] + 8012d0e: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012d12: 78fa ldrb r2, [r7, #3] + 8012d14: 4611 mov r1, r2 + 8012d16: 4618 mov r0, r3 + 8012d18: f7f5 fb5d bl 80083d6 + 8012d1c: 4603 mov r3, r0 + 8012d1e: 73bb strb r3, [r7, #14] switch (hal_status) { - 80108a0: 7bbb ldrb r3, [r7, #14] - 80108a2: 2b03 cmp r3, #3 - 80108a4: d816 bhi.n 80108d4 - 80108a6: a201 add r2, pc, #4 ; (adr r2, 80108ac ) - 80108a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80108ac: 080108bd .word 0x080108bd - 80108b0: 080108c3 .word 0x080108c3 - 80108b4: 080108c9 .word 0x080108c9 - 80108b8: 080108cf .word 0x080108cf + 8012d20: 7bbb ldrb r3, [r7, #14] + 8012d22: 2b03 cmp r3, #3 + 8012d24: d816 bhi.n 8012d54 + 8012d26: a201 add r2, pc, #4 ; (adr r2, 8012d2c ) + 8012d28: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012d2c: 08012d3d .word 0x08012d3d + 8012d30: 08012d43 .word 0x08012d43 + 8012d34: 08012d49 .word 0x08012d49 + 8012d38: 08012d4f .word 0x08012d4f case HAL_OK : usb_status = USBD_OK; - 80108bc: 2300 movs r3, #0 - 80108be: 73fb strb r3, [r7, #15] + 8012d3c: 2300 movs r3, #0 + 8012d3e: 73fb strb r3, [r7, #15] break; - 80108c0: e00b b.n 80108da + 8012d40: e00b b.n 8012d5a case HAL_ERROR : usb_status = USBD_FAIL; - 80108c2: 2303 movs r3, #3 - 80108c4: 73fb strb r3, [r7, #15] + 8012d42: 2303 movs r3, #3 + 8012d44: 73fb strb r3, [r7, #15] break; - 80108c6: e008 b.n 80108da + 8012d46: e008 b.n 8012d5a case HAL_BUSY : usb_status = USBD_BUSY; - 80108c8: 2301 movs r3, #1 - 80108ca: 73fb strb r3, [r7, #15] + 8012d48: 2301 movs r3, #1 + 8012d4a: 73fb strb r3, [r7, #15] break; - 80108cc: e005 b.n 80108da + 8012d4c: e005 b.n 8012d5a case HAL_TIMEOUT : usb_status = USBD_FAIL; - 80108ce: 2303 movs r3, #3 - 80108d0: 73fb strb r3, [r7, #15] + 8012d4e: 2303 movs r3, #3 + 8012d50: 73fb strb r3, [r7, #15] break; - 80108d2: e002 b.n 80108da + 8012d52: e002 b.n 8012d5a default : usb_status = USBD_FAIL; - 80108d4: 2303 movs r3, #3 - 80108d6: 73fb strb r3, [r7, #15] + 8012d54: 2303 movs r3, #3 + 8012d56: 73fb strb r3, [r7, #15] break; - 80108d8: bf00 nop + 8012d58: bf00 nop } return usb_status; - 80108da: 7bfb ldrb r3, [r7, #15] + 8012d5a: 7bfb ldrb r3, [r7, #15] } - 80108dc: 4618 mov r0, r3 - 80108de: 3710 adds r7, #16 - 80108e0: 46bd mov sp, r7 - 80108e2: bd80 pop {r7, pc} + 8012d5c: 4618 mov r0, r3 + 8012d5e: 3710 adds r7, #16 + 8012d60: 46bd mov sp, r7 + 8012d62: bd80 pop {r7, pc} -080108e4 : +08012d64 : * @param pdev: Device handle * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { - 80108e4: b480 push {r7} - 80108e6: b085 sub sp, #20 - 80108e8: af00 add r7, sp, #0 - 80108ea: 6078 str r0, [r7, #4] - 80108ec: 460b mov r3, r1 - 80108ee: 70fb strb r3, [r7, #3] + 8012d64: b480 push {r7} + 8012d66: b085 sub sp, #20 + 8012d68: af00 add r7, sp, #0 + 8012d6a: 6078 str r0, [r7, #4] + 8012d6c: 460b mov r3, r1 + 8012d6e: 70fb strb r3, [r7, #3] PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - 80108f0: 687b ldr r3, [r7, #4] - 80108f2: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 80108f6: 60fb str r3, [r7, #12] + 8012d70: 687b ldr r3, [r7, #4] + 8012d72: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012d76: 60fb str r3, [r7, #12] if((ep_addr & 0x80) == 0x80) - 80108f8: f997 3003 ldrsb.w r3, [r7, #3] - 80108fc: 2b00 cmp r3, #0 - 80108fe: da0c bge.n 801091a + 8012d78: f997 3003 ldrsb.w r3, [r7, #3] + 8012d7c: 2b00 cmp r3, #0 + 8012d7e: da0c bge.n 8012d9a { return hpcd->IN_ep[ep_addr & 0x7F].is_stall; - 8010900: 78fb ldrb r3, [r7, #3] - 8010902: f003 037f and.w r3, r3, #127 ; 0x7f - 8010906: 68f9 ldr r1, [r7, #12] - 8010908: 1c5a adds r2, r3, #1 - 801090a: 4613 mov r3, r2 - 801090c: 009b lsls r3, r3, #2 - 801090e: 4413 add r3, r2 - 8010910: 00db lsls r3, r3, #3 - 8010912: 440b add r3, r1 - 8010914: 3302 adds r3, #2 - 8010916: 781b ldrb r3, [r3, #0] - 8010918: e00b b.n 8010932 + 8012d80: 78fb ldrb r3, [r7, #3] + 8012d82: f003 037f and.w r3, r3, #127 ; 0x7f + 8012d86: 68f9 ldr r1, [r7, #12] + 8012d88: 1c5a adds r2, r3, #1 + 8012d8a: 4613 mov r3, r2 + 8012d8c: 009b lsls r3, r3, #2 + 8012d8e: 4413 add r3, r2 + 8012d90: 00db lsls r3, r3, #3 + 8012d92: 440b add r3, r1 + 8012d94: 3302 adds r3, #2 + 8012d96: 781b ldrb r3, [r3, #0] + 8012d98: e00b b.n 8012db2 } else { return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; - 801091a: 78fb ldrb r3, [r7, #3] - 801091c: f003 027f and.w r2, r3, #127 ; 0x7f - 8010920: 68f9 ldr r1, [r7, #12] - 8010922: 4613 mov r3, r2 - 8010924: 009b lsls r3, r3, #2 - 8010926: 4413 add r3, r2 - 8010928: 00db lsls r3, r3, #3 - 801092a: 440b add r3, r1 - 801092c: f503 73b5 add.w r3, r3, #362 ; 0x16a - 8010930: 781b ldrb r3, [r3, #0] - } -} - 8010932: 4618 mov r0, r3 - 8010934: 3714 adds r7, #20 - 8010936: 46bd mov sp, r7 - 8010938: f85d 7b04 ldr.w r7, [sp], #4 - 801093c: 4770 bx lr + 8012d9a: 78fb ldrb r3, [r7, #3] + 8012d9c: f003 027f and.w r2, r3, #127 ; 0x7f + 8012da0: 68f9 ldr r1, [r7, #12] + 8012da2: 4613 mov r3, r2 + 8012da4: 009b lsls r3, r3, #2 + 8012da6: 4413 add r3, r2 + 8012da8: 00db lsls r3, r3, #3 + 8012daa: 440b add r3, r1 + 8012dac: f503 73b5 add.w r3, r3, #362 ; 0x16a + 8012db0: 781b ldrb r3, [r3, #0] + } +} + 8012db2: 4618 mov r0, r3 + 8012db4: 3714 adds r7, #20 + 8012db6: 46bd mov sp, r7 + 8012db8: f85d 7b04 ldr.w r7, [sp], #4 + 8012dbc: 4770 bx lr ... -08010940 : +08012dc0 : * @param pdev: Device handle * @param dev_addr: Device address * @retval USBD status */ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { - 8010940: b580 push {r7, lr} - 8010942: b084 sub sp, #16 - 8010944: af00 add r7, sp, #0 - 8010946: 6078 str r0, [r7, #4] - 8010948: 460b mov r3, r1 - 801094a: 70fb strb r3, [r7, #3] + 8012dc0: b580 push {r7, lr} + 8012dc2: b084 sub sp, #16 + 8012dc4: af00 add r7, sp, #0 + 8012dc6: 6078 str r0, [r7, #4] + 8012dc8: 460b mov r3, r1 + 8012dca: 70fb strb r3, [r7, #3] HAL_StatusTypeDef hal_status = HAL_OK; - 801094c: 2300 movs r3, #0 - 801094e: 73bb strb r3, [r7, #14] + 8012dcc: 2300 movs r3, #0 + 8012dce: 73bb strb r3, [r7, #14] USBD_StatusTypeDef usb_status = USBD_OK; - 8010950: 2300 movs r3, #0 - 8010952: 73fb strb r3, [r7, #15] + 8012dd0: 2300 movs r3, #0 + 8012dd2: 73fb strb r3, [r7, #15] hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - 8010954: 687b ldr r3, [r7, #4] - 8010956: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 - 801095a: 78fa ldrb r2, [r7, #3] - 801095c: 4611 mov r1, r2 - 801095e: 4618 mov r0, r3 - 8010960: f7f6 fed3 bl 800770a - 8010964: 4603 mov r3, r0 - 8010966: 73bb strb r3, [r7, #14] + 8012dd4: 687b ldr r3, [r7, #4] + 8012dd6: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012dda: 78fa ldrb r2, [r7, #3] + 8012ddc: 4611 mov r1, r2 + 8012dde: 4618 mov r0, r3 + 8012de0: f7f5 f94f bl 8008082 + 8012de4: 4603 mov r3, r0 + 8012de6: 73bb strb r3, [r7, #14] switch (hal_status) { - 8010968: 7bbb ldrb r3, [r7, #14] - 801096a: 2b03 cmp r3, #3 - 801096c: d816 bhi.n 801099c - 801096e: a201 add r2, pc, #4 ; (adr r2, 8010974 ) - 8010970: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8010974: 08010985 .word 0x08010985 - 8010978: 0801098b .word 0x0801098b - 801097c: 08010991 .word 0x08010991 - 8010980: 08010997 .word 0x08010997 + 8012de8: 7bbb ldrb r3, [r7, #14] + 8012dea: 2b03 cmp r3, #3 + 8012dec: d816 bhi.n 8012e1c + 8012dee: a201 add r2, pc, #4 ; (adr r2, 8012df4 ) + 8012df0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012df4: 08012e05 .word 0x08012e05 + 8012df8: 08012e0b .word 0x08012e0b + 8012dfc: 08012e11 .word 0x08012e11 + 8012e00: 08012e17 .word 0x08012e17 case HAL_OK : usb_status = USBD_OK; - 8010984: 2300 movs r3, #0 - 8010986: 73fb strb r3, [r7, #15] + 8012e04: 2300 movs r3, #0 + 8012e06: 73fb strb r3, [r7, #15] break; - 8010988: e00b b.n 80109a2 + 8012e08: e00b b.n 8012e22 case HAL_ERROR : usb_status = USBD_FAIL; - 801098a: 2303 movs r3, #3 - 801098c: 73fb strb r3, [r7, #15] + 8012e0a: 2303 movs r3, #3 + 8012e0c: 73fb strb r3, [r7, #15] break; - 801098e: e008 b.n 80109a2 + 8012e0e: e008 b.n 8012e22 case HAL_BUSY : usb_status = USBD_BUSY; - 8010990: 2301 movs r3, #1 - 8010992: 73fb strb r3, [r7, #15] + 8012e10: 2301 movs r3, #1 + 8012e12: 73fb strb r3, [r7, #15] break; - 8010994: e005 b.n 80109a2 + 8012e14: e005 b.n 8012e22 case HAL_TIMEOUT : usb_status = USBD_FAIL; - 8010996: 2303 movs r3, #3 - 8010998: 73fb strb r3, [r7, #15] + 8012e16: 2303 movs r3, #3 + 8012e18: 73fb strb r3, [r7, #15] break; - 801099a: e002 b.n 80109a2 + 8012e1a: e002 b.n 8012e22 default : usb_status = USBD_FAIL; - 801099c: 2303 movs r3, #3 - 801099e: 73fb strb r3, [r7, #15] + 8012e1c: 2303 movs r3, #3 + 8012e1e: 73fb strb r3, [r7, #15] break; - 80109a0: bf00 nop + 8012e20: bf00 nop } return usb_status; - 80109a2: 7bfb ldrb r3, [r7, #15] + 8012e22: 7bfb ldrb r3, [r7, #15] } - 80109a4: 4618 mov r0, r3 - 80109a6: 3710 adds r7, #16 - 80109a8: 46bd mov sp, r7 - 80109aa: bd80 pop {r7, pc} + 8012e24: 4618 mov r0, r3 + 8012e26: 3710 adds r7, #16 + 8012e28: 46bd mov sp, r7 + 8012e2a: bd80 pop {r7, pc} -080109ac : +08012e2c : * @param pbuf: Pointer to data to be sent * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { - 80109ac: b580 push {r7, lr} - 80109ae: b086 sub sp, #24 - 80109b0: af00 add r7, sp, #0 - 80109b2: 60f8 str r0, [r7, #12] - 80109b4: 607a str r2, [r7, #4] - 80109b6: 603b str r3, [r7, #0] - 80109b8: 460b mov r3, r1 - 80109ba: 72fb strb r3, [r7, #11] + 8012e2c: b580 push {r7, lr} + 8012e2e: b086 sub sp, #24 + 8012e30: af00 add r7, sp, #0 + 8012e32: 60f8 str r0, [r7, #12] + 8012e34: 607a str r2, [r7, #4] + 8012e36: 603b str r3, [r7, #0] + 8012e38: 460b mov r3, r1 + 8012e3a: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; - 80109bc: 2300 movs r3, #0 - 80109be: 75bb strb r3, [r7, #22] + 8012e3c: 2300 movs r3, #0 + 8012e3e: 75bb strb r3, [r7, #22] USBD_StatusTypeDef usb_status = USBD_OK; - 80109c0: 2300 movs r3, #0 - 80109c2: 75fb strb r3, [r7, #23] + 8012e40: 2300 movs r3, #0 + 8012e42: 75fb strb r3, [r7, #23] hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - 80109c4: 68fb ldr r3, [r7, #12] - 80109c6: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 80109ca: 7af9 ldrb r1, [r7, #11] - 80109cc: 683b ldr r3, [r7, #0] - 80109ce: 687a ldr r2, [r7, #4] - 80109d0: f7f6 ff96 bl 8007900 - 80109d4: 4603 mov r3, r0 - 80109d6: 75bb strb r3, [r7, #22] + 8012e44: 68fb ldr r3, [r7, #12] + 8012e46: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012e4a: 7af9 ldrb r1, [r7, #11] + 8012e4c: 683b ldr r3, [r7, #0] + 8012e4e: 687a ldr r2, [r7, #4] + 8012e50: f7f5 fa2a bl 80082a8 + 8012e54: 4603 mov r3, r0 + 8012e56: 75bb strb r3, [r7, #22] switch (hal_status) { - 80109d8: 7dbb ldrb r3, [r7, #22] - 80109da: 2b03 cmp r3, #3 - 80109dc: d816 bhi.n 8010a0c - 80109de: a201 add r2, pc, #4 ; (adr r2, 80109e4 ) - 80109e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80109e4: 080109f5 .word 0x080109f5 - 80109e8: 080109fb .word 0x080109fb - 80109ec: 08010a01 .word 0x08010a01 - 80109f0: 08010a07 .word 0x08010a07 + 8012e58: 7dbb ldrb r3, [r7, #22] + 8012e5a: 2b03 cmp r3, #3 + 8012e5c: d816 bhi.n 8012e8c + 8012e5e: a201 add r2, pc, #4 ; (adr r2, 8012e64 ) + 8012e60: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012e64: 08012e75 .word 0x08012e75 + 8012e68: 08012e7b .word 0x08012e7b + 8012e6c: 08012e81 .word 0x08012e81 + 8012e70: 08012e87 .word 0x08012e87 case HAL_OK : usb_status = USBD_OK; - 80109f4: 2300 movs r3, #0 - 80109f6: 75fb strb r3, [r7, #23] + 8012e74: 2300 movs r3, #0 + 8012e76: 75fb strb r3, [r7, #23] break; - 80109f8: e00b b.n 8010a12 + 8012e78: e00b b.n 8012e92 case HAL_ERROR : usb_status = USBD_FAIL; - 80109fa: 2303 movs r3, #3 - 80109fc: 75fb strb r3, [r7, #23] + 8012e7a: 2303 movs r3, #3 + 8012e7c: 75fb strb r3, [r7, #23] break; - 80109fe: e008 b.n 8010a12 + 8012e7e: e008 b.n 8012e92 case HAL_BUSY : usb_status = USBD_BUSY; - 8010a00: 2301 movs r3, #1 - 8010a02: 75fb strb r3, [r7, #23] + 8012e80: 2301 movs r3, #1 + 8012e82: 75fb strb r3, [r7, #23] break; - 8010a04: e005 b.n 8010a12 + 8012e84: e005 b.n 8012e92 case HAL_TIMEOUT : usb_status = USBD_FAIL; - 8010a06: 2303 movs r3, #3 - 8010a08: 75fb strb r3, [r7, #23] + 8012e86: 2303 movs r3, #3 + 8012e88: 75fb strb r3, [r7, #23] break; - 8010a0a: e002 b.n 8010a12 + 8012e8a: e002 b.n 8012e92 default : usb_status = USBD_FAIL; - 8010a0c: 2303 movs r3, #3 - 8010a0e: 75fb strb r3, [r7, #23] + 8012e8c: 2303 movs r3, #3 + 8012e8e: 75fb strb r3, [r7, #23] break; - 8010a10: bf00 nop + 8012e90: bf00 nop } return usb_status; - 8010a12: 7dfb ldrb r3, [r7, #23] + 8012e92: 7dfb ldrb r3, [r7, #23] } - 8010a14: 4618 mov r0, r3 - 8010a16: 3718 adds r7, #24 - 8010a18: 46bd mov sp, r7 - 8010a1a: bd80 pop {r7, pc} + 8012e94: 4618 mov r0, r3 + 8012e96: 3718 adds r7, #24 + 8012e98: 46bd mov sp, r7 + 8012e9a: bd80 pop {r7, pc} -08010a1c : +08012e9c : * @param pbuf: Pointer to data to be received * @param size: Data size * @retval USBD status */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { - 8010a1c: b580 push {r7, lr} - 8010a1e: b086 sub sp, #24 - 8010a20: af00 add r7, sp, #0 - 8010a22: 60f8 str r0, [r7, #12] - 8010a24: 607a str r2, [r7, #4] - 8010a26: 603b str r3, [r7, #0] - 8010a28: 460b mov r3, r1 - 8010a2a: 72fb strb r3, [r7, #11] + 8012e9c: b580 push {r7, lr} + 8012e9e: b086 sub sp, #24 + 8012ea0: af00 add r7, sp, #0 + 8012ea2: 60f8 str r0, [r7, #12] + 8012ea4: 607a str r2, [r7, #4] + 8012ea6: 603b str r3, [r7, #0] + 8012ea8: 460b mov r3, r1 + 8012eaa: 72fb strb r3, [r7, #11] HAL_StatusTypeDef hal_status = HAL_OK; - 8010a2c: 2300 movs r3, #0 - 8010a2e: 75bb strb r3, [r7, #22] + 8012eac: 2300 movs r3, #0 + 8012eae: 75bb strb r3, [r7, #22] USBD_StatusTypeDef usb_status = USBD_OK; - 8010a30: 2300 movs r3, #0 - 8010a32: 75fb strb r3, [r7, #23] + 8012eb0: 2300 movs r3, #0 + 8012eb2: 75fb strb r3, [r7, #23] hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - 8010a34: 68fb ldr r3, [r7, #12] - 8010a36: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 - 8010a3a: 7af9 ldrb r1, [r7, #11] - 8010a3c: 683b ldr r3, [r7, #0] - 8010a3e: 687a ldr r2, [r7, #4] - 8010a40: f7f6 ff2d bl 800789e - 8010a44: 4603 mov r3, r0 - 8010a46: 75bb strb r3, [r7, #22] + 8012eb4: 68fb ldr r3, [r7, #12] + 8012eb6: f8d3 02c8 ldr.w r0, [r3, #712] ; 0x2c8 + 8012eba: 7af9 ldrb r1, [r7, #11] + 8012ebc: 683b ldr r3, [r7, #0] + 8012ebe: 687a ldr r2, [r7, #4] + 8012ec0: f7f5 f9a9 bl 8008216 + 8012ec4: 4603 mov r3, r0 + 8012ec6: 75bb strb r3, [r7, #22] switch (hal_status) { - 8010a48: 7dbb ldrb r3, [r7, #22] - 8010a4a: 2b03 cmp r3, #3 - 8010a4c: d816 bhi.n 8010a7c - 8010a4e: a201 add r2, pc, #4 ; (adr r2, 8010a54 ) - 8010a50: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8010a54: 08010a65 .word 0x08010a65 - 8010a58: 08010a6b .word 0x08010a6b - 8010a5c: 08010a71 .word 0x08010a71 - 8010a60: 08010a77 .word 0x08010a77 + 8012ec8: 7dbb ldrb r3, [r7, #22] + 8012eca: 2b03 cmp r3, #3 + 8012ecc: d816 bhi.n 8012efc + 8012ece: a201 add r2, pc, #4 ; (adr r2, 8012ed4 ) + 8012ed0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8012ed4: 08012ee5 .word 0x08012ee5 + 8012ed8: 08012eeb .word 0x08012eeb + 8012edc: 08012ef1 .word 0x08012ef1 + 8012ee0: 08012ef7 .word 0x08012ef7 case HAL_OK : usb_status = USBD_OK; - 8010a64: 2300 movs r3, #0 - 8010a66: 75fb strb r3, [r7, #23] + 8012ee4: 2300 movs r3, #0 + 8012ee6: 75fb strb r3, [r7, #23] break; - 8010a68: e00b b.n 8010a82 + 8012ee8: e00b b.n 8012f02 case HAL_ERROR : usb_status = USBD_FAIL; - 8010a6a: 2303 movs r3, #3 - 8010a6c: 75fb strb r3, [r7, #23] + 8012eea: 2303 movs r3, #3 + 8012eec: 75fb strb r3, [r7, #23] break; - 8010a6e: e008 b.n 8010a82 + 8012eee: e008 b.n 8012f02 case HAL_BUSY : usb_status = USBD_BUSY; - 8010a70: 2301 movs r3, #1 - 8010a72: 75fb strb r3, [r7, #23] + 8012ef0: 2301 movs r3, #1 + 8012ef2: 75fb strb r3, [r7, #23] break; - 8010a74: e005 b.n 8010a82 + 8012ef4: e005 b.n 8012f02 case HAL_TIMEOUT : usb_status = USBD_FAIL; - 8010a76: 2303 movs r3, #3 - 8010a78: 75fb strb r3, [r7, #23] + 8012ef6: 2303 movs r3, #3 + 8012ef8: 75fb strb r3, [r7, #23] break; - 8010a7a: e002 b.n 8010a82 + 8012efa: e002 b.n 8012f02 default : usb_status = USBD_FAIL; - 8010a7c: 2303 movs r3, #3 - 8010a7e: 75fb strb r3, [r7, #23] + 8012efc: 2303 movs r3, #3 + 8012efe: 75fb strb r3, [r7, #23] break; - 8010a80: bf00 nop + 8012f00: bf00 nop } return usb_status; - 8010a82: 7dfb ldrb r3, [r7, #23] + 8012f02: 7dfb ldrb r3, [r7, #23] } - 8010a84: 4618 mov r0, r3 - 8010a86: 3718 adds r7, #24 - 8010a88: 46bd mov sp, r7 - 8010a8a: bd80 pop {r7, pc} + 8012f04: 4618 mov r0, r3 + 8012f06: 3718 adds r7, #24 + 8012f08: 46bd mov sp, r7 + 8012f0a: bd80 pop {r7, pc} + +08012f0c : + * @param pdev: Device handle + * @param ep_addr: Endpoint number + * @retval Received Data Size + */ +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) +{ + 8012f0c: b580 push {r7, lr} + 8012f0e: b082 sub sp, #8 + 8012f10: af00 add r7, sp, #0 + 8012f12: 6078 str r0, [r7, #4] + 8012f14: 460b mov r3, r1 + 8012f16: 70fb strb r3, [r7, #3] + return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); + 8012f18: 687b ldr r3, [r7, #4] + 8012f1a: f8d3 32c8 ldr.w r3, [r3, #712] ; 0x2c8 + 8012f1e: 78fa ldrb r2, [r7, #3] + 8012f20: 4611 mov r1, r2 + 8012f22: 4618 mov r0, r3 + 8012f24: f7f5 f9a8 bl 8008278 + 8012f28: 4603 mov r3, r0 +} + 8012f2a: 4618 mov r0, r3 + 8012f2c: 3708 adds r7, #8 + 8012f2e: 46bd mov sp, r7 + 8012f30: bd80 pop {r7, pc} + ... -08010a8c : +08012f34 : * @param hpcd: PCD handle * @param msg: LPM message * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { - 8010a8c: b580 push {r7, lr} - 8010a8e: b082 sub sp, #8 - 8010a90: af00 add r7, sp, #0 - 8010a92: 6078 str r0, [r7, #4] - 8010a94: 460b mov r3, r1 - 8010a96: 70fb strb r3, [r7, #3] + 8012f34: b580 push {r7, lr} + 8012f36: b082 sub sp, #8 + 8012f38: af00 add r7, sp, #0 + 8012f3a: 6078 str r0, [r7, #4] + 8012f3c: 460b mov r3, r1 + 8012f3e: 70fb strb r3, [r7, #3] switch (msg) - 8010a98: 78fb ldrb r3, [r7, #3] - 8010a9a: 2b00 cmp r3, #0 - 8010a9c: d002 beq.n 8010aa4 - 8010a9e: 2b01 cmp r3, #1 - 8010aa0: d013 beq.n 8010aca + 8012f40: 78fb ldrb r3, [r7, #3] + 8012f42: 2b00 cmp r3, #0 + 8012f44: d002 beq.n 8012f4c + 8012f46: 2b01 cmp r3, #1 + 8012f48: d013 beq.n 8012f72 /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } } - 8010aa2: e023 b.n 8010aec + 8012f4a: e023 b.n 8012f94 if (hpcd->Init.low_power_enable) - 8010aa4: 687b ldr r3, [r7, #4] - 8010aa6: 699b ldr r3, [r3, #24] - 8010aa8: 2b00 cmp r3, #0 - 8010aaa: d007 beq.n 8010abc + 8012f4c: 687b ldr r3, [r7, #4] + 8012f4e: 699b ldr r3, [r3, #24] + 8012f50: 2b00 cmp r3, #0 + 8012f52: d007 beq.n 8012f64 SystemClockConfig_Resume(); - 8010aac: f000 f83c bl 8010b28 + 8012f54: f000 f83c bl 8012fd0 SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - 8010ab0: 4b10 ldr r3, [pc, #64] ; (8010af4 ) - 8010ab2: 691b ldr r3, [r3, #16] - 8010ab4: 4a0f ldr r2, [pc, #60] ; (8010af4 ) - 8010ab6: f023 0306 bic.w r3, r3, #6 - 8010aba: 6113 str r3, [r2, #16] + 8012f58: 4b10 ldr r3, [pc, #64] ; (8012f9c ) + 8012f5a: 691b ldr r3, [r3, #16] + 8012f5c: 4a0f ldr r2, [pc, #60] ; (8012f9c ) + 8012f5e: f023 0306 bic.w r3, r3, #6 + 8012f62: 6113 str r3, [r2, #16] USBD_LL_Resume(hpcd->pData); - 8010abc: 687b ldr r3, [r7, #4] - 8010abe: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 8010ac2: 4618 mov r0, r3 - 8010ac4: f7fe fc0b bl 800f2de + 8012f64: 687b ldr r3, [r7, #4] + 8012f66: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 8012f6a: 4618 mov r0, r3 + 8012f6c: f7fd fdb5 bl 8010ada break; - 8010ac8: e010 b.n 8010aec + 8012f70: e010 b.n 8012f94 USBD_LL_Suspend(hpcd->pData); - 8010aca: 687b ldr r3, [r7, #4] - 8010acc: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 - 8010ad0: 4618 mov r0, r3 - 8010ad2: f7fe fbe8 bl 800f2a6 + 8012f72: 687b ldr r3, [r7, #4] + 8012f74: f8d3 32f4 ldr.w r3, [r3, #756] ; 0x2f4 + 8012f78: 4618 mov r0, r3 + 8012f7a: f7fd fd92 bl 8010aa2 if (hpcd->Init.low_power_enable) - 8010ad6: 687b ldr r3, [r7, #4] - 8010ad8: 699b ldr r3, [r3, #24] - 8010ada: 2b00 cmp r3, #0 - 8010adc: d005 beq.n 8010aea + 8012f7e: 687b ldr r3, [r7, #4] + 8012f80: 699b ldr r3, [r3, #24] + 8012f82: 2b00 cmp r3, #0 + 8012f84: d005 beq.n 8012f92 SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - 8010ade: 4b05 ldr r3, [pc, #20] ; (8010af4 ) - 8010ae0: 691b ldr r3, [r3, #16] - 8010ae2: 4a04 ldr r2, [pc, #16] ; (8010af4 ) - 8010ae4: f043 0306 orr.w r3, r3, #6 - 8010ae8: 6113 str r3, [r2, #16] + 8012f86: 4b05 ldr r3, [pc, #20] ; (8012f9c ) + 8012f88: 691b ldr r3, [r3, #16] + 8012f8a: 4a04 ldr r2, [pc, #16] ; (8012f9c ) + 8012f8c: f043 0306 orr.w r3, r3, #6 + 8012f90: 6113 str r3, [r2, #16] break; - 8010aea: bf00 nop + 8012f92: bf00 nop } - 8010aec: bf00 nop - 8010aee: 3708 adds r7, #8 - 8010af0: 46bd mov sp, r7 - 8010af2: bd80 pop {r7, pc} - 8010af4: e000ed00 .word 0xe000ed00 + 8012f94: bf00 nop + 8012f96: 3708 adds r7, #8 + 8012f98: 46bd mov sp, r7 + 8012f9a: bd80 pop {r7, pc} + 8012f9c: e000ed00 .word 0xe000ed00 -08010af8 : +08012fa0 : * @brief Static single allocation. * @param size: Size of allocated memory * @retval None */ void *USBD_static_malloc(uint32_t size) { - 8010af8: b480 push {r7} - 8010afa: b083 sub sp, #12 - 8010afc: af00 add r7, sp, #0 - 8010afe: 6078 str r0, [r7, #4] - static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + 8012fa0: b480 push {r7} + 8012fa2: b083 sub sp, #12 + 8012fa4: af00 add r7, sp, #0 + 8012fa6: 6078 str r0, [r7, #4] + static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; - 8010b00: 4b03 ldr r3, [pc, #12] ; (8010b10 ) + 8012fa8: 4b03 ldr r3, [pc, #12] ; (8012fb8 ) } - 8010b02: 4618 mov r0, r3 - 8010b04: 370c adds r7, #12 - 8010b06: 46bd mov sp, r7 - 8010b08: f85d 7b04 ldr.w r7, [sp], #4 - 8010b0c: 4770 bx lr - 8010b0e: bf00 nop - 8010b10: 20001478 .word 0x20001478 + 8012faa: 4618 mov r0, r3 + 8012fac: 370c adds r7, #12 + 8012fae: 46bd mov sp, r7 + 8012fb0: f85d 7b04 ldr.w r7, [sp], #4 + 8012fb4: 4770 bx lr + 8012fb6: bf00 nop + 8012fb8: 20002024 .word 0x20002024 -08010b14 : +08012fbc : * @brief Dummy memory free * @param p: Pointer to allocated memory address * @retval None */ void USBD_static_free(void *p) { - 8010b14: b480 push {r7} - 8010b16: b083 sub sp, #12 - 8010b18: af00 add r7, sp, #0 - 8010b1a: 6078 str r0, [r7, #4] + 8012fbc: b480 push {r7} + 8012fbe: b083 sub sp, #12 + 8012fc0: af00 add r7, sp, #0 + 8012fc2: 6078 str r0, [r7, #4] } - 8010b1c: bf00 nop - 8010b1e: 370c adds r7, #12 - 8010b20: 46bd mov sp, r7 - 8010b22: f85d 7b04 ldr.w r7, [sp], #4 - 8010b26: 4770 bx lr + 8012fc4: bf00 nop + 8012fc6: 370c adds r7, #12 + 8012fc8: 46bd mov sp, r7 + 8012fca: f85d 7b04 ldr.w r7, [sp], #4 + 8012fce: 4770 bx lr -08010b28 : +08012fd0 : * @brief Configures system clock after wake-up from USB resume callBack: * enable HSI, PLL and select PLL as system clock source. * @retval None */ static void SystemClockConfig_Resume(void) { - 8010b28: b580 push {r7, lr} - 8010b2a: af00 add r7, sp, #0 + 8012fd0: b580 push {r7, lr} + 8012fd2: af00 add r7, sp, #0 SystemClock_Config(); - 8010b2c: f7f0 fbe2 bl 80012f4 -} - 8010b30: bf00 nop - 8010b32: bd80 pop {r7, pc} - -08010b34 : - 8010b34: 4b02 ldr r3, [pc, #8] ; (8010b40 ) - 8010b36: 4601 mov r1, r0 - 8010b38: 6818 ldr r0, [r3, #0] - 8010b3a: f000 b82b b.w 8010b94 <_malloc_r> - 8010b3e: bf00 nop - 8010b40: 20000310 .word 0x20000310 - -08010b44 : - 8010b44: 4b02 ldr r3, [pc, #8] ; (8010b50 ) - 8010b46: 4601 mov r1, r0 - 8010b48: 6818 ldr r0, [r3, #0] - 8010b4a: f002 bf57 b.w 80139fc <_free_r> - 8010b4e: bf00 nop - 8010b50: 20000310 .word 0x20000310 - -08010b54 : - 8010b54: b570 push {r4, r5, r6, lr} - 8010b56: 4e0e ldr r6, [pc, #56] ; (8010b90 ) - 8010b58: 460c mov r4, r1 - 8010b5a: 6831 ldr r1, [r6, #0] - 8010b5c: 4605 mov r5, r0 - 8010b5e: b911 cbnz r1, 8010b66 - 8010b60: f002 f840 bl 8012be4 <_sbrk_r> - 8010b64: 6030 str r0, [r6, #0] - 8010b66: 4621 mov r1, r4 - 8010b68: 4628 mov r0, r5 - 8010b6a: f002 f83b bl 8012be4 <_sbrk_r> - 8010b6e: 1c43 adds r3, r0, #1 - 8010b70: d00a beq.n 8010b88 - 8010b72: 1cc4 adds r4, r0, #3 - 8010b74: f024 0403 bic.w r4, r4, #3 - 8010b78: 42a0 cmp r0, r4 - 8010b7a: d007 beq.n 8010b8c - 8010b7c: 1a21 subs r1, r4, r0 - 8010b7e: 4628 mov r0, r5 - 8010b80: f002 f830 bl 8012be4 <_sbrk_r> - 8010b84: 3001 adds r0, #1 - 8010b86: d101 bne.n 8010b8c - 8010b88: f04f 34ff mov.w r4, #4294967295 - 8010b8c: 4620 mov r0, r4 - 8010b8e: bd70 pop {r4, r5, r6, pc} - 8010b90: 20001490 .word 0x20001490 - -08010b94 <_malloc_r>: - 8010b94: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 8010b98: 1ccd adds r5, r1, #3 - 8010b9a: f025 0503 bic.w r5, r5, #3 - 8010b9e: 3508 adds r5, #8 - 8010ba0: 2d0c cmp r5, #12 - 8010ba2: bf38 it cc - 8010ba4: 250c movcc r5, #12 - 8010ba6: 2d00 cmp r5, #0 - 8010ba8: 4607 mov r7, r0 - 8010baa: db01 blt.n 8010bb0 <_malloc_r+0x1c> - 8010bac: 42a9 cmp r1, r5 - 8010bae: d905 bls.n 8010bbc <_malloc_r+0x28> - 8010bb0: 230c movs r3, #12 - 8010bb2: 603b str r3, [r7, #0] - 8010bb4: 2600 movs r6, #0 - 8010bb6: 4630 mov r0, r6 - 8010bb8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8010bbc: f8df 80d0 ldr.w r8, [pc, #208] ; 8010c90 <_malloc_r+0xfc> - 8010bc0: f000 f868 bl 8010c94 <__malloc_lock> - 8010bc4: f8d8 3000 ldr.w r3, [r8] - 8010bc8: 461c mov r4, r3 - 8010bca: bb5c cbnz r4, 8010c24 <_malloc_r+0x90> - 8010bcc: 4629 mov r1, r5 - 8010bce: 4638 mov r0, r7 - 8010bd0: f7ff ffc0 bl 8010b54 - 8010bd4: 1c43 adds r3, r0, #1 - 8010bd6: 4604 mov r4, r0 - 8010bd8: d155 bne.n 8010c86 <_malloc_r+0xf2> - 8010bda: f8d8 4000 ldr.w r4, [r8] - 8010bde: 4626 mov r6, r4 - 8010be0: 2e00 cmp r6, #0 - 8010be2: d145 bne.n 8010c70 <_malloc_r+0xdc> - 8010be4: 2c00 cmp r4, #0 - 8010be6: d048 beq.n 8010c7a <_malloc_r+0xe6> - 8010be8: 6823 ldr r3, [r4, #0] - 8010bea: 4631 mov r1, r6 - 8010bec: 4638 mov r0, r7 - 8010bee: eb04 0903 add.w r9, r4, r3 - 8010bf2: f001 fff7 bl 8012be4 <_sbrk_r> - 8010bf6: 4581 cmp r9, r0 - 8010bf8: d13f bne.n 8010c7a <_malloc_r+0xe6> - 8010bfa: 6821 ldr r1, [r4, #0] - 8010bfc: 1a6d subs r5, r5, r1 - 8010bfe: 4629 mov r1, r5 - 8010c00: 4638 mov r0, r7 - 8010c02: f7ff ffa7 bl 8010b54 - 8010c06: 3001 adds r0, #1 - 8010c08: d037 beq.n 8010c7a <_malloc_r+0xe6> - 8010c0a: 6823 ldr r3, [r4, #0] - 8010c0c: 442b add r3, r5 - 8010c0e: 6023 str r3, [r4, #0] - 8010c10: f8d8 3000 ldr.w r3, [r8] - 8010c14: 2b00 cmp r3, #0 - 8010c16: d038 beq.n 8010c8a <_malloc_r+0xf6> - 8010c18: 685a ldr r2, [r3, #4] - 8010c1a: 42a2 cmp r2, r4 - 8010c1c: d12b bne.n 8010c76 <_malloc_r+0xe2> - 8010c1e: 2200 movs r2, #0 - 8010c20: 605a str r2, [r3, #4] - 8010c22: e00f b.n 8010c44 <_malloc_r+0xb0> - 8010c24: 6822 ldr r2, [r4, #0] - 8010c26: 1b52 subs r2, r2, r5 - 8010c28: d41f bmi.n 8010c6a <_malloc_r+0xd6> - 8010c2a: 2a0b cmp r2, #11 - 8010c2c: d917 bls.n 8010c5e <_malloc_r+0xca> - 8010c2e: 1961 adds r1, r4, r5 - 8010c30: 42a3 cmp r3, r4 - 8010c32: 6025 str r5, [r4, #0] - 8010c34: bf18 it ne - 8010c36: 6059 strne r1, [r3, #4] - 8010c38: 6863 ldr r3, [r4, #4] - 8010c3a: bf08 it eq - 8010c3c: f8c8 1000 streq.w r1, [r8] - 8010c40: 5162 str r2, [r4, r5] - 8010c42: 604b str r3, [r1, #4] - 8010c44: 4638 mov r0, r7 - 8010c46: f104 060b add.w r6, r4, #11 - 8010c4a: f000 f829 bl 8010ca0 <__malloc_unlock> - 8010c4e: f026 0607 bic.w r6, r6, #7 - 8010c52: 1d23 adds r3, r4, #4 - 8010c54: 1af2 subs r2, r6, r3 - 8010c56: d0ae beq.n 8010bb6 <_malloc_r+0x22> - 8010c58: 1b9b subs r3, r3, r6 - 8010c5a: 50a3 str r3, [r4, r2] - 8010c5c: e7ab b.n 8010bb6 <_malloc_r+0x22> - 8010c5e: 42a3 cmp r3, r4 - 8010c60: 6862 ldr r2, [r4, #4] - 8010c62: d1dd bne.n 8010c20 <_malloc_r+0x8c> - 8010c64: f8c8 2000 str.w r2, [r8] - 8010c68: e7ec b.n 8010c44 <_malloc_r+0xb0> - 8010c6a: 4623 mov r3, r4 - 8010c6c: 6864 ldr r4, [r4, #4] - 8010c6e: e7ac b.n 8010bca <_malloc_r+0x36> - 8010c70: 4634 mov r4, r6 - 8010c72: 6876 ldr r6, [r6, #4] - 8010c74: e7b4 b.n 8010be0 <_malloc_r+0x4c> - 8010c76: 4613 mov r3, r2 - 8010c78: e7cc b.n 8010c14 <_malloc_r+0x80> - 8010c7a: 230c movs r3, #12 - 8010c7c: 603b str r3, [r7, #0] - 8010c7e: 4638 mov r0, r7 - 8010c80: f000 f80e bl 8010ca0 <__malloc_unlock> - 8010c84: e797 b.n 8010bb6 <_malloc_r+0x22> - 8010c86: 6025 str r5, [r4, #0] - 8010c88: e7dc b.n 8010c44 <_malloc_r+0xb0> - 8010c8a: 605b str r3, [r3, #4] - 8010c8c: deff udf #255 ; 0xff - 8010c8e: bf00 nop - 8010c90: 2000148c .word 0x2000148c - -08010c94 <__malloc_lock>: - 8010c94: 4801 ldr r0, [pc, #4] ; (8010c9c <__malloc_lock+0x8>) - 8010c96: f001 bff2 b.w 8012c7e <__retarget_lock_acquire_recursive> - 8010c9a: bf00 nop - 8010c9c: 200015d4 .word 0x200015d4 - -08010ca0 <__malloc_unlock>: - 8010ca0: 4801 ldr r0, [pc, #4] ; (8010ca8 <__malloc_unlock+0x8>) - 8010ca2: f001 bfed b.w 8012c80 <__retarget_lock_release_recursive> - 8010ca6: bf00 nop - 8010ca8: 200015d4 .word 0x200015d4 - -08010cac : - 8010cac: b570 push {r4, r5, r6, lr} - 8010cae: 4604 mov r4, r0 - 8010cb0: 460d mov r5, r1 - 8010cb2: ec45 4b10 vmov d0, r4, r5 - 8010cb6: 4616 mov r6, r2 - 8010cb8: f003 fdc2 bl 8014840 <__ulp> - 8010cbc: ec51 0b10 vmov r0, r1, d0 - 8010cc0: b17e cbz r6, 8010ce2 - 8010cc2: f3c5 530a ubfx r3, r5, #20, #11 - 8010cc6: f1c3 036b rsb r3, r3, #107 ; 0x6b - 8010cca: 2b00 cmp r3, #0 - 8010ccc: dd09 ble.n 8010ce2 - 8010cce: 051b lsls r3, r3, #20 - 8010cd0: f103 557f add.w r5, r3, #1069547520 ; 0x3fc00000 - 8010cd4: 2400 movs r4, #0 - 8010cd6: f505 1540 add.w r5, r5, #3145728 ; 0x300000 - 8010cda: 4622 mov r2, r4 - 8010cdc: 462b mov r3, r5 - 8010cde: f7ef fc8b bl 80005f8 <__aeabi_dmul> - 8010ce2: bd70 pop {r4, r5, r6, pc} - 8010ce4: 0000 movs r0, r0 + 8012fd4: f7ee fc8c bl 80018f0 +} + 8012fd8: bf00 nop + 8012fda: bd80 pop {r7, pc} + +08012fdc : + 8012fdc: 220a movs r2, #10 + 8012fde: 2100 movs r1, #0 + 8012fe0: f000 bfba b.w 8013f58 + +08012fe4 : + 8012fe4: 4b02 ldr r3, [pc, #8] ; (8012ff0 ) + 8012fe6: 4601 mov r1, r0 + 8012fe8: 6818 ldr r0, [r3, #0] + 8012fea: f000 b82b b.w 8013044 <_malloc_r> + 8012fee: bf00 nop + 8012ff0: 200002f0 .word 0x200002f0 + +08012ff4 : + 8012ff4: 4b02 ldr r3, [pc, #8] ; (8013000 ) + 8012ff6: 4601 mov r1, r0 + 8012ff8: 6818 ldr r0, [r3, #0] + 8012ffa: f002 bf57 b.w 8015eac <_free_r> + 8012ffe: bf00 nop + 8013000: 200002f0 .word 0x200002f0 + +08013004 : + 8013004: b570 push {r4, r5, r6, lr} + 8013006: 4e0e ldr r6, [pc, #56] ; (8013040 ) + 8013008: 460c mov r4, r1 + 801300a: 6831 ldr r1, [r6, #0] + 801300c: 4605 mov r5, r0 + 801300e: b911 cbnz r1, 8013016 + 8013010: f002 f840 bl 8015094 <_sbrk_r> + 8013014: 6030 str r0, [r6, #0] + 8013016: 4621 mov r1, r4 + 8013018: 4628 mov r0, r5 + 801301a: f002 f83b bl 8015094 <_sbrk_r> + 801301e: 1c43 adds r3, r0, #1 + 8013020: d00a beq.n 8013038 + 8013022: 1cc4 adds r4, r0, #3 + 8013024: f024 0403 bic.w r4, r4, #3 + 8013028: 42a0 cmp r0, r4 + 801302a: d007 beq.n 801303c + 801302c: 1a21 subs r1, r4, r0 + 801302e: 4628 mov r0, r5 + 8013030: f002 f830 bl 8015094 <_sbrk_r> + 8013034: 3001 adds r0, #1 + 8013036: d101 bne.n 801303c + 8013038: f04f 34ff mov.w r4, #4294967295 + 801303c: 4620 mov r0, r4 + 801303e: bd70 pop {r4, r5, r6, pc} + 8013040: 20002248 .word 0x20002248 + +08013044 <_malloc_r>: + 8013044: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8013048: 1ccd adds r5, r1, #3 + 801304a: f025 0503 bic.w r5, r5, #3 + 801304e: 3508 adds r5, #8 + 8013050: 2d0c cmp r5, #12 + 8013052: bf38 it cc + 8013054: 250c movcc r5, #12 + 8013056: 2d00 cmp r5, #0 + 8013058: 4607 mov r7, r0 + 801305a: db01 blt.n 8013060 <_malloc_r+0x1c> + 801305c: 42a9 cmp r1, r5 + 801305e: d905 bls.n 801306c <_malloc_r+0x28> + 8013060: 230c movs r3, #12 + 8013062: 603b str r3, [r7, #0] + 8013064: 2600 movs r6, #0 + 8013066: 4630 mov r0, r6 + 8013068: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 801306c: f8df 80d0 ldr.w r8, [pc, #208] ; 8013140 <_malloc_r+0xfc> + 8013070: f000 f868 bl 8013144 <__malloc_lock> + 8013074: f8d8 3000 ldr.w r3, [r8] + 8013078: 461c mov r4, r3 + 801307a: bb5c cbnz r4, 80130d4 <_malloc_r+0x90> + 801307c: 4629 mov r1, r5 + 801307e: 4638 mov r0, r7 + 8013080: f7ff ffc0 bl 8013004 + 8013084: 1c43 adds r3, r0, #1 + 8013086: 4604 mov r4, r0 + 8013088: d155 bne.n 8013136 <_malloc_r+0xf2> + 801308a: f8d8 4000 ldr.w r4, [r8] + 801308e: 4626 mov r6, r4 + 8013090: 2e00 cmp r6, #0 + 8013092: d145 bne.n 8013120 <_malloc_r+0xdc> + 8013094: 2c00 cmp r4, #0 + 8013096: d048 beq.n 801312a <_malloc_r+0xe6> + 8013098: 6823 ldr r3, [r4, #0] + 801309a: 4631 mov r1, r6 + 801309c: 4638 mov r0, r7 + 801309e: eb04 0903 add.w r9, r4, r3 + 80130a2: f001 fff7 bl 8015094 <_sbrk_r> + 80130a6: 4581 cmp r9, r0 + 80130a8: d13f bne.n 801312a <_malloc_r+0xe6> + 80130aa: 6821 ldr r1, [r4, #0] + 80130ac: 1a6d subs r5, r5, r1 + 80130ae: 4629 mov r1, r5 + 80130b0: 4638 mov r0, r7 + 80130b2: f7ff ffa7 bl 8013004 + 80130b6: 3001 adds r0, #1 + 80130b8: d037 beq.n 801312a <_malloc_r+0xe6> + 80130ba: 6823 ldr r3, [r4, #0] + 80130bc: 442b add r3, r5 + 80130be: 6023 str r3, [r4, #0] + 80130c0: f8d8 3000 ldr.w r3, [r8] + 80130c4: 2b00 cmp r3, #0 + 80130c6: d038 beq.n 801313a <_malloc_r+0xf6> + 80130c8: 685a ldr r2, [r3, #4] + 80130ca: 42a2 cmp r2, r4 + 80130cc: d12b bne.n 8013126 <_malloc_r+0xe2> + 80130ce: 2200 movs r2, #0 + 80130d0: 605a str r2, [r3, #4] + 80130d2: e00f b.n 80130f4 <_malloc_r+0xb0> + 80130d4: 6822 ldr r2, [r4, #0] + 80130d6: 1b52 subs r2, r2, r5 + 80130d8: d41f bmi.n 801311a <_malloc_r+0xd6> + 80130da: 2a0b cmp r2, #11 + 80130dc: d917 bls.n 801310e <_malloc_r+0xca> + 80130de: 1961 adds r1, r4, r5 + 80130e0: 42a3 cmp r3, r4 + 80130e2: 6025 str r5, [r4, #0] + 80130e4: bf18 it ne + 80130e6: 6059 strne r1, [r3, #4] + 80130e8: 6863 ldr r3, [r4, #4] + 80130ea: bf08 it eq + 80130ec: f8c8 1000 streq.w r1, [r8] + 80130f0: 5162 str r2, [r4, r5] + 80130f2: 604b str r3, [r1, #4] + 80130f4: 4638 mov r0, r7 + 80130f6: f104 060b add.w r6, r4, #11 + 80130fa: f000 f829 bl 8013150 <__malloc_unlock> + 80130fe: f026 0607 bic.w r6, r6, #7 + 8013102: 1d23 adds r3, r4, #4 + 8013104: 1af2 subs r2, r6, r3 + 8013106: d0ae beq.n 8013066 <_malloc_r+0x22> + 8013108: 1b9b subs r3, r3, r6 + 801310a: 50a3 str r3, [r4, r2] + 801310c: e7ab b.n 8013066 <_malloc_r+0x22> + 801310e: 42a3 cmp r3, r4 + 8013110: 6862 ldr r2, [r4, #4] + 8013112: d1dd bne.n 80130d0 <_malloc_r+0x8c> + 8013114: f8c8 2000 str.w r2, [r8] + 8013118: e7ec b.n 80130f4 <_malloc_r+0xb0> + 801311a: 4623 mov r3, r4 + 801311c: 6864 ldr r4, [r4, #4] + 801311e: e7ac b.n 801307a <_malloc_r+0x36> + 8013120: 4634 mov r4, r6 + 8013122: 6876 ldr r6, [r6, #4] + 8013124: e7b4 b.n 8013090 <_malloc_r+0x4c> + 8013126: 4613 mov r3, r2 + 8013128: e7cc b.n 80130c4 <_malloc_r+0x80> + 801312a: 230c movs r3, #12 + 801312c: 603b str r3, [r7, #0] + 801312e: 4638 mov r0, r7 + 8013130: f000 f80e bl 8013150 <__malloc_unlock> + 8013134: e797 b.n 8013066 <_malloc_r+0x22> + 8013136: 6025 str r5, [r4, #0] + 8013138: e7dc b.n 80130f4 <_malloc_r+0xb0> + 801313a: 605b str r3, [r3, #4] + 801313c: deff udf #255 ; 0xff + 801313e: bf00 nop + 8013140: 20002244 .word 0x20002244 + +08013144 <__malloc_lock>: + 8013144: 4801 ldr r0, [pc, #4] ; (801314c <__malloc_lock+0x8>) + 8013146: f001 bff2 b.w 801512e <__retarget_lock_acquire_recursive> + 801314a: bf00 nop + 801314c: 2000238c .word 0x2000238c + +08013150 <__malloc_unlock>: + 8013150: 4801 ldr r0, [pc, #4] ; (8013158 <__malloc_unlock+0x8>) + 8013152: f001 bfed b.w 8015130 <__retarget_lock_release_recursive> + 8013156: bf00 nop + 8013158: 2000238c .word 0x2000238c + +0801315c : + 801315c: b570 push {r4, r5, r6, lr} + 801315e: 4604 mov r4, r0 + 8013160: 460d mov r5, r1 + 8013162: ec45 4b10 vmov d0, r4, r5 + 8013166: 4616 mov r6, r2 + 8013168: f003 fdc2 bl 8016cf0 <__ulp> + 801316c: ec51 0b10 vmov r0, r1, d0 + 8013170: b17e cbz r6, 8013192 + 8013172: f3c5 530a ubfx r3, r5, #20, #11 + 8013176: f1c3 036b rsb r3, r3, #107 ; 0x6b + 801317a: 2b00 cmp r3, #0 + 801317c: dd09 ble.n 8013192 + 801317e: 051b lsls r3, r3, #20 + 8013180: f103 557f add.w r5, r3, #1069547520 ; 0x3fc00000 + 8013184: 2400 movs r4, #0 + 8013186: f505 1540 add.w r5, r5, #3145728 ; 0x300000 + 801318a: 4622 mov r2, r4 + 801318c: 462b mov r3, r5 + 801318e: f7ed fa33 bl 80005f8 <__aeabi_dmul> + 8013192: bd70 pop {r4, r5, r6, pc} + 8013194: 0000 movs r0, r0 ... -08010ce8 <_strtod_l>: - 8010ce8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8010cec: ed2d 8b02 vpush {d8} - 8010cf0: b09b sub sp, #108 ; 0x6c - 8010cf2: 4604 mov r4, r0 - 8010cf4: 9213 str r2, [sp, #76] ; 0x4c - 8010cf6: 2200 movs r2, #0 - 8010cf8: 9216 str r2, [sp, #88] ; 0x58 - 8010cfa: 460d mov r5, r1 - 8010cfc: f04f 0800 mov.w r8, #0 - 8010d00: f04f 0900 mov.w r9, #0 - 8010d04: 460a mov r2, r1 - 8010d06: 9215 str r2, [sp, #84] ; 0x54 - 8010d08: 7811 ldrb r1, [r2, #0] - 8010d0a: 292b cmp r1, #43 ; 0x2b - 8010d0c: d04c beq.n 8010da8 <_strtod_l+0xc0> - 8010d0e: d83a bhi.n 8010d86 <_strtod_l+0x9e> - 8010d10: 290d cmp r1, #13 - 8010d12: d834 bhi.n 8010d7e <_strtod_l+0x96> - 8010d14: 2908 cmp r1, #8 - 8010d16: d834 bhi.n 8010d82 <_strtod_l+0x9a> - 8010d18: 2900 cmp r1, #0 - 8010d1a: d03d beq.n 8010d98 <_strtod_l+0xb0> - 8010d1c: 2200 movs r2, #0 - 8010d1e: 920a str r2, [sp, #40] ; 0x28 - 8010d20: 9e15 ldr r6, [sp, #84] ; 0x54 - 8010d22: 7832 ldrb r2, [r6, #0] - 8010d24: 2a30 cmp r2, #48 ; 0x30 - 8010d26: f040 80b4 bne.w 8010e92 <_strtod_l+0x1aa> - 8010d2a: 7872 ldrb r2, [r6, #1] - 8010d2c: f002 02df and.w r2, r2, #223 ; 0xdf - 8010d30: 2a58 cmp r2, #88 ; 0x58 - 8010d32: d170 bne.n 8010e16 <_strtod_l+0x12e> - 8010d34: 9302 str r3, [sp, #8] - 8010d36: 9b0a ldr r3, [sp, #40] ; 0x28 - 8010d38: 9301 str r3, [sp, #4] - 8010d3a: ab16 add r3, sp, #88 ; 0x58 - 8010d3c: 9300 str r3, [sp, #0] - 8010d3e: 4a8e ldr r2, [pc, #568] ; (8010f78 <_strtod_l+0x290>) - 8010d40: ab17 add r3, sp, #92 ; 0x5c - 8010d42: a915 add r1, sp, #84 ; 0x54 - 8010d44: 4620 mov r0, r4 - 8010d46: f002 ff0d bl 8013b64 <__gethex> - 8010d4a: f010 070f ands.w r7, r0, #15 - 8010d4e: 4605 mov r5, r0 - 8010d50: d005 beq.n 8010d5e <_strtod_l+0x76> - 8010d52: 2f06 cmp r7, #6 - 8010d54: d12a bne.n 8010dac <_strtod_l+0xc4> - 8010d56: 3601 adds r6, #1 - 8010d58: 2300 movs r3, #0 - 8010d5a: 9615 str r6, [sp, #84] ; 0x54 - 8010d5c: 930a str r3, [sp, #40] ; 0x28 - 8010d5e: 9b13 ldr r3, [sp, #76] ; 0x4c - 8010d60: 2b00 cmp r3, #0 - 8010d62: f040 857f bne.w 8011864 <_strtod_l+0xb7c> - 8010d66: 9b0a ldr r3, [sp, #40] ; 0x28 - 8010d68: b1db cbz r3, 8010da2 <_strtod_l+0xba> - 8010d6a: 4642 mov r2, r8 - 8010d6c: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 - 8010d70: ec43 2b10 vmov d0, r2, r3 - 8010d74: b01b add sp, #108 ; 0x6c - 8010d76: ecbd 8b02 vpop {d8} - 8010d7a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8010d7e: 2920 cmp r1, #32 - 8010d80: d1cc bne.n 8010d1c <_strtod_l+0x34> - 8010d82: 3201 adds r2, #1 - 8010d84: e7bf b.n 8010d06 <_strtod_l+0x1e> - 8010d86: 292d cmp r1, #45 ; 0x2d - 8010d88: d1c8 bne.n 8010d1c <_strtod_l+0x34> - 8010d8a: 2101 movs r1, #1 - 8010d8c: 910a str r1, [sp, #40] ; 0x28 - 8010d8e: 1c51 adds r1, r2, #1 - 8010d90: 9115 str r1, [sp, #84] ; 0x54 - 8010d92: 7852 ldrb r2, [r2, #1] - 8010d94: 2a00 cmp r2, #0 - 8010d96: d1c3 bne.n 8010d20 <_strtod_l+0x38> - 8010d98: 9b13 ldr r3, [sp, #76] ; 0x4c - 8010d9a: 9515 str r5, [sp, #84] ; 0x54 - 8010d9c: 2b00 cmp r3, #0 - 8010d9e: f040 855f bne.w 8011860 <_strtod_l+0xb78> - 8010da2: 4642 mov r2, r8 - 8010da4: 464b mov r3, r9 - 8010da6: e7e3 b.n 8010d70 <_strtod_l+0x88> - 8010da8: 2100 movs r1, #0 - 8010daa: e7ef b.n 8010d8c <_strtod_l+0xa4> - 8010dac: 9a16 ldr r2, [sp, #88] ; 0x58 - 8010dae: b13a cbz r2, 8010dc0 <_strtod_l+0xd8> - 8010db0: 2135 movs r1, #53 ; 0x35 - 8010db2: a818 add r0, sp, #96 ; 0x60 - 8010db4: f003 fe41 bl 8014a3a <__copybits> - 8010db8: 9916 ldr r1, [sp, #88] ; 0x58 - 8010dba: 4620 mov r0, r4 - 8010dbc: f003 fa14 bl 80141e8 <_Bfree> - 8010dc0: 3f01 subs r7, #1 - 8010dc2: 9a17 ldr r2, [sp, #92] ; 0x5c - 8010dc4: 2f04 cmp r7, #4 - 8010dc6: d806 bhi.n 8010dd6 <_strtod_l+0xee> - 8010dc8: e8df f007 tbb [pc, r7] - 8010dcc: 201d0314 .word 0x201d0314 - 8010dd0: 14 .byte 0x14 - 8010dd1: 00 .byte 0x00 - 8010dd2: e9dd 8918 ldrd r8, r9, [sp, #96] ; 0x60 - 8010dd6: 05e9 lsls r1, r5, #23 - 8010dd8: bf48 it mi - 8010dda: f049 4900 orrmi.w r9, r9, #2147483648 ; 0x80000000 - 8010dde: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 - 8010de2: 0d1b lsrs r3, r3, #20 - 8010de4: 051b lsls r3, r3, #20 - 8010de6: 2b00 cmp r3, #0 - 8010de8: d1b9 bne.n 8010d5e <_strtod_l+0x76> - 8010dea: f001 ff1d bl 8012c28 <__errno> - 8010dee: 2322 movs r3, #34 ; 0x22 - 8010df0: 6003 str r3, [r0, #0] - 8010df2: e7b4 b.n 8010d5e <_strtod_l+0x76> - 8010df4: e9dd 8318 ldrd r8, r3, [sp, #96] ; 0x60 - 8010df8: f202 4233 addw r2, r2, #1075 ; 0x433 - 8010dfc: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 - 8010e00: ea43 5902 orr.w r9, r3, r2, lsl #20 - 8010e04: e7e7 b.n 8010dd6 <_strtod_l+0xee> - 8010e06: f8df 9178 ldr.w r9, [pc, #376] ; 8010f80 <_strtod_l+0x298> - 8010e0a: e7e4 b.n 8010dd6 <_strtod_l+0xee> - 8010e0c: f06f 4900 mvn.w r9, #2147483648 ; 0x80000000 - 8010e10: f04f 38ff mov.w r8, #4294967295 - 8010e14: e7df b.n 8010dd6 <_strtod_l+0xee> - 8010e16: 9b15 ldr r3, [sp, #84] ; 0x54 - 8010e18: 1c5a adds r2, r3, #1 - 8010e1a: 9215 str r2, [sp, #84] ; 0x54 - 8010e1c: 785b ldrb r3, [r3, #1] - 8010e1e: 2b30 cmp r3, #48 ; 0x30 - 8010e20: d0f9 beq.n 8010e16 <_strtod_l+0x12e> - 8010e22: 2b00 cmp r3, #0 - 8010e24: d09b beq.n 8010d5e <_strtod_l+0x76> - 8010e26: 2301 movs r3, #1 - 8010e28: f04f 0a00 mov.w sl, #0 - 8010e2c: 9304 str r3, [sp, #16] - 8010e2e: 9b15 ldr r3, [sp, #84] ; 0x54 - 8010e30: 930b str r3, [sp, #44] ; 0x2c - 8010e32: f8cd a024 str.w sl, [sp, #36] ; 0x24 - 8010e36: 46d3 mov fp, sl - 8010e38: 220a movs r2, #10 - 8010e3a: 9815 ldr r0, [sp, #84] ; 0x54 - 8010e3c: 7806 ldrb r6, [r0, #0] - 8010e3e: f1a6 0330 sub.w r3, r6, #48 ; 0x30 - 8010e42: b2d9 uxtb r1, r3 - 8010e44: 2909 cmp r1, #9 - 8010e46: d926 bls.n 8010e96 <_strtod_l+0x1ae> - 8010e48: 494c ldr r1, [pc, #304] ; (8010f7c <_strtod_l+0x294>) - 8010e4a: 2201 movs r2, #1 - 8010e4c: f001 fe0d bl 8012a6a - 8010e50: 2800 cmp r0, #0 - 8010e52: d030 beq.n 8010eb6 <_strtod_l+0x1ce> - 8010e54: 2000 movs r0, #0 - 8010e56: 4632 mov r2, r6 - 8010e58: 9005 str r0, [sp, #20] - 8010e5a: 465e mov r6, fp - 8010e5c: 4603 mov r3, r0 - 8010e5e: 2a65 cmp r2, #101 ; 0x65 - 8010e60: d001 beq.n 8010e66 <_strtod_l+0x17e> - 8010e62: 2a45 cmp r2, #69 ; 0x45 - 8010e64: d113 bne.n 8010e8e <_strtod_l+0x1a6> - 8010e66: b91e cbnz r6, 8010e70 <_strtod_l+0x188> - 8010e68: 9a04 ldr r2, [sp, #16] - 8010e6a: 4302 orrs r2, r0 - 8010e6c: d094 beq.n 8010d98 <_strtod_l+0xb0> - 8010e6e: 2600 movs r6, #0 - 8010e70: 9d15 ldr r5, [sp, #84] ; 0x54 - 8010e72: 1c6a adds r2, r5, #1 - 8010e74: 9215 str r2, [sp, #84] ; 0x54 - 8010e76: 786a ldrb r2, [r5, #1] - 8010e78: 2a2b cmp r2, #43 ; 0x2b - 8010e7a: d074 beq.n 8010f66 <_strtod_l+0x27e> - 8010e7c: 2a2d cmp r2, #45 ; 0x2d - 8010e7e: d078 beq.n 8010f72 <_strtod_l+0x28a> - 8010e80: f04f 0c00 mov.w ip, #0 - 8010e84: f1a2 0130 sub.w r1, r2, #48 ; 0x30 - 8010e88: 2909 cmp r1, #9 - 8010e8a: d97f bls.n 8010f8c <_strtod_l+0x2a4> - 8010e8c: 9515 str r5, [sp, #84] ; 0x54 - 8010e8e: 2700 movs r7, #0 - 8010e90: e09e b.n 8010fd0 <_strtod_l+0x2e8> - 8010e92: 2300 movs r3, #0 - 8010e94: e7c8 b.n 8010e28 <_strtod_l+0x140> - 8010e96: f1bb 0f08 cmp.w fp, #8 - 8010e9a: bfd8 it le - 8010e9c: 9909 ldrle r1, [sp, #36] ; 0x24 - 8010e9e: f100 0001 add.w r0, r0, #1 - 8010ea2: bfda itte le - 8010ea4: fb02 3301 mlale r3, r2, r1, r3 - 8010ea8: 9309 strle r3, [sp, #36] ; 0x24 - 8010eaa: fb02 3a0a mlagt sl, r2, sl, r3 - 8010eae: f10b 0b01 add.w fp, fp, #1 - 8010eb2: 9015 str r0, [sp, #84] ; 0x54 - 8010eb4: e7c1 b.n 8010e3a <_strtod_l+0x152> - 8010eb6: 9b15 ldr r3, [sp, #84] ; 0x54 - 8010eb8: 1c5a adds r2, r3, #1 - 8010eba: 9215 str r2, [sp, #84] ; 0x54 - 8010ebc: 785a ldrb r2, [r3, #1] - 8010ebe: f1bb 0f00 cmp.w fp, #0 - 8010ec2: d037 beq.n 8010f34 <_strtod_l+0x24c> - 8010ec4: 9005 str r0, [sp, #20] - 8010ec6: 465e mov r6, fp - 8010ec8: f1a2 0330 sub.w r3, r2, #48 ; 0x30 - 8010ecc: 2b09 cmp r3, #9 - 8010ece: d912 bls.n 8010ef6 <_strtod_l+0x20e> - 8010ed0: 2301 movs r3, #1 - 8010ed2: e7c4 b.n 8010e5e <_strtod_l+0x176> - 8010ed4: 9b15 ldr r3, [sp, #84] ; 0x54 - 8010ed6: 1c5a adds r2, r3, #1 - 8010ed8: 9215 str r2, [sp, #84] ; 0x54 - 8010eda: 785a ldrb r2, [r3, #1] - 8010edc: 3001 adds r0, #1 - 8010ede: 2a30 cmp r2, #48 ; 0x30 - 8010ee0: d0f8 beq.n 8010ed4 <_strtod_l+0x1ec> - 8010ee2: f1a2 0331 sub.w r3, r2, #49 ; 0x31 - 8010ee6: 2b08 cmp r3, #8 - 8010ee8: f200 84c1 bhi.w 801186e <_strtod_l+0xb86> - 8010eec: 9b15 ldr r3, [sp, #84] ; 0x54 - 8010eee: 9005 str r0, [sp, #20] - 8010ef0: 2000 movs r0, #0 - 8010ef2: 930b str r3, [sp, #44] ; 0x2c - 8010ef4: 4606 mov r6, r0 - 8010ef6: 3a30 subs r2, #48 ; 0x30 - 8010ef8: f100 0301 add.w r3, r0, #1 - 8010efc: d014 beq.n 8010f28 <_strtod_l+0x240> - 8010efe: 9905 ldr r1, [sp, #20] - 8010f00: 4419 add r1, r3 - 8010f02: 9105 str r1, [sp, #20] - 8010f04: 4633 mov r3, r6 - 8010f06: eb00 0c06 add.w ip, r0, r6 - 8010f0a: 210a movs r1, #10 - 8010f0c: 4563 cmp r3, ip - 8010f0e: d113 bne.n 8010f38 <_strtod_l+0x250> - 8010f10: 1833 adds r3, r6, r0 - 8010f12: 2b08 cmp r3, #8 - 8010f14: f106 0601 add.w r6, r6, #1 - 8010f18: 4406 add r6, r0 - 8010f1a: dc1a bgt.n 8010f52 <_strtod_l+0x26a> - 8010f1c: 9909 ldr r1, [sp, #36] ; 0x24 - 8010f1e: 230a movs r3, #10 - 8010f20: fb03 2301 mla r3, r3, r1, r2 - 8010f24: 9309 str r3, [sp, #36] ; 0x24 - 8010f26: 2300 movs r3, #0 - 8010f28: 9a15 ldr r2, [sp, #84] ; 0x54 - 8010f2a: 1c51 adds r1, r2, #1 - 8010f2c: 9115 str r1, [sp, #84] ; 0x54 - 8010f2e: 7852 ldrb r2, [r2, #1] - 8010f30: 4618 mov r0, r3 - 8010f32: e7c9 b.n 8010ec8 <_strtod_l+0x1e0> - 8010f34: 4658 mov r0, fp - 8010f36: e7d2 b.n 8010ede <_strtod_l+0x1f6> - 8010f38: 2b08 cmp r3, #8 - 8010f3a: f103 0301 add.w r3, r3, #1 - 8010f3e: dc03 bgt.n 8010f48 <_strtod_l+0x260> - 8010f40: 9f09 ldr r7, [sp, #36] ; 0x24 - 8010f42: 434f muls r7, r1 - 8010f44: 9709 str r7, [sp, #36] ; 0x24 - 8010f46: e7e1 b.n 8010f0c <_strtod_l+0x224> - 8010f48: 2b10 cmp r3, #16 - 8010f4a: bfd8 it le - 8010f4c: fb01 fa0a mulle.w sl, r1, sl - 8010f50: e7dc b.n 8010f0c <_strtod_l+0x224> - 8010f52: 2e10 cmp r6, #16 - 8010f54: bfdc itt le - 8010f56: 230a movle r3, #10 - 8010f58: fb03 2a0a mlale sl, r3, sl, r2 - 8010f5c: e7e3 b.n 8010f26 <_strtod_l+0x23e> - 8010f5e: 2300 movs r3, #0 - 8010f60: 9305 str r3, [sp, #20] - 8010f62: 2301 movs r3, #1 - 8010f64: e780 b.n 8010e68 <_strtod_l+0x180> - 8010f66: f04f 0c00 mov.w ip, #0 - 8010f6a: 1caa adds r2, r5, #2 - 8010f6c: 9215 str r2, [sp, #84] ; 0x54 - 8010f6e: 78aa ldrb r2, [r5, #2] - 8010f70: e788 b.n 8010e84 <_strtod_l+0x19c> - 8010f72: f04f 0c01 mov.w ip, #1 - 8010f76: e7f8 b.n 8010f6a <_strtod_l+0x282> - 8010f78: 08018718 .word 0x08018718 - 8010f7c: 08018714 .word 0x08018714 - 8010f80: 7ff00000 .word 0x7ff00000 - 8010f84: 9a15 ldr r2, [sp, #84] ; 0x54 - 8010f86: 1c51 adds r1, r2, #1 - 8010f88: 9115 str r1, [sp, #84] ; 0x54 - 8010f8a: 7852 ldrb r2, [r2, #1] - 8010f8c: 2a30 cmp r2, #48 ; 0x30 - 8010f8e: d0f9 beq.n 8010f84 <_strtod_l+0x29c> - 8010f90: f1a2 0131 sub.w r1, r2, #49 ; 0x31 - 8010f94: 2908 cmp r1, #8 - 8010f96: f63f af7a bhi.w 8010e8e <_strtod_l+0x1a6> - 8010f9a: 3a30 subs r2, #48 ; 0x30 - 8010f9c: 9208 str r2, [sp, #32] - 8010f9e: 9a15 ldr r2, [sp, #84] ; 0x54 - 8010fa0: 920c str r2, [sp, #48] ; 0x30 - 8010fa2: 9a15 ldr r2, [sp, #84] ; 0x54 - 8010fa4: 1c57 adds r7, r2, #1 - 8010fa6: 9715 str r7, [sp, #84] ; 0x54 - 8010fa8: 7852 ldrb r2, [r2, #1] - 8010faa: f1a2 0e30 sub.w lr, r2, #48 ; 0x30 - 8010fae: f1be 0f09 cmp.w lr, #9 - 8010fb2: d938 bls.n 8011026 <_strtod_l+0x33e> - 8010fb4: 990c ldr r1, [sp, #48] ; 0x30 - 8010fb6: 1a7f subs r7, r7, r1 - 8010fb8: 2f08 cmp r7, #8 - 8010fba: f644 671f movw r7, #19999 ; 0x4e1f - 8010fbe: dc03 bgt.n 8010fc8 <_strtod_l+0x2e0> - 8010fc0: 9908 ldr r1, [sp, #32] - 8010fc2: 428f cmp r7, r1 - 8010fc4: bfa8 it ge - 8010fc6: 460f movge r7, r1 - 8010fc8: f1bc 0f00 cmp.w ip, #0 - 8010fcc: d000 beq.n 8010fd0 <_strtod_l+0x2e8> - 8010fce: 427f negs r7, r7 - 8010fd0: 2e00 cmp r6, #0 - 8010fd2: d14f bne.n 8011074 <_strtod_l+0x38c> - 8010fd4: 9904 ldr r1, [sp, #16] - 8010fd6: 4301 orrs r1, r0 - 8010fd8: f47f aec1 bne.w 8010d5e <_strtod_l+0x76> - 8010fdc: 2b00 cmp r3, #0 - 8010fde: f47f aedb bne.w 8010d98 <_strtod_l+0xb0> - 8010fe2: 2a69 cmp r2, #105 ; 0x69 - 8010fe4: d029 beq.n 801103a <_strtod_l+0x352> - 8010fe6: dc26 bgt.n 8011036 <_strtod_l+0x34e> - 8010fe8: 2a49 cmp r2, #73 ; 0x49 - 8010fea: d026 beq.n 801103a <_strtod_l+0x352> - 8010fec: 2a4e cmp r2, #78 ; 0x4e - 8010fee: f47f aed3 bne.w 8010d98 <_strtod_l+0xb0> - 8010ff2: 499b ldr r1, [pc, #620] ; (8011260 <_strtod_l+0x578>) - 8010ff4: a815 add r0, sp, #84 ; 0x54 - 8010ff6: f002 fff5 bl 8013fe4 <__match> - 8010ffa: 2800 cmp r0, #0 - 8010ffc: f43f aecc beq.w 8010d98 <_strtod_l+0xb0> - 8011000: 9b15 ldr r3, [sp, #84] ; 0x54 - 8011002: 781b ldrb r3, [r3, #0] - 8011004: 2b28 cmp r3, #40 ; 0x28 - 8011006: d12f bne.n 8011068 <_strtod_l+0x380> - 8011008: 4996 ldr r1, [pc, #600] ; (8011264 <_strtod_l+0x57c>) - 801100a: aa18 add r2, sp, #96 ; 0x60 - 801100c: a815 add r0, sp, #84 ; 0x54 - 801100e: f002 fffd bl 801400c <__hexnan> - 8011012: 2805 cmp r0, #5 - 8011014: d128 bne.n 8011068 <_strtod_l+0x380> - 8011016: 9b19 ldr r3, [sp, #100] ; 0x64 - 8011018: f8dd 8060 ldr.w r8, [sp, #96] ; 0x60 - 801101c: f043 49ff orr.w r9, r3, #2139095040 ; 0x7f800000 - 8011020: f449 09e0 orr.w r9, r9, #7340032 ; 0x700000 - 8011024: e69b b.n 8010d5e <_strtod_l+0x76> - 8011026: 9f08 ldr r7, [sp, #32] - 8011028: 210a movs r1, #10 - 801102a: fb01 2107 mla r1, r1, r7, r2 - 801102e: f1a1 0230 sub.w r2, r1, #48 ; 0x30 - 8011032: 9208 str r2, [sp, #32] - 8011034: e7b5 b.n 8010fa2 <_strtod_l+0x2ba> - 8011036: 2a6e cmp r2, #110 ; 0x6e - 8011038: e7d9 b.n 8010fee <_strtod_l+0x306> - 801103a: 498b ldr r1, [pc, #556] ; (8011268 <_strtod_l+0x580>) - 801103c: a815 add r0, sp, #84 ; 0x54 - 801103e: f002 ffd1 bl 8013fe4 <__match> - 8011042: 2800 cmp r0, #0 - 8011044: f43f aea8 beq.w 8010d98 <_strtod_l+0xb0> - 8011048: 9b15 ldr r3, [sp, #84] ; 0x54 - 801104a: 4988 ldr r1, [pc, #544] ; (801126c <_strtod_l+0x584>) - 801104c: 3b01 subs r3, #1 - 801104e: a815 add r0, sp, #84 ; 0x54 - 8011050: 9315 str r3, [sp, #84] ; 0x54 - 8011052: f002 ffc7 bl 8013fe4 <__match> - 8011056: b910 cbnz r0, 801105e <_strtod_l+0x376> - 8011058: 9b15 ldr r3, [sp, #84] ; 0x54 - 801105a: 3301 adds r3, #1 - 801105c: 9315 str r3, [sp, #84] ; 0x54 - 801105e: f8df 921c ldr.w r9, [pc, #540] ; 801127c <_strtod_l+0x594> - 8011062: f04f 0800 mov.w r8, #0 - 8011066: e67a b.n 8010d5e <_strtod_l+0x76> - 8011068: 4881 ldr r0, [pc, #516] ; (8011270 <_strtod_l+0x588>) - 801106a: f001 fe21 bl 8012cb0 - 801106e: ec59 8b10 vmov r8, r9, d0 - 8011072: e674 b.n 8010d5e <_strtod_l+0x76> - 8011074: 9b05 ldr r3, [sp, #20] - 8011076: 9809 ldr r0, [sp, #36] ; 0x24 - 8011078: 1afb subs r3, r7, r3 - 801107a: f1bb 0f00 cmp.w fp, #0 - 801107e: bf08 it eq - 8011080: 46b3 moveq fp, r6 - 8011082: 2e10 cmp r6, #16 - 8011084: 9308 str r3, [sp, #32] - 8011086: 4635 mov r5, r6 - 8011088: bfa8 it ge - 801108a: 2510 movge r5, #16 - 801108c: f7ef fa3a bl 8000504 <__aeabi_ui2d> - 8011090: 2e09 cmp r6, #9 - 8011092: 4680 mov r8, r0 - 8011094: 4689 mov r9, r1 - 8011096: dd13 ble.n 80110c0 <_strtod_l+0x3d8> - 8011098: 4b76 ldr r3, [pc, #472] ; (8011274 <_strtod_l+0x58c>) - 801109a: eb03 03c5 add.w r3, r3, r5, lsl #3 - 801109e: e953 2312 ldrd r2, r3, [r3, #-72] ; 0x48 - 80110a2: f7ef faa9 bl 80005f8 <__aeabi_dmul> - 80110a6: 4680 mov r8, r0 - 80110a8: 4650 mov r0, sl - 80110aa: 4689 mov r9, r1 - 80110ac: f7ef fa2a bl 8000504 <__aeabi_ui2d> - 80110b0: 4602 mov r2, r0 - 80110b2: 460b mov r3, r1 - 80110b4: 4640 mov r0, r8 - 80110b6: 4649 mov r1, r9 - 80110b8: f7ef f8e8 bl 800028c <__adddf3> - 80110bc: 4680 mov r8, r0 - 80110be: 4689 mov r9, r1 - 80110c0: 2e0f cmp r6, #15 - 80110c2: dc38 bgt.n 8011136 <_strtod_l+0x44e> - 80110c4: 9b08 ldr r3, [sp, #32] - 80110c6: 2b00 cmp r3, #0 - 80110c8: f43f ae49 beq.w 8010d5e <_strtod_l+0x76> - 80110cc: dd24 ble.n 8011118 <_strtod_l+0x430> - 80110ce: 2b16 cmp r3, #22 - 80110d0: dc0b bgt.n 80110ea <_strtod_l+0x402> - 80110d2: 4968 ldr r1, [pc, #416] ; (8011274 <_strtod_l+0x58c>) - 80110d4: eb01 01c3 add.w r1, r1, r3, lsl #3 - 80110d8: e9d1 0100 ldrd r0, r1, [r1] - 80110dc: 4642 mov r2, r8 - 80110de: 464b mov r3, r9 - 80110e0: f7ef fa8a bl 80005f8 <__aeabi_dmul> - 80110e4: 4680 mov r8, r0 - 80110e6: 4689 mov r9, r1 - 80110e8: e639 b.n 8010d5e <_strtod_l+0x76> - 80110ea: 9a08 ldr r2, [sp, #32] - 80110ec: f1c6 0325 rsb r3, r6, #37 ; 0x25 - 80110f0: 4293 cmp r3, r2 - 80110f2: db20 blt.n 8011136 <_strtod_l+0x44e> - 80110f4: 4c5f ldr r4, [pc, #380] ; (8011274 <_strtod_l+0x58c>) - 80110f6: f1c6 060f rsb r6, r6, #15 - 80110fa: eb04 01c6 add.w r1, r4, r6, lsl #3 - 80110fe: 4642 mov r2, r8 - 8011100: 464b mov r3, r9 - 8011102: e9d1 0100 ldrd r0, r1, [r1] - 8011106: f7ef fa77 bl 80005f8 <__aeabi_dmul> - 801110a: 9b08 ldr r3, [sp, #32] - 801110c: 1b9e subs r6, r3, r6 - 801110e: eb04 04c6 add.w r4, r4, r6, lsl #3 - 8011112: e9d4 2300 ldrd r2, r3, [r4] - 8011116: e7e3 b.n 80110e0 <_strtod_l+0x3f8> - 8011118: 9b08 ldr r3, [sp, #32] - 801111a: 3316 adds r3, #22 - 801111c: db0b blt.n 8011136 <_strtod_l+0x44e> - 801111e: 9b05 ldr r3, [sp, #20] - 8011120: 1bdf subs r7, r3, r7 - 8011122: 4b54 ldr r3, [pc, #336] ; (8011274 <_strtod_l+0x58c>) - 8011124: eb03 07c7 add.w r7, r3, r7, lsl #3 - 8011128: e9d7 2300 ldrd r2, r3, [r7] - 801112c: 4640 mov r0, r8 - 801112e: 4649 mov r1, r9 - 8011130: f7ef fb8c bl 800084c <__aeabi_ddiv> - 8011134: e7d6 b.n 80110e4 <_strtod_l+0x3fc> - 8011136: 9b08 ldr r3, [sp, #32] - 8011138: 1b75 subs r5, r6, r5 - 801113a: 441d add r5, r3 - 801113c: 2d00 cmp r5, #0 - 801113e: dd70 ble.n 8011222 <_strtod_l+0x53a> - 8011140: f015 030f ands.w r3, r5, #15 - 8011144: d00a beq.n 801115c <_strtod_l+0x474> - 8011146: 494b ldr r1, [pc, #300] ; (8011274 <_strtod_l+0x58c>) - 8011148: eb01 01c3 add.w r1, r1, r3, lsl #3 - 801114c: 4642 mov r2, r8 - 801114e: 464b mov r3, r9 - 8011150: e9d1 0100 ldrd r0, r1, [r1] - 8011154: f7ef fa50 bl 80005f8 <__aeabi_dmul> - 8011158: 4680 mov r8, r0 - 801115a: 4689 mov r9, r1 - 801115c: f035 050f bics.w r5, r5, #15 - 8011160: d04d beq.n 80111fe <_strtod_l+0x516> - 8011162: f5b5 7f9a cmp.w r5, #308 ; 0x134 - 8011166: dd22 ble.n 80111ae <_strtod_l+0x4c6> - 8011168: 2500 movs r5, #0 - 801116a: 46ab mov fp, r5 - 801116c: 9509 str r5, [sp, #36] ; 0x24 - 801116e: 9505 str r5, [sp, #20] - 8011170: 2322 movs r3, #34 ; 0x22 - 8011172: f8df 9108 ldr.w r9, [pc, #264] ; 801127c <_strtod_l+0x594> - 8011176: 6023 str r3, [r4, #0] - 8011178: f04f 0800 mov.w r8, #0 - 801117c: 9b09 ldr r3, [sp, #36] ; 0x24 - 801117e: 2b00 cmp r3, #0 - 8011180: f43f aded beq.w 8010d5e <_strtod_l+0x76> - 8011184: 9916 ldr r1, [sp, #88] ; 0x58 - 8011186: 4620 mov r0, r4 - 8011188: f003 f82e bl 80141e8 <_Bfree> - 801118c: 9905 ldr r1, [sp, #20] - 801118e: 4620 mov r0, r4 - 8011190: f003 f82a bl 80141e8 <_Bfree> - 8011194: 4659 mov r1, fp - 8011196: 4620 mov r0, r4 - 8011198: f003 f826 bl 80141e8 <_Bfree> - 801119c: 9909 ldr r1, [sp, #36] ; 0x24 - 801119e: 4620 mov r0, r4 - 80111a0: f003 f822 bl 80141e8 <_Bfree> - 80111a4: 4629 mov r1, r5 - 80111a6: 4620 mov r0, r4 - 80111a8: f003 f81e bl 80141e8 <_Bfree> - 80111ac: e5d7 b.n 8010d5e <_strtod_l+0x76> - 80111ae: 4b32 ldr r3, [pc, #200] ; (8011278 <_strtod_l+0x590>) - 80111b0: 9304 str r3, [sp, #16] - 80111b2: 2300 movs r3, #0 - 80111b4: 112d asrs r5, r5, #4 - 80111b6: 4640 mov r0, r8 - 80111b8: 4649 mov r1, r9 - 80111ba: 469a mov sl, r3 - 80111bc: 2d01 cmp r5, #1 - 80111be: dc21 bgt.n 8011204 <_strtod_l+0x51c> - 80111c0: b10b cbz r3, 80111c6 <_strtod_l+0x4de> - 80111c2: 4680 mov r8, r0 - 80111c4: 4689 mov r9, r1 - 80111c6: 492c ldr r1, [pc, #176] ; (8011278 <_strtod_l+0x590>) - 80111c8: f1a9 7954 sub.w r9, r9, #55574528 ; 0x3500000 - 80111cc: eb01 01ca add.w r1, r1, sl, lsl #3 - 80111d0: 4642 mov r2, r8 - 80111d2: 464b mov r3, r9 - 80111d4: e9d1 0100 ldrd r0, r1, [r1] - 80111d8: f7ef fa0e bl 80005f8 <__aeabi_dmul> - 80111dc: 4b27 ldr r3, [pc, #156] ; (801127c <_strtod_l+0x594>) - 80111de: 460a mov r2, r1 - 80111e0: 400b ands r3, r1 - 80111e2: 4927 ldr r1, [pc, #156] ; (8011280 <_strtod_l+0x598>) - 80111e4: 428b cmp r3, r1 - 80111e6: 4680 mov r8, r0 - 80111e8: d8be bhi.n 8011168 <_strtod_l+0x480> - 80111ea: f5a1 1180 sub.w r1, r1, #1048576 ; 0x100000 - 80111ee: 428b cmp r3, r1 - 80111f0: bf86 itte hi - 80111f2: f8df 9090 ldrhi.w r9, [pc, #144] ; 8011284 <_strtod_l+0x59c> - 80111f6: f04f 38ff movhi.w r8, #4294967295 - 80111fa: f102 7954 addls.w r9, r2, #55574528 ; 0x3500000 - 80111fe: 2300 movs r3, #0 - 8011200: 9304 str r3, [sp, #16] - 8011202: e07b b.n 80112fc <_strtod_l+0x614> - 8011204: 07ea lsls r2, r5, #31 - 8011206: d505 bpl.n 8011214 <_strtod_l+0x52c> - 8011208: 9b04 ldr r3, [sp, #16] - 801120a: e9d3 2300 ldrd r2, r3, [r3] - 801120e: f7ef f9f3 bl 80005f8 <__aeabi_dmul> - 8011212: 2301 movs r3, #1 - 8011214: 9a04 ldr r2, [sp, #16] - 8011216: 3208 adds r2, #8 - 8011218: f10a 0a01 add.w sl, sl, #1 - 801121c: 106d asrs r5, r5, #1 - 801121e: 9204 str r2, [sp, #16] - 8011220: e7cc b.n 80111bc <_strtod_l+0x4d4> - 8011222: d0ec beq.n 80111fe <_strtod_l+0x516> - 8011224: 426d negs r5, r5 - 8011226: f015 020f ands.w r2, r5, #15 - 801122a: d00a beq.n 8011242 <_strtod_l+0x55a> - 801122c: 4b11 ldr r3, [pc, #68] ; (8011274 <_strtod_l+0x58c>) - 801122e: eb03 03c2 add.w r3, r3, r2, lsl #3 - 8011232: 4640 mov r0, r8 - 8011234: 4649 mov r1, r9 - 8011236: e9d3 2300 ldrd r2, r3, [r3] - 801123a: f7ef fb07 bl 800084c <__aeabi_ddiv> - 801123e: 4680 mov r8, r0 - 8011240: 4689 mov r9, r1 - 8011242: 112d asrs r5, r5, #4 - 8011244: d0db beq.n 80111fe <_strtod_l+0x516> - 8011246: 2d1f cmp r5, #31 - 8011248: dd1e ble.n 8011288 <_strtod_l+0x5a0> - 801124a: 2500 movs r5, #0 - 801124c: 46ab mov fp, r5 - 801124e: 9509 str r5, [sp, #36] ; 0x24 - 8011250: 9505 str r5, [sp, #20] - 8011252: 2322 movs r3, #34 ; 0x22 - 8011254: f04f 0800 mov.w r8, #0 - 8011258: f04f 0900 mov.w r9, #0 - 801125c: 6023 str r3, [r4, #0] - 801125e: e78d b.n 801117c <_strtod_l+0x494> - 8011260: 08018876 .word 0x08018876 - 8011264: 0801872c .word 0x0801872c - 8011268: 0801886e .word 0x0801886e - 801126c: 0801895a .word 0x0801895a - 8011270: 08018956 .word 0x08018956 - 8011274: 08018ab0 .word 0x08018ab0 - 8011278: 08018a88 .word 0x08018a88 - 801127c: 7ff00000 .word 0x7ff00000 - 8011280: 7ca00000 .word 0x7ca00000 - 8011284: 7fefffff .word 0x7fefffff - 8011288: f015 0310 ands.w r3, r5, #16 - 801128c: bf18 it ne - 801128e: 236a movne r3, #106 ; 0x6a - 8011290: f8df a3a0 ldr.w sl, [pc, #928] ; 8011634 <_strtod_l+0x94c> - 8011294: 9304 str r3, [sp, #16] - 8011296: 4640 mov r0, r8 - 8011298: 4649 mov r1, r9 - 801129a: 2300 movs r3, #0 - 801129c: 07ea lsls r2, r5, #31 - 801129e: d504 bpl.n 80112aa <_strtod_l+0x5c2> - 80112a0: e9da 2300 ldrd r2, r3, [sl] - 80112a4: f7ef f9a8 bl 80005f8 <__aeabi_dmul> - 80112a8: 2301 movs r3, #1 - 80112aa: 106d asrs r5, r5, #1 - 80112ac: f10a 0a08 add.w sl, sl, #8 - 80112b0: d1f4 bne.n 801129c <_strtod_l+0x5b4> - 80112b2: b10b cbz r3, 80112b8 <_strtod_l+0x5d0> - 80112b4: 4680 mov r8, r0 - 80112b6: 4689 mov r9, r1 - 80112b8: 9b04 ldr r3, [sp, #16] - 80112ba: b1bb cbz r3, 80112ec <_strtod_l+0x604> - 80112bc: f3c9 520a ubfx r2, r9, #20, #11 - 80112c0: f1c2 036b rsb r3, r2, #107 ; 0x6b - 80112c4: 2b00 cmp r3, #0 - 80112c6: 4649 mov r1, r9 - 80112c8: dd10 ble.n 80112ec <_strtod_l+0x604> - 80112ca: 2b1f cmp r3, #31 - 80112cc: f340 811e ble.w 801150c <_strtod_l+0x824> - 80112d0: 2b34 cmp r3, #52 ; 0x34 - 80112d2: bfde ittt le - 80112d4: f04f 33ff movle.w r3, #4294967295 - 80112d8: f1c2 024b rsble r2, r2, #75 ; 0x4b - 80112dc: 4093 lslle r3, r2 - 80112de: f04f 0800 mov.w r8, #0 - 80112e2: bfcc ite gt - 80112e4: f04f 795c movgt.w r9, #57671680 ; 0x3700000 - 80112e8: ea03 0901 andle.w r9, r3, r1 - 80112ec: 2200 movs r2, #0 - 80112ee: 2300 movs r3, #0 - 80112f0: 4640 mov r0, r8 - 80112f2: 4649 mov r1, r9 - 80112f4: f7ef fbe8 bl 8000ac8 <__aeabi_dcmpeq> - 80112f8: 2800 cmp r0, #0 - 80112fa: d1a6 bne.n 801124a <_strtod_l+0x562> - 80112fc: 9b09 ldr r3, [sp, #36] ; 0x24 - 80112fe: 9300 str r3, [sp, #0] - 8011300: 990b ldr r1, [sp, #44] ; 0x2c - 8011302: 4633 mov r3, r6 - 8011304: 465a mov r2, fp - 8011306: 4620 mov r0, r4 - 8011308: f002 ffd6 bl 80142b8 <__s2b> - 801130c: 9009 str r0, [sp, #36] ; 0x24 - 801130e: 2800 cmp r0, #0 - 8011310: f43f af2a beq.w 8011168 <_strtod_l+0x480> - 8011314: 9a08 ldr r2, [sp, #32] - 8011316: 9b05 ldr r3, [sp, #20] - 8011318: 2a00 cmp r2, #0 - 801131a: eba3 0307 sub.w r3, r3, r7 - 801131e: bfa8 it ge - 8011320: 2300 movge r3, #0 - 8011322: 930c str r3, [sp, #48] ; 0x30 - 8011324: 2500 movs r5, #0 - 8011326: ea22 73e2 bic.w r3, r2, r2, asr #31 - 801132a: 9312 str r3, [sp, #72] ; 0x48 - 801132c: 46ab mov fp, r5 - 801132e: 9b09 ldr r3, [sp, #36] ; 0x24 - 8011330: 4620 mov r0, r4 - 8011332: 6859 ldr r1, [r3, #4] - 8011334: f002 ff18 bl 8014168 <_Balloc> - 8011338: 9005 str r0, [sp, #20] - 801133a: 2800 cmp r0, #0 - 801133c: f43f af18 beq.w 8011170 <_strtod_l+0x488> - 8011340: 9b09 ldr r3, [sp, #36] ; 0x24 - 8011342: 691a ldr r2, [r3, #16] - 8011344: 3202 adds r2, #2 - 8011346: f103 010c add.w r1, r3, #12 - 801134a: 0092 lsls r2, r2, #2 - 801134c: 300c adds r0, #12 - 801134e: f001 fca0 bl 8012c92 - 8011352: ec49 8b10 vmov d0, r8, r9 - 8011356: aa18 add r2, sp, #96 ; 0x60 - 8011358: a917 add r1, sp, #92 ; 0x5c - 801135a: 4620 mov r0, r4 - 801135c: f003 fae0 bl 8014920 <__d2b> - 8011360: ec49 8b18 vmov d8, r8, r9 - 8011364: 9016 str r0, [sp, #88] ; 0x58 - 8011366: 2800 cmp r0, #0 - 8011368: f43f af02 beq.w 8011170 <_strtod_l+0x488> - 801136c: 2101 movs r1, #1 - 801136e: 4620 mov r0, r4 - 8011370: f003 f83a bl 80143e8 <__i2b> - 8011374: 4683 mov fp, r0 - 8011376: 2800 cmp r0, #0 - 8011378: f43f aefa beq.w 8011170 <_strtod_l+0x488> - 801137c: 9e17 ldr r6, [sp, #92] ; 0x5c - 801137e: 9a18 ldr r2, [sp, #96] ; 0x60 - 8011380: 2e00 cmp r6, #0 - 8011382: bfab itete ge - 8011384: 9b0c ldrge r3, [sp, #48] ; 0x30 - 8011386: 9b12 ldrlt r3, [sp, #72] ; 0x48 - 8011388: 9f12 ldrge r7, [sp, #72] ; 0x48 - 801138a: f8dd a030 ldrlt.w sl, [sp, #48] ; 0x30 - 801138e: bfac ite ge - 8011390: eb06 0a03 addge.w sl, r6, r3 - 8011394: 1b9f sublt r7, r3, r6 - 8011396: 9b04 ldr r3, [sp, #16] - 8011398: 1af6 subs r6, r6, r3 - 801139a: 4416 add r6, r2 - 801139c: 4ba0 ldr r3, [pc, #640] ; (8011620 <_strtod_l+0x938>) - 801139e: 3e01 subs r6, #1 - 80113a0: 429e cmp r6, r3 - 80113a2: f1c2 0236 rsb r2, r2, #54 ; 0x36 - 80113a6: f280 80c4 bge.w 8011532 <_strtod_l+0x84a> - 80113aa: 1b9b subs r3, r3, r6 - 80113ac: 2b1f cmp r3, #31 - 80113ae: eba2 0203 sub.w r2, r2, r3 - 80113b2: f04f 0101 mov.w r1, #1 - 80113b6: f300 80b0 bgt.w 801151a <_strtod_l+0x832> - 80113ba: fa01 f303 lsl.w r3, r1, r3 - 80113be: 930e str r3, [sp, #56] ; 0x38 - 80113c0: 2300 movs r3, #0 - 80113c2: 930d str r3, [sp, #52] ; 0x34 - 80113c4: eb0a 0602 add.w r6, sl, r2 - 80113c8: 9b04 ldr r3, [sp, #16] - 80113ca: 45b2 cmp sl, r6 - 80113cc: 4417 add r7, r2 - 80113ce: 441f add r7, r3 - 80113d0: 4653 mov r3, sl - 80113d2: bfa8 it ge - 80113d4: 4633 movge r3, r6 - 80113d6: 42bb cmp r3, r7 - 80113d8: bfa8 it ge - 80113da: 463b movge r3, r7 - 80113dc: 2b00 cmp r3, #0 - 80113de: bfc2 ittt gt - 80113e0: 1af6 subgt r6, r6, r3 - 80113e2: 1aff subgt r7, r7, r3 - 80113e4: ebaa 0a03 subgt.w sl, sl, r3 - 80113e8: 9b0c ldr r3, [sp, #48] ; 0x30 - 80113ea: 2b00 cmp r3, #0 - 80113ec: dd17 ble.n 801141e <_strtod_l+0x736> - 80113ee: 4659 mov r1, fp - 80113f0: 461a mov r2, r3 - 80113f2: 4620 mov r0, r4 - 80113f4: f003 f8b8 bl 8014568 <__pow5mult> - 80113f8: 4683 mov fp, r0 - 80113fa: 2800 cmp r0, #0 - 80113fc: f43f aeb8 beq.w 8011170 <_strtod_l+0x488> - 8011400: 4601 mov r1, r0 - 8011402: 9a16 ldr r2, [sp, #88] ; 0x58 - 8011404: 4620 mov r0, r4 - 8011406: f003 f805 bl 8014414 <__multiply> - 801140a: 900b str r0, [sp, #44] ; 0x2c - 801140c: 2800 cmp r0, #0 - 801140e: f43f aeaf beq.w 8011170 <_strtod_l+0x488> - 8011412: 9916 ldr r1, [sp, #88] ; 0x58 - 8011414: 4620 mov r0, r4 - 8011416: f002 fee7 bl 80141e8 <_Bfree> - 801141a: 9b0b ldr r3, [sp, #44] ; 0x2c - 801141c: 9316 str r3, [sp, #88] ; 0x58 - 801141e: 2e00 cmp r6, #0 - 8011420: f300 808c bgt.w 801153c <_strtod_l+0x854> - 8011424: 9b08 ldr r3, [sp, #32] - 8011426: 2b00 cmp r3, #0 - 8011428: dd08 ble.n 801143c <_strtod_l+0x754> - 801142a: 9a12 ldr r2, [sp, #72] ; 0x48 - 801142c: 9905 ldr r1, [sp, #20] - 801142e: 4620 mov r0, r4 - 8011430: f003 f89a bl 8014568 <__pow5mult> - 8011434: 9005 str r0, [sp, #20] - 8011436: 2800 cmp r0, #0 - 8011438: f43f ae9a beq.w 8011170 <_strtod_l+0x488> - 801143c: 2f00 cmp r7, #0 - 801143e: dd08 ble.n 8011452 <_strtod_l+0x76a> - 8011440: 9905 ldr r1, [sp, #20] - 8011442: 463a mov r2, r7 - 8011444: 4620 mov r0, r4 - 8011446: f003 f8e9 bl 801461c <__lshift> - 801144a: 9005 str r0, [sp, #20] - 801144c: 2800 cmp r0, #0 - 801144e: f43f ae8f beq.w 8011170 <_strtod_l+0x488> - 8011452: f1ba 0f00 cmp.w sl, #0 - 8011456: dd08 ble.n 801146a <_strtod_l+0x782> - 8011458: 4659 mov r1, fp - 801145a: 4652 mov r2, sl - 801145c: 4620 mov r0, r4 - 801145e: f003 f8dd bl 801461c <__lshift> - 8011462: 4683 mov fp, r0 - 8011464: 2800 cmp r0, #0 - 8011466: f43f ae83 beq.w 8011170 <_strtod_l+0x488> - 801146a: 9a05 ldr r2, [sp, #20] - 801146c: 9916 ldr r1, [sp, #88] ; 0x58 - 801146e: 4620 mov r0, r4 - 8011470: f003 f95c bl 801472c <__mdiff> - 8011474: 4605 mov r5, r0 - 8011476: 2800 cmp r0, #0 - 8011478: f43f ae7a beq.w 8011170 <_strtod_l+0x488> - 801147c: 68c3 ldr r3, [r0, #12] - 801147e: 930b str r3, [sp, #44] ; 0x2c - 8011480: 2300 movs r3, #0 - 8011482: 60c3 str r3, [r0, #12] - 8011484: 4659 mov r1, fp - 8011486: f003 f935 bl 80146f4 <__mcmp> - 801148a: 2800 cmp r0, #0 - 801148c: da60 bge.n 8011550 <_strtod_l+0x868> - 801148e: 9b0b ldr r3, [sp, #44] ; 0x2c - 8011490: ea53 0308 orrs.w r3, r3, r8 - 8011494: f040 8084 bne.w 80115a0 <_strtod_l+0x8b8> - 8011498: f3c9 0313 ubfx r3, r9, #0, #20 - 801149c: 2b00 cmp r3, #0 - 801149e: d17f bne.n 80115a0 <_strtod_l+0x8b8> - 80114a0: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 - 80114a4: 0d1b lsrs r3, r3, #20 - 80114a6: 051b lsls r3, r3, #20 - 80114a8: f1b3 6fd6 cmp.w r3, #112197632 ; 0x6b00000 - 80114ac: d978 bls.n 80115a0 <_strtod_l+0x8b8> - 80114ae: 696b ldr r3, [r5, #20] - 80114b0: b913 cbnz r3, 80114b8 <_strtod_l+0x7d0> - 80114b2: 692b ldr r3, [r5, #16] - 80114b4: 2b01 cmp r3, #1 - 80114b6: dd73 ble.n 80115a0 <_strtod_l+0x8b8> - 80114b8: 4629 mov r1, r5 - 80114ba: 2201 movs r2, #1 - 80114bc: 4620 mov r0, r4 - 80114be: f003 f8ad bl 801461c <__lshift> - 80114c2: 4659 mov r1, fp - 80114c4: 4605 mov r5, r0 - 80114c6: f003 f915 bl 80146f4 <__mcmp> - 80114ca: 2800 cmp r0, #0 - 80114cc: dd68 ble.n 80115a0 <_strtod_l+0x8b8> - 80114ce: 9904 ldr r1, [sp, #16] - 80114d0: 4a54 ldr r2, [pc, #336] ; (8011624 <_strtod_l+0x93c>) - 80114d2: 464b mov r3, r9 - 80114d4: 2900 cmp r1, #0 - 80114d6: f000 8084 beq.w 80115e2 <_strtod_l+0x8fa> - 80114da: ea02 0109 and.w r1, r2, r9 - 80114de: f1b1 6fd6 cmp.w r1, #112197632 ; 0x6b00000 - 80114e2: dc7e bgt.n 80115e2 <_strtod_l+0x8fa> - 80114e4: f1b1 7f5c cmp.w r1, #57671680 ; 0x3700000 - 80114e8: f77f aeb3 ble.w 8011252 <_strtod_l+0x56a> - 80114ec: 4b4e ldr r3, [pc, #312] ; (8011628 <_strtod_l+0x940>) - 80114ee: 4640 mov r0, r8 - 80114f0: 4649 mov r1, r9 - 80114f2: 2200 movs r2, #0 - 80114f4: f7ef f880 bl 80005f8 <__aeabi_dmul> - 80114f8: 4b4a ldr r3, [pc, #296] ; (8011624 <_strtod_l+0x93c>) - 80114fa: 400b ands r3, r1 - 80114fc: 4680 mov r8, r0 - 80114fe: 4689 mov r9, r1 - 8011500: 2b00 cmp r3, #0 - 8011502: f47f ae3f bne.w 8011184 <_strtod_l+0x49c> - 8011506: 2322 movs r3, #34 ; 0x22 - 8011508: 6023 str r3, [r4, #0] - 801150a: e63b b.n 8011184 <_strtod_l+0x49c> - 801150c: f04f 32ff mov.w r2, #4294967295 - 8011510: fa02 f303 lsl.w r3, r2, r3 - 8011514: ea03 0808 and.w r8, r3, r8 - 8011518: e6e8 b.n 80112ec <_strtod_l+0x604> - 801151a: f1c6 467f rsb r6, r6, #4278190080 ; 0xff000000 - 801151e: f506 067f add.w r6, r6, #16711680 ; 0xff0000 - 8011522: f506 467b add.w r6, r6, #64256 ; 0xfb00 - 8011526: 36e2 adds r6, #226 ; 0xe2 - 8011528: fa01 f306 lsl.w r3, r1, r6 - 801152c: e9cd 310d strd r3, r1, [sp, #52] ; 0x34 - 8011530: e748 b.n 80113c4 <_strtod_l+0x6dc> - 8011532: 2100 movs r1, #0 - 8011534: 2301 movs r3, #1 - 8011536: e9cd 130d strd r1, r3, [sp, #52] ; 0x34 - 801153a: e743 b.n 80113c4 <_strtod_l+0x6dc> - 801153c: 9916 ldr r1, [sp, #88] ; 0x58 - 801153e: 4632 mov r2, r6 - 8011540: 4620 mov r0, r4 - 8011542: f003 f86b bl 801461c <__lshift> - 8011546: 9016 str r0, [sp, #88] ; 0x58 - 8011548: 2800 cmp r0, #0 - 801154a: f47f af6b bne.w 8011424 <_strtod_l+0x73c> - 801154e: e60f b.n 8011170 <_strtod_l+0x488> - 8011550: 46ca mov sl, r9 - 8011552: d171 bne.n 8011638 <_strtod_l+0x950> - 8011554: 9a0b ldr r2, [sp, #44] ; 0x2c - 8011556: f3c9 0313 ubfx r3, r9, #0, #20 - 801155a: b352 cbz r2, 80115b2 <_strtod_l+0x8ca> - 801155c: 4a33 ldr r2, [pc, #204] ; (801162c <_strtod_l+0x944>) - 801155e: 4293 cmp r3, r2 - 8011560: d12a bne.n 80115b8 <_strtod_l+0x8d0> - 8011562: 9b04 ldr r3, [sp, #16] - 8011564: 4641 mov r1, r8 - 8011566: b1fb cbz r3, 80115a8 <_strtod_l+0x8c0> - 8011568: 4b2e ldr r3, [pc, #184] ; (8011624 <_strtod_l+0x93c>) - 801156a: ea09 0303 and.w r3, r9, r3 - 801156e: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 - 8011572: f04f 32ff mov.w r2, #4294967295 - 8011576: d81a bhi.n 80115ae <_strtod_l+0x8c6> - 8011578: 0d1b lsrs r3, r3, #20 - 801157a: f1c3 036b rsb r3, r3, #107 ; 0x6b - 801157e: fa02 f303 lsl.w r3, r2, r3 - 8011582: 4299 cmp r1, r3 - 8011584: d118 bne.n 80115b8 <_strtod_l+0x8d0> - 8011586: 4b2a ldr r3, [pc, #168] ; (8011630 <_strtod_l+0x948>) - 8011588: 459a cmp sl, r3 - 801158a: d102 bne.n 8011592 <_strtod_l+0x8aa> - 801158c: 3101 adds r1, #1 - 801158e: f43f adef beq.w 8011170 <_strtod_l+0x488> - 8011592: 4b24 ldr r3, [pc, #144] ; (8011624 <_strtod_l+0x93c>) - 8011594: ea0a 0303 and.w r3, sl, r3 - 8011598: f503 1980 add.w r9, r3, #1048576 ; 0x100000 - 801159c: f04f 0800 mov.w r8, #0 - 80115a0: 9b04 ldr r3, [sp, #16] - 80115a2: 2b00 cmp r3, #0 - 80115a4: d1a2 bne.n 80114ec <_strtod_l+0x804> - 80115a6: e5ed b.n 8011184 <_strtod_l+0x49c> - 80115a8: f04f 33ff mov.w r3, #4294967295 - 80115ac: e7e9 b.n 8011582 <_strtod_l+0x89a> - 80115ae: 4613 mov r3, r2 - 80115b0: e7e7 b.n 8011582 <_strtod_l+0x89a> - 80115b2: ea53 0308 orrs.w r3, r3, r8 - 80115b6: d08a beq.n 80114ce <_strtod_l+0x7e6> - 80115b8: 9b0d ldr r3, [sp, #52] ; 0x34 - 80115ba: b1e3 cbz r3, 80115f6 <_strtod_l+0x90e> - 80115bc: ea13 0f0a tst.w r3, sl - 80115c0: d0ee beq.n 80115a0 <_strtod_l+0x8b8> - 80115c2: 9b0b ldr r3, [sp, #44] ; 0x2c - 80115c4: 9a04 ldr r2, [sp, #16] - 80115c6: 4640 mov r0, r8 - 80115c8: 4649 mov r1, r9 - 80115ca: b1c3 cbz r3, 80115fe <_strtod_l+0x916> - 80115cc: f7ff fb6e bl 8010cac - 80115d0: 4602 mov r2, r0 - 80115d2: 460b mov r3, r1 - 80115d4: ec51 0b18 vmov r0, r1, d8 - 80115d8: f7ee fe58 bl 800028c <__adddf3> - 80115dc: 4680 mov r8, r0 - 80115de: 4689 mov r9, r1 - 80115e0: e7de b.n 80115a0 <_strtod_l+0x8b8> - 80115e2: 4013 ands r3, r2 - 80115e4: f5a3 1380 sub.w r3, r3, #1048576 ; 0x100000 - 80115e8: ea6f 5913 mvn.w r9, r3, lsr #20 - 80115ec: ea6f 5909 mvn.w r9, r9, lsl #20 - 80115f0: f04f 38ff mov.w r8, #4294967295 - 80115f4: e7d4 b.n 80115a0 <_strtod_l+0x8b8> - 80115f6: 9b0e ldr r3, [sp, #56] ; 0x38 - 80115f8: ea13 0f08 tst.w r3, r8 - 80115fc: e7e0 b.n 80115c0 <_strtod_l+0x8d8> - 80115fe: f7ff fb55 bl 8010cac - 8011602: 4602 mov r2, r0 - 8011604: 460b mov r3, r1 - 8011606: ec51 0b18 vmov r0, r1, d8 - 801160a: f7ee fe3d bl 8000288 <__aeabi_dsub> - 801160e: 2200 movs r2, #0 - 8011610: 2300 movs r3, #0 - 8011612: 4680 mov r8, r0 - 8011614: 4689 mov r9, r1 - 8011616: f7ef fa57 bl 8000ac8 <__aeabi_dcmpeq> - 801161a: 2800 cmp r0, #0 - 801161c: d0c0 beq.n 80115a0 <_strtod_l+0x8b8> - 801161e: e618 b.n 8011252 <_strtod_l+0x56a> - 8011620: fffffc02 .word 0xfffffc02 - 8011624: 7ff00000 .word 0x7ff00000 - 8011628: 39500000 .word 0x39500000 - 801162c: 000fffff .word 0x000fffff - 8011630: 7fefffff .word 0x7fefffff - 8011634: 08018740 .word 0x08018740 - 8011638: 4659 mov r1, fp - 801163a: 4628 mov r0, r5 - 801163c: f003 f9ca bl 80149d4 <__ratio> - 8011640: ec57 6b10 vmov r6, r7, d0 - 8011644: ee10 0a10 vmov r0, s0 - 8011648: 2200 movs r2, #0 - 801164a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 - 801164e: 4639 mov r1, r7 - 8011650: f7ef fa4e bl 8000af0 <__aeabi_dcmple> - 8011654: 2800 cmp r0, #0 - 8011656: d071 beq.n 801173c <_strtod_l+0xa54> - 8011658: 9b0b ldr r3, [sp, #44] ; 0x2c - 801165a: 2b00 cmp r3, #0 - 801165c: d17c bne.n 8011758 <_strtod_l+0xa70> - 801165e: f1b8 0f00 cmp.w r8, #0 - 8011662: d15a bne.n 801171a <_strtod_l+0xa32> - 8011664: f3c9 0313 ubfx r3, r9, #0, #20 - 8011668: 2b00 cmp r3, #0 - 801166a: d15d bne.n 8011728 <_strtod_l+0xa40> - 801166c: 4b90 ldr r3, [pc, #576] ; (80118b0 <_strtod_l+0xbc8>) - 801166e: 2200 movs r2, #0 - 8011670: 4630 mov r0, r6 - 8011672: 4639 mov r1, r7 - 8011674: f7ef fa32 bl 8000adc <__aeabi_dcmplt> - 8011678: 2800 cmp r0, #0 - 801167a: d15c bne.n 8011736 <_strtod_l+0xa4e> - 801167c: 4630 mov r0, r6 - 801167e: 4639 mov r1, r7 - 8011680: 4b8c ldr r3, [pc, #560] ; (80118b4 <_strtod_l+0xbcc>) - 8011682: 2200 movs r2, #0 - 8011684: f7ee ffb8 bl 80005f8 <__aeabi_dmul> - 8011688: 4606 mov r6, r0 - 801168a: 460f mov r7, r1 - 801168c: f107 4300 add.w r3, r7, #2147483648 ; 0x80000000 - 8011690: 9606 str r6, [sp, #24] - 8011692: 9307 str r3, [sp, #28] - 8011694: e9dd 2306 ldrd r2, r3, [sp, #24] - 8011698: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 - 801169c: 4b86 ldr r3, [pc, #536] ; (80118b8 <_strtod_l+0xbd0>) - 801169e: ea0a 0303 and.w r3, sl, r3 - 80116a2: 930d str r3, [sp, #52] ; 0x34 - 80116a4: 9a0d ldr r2, [sp, #52] ; 0x34 - 80116a6: 4b85 ldr r3, [pc, #532] ; (80118bc <_strtod_l+0xbd4>) - 80116a8: 429a cmp r2, r3 - 80116aa: f040 8090 bne.w 80117ce <_strtod_l+0xae6> - 80116ae: f1aa 7954 sub.w r9, sl, #55574528 ; 0x3500000 - 80116b2: ec49 8b10 vmov d0, r8, r9 - 80116b6: f003 f8c3 bl 8014840 <__ulp> - 80116ba: e9dd 2306 ldrd r2, r3, [sp, #24] - 80116be: ec51 0b10 vmov r0, r1, d0 - 80116c2: f7ee ff99 bl 80005f8 <__aeabi_dmul> - 80116c6: 4642 mov r2, r8 - 80116c8: 464b mov r3, r9 - 80116ca: f7ee fddf bl 800028c <__adddf3> - 80116ce: 460b mov r3, r1 - 80116d0: 4979 ldr r1, [pc, #484] ; (80118b8 <_strtod_l+0xbd0>) - 80116d2: 4a7b ldr r2, [pc, #492] ; (80118c0 <_strtod_l+0xbd8>) - 80116d4: 4019 ands r1, r3 - 80116d6: 4291 cmp r1, r2 - 80116d8: 4680 mov r8, r0 - 80116da: d944 bls.n 8011766 <_strtod_l+0xa7e> - 80116dc: ee18 2a90 vmov r2, s17 - 80116e0: 4b78 ldr r3, [pc, #480] ; (80118c4 <_strtod_l+0xbdc>) - 80116e2: 429a cmp r2, r3 - 80116e4: d104 bne.n 80116f0 <_strtod_l+0xa08> - 80116e6: ee18 3a10 vmov r3, s16 - 80116ea: 3301 adds r3, #1 - 80116ec: f43f ad40 beq.w 8011170 <_strtod_l+0x488> - 80116f0: f8df 91d0 ldr.w r9, [pc, #464] ; 80118c4 <_strtod_l+0xbdc> - 80116f4: f04f 38ff mov.w r8, #4294967295 - 80116f8: 9916 ldr r1, [sp, #88] ; 0x58 - 80116fa: 4620 mov r0, r4 - 80116fc: f002 fd74 bl 80141e8 <_Bfree> - 8011700: 9905 ldr r1, [sp, #20] - 8011702: 4620 mov r0, r4 - 8011704: f002 fd70 bl 80141e8 <_Bfree> - 8011708: 4659 mov r1, fp - 801170a: 4620 mov r0, r4 - 801170c: f002 fd6c bl 80141e8 <_Bfree> - 8011710: 4629 mov r1, r5 - 8011712: 4620 mov r0, r4 - 8011714: f002 fd68 bl 80141e8 <_Bfree> - 8011718: e609 b.n 801132e <_strtod_l+0x646> - 801171a: f1b8 0f01 cmp.w r8, #1 - 801171e: d103 bne.n 8011728 <_strtod_l+0xa40> - 8011720: f1b9 0f00 cmp.w r9, #0 - 8011724: f43f ad95 beq.w 8011252 <_strtod_l+0x56a> - 8011728: ed9f 7b55 vldr d7, [pc, #340] ; 8011880 <_strtod_l+0xb98> - 801172c: 4f60 ldr r7, [pc, #384] ; (80118b0 <_strtod_l+0xbc8>) - 801172e: ed8d 7b06 vstr d7, [sp, #24] - 8011732: 2600 movs r6, #0 - 8011734: e7ae b.n 8011694 <_strtod_l+0x9ac> - 8011736: 4f5f ldr r7, [pc, #380] ; (80118b4 <_strtod_l+0xbcc>) - 8011738: 2600 movs r6, #0 - 801173a: e7a7 b.n 801168c <_strtod_l+0x9a4> - 801173c: 4b5d ldr r3, [pc, #372] ; (80118b4 <_strtod_l+0xbcc>) - 801173e: 4630 mov r0, r6 - 8011740: 4639 mov r1, r7 - 8011742: 2200 movs r2, #0 - 8011744: f7ee ff58 bl 80005f8 <__aeabi_dmul> - 8011748: 9b0b ldr r3, [sp, #44] ; 0x2c - 801174a: 4606 mov r6, r0 - 801174c: 460f mov r7, r1 - 801174e: 2b00 cmp r3, #0 - 8011750: d09c beq.n 801168c <_strtod_l+0x9a4> - 8011752: e9cd 6706 strd r6, r7, [sp, #24] - 8011756: e79d b.n 8011694 <_strtod_l+0x9ac> - 8011758: ed9f 7b4b vldr d7, [pc, #300] ; 8011888 <_strtod_l+0xba0> - 801175c: ed8d 7b06 vstr d7, [sp, #24] - 8011760: ec57 6b17 vmov r6, r7, d7 - 8011764: e796 b.n 8011694 <_strtod_l+0x9ac> - 8011766: f103 7954 add.w r9, r3, #55574528 ; 0x3500000 - 801176a: 9b04 ldr r3, [sp, #16] - 801176c: 46ca mov sl, r9 - 801176e: 2b00 cmp r3, #0 - 8011770: d1c2 bne.n 80116f8 <_strtod_l+0xa10> - 8011772: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 - 8011776: 9a0d ldr r2, [sp, #52] ; 0x34 - 8011778: 0d1b lsrs r3, r3, #20 - 801177a: 051b lsls r3, r3, #20 - 801177c: 429a cmp r2, r3 - 801177e: d1bb bne.n 80116f8 <_strtod_l+0xa10> - 8011780: 4630 mov r0, r6 - 8011782: 4639 mov r1, r7 - 8011784: f7ef fa98 bl 8000cb8 <__aeabi_d2lz> - 8011788: f7ee ff08 bl 800059c <__aeabi_l2d> - 801178c: 4602 mov r2, r0 - 801178e: 460b mov r3, r1 - 8011790: 4630 mov r0, r6 - 8011792: 4639 mov r1, r7 - 8011794: f7ee fd78 bl 8000288 <__aeabi_dsub> - 8011798: 9a0b ldr r2, [sp, #44] ; 0x2c - 801179a: f3c9 0313 ubfx r3, r9, #0, #20 - 801179e: ea43 0308 orr.w r3, r3, r8 - 80117a2: 4313 orrs r3, r2 - 80117a4: 4606 mov r6, r0 - 80117a6: 460f mov r7, r1 - 80117a8: d054 beq.n 8011854 <_strtod_l+0xb6c> - 80117aa: a339 add r3, pc, #228 ; (adr r3, 8011890 <_strtod_l+0xba8>) - 80117ac: e9d3 2300 ldrd r2, r3, [r3] - 80117b0: f7ef f994 bl 8000adc <__aeabi_dcmplt> - 80117b4: 2800 cmp r0, #0 - 80117b6: f47f ace5 bne.w 8011184 <_strtod_l+0x49c> - 80117ba: a337 add r3, pc, #220 ; (adr r3, 8011898 <_strtod_l+0xbb0>) - 80117bc: e9d3 2300 ldrd r2, r3, [r3] - 80117c0: 4630 mov r0, r6 - 80117c2: 4639 mov r1, r7 - 80117c4: f7ef f9a8 bl 8000b18 <__aeabi_dcmpgt> - 80117c8: 2800 cmp r0, #0 - 80117ca: d095 beq.n 80116f8 <_strtod_l+0xa10> - 80117cc: e4da b.n 8011184 <_strtod_l+0x49c> - 80117ce: 9b04 ldr r3, [sp, #16] - 80117d0: b333 cbz r3, 8011820 <_strtod_l+0xb38> - 80117d2: 9b0d ldr r3, [sp, #52] ; 0x34 - 80117d4: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 - 80117d8: d822 bhi.n 8011820 <_strtod_l+0xb38> - 80117da: a331 add r3, pc, #196 ; (adr r3, 80118a0 <_strtod_l+0xbb8>) - 80117dc: e9d3 2300 ldrd r2, r3, [r3] - 80117e0: 4630 mov r0, r6 - 80117e2: 4639 mov r1, r7 - 80117e4: f7ef f984 bl 8000af0 <__aeabi_dcmple> - 80117e8: b1a0 cbz r0, 8011814 <_strtod_l+0xb2c> - 80117ea: 4639 mov r1, r7 - 80117ec: 4630 mov r0, r6 - 80117ee: f7ef f9db bl 8000ba8 <__aeabi_d2uiz> - 80117f2: 2801 cmp r0, #1 - 80117f4: bf38 it cc - 80117f6: 2001 movcc r0, #1 - 80117f8: f7ee fe84 bl 8000504 <__aeabi_ui2d> - 80117fc: 9b0b ldr r3, [sp, #44] ; 0x2c - 80117fe: 4606 mov r6, r0 - 8011800: 460f mov r7, r1 - 8011802: bb23 cbnz r3, 801184e <_strtod_l+0xb66> - 8011804: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8011808: 9010 str r0, [sp, #64] ; 0x40 - 801180a: 9311 str r3, [sp, #68] ; 0x44 - 801180c: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 - 8011810: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 - 8011814: 9b0f ldr r3, [sp, #60] ; 0x3c - 8011816: 9a0d ldr r2, [sp, #52] ; 0x34 - 8011818: f103 63d6 add.w r3, r3, #112197632 ; 0x6b00000 - 801181c: 1a9b subs r3, r3, r2 - 801181e: 930f str r3, [sp, #60] ; 0x3c - 8011820: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 - 8011824: eeb0 0a48 vmov.f32 s0, s16 - 8011828: eef0 0a68 vmov.f32 s1, s17 - 801182c: e9cd 010e strd r0, r1, [sp, #56] ; 0x38 - 8011830: f003 f806 bl 8014840 <__ulp> - 8011834: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 - 8011838: ec53 2b10 vmov r2, r3, d0 - 801183c: f7ee fedc bl 80005f8 <__aeabi_dmul> - 8011840: ec53 2b18 vmov r2, r3, d8 - 8011844: f7ee fd22 bl 800028c <__adddf3> - 8011848: 4680 mov r8, r0 - 801184a: 4689 mov r9, r1 - 801184c: e78d b.n 801176a <_strtod_l+0xa82> - 801184e: e9cd 6710 strd r6, r7, [sp, #64] ; 0x40 - 8011852: e7db b.n 801180c <_strtod_l+0xb24> - 8011854: a314 add r3, pc, #80 ; (adr r3, 80118a8 <_strtod_l+0xbc0>) - 8011856: e9d3 2300 ldrd r2, r3, [r3] - 801185a: f7ef f93f bl 8000adc <__aeabi_dcmplt> - 801185e: e7b3 b.n 80117c8 <_strtod_l+0xae0> - 8011860: 2300 movs r3, #0 - 8011862: 930a str r3, [sp, #40] ; 0x28 - 8011864: 9a13 ldr r2, [sp, #76] ; 0x4c - 8011866: 9b15 ldr r3, [sp, #84] ; 0x54 - 8011868: 6013 str r3, [r2, #0] - 801186a: f7ff ba7c b.w 8010d66 <_strtod_l+0x7e> - 801186e: 2a65 cmp r2, #101 ; 0x65 - 8011870: f43f ab75 beq.w 8010f5e <_strtod_l+0x276> - 8011874: 2a45 cmp r2, #69 ; 0x45 - 8011876: f43f ab72 beq.w 8010f5e <_strtod_l+0x276> - 801187a: 2301 movs r3, #1 - 801187c: f7ff bbaa b.w 8010fd4 <_strtod_l+0x2ec> - 8011880: 00000000 .word 0x00000000 - 8011884: bff00000 .word 0xbff00000 - 8011888: 00000000 .word 0x00000000 - 801188c: 3ff00000 .word 0x3ff00000 - 8011890: 94a03595 .word 0x94a03595 - 8011894: 3fdfffff .word 0x3fdfffff - 8011898: 35afe535 .word 0x35afe535 - 801189c: 3fe00000 .word 0x3fe00000 - 80118a0: ffc00000 .word 0xffc00000 - 80118a4: 41dfffff .word 0x41dfffff - 80118a8: 94a03595 .word 0x94a03595 - 80118ac: 3fcfffff .word 0x3fcfffff - 80118b0: 3ff00000 .word 0x3ff00000 - 80118b4: 3fe00000 .word 0x3fe00000 - 80118b8: 7ff00000 .word 0x7ff00000 - 80118bc: 7fe00000 .word 0x7fe00000 - 80118c0: 7c9fffff .word 0x7c9fffff - 80118c4: 7fefffff .word 0x7fefffff - -080118c8 <_strtod_r>: - 80118c8: 4b01 ldr r3, [pc, #4] ; (80118d0 <_strtod_r+0x8>) - 80118ca: f7ff ba0d b.w 8010ce8 <_strtod_l> - 80118ce: bf00 nop - 80118d0: 20000158 .word 0x20000158 - -080118d4 : - 80118d4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 80118d8: f8df 80c0 ldr.w r8, [pc, #192] ; 801199c - 80118dc: 4b2a ldr r3, [pc, #168] ; (8011988 ) - 80118de: 460a mov r2, r1 - 80118e0: ed2d 8b02 vpush {d8} - 80118e4: 4601 mov r1, r0 - 80118e6: f8d8 0000 ldr.w r0, [r8] - 80118ea: f7ff f9fd bl 8010ce8 <_strtod_l> - 80118ee: ec55 4b10 vmov r4, r5, d0 - 80118f2: ee10 2a10 vmov r2, s0 - 80118f6: ee10 0a10 vmov r0, s0 - 80118fa: 462b mov r3, r5 - 80118fc: 4629 mov r1, r5 - 80118fe: f7ef f915 bl 8000b2c <__aeabi_dcmpun> - 8011902: b190 cbz r0, 801192a - 8011904: 2d00 cmp r5, #0 - 8011906: 4821 ldr r0, [pc, #132] ; (801198c ) - 8011908: da09 bge.n 801191e - 801190a: f001 f9d9 bl 8012cc0 - 801190e: eeb1 8a40 vneg.f32 s16, s0 - 8011912: eeb0 0a48 vmov.f32 s0, s16 - 8011916: ecbd 8b02 vpop {d8} - 801191a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 801191e: ecbd 8b02 vpop {d8} - 8011922: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 8011926: f001 b9cb b.w 8012cc0 - 801192a: 4620 mov r0, r4 - 801192c: 4629 mov r1, r5 - 801192e: f7ef f95b bl 8000be8 <__aeabi_d2f> - 8011932: ee08 0a10 vmov s16, r0 - 8011936: eddf 7a16 vldr s15, [pc, #88] ; 8011990 - 801193a: eeb0 7ac8 vabs.f32 s14, s16 - 801193e: eeb4 7a67 vcmp.f32 s14, s15 - 8011942: eef1 fa10 vmrs APSR_nzcv, fpscr - 8011946: dd11 ble.n 801196c - 8011948: f025 4700 bic.w r7, r5, #2147483648 ; 0x80000000 - 801194c: 4b11 ldr r3, [pc, #68] ; (8011994 ) - 801194e: f04f 32ff mov.w r2, #4294967295 - 8011952: 4620 mov r0, r4 - 8011954: 4639 mov r1, r7 - 8011956: f7ef f8e9 bl 8000b2c <__aeabi_dcmpun> - 801195a: b980 cbnz r0, 801197e - 801195c: 4b0d ldr r3, [pc, #52] ; (8011994 ) - 801195e: f04f 32ff mov.w r2, #4294967295 - 8011962: 4620 mov r0, r4 - 8011964: 4639 mov r1, r7 - 8011966: f7ef f8c3 bl 8000af0 <__aeabi_dcmple> - 801196a: b940 cbnz r0, 801197e - 801196c: ee18 3a10 vmov r3, s16 - 8011970: f013 4fff tst.w r3, #2139095040 ; 0x7f800000 - 8011974: d1cd bne.n 8011912 - 8011976: 4b08 ldr r3, [pc, #32] ; (8011998 ) - 8011978: 402b ands r3, r5 - 801197a: 2b00 cmp r3, #0 - 801197c: d0c9 beq.n 8011912 - 801197e: f8d8 3000 ldr.w r3, [r8] - 8011982: 2222 movs r2, #34 ; 0x22 - 8011984: 601a str r2, [r3, #0] - 8011986: e7c4 b.n 8011912 - 8011988: 20000158 .word 0x20000158 - 801198c: 08018956 .word 0x08018956 - 8011990: 7f7fffff .word 0x7f7fffff - 8011994: 7fefffff .word 0x7fefffff - 8011998: 7ff00000 .word 0x7ff00000 - 801199c: 20000310 .word 0x20000310 - -080119a0 <_strtol_l.constprop.0>: - 80119a0: 2b01 cmp r3, #1 - 80119a2: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 80119a6: d001 beq.n 80119ac <_strtol_l.constprop.0+0xc> - 80119a8: 2b24 cmp r3, #36 ; 0x24 - 80119aa: d906 bls.n 80119ba <_strtol_l.constprop.0+0x1a> - 80119ac: f001 f93c bl 8012c28 <__errno> - 80119b0: 2316 movs r3, #22 - 80119b2: 6003 str r3, [r0, #0] - 80119b4: 2000 movs r0, #0 - 80119b6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80119ba: f8df c0e4 ldr.w ip, [pc, #228] ; 8011aa0 <_strtol_l.constprop.0+0x100> - 80119be: 460d mov r5, r1 - 80119c0: 462e mov r6, r5 - 80119c2: f815 4b01 ldrb.w r4, [r5], #1 - 80119c6: f81c 7004 ldrb.w r7, [ip, r4] - 80119ca: f017 0708 ands.w r7, r7, #8 - 80119ce: d1f7 bne.n 80119c0 <_strtol_l.constprop.0+0x20> - 80119d0: 2c2d cmp r4, #45 ; 0x2d - 80119d2: d132 bne.n 8011a3a <_strtol_l.constprop.0+0x9a> - 80119d4: 782c ldrb r4, [r5, #0] - 80119d6: 2701 movs r7, #1 - 80119d8: 1cb5 adds r5, r6, #2 - 80119da: 2b00 cmp r3, #0 - 80119dc: d05b beq.n 8011a96 <_strtol_l.constprop.0+0xf6> - 80119de: 2b10 cmp r3, #16 - 80119e0: d109 bne.n 80119f6 <_strtol_l.constprop.0+0x56> - 80119e2: 2c30 cmp r4, #48 ; 0x30 - 80119e4: d107 bne.n 80119f6 <_strtol_l.constprop.0+0x56> - 80119e6: 782c ldrb r4, [r5, #0] - 80119e8: f004 04df and.w r4, r4, #223 ; 0xdf - 80119ec: 2c58 cmp r4, #88 ; 0x58 - 80119ee: d14d bne.n 8011a8c <_strtol_l.constprop.0+0xec> - 80119f0: 786c ldrb r4, [r5, #1] - 80119f2: 2310 movs r3, #16 - 80119f4: 3502 adds r5, #2 - 80119f6: f107 4800 add.w r8, r7, #2147483648 ; 0x80000000 - 80119fa: f108 38ff add.w r8, r8, #4294967295 - 80119fe: f04f 0e00 mov.w lr, #0 - 8011a02: fbb8 f9f3 udiv r9, r8, r3 - 8011a06: 4676 mov r6, lr - 8011a08: fb03 8a19 mls sl, r3, r9, r8 - 8011a0c: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 - 8011a10: f1bc 0f09 cmp.w ip, #9 - 8011a14: d816 bhi.n 8011a44 <_strtol_l.constprop.0+0xa4> - 8011a16: 4664 mov r4, ip - 8011a18: 42a3 cmp r3, r4 - 8011a1a: dd24 ble.n 8011a66 <_strtol_l.constprop.0+0xc6> - 8011a1c: f1be 3fff cmp.w lr, #4294967295 - 8011a20: d008 beq.n 8011a34 <_strtol_l.constprop.0+0x94> - 8011a22: 45b1 cmp r9, r6 - 8011a24: d31c bcc.n 8011a60 <_strtol_l.constprop.0+0xc0> - 8011a26: d101 bne.n 8011a2c <_strtol_l.constprop.0+0x8c> - 8011a28: 45a2 cmp sl, r4 - 8011a2a: db19 blt.n 8011a60 <_strtol_l.constprop.0+0xc0> - 8011a2c: fb06 4603 mla r6, r6, r3, r4 - 8011a30: f04f 0e01 mov.w lr, #1 - 8011a34: f815 4b01 ldrb.w r4, [r5], #1 - 8011a38: e7e8 b.n 8011a0c <_strtol_l.constprop.0+0x6c> - 8011a3a: 2c2b cmp r4, #43 ; 0x2b - 8011a3c: bf04 itt eq - 8011a3e: 782c ldrbeq r4, [r5, #0] - 8011a40: 1cb5 addeq r5, r6, #2 - 8011a42: e7ca b.n 80119da <_strtol_l.constprop.0+0x3a> - 8011a44: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 - 8011a48: f1bc 0f19 cmp.w ip, #25 - 8011a4c: d801 bhi.n 8011a52 <_strtol_l.constprop.0+0xb2> - 8011a4e: 3c37 subs r4, #55 ; 0x37 - 8011a50: e7e2 b.n 8011a18 <_strtol_l.constprop.0+0x78> - 8011a52: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 - 8011a56: f1bc 0f19 cmp.w ip, #25 - 8011a5a: d804 bhi.n 8011a66 <_strtol_l.constprop.0+0xc6> - 8011a5c: 3c57 subs r4, #87 ; 0x57 - 8011a5e: e7db b.n 8011a18 <_strtol_l.constprop.0+0x78> - 8011a60: f04f 3eff mov.w lr, #4294967295 - 8011a64: e7e6 b.n 8011a34 <_strtol_l.constprop.0+0x94> - 8011a66: f1be 3fff cmp.w lr, #4294967295 - 8011a6a: d105 bne.n 8011a78 <_strtol_l.constprop.0+0xd8> - 8011a6c: 2322 movs r3, #34 ; 0x22 - 8011a6e: 6003 str r3, [r0, #0] - 8011a70: 4646 mov r6, r8 - 8011a72: b942 cbnz r2, 8011a86 <_strtol_l.constprop.0+0xe6> - 8011a74: 4630 mov r0, r6 - 8011a76: e79e b.n 80119b6 <_strtol_l.constprop.0+0x16> - 8011a78: b107 cbz r7, 8011a7c <_strtol_l.constprop.0+0xdc> - 8011a7a: 4276 negs r6, r6 - 8011a7c: 2a00 cmp r2, #0 - 8011a7e: d0f9 beq.n 8011a74 <_strtol_l.constprop.0+0xd4> - 8011a80: f1be 0f00 cmp.w lr, #0 - 8011a84: d000 beq.n 8011a88 <_strtol_l.constprop.0+0xe8> - 8011a86: 1e69 subs r1, r5, #1 - 8011a88: 6011 str r1, [r2, #0] - 8011a8a: e7f3 b.n 8011a74 <_strtol_l.constprop.0+0xd4> - 8011a8c: 2430 movs r4, #48 ; 0x30 - 8011a8e: 2b00 cmp r3, #0 - 8011a90: d1b1 bne.n 80119f6 <_strtol_l.constprop.0+0x56> - 8011a92: 2308 movs r3, #8 - 8011a94: e7af b.n 80119f6 <_strtol_l.constprop.0+0x56> - 8011a96: 2c30 cmp r4, #48 ; 0x30 - 8011a98: d0a5 beq.n 80119e6 <_strtol_l.constprop.0+0x46> - 8011a9a: 230a movs r3, #10 - 8011a9c: e7ab b.n 80119f6 <_strtol_l.constprop.0+0x56> - 8011a9e: bf00 nop - 8011aa0: 08018769 .word 0x08018769 - -08011aa4 <_strtol_r>: - 8011aa4: f7ff bf7c b.w 80119a0 <_strtol_l.constprop.0> - -08011aa8 : - 8011aa8: 4613 mov r3, r2 - 8011aaa: 460a mov r2, r1 - 8011aac: 4601 mov r1, r0 - 8011aae: 4802 ldr r0, [pc, #8] ; (8011ab8 ) - 8011ab0: 6800 ldr r0, [r0, #0] - 8011ab2: f7ff bf75 b.w 80119a0 <_strtol_l.constprop.0> - 8011ab6: bf00 nop - 8011ab8: 20000310 .word 0x20000310 - -08011abc <__cvt>: - 8011abc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 8011ac0: ec55 4b10 vmov r4, r5, d0 - 8011ac4: 2d00 cmp r5, #0 - 8011ac6: 460e mov r6, r1 - 8011ac8: 4619 mov r1, r3 - 8011aca: 462b mov r3, r5 - 8011acc: bfbb ittet lt - 8011ace: f105 4300 addlt.w r3, r5, #2147483648 ; 0x80000000 - 8011ad2: 461d movlt r5, r3 - 8011ad4: 2300 movge r3, #0 - 8011ad6: 232d movlt r3, #45 ; 0x2d - 8011ad8: 700b strb r3, [r1, #0] - 8011ada: 9b0d ldr r3, [sp, #52] ; 0x34 - 8011adc: f8dd a030 ldr.w sl, [sp, #48] ; 0x30 - 8011ae0: 4691 mov r9, r2 - 8011ae2: f023 0820 bic.w r8, r3, #32 - 8011ae6: bfbc itt lt - 8011ae8: 4622 movlt r2, r4 - 8011aea: 4614 movlt r4, r2 - 8011aec: f1b8 0f46 cmp.w r8, #70 ; 0x46 - 8011af0: d005 beq.n 8011afe <__cvt+0x42> - 8011af2: f1b8 0f45 cmp.w r8, #69 ; 0x45 - 8011af6: d100 bne.n 8011afa <__cvt+0x3e> - 8011af8: 3601 adds r6, #1 - 8011afa: 2102 movs r1, #2 - 8011afc: e000 b.n 8011b00 <__cvt+0x44> - 8011afe: 2103 movs r1, #3 - 8011b00: ab03 add r3, sp, #12 - 8011b02: 9301 str r3, [sp, #4] - 8011b04: ab02 add r3, sp, #8 - 8011b06: 9300 str r3, [sp, #0] - 8011b08: ec45 4b10 vmov d0, r4, r5 - 8011b0c: 4653 mov r3, sl - 8011b0e: 4632 mov r2, r6 - 8011b10: f001 f982 bl 8012e18 <_dtoa_r> - 8011b14: f1b8 0f47 cmp.w r8, #71 ; 0x47 - 8011b18: 4607 mov r7, r0 - 8011b1a: d102 bne.n 8011b22 <__cvt+0x66> - 8011b1c: f019 0f01 tst.w r9, #1 - 8011b20: d022 beq.n 8011b68 <__cvt+0xac> - 8011b22: f1b8 0f46 cmp.w r8, #70 ; 0x46 - 8011b26: eb07 0906 add.w r9, r7, r6 - 8011b2a: d110 bne.n 8011b4e <__cvt+0x92> - 8011b2c: 783b ldrb r3, [r7, #0] - 8011b2e: 2b30 cmp r3, #48 ; 0x30 - 8011b30: d10a bne.n 8011b48 <__cvt+0x8c> - 8011b32: 2200 movs r2, #0 - 8011b34: 2300 movs r3, #0 - 8011b36: 4620 mov r0, r4 - 8011b38: 4629 mov r1, r5 - 8011b3a: f7ee ffc5 bl 8000ac8 <__aeabi_dcmpeq> - 8011b3e: b918 cbnz r0, 8011b48 <__cvt+0x8c> - 8011b40: f1c6 0601 rsb r6, r6, #1 - 8011b44: f8ca 6000 str.w r6, [sl] - 8011b48: f8da 3000 ldr.w r3, [sl] - 8011b4c: 4499 add r9, r3 - 8011b4e: 2200 movs r2, #0 - 8011b50: 2300 movs r3, #0 - 8011b52: 4620 mov r0, r4 - 8011b54: 4629 mov r1, r5 - 8011b56: f7ee ffb7 bl 8000ac8 <__aeabi_dcmpeq> - 8011b5a: b108 cbz r0, 8011b60 <__cvt+0xa4> - 8011b5c: f8cd 900c str.w r9, [sp, #12] - 8011b60: 2230 movs r2, #48 ; 0x30 - 8011b62: 9b03 ldr r3, [sp, #12] - 8011b64: 454b cmp r3, r9 - 8011b66: d307 bcc.n 8011b78 <__cvt+0xbc> - 8011b68: 9b03 ldr r3, [sp, #12] - 8011b6a: 9a0e ldr r2, [sp, #56] ; 0x38 - 8011b6c: 1bdb subs r3, r3, r7 - 8011b6e: 4638 mov r0, r7 - 8011b70: 6013 str r3, [r2, #0] - 8011b72: b004 add sp, #16 - 8011b74: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8011b78: 1c59 adds r1, r3, #1 - 8011b7a: 9103 str r1, [sp, #12] - 8011b7c: 701a strb r2, [r3, #0] - 8011b7e: e7f0 b.n 8011b62 <__cvt+0xa6> - -08011b80 <__exponent>: - 8011b80: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} - 8011b82: 4603 mov r3, r0 - 8011b84: 2900 cmp r1, #0 - 8011b86: bfb8 it lt - 8011b88: 4249 neglt r1, r1 - 8011b8a: f803 2b02 strb.w r2, [r3], #2 - 8011b8e: bfb4 ite lt - 8011b90: 222d movlt r2, #45 ; 0x2d - 8011b92: 222b movge r2, #43 ; 0x2b - 8011b94: 2909 cmp r1, #9 - 8011b96: 7042 strb r2, [r0, #1] - 8011b98: dd2a ble.n 8011bf0 <__exponent+0x70> - 8011b9a: f10d 0207 add.w r2, sp, #7 - 8011b9e: 4617 mov r7, r2 - 8011ba0: 260a movs r6, #10 - 8011ba2: 4694 mov ip, r2 - 8011ba4: fb91 f5f6 sdiv r5, r1, r6 - 8011ba8: fb06 1415 mls r4, r6, r5, r1 - 8011bac: 3430 adds r4, #48 ; 0x30 - 8011bae: f80c 4c01 strb.w r4, [ip, #-1] - 8011bb2: 460c mov r4, r1 - 8011bb4: 2c63 cmp r4, #99 ; 0x63 - 8011bb6: f102 32ff add.w r2, r2, #4294967295 - 8011bba: 4629 mov r1, r5 - 8011bbc: dcf1 bgt.n 8011ba2 <__exponent+0x22> - 8011bbe: 3130 adds r1, #48 ; 0x30 - 8011bc0: f1ac 0402 sub.w r4, ip, #2 - 8011bc4: f802 1c01 strb.w r1, [r2, #-1] - 8011bc8: 1c41 adds r1, r0, #1 - 8011bca: 4622 mov r2, r4 - 8011bcc: 42ba cmp r2, r7 - 8011bce: d30a bcc.n 8011be6 <__exponent+0x66> - 8011bd0: f10d 0209 add.w r2, sp, #9 - 8011bd4: eba2 020c sub.w r2, r2, ip - 8011bd8: 42bc cmp r4, r7 - 8011bda: bf88 it hi - 8011bdc: 2200 movhi r2, #0 - 8011bde: 4413 add r3, r2 - 8011be0: 1a18 subs r0, r3, r0 - 8011be2: b003 add sp, #12 - 8011be4: bdf0 pop {r4, r5, r6, r7, pc} - 8011be6: f812 5b01 ldrb.w r5, [r2], #1 - 8011bea: f801 5f01 strb.w r5, [r1, #1]! - 8011bee: e7ed b.n 8011bcc <__exponent+0x4c> - 8011bf0: 2330 movs r3, #48 ; 0x30 - 8011bf2: 3130 adds r1, #48 ; 0x30 - 8011bf4: 7083 strb r3, [r0, #2] - 8011bf6: 70c1 strb r1, [r0, #3] - 8011bf8: 1d03 adds r3, r0, #4 - 8011bfa: e7f1 b.n 8011be0 <__exponent+0x60> - -08011bfc <_printf_float>: - 8011bfc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8011c00: ed2d 8b02 vpush {d8} - 8011c04: b08d sub sp, #52 ; 0x34 - 8011c06: 460c mov r4, r1 - 8011c08: f8dd 8060 ldr.w r8, [sp, #96] ; 0x60 - 8011c0c: 4616 mov r6, r2 - 8011c0e: 461f mov r7, r3 - 8011c10: 4605 mov r5, r0 - 8011c12: f000 ffaf bl 8012b74 <_localeconv_r> - 8011c16: f8d0 a000 ldr.w sl, [r0] - 8011c1a: 4650 mov r0, sl - 8011c1c: f7ee fb28 bl 8000270 - 8011c20: 2300 movs r3, #0 - 8011c22: 930a str r3, [sp, #40] ; 0x28 - 8011c24: 6823 ldr r3, [r4, #0] - 8011c26: 9305 str r3, [sp, #20] - 8011c28: f8d8 3000 ldr.w r3, [r8] - 8011c2c: f894 b018 ldrb.w fp, [r4, #24] - 8011c30: 3307 adds r3, #7 - 8011c32: f023 0307 bic.w r3, r3, #7 - 8011c36: f103 0208 add.w r2, r3, #8 - 8011c3a: f8c8 2000 str.w r2, [r8] - 8011c3e: e9d3 8900 ldrd r8, r9, [r3] - 8011c42: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 - 8011c46: 9307 str r3, [sp, #28] - 8011c48: f8cd 8018 str.w r8, [sp, #24] - 8011c4c: ee08 0a10 vmov s16, r0 - 8011c50: e9c4 8912 strd r8, r9, [r4, #72] ; 0x48 - 8011c54: e9dd 0106 ldrd r0, r1, [sp, #24] - 8011c58: 4b9e ldr r3, [pc, #632] ; (8011ed4 <_printf_float+0x2d8>) - 8011c5a: f04f 32ff mov.w r2, #4294967295 - 8011c5e: f7ee ff65 bl 8000b2c <__aeabi_dcmpun> - 8011c62: bb88 cbnz r0, 8011cc8 <_printf_float+0xcc> - 8011c64: e9dd 0106 ldrd r0, r1, [sp, #24] - 8011c68: 4b9a ldr r3, [pc, #616] ; (8011ed4 <_printf_float+0x2d8>) - 8011c6a: f04f 32ff mov.w r2, #4294967295 - 8011c6e: f7ee ff3f bl 8000af0 <__aeabi_dcmple> - 8011c72: bb48 cbnz r0, 8011cc8 <_printf_float+0xcc> - 8011c74: 2200 movs r2, #0 - 8011c76: 2300 movs r3, #0 - 8011c78: 4640 mov r0, r8 - 8011c7a: 4649 mov r1, r9 - 8011c7c: f7ee ff2e bl 8000adc <__aeabi_dcmplt> - 8011c80: b110 cbz r0, 8011c88 <_printf_float+0x8c> - 8011c82: 232d movs r3, #45 ; 0x2d - 8011c84: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 8011c88: 4a93 ldr r2, [pc, #588] ; (8011ed8 <_printf_float+0x2dc>) - 8011c8a: 4b94 ldr r3, [pc, #592] ; (8011edc <_printf_float+0x2e0>) - 8011c8c: f1bb 0f47 cmp.w fp, #71 ; 0x47 - 8011c90: bf94 ite ls - 8011c92: 4690 movls r8, r2 - 8011c94: 4698 movhi r8, r3 - 8011c96: 2303 movs r3, #3 - 8011c98: 6123 str r3, [r4, #16] - 8011c9a: 9b05 ldr r3, [sp, #20] - 8011c9c: f023 0304 bic.w r3, r3, #4 - 8011ca0: 6023 str r3, [r4, #0] - 8011ca2: f04f 0900 mov.w r9, #0 - 8011ca6: 9700 str r7, [sp, #0] - 8011ca8: 4633 mov r3, r6 - 8011caa: aa0b add r2, sp, #44 ; 0x2c - 8011cac: 4621 mov r1, r4 - 8011cae: 4628 mov r0, r5 - 8011cb0: f000 f9da bl 8012068 <_printf_common> - 8011cb4: 3001 adds r0, #1 - 8011cb6: f040 8090 bne.w 8011dda <_printf_float+0x1de> - 8011cba: f04f 30ff mov.w r0, #4294967295 - 8011cbe: b00d add sp, #52 ; 0x34 - 8011cc0: ecbd 8b02 vpop {d8} - 8011cc4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8011cc8: 4642 mov r2, r8 - 8011cca: 464b mov r3, r9 - 8011ccc: 4640 mov r0, r8 - 8011cce: 4649 mov r1, r9 - 8011cd0: f7ee ff2c bl 8000b2c <__aeabi_dcmpun> - 8011cd4: b140 cbz r0, 8011ce8 <_printf_float+0xec> - 8011cd6: 464b mov r3, r9 - 8011cd8: 2b00 cmp r3, #0 - 8011cda: bfbc itt lt - 8011cdc: 232d movlt r3, #45 ; 0x2d - 8011cde: f884 3043 strblt.w r3, [r4, #67] ; 0x43 - 8011ce2: 4a7f ldr r2, [pc, #508] ; (8011ee0 <_printf_float+0x2e4>) - 8011ce4: 4b7f ldr r3, [pc, #508] ; (8011ee4 <_printf_float+0x2e8>) - 8011ce6: e7d1 b.n 8011c8c <_printf_float+0x90> - 8011ce8: 6863 ldr r3, [r4, #4] - 8011cea: f00b 02df and.w r2, fp, #223 ; 0xdf - 8011cee: 9206 str r2, [sp, #24] - 8011cf0: 1c5a adds r2, r3, #1 - 8011cf2: d13f bne.n 8011d74 <_printf_float+0x178> - 8011cf4: 2306 movs r3, #6 - 8011cf6: 6063 str r3, [r4, #4] - 8011cf8: 9b05 ldr r3, [sp, #20] - 8011cfa: 6861 ldr r1, [r4, #4] - 8011cfc: f443 6280 orr.w r2, r3, #1024 ; 0x400 - 8011d00: 2300 movs r3, #0 - 8011d02: 9303 str r3, [sp, #12] - 8011d04: ab0a add r3, sp, #40 ; 0x28 - 8011d06: e9cd b301 strd fp, r3, [sp, #4] - 8011d0a: ab09 add r3, sp, #36 ; 0x24 - 8011d0c: ec49 8b10 vmov d0, r8, r9 - 8011d10: 9300 str r3, [sp, #0] - 8011d12: 6022 str r2, [r4, #0] - 8011d14: f10d 0323 add.w r3, sp, #35 ; 0x23 - 8011d18: 4628 mov r0, r5 - 8011d1a: f7ff fecf bl 8011abc <__cvt> - 8011d1e: 9b06 ldr r3, [sp, #24] - 8011d20: 9909 ldr r1, [sp, #36] ; 0x24 - 8011d22: 2b47 cmp r3, #71 ; 0x47 - 8011d24: 4680 mov r8, r0 - 8011d26: d108 bne.n 8011d3a <_printf_float+0x13e> - 8011d28: 1cc8 adds r0, r1, #3 - 8011d2a: db02 blt.n 8011d32 <_printf_float+0x136> - 8011d2c: 6863 ldr r3, [r4, #4] - 8011d2e: 4299 cmp r1, r3 - 8011d30: dd41 ble.n 8011db6 <_printf_float+0x1ba> - 8011d32: f1ab 0302 sub.w r3, fp, #2 - 8011d36: fa5f fb83 uxtb.w fp, r3 - 8011d3a: f1bb 0f65 cmp.w fp, #101 ; 0x65 - 8011d3e: d820 bhi.n 8011d82 <_printf_float+0x186> - 8011d40: 3901 subs r1, #1 - 8011d42: 465a mov r2, fp - 8011d44: f104 0050 add.w r0, r4, #80 ; 0x50 - 8011d48: 9109 str r1, [sp, #36] ; 0x24 - 8011d4a: f7ff ff19 bl 8011b80 <__exponent> - 8011d4e: 9a0a ldr r2, [sp, #40] ; 0x28 - 8011d50: 1813 adds r3, r2, r0 - 8011d52: 2a01 cmp r2, #1 - 8011d54: 4681 mov r9, r0 - 8011d56: 6123 str r3, [r4, #16] - 8011d58: dc02 bgt.n 8011d60 <_printf_float+0x164> - 8011d5a: 6822 ldr r2, [r4, #0] - 8011d5c: 07d2 lsls r2, r2, #31 - 8011d5e: d501 bpl.n 8011d64 <_printf_float+0x168> - 8011d60: 3301 adds r3, #1 - 8011d62: 6123 str r3, [r4, #16] - 8011d64: f89d 3023 ldrb.w r3, [sp, #35] ; 0x23 - 8011d68: 2b00 cmp r3, #0 - 8011d6a: d09c beq.n 8011ca6 <_printf_float+0xaa> - 8011d6c: 232d movs r3, #45 ; 0x2d - 8011d6e: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 8011d72: e798 b.n 8011ca6 <_printf_float+0xaa> - 8011d74: 9a06 ldr r2, [sp, #24] - 8011d76: 2a47 cmp r2, #71 ; 0x47 - 8011d78: d1be bne.n 8011cf8 <_printf_float+0xfc> - 8011d7a: 2b00 cmp r3, #0 - 8011d7c: d1bc bne.n 8011cf8 <_printf_float+0xfc> - 8011d7e: 2301 movs r3, #1 - 8011d80: e7b9 b.n 8011cf6 <_printf_float+0xfa> - 8011d82: f1bb 0f66 cmp.w fp, #102 ; 0x66 - 8011d86: d118 bne.n 8011dba <_printf_float+0x1be> - 8011d88: 2900 cmp r1, #0 - 8011d8a: 6863 ldr r3, [r4, #4] - 8011d8c: dd0b ble.n 8011da6 <_printf_float+0x1aa> - 8011d8e: 6121 str r1, [r4, #16] - 8011d90: b913 cbnz r3, 8011d98 <_printf_float+0x19c> - 8011d92: 6822 ldr r2, [r4, #0] - 8011d94: 07d0 lsls r0, r2, #31 - 8011d96: d502 bpl.n 8011d9e <_printf_float+0x1a2> - 8011d98: 3301 adds r3, #1 - 8011d9a: 440b add r3, r1 - 8011d9c: 6123 str r3, [r4, #16] - 8011d9e: 65a1 str r1, [r4, #88] ; 0x58 - 8011da0: f04f 0900 mov.w r9, #0 - 8011da4: e7de b.n 8011d64 <_printf_float+0x168> - 8011da6: b913 cbnz r3, 8011dae <_printf_float+0x1b2> - 8011da8: 6822 ldr r2, [r4, #0] - 8011daa: 07d2 lsls r2, r2, #31 - 8011dac: d501 bpl.n 8011db2 <_printf_float+0x1b6> - 8011dae: 3302 adds r3, #2 - 8011db0: e7f4 b.n 8011d9c <_printf_float+0x1a0> - 8011db2: 2301 movs r3, #1 - 8011db4: e7f2 b.n 8011d9c <_printf_float+0x1a0> - 8011db6: f04f 0b67 mov.w fp, #103 ; 0x67 - 8011dba: 9b0a ldr r3, [sp, #40] ; 0x28 - 8011dbc: 4299 cmp r1, r3 - 8011dbe: db05 blt.n 8011dcc <_printf_float+0x1d0> - 8011dc0: 6823 ldr r3, [r4, #0] - 8011dc2: 6121 str r1, [r4, #16] - 8011dc4: 07d8 lsls r0, r3, #31 - 8011dc6: d5ea bpl.n 8011d9e <_printf_float+0x1a2> - 8011dc8: 1c4b adds r3, r1, #1 - 8011dca: e7e7 b.n 8011d9c <_printf_float+0x1a0> - 8011dcc: 2900 cmp r1, #0 - 8011dce: bfd4 ite le - 8011dd0: f1c1 0202 rsble r2, r1, #2 - 8011dd4: 2201 movgt r2, #1 - 8011dd6: 4413 add r3, r2 - 8011dd8: e7e0 b.n 8011d9c <_printf_float+0x1a0> - 8011dda: 6823 ldr r3, [r4, #0] - 8011ddc: 055a lsls r2, r3, #21 - 8011dde: d407 bmi.n 8011df0 <_printf_float+0x1f4> - 8011de0: 6923 ldr r3, [r4, #16] - 8011de2: 4642 mov r2, r8 - 8011de4: 4631 mov r1, r6 - 8011de6: 4628 mov r0, r5 - 8011de8: 47b8 blx r7 - 8011dea: 3001 adds r0, #1 - 8011dec: d12c bne.n 8011e48 <_printf_float+0x24c> - 8011dee: e764 b.n 8011cba <_printf_float+0xbe> - 8011df0: f1bb 0f65 cmp.w fp, #101 ; 0x65 - 8011df4: f240 80e0 bls.w 8011fb8 <_printf_float+0x3bc> - 8011df8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 - 8011dfc: 2200 movs r2, #0 - 8011dfe: 2300 movs r3, #0 - 8011e00: f7ee fe62 bl 8000ac8 <__aeabi_dcmpeq> - 8011e04: 2800 cmp r0, #0 - 8011e06: d034 beq.n 8011e72 <_printf_float+0x276> - 8011e08: 4a37 ldr r2, [pc, #220] ; (8011ee8 <_printf_float+0x2ec>) - 8011e0a: 2301 movs r3, #1 - 8011e0c: 4631 mov r1, r6 - 8011e0e: 4628 mov r0, r5 - 8011e10: 47b8 blx r7 - 8011e12: 3001 adds r0, #1 - 8011e14: f43f af51 beq.w 8011cba <_printf_float+0xbe> - 8011e18: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 - 8011e1c: 429a cmp r2, r3 - 8011e1e: db02 blt.n 8011e26 <_printf_float+0x22a> - 8011e20: 6823 ldr r3, [r4, #0] - 8011e22: 07d8 lsls r0, r3, #31 - 8011e24: d510 bpl.n 8011e48 <_printf_float+0x24c> - 8011e26: ee18 3a10 vmov r3, s16 - 8011e2a: 4652 mov r2, sl - 8011e2c: 4631 mov r1, r6 - 8011e2e: 4628 mov r0, r5 - 8011e30: 47b8 blx r7 - 8011e32: 3001 adds r0, #1 - 8011e34: f43f af41 beq.w 8011cba <_printf_float+0xbe> - 8011e38: f04f 0800 mov.w r8, #0 - 8011e3c: f104 091a add.w r9, r4, #26 - 8011e40: 9b0a ldr r3, [sp, #40] ; 0x28 - 8011e42: 3b01 subs r3, #1 - 8011e44: 4543 cmp r3, r8 - 8011e46: dc09 bgt.n 8011e5c <_printf_float+0x260> - 8011e48: 6823 ldr r3, [r4, #0] - 8011e4a: 079b lsls r3, r3, #30 - 8011e4c: f100 8107 bmi.w 801205e <_printf_float+0x462> - 8011e50: 68e0 ldr r0, [r4, #12] - 8011e52: 9b0b ldr r3, [sp, #44] ; 0x2c - 8011e54: 4298 cmp r0, r3 - 8011e56: bfb8 it lt - 8011e58: 4618 movlt r0, r3 - 8011e5a: e730 b.n 8011cbe <_printf_float+0xc2> - 8011e5c: 2301 movs r3, #1 - 8011e5e: 464a mov r2, r9 - 8011e60: 4631 mov r1, r6 - 8011e62: 4628 mov r0, r5 - 8011e64: 47b8 blx r7 - 8011e66: 3001 adds r0, #1 - 8011e68: f43f af27 beq.w 8011cba <_printf_float+0xbe> - 8011e6c: f108 0801 add.w r8, r8, #1 - 8011e70: e7e6 b.n 8011e40 <_printf_float+0x244> - 8011e72: 9b09 ldr r3, [sp, #36] ; 0x24 - 8011e74: 2b00 cmp r3, #0 - 8011e76: dc39 bgt.n 8011eec <_printf_float+0x2f0> - 8011e78: 4a1b ldr r2, [pc, #108] ; (8011ee8 <_printf_float+0x2ec>) - 8011e7a: 2301 movs r3, #1 - 8011e7c: 4631 mov r1, r6 - 8011e7e: 4628 mov r0, r5 - 8011e80: 47b8 blx r7 - 8011e82: 3001 adds r0, #1 - 8011e84: f43f af19 beq.w 8011cba <_printf_float+0xbe> - 8011e88: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 - 8011e8c: 4313 orrs r3, r2 - 8011e8e: d102 bne.n 8011e96 <_printf_float+0x29a> - 8011e90: 6823 ldr r3, [r4, #0] - 8011e92: 07d9 lsls r1, r3, #31 - 8011e94: d5d8 bpl.n 8011e48 <_printf_float+0x24c> - 8011e96: ee18 3a10 vmov r3, s16 - 8011e9a: 4652 mov r2, sl - 8011e9c: 4631 mov r1, r6 - 8011e9e: 4628 mov r0, r5 - 8011ea0: 47b8 blx r7 - 8011ea2: 3001 adds r0, #1 - 8011ea4: f43f af09 beq.w 8011cba <_printf_float+0xbe> - 8011ea8: f04f 0900 mov.w r9, #0 - 8011eac: f104 0a1a add.w sl, r4, #26 - 8011eb0: 9b09 ldr r3, [sp, #36] ; 0x24 - 8011eb2: 425b negs r3, r3 - 8011eb4: 454b cmp r3, r9 - 8011eb6: dc01 bgt.n 8011ebc <_printf_float+0x2c0> - 8011eb8: 9b0a ldr r3, [sp, #40] ; 0x28 - 8011eba: e792 b.n 8011de2 <_printf_float+0x1e6> - 8011ebc: 2301 movs r3, #1 - 8011ebe: 4652 mov r2, sl - 8011ec0: 4631 mov r1, r6 - 8011ec2: 4628 mov r0, r5 - 8011ec4: 47b8 blx r7 - 8011ec6: 3001 adds r0, #1 - 8011ec8: f43f aef7 beq.w 8011cba <_printf_float+0xbe> - 8011ecc: f109 0901 add.w r9, r9, #1 - 8011ed0: e7ee b.n 8011eb0 <_printf_float+0x2b4> - 8011ed2: bf00 nop - 8011ed4: 7fefffff .word 0x7fefffff - 8011ed8: 08018869 .word 0x08018869 - 8011edc: 0801886d .word 0x0801886d - 8011ee0: 08018871 .word 0x08018871 - 8011ee4: 08018875 .word 0x08018875 - 8011ee8: 08018879 .word 0x08018879 - 8011eec: 9a0a ldr r2, [sp, #40] ; 0x28 - 8011eee: 6da3 ldr r3, [r4, #88] ; 0x58 - 8011ef0: 429a cmp r2, r3 - 8011ef2: bfa8 it ge - 8011ef4: 461a movge r2, r3 - 8011ef6: 2a00 cmp r2, #0 - 8011ef8: 4691 mov r9, r2 - 8011efa: dc37 bgt.n 8011f6c <_printf_float+0x370> - 8011efc: f04f 0b00 mov.w fp, #0 - 8011f00: ea29 79e9 bic.w r9, r9, r9, asr #31 - 8011f04: f104 021a add.w r2, r4, #26 - 8011f08: 6da3 ldr r3, [r4, #88] ; 0x58 - 8011f0a: 9305 str r3, [sp, #20] - 8011f0c: eba3 0309 sub.w r3, r3, r9 - 8011f10: 455b cmp r3, fp - 8011f12: dc33 bgt.n 8011f7c <_printf_float+0x380> - 8011f14: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 - 8011f18: 429a cmp r2, r3 - 8011f1a: db3b blt.n 8011f94 <_printf_float+0x398> - 8011f1c: 6823 ldr r3, [r4, #0] - 8011f1e: 07da lsls r2, r3, #31 - 8011f20: d438 bmi.n 8011f94 <_printf_float+0x398> - 8011f22: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 - 8011f26: eba2 0903 sub.w r9, r2, r3 - 8011f2a: 9b05 ldr r3, [sp, #20] - 8011f2c: 1ad2 subs r2, r2, r3 - 8011f2e: 4591 cmp r9, r2 - 8011f30: bfa8 it ge - 8011f32: 4691 movge r9, r2 - 8011f34: f1b9 0f00 cmp.w r9, #0 - 8011f38: dc35 bgt.n 8011fa6 <_printf_float+0x3aa> - 8011f3a: f04f 0800 mov.w r8, #0 - 8011f3e: ea29 79e9 bic.w r9, r9, r9, asr #31 - 8011f42: f104 0a1a add.w sl, r4, #26 - 8011f46: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 - 8011f4a: 1a9b subs r3, r3, r2 - 8011f4c: eba3 0309 sub.w r3, r3, r9 - 8011f50: 4543 cmp r3, r8 - 8011f52: f77f af79 ble.w 8011e48 <_printf_float+0x24c> - 8011f56: 2301 movs r3, #1 - 8011f58: 4652 mov r2, sl - 8011f5a: 4631 mov r1, r6 - 8011f5c: 4628 mov r0, r5 - 8011f5e: 47b8 blx r7 - 8011f60: 3001 adds r0, #1 - 8011f62: f43f aeaa beq.w 8011cba <_printf_float+0xbe> - 8011f66: f108 0801 add.w r8, r8, #1 - 8011f6a: e7ec b.n 8011f46 <_printf_float+0x34a> - 8011f6c: 4613 mov r3, r2 - 8011f6e: 4631 mov r1, r6 - 8011f70: 4642 mov r2, r8 - 8011f72: 4628 mov r0, r5 - 8011f74: 47b8 blx r7 - 8011f76: 3001 adds r0, #1 - 8011f78: d1c0 bne.n 8011efc <_printf_float+0x300> - 8011f7a: e69e b.n 8011cba <_printf_float+0xbe> - 8011f7c: 2301 movs r3, #1 - 8011f7e: 4631 mov r1, r6 - 8011f80: 4628 mov r0, r5 - 8011f82: 9205 str r2, [sp, #20] - 8011f84: 47b8 blx r7 - 8011f86: 3001 adds r0, #1 - 8011f88: f43f ae97 beq.w 8011cba <_printf_float+0xbe> - 8011f8c: 9a05 ldr r2, [sp, #20] - 8011f8e: f10b 0b01 add.w fp, fp, #1 - 8011f92: e7b9 b.n 8011f08 <_printf_float+0x30c> - 8011f94: ee18 3a10 vmov r3, s16 - 8011f98: 4652 mov r2, sl - 8011f9a: 4631 mov r1, r6 - 8011f9c: 4628 mov r0, r5 - 8011f9e: 47b8 blx r7 - 8011fa0: 3001 adds r0, #1 - 8011fa2: d1be bne.n 8011f22 <_printf_float+0x326> - 8011fa4: e689 b.n 8011cba <_printf_float+0xbe> - 8011fa6: 9a05 ldr r2, [sp, #20] - 8011fa8: 464b mov r3, r9 - 8011faa: 4442 add r2, r8 - 8011fac: 4631 mov r1, r6 - 8011fae: 4628 mov r0, r5 - 8011fb0: 47b8 blx r7 - 8011fb2: 3001 adds r0, #1 - 8011fb4: d1c1 bne.n 8011f3a <_printf_float+0x33e> - 8011fb6: e680 b.n 8011cba <_printf_float+0xbe> - 8011fb8: 9a0a ldr r2, [sp, #40] ; 0x28 - 8011fba: 2a01 cmp r2, #1 - 8011fbc: dc01 bgt.n 8011fc2 <_printf_float+0x3c6> - 8011fbe: 07db lsls r3, r3, #31 - 8011fc0: d53a bpl.n 8012038 <_printf_float+0x43c> - 8011fc2: 2301 movs r3, #1 - 8011fc4: 4642 mov r2, r8 - 8011fc6: 4631 mov r1, r6 - 8011fc8: 4628 mov r0, r5 - 8011fca: 47b8 blx r7 - 8011fcc: 3001 adds r0, #1 - 8011fce: f43f ae74 beq.w 8011cba <_printf_float+0xbe> - 8011fd2: ee18 3a10 vmov r3, s16 - 8011fd6: 4652 mov r2, sl - 8011fd8: 4631 mov r1, r6 - 8011fda: 4628 mov r0, r5 - 8011fdc: 47b8 blx r7 - 8011fde: 3001 adds r0, #1 - 8011fe0: f43f ae6b beq.w 8011cba <_printf_float+0xbe> - 8011fe4: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 - 8011fe8: 2200 movs r2, #0 - 8011fea: 2300 movs r3, #0 - 8011fec: f8dd a028 ldr.w sl, [sp, #40] ; 0x28 - 8011ff0: f7ee fd6a bl 8000ac8 <__aeabi_dcmpeq> - 8011ff4: b9d8 cbnz r0, 801202e <_printf_float+0x432> - 8011ff6: f10a 33ff add.w r3, sl, #4294967295 - 8011ffa: f108 0201 add.w r2, r8, #1 - 8011ffe: 4631 mov r1, r6 - 8012000: 4628 mov r0, r5 - 8012002: 47b8 blx r7 - 8012004: 3001 adds r0, #1 - 8012006: d10e bne.n 8012026 <_printf_float+0x42a> - 8012008: e657 b.n 8011cba <_printf_float+0xbe> - 801200a: 2301 movs r3, #1 - 801200c: 4652 mov r2, sl - 801200e: 4631 mov r1, r6 - 8012010: 4628 mov r0, r5 - 8012012: 47b8 blx r7 - 8012014: 3001 adds r0, #1 - 8012016: f43f ae50 beq.w 8011cba <_printf_float+0xbe> - 801201a: f108 0801 add.w r8, r8, #1 - 801201e: 9b0a ldr r3, [sp, #40] ; 0x28 - 8012020: 3b01 subs r3, #1 - 8012022: 4543 cmp r3, r8 - 8012024: dcf1 bgt.n 801200a <_printf_float+0x40e> - 8012026: 464b mov r3, r9 - 8012028: f104 0250 add.w r2, r4, #80 ; 0x50 - 801202c: e6da b.n 8011de4 <_printf_float+0x1e8> - 801202e: f04f 0800 mov.w r8, #0 - 8012032: f104 0a1a add.w sl, r4, #26 - 8012036: e7f2 b.n 801201e <_printf_float+0x422> - 8012038: 2301 movs r3, #1 - 801203a: 4642 mov r2, r8 - 801203c: e7df b.n 8011ffe <_printf_float+0x402> - 801203e: 2301 movs r3, #1 - 8012040: 464a mov r2, r9 - 8012042: 4631 mov r1, r6 - 8012044: 4628 mov r0, r5 - 8012046: 47b8 blx r7 - 8012048: 3001 adds r0, #1 - 801204a: f43f ae36 beq.w 8011cba <_printf_float+0xbe> - 801204e: f108 0801 add.w r8, r8, #1 - 8012052: 68e3 ldr r3, [r4, #12] - 8012054: 990b ldr r1, [sp, #44] ; 0x2c - 8012056: 1a5b subs r3, r3, r1 - 8012058: 4543 cmp r3, r8 - 801205a: dcf0 bgt.n 801203e <_printf_float+0x442> - 801205c: e6f8 b.n 8011e50 <_printf_float+0x254> - 801205e: f04f 0800 mov.w r8, #0 - 8012062: f104 0919 add.w r9, r4, #25 - 8012066: e7f4 b.n 8012052 <_printf_float+0x456> - -08012068 <_printf_common>: - 8012068: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 801206c: 4616 mov r6, r2 - 801206e: 4699 mov r9, r3 - 8012070: 688a ldr r2, [r1, #8] - 8012072: 690b ldr r3, [r1, #16] - 8012074: f8dd 8020 ldr.w r8, [sp, #32] - 8012078: 4293 cmp r3, r2 - 801207a: bfb8 it lt - 801207c: 4613 movlt r3, r2 - 801207e: 6033 str r3, [r6, #0] - 8012080: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 - 8012084: 4607 mov r7, r0 - 8012086: 460c mov r4, r1 - 8012088: b10a cbz r2, 801208e <_printf_common+0x26> - 801208a: 3301 adds r3, #1 - 801208c: 6033 str r3, [r6, #0] - 801208e: 6823 ldr r3, [r4, #0] - 8012090: 0699 lsls r1, r3, #26 - 8012092: bf42 ittt mi - 8012094: 6833 ldrmi r3, [r6, #0] - 8012096: 3302 addmi r3, #2 - 8012098: 6033 strmi r3, [r6, #0] - 801209a: 6825 ldr r5, [r4, #0] - 801209c: f015 0506 ands.w r5, r5, #6 - 80120a0: d106 bne.n 80120b0 <_printf_common+0x48> - 80120a2: f104 0a19 add.w sl, r4, #25 - 80120a6: 68e3 ldr r3, [r4, #12] - 80120a8: 6832 ldr r2, [r6, #0] - 80120aa: 1a9b subs r3, r3, r2 - 80120ac: 42ab cmp r3, r5 - 80120ae: dc26 bgt.n 80120fe <_printf_common+0x96> - 80120b0: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 - 80120b4: 1e13 subs r3, r2, #0 - 80120b6: 6822 ldr r2, [r4, #0] - 80120b8: bf18 it ne - 80120ba: 2301 movne r3, #1 - 80120bc: 0692 lsls r2, r2, #26 - 80120be: d42b bmi.n 8012118 <_printf_common+0xb0> - 80120c0: f104 0243 add.w r2, r4, #67 ; 0x43 - 80120c4: 4649 mov r1, r9 - 80120c6: 4638 mov r0, r7 - 80120c8: 47c0 blx r8 - 80120ca: 3001 adds r0, #1 - 80120cc: d01e beq.n 801210c <_printf_common+0xa4> - 80120ce: 6823 ldr r3, [r4, #0] - 80120d0: 6922 ldr r2, [r4, #16] - 80120d2: f003 0306 and.w r3, r3, #6 - 80120d6: 2b04 cmp r3, #4 - 80120d8: bf02 ittt eq - 80120da: 68e5 ldreq r5, [r4, #12] - 80120dc: 6833 ldreq r3, [r6, #0] - 80120de: 1aed subeq r5, r5, r3 - 80120e0: 68a3 ldr r3, [r4, #8] - 80120e2: bf0c ite eq - 80120e4: ea25 75e5 biceq.w r5, r5, r5, asr #31 - 80120e8: 2500 movne r5, #0 - 80120ea: 4293 cmp r3, r2 - 80120ec: bfc4 itt gt - 80120ee: 1a9b subgt r3, r3, r2 - 80120f0: 18ed addgt r5, r5, r3 - 80120f2: 2600 movs r6, #0 - 80120f4: 341a adds r4, #26 - 80120f6: 42b5 cmp r5, r6 - 80120f8: d11a bne.n 8012130 <_printf_common+0xc8> - 80120fa: 2000 movs r0, #0 - 80120fc: e008 b.n 8012110 <_printf_common+0xa8> - 80120fe: 2301 movs r3, #1 - 8012100: 4652 mov r2, sl - 8012102: 4649 mov r1, r9 - 8012104: 4638 mov r0, r7 - 8012106: 47c0 blx r8 - 8012108: 3001 adds r0, #1 - 801210a: d103 bne.n 8012114 <_printf_common+0xac> - 801210c: f04f 30ff mov.w r0, #4294967295 - 8012110: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8012114: 3501 adds r5, #1 - 8012116: e7c6 b.n 80120a6 <_printf_common+0x3e> - 8012118: 18e1 adds r1, r4, r3 - 801211a: 1c5a adds r2, r3, #1 - 801211c: 2030 movs r0, #48 ; 0x30 - 801211e: f881 0043 strb.w r0, [r1, #67] ; 0x43 - 8012122: 4422 add r2, r4 - 8012124: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 - 8012128: f882 1043 strb.w r1, [r2, #67] ; 0x43 - 801212c: 3302 adds r3, #2 - 801212e: e7c7 b.n 80120c0 <_printf_common+0x58> - 8012130: 2301 movs r3, #1 - 8012132: 4622 mov r2, r4 - 8012134: 4649 mov r1, r9 - 8012136: 4638 mov r0, r7 - 8012138: 47c0 blx r8 - 801213a: 3001 adds r0, #1 - 801213c: d0e6 beq.n 801210c <_printf_common+0xa4> - 801213e: 3601 adds r6, #1 - 8012140: e7d9 b.n 80120f6 <_printf_common+0x8e> +08013198 <_strtod_l>: + 8013198: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801319c: ed2d 8b02 vpush {d8} + 80131a0: b09b sub sp, #108 ; 0x6c + 80131a2: 4604 mov r4, r0 + 80131a4: 9213 str r2, [sp, #76] ; 0x4c + 80131a6: 2200 movs r2, #0 + 80131a8: 9216 str r2, [sp, #88] ; 0x58 + 80131aa: 460d mov r5, r1 + 80131ac: f04f 0800 mov.w r8, #0 + 80131b0: f04f 0900 mov.w r9, #0 + 80131b4: 460a mov r2, r1 + 80131b6: 9215 str r2, [sp, #84] ; 0x54 + 80131b8: 7811 ldrb r1, [r2, #0] + 80131ba: 292b cmp r1, #43 ; 0x2b + 80131bc: d04c beq.n 8013258 <_strtod_l+0xc0> + 80131be: d83a bhi.n 8013236 <_strtod_l+0x9e> + 80131c0: 290d cmp r1, #13 + 80131c2: d834 bhi.n 801322e <_strtod_l+0x96> + 80131c4: 2908 cmp r1, #8 + 80131c6: d834 bhi.n 8013232 <_strtod_l+0x9a> + 80131c8: 2900 cmp r1, #0 + 80131ca: d03d beq.n 8013248 <_strtod_l+0xb0> + 80131cc: 2200 movs r2, #0 + 80131ce: 920a str r2, [sp, #40] ; 0x28 + 80131d0: 9e15 ldr r6, [sp, #84] ; 0x54 + 80131d2: 7832 ldrb r2, [r6, #0] + 80131d4: 2a30 cmp r2, #48 ; 0x30 + 80131d6: f040 80b4 bne.w 8013342 <_strtod_l+0x1aa> + 80131da: 7872 ldrb r2, [r6, #1] + 80131dc: f002 02df and.w r2, r2, #223 ; 0xdf + 80131e0: 2a58 cmp r2, #88 ; 0x58 + 80131e2: d170 bne.n 80132c6 <_strtod_l+0x12e> + 80131e4: 9302 str r3, [sp, #8] + 80131e6: 9b0a ldr r3, [sp, #40] ; 0x28 + 80131e8: 9301 str r3, [sp, #4] + 80131ea: ab16 add r3, sp, #88 ; 0x58 + 80131ec: 9300 str r3, [sp, #0] + 80131ee: 4a8e ldr r2, [pc, #568] ; (8013428 <_strtod_l+0x290>) + 80131f0: ab17 add r3, sp, #92 ; 0x5c + 80131f2: a915 add r1, sp, #84 ; 0x54 + 80131f4: 4620 mov r0, r4 + 80131f6: f002 ff0d bl 8016014 <__gethex> + 80131fa: f010 070f ands.w r7, r0, #15 + 80131fe: 4605 mov r5, r0 + 8013200: d005 beq.n 801320e <_strtod_l+0x76> + 8013202: 2f06 cmp r7, #6 + 8013204: d12a bne.n 801325c <_strtod_l+0xc4> + 8013206: 3601 adds r6, #1 + 8013208: 2300 movs r3, #0 + 801320a: 9615 str r6, [sp, #84] ; 0x54 + 801320c: 930a str r3, [sp, #40] ; 0x28 + 801320e: 9b13 ldr r3, [sp, #76] ; 0x4c + 8013210: 2b00 cmp r3, #0 + 8013212: f040 857f bne.w 8013d14 <_strtod_l+0xb7c> + 8013216: 9b0a ldr r3, [sp, #40] ; 0x28 + 8013218: b1db cbz r3, 8013252 <_strtod_l+0xba> + 801321a: 4642 mov r2, r8 + 801321c: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 + 8013220: ec43 2b10 vmov d0, r2, r3 + 8013224: b01b add sp, #108 ; 0x6c + 8013226: ecbd 8b02 vpop {d8} + 801322a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801322e: 2920 cmp r1, #32 + 8013230: d1cc bne.n 80131cc <_strtod_l+0x34> + 8013232: 3201 adds r2, #1 + 8013234: e7bf b.n 80131b6 <_strtod_l+0x1e> + 8013236: 292d cmp r1, #45 ; 0x2d + 8013238: d1c8 bne.n 80131cc <_strtod_l+0x34> + 801323a: 2101 movs r1, #1 + 801323c: 910a str r1, [sp, #40] ; 0x28 + 801323e: 1c51 adds r1, r2, #1 + 8013240: 9115 str r1, [sp, #84] ; 0x54 + 8013242: 7852 ldrb r2, [r2, #1] + 8013244: 2a00 cmp r2, #0 + 8013246: d1c3 bne.n 80131d0 <_strtod_l+0x38> + 8013248: 9b13 ldr r3, [sp, #76] ; 0x4c + 801324a: 9515 str r5, [sp, #84] ; 0x54 + 801324c: 2b00 cmp r3, #0 + 801324e: f040 855f bne.w 8013d10 <_strtod_l+0xb78> + 8013252: 4642 mov r2, r8 + 8013254: 464b mov r3, r9 + 8013256: e7e3 b.n 8013220 <_strtod_l+0x88> + 8013258: 2100 movs r1, #0 + 801325a: e7ef b.n 801323c <_strtod_l+0xa4> + 801325c: 9a16 ldr r2, [sp, #88] ; 0x58 + 801325e: b13a cbz r2, 8013270 <_strtod_l+0xd8> + 8013260: 2135 movs r1, #53 ; 0x35 + 8013262: a818 add r0, sp, #96 ; 0x60 + 8013264: f003 fe41 bl 8016eea <__copybits> + 8013268: 9916 ldr r1, [sp, #88] ; 0x58 + 801326a: 4620 mov r0, r4 + 801326c: f003 fa14 bl 8016698 <_Bfree> + 8013270: 3f01 subs r7, #1 + 8013272: 9a17 ldr r2, [sp, #92] ; 0x5c + 8013274: 2f04 cmp r7, #4 + 8013276: d806 bhi.n 8013286 <_strtod_l+0xee> + 8013278: e8df f007 tbb [pc, r7] + 801327c: 201d0314 .word 0x201d0314 + 8013280: 14 .byte 0x14 + 8013281: 00 .byte 0x00 + 8013282: e9dd 8918 ldrd r8, r9, [sp, #96] ; 0x60 + 8013286: 05e9 lsls r1, r5, #23 + 8013288: bf48 it mi + 801328a: f049 4900 orrmi.w r9, r9, #2147483648 ; 0x80000000 + 801328e: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 8013292: 0d1b lsrs r3, r3, #20 + 8013294: 051b lsls r3, r3, #20 + 8013296: 2b00 cmp r3, #0 + 8013298: d1b9 bne.n 801320e <_strtod_l+0x76> + 801329a: f001 ff1d bl 80150d8 <__errno> + 801329e: 2322 movs r3, #34 ; 0x22 + 80132a0: 6003 str r3, [r0, #0] + 80132a2: e7b4 b.n 801320e <_strtod_l+0x76> + 80132a4: e9dd 8318 ldrd r8, r3, [sp, #96] ; 0x60 + 80132a8: f202 4233 addw r2, r2, #1075 ; 0x433 + 80132ac: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 + 80132b0: ea43 5902 orr.w r9, r3, r2, lsl #20 + 80132b4: e7e7 b.n 8013286 <_strtod_l+0xee> + 80132b6: f8df 9178 ldr.w r9, [pc, #376] ; 8013430 <_strtod_l+0x298> + 80132ba: e7e4 b.n 8013286 <_strtod_l+0xee> + 80132bc: f06f 4900 mvn.w r9, #2147483648 ; 0x80000000 + 80132c0: f04f 38ff mov.w r8, #4294967295 + 80132c4: e7df b.n 8013286 <_strtod_l+0xee> + 80132c6: 9b15 ldr r3, [sp, #84] ; 0x54 + 80132c8: 1c5a adds r2, r3, #1 + 80132ca: 9215 str r2, [sp, #84] ; 0x54 + 80132cc: 785b ldrb r3, [r3, #1] + 80132ce: 2b30 cmp r3, #48 ; 0x30 + 80132d0: d0f9 beq.n 80132c6 <_strtod_l+0x12e> + 80132d2: 2b00 cmp r3, #0 + 80132d4: d09b beq.n 801320e <_strtod_l+0x76> + 80132d6: 2301 movs r3, #1 + 80132d8: f04f 0a00 mov.w sl, #0 + 80132dc: 9304 str r3, [sp, #16] + 80132de: 9b15 ldr r3, [sp, #84] ; 0x54 + 80132e0: 930b str r3, [sp, #44] ; 0x2c + 80132e2: f8cd a024 str.w sl, [sp, #36] ; 0x24 + 80132e6: 46d3 mov fp, sl + 80132e8: 220a movs r2, #10 + 80132ea: 9815 ldr r0, [sp, #84] ; 0x54 + 80132ec: 7806 ldrb r6, [r0, #0] + 80132ee: f1a6 0330 sub.w r3, r6, #48 ; 0x30 + 80132f2: b2d9 uxtb r1, r3 + 80132f4: 2909 cmp r1, #9 + 80132f6: d926 bls.n 8013346 <_strtod_l+0x1ae> + 80132f8: 494c ldr r1, [pc, #304] ; (801342c <_strtod_l+0x294>) + 80132fa: 2201 movs r2, #1 + 80132fc: f001 fe0d bl 8014f1a + 8013300: 2800 cmp r0, #0 + 8013302: d030 beq.n 8013366 <_strtod_l+0x1ce> + 8013304: 2000 movs r0, #0 + 8013306: 4632 mov r2, r6 + 8013308: 9005 str r0, [sp, #20] + 801330a: 465e mov r6, fp + 801330c: 4603 mov r3, r0 + 801330e: 2a65 cmp r2, #101 ; 0x65 + 8013310: d001 beq.n 8013316 <_strtod_l+0x17e> + 8013312: 2a45 cmp r2, #69 ; 0x45 + 8013314: d113 bne.n 801333e <_strtod_l+0x1a6> + 8013316: b91e cbnz r6, 8013320 <_strtod_l+0x188> + 8013318: 9a04 ldr r2, [sp, #16] + 801331a: 4302 orrs r2, r0 + 801331c: d094 beq.n 8013248 <_strtod_l+0xb0> + 801331e: 2600 movs r6, #0 + 8013320: 9d15 ldr r5, [sp, #84] ; 0x54 + 8013322: 1c6a adds r2, r5, #1 + 8013324: 9215 str r2, [sp, #84] ; 0x54 + 8013326: 786a ldrb r2, [r5, #1] + 8013328: 2a2b cmp r2, #43 ; 0x2b + 801332a: d074 beq.n 8013416 <_strtod_l+0x27e> + 801332c: 2a2d cmp r2, #45 ; 0x2d + 801332e: d078 beq.n 8013422 <_strtod_l+0x28a> + 8013330: f04f 0c00 mov.w ip, #0 + 8013334: f1a2 0130 sub.w r1, r2, #48 ; 0x30 + 8013338: 2909 cmp r1, #9 + 801333a: d97f bls.n 801343c <_strtod_l+0x2a4> + 801333c: 9515 str r5, [sp, #84] ; 0x54 + 801333e: 2700 movs r7, #0 + 8013340: e09e b.n 8013480 <_strtod_l+0x2e8> + 8013342: 2300 movs r3, #0 + 8013344: e7c8 b.n 80132d8 <_strtod_l+0x140> + 8013346: f1bb 0f08 cmp.w fp, #8 + 801334a: bfd8 it le + 801334c: 9909 ldrle r1, [sp, #36] ; 0x24 + 801334e: f100 0001 add.w r0, r0, #1 + 8013352: bfda itte le + 8013354: fb02 3301 mlale r3, r2, r1, r3 + 8013358: 9309 strle r3, [sp, #36] ; 0x24 + 801335a: fb02 3a0a mlagt sl, r2, sl, r3 + 801335e: f10b 0b01 add.w fp, fp, #1 + 8013362: 9015 str r0, [sp, #84] ; 0x54 + 8013364: e7c1 b.n 80132ea <_strtod_l+0x152> + 8013366: 9b15 ldr r3, [sp, #84] ; 0x54 + 8013368: 1c5a adds r2, r3, #1 + 801336a: 9215 str r2, [sp, #84] ; 0x54 + 801336c: 785a ldrb r2, [r3, #1] + 801336e: f1bb 0f00 cmp.w fp, #0 + 8013372: d037 beq.n 80133e4 <_strtod_l+0x24c> + 8013374: 9005 str r0, [sp, #20] + 8013376: 465e mov r6, fp + 8013378: f1a2 0330 sub.w r3, r2, #48 ; 0x30 + 801337c: 2b09 cmp r3, #9 + 801337e: d912 bls.n 80133a6 <_strtod_l+0x20e> + 8013380: 2301 movs r3, #1 + 8013382: e7c4 b.n 801330e <_strtod_l+0x176> + 8013384: 9b15 ldr r3, [sp, #84] ; 0x54 + 8013386: 1c5a adds r2, r3, #1 + 8013388: 9215 str r2, [sp, #84] ; 0x54 + 801338a: 785a ldrb r2, [r3, #1] + 801338c: 3001 adds r0, #1 + 801338e: 2a30 cmp r2, #48 ; 0x30 + 8013390: d0f8 beq.n 8013384 <_strtod_l+0x1ec> + 8013392: f1a2 0331 sub.w r3, r2, #49 ; 0x31 + 8013396: 2b08 cmp r3, #8 + 8013398: f200 84c1 bhi.w 8013d1e <_strtod_l+0xb86> + 801339c: 9b15 ldr r3, [sp, #84] ; 0x54 + 801339e: 9005 str r0, [sp, #20] + 80133a0: 2000 movs r0, #0 + 80133a2: 930b str r3, [sp, #44] ; 0x2c + 80133a4: 4606 mov r6, r0 + 80133a6: 3a30 subs r2, #48 ; 0x30 + 80133a8: f100 0301 add.w r3, r0, #1 + 80133ac: d014 beq.n 80133d8 <_strtod_l+0x240> + 80133ae: 9905 ldr r1, [sp, #20] + 80133b0: 4419 add r1, r3 + 80133b2: 9105 str r1, [sp, #20] + 80133b4: 4633 mov r3, r6 + 80133b6: eb00 0c06 add.w ip, r0, r6 + 80133ba: 210a movs r1, #10 + 80133bc: 4563 cmp r3, ip + 80133be: d113 bne.n 80133e8 <_strtod_l+0x250> + 80133c0: 1833 adds r3, r6, r0 + 80133c2: 2b08 cmp r3, #8 + 80133c4: f106 0601 add.w r6, r6, #1 + 80133c8: 4406 add r6, r0 + 80133ca: dc1a bgt.n 8013402 <_strtod_l+0x26a> + 80133cc: 9909 ldr r1, [sp, #36] ; 0x24 + 80133ce: 230a movs r3, #10 + 80133d0: fb03 2301 mla r3, r3, r1, r2 + 80133d4: 9309 str r3, [sp, #36] ; 0x24 + 80133d6: 2300 movs r3, #0 + 80133d8: 9a15 ldr r2, [sp, #84] ; 0x54 + 80133da: 1c51 adds r1, r2, #1 + 80133dc: 9115 str r1, [sp, #84] ; 0x54 + 80133de: 7852 ldrb r2, [r2, #1] + 80133e0: 4618 mov r0, r3 + 80133e2: e7c9 b.n 8013378 <_strtod_l+0x1e0> + 80133e4: 4658 mov r0, fp + 80133e6: e7d2 b.n 801338e <_strtod_l+0x1f6> + 80133e8: 2b08 cmp r3, #8 + 80133ea: f103 0301 add.w r3, r3, #1 + 80133ee: dc03 bgt.n 80133f8 <_strtod_l+0x260> + 80133f0: 9f09 ldr r7, [sp, #36] ; 0x24 + 80133f2: 434f muls r7, r1 + 80133f4: 9709 str r7, [sp, #36] ; 0x24 + 80133f6: e7e1 b.n 80133bc <_strtod_l+0x224> + 80133f8: 2b10 cmp r3, #16 + 80133fa: bfd8 it le + 80133fc: fb01 fa0a mulle.w sl, r1, sl + 8013400: e7dc b.n 80133bc <_strtod_l+0x224> + 8013402: 2e10 cmp r6, #16 + 8013404: bfdc itt le + 8013406: 230a movle r3, #10 + 8013408: fb03 2a0a mlale sl, r3, sl, r2 + 801340c: e7e3 b.n 80133d6 <_strtod_l+0x23e> + 801340e: 2300 movs r3, #0 + 8013410: 9305 str r3, [sp, #20] + 8013412: 2301 movs r3, #1 + 8013414: e780 b.n 8013318 <_strtod_l+0x180> + 8013416: f04f 0c00 mov.w ip, #0 + 801341a: 1caa adds r2, r5, #2 + 801341c: 9215 str r2, [sp, #84] ; 0x54 + 801341e: 78aa ldrb r2, [r5, #2] + 8013420: e788 b.n 8013334 <_strtod_l+0x19c> + 8013422: f04f 0c01 mov.w ip, #1 + 8013426: e7f8 b.n 801341a <_strtod_l+0x282> + 8013428: 0801abf0 .word 0x0801abf0 + 801342c: 0801abec .word 0x0801abec + 8013430: 7ff00000 .word 0x7ff00000 + 8013434: 9a15 ldr r2, [sp, #84] ; 0x54 + 8013436: 1c51 adds r1, r2, #1 + 8013438: 9115 str r1, [sp, #84] ; 0x54 + 801343a: 7852 ldrb r2, [r2, #1] + 801343c: 2a30 cmp r2, #48 ; 0x30 + 801343e: d0f9 beq.n 8013434 <_strtod_l+0x29c> + 8013440: f1a2 0131 sub.w r1, r2, #49 ; 0x31 + 8013444: 2908 cmp r1, #8 + 8013446: f63f af7a bhi.w 801333e <_strtod_l+0x1a6> + 801344a: 3a30 subs r2, #48 ; 0x30 + 801344c: 9208 str r2, [sp, #32] + 801344e: 9a15 ldr r2, [sp, #84] ; 0x54 + 8013450: 920c str r2, [sp, #48] ; 0x30 + 8013452: 9a15 ldr r2, [sp, #84] ; 0x54 + 8013454: 1c57 adds r7, r2, #1 + 8013456: 9715 str r7, [sp, #84] ; 0x54 + 8013458: 7852 ldrb r2, [r2, #1] + 801345a: f1a2 0e30 sub.w lr, r2, #48 ; 0x30 + 801345e: f1be 0f09 cmp.w lr, #9 + 8013462: d938 bls.n 80134d6 <_strtod_l+0x33e> + 8013464: 990c ldr r1, [sp, #48] ; 0x30 + 8013466: 1a7f subs r7, r7, r1 + 8013468: 2f08 cmp r7, #8 + 801346a: f644 671f movw r7, #19999 ; 0x4e1f + 801346e: dc03 bgt.n 8013478 <_strtod_l+0x2e0> + 8013470: 9908 ldr r1, [sp, #32] + 8013472: 428f cmp r7, r1 + 8013474: bfa8 it ge + 8013476: 460f movge r7, r1 + 8013478: f1bc 0f00 cmp.w ip, #0 + 801347c: d000 beq.n 8013480 <_strtod_l+0x2e8> + 801347e: 427f negs r7, r7 + 8013480: 2e00 cmp r6, #0 + 8013482: d14f bne.n 8013524 <_strtod_l+0x38c> + 8013484: 9904 ldr r1, [sp, #16] + 8013486: 4301 orrs r1, r0 + 8013488: f47f aec1 bne.w 801320e <_strtod_l+0x76> + 801348c: 2b00 cmp r3, #0 + 801348e: f47f aedb bne.w 8013248 <_strtod_l+0xb0> + 8013492: 2a69 cmp r2, #105 ; 0x69 + 8013494: d029 beq.n 80134ea <_strtod_l+0x352> + 8013496: dc26 bgt.n 80134e6 <_strtod_l+0x34e> + 8013498: 2a49 cmp r2, #73 ; 0x49 + 801349a: d026 beq.n 80134ea <_strtod_l+0x352> + 801349c: 2a4e cmp r2, #78 ; 0x4e + 801349e: f47f aed3 bne.w 8013248 <_strtod_l+0xb0> + 80134a2: 499b ldr r1, [pc, #620] ; (8013710 <_strtod_l+0x578>) + 80134a4: a815 add r0, sp, #84 ; 0x54 + 80134a6: f002 fff5 bl 8016494 <__match> + 80134aa: 2800 cmp r0, #0 + 80134ac: f43f aecc beq.w 8013248 <_strtod_l+0xb0> + 80134b0: 9b15 ldr r3, [sp, #84] ; 0x54 + 80134b2: 781b ldrb r3, [r3, #0] + 80134b4: 2b28 cmp r3, #40 ; 0x28 + 80134b6: d12f bne.n 8013518 <_strtod_l+0x380> + 80134b8: 4996 ldr r1, [pc, #600] ; (8013714 <_strtod_l+0x57c>) + 80134ba: aa18 add r2, sp, #96 ; 0x60 + 80134bc: a815 add r0, sp, #84 ; 0x54 + 80134be: f002 fffd bl 80164bc <__hexnan> + 80134c2: 2805 cmp r0, #5 + 80134c4: d128 bne.n 8013518 <_strtod_l+0x380> + 80134c6: 9b19 ldr r3, [sp, #100] ; 0x64 + 80134c8: f8dd 8060 ldr.w r8, [sp, #96] ; 0x60 + 80134cc: f043 49ff orr.w r9, r3, #2139095040 ; 0x7f800000 + 80134d0: f449 09e0 orr.w r9, r9, #7340032 ; 0x700000 + 80134d4: e69b b.n 801320e <_strtod_l+0x76> + 80134d6: 9f08 ldr r7, [sp, #32] + 80134d8: 210a movs r1, #10 + 80134da: fb01 2107 mla r1, r1, r7, r2 + 80134de: f1a1 0230 sub.w r2, r1, #48 ; 0x30 + 80134e2: 9208 str r2, [sp, #32] + 80134e4: e7b5 b.n 8013452 <_strtod_l+0x2ba> + 80134e6: 2a6e cmp r2, #110 ; 0x6e + 80134e8: e7d9 b.n 801349e <_strtod_l+0x306> + 80134ea: 498b ldr r1, [pc, #556] ; (8013718 <_strtod_l+0x580>) + 80134ec: a815 add r0, sp, #84 ; 0x54 + 80134ee: f002 ffd1 bl 8016494 <__match> + 80134f2: 2800 cmp r0, #0 + 80134f4: f43f aea8 beq.w 8013248 <_strtod_l+0xb0> + 80134f8: 9b15 ldr r3, [sp, #84] ; 0x54 + 80134fa: 4988 ldr r1, [pc, #544] ; (801371c <_strtod_l+0x584>) + 80134fc: 3b01 subs r3, #1 + 80134fe: a815 add r0, sp, #84 ; 0x54 + 8013500: 9315 str r3, [sp, #84] ; 0x54 + 8013502: f002 ffc7 bl 8016494 <__match> + 8013506: b910 cbnz r0, 801350e <_strtod_l+0x376> + 8013508: 9b15 ldr r3, [sp, #84] ; 0x54 + 801350a: 3301 adds r3, #1 + 801350c: 9315 str r3, [sp, #84] ; 0x54 + 801350e: f8df 921c ldr.w r9, [pc, #540] ; 801372c <_strtod_l+0x594> + 8013512: f04f 0800 mov.w r8, #0 + 8013516: e67a b.n 801320e <_strtod_l+0x76> + 8013518: 4881 ldr r0, [pc, #516] ; (8013720 <_strtod_l+0x588>) + 801351a: f001 fe21 bl 8015160 + 801351e: ec59 8b10 vmov r8, r9, d0 + 8013522: e674 b.n 801320e <_strtod_l+0x76> + 8013524: 9b05 ldr r3, [sp, #20] + 8013526: 9809 ldr r0, [sp, #36] ; 0x24 + 8013528: 1afb subs r3, r7, r3 + 801352a: f1bb 0f00 cmp.w fp, #0 + 801352e: bf08 it eq + 8013530: 46b3 moveq fp, r6 + 8013532: 2e10 cmp r6, #16 + 8013534: 9308 str r3, [sp, #32] + 8013536: 4635 mov r5, r6 + 8013538: bfa8 it ge + 801353a: 2510 movge r5, #16 + 801353c: f7ec ffe2 bl 8000504 <__aeabi_ui2d> + 8013540: 2e09 cmp r6, #9 + 8013542: 4680 mov r8, r0 + 8013544: 4689 mov r9, r1 + 8013546: dd13 ble.n 8013570 <_strtod_l+0x3d8> + 8013548: 4b76 ldr r3, [pc, #472] ; (8013724 <_strtod_l+0x58c>) + 801354a: eb03 03c5 add.w r3, r3, r5, lsl #3 + 801354e: e953 2312 ldrd r2, r3, [r3, #-72] ; 0x48 + 8013552: f7ed f851 bl 80005f8 <__aeabi_dmul> + 8013556: 4680 mov r8, r0 + 8013558: 4650 mov r0, sl + 801355a: 4689 mov r9, r1 + 801355c: f7ec ffd2 bl 8000504 <__aeabi_ui2d> + 8013560: 4602 mov r2, r0 + 8013562: 460b mov r3, r1 + 8013564: 4640 mov r0, r8 + 8013566: 4649 mov r1, r9 + 8013568: f7ec fe90 bl 800028c <__adddf3> + 801356c: 4680 mov r8, r0 + 801356e: 4689 mov r9, r1 + 8013570: 2e0f cmp r6, #15 + 8013572: dc38 bgt.n 80135e6 <_strtod_l+0x44e> + 8013574: 9b08 ldr r3, [sp, #32] + 8013576: 2b00 cmp r3, #0 + 8013578: f43f ae49 beq.w 801320e <_strtod_l+0x76> + 801357c: dd24 ble.n 80135c8 <_strtod_l+0x430> + 801357e: 2b16 cmp r3, #22 + 8013580: dc0b bgt.n 801359a <_strtod_l+0x402> + 8013582: 4968 ldr r1, [pc, #416] ; (8013724 <_strtod_l+0x58c>) + 8013584: eb01 01c3 add.w r1, r1, r3, lsl #3 + 8013588: e9d1 0100 ldrd r0, r1, [r1] + 801358c: 4642 mov r2, r8 + 801358e: 464b mov r3, r9 + 8013590: f7ed f832 bl 80005f8 <__aeabi_dmul> + 8013594: 4680 mov r8, r0 + 8013596: 4689 mov r9, r1 + 8013598: e639 b.n 801320e <_strtod_l+0x76> + 801359a: 9a08 ldr r2, [sp, #32] + 801359c: f1c6 0325 rsb r3, r6, #37 ; 0x25 + 80135a0: 4293 cmp r3, r2 + 80135a2: db20 blt.n 80135e6 <_strtod_l+0x44e> + 80135a4: 4c5f ldr r4, [pc, #380] ; (8013724 <_strtod_l+0x58c>) + 80135a6: f1c6 060f rsb r6, r6, #15 + 80135aa: eb04 01c6 add.w r1, r4, r6, lsl #3 + 80135ae: 4642 mov r2, r8 + 80135b0: 464b mov r3, r9 + 80135b2: e9d1 0100 ldrd r0, r1, [r1] + 80135b6: f7ed f81f bl 80005f8 <__aeabi_dmul> + 80135ba: 9b08 ldr r3, [sp, #32] + 80135bc: 1b9e subs r6, r3, r6 + 80135be: eb04 04c6 add.w r4, r4, r6, lsl #3 + 80135c2: e9d4 2300 ldrd r2, r3, [r4] + 80135c6: e7e3 b.n 8013590 <_strtod_l+0x3f8> + 80135c8: 9b08 ldr r3, [sp, #32] + 80135ca: 3316 adds r3, #22 + 80135cc: db0b blt.n 80135e6 <_strtod_l+0x44e> + 80135ce: 9b05 ldr r3, [sp, #20] + 80135d0: 1bdf subs r7, r3, r7 + 80135d2: 4b54 ldr r3, [pc, #336] ; (8013724 <_strtod_l+0x58c>) + 80135d4: eb03 07c7 add.w r7, r3, r7, lsl #3 + 80135d8: e9d7 2300 ldrd r2, r3, [r7] + 80135dc: 4640 mov r0, r8 + 80135de: 4649 mov r1, r9 + 80135e0: f7ed f934 bl 800084c <__aeabi_ddiv> + 80135e4: e7d6 b.n 8013594 <_strtod_l+0x3fc> + 80135e6: 9b08 ldr r3, [sp, #32] + 80135e8: 1b75 subs r5, r6, r5 + 80135ea: 441d add r5, r3 + 80135ec: 2d00 cmp r5, #0 + 80135ee: dd70 ble.n 80136d2 <_strtod_l+0x53a> + 80135f0: f015 030f ands.w r3, r5, #15 + 80135f4: d00a beq.n 801360c <_strtod_l+0x474> + 80135f6: 494b ldr r1, [pc, #300] ; (8013724 <_strtod_l+0x58c>) + 80135f8: eb01 01c3 add.w r1, r1, r3, lsl #3 + 80135fc: 4642 mov r2, r8 + 80135fe: 464b mov r3, r9 + 8013600: e9d1 0100 ldrd r0, r1, [r1] + 8013604: f7ec fff8 bl 80005f8 <__aeabi_dmul> + 8013608: 4680 mov r8, r0 + 801360a: 4689 mov r9, r1 + 801360c: f035 050f bics.w r5, r5, #15 + 8013610: d04d beq.n 80136ae <_strtod_l+0x516> + 8013612: f5b5 7f9a cmp.w r5, #308 ; 0x134 + 8013616: dd22 ble.n 801365e <_strtod_l+0x4c6> + 8013618: 2500 movs r5, #0 + 801361a: 46ab mov fp, r5 + 801361c: 9509 str r5, [sp, #36] ; 0x24 + 801361e: 9505 str r5, [sp, #20] + 8013620: 2322 movs r3, #34 ; 0x22 + 8013622: f8df 9108 ldr.w r9, [pc, #264] ; 801372c <_strtod_l+0x594> + 8013626: 6023 str r3, [r4, #0] + 8013628: f04f 0800 mov.w r8, #0 + 801362c: 9b09 ldr r3, [sp, #36] ; 0x24 + 801362e: 2b00 cmp r3, #0 + 8013630: f43f aded beq.w 801320e <_strtod_l+0x76> + 8013634: 9916 ldr r1, [sp, #88] ; 0x58 + 8013636: 4620 mov r0, r4 + 8013638: f003 f82e bl 8016698 <_Bfree> + 801363c: 9905 ldr r1, [sp, #20] + 801363e: 4620 mov r0, r4 + 8013640: f003 f82a bl 8016698 <_Bfree> + 8013644: 4659 mov r1, fp + 8013646: 4620 mov r0, r4 + 8013648: f003 f826 bl 8016698 <_Bfree> + 801364c: 9909 ldr r1, [sp, #36] ; 0x24 + 801364e: 4620 mov r0, r4 + 8013650: f003 f822 bl 8016698 <_Bfree> + 8013654: 4629 mov r1, r5 + 8013656: 4620 mov r0, r4 + 8013658: f003 f81e bl 8016698 <_Bfree> + 801365c: e5d7 b.n 801320e <_strtod_l+0x76> + 801365e: 4b32 ldr r3, [pc, #200] ; (8013728 <_strtod_l+0x590>) + 8013660: 9304 str r3, [sp, #16] + 8013662: 2300 movs r3, #0 + 8013664: 112d asrs r5, r5, #4 + 8013666: 4640 mov r0, r8 + 8013668: 4649 mov r1, r9 + 801366a: 469a mov sl, r3 + 801366c: 2d01 cmp r5, #1 + 801366e: dc21 bgt.n 80136b4 <_strtod_l+0x51c> + 8013670: b10b cbz r3, 8013676 <_strtod_l+0x4de> + 8013672: 4680 mov r8, r0 + 8013674: 4689 mov r9, r1 + 8013676: 492c ldr r1, [pc, #176] ; (8013728 <_strtod_l+0x590>) + 8013678: f1a9 7954 sub.w r9, r9, #55574528 ; 0x3500000 + 801367c: eb01 01ca add.w r1, r1, sl, lsl #3 + 8013680: 4642 mov r2, r8 + 8013682: 464b mov r3, r9 + 8013684: e9d1 0100 ldrd r0, r1, [r1] + 8013688: f7ec ffb6 bl 80005f8 <__aeabi_dmul> + 801368c: 4b27 ldr r3, [pc, #156] ; (801372c <_strtod_l+0x594>) + 801368e: 460a mov r2, r1 + 8013690: 400b ands r3, r1 + 8013692: 4927 ldr r1, [pc, #156] ; (8013730 <_strtod_l+0x598>) + 8013694: 428b cmp r3, r1 + 8013696: 4680 mov r8, r0 + 8013698: d8be bhi.n 8013618 <_strtod_l+0x480> + 801369a: f5a1 1180 sub.w r1, r1, #1048576 ; 0x100000 + 801369e: 428b cmp r3, r1 + 80136a0: bf86 itte hi + 80136a2: f8df 9090 ldrhi.w r9, [pc, #144] ; 8013734 <_strtod_l+0x59c> + 80136a6: f04f 38ff movhi.w r8, #4294967295 + 80136aa: f102 7954 addls.w r9, r2, #55574528 ; 0x3500000 + 80136ae: 2300 movs r3, #0 + 80136b0: 9304 str r3, [sp, #16] + 80136b2: e07b b.n 80137ac <_strtod_l+0x614> + 80136b4: 07ea lsls r2, r5, #31 + 80136b6: d505 bpl.n 80136c4 <_strtod_l+0x52c> + 80136b8: 9b04 ldr r3, [sp, #16] + 80136ba: e9d3 2300 ldrd r2, r3, [r3] + 80136be: f7ec ff9b bl 80005f8 <__aeabi_dmul> + 80136c2: 2301 movs r3, #1 + 80136c4: 9a04 ldr r2, [sp, #16] + 80136c6: 3208 adds r2, #8 + 80136c8: f10a 0a01 add.w sl, sl, #1 + 80136cc: 106d asrs r5, r5, #1 + 80136ce: 9204 str r2, [sp, #16] + 80136d0: e7cc b.n 801366c <_strtod_l+0x4d4> + 80136d2: d0ec beq.n 80136ae <_strtod_l+0x516> + 80136d4: 426d negs r5, r5 + 80136d6: f015 020f ands.w r2, r5, #15 + 80136da: d00a beq.n 80136f2 <_strtod_l+0x55a> + 80136dc: 4b11 ldr r3, [pc, #68] ; (8013724 <_strtod_l+0x58c>) + 80136de: eb03 03c2 add.w r3, r3, r2, lsl #3 + 80136e2: 4640 mov r0, r8 + 80136e4: 4649 mov r1, r9 + 80136e6: e9d3 2300 ldrd r2, r3, [r3] + 80136ea: f7ed f8af bl 800084c <__aeabi_ddiv> + 80136ee: 4680 mov r8, r0 + 80136f0: 4689 mov r9, r1 + 80136f2: 112d asrs r5, r5, #4 + 80136f4: d0db beq.n 80136ae <_strtod_l+0x516> + 80136f6: 2d1f cmp r5, #31 + 80136f8: dd1e ble.n 8013738 <_strtod_l+0x5a0> + 80136fa: 2500 movs r5, #0 + 80136fc: 46ab mov fp, r5 + 80136fe: 9509 str r5, [sp, #36] ; 0x24 + 8013700: 9505 str r5, [sp, #20] + 8013702: 2322 movs r3, #34 ; 0x22 + 8013704: f04f 0800 mov.w r8, #0 + 8013708: f04f 0900 mov.w r9, #0 + 801370c: 6023 str r3, [r4, #0] + 801370e: e78d b.n 801362c <_strtod_l+0x494> + 8013710: 0801ad4e .word 0x0801ad4e + 8013714: 0801ac04 .word 0x0801ac04 + 8013718: 0801ad46 .word 0x0801ad46 + 801371c: 0801ae32 .word 0x0801ae32 + 8013720: 0801ae2e .word 0x0801ae2e + 8013724: 0801af88 .word 0x0801af88 + 8013728: 0801af60 .word 0x0801af60 + 801372c: 7ff00000 .word 0x7ff00000 + 8013730: 7ca00000 .word 0x7ca00000 + 8013734: 7fefffff .word 0x7fefffff + 8013738: f015 0310 ands.w r3, r5, #16 + 801373c: bf18 it ne + 801373e: 236a movne r3, #106 ; 0x6a + 8013740: f8df a3a0 ldr.w sl, [pc, #928] ; 8013ae4 <_strtod_l+0x94c> + 8013744: 9304 str r3, [sp, #16] + 8013746: 4640 mov r0, r8 + 8013748: 4649 mov r1, r9 + 801374a: 2300 movs r3, #0 + 801374c: 07ea lsls r2, r5, #31 + 801374e: d504 bpl.n 801375a <_strtod_l+0x5c2> + 8013750: e9da 2300 ldrd r2, r3, [sl] + 8013754: f7ec ff50 bl 80005f8 <__aeabi_dmul> + 8013758: 2301 movs r3, #1 + 801375a: 106d asrs r5, r5, #1 + 801375c: f10a 0a08 add.w sl, sl, #8 + 8013760: d1f4 bne.n 801374c <_strtod_l+0x5b4> + 8013762: b10b cbz r3, 8013768 <_strtod_l+0x5d0> + 8013764: 4680 mov r8, r0 + 8013766: 4689 mov r9, r1 + 8013768: 9b04 ldr r3, [sp, #16] + 801376a: b1bb cbz r3, 801379c <_strtod_l+0x604> + 801376c: f3c9 520a ubfx r2, r9, #20, #11 + 8013770: f1c2 036b rsb r3, r2, #107 ; 0x6b + 8013774: 2b00 cmp r3, #0 + 8013776: 4649 mov r1, r9 + 8013778: dd10 ble.n 801379c <_strtod_l+0x604> + 801377a: 2b1f cmp r3, #31 + 801377c: f340 811e ble.w 80139bc <_strtod_l+0x824> + 8013780: 2b34 cmp r3, #52 ; 0x34 + 8013782: bfde ittt le + 8013784: f04f 33ff movle.w r3, #4294967295 + 8013788: f1c2 024b rsble r2, r2, #75 ; 0x4b + 801378c: 4093 lslle r3, r2 + 801378e: f04f 0800 mov.w r8, #0 + 8013792: bfcc ite gt + 8013794: f04f 795c movgt.w r9, #57671680 ; 0x3700000 + 8013798: ea03 0901 andle.w r9, r3, r1 + 801379c: 2200 movs r2, #0 + 801379e: 2300 movs r3, #0 + 80137a0: 4640 mov r0, r8 + 80137a2: 4649 mov r1, r9 + 80137a4: f7ed f990 bl 8000ac8 <__aeabi_dcmpeq> + 80137a8: 2800 cmp r0, #0 + 80137aa: d1a6 bne.n 80136fa <_strtod_l+0x562> + 80137ac: 9b09 ldr r3, [sp, #36] ; 0x24 + 80137ae: 9300 str r3, [sp, #0] + 80137b0: 990b ldr r1, [sp, #44] ; 0x2c + 80137b2: 4633 mov r3, r6 + 80137b4: 465a mov r2, fp + 80137b6: 4620 mov r0, r4 + 80137b8: f002 ffd6 bl 8016768 <__s2b> + 80137bc: 9009 str r0, [sp, #36] ; 0x24 + 80137be: 2800 cmp r0, #0 + 80137c0: f43f af2a beq.w 8013618 <_strtod_l+0x480> + 80137c4: 9a08 ldr r2, [sp, #32] + 80137c6: 9b05 ldr r3, [sp, #20] + 80137c8: 2a00 cmp r2, #0 + 80137ca: eba3 0307 sub.w r3, r3, r7 + 80137ce: bfa8 it ge + 80137d0: 2300 movge r3, #0 + 80137d2: 930c str r3, [sp, #48] ; 0x30 + 80137d4: 2500 movs r5, #0 + 80137d6: ea22 73e2 bic.w r3, r2, r2, asr #31 + 80137da: 9312 str r3, [sp, #72] ; 0x48 + 80137dc: 46ab mov fp, r5 + 80137de: 9b09 ldr r3, [sp, #36] ; 0x24 + 80137e0: 4620 mov r0, r4 + 80137e2: 6859 ldr r1, [r3, #4] + 80137e4: f002 ff18 bl 8016618 <_Balloc> + 80137e8: 9005 str r0, [sp, #20] + 80137ea: 2800 cmp r0, #0 + 80137ec: f43f af18 beq.w 8013620 <_strtod_l+0x488> + 80137f0: 9b09 ldr r3, [sp, #36] ; 0x24 + 80137f2: 691a ldr r2, [r3, #16] + 80137f4: 3202 adds r2, #2 + 80137f6: f103 010c add.w r1, r3, #12 + 80137fa: 0092 lsls r2, r2, #2 + 80137fc: 300c adds r0, #12 + 80137fe: f001 fca0 bl 8015142 + 8013802: ec49 8b10 vmov d0, r8, r9 + 8013806: aa18 add r2, sp, #96 ; 0x60 + 8013808: a917 add r1, sp, #92 ; 0x5c + 801380a: 4620 mov r0, r4 + 801380c: f003 fae0 bl 8016dd0 <__d2b> + 8013810: ec49 8b18 vmov d8, r8, r9 + 8013814: 9016 str r0, [sp, #88] ; 0x58 + 8013816: 2800 cmp r0, #0 + 8013818: f43f af02 beq.w 8013620 <_strtod_l+0x488> + 801381c: 2101 movs r1, #1 + 801381e: 4620 mov r0, r4 + 8013820: f003 f83a bl 8016898 <__i2b> + 8013824: 4683 mov fp, r0 + 8013826: 2800 cmp r0, #0 + 8013828: f43f aefa beq.w 8013620 <_strtod_l+0x488> + 801382c: 9e17 ldr r6, [sp, #92] ; 0x5c + 801382e: 9a18 ldr r2, [sp, #96] ; 0x60 + 8013830: 2e00 cmp r6, #0 + 8013832: bfab itete ge + 8013834: 9b0c ldrge r3, [sp, #48] ; 0x30 + 8013836: 9b12 ldrlt r3, [sp, #72] ; 0x48 + 8013838: 9f12 ldrge r7, [sp, #72] ; 0x48 + 801383a: f8dd a030 ldrlt.w sl, [sp, #48] ; 0x30 + 801383e: bfac ite ge + 8013840: eb06 0a03 addge.w sl, r6, r3 + 8013844: 1b9f sublt r7, r3, r6 + 8013846: 9b04 ldr r3, [sp, #16] + 8013848: 1af6 subs r6, r6, r3 + 801384a: 4416 add r6, r2 + 801384c: 4ba0 ldr r3, [pc, #640] ; (8013ad0 <_strtod_l+0x938>) + 801384e: 3e01 subs r6, #1 + 8013850: 429e cmp r6, r3 + 8013852: f1c2 0236 rsb r2, r2, #54 ; 0x36 + 8013856: f280 80c4 bge.w 80139e2 <_strtod_l+0x84a> + 801385a: 1b9b subs r3, r3, r6 + 801385c: 2b1f cmp r3, #31 + 801385e: eba2 0203 sub.w r2, r2, r3 + 8013862: f04f 0101 mov.w r1, #1 + 8013866: f300 80b0 bgt.w 80139ca <_strtod_l+0x832> + 801386a: fa01 f303 lsl.w r3, r1, r3 + 801386e: 930e str r3, [sp, #56] ; 0x38 + 8013870: 2300 movs r3, #0 + 8013872: 930d str r3, [sp, #52] ; 0x34 + 8013874: eb0a 0602 add.w r6, sl, r2 + 8013878: 9b04 ldr r3, [sp, #16] + 801387a: 45b2 cmp sl, r6 + 801387c: 4417 add r7, r2 + 801387e: 441f add r7, r3 + 8013880: 4653 mov r3, sl + 8013882: bfa8 it ge + 8013884: 4633 movge r3, r6 + 8013886: 42bb cmp r3, r7 + 8013888: bfa8 it ge + 801388a: 463b movge r3, r7 + 801388c: 2b00 cmp r3, #0 + 801388e: bfc2 ittt gt + 8013890: 1af6 subgt r6, r6, r3 + 8013892: 1aff subgt r7, r7, r3 + 8013894: ebaa 0a03 subgt.w sl, sl, r3 + 8013898: 9b0c ldr r3, [sp, #48] ; 0x30 + 801389a: 2b00 cmp r3, #0 + 801389c: dd17 ble.n 80138ce <_strtod_l+0x736> + 801389e: 4659 mov r1, fp + 80138a0: 461a mov r2, r3 + 80138a2: 4620 mov r0, r4 + 80138a4: f003 f8b8 bl 8016a18 <__pow5mult> + 80138a8: 4683 mov fp, r0 + 80138aa: 2800 cmp r0, #0 + 80138ac: f43f aeb8 beq.w 8013620 <_strtod_l+0x488> + 80138b0: 4601 mov r1, r0 + 80138b2: 9a16 ldr r2, [sp, #88] ; 0x58 + 80138b4: 4620 mov r0, r4 + 80138b6: f003 f805 bl 80168c4 <__multiply> + 80138ba: 900b str r0, [sp, #44] ; 0x2c + 80138bc: 2800 cmp r0, #0 + 80138be: f43f aeaf beq.w 8013620 <_strtod_l+0x488> + 80138c2: 9916 ldr r1, [sp, #88] ; 0x58 + 80138c4: 4620 mov r0, r4 + 80138c6: f002 fee7 bl 8016698 <_Bfree> + 80138ca: 9b0b ldr r3, [sp, #44] ; 0x2c + 80138cc: 9316 str r3, [sp, #88] ; 0x58 + 80138ce: 2e00 cmp r6, #0 + 80138d0: f300 808c bgt.w 80139ec <_strtod_l+0x854> + 80138d4: 9b08 ldr r3, [sp, #32] + 80138d6: 2b00 cmp r3, #0 + 80138d8: dd08 ble.n 80138ec <_strtod_l+0x754> + 80138da: 9a12 ldr r2, [sp, #72] ; 0x48 + 80138dc: 9905 ldr r1, [sp, #20] + 80138de: 4620 mov r0, r4 + 80138e0: f003 f89a bl 8016a18 <__pow5mult> + 80138e4: 9005 str r0, [sp, #20] + 80138e6: 2800 cmp r0, #0 + 80138e8: f43f ae9a beq.w 8013620 <_strtod_l+0x488> + 80138ec: 2f00 cmp r7, #0 + 80138ee: dd08 ble.n 8013902 <_strtod_l+0x76a> + 80138f0: 9905 ldr r1, [sp, #20] + 80138f2: 463a mov r2, r7 + 80138f4: 4620 mov r0, r4 + 80138f6: f003 f8e9 bl 8016acc <__lshift> + 80138fa: 9005 str r0, [sp, #20] + 80138fc: 2800 cmp r0, #0 + 80138fe: f43f ae8f beq.w 8013620 <_strtod_l+0x488> + 8013902: f1ba 0f00 cmp.w sl, #0 + 8013906: dd08 ble.n 801391a <_strtod_l+0x782> + 8013908: 4659 mov r1, fp + 801390a: 4652 mov r2, sl + 801390c: 4620 mov r0, r4 + 801390e: f003 f8dd bl 8016acc <__lshift> + 8013912: 4683 mov fp, r0 + 8013914: 2800 cmp r0, #0 + 8013916: f43f ae83 beq.w 8013620 <_strtod_l+0x488> + 801391a: 9a05 ldr r2, [sp, #20] + 801391c: 9916 ldr r1, [sp, #88] ; 0x58 + 801391e: 4620 mov r0, r4 + 8013920: f003 f95c bl 8016bdc <__mdiff> + 8013924: 4605 mov r5, r0 + 8013926: 2800 cmp r0, #0 + 8013928: f43f ae7a beq.w 8013620 <_strtod_l+0x488> + 801392c: 68c3 ldr r3, [r0, #12] + 801392e: 930b str r3, [sp, #44] ; 0x2c + 8013930: 2300 movs r3, #0 + 8013932: 60c3 str r3, [r0, #12] + 8013934: 4659 mov r1, fp + 8013936: f003 f935 bl 8016ba4 <__mcmp> + 801393a: 2800 cmp r0, #0 + 801393c: da60 bge.n 8013a00 <_strtod_l+0x868> + 801393e: 9b0b ldr r3, [sp, #44] ; 0x2c + 8013940: ea53 0308 orrs.w r3, r3, r8 + 8013944: f040 8084 bne.w 8013a50 <_strtod_l+0x8b8> + 8013948: f3c9 0313 ubfx r3, r9, #0, #20 + 801394c: 2b00 cmp r3, #0 + 801394e: d17f bne.n 8013a50 <_strtod_l+0x8b8> + 8013950: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 8013954: 0d1b lsrs r3, r3, #20 + 8013956: 051b lsls r3, r3, #20 + 8013958: f1b3 6fd6 cmp.w r3, #112197632 ; 0x6b00000 + 801395c: d978 bls.n 8013a50 <_strtod_l+0x8b8> + 801395e: 696b ldr r3, [r5, #20] + 8013960: b913 cbnz r3, 8013968 <_strtod_l+0x7d0> + 8013962: 692b ldr r3, [r5, #16] + 8013964: 2b01 cmp r3, #1 + 8013966: dd73 ble.n 8013a50 <_strtod_l+0x8b8> + 8013968: 4629 mov r1, r5 + 801396a: 2201 movs r2, #1 + 801396c: 4620 mov r0, r4 + 801396e: f003 f8ad bl 8016acc <__lshift> + 8013972: 4659 mov r1, fp + 8013974: 4605 mov r5, r0 + 8013976: f003 f915 bl 8016ba4 <__mcmp> + 801397a: 2800 cmp r0, #0 + 801397c: dd68 ble.n 8013a50 <_strtod_l+0x8b8> + 801397e: 9904 ldr r1, [sp, #16] + 8013980: 4a54 ldr r2, [pc, #336] ; (8013ad4 <_strtod_l+0x93c>) + 8013982: 464b mov r3, r9 + 8013984: 2900 cmp r1, #0 + 8013986: f000 8084 beq.w 8013a92 <_strtod_l+0x8fa> + 801398a: ea02 0109 and.w r1, r2, r9 + 801398e: f1b1 6fd6 cmp.w r1, #112197632 ; 0x6b00000 + 8013992: dc7e bgt.n 8013a92 <_strtod_l+0x8fa> + 8013994: f1b1 7f5c cmp.w r1, #57671680 ; 0x3700000 + 8013998: f77f aeb3 ble.w 8013702 <_strtod_l+0x56a> + 801399c: 4b4e ldr r3, [pc, #312] ; (8013ad8 <_strtod_l+0x940>) + 801399e: 4640 mov r0, r8 + 80139a0: 4649 mov r1, r9 + 80139a2: 2200 movs r2, #0 + 80139a4: f7ec fe28 bl 80005f8 <__aeabi_dmul> + 80139a8: 4b4a ldr r3, [pc, #296] ; (8013ad4 <_strtod_l+0x93c>) + 80139aa: 400b ands r3, r1 + 80139ac: 4680 mov r8, r0 + 80139ae: 4689 mov r9, r1 + 80139b0: 2b00 cmp r3, #0 + 80139b2: f47f ae3f bne.w 8013634 <_strtod_l+0x49c> + 80139b6: 2322 movs r3, #34 ; 0x22 + 80139b8: 6023 str r3, [r4, #0] + 80139ba: e63b b.n 8013634 <_strtod_l+0x49c> + 80139bc: f04f 32ff mov.w r2, #4294967295 + 80139c0: fa02 f303 lsl.w r3, r2, r3 + 80139c4: ea03 0808 and.w r8, r3, r8 + 80139c8: e6e8 b.n 801379c <_strtod_l+0x604> + 80139ca: f1c6 467f rsb r6, r6, #4278190080 ; 0xff000000 + 80139ce: f506 067f add.w r6, r6, #16711680 ; 0xff0000 + 80139d2: f506 467b add.w r6, r6, #64256 ; 0xfb00 + 80139d6: 36e2 adds r6, #226 ; 0xe2 + 80139d8: fa01 f306 lsl.w r3, r1, r6 + 80139dc: e9cd 310d strd r3, r1, [sp, #52] ; 0x34 + 80139e0: e748 b.n 8013874 <_strtod_l+0x6dc> + 80139e2: 2100 movs r1, #0 + 80139e4: 2301 movs r3, #1 + 80139e6: e9cd 130d strd r1, r3, [sp, #52] ; 0x34 + 80139ea: e743 b.n 8013874 <_strtod_l+0x6dc> + 80139ec: 9916 ldr r1, [sp, #88] ; 0x58 + 80139ee: 4632 mov r2, r6 + 80139f0: 4620 mov r0, r4 + 80139f2: f003 f86b bl 8016acc <__lshift> + 80139f6: 9016 str r0, [sp, #88] ; 0x58 + 80139f8: 2800 cmp r0, #0 + 80139fa: f47f af6b bne.w 80138d4 <_strtod_l+0x73c> + 80139fe: e60f b.n 8013620 <_strtod_l+0x488> + 8013a00: 46ca mov sl, r9 + 8013a02: d171 bne.n 8013ae8 <_strtod_l+0x950> + 8013a04: 9a0b ldr r2, [sp, #44] ; 0x2c + 8013a06: f3c9 0313 ubfx r3, r9, #0, #20 + 8013a0a: b352 cbz r2, 8013a62 <_strtod_l+0x8ca> + 8013a0c: 4a33 ldr r2, [pc, #204] ; (8013adc <_strtod_l+0x944>) + 8013a0e: 4293 cmp r3, r2 + 8013a10: d12a bne.n 8013a68 <_strtod_l+0x8d0> + 8013a12: 9b04 ldr r3, [sp, #16] + 8013a14: 4641 mov r1, r8 + 8013a16: b1fb cbz r3, 8013a58 <_strtod_l+0x8c0> + 8013a18: 4b2e ldr r3, [pc, #184] ; (8013ad4 <_strtod_l+0x93c>) + 8013a1a: ea09 0303 and.w r3, r9, r3 + 8013a1e: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 + 8013a22: f04f 32ff mov.w r2, #4294967295 + 8013a26: d81a bhi.n 8013a5e <_strtod_l+0x8c6> + 8013a28: 0d1b lsrs r3, r3, #20 + 8013a2a: f1c3 036b rsb r3, r3, #107 ; 0x6b + 8013a2e: fa02 f303 lsl.w r3, r2, r3 + 8013a32: 4299 cmp r1, r3 + 8013a34: d118 bne.n 8013a68 <_strtod_l+0x8d0> + 8013a36: 4b2a ldr r3, [pc, #168] ; (8013ae0 <_strtod_l+0x948>) + 8013a38: 459a cmp sl, r3 + 8013a3a: d102 bne.n 8013a42 <_strtod_l+0x8aa> + 8013a3c: 3101 adds r1, #1 + 8013a3e: f43f adef beq.w 8013620 <_strtod_l+0x488> + 8013a42: 4b24 ldr r3, [pc, #144] ; (8013ad4 <_strtod_l+0x93c>) + 8013a44: ea0a 0303 and.w r3, sl, r3 + 8013a48: f503 1980 add.w r9, r3, #1048576 ; 0x100000 + 8013a4c: f04f 0800 mov.w r8, #0 + 8013a50: 9b04 ldr r3, [sp, #16] + 8013a52: 2b00 cmp r3, #0 + 8013a54: d1a2 bne.n 801399c <_strtod_l+0x804> + 8013a56: e5ed b.n 8013634 <_strtod_l+0x49c> + 8013a58: f04f 33ff mov.w r3, #4294967295 + 8013a5c: e7e9 b.n 8013a32 <_strtod_l+0x89a> + 8013a5e: 4613 mov r3, r2 + 8013a60: e7e7 b.n 8013a32 <_strtod_l+0x89a> + 8013a62: ea53 0308 orrs.w r3, r3, r8 + 8013a66: d08a beq.n 801397e <_strtod_l+0x7e6> + 8013a68: 9b0d ldr r3, [sp, #52] ; 0x34 + 8013a6a: b1e3 cbz r3, 8013aa6 <_strtod_l+0x90e> + 8013a6c: ea13 0f0a tst.w r3, sl + 8013a70: d0ee beq.n 8013a50 <_strtod_l+0x8b8> + 8013a72: 9b0b ldr r3, [sp, #44] ; 0x2c + 8013a74: 9a04 ldr r2, [sp, #16] + 8013a76: 4640 mov r0, r8 + 8013a78: 4649 mov r1, r9 + 8013a7a: b1c3 cbz r3, 8013aae <_strtod_l+0x916> + 8013a7c: f7ff fb6e bl 801315c + 8013a80: 4602 mov r2, r0 + 8013a82: 460b mov r3, r1 + 8013a84: ec51 0b18 vmov r0, r1, d8 + 8013a88: f7ec fc00 bl 800028c <__adddf3> + 8013a8c: 4680 mov r8, r0 + 8013a8e: 4689 mov r9, r1 + 8013a90: e7de b.n 8013a50 <_strtod_l+0x8b8> + 8013a92: 4013 ands r3, r2 + 8013a94: f5a3 1380 sub.w r3, r3, #1048576 ; 0x100000 + 8013a98: ea6f 5913 mvn.w r9, r3, lsr #20 + 8013a9c: ea6f 5909 mvn.w r9, r9, lsl #20 + 8013aa0: f04f 38ff mov.w r8, #4294967295 + 8013aa4: e7d4 b.n 8013a50 <_strtod_l+0x8b8> + 8013aa6: 9b0e ldr r3, [sp, #56] ; 0x38 + 8013aa8: ea13 0f08 tst.w r3, r8 + 8013aac: e7e0 b.n 8013a70 <_strtod_l+0x8d8> + 8013aae: f7ff fb55 bl 801315c + 8013ab2: 4602 mov r2, r0 + 8013ab4: 460b mov r3, r1 + 8013ab6: ec51 0b18 vmov r0, r1, d8 + 8013aba: f7ec fbe5 bl 8000288 <__aeabi_dsub> + 8013abe: 2200 movs r2, #0 + 8013ac0: 2300 movs r3, #0 + 8013ac2: 4680 mov r8, r0 + 8013ac4: 4689 mov r9, r1 + 8013ac6: f7ec ffff bl 8000ac8 <__aeabi_dcmpeq> + 8013aca: 2800 cmp r0, #0 + 8013acc: d0c0 beq.n 8013a50 <_strtod_l+0x8b8> + 8013ace: e618 b.n 8013702 <_strtod_l+0x56a> + 8013ad0: fffffc02 .word 0xfffffc02 + 8013ad4: 7ff00000 .word 0x7ff00000 + 8013ad8: 39500000 .word 0x39500000 + 8013adc: 000fffff .word 0x000fffff + 8013ae0: 7fefffff .word 0x7fefffff + 8013ae4: 0801ac18 .word 0x0801ac18 + 8013ae8: 4659 mov r1, fp + 8013aea: 4628 mov r0, r5 + 8013aec: f003 f9ca bl 8016e84 <__ratio> + 8013af0: ec57 6b10 vmov r6, r7, d0 + 8013af4: ee10 0a10 vmov r0, s0 + 8013af8: 2200 movs r2, #0 + 8013afa: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 + 8013afe: 4639 mov r1, r7 + 8013b00: f7ec fff6 bl 8000af0 <__aeabi_dcmple> + 8013b04: 2800 cmp r0, #0 + 8013b06: d071 beq.n 8013bec <_strtod_l+0xa54> + 8013b08: 9b0b ldr r3, [sp, #44] ; 0x2c + 8013b0a: 2b00 cmp r3, #0 + 8013b0c: d17c bne.n 8013c08 <_strtod_l+0xa70> + 8013b0e: f1b8 0f00 cmp.w r8, #0 + 8013b12: d15a bne.n 8013bca <_strtod_l+0xa32> + 8013b14: f3c9 0313 ubfx r3, r9, #0, #20 + 8013b18: 2b00 cmp r3, #0 + 8013b1a: d15d bne.n 8013bd8 <_strtod_l+0xa40> + 8013b1c: 4b90 ldr r3, [pc, #576] ; (8013d60 <_strtod_l+0xbc8>) + 8013b1e: 2200 movs r2, #0 + 8013b20: 4630 mov r0, r6 + 8013b22: 4639 mov r1, r7 + 8013b24: f7ec ffda bl 8000adc <__aeabi_dcmplt> + 8013b28: 2800 cmp r0, #0 + 8013b2a: d15c bne.n 8013be6 <_strtod_l+0xa4e> + 8013b2c: 4630 mov r0, r6 + 8013b2e: 4639 mov r1, r7 + 8013b30: 4b8c ldr r3, [pc, #560] ; (8013d64 <_strtod_l+0xbcc>) + 8013b32: 2200 movs r2, #0 + 8013b34: f7ec fd60 bl 80005f8 <__aeabi_dmul> + 8013b38: 4606 mov r6, r0 + 8013b3a: 460f mov r7, r1 + 8013b3c: f107 4300 add.w r3, r7, #2147483648 ; 0x80000000 + 8013b40: 9606 str r6, [sp, #24] + 8013b42: 9307 str r3, [sp, #28] + 8013b44: e9dd 2306 ldrd r2, r3, [sp, #24] + 8013b48: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 + 8013b4c: 4b86 ldr r3, [pc, #536] ; (8013d68 <_strtod_l+0xbd0>) + 8013b4e: ea0a 0303 and.w r3, sl, r3 + 8013b52: 930d str r3, [sp, #52] ; 0x34 + 8013b54: 9a0d ldr r2, [sp, #52] ; 0x34 + 8013b56: 4b85 ldr r3, [pc, #532] ; (8013d6c <_strtod_l+0xbd4>) + 8013b58: 429a cmp r2, r3 + 8013b5a: f040 8090 bne.w 8013c7e <_strtod_l+0xae6> + 8013b5e: f1aa 7954 sub.w r9, sl, #55574528 ; 0x3500000 + 8013b62: ec49 8b10 vmov d0, r8, r9 + 8013b66: f003 f8c3 bl 8016cf0 <__ulp> + 8013b6a: e9dd 2306 ldrd r2, r3, [sp, #24] + 8013b6e: ec51 0b10 vmov r0, r1, d0 + 8013b72: f7ec fd41 bl 80005f8 <__aeabi_dmul> + 8013b76: 4642 mov r2, r8 + 8013b78: 464b mov r3, r9 + 8013b7a: f7ec fb87 bl 800028c <__adddf3> + 8013b7e: 460b mov r3, r1 + 8013b80: 4979 ldr r1, [pc, #484] ; (8013d68 <_strtod_l+0xbd0>) + 8013b82: 4a7b ldr r2, [pc, #492] ; (8013d70 <_strtod_l+0xbd8>) + 8013b84: 4019 ands r1, r3 + 8013b86: 4291 cmp r1, r2 + 8013b88: 4680 mov r8, r0 + 8013b8a: d944 bls.n 8013c16 <_strtod_l+0xa7e> + 8013b8c: ee18 2a90 vmov r2, s17 + 8013b90: 4b78 ldr r3, [pc, #480] ; (8013d74 <_strtod_l+0xbdc>) + 8013b92: 429a cmp r2, r3 + 8013b94: d104 bne.n 8013ba0 <_strtod_l+0xa08> + 8013b96: ee18 3a10 vmov r3, s16 + 8013b9a: 3301 adds r3, #1 + 8013b9c: f43f ad40 beq.w 8013620 <_strtod_l+0x488> + 8013ba0: f8df 91d0 ldr.w r9, [pc, #464] ; 8013d74 <_strtod_l+0xbdc> + 8013ba4: f04f 38ff mov.w r8, #4294967295 + 8013ba8: 9916 ldr r1, [sp, #88] ; 0x58 + 8013baa: 4620 mov r0, r4 + 8013bac: f002 fd74 bl 8016698 <_Bfree> + 8013bb0: 9905 ldr r1, [sp, #20] + 8013bb2: 4620 mov r0, r4 + 8013bb4: f002 fd70 bl 8016698 <_Bfree> + 8013bb8: 4659 mov r1, fp + 8013bba: 4620 mov r0, r4 + 8013bbc: f002 fd6c bl 8016698 <_Bfree> + 8013bc0: 4629 mov r1, r5 + 8013bc2: 4620 mov r0, r4 + 8013bc4: f002 fd68 bl 8016698 <_Bfree> + 8013bc8: e609 b.n 80137de <_strtod_l+0x646> + 8013bca: f1b8 0f01 cmp.w r8, #1 + 8013bce: d103 bne.n 8013bd8 <_strtod_l+0xa40> + 8013bd0: f1b9 0f00 cmp.w r9, #0 + 8013bd4: f43f ad95 beq.w 8013702 <_strtod_l+0x56a> + 8013bd8: ed9f 7b55 vldr d7, [pc, #340] ; 8013d30 <_strtod_l+0xb98> + 8013bdc: 4f60 ldr r7, [pc, #384] ; (8013d60 <_strtod_l+0xbc8>) + 8013bde: ed8d 7b06 vstr d7, [sp, #24] + 8013be2: 2600 movs r6, #0 + 8013be4: e7ae b.n 8013b44 <_strtod_l+0x9ac> + 8013be6: 4f5f ldr r7, [pc, #380] ; (8013d64 <_strtod_l+0xbcc>) + 8013be8: 2600 movs r6, #0 + 8013bea: e7a7 b.n 8013b3c <_strtod_l+0x9a4> + 8013bec: 4b5d ldr r3, [pc, #372] ; (8013d64 <_strtod_l+0xbcc>) + 8013bee: 4630 mov r0, r6 + 8013bf0: 4639 mov r1, r7 + 8013bf2: 2200 movs r2, #0 + 8013bf4: f7ec fd00 bl 80005f8 <__aeabi_dmul> + 8013bf8: 9b0b ldr r3, [sp, #44] ; 0x2c + 8013bfa: 4606 mov r6, r0 + 8013bfc: 460f mov r7, r1 + 8013bfe: 2b00 cmp r3, #0 + 8013c00: d09c beq.n 8013b3c <_strtod_l+0x9a4> + 8013c02: e9cd 6706 strd r6, r7, [sp, #24] + 8013c06: e79d b.n 8013b44 <_strtod_l+0x9ac> + 8013c08: ed9f 7b4b vldr d7, [pc, #300] ; 8013d38 <_strtod_l+0xba0> + 8013c0c: ed8d 7b06 vstr d7, [sp, #24] + 8013c10: ec57 6b17 vmov r6, r7, d7 + 8013c14: e796 b.n 8013b44 <_strtod_l+0x9ac> + 8013c16: f103 7954 add.w r9, r3, #55574528 ; 0x3500000 + 8013c1a: 9b04 ldr r3, [sp, #16] + 8013c1c: 46ca mov sl, r9 + 8013c1e: 2b00 cmp r3, #0 + 8013c20: d1c2 bne.n 8013ba8 <_strtod_l+0xa10> + 8013c22: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 8013c26: 9a0d ldr r2, [sp, #52] ; 0x34 + 8013c28: 0d1b lsrs r3, r3, #20 + 8013c2a: 051b lsls r3, r3, #20 + 8013c2c: 429a cmp r2, r3 + 8013c2e: d1bb bne.n 8013ba8 <_strtod_l+0xa10> + 8013c30: 4630 mov r0, r6 + 8013c32: 4639 mov r1, r7 + 8013c34: f7ed f840 bl 8000cb8 <__aeabi_d2lz> + 8013c38: f7ec fcb0 bl 800059c <__aeabi_l2d> + 8013c3c: 4602 mov r2, r0 + 8013c3e: 460b mov r3, r1 + 8013c40: 4630 mov r0, r6 + 8013c42: 4639 mov r1, r7 + 8013c44: f7ec fb20 bl 8000288 <__aeabi_dsub> + 8013c48: 9a0b ldr r2, [sp, #44] ; 0x2c + 8013c4a: f3c9 0313 ubfx r3, r9, #0, #20 + 8013c4e: ea43 0308 orr.w r3, r3, r8 + 8013c52: 4313 orrs r3, r2 + 8013c54: 4606 mov r6, r0 + 8013c56: 460f mov r7, r1 + 8013c58: d054 beq.n 8013d04 <_strtod_l+0xb6c> + 8013c5a: a339 add r3, pc, #228 ; (adr r3, 8013d40 <_strtod_l+0xba8>) + 8013c5c: e9d3 2300 ldrd r2, r3, [r3] + 8013c60: f7ec ff3c bl 8000adc <__aeabi_dcmplt> + 8013c64: 2800 cmp r0, #0 + 8013c66: f47f ace5 bne.w 8013634 <_strtod_l+0x49c> + 8013c6a: a337 add r3, pc, #220 ; (adr r3, 8013d48 <_strtod_l+0xbb0>) + 8013c6c: e9d3 2300 ldrd r2, r3, [r3] + 8013c70: 4630 mov r0, r6 + 8013c72: 4639 mov r1, r7 + 8013c74: f7ec ff50 bl 8000b18 <__aeabi_dcmpgt> + 8013c78: 2800 cmp r0, #0 + 8013c7a: d095 beq.n 8013ba8 <_strtod_l+0xa10> + 8013c7c: e4da b.n 8013634 <_strtod_l+0x49c> + 8013c7e: 9b04 ldr r3, [sp, #16] + 8013c80: b333 cbz r3, 8013cd0 <_strtod_l+0xb38> + 8013c82: 9b0d ldr r3, [sp, #52] ; 0x34 + 8013c84: f1b3 6fd4 cmp.w r3, #111149056 ; 0x6a00000 + 8013c88: d822 bhi.n 8013cd0 <_strtod_l+0xb38> + 8013c8a: a331 add r3, pc, #196 ; (adr r3, 8013d50 <_strtod_l+0xbb8>) + 8013c8c: e9d3 2300 ldrd r2, r3, [r3] + 8013c90: 4630 mov r0, r6 + 8013c92: 4639 mov r1, r7 + 8013c94: f7ec ff2c bl 8000af0 <__aeabi_dcmple> + 8013c98: b1a0 cbz r0, 8013cc4 <_strtod_l+0xb2c> + 8013c9a: 4639 mov r1, r7 + 8013c9c: 4630 mov r0, r6 + 8013c9e: f7ec ff83 bl 8000ba8 <__aeabi_d2uiz> + 8013ca2: 2801 cmp r0, #1 + 8013ca4: bf38 it cc + 8013ca6: 2001 movcc r0, #1 + 8013ca8: f7ec fc2c bl 8000504 <__aeabi_ui2d> + 8013cac: 9b0b ldr r3, [sp, #44] ; 0x2c + 8013cae: 4606 mov r6, r0 + 8013cb0: 460f mov r7, r1 + 8013cb2: bb23 cbnz r3, 8013cfe <_strtod_l+0xb66> + 8013cb4: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8013cb8: 9010 str r0, [sp, #64] ; 0x40 + 8013cba: 9311 str r3, [sp, #68] ; 0x44 + 8013cbc: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 + 8013cc0: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 + 8013cc4: 9b0f ldr r3, [sp, #60] ; 0x3c + 8013cc6: 9a0d ldr r2, [sp, #52] ; 0x34 + 8013cc8: f103 63d6 add.w r3, r3, #112197632 ; 0x6b00000 + 8013ccc: 1a9b subs r3, r3, r2 + 8013cce: 930f str r3, [sp, #60] ; 0x3c + 8013cd0: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 + 8013cd4: eeb0 0a48 vmov.f32 s0, s16 + 8013cd8: eef0 0a68 vmov.f32 s1, s17 + 8013cdc: e9cd 010e strd r0, r1, [sp, #56] ; 0x38 + 8013ce0: f003 f806 bl 8016cf0 <__ulp> + 8013ce4: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 + 8013ce8: ec53 2b10 vmov r2, r3, d0 + 8013cec: f7ec fc84 bl 80005f8 <__aeabi_dmul> + 8013cf0: ec53 2b18 vmov r2, r3, d8 + 8013cf4: f7ec faca bl 800028c <__adddf3> + 8013cf8: 4680 mov r8, r0 + 8013cfa: 4689 mov r9, r1 + 8013cfc: e78d b.n 8013c1a <_strtod_l+0xa82> + 8013cfe: e9cd 6710 strd r6, r7, [sp, #64] ; 0x40 + 8013d02: e7db b.n 8013cbc <_strtod_l+0xb24> + 8013d04: a314 add r3, pc, #80 ; (adr r3, 8013d58 <_strtod_l+0xbc0>) + 8013d06: e9d3 2300 ldrd r2, r3, [r3] + 8013d0a: f7ec fee7 bl 8000adc <__aeabi_dcmplt> + 8013d0e: e7b3 b.n 8013c78 <_strtod_l+0xae0> + 8013d10: 2300 movs r3, #0 + 8013d12: 930a str r3, [sp, #40] ; 0x28 + 8013d14: 9a13 ldr r2, [sp, #76] ; 0x4c + 8013d16: 9b15 ldr r3, [sp, #84] ; 0x54 + 8013d18: 6013 str r3, [r2, #0] + 8013d1a: f7ff ba7c b.w 8013216 <_strtod_l+0x7e> + 8013d1e: 2a65 cmp r2, #101 ; 0x65 + 8013d20: f43f ab75 beq.w 801340e <_strtod_l+0x276> + 8013d24: 2a45 cmp r2, #69 ; 0x45 + 8013d26: f43f ab72 beq.w 801340e <_strtod_l+0x276> + 8013d2a: 2301 movs r3, #1 + 8013d2c: f7ff bbaa b.w 8013484 <_strtod_l+0x2ec> + 8013d30: 00000000 .word 0x00000000 + 8013d34: bff00000 .word 0xbff00000 + 8013d38: 00000000 .word 0x00000000 + 8013d3c: 3ff00000 .word 0x3ff00000 + 8013d40: 94a03595 .word 0x94a03595 + 8013d44: 3fdfffff .word 0x3fdfffff + 8013d48: 35afe535 .word 0x35afe535 + 8013d4c: 3fe00000 .word 0x3fe00000 + 8013d50: ffc00000 .word 0xffc00000 + 8013d54: 41dfffff .word 0x41dfffff + 8013d58: 94a03595 .word 0x94a03595 + 8013d5c: 3fcfffff .word 0x3fcfffff + 8013d60: 3ff00000 .word 0x3ff00000 + 8013d64: 3fe00000 .word 0x3fe00000 + 8013d68: 7ff00000 .word 0x7ff00000 + 8013d6c: 7fe00000 .word 0x7fe00000 + 8013d70: 7c9fffff .word 0x7c9fffff + 8013d74: 7fefffff .word 0x7fefffff + +08013d78 <_strtod_r>: + 8013d78: 4b01 ldr r3, [pc, #4] ; (8013d80 <_strtod_r+0x8>) + 8013d7a: f7ff ba0d b.w 8013198 <_strtod_l> + 8013d7e: bf00 nop + 8013d80: 20000138 .word 0x20000138 + +08013d84 : + 8013d84: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8013d88: f8df 80c0 ldr.w r8, [pc, #192] ; 8013e4c + 8013d8c: 4b2a ldr r3, [pc, #168] ; (8013e38 ) + 8013d8e: 460a mov r2, r1 + 8013d90: ed2d 8b02 vpush {d8} + 8013d94: 4601 mov r1, r0 + 8013d96: f8d8 0000 ldr.w r0, [r8] + 8013d9a: f7ff f9fd bl 8013198 <_strtod_l> + 8013d9e: ec55 4b10 vmov r4, r5, d0 + 8013da2: ee10 2a10 vmov r2, s0 + 8013da6: ee10 0a10 vmov r0, s0 + 8013daa: 462b mov r3, r5 + 8013dac: 4629 mov r1, r5 + 8013dae: f7ec febd bl 8000b2c <__aeabi_dcmpun> + 8013db2: b190 cbz r0, 8013dda + 8013db4: 2d00 cmp r5, #0 + 8013db6: 4821 ldr r0, [pc, #132] ; (8013e3c ) + 8013db8: da09 bge.n 8013dce + 8013dba: f001 f9d9 bl 8015170 + 8013dbe: eeb1 8a40 vneg.f32 s16, s0 + 8013dc2: eeb0 0a48 vmov.f32 s0, s16 + 8013dc6: ecbd 8b02 vpop {d8} + 8013dca: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8013dce: ecbd 8b02 vpop {d8} + 8013dd2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8013dd6: f001 b9cb b.w 8015170 + 8013dda: 4620 mov r0, r4 + 8013ddc: 4629 mov r1, r5 + 8013dde: f7ec ff03 bl 8000be8 <__aeabi_d2f> + 8013de2: ee08 0a10 vmov s16, r0 + 8013de6: eddf 7a16 vldr s15, [pc, #88] ; 8013e40 + 8013dea: eeb0 7ac8 vabs.f32 s14, s16 + 8013dee: eeb4 7a67 vcmp.f32 s14, s15 + 8013df2: eef1 fa10 vmrs APSR_nzcv, fpscr + 8013df6: dd11 ble.n 8013e1c + 8013df8: f025 4700 bic.w r7, r5, #2147483648 ; 0x80000000 + 8013dfc: 4b11 ldr r3, [pc, #68] ; (8013e44 ) + 8013dfe: f04f 32ff mov.w r2, #4294967295 + 8013e02: 4620 mov r0, r4 + 8013e04: 4639 mov r1, r7 + 8013e06: f7ec fe91 bl 8000b2c <__aeabi_dcmpun> + 8013e0a: b980 cbnz r0, 8013e2e + 8013e0c: 4b0d ldr r3, [pc, #52] ; (8013e44 ) + 8013e0e: f04f 32ff mov.w r2, #4294967295 + 8013e12: 4620 mov r0, r4 + 8013e14: 4639 mov r1, r7 + 8013e16: f7ec fe6b bl 8000af0 <__aeabi_dcmple> + 8013e1a: b940 cbnz r0, 8013e2e + 8013e1c: ee18 3a10 vmov r3, s16 + 8013e20: f013 4fff tst.w r3, #2139095040 ; 0x7f800000 + 8013e24: d1cd bne.n 8013dc2 + 8013e26: 4b08 ldr r3, [pc, #32] ; (8013e48 ) + 8013e28: 402b ands r3, r5 + 8013e2a: 2b00 cmp r3, #0 + 8013e2c: d0c9 beq.n 8013dc2 + 8013e2e: f8d8 3000 ldr.w r3, [r8] + 8013e32: 2222 movs r2, #34 ; 0x22 + 8013e34: 601a str r2, [r3, #0] + 8013e36: e7c4 b.n 8013dc2 + 8013e38: 20000138 .word 0x20000138 + 8013e3c: 0801ae2e .word 0x0801ae2e + 8013e40: 7f7fffff .word 0x7f7fffff + 8013e44: 7fefffff .word 0x7fefffff + 8013e48: 7ff00000 .word 0x7ff00000 + 8013e4c: 200002f0 .word 0x200002f0 + +08013e50 <_strtol_l.constprop.0>: + 8013e50: 2b01 cmp r3, #1 + 8013e52: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8013e56: d001 beq.n 8013e5c <_strtol_l.constprop.0+0xc> + 8013e58: 2b24 cmp r3, #36 ; 0x24 + 8013e5a: d906 bls.n 8013e6a <_strtol_l.constprop.0+0x1a> + 8013e5c: f001 f93c bl 80150d8 <__errno> + 8013e60: 2316 movs r3, #22 + 8013e62: 6003 str r3, [r0, #0] + 8013e64: 2000 movs r0, #0 + 8013e66: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8013e6a: f8df c0e4 ldr.w ip, [pc, #228] ; 8013f50 <_strtol_l.constprop.0+0x100> + 8013e6e: 460d mov r5, r1 + 8013e70: 462e mov r6, r5 + 8013e72: f815 4b01 ldrb.w r4, [r5], #1 + 8013e76: f81c 7004 ldrb.w r7, [ip, r4] + 8013e7a: f017 0708 ands.w r7, r7, #8 + 8013e7e: d1f7 bne.n 8013e70 <_strtol_l.constprop.0+0x20> + 8013e80: 2c2d cmp r4, #45 ; 0x2d + 8013e82: d132 bne.n 8013eea <_strtol_l.constprop.0+0x9a> + 8013e84: 782c ldrb r4, [r5, #0] + 8013e86: 2701 movs r7, #1 + 8013e88: 1cb5 adds r5, r6, #2 + 8013e8a: 2b00 cmp r3, #0 + 8013e8c: d05b beq.n 8013f46 <_strtol_l.constprop.0+0xf6> + 8013e8e: 2b10 cmp r3, #16 + 8013e90: d109 bne.n 8013ea6 <_strtol_l.constprop.0+0x56> + 8013e92: 2c30 cmp r4, #48 ; 0x30 + 8013e94: d107 bne.n 8013ea6 <_strtol_l.constprop.0+0x56> + 8013e96: 782c ldrb r4, [r5, #0] + 8013e98: f004 04df and.w r4, r4, #223 ; 0xdf + 8013e9c: 2c58 cmp r4, #88 ; 0x58 + 8013e9e: d14d bne.n 8013f3c <_strtol_l.constprop.0+0xec> + 8013ea0: 786c ldrb r4, [r5, #1] + 8013ea2: 2310 movs r3, #16 + 8013ea4: 3502 adds r5, #2 + 8013ea6: f107 4800 add.w r8, r7, #2147483648 ; 0x80000000 + 8013eaa: f108 38ff add.w r8, r8, #4294967295 + 8013eae: f04f 0e00 mov.w lr, #0 + 8013eb2: fbb8 f9f3 udiv r9, r8, r3 + 8013eb6: 4676 mov r6, lr + 8013eb8: fb03 8a19 mls sl, r3, r9, r8 + 8013ebc: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 + 8013ec0: f1bc 0f09 cmp.w ip, #9 + 8013ec4: d816 bhi.n 8013ef4 <_strtol_l.constprop.0+0xa4> + 8013ec6: 4664 mov r4, ip + 8013ec8: 42a3 cmp r3, r4 + 8013eca: dd24 ble.n 8013f16 <_strtol_l.constprop.0+0xc6> + 8013ecc: f1be 3fff cmp.w lr, #4294967295 + 8013ed0: d008 beq.n 8013ee4 <_strtol_l.constprop.0+0x94> + 8013ed2: 45b1 cmp r9, r6 + 8013ed4: d31c bcc.n 8013f10 <_strtol_l.constprop.0+0xc0> + 8013ed6: d101 bne.n 8013edc <_strtol_l.constprop.0+0x8c> + 8013ed8: 45a2 cmp sl, r4 + 8013eda: db19 blt.n 8013f10 <_strtol_l.constprop.0+0xc0> + 8013edc: fb06 4603 mla r6, r6, r3, r4 + 8013ee0: f04f 0e01 mov.w lr, #1 + 8013ee4: f815 4b01 ldrb.w r4, [r5], #1 + 8013ee8: e7e8 b.n 8013ebc <_strtol_l.constprop.0+0x6c> + 8013eea: 2c2b cmp r4, #43 ; 0x2b + 8013eec: bf04 itt eq + 8013eee: 782c ldrbeq r4, [r5, #0] + 8013ef0: 1cb5 addeq r5, r6, #2 + 8013ef2: e7ca b.n 8013e8a <_strtol_l.constprop.0+0x3a> + 8013ef4: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 + 8013ef8: f1bc 0f19 cmp.w ip, #25 + 8013efc: d801 bhi.n 8013f02 <_strtol_l.constprop.0+0xb2> + 8013efe: 3c37 subs r4, #55 ; 0x37 + 8013f00: e7e2 b.n 8013ec8 <_strtol_l.constprop.0+0x78> + 8013f02: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 + 8013f06: f1bc 0f19 cmp.w ip, #25 + 8013f0a: d804 bhi.n 8013f16 <_strtol_l.constprop.0+0xc6> + 8013f0c: 3c57 subs r4, #87 ; 0x57 + 8013f0e: e7db b.n 8013ec8 <_strtol_l.constprop.0+0x78> + 8013f10: f04f 3eff mov.w lr, #4294967295 + 8013f14: e7e6 b.n 8013ee4 <_strtol_l.constprop.0+0x94> + 8013f16: f1be 3fff cmp.w lr, #4294967295 + 8013f1a: d105 bne.n 8013f28 <_strtol_l.constprop.0+0xd8> + 8013f1c: 2322 movs r3, #34 ; 0x22 + 8013f1e: 6003 str r3, [r0, #0] + 8013f20: 4646 mov r6, r8 + 8013f22: b942 cbnz r2, 8013f36 <_strtol_l.constprop.0+0xe6> + 8013f24: 4630 mov r0, r6 + 8013f26: e79e b.n 8013e66 <_strtol_l.constprop.0+0x16> + 8013f28: b107 cbz r7, 8013f2c <_strtol_l.constprop.0+0xdc> + 8013f2a: 4276 negs r6, r6 + 8013f2c: 2a00 cmp r2, #0 + 8013f2e: d0f9 beq.n 8013f24 <_strtol_l.constprop.0+0xd4> + 8013f30: f1be 0f00 cmp.w lr, #0 + 8013f34: d000 beq.n 8013f38 <_strtol_l.constprop.0+0xe8> + 8013f36: 1e69 subs r1, r5, #1 + 8013f38: 6011 str r1, [r2, #0] + 8013f3a: e7f3 b.n 8013f24 <_strtol_l.constprop.0+0xd4> + 8013f3c: 2430 movs r4, #48 ; 0x30 + 8013f3e: 2b00 cmp r3, #0 + 8013f40: d1b1 bne.n 8013ea6 <_strtol_l.constprop.0+0x56> + 8013f42: 2308 movs r3, #8 + 8013f44: e7af b.n 8013ea6 <_strtol_l.constprop.0+0x56> + 8013f46: 2c30 cmp r4, #48 ; 0x30 + 8013f48: d0a5 beq.n 8013e96 <_strtol_l.constprop.0+0x46> + 8013f4a: 230a movs r3, #10 + 8013f4c: e7ab b.n 8013ea6 <_strtol_l.constprop.0+0x56> + 8013f4e: bf00 nop + 8013f50: 0801ac41 .word 0x0801ac41 + +08013f54 <_strtol_r>: + 8013f54: f7ff bf7c b.w 8013e50 <_strtol_l.constprop.0> + +08013f58 : + 8013f58: 4613 mov r3, r2 + 8013f5a: 460a mov r2, r1 + 8013f5c: 4601 mov r1, r0 + 8013f5e: 4802 ldr r0, [pc, #8] ; (8013f68 ) + 8013f60: 6800 ldr r0, [r0, #0] + 8013f62: f7ff bf75 b.w 8013e50 <_strtol_l.constprop.0> + 8013f66: bf00 nop + 8013f68: 200002f0 .word 0x200002f0 + +08013f6c <__cvt>: + 8013f6c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8013f70: ec55 4b10 vmov r4, r5, d0 + 8013f74: 2d00 cmp r5, #0 + 8013f76: 460e mov r6, r1 + 8013f78: 4619 mov r1, r3 + 8013f7a: 462b mov r3, r5 + 8013f7c: bfbb ittet lt + 8013f7e: f105 4300 addlt.w r3, r5, #2147483648 ; 0x80000000 + 8013f82: 461d movlt r5, r3 + 8013f84: 2300 movge r3, #0 + 8013f86: 232d movlt r3, #45 ; 0x2d + 8013f88: 700b strb r3, [r1, #0] + 8013f8a: 9b0d ldr r3, [sp, #52] ; 0x34 + 8013f8c: f8dd a030 ldr.w sl, [sp, #48] ; 0x30 + 8013f90: 4691 mov r9, r2 + 8013f92: f023 0820 bic.w r8, r3, #32 + 8013f96: bfbc itt lt + 8013f98: 4622 movlt r2, r4 + 8013f9a: 4614 movlt r4, r2 + 8013f9c: f1b8 0f46 cmp.w r8, #70 ; 0x46 + 8013fa0: d005 beq.n 8013fae <__cvt+0x42> + 8013fa2: f1b8 0f45 cmp.w r8, #69 ; 0x45 + 8013fa6: d100 bne.n 8013faa <__cvt+0x3e> + 8013fa8: 3601 adds r6, #1 + 8013faa: 2102 movs r1, #2 + 8013fac: e000 b.n 8013fb0 <__cvt+0x44> + 8013fae: 2103 movs r1, #3 + 8013fb0: ab03 add r3, sp, #12 + 8013fb2: 9301 str r3, [sp, #4] + 8013fb4: ab02 add r3, sp, #8 + 8013fb6: 9300 str r3, [sp, #0] + 8013fb8: ec45 4b10 vmov d0, r4, r5 + 8013fbc: 4653 mov r3, sl + 8013fbe: 4632 mov r2, r6 + 8013fc0: f001 f982 bl 80152c8 <_dtoa_r> + 8013fc4: f1b8 0f47 cmp.w r8, #71 ; 0x47 + 8013fc8: 4607 mov r7, r0 + 8013fca: d102 bne.n 8013fd2 <__cvt+0x66> + 8013fcc: f019 0f01 tst.w r9, #1 + 8013fd0: d022 beq.n 8014018 <__cvt+0xac> + 8013fd2: f1b8 0f46 cmp.w r8, #70 ; 0x46 + 8013fd6: eb07 0906 add.w r9, r7, r6 + 8013fda: d110 bne.n 8013ffe <__cvt+0x92> + 8013fdc: 783b ldrb r3, [r7, #0] + 8013fde: 2b30 cmp r3, #48 ; 0x30 + 8013fe0: d10a bne.n 8013ff8 <__cvt+0x8c> + 8013fe2: 2200 movs r2, #0 + 8013fe4: 2300 movs r3, #0 + 8013fe6: 4620 mov r0, r4 + 8013fe8: 4629 mov r1, r5 + 8013fea: f7ec fd6d bl 8000ac8 <__aeabi_dcmpeq> + 8013fee: b918 cbnz r0, 8013ff8 <__cvt+0x8c> + 8013ff0: f1c6 0601 rsb r6, r6, #1 + 8013ff4: f8ca 6000 str.w r6, [sl] + 8013ff8: f8da 3000 ldr.w r3, [sl] + 8013ffc: 4499 add r9, r3 + 8013ffe: 2200 movs r2, #0 + 8014000: 2300 movs r3, #0 + 8014002: 4620 mov r0, r4 + 8014004: 4629 mov r1, r5 + 8014006: f7ec fd5f bl 8000ac8 <__aeabi_dcmpeq> + 801400a: b108 cbz r0, 8014010 <__cvt+0xa4> + 801400c: f8cd 900c str.w r9, [sp, #12] + 8014010: 2230 movs r2, #48 ; 0x30 + 8014012: 9b03 ldr r3, [sp, #12] + 8014014: 454b cmp r3, r9 + 8014016: d307 bcc.n 8014028 <__cvt+0xbc> + 8014018: 9b03 ldr r3, [sp, #12] + 801401a: 9a0e ldr r2, [sp, #56] ; 0x38 + 801401c: 1bdb subs r3, r3, r7 + 801401e: 4638 mov r0, r7 + 8014020: 6013 str r3, [r2, #0] + 8014022: b004 add sp, #16 + 8014024: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8014028: 1c59 adds r1, r3, #1 + 801402a: 9103 str r1, [sp, #12] + 801402c: 701a strb r2, [r3, #0] + 801402e: e7f0 b.n 8014012 <__cvt+0xa6> + +08014030 <__exponent>: + 8014030: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8014032: 4603 mov r3, r0 + 8014034: 2900 cmp r1, #0 + 8014036: bfb8 it lt + 8014038: 4249 neglt r1, r1 + 801403a: f803 2b02 strb.w r2, [r3], #2 + 801403e: bfb4 ite lt + 8014040: 222d movlt r2, #45 ; 0x2d + 8014042: 222b movge r2, #43 ; 0x2b + 8014044: 2909 cmp r1, #9 + 8014046: 7042 strb r2, [r0, #1] + 8014048: dd2a ble.n 80140a0 <__exponent+0x70> + 801404a: f10d 0207 add.w r2, sp, #7 + 801404e: 4617 mov r7, r2 + 8014050: 260a movs r6, #10 + 8014052: 4694 mov ip, r2 + 8014054: fb91 f5f6 sdiv r5, r1, r6 + 8014058: fb06 1415 mls r4, r6, r5, r1 + 801405c: 3430 adds r4, #48 ; 0x30 + 801405e: f80c 4c01 strb.w r4, [ip, #-1] + 8014062: 460c mov r4, r1 + 8014064: 2c63 cmp r4, #99 ; 0x63 + 8014066: f102 32ff add.w r2, r2, #4294967295 + 801406a: 4629 mov r1, r5 + 801406c: dcf1 bgt.n 8014052 <__exponent+0x22> + 801406e: 3130 adds r1, #48 ; 0x30 + 8014070: f1ac 0402 sub.w r4, ip, #2 + 8014074: f802 1c01 strb.w r1, [r2, #-1] + 8014078: 1c41 adds r1, r0, #1 + 801407a: 4622 mov r2, r4 + 801407c: 42ba cmp r2, r7 + 801407e: d30a bcc.n 8014096 <__exponent+0x66> + 8014080: f10d 0209 add.w r2, sp, #9 + 8014084: eba2 020c sub.w r2, r2, ip + 8014088: 42bc cmp r4, r7 + 801408a: bf88 it hi + 801408c: 2200 movhi r2, #0 + 801408e: 4413 add r3, r2 + 8014090: 1a18 subs r0, r3, r0 + 8014092: b003 add sp, #12 + 8014094: bdf0 pop {r4, r5, r6, r7, pc} + 8014096: f812 5b01 ldrb.w r5, [r2], #1 + 801409a: f801 5f01 strb.w r5, [r1, #1]! + 801409e: e7ed b.n 801407c <__exponent+0x4c> + 80140a0: 2330 movs r3, #48 ; 0x30 + 80140a2: 3130 adds r1, #48 ; 0x30 + 80140a4: 7083 strb r3, [r0, #2] + 80140a6: 70c1 strb r1, [r0, #3] + 80140a8: 1d03 adds r3, r0, #4 + 80140aa: e7f1 b.n 8014090 <__exponent+0x60> + +080140ac <_printf_float>: + 80140ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80140b0: ed2d 8b02 vpush {d8} + 80140b4: b08d sub sp, #52 ; 0x34 + 80140b6: 460c mov r4, r1 + 80140b8: f8dd 8060 ldr.w r8, [sp, #96] ; 0x60 + 80140bc: 4616 mov r6, r2 + 80140be: 461f mov r7, r3 + 80140c0: 4605 mov r5, r0 + 80140c2: f000 ffaf bl 8015024 <_localeconv_r> + 80140c6: f8d0 a000 ldr.w sl, [r0] + 80140ca: 4650 mov r0, sl + 80140cc: f7ec f8d0 bl 8000270 + 80140d0: 2300 movs r3, #0 + 80140d2: 930a str r3, [sp, #40] ; 0x28 + 80140d4: 6823 ldr r3, [r4, #0] + 80140d6: 9305 str r3, [sp, #20] + 80140d8: f8d8 3000 ldr.w r3, [r8] + 80140dc: f894 b018 ldrb.w fp, [r4, #24] + 80140e0: 3307 adds r3, #7 + 80140e2: f023 0307 bic.w r3, r3, #7 + 80140e6: f103 0208 add.w r2, r3, #8 + 80140ea: f8c8 2000 str.w r2, [r8] + 80140ee: e9d3 8900 ldrd r8, r9, [r3] + 80140f2: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 + 80140f6: 9307 str r3, [sp, #28] + 80140f8: f8cd 8018 str.w r8, [sp, #24] + 80140fc: ee08 0a10 vmov s16, r0 + 8014100: e9c4 8912 strd r8, r9, [r4, #72] ; 0x48 + 8014104: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014108: 4b9e ldr r3, [pc, #632] ; (8014384 <_printf_float+0x2d8>) + 801410a: f04f 32ff mov.w r2, #4294967295 + 801410e: f7ec fd0d bl 8000b2c <__aeabi_dcmpun> + 8014112: bb88 cbnz r0, 8014178 <_printf_float+0xcc> + 8014114: e9dd 0106 ldrd r0, r1, [sp, #24] + 8014118: 4b9a ldr r3, [pc, #616] ; (8014384 <_printf_float+0x2d8>) + 801411a: f04f 32ff mov.w r2, #4294967295 + 801411e: f7ec fce7 bl 8000af0 <__aeabi_dcmple> + 8014122: bb48 cbnz r0, 8014178 <_printf_float+0xcc> + 8014124: 2200 movs r2, #0 + 8014126: 2300 movs r3, #0 + 8014128: 4640 mov r0, r8 + 801412a: 4649 mov r1, r9 + 801412c: f7ec fcd6 bl 8000adc <__aeabi_dcmplt> + 8014130: b110 cbz r0, 8014138 <_printf_float+0x8c> + 8014132: 232d movs r3, #45 ; 0x2d + 8014134: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8014138: 4a93 ldr r2, [pc, #588] ; (8014388 <_printf_float+0x2dc>) + 801413a: 4b94 ldr r3, [pc, #592] ; (801438c <_printf_float+0x2e0>) + 801413c: f1bb 0f47 cmp.w fp, #71 ; 0x47 + 8014140: bf94 ite ls + 8014142: 4690 movls r8, r2 + 8014144: 4698 movhi r8, r3 + 8014146: 2303 movs r3, #3 + 8014148: 6123 str r3, [r4, #16] + 801414a: 9b05 ldr r3, [sp, #20] + 801414c: f023 0304 bic.w r3, r3, #4 + 8014150: 6023 str r3, [r4, #0] + 8014152: f04f 0900 mov.w r9, #0 + 8014156: 9700 str r7, [sp, #0] + 8014158: 4633 mov r3, r6 + 801415a: aa0b add r2, sp, #44 ; 0x2c + 801415c: 4621 mov r1, r4 + 801415e: 4628 mov r0, r5 + 8014160: f000 f9da bl 8014518 <_printf_common> + 8014164: 3001 adds r0, #1 + 8014166: f040 8090 bne.w 801428a <_printf_float+0x1de> + 801416a: f04f 30ff mov.w r0, #4294967295 + 801416e: b00d add sp, #52 ; 0x34 + 8014170: ecbd 8b02 vpop {d8} + 8014174: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8014178: 4642 mov r2, r8 + 801417a: 464b mov r3, r9 + 801417c: 4640 mov r0, r8 + 801417e: 4649 mov r1, r9 + 8014180: f7ec fcd4 bl 8000b2c <__aeabi_dcmpun> + 8014184: b140 cbz r0, 8014198 <_printf_float+0xec> + 8014186: 464b mov r3, r9 + 8014188: 2b00 cmp r3, #0 + 801418a: bfbc itt lt + 801418c: 232d movlt r3, #45 ; 0x2d + 801418e: f884 3043 strblt.w r3, [r4, #67] ; 0x43 + 8014192: 4a7f ldr r2, [pc, #508] ; (8014390 <_printf_float+0x2e4>) + 8014194: 4b7f ldr r3, [pc, #508] ; (8014394 <_printf_float+0x2e8>) + 8014196: e7d1 b.n 801413c <_printf_float+0x90> + 8014198: 6863 ldr r3, [r4, #4] + 801419a: f00b 02df and.w r2, fp, #223 ; 0xdf + 801419e: 9206 str r2, [sp, #24] + 80141a0: 1c5a adds r2, r3, #1 + 80141a2: d13f bne.n 8014224 <_printf_float+0x178> + 80141a4: 2306 movs r3, #6 + 80141a6: 6063 str r3, [r4, #4] + 80141a8: 9b05 ldr r3, [sp, #20] + 80141aa: 6861 ldr r1, [r4, #4] + 80141ac: f443 6280 orr.w r2, r3, #1024 ; 0x400 + 80141b0: 2300 movs r3, #0 + 80141b2: 9303 str r3, [sp, #12] + 80141b4: ab0a add r3, sp, #40 ; 0x28 + 80141b6: e9cd b301 strd fp, r3, [sp, #4] + 80141ba: ab09 add r3, sp, #36 ; 0x24 + 80141bc: ec49 8b10 vmov d0, r8, r9 + 80141c0: 9300 str r3, [sp, #0] + 80141c2: 6022 str r2, [r4, #0] + 80141c4: f10d 0323 add.w r3, sp, #35 ; 0x23 + 80141c8: 4628 mov r0, r5 + 80141ca: f7ff fecf bl 8013f6c <__cvt> + 80141ce: 9b06 ldr r3, [sp, #24] + 80141d0: 9909 ldr r1, [sp, #36] ; 0x24 + 80141d2: 2b47 cmp r3, #71 ; 0x47 + 80141d4: 4680 mov r8, r0 + 80141d6: d108 bne.n 80141ea <_printf_float+0x13e> + 80141d8: 1cc8 adds r0, r1, #3 + 80141da: db02 blt.n 80141e2 <_printf_float+0x136> + 80141dc: 6863 ldr r3, [r4, #4] + 80141de: 4299 cmp r1, r3 + 80141e0: dd41 ble.n 8014266 <_printf_float+0x1ba> + 80141e2: f1ab 0302 sub.w r3, fp, #2 + 80141e6: fa5f fb83 uxtb.w fp, r3 + 80141ea: f1bb 0f65 cmp.w fp, #101 ; 0x65 + 80141ee: d820 bhi.n 8014232 <_printf_float+0x186> + 80141f0: 3901 subs r1, #1 + 80141f2: 465a mov r2, fp + 80141f4: f104 0050 add.w r0, r4, #80 ; 0x50 + 80141f8: 9109 str r1, [sp, #36] ; 0x24 + 80141fa: f7ff ff19 bl 8014030 <__exponent> + 80141fe: 9a0a ldr r2, [sp, #40] ; 0x28 + 8014200: 1813 adds r3, r2, r0 + 8014202: 2a01 cmp r2, #1 + 8014204: 4681 mov r9, r0 + 8014206: 6123 str r3, [r4, #16] + 8014208: dc02 bgt.n 8014210 <_printf_float+0x164> + 801420a: 6822 ldr r2, [r4, #0] + 801420c: 07d2 lsls r2, r2, #31 + 801420e: d501 bpl.n 8014214 <_printf_float+0x168> + 8014210: 3301 adds r3, #1 + 8014212: 6123 str r3, [r4, #16] + 8014214: f89d 3023 ldrb.w r3, [sp, #35] ; 0x23 + 8014218: 2b00 cmp r3, #0 + 801421a: d09c beq.n 8014156 <_printf_float+0xaa> + 801421c: 232d movs r3, #45 ; 0x2d + 801421e: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8014222: e798 b.n 8014156 <_printf_float+0xaa> + 8014224: 9a06 ldr r2, [sp, #24] + 8014226: 2a47 cmp r2, #71 ; 0x47 + 8014228: d1be bne.n 80141a8 <_printf_float+0xfc> + 801422a: 2b00 cmp r3, #0 + 801422c: d1bc bne.n 80141a8 <_printf_float+0xfc> + 801422e: 2301 movs r3, #1 + 8014230: e7b9 b.n 80141a6 <_printf_float+0xfa> + 8014232: f1bb 0f66 cmp.w fp, #102 ; 0x66 + 8014236: d118 bne.n 801426a <_printf_float+0x1be> + 8014238: 2900 cmp r1, #0 + 801423a: 6863 ldr r3, [r4, #4] + 801423c: dd0b ble.n 8014256 <_printf_float+0x1aa> + 801423e: 6121 str r1, [r4, #16] + 8014240: b913 cbnz r3, 8014248 <_printf_float+0x19c> + 8014242: 6822 ldr r2, [r4, #0] + 8014244: 07d0 lsls r0, r2, #31 + 8014246: d502 bpl.n 801424e <_printf_float+0x1a2> + 8014248: 3301 adds r3, #1 + 801424a: 440b add r3, r1 + 801424c: 6123 str r3, [r4, #16] + 801424e: 65a1 str r1, [r4, #88] ; 0x58 + 8014250: f04f 0900 mov.w r9, #0 + 8014254: e7de b.n 8014214 <_printf_float+0x168> + 8014256: b913 cbnz r3, 801425e <_printf_float+0x1b2> + 8014258: 6822 ldr r2, [r4, #0] + 801425a: 07d2 lsls r2, r2, #31 + 801425c: d501 bpl.n 8014262 <_printf_float+0x1b6> + 801425e: 3302 adds r3, #2 + 8014260: e7f4 b.n 801424c <_printf_float+0x1a0> + 8014262: 2301 movs r3, #1 + 8014264: e7f2 b.n 801424c <_printf_float+0x1a0> + 8014266: f04f 0b67 mov.w fp, #103 ; 0x67 + 801426a: 9b0a ldr r3, [sp, #40] ; 0x28 + 801426c: 4299 cmp r1, r3 + 801426e: db05 blt.n 801427c <_printf_float+0x1d0> + 8014270: 6823 ldr r3, [r4, #0] + 8014272: 6121 str r1, [r4, #16] + 8014274: 07d8 lsls r0, r3, #31 + 8014276: d5ea bpl.n 801424e <_printf_float+0x1a2> + 8014278: 1c4b adds r3, r1, #1 + 801427a: e7e7 b.n 801424c <_printf_float+0x1a0> + 801427c: 2900 cmp r1, #0 + 801427e: bfd4 ite le + 8014280: f1c1 0202 rsble r2, r1, #2 + 8014284: 2201 movgt r2, #1 + 8014286: 4413 add r3, r2 + 8014288: e7e0 b.n 801424c <_printf_float+0x1a0> + 801428a: 6823 ldr r3, [r4, #0] + 801428c: 055a lsls r2, r3, #21 + 801428e: d407 bmi.n 80142a0 <_printf_float+0x1f4> + 8014290: 6923 ldr r3, [r4, #16] + 8014292: 4642 mov r2, r8 + 8014294: 4631 mov r1, r6 + 8014296: 4628 mov r0, r5 + 8014298: 47b8 blx r7 + 801429a: 3001 adds r0, #1 + 801429c: d12c bne.n 80142f8 <_printf_float+0x24c> + 801429e: e764 b.n 801416a <_printf_float+0xbe> + 80142a0: f1bb 0f65 cmp.w fp, #101 ; 0x65 + 80142a4: f240 80e0 bls.w 8014468 <_printf_float+0x3bc> + 80142a8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 80142ac: 2200 movs r2, #0 + 80142ae: 2300 movs r3, #0 + 80142b0: f7ec fc0a bl 8000ac8 <__aeabi_dcmpeq> + 80142b4: 2800 cmp r0, #0 + 80142b6: d034 beq.n 8014322 <_printf_float+0x276> + 80142b8: 4a37 ldr r2, [pc, #220] ; (8014398 <_printf_float+0x2ec>) + 80142ba: 2301 movs r3, #1 + 80142bc: 4631 mov r1, r6 + 80142be: 4628 mov r0, r5 + 80142c0: 47b8 blx r7 + 80142c2: 3001 adds r0, #1 + 80142c4: f43f af51 beq.w 801416a <_printf_float+0xbe> + 80142c8: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 80142cc: 429a cmp r2, r3 + 80142ce: db02 blt.n 80142d6 <_printf_float+0x22a> + 80142d0: 6823 ldr r3, [r4, #0] + 80142d2: 07d8 lsls r0, r3, #31 + 80142d4: d510 bpl.n 80142f8 <_printf_float+0x24c> + 80142d6: ee18 3a10 vmov r3, s16 + 80142da: 4652 mov r2, sl + 80142dc: 4631 mov r1, r6 + 80142de: 4628 mov r0, r5 + 80142e0: 47b8 blx r7 + 80142e2: 3001 adds r0, #1 + 80142e4: f43f af41 beq.w 801416a <_printf_float+0xbe> + 80142e8: f04f 0800 mov.w r8, #0 + 80142ec: f104 091a add.w r9, r4, #26 + 80142f0: 9b0a ldr r3, [sp, #40] ; 0x28 + 80142f2: 3b01 subs r3, #1 + 80142f4: 4543 cmp r3, r8 + 80142f6: dc09 bgt.n 801430c <_printf_float+0x260> + 80142f8: 6823 ldr r3, [r4, #0] + 80142fa: 079b lsls r3, r3, #30 + 80142fc: f100 8107 bmi.w 801450e <_printf_float+0x462> + 8014300: 68e0 ldr r0, [r4, #12] + 8014302: 9b0b ldr r3, [sp, #44] ; 0x2c + 8014304: 4298 cmp r0, r3 + 8014306: bfb8 it lt + 8014308: 4618 movlt r0, r3 + 801430a: e730 b.n 801416e <_printf_float+0xc2> + 801430c: 2301 movs r3, #1 + 801430e: 464a mov r2, r9 + 8014310: 4631 mov r1, r6 + 8014312: 4628 mov r0, r5 + 8014314: 47b8 blx r7 + 8014316: 3001 adds r0, #1 + 8014318: f43f af27 beq.w 801416a <_printf_float+0xbe> + 801431c: f108 0801 add.w r8, r8, #1 + 8014320: e7e6 b.n 80142f0 <_printf_float+0x244> + 8014322: 9b09 ldr r3, [sp, #36] ; 0x24 + 8014324: 2b00 cmp r3, #0 + 8014326: dc39 bgt.n 801439c <_printf_float+0x2f0> + 8014328: 4a1b ldr r2, [pc, #108] ; (8014398 <_printf_float+0x2ec>) + 801432a: 2301 movs r3, #1 + 801432c: 4631 mov r1, r6 + 801432e: 4628 mov r0, r5 + 8014330: 47b8 blx r7 + 8014332: 3001 adds r0, #1 + 8014334: f43f af19 beq.w 801416a <_printf_float+0xbe> + 8014338: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 + 801433c: 4313 orrs r3, r2 + 801433e: d102 bne.n 8014346 <_printf_float+0x29a> + 8014340: 6823 ldr r3, [r4, #0] + 8014342: 07d9 lsls r1, r3, #31 + 8014344: d5d8 bpl.n 80142f8 <_printf_float+0x24c> + 8014346: ee18 3a10 vmov r3, s16 + 801434a: 4652 mov r2, sl + 801434c: 4631 mov r1, r6 + 801434e: 4628 mov r0, r5 + 8014350: 47b8 blx r7 + 8014352: 3001 adds r0, #1 + 8014354: f43f af09 beq.w 801416a <_printf_float+0xbe> + 8014358: f04f 0900 mov.w r9, #0 + 801435c: f104 0a1a add.w sl, r4, #26 + 8014360: 9b09 ldr r3, [sp, #36] ; 0x24 + 8014362: 425b negs r3, r3 + 8014364: 454b cmp r3, r9 + 8014366: dc01 bgt.n 801436c <_printf_float+0x2c0> + 8014368: 9b0a ldr r3, [sp, #40] ; 0x28 + 801436a: e792 b.n 8014292 <_printf_float+0x1e6> + 801436c: 2301 movs r3, #1 + 801436e: 4652 mov r2, sl + 8014370: 4631 mov r1, r6 + 8014372: 4628 mov r0, r5 + 8014374: 47b8 blx r7 + 8014376: 3001 adds r0, #1 + 8014378: f43f aef7 beq.w 801416a <_printf_float+0xbe> + 801437c: f109 0901 add.w r9, r9, #1 + 8014380: e7ee b.n 8014360 <_printf_float+0x2b4> + 8014382: bf00 nop + 8014384: 7fefffff .word 0x7fefffff + 8014388: 0801ad41 .word 0x0801ad41 + 801438c: 0801ad45 .word 0x0801ad45 + 8014390: 0801ad49 .word 0x0801ad49 + 8014394: 0801ad4d .word 0x0801ad4d + 8014398: 0801ad51 .word 0x0801ad51 + 801439c: 9a0a ldr r2, [sp, #40] ; 0x28 + 801439e: 6da3 ldr r3, [r4, #88] ; 0x58 + 80143a0: 429a cmp r2, r3 + 80143a2: bfa8 it ge + 80143a4: 461a movge r2, r3 + 80143a6: 2a00 cmp r2, #0 + 80143a8: 4691 mov r9, r2 + 80143aa: dc37 bgt.n 801441c <_printf_float+0x370> + 80143ac: f04f 0b00 mov.w fp, #0 + 80143b0: ea29 79e9 bic.w r9, r9, r9, asr #31 + 80143b4: f104 021a add.w r2, r4, #26 + 80143b8: 6da3 ldr r3, [r4, #88] ; 0x58 + 80143ba: 9305 str r3, [sp, #20] + 80143bc: eba3 0309 sub.w r3, r3, r9 + 80143c0: 455b cmp r3, fp + 80143c2: dc33 bgt.n 801442c <_printf_float+0x380> + 80143c4: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 80143c8: 429a cmp r2, r3 + 80143ca: db3b blt.n 8014444 <_printf_float+0x398> + 80143cc: 6823 ldr r3, [r4, #0] + 80143ce: 07da lsls r2, r3, #31 + 80143d0: d438 bmi.n 8014444 <_printf_float+0x398> + 80143d2: e9dd 3209 ldrd r3, r2, [sp, #36] ; 0x24 + 80143d6: eba2 0903 sub.w r9, r2, r3 + 80143da: 9b05 ldr r3, [sp, #20] + 80143dc: 1ad2 subs r2, r2, r3 + 80143de: 4591 cmp r9, r2 + 80143e0: bfa8 it ge + 80143e2: 4691 movge r9, r2 + 80143e4: f1b9 0f00 cmp.w r9, #0 + 80143e8: dc35 bgt.n 8014456 <_printf_float+0x3aa> + 80143ea: f04f 0800 mov.w r8, #0 + 80143ee: ea29 79e9 bic.w r9, r9, r9, asr #31 + 80143f2: f104 0a1a add.w sl, r4, #26 + 80143f6: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 + 80143fa: 1a9b subs r3, r3, r2 + 80143fc: eba3 0309 sub.w r3, r3, r9 + 8014400: 4543 cmp r3, r8 + 8014402: f77f af79 ble.w 80142f8 <_printf_float+0x24c> + 8014406: 2301 movs r3, #1 + 8014408: 4652 mov r2, sl + 801440a: 4631 mov r1, r6 + 801440c: 4628 mov r0, r5 + 801440e: 47b8 blx r7 + 8014410: 3001 adds r0, #1 + 8014412: f43f aeaa beq.w 801416a <_printf_float+0xbe> + 8014416: f108 0801 add.w r8, r8, #1 + 801441a: e7ec b.n 80143f6 <_printf_float+0x34a> + 801441c: 4613 mov r3, r2 + 801441e: 4631 mov r1, r6 + 8014420: 4642 mov r2, r8 + 8014422: 4628 mov r0, r5 + 8014424: 47b8 blx r7 + 8014426: 3001 adds r0, #1 + 8014428: d1c0 bne.n 80143ac <_printf_float+0x300> + 801442a: e69e b.n 801416a <_printf_float+0xbe> + 801442c: 2301 movs r3, #1 + 801442e: 4631 mov r1, r6 + 8014430: 4628 mov r0, r5 + 8014432: 9205 str r2, [sp, #20] + 8014434: 47b8 blx r7 + 8014436: 3001 adds r0, #1 + 8014438: f43f ae97 beq.w 801416a <_printf_float+0xbe> + 801443c: 9a05 ldr r2, [sp, #20] + 801443e: f10b 0b01 add.w fp, fp, #1 + 8014442: e7b9 b.n 80143b8 <_printf_float+0x30c> + 8014444: ee18 3a10 vmov r3, s16 + 8014448: 4652 mov r2, sl + 801444a: 4631 mov r1, r6 + 801444c: 4628 mov r0, r5 + 801444e: 47b8 blx r7 + 8014450: 3001 adds r0, #1 + 8014452: d1be bne.n 80143d2 <_printf_float+0x326> + 8014454: e689 b.n 801416a <_printf_float+0xbe> + 8014456: 9a05 ldr r2, [sp, #20] + 8014458: 464b mov r3, r9 + 801445a: 4442 add r2, r8 + 801445c: 4631 mov r1, r6 + 801445e: 4628 mov r0, r5 + 8014460: 47b8 blx r7 + 8014462: 3001 adds r0, #1 + 8014464: d1c1 bne.n 80143ea <_printf_float+0x33e> + 8014466: e680 b.n 801416a <_printf_float+0xbe> + 8014468: 9a0a ldr r2, [sp, #40] ; 0x28 + 801446a: 2a01 cmp r2, #1 + 801446c: dc01 bgt.n 8014472 <_printf_float+0x3c6> + 801446e: 07db lsls r3, r3, #31 + 8014470: d53a bpl.n 80144e8 <_printf_float+0x43c> + 8014472: 2301 movs r3, #1 + 8014474: 4642 mov r2, r8 + 8014476: 4631 mov r1, r6 + 8014478: 4628 mov r0, r5 + 801447a: 47b8 blx r7 + 801447c: 3001 adds r0, #1 + 801447e: f43f ae74 beq.w 801416a <_printf_float+0xbe> + 8014482: ee18 3a10 vmov r3, s16 + 8014486: 4652 mov r2, sl + 8014488: 4631 mov r1, r6 + 801448a: 4628 mov r0, r5 + 801448c: 47b8 blx r7 + 801448e: 3001 adds r0, #1 + 8014490: f43f ae6b beq.w 801416a <_printf_float+0xbe> + 8014494: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 + 8014498: 2200 movs r2, #0 + 801449a: 2300 movs r3, #0 + 801449c: f8dd a028 ldr.w sl, [sp, #40] ; 0x28 + 80144a0: f7ec fb12 bl 8000ac8 <__aeabi_dcmpeq> + 80144a4: b9d8 cbnz r0, 80144de <_printf_float+0x432> + 80144a6: f10a 33ff add.w r3, sl, #4294967295 + 80144aa: f108 0201 add.w r2, r8, #1 + 80144ae: 4631 mov r1, r6 + 80144b0: 4628 mov r0, r5 + 80144b2: 47b8 blx r7 + 80144b4: 3001 adds r0, #1 + 80144b6: d10e bne.n 80144d6 <_printf_float+0x42a> + 80144b8: e657 b.n 801416a <_printf_float+0xbe> + 80144ba: 2301 movs r3, #1 + 80144bc: 4652 mov r2, sl + 80144be: 4631 mov r1, r6 + 80144c0: 4628 mov r0, r5 + 80144c2: 47b8 blx r7 + 80144c4: 3001 adds r0, #1 + 80144c6: f43f ae50 beq.w 801416a <_printf_float+0xbe> + 80144ca: f108 0801 add.w r8, r8, #1 + 80144ce: 9b0a ldr r3, [sp, #40] ; 0x28 + 80144d0: 3b01 subs r3, #1 + 80144d2: 4543 cmp r3, r8 + 80144d4: dcf1 bgt.n 80144ba <_printf_float+0x40e> + 80144d6: 464b mov r3, r9 + 80144d8: f104 0250 add.w r2, r4, #80 ; 0x50 + 80144dc: e6da b.n 8014294 <_printf_float+0x1e8> + 80144de: f04f 0800 mov.w r8, #0 + 80144e2: f104 0a1a add.w sl, r4, #26 + 80144e6: e7f2 b.n 80144ce <_printf_float+0x422> + 80144e8: 2301 movs r3, #1 + 80144ea: 4642 mov r2, r8 + 80144ec: e7df b.n 80144ae <_printf_float+0x402> + 80144ee: 2301 movs r3, #1 + 80144f0: 464a mov r2, r9 + 80144f2: 4631 mov r1, r6 + 80144f4: 4628 mov r0, r5 + 80144f6: 47b8 blx r7 + 80144f8: 3001 adds r0, #1 + 80144fa: f43f ae36 beq.w 801416a <_printf_float+0xbe> + 80144fe: f108 0801 add.w r8, r8, #1 + 8014502: 68e3 ldr r3, [r4, #12] + 8014504: 990b ldr r1, [sp, #44] ; 0x2c + 8014506: 1a5b subs r3, r3, r1 + 8014508: 4543 cmp r3, r8 + 801450a: dcf0 bgt.n 80144ee <_printf_float+0x442> + 801450c: e6f8 b.n 8014300 <_printf_float+0x254> + 801450e: f04f 0800 mov.w r8, #0 + 8014512: f104 0919 add.w r9, r4, #25 + 8014516: e7f4 b.n 8014502 <_printf_float+0x456> + +08014518 <_printf_common>: + 8014518: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 801451c: 4616 mov r6, r2 + 801451e: 4699 mov r9, r3 + 8014520: 688a ldr r2, [r1, #8] + 8014522: 690b ldr r3, [r1, #16] + 8014524: f8dd 8020 ldr.w r8, [sp, #32] + 8014528: 4293 cmp r3, r2 + 801452a: bfb8 it lt + 801452c: 4613 movlt r3, r2 + 801452e: 6033 str r3, [r6, #0] + 8014530: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 8014534: 4607 mov r7, r0 + 8014536: 460c mov r4, r1 + 8014538: b10a cbz r2, 801453e <_printf_common+0x26> + 801453a: 3301 adds r3, #1 + 801453c: 6033 str r3, [r6, #0] + 801453e: 6823 ldr r3, [r4, #0] + 8014540: 0699 lsls r1, r3, #26 + 8014542: bf42 ittt mi + 8014544: 6833 ldrmi r3, [r6, #0] + 8014546: 3302 addmi r3, #2 + 8014548: 6033 strmi r3, [r6, #0] + 801454a: 6825 ldr r5, [r4, #0] + 801454c: f015 0506 ands.w r5, r5, #6 + 8014550: d106 bne.n 8014560 <_printf_common+0x48> + 8014552: f104 0a19 add.w sl, r4, #25 + 8014556: 68e3 ldr r3, [r4, #12] + 8014558: 6832 ldr r2, [r6, #0] + 801455a: 1a9b subs r3, r3, r2 + 801455c: 42ab cmp r3, r5 + 801455e: dc26 bgt.n 80145ae <_printf_common+0x96> + 8014560: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 8014564: 1e13 subs r3, r2, #0 + 8014566: 6822 ldr r2, [r4, #0] + 8014568: bf18 it ne + 801456a: 2301 movne r3, #1 + 801456c: 0692 lsls r2, r2, #26 + 801456e: d42b bmi.n 80145c8 <_printf_common+0xb0> + 8014570: f104 0243 add.w r2, r4, #67 ; 0x43 + 8014574: 4649 mov r1, r9 + 8014576: 4638 mov r0, r7 + 8014578: 47c0 blx r8 + 801457a: 3001 adds r0, #1 + 801457c: d01e beq.n 80145bc <_printf_common+0xa4> + 801457e: 6823 ldr r3, [r4, #0] + 8014580: 6922 ldr r2, [r4, #16] + 8014582: f003 0306 and.w r3, r3, #6 + 8014586: 2b04 cmp r3, #4 + 8014588: bf02 ittt eq + 801458a: 68e5 ldreq r5, [r4, #12] + 801458c: 6833 ldreq r3, [r6, #0] + 801458e: 1aed subeq r5, r5, r3 + 8014590: 68a3 ldr r3, [r4, #8] + 8014592: bf0c ite eq + 8014594: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8014598: 2500 movne r5, #0 + 801459a: 4293 cmp r3, r2 + 801459c: bfc4 itt gt + 801459e: 1a9b subgt r3, r3, r2 + 80145a0: 18ed addgt r5, r5, r3 + 80145a2: 2600 movs r6, #0 + 80145a4: 341a adds r4, #26 + 80145a6: 42b5 cmp r5, r6 + 80145a8: d11a bne.n 80145e0 <_printf_common+0xc8> + 80145aa: 2000 movs r0, #0 + 80145ac: e008 b.n 80145c0 <_printf_common+0xa8> + 80145ae: 2301 movs r3, #1 + 80145b0: 4652 mov r2, sl + 80145b2: 4649 mov r1, r9 + 80145b4: 4638 mov r0, r7 + 80145b6: 47c0 blx r8 + 80145b8: 3001 adds r0, #1 + 80145ba: d103 bne.n 80145c4 <_printf_common+0xac> + 80145bc: f04f 30ff mov.w r0, #4294967295 + 80145c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80145c4: 3501 adds r5, #1 + 80145c6: e7c6 b.n 8014556 <_printf_common+0x3e> + 80145c8: 18e1 adds r1, r4, r3 + 80145ca: 1c5a adds r2, r3, #1 + 80145cc: 2030 movs r0, #48 ; 0x30 + 80145ce: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 80145d2: 4422 add r2, r4 + 80145d4: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 80145d8: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 80145dc: 3302 adds r3, #2 + 80145de: e7c7 b.n 8014570 <_printf_common+0x58> + 80145e0: 2301 movs r3, #1 + 80145e2: 4622 mov r2, r4 + 80145e4: 4649 mov r1, r9 + 80145e6: 4638 mov r0, r7 + 80145e8: 47c0 blx r8 + 80145ea: 3001 adds r0, #1 + 80145ec: d0e6 beq.n 80145bc <_printf_common+0xa4> + 80145ee: 3601 adds r6, #1 + 80145f0: e7d9 b.n 80145a6 <_printf_common+0x8e> ... -08012144 <_printf_i>: - 8012144: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 8012148: 7e0f ldrb r7, [r1, #24] - 801214a: 9d0c ldr r5, [sp, #48] ; 0x30 - 801214c: 2f78 cmp r7, #120 ; 0x78 - 801214e: 4691 mov r9, r2 - 8012150: 4680 mov r8, r0 - 8012152: 460c mov r4, r1 - 8012154: 469a mov sl, r3 - 8012156: f101 0243 add.w r2, r1, #67 ; 0x43 - 801215a: d807 bhi.n 801216c <_printf_i+0x28> - 801215c: 2f62 cmp r7, #98 ; 0x62 - 801215e: d80a bhi.n 8012176 <_printf_i+0x32> - 8012160: 2f00 cmp r7, #0 - 8012162: f000 80d4 beq.w 801230e <_printf_i+0x1ca> - 8012166: 2f58 cmp r7, #88 ; 0x58 - 8012168: f000 80c0 beq.w 80122ec <_printf_i+0x1a8> - 801216c: f104 0542 add.w r5, r4, #66 ; 0x42 - 8012170: f884 7042 strb.w r7, [r4, #66] ; 0x42 - 8012174: e03a b.n 80121ec <_printf_i+0xa8> - 8012176: f1a7 0363 sub.w r3, r7, #99 ; 0x63 - 801217a: 2b15 cmp r3, #21 - 801217c: d8f6 bhi.n 801216c <_printf_i+0x28> - 801217e: a101 add r1, pc, #4 ; (adr r1, 8012184 <_printf_i+0x40>) - 8012180: f851 f023 ldr.w pc, [r1, r3, lsl #2] - 8012184: 080121dd .word 0x080121dd - 8012188: 080121f1 .word 0x080121f1 - 801218c: 0801216d .word 0x0801216d - 8012190: 0801216d .word 0x0801216d - 8012194: 0801216d .word 0x0801216d - 8012198: 0801216d .word 0x0801216d - 801219c: 080121f1 .word 0x080121f1 - 80121a0: 0801216d .word 0x0801216d - 80121a4: 0801216d .word 0x0801216d - 80121a8: 0801216d .word 0x0801216d - 80121ac: 0801216d .word 0x0801216d - 80121b0: 080122f5 .word 0x080122f5 - 80121b4: 0801221d .word 0x0801221d - 80121b8: 080122af .word 0x080122af - 80121bc: 0801216d .word 0x0801216d - 80121c0: 0801216d .word 0x0801216d - 80121c4: 08012317 .word 0x08012317 - 80121c8: 0801216d .word 0x0801216d - 80121cc: 0801221d .word 0x0801221d - 80121d0: 0801216d .word 0x0801216d - 80121d4: 0801216d .word 0x0801216d - 80121d8: 080122b7 .word 0x080122b7 - 80121dc: 682b ldr r3, [r5, #0] - 80121de: 1d1a adds r2, r3, #4 - 80121e0: 681b ldr r3, [r3, #0] - 80121e2: 602a str r2, [r5, #0] - 80121e4: f104 0542 add.w r5, r4, #66 ; 0x42 - 80121e8: f884 3042 strb.w r3, [r4, #66] ; 0x42 - 80121ec: 2301 movs r3, #1 - 80121ee: e09f b.n 8012330 <_printf_i+0x1ec> - 80121f0: 6820 ldr r0, [r4, #0] - 80121f2: 682b ldr r3, [r5, #0] - 80121f4: 0607 lsls r7, r0, #24 - 80121f6: f103 0104 add.w r1, r3, #4 - 80121fa: 6029 str r1, [r5, #0] - 80121fc: d501 bpl.n 8012202 <_printf_i+0xbe> - 80121fe: 681e ldr r6, [r3, #0] - 8012200: e003 b.n 801220a <_printf_i+0xc6> - 8012202: 0646 lsls r6, r0, #25 - 8012204: d5fb bpl.n 80121fe <_printf_i+0xba> - 8012206: f9b3 6000 ldrsh.w r6, [r3] - 801220a: 2e00 cmp r6, #0 - 801220c: da03 bge.n 8012216 <_printf_i+0xd2> - 801220e: 232d movs r3, #45 ; 0x2d - 8012210: 4276 negs r6, r6 - 8012212: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 8012216: 485a ldr r0, [pc, #360] ; (8012380 <_printf_i+0x23c>) - 8012218: 230a movs r3, #10 - 801221a: e012 b.n 8012242 <_printf_i+0xfe> - 801221c: 682b ldr r3, [r5, #0] - 801221e: 6820 ldr r0, [r4, #0] - 8012220: 1d19 adds r1, r3, #4 - 8012222: 6029 str r1, [r5, #0] - 8012224: 0605 lsls r5, r0, #24 - 8012226: d501 bpl.n 801222c <_printf_i+0xe8> - 8012228: 681e ldr r6, [r3, #0] - 801222a: e002 b.n 8012232 <_printf_i+0xee> - 801222c: 0641 lsls r1, r0, #25 - 801222e: d5fb bpl.n 8012228 <_printf_i+0xe4> - 8012230: 881e ldrh r6, [r3, #0] - 8012232: 4853 ldr r0, [pc, #332] ; (8012380 <_printf_i+0x23c>) - 8012234: 2f6f cmp r7, #111 ; 0x6f - 8012236: bf0c ite eq - 8012238: 2308 moveq r3, #8 - 801223a: 230a movne r3, #10 - 801223c: 2100 movs r1, #0 - 801223e: f884 1043 strb.w r1, [r4, #67] ; 0x43 - 8012242: 6865 ldr r5, [r4, #4] - 8012244: 60a5 str r5, [r4, #8] - 8012246: 2d00 cmp r5, #0 - 8012248: bfa2 ittt ge - 801224a: 6821 ldrge r1, [r4, #0] - 801224c: f021 0104 bicge.w r1, r1, #4 - 8012250: 6021 strge r1, [r4, #0] - 8012252: b90e cbnz r6, 8012258 <_printf_i+0x114> - 8012254: 2d00 cmp r5, #0 - 8012256: d04b beq.n 80122f0 <_printf_i+0x1ac> - 8012258: 4615 mov r5, r2 - 801225a: fbb6 f1f3 udiv r1, r6, r3 - 801225e: fb03 6711 mls r7, r3, r1, r6 - 8012262: 5dc7 ldrb r7, [r0, r7] - 8012264: f805 7d01 strb.w r7, [r5, #-1]! - 8012268: 4637 mov r7, r6 - 801226a: 42bb cmp r3, r7 - 801226c: 460e mov r6, r1 - 801226e: d9f4 bls.n 801225a <_printf_i+0x116> - 8012270: 2b08 cmp r3, #8 - 8012272: d10b bne.n 801228c <_printf_i+0x148> - 8012274: 6823 ldr r3, [r4, #0] - 8012276: 07de lsls r6, r3, #31 - 8012278: d508 bpl.n 801228c <_printf_i+0x148> - 801227a: 6923 ldr r3, [r4, #16] - 801227c: 6861 ldr r1, [r4, #4] - 801227e: 4299 cmp r1, r3 - 8012280: bfde ittt le - 8012282: 2330 movle r3, #48 ; 0x30 - 8012284: f805 3c01 strble.w r3, [r5, #-1] - 8012288: f105 35ff addle.w r5, r5, #4294967295 - 801228c: 1b52 subs r2, r2, r5 - 801228e: 6122 str r2, [r4, #16] - 8012290: f8cd a000 str.w sl, [sp] - 8012294: 464b mov r3, r9 - 8012296: aa03 add r2, sp, #12 - 8012298: 4621 mov r1, r4 - 801229a: 4640 mov r0, r8 - 801229c: f7ff fee4 bl 8012068 <_printf_common> - 80122a0: 3001 adds r0, #1 - 80122a2: d14a bne.n 801233a <_printf_i+0x1f6> - 80122a4: f04f 30ff mov.w r0, #4294967295 - 80122a8: b004 add sp, #16 - 80122aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80122ae: 6823 ldr r3, [r4, #0] - 80122b0: f043 0320 orr.w r3, r3, #32 - 80122b4: 6023 str r3, [r4, #0] - 80122b6: 4833 ldr r0, [pc, #204] ; (8012384 <_printf_i+0x240>) - 80122b8: 2778 movs r7, #120 ; 0x78 - 80122ba: f884 7045 strb.w r7, [r4, #69] ; 0x45 - 80122be: 6823 ldr r3, [r4, #0] - 80122c0: 6829 ldr r1, [r5, #0] - 80122c2: 061f lsls r7, r3, #24 - 80122c4: f851 6b04 ldr.w r6, [r1], #4 - 80122c8: d402 bmi.n 80122d0 <_printf_i+0x18c> - 80122ca: 065f lsls r7, r3, #25 - 80122cc: bf48 it mi - 80122ce: b2b6 uxthmi r6, r6 - 80122d0: 07df lsls r7, r3, #31 - 80122d2: bf48 it mi - 80122d4: f043 0320 orrmi.w r3, r3, #32 - 80122d8: 6029 str r1, [r5, #0] - 80122da: bf48 it mi - 80122dc: 6023 strmi r3, [r4, #0] - 80122de: b91e cbnz r6, 80122e8 <_printf_i+0x1a4> - 80122e0: 6823 ldr r3, [r4, #0] - 80122e2: f023 0320 bic.w r3, r3, #32 - 80122e6: 6023 str r3, [r4, #0] - 80122e8: 2310 movs r3, #16 - 80122ea: e7a7 b.n 801223c <_printf_i+0xf8> - 80122ec: 4824 ldr r0, [pc, #144] ; (8012380 <_printf_i+0x23c>) - 80122ee: e7e4 b.n 80122ba <_printf_i+0x176> - 80122f0: 4615 mov r5, r2 - 80122f2: e7bd b.n 8012270 <_printf_i+0x12c> - 80122f4: 682b ldr r3, [r5, #0] - 80122f6: 6826 ldr r6, [r4, #0] - 80122f8: 6961 ldr r1, [r4, #20] - 80122fa: 1d18 adds r0, r3, #4 - 80122fc: 6028 str r0, [r5, #0] - 80122fe: 0635 lsls r5, r6, #24 - 8012300: 681b ldr r3, [r3, #0] - 8012302: d501 bpl.n 8012308 <_printf_i+0x1c4> - 8012304: 6019 str r1, [r3, #0] - 8012306: e002 b.n 801230e <_printf_i+0x1ca> - 8012308: 0670 lsls r0, r6, #25 - 801230a: d5fb bpl.n 8012304 <_printf_i+0x1c0> - 801230c: 8019 strh r1, [r3, #0] - 801230e: 2300 movs r3, #0 - 8012310: 6123 str r3, [r4, #16] - 8012312: 4615 mov r5, r2 - 8012314: e7bc b.n 8012290 <_printf_i+0x14c> - 8012316: 682b ldr r3, [r5, #0] - 8012318: 1d1a adds r2, r3, #4 - 801231a: 602a str r2, [r5, #0] - 801231c: 681d ldr r5, [r3, #0] - 801231e: 6862 ldr r2, [r4, #4] - 8012320: 2100 movs r1, #0 - 8012322: 4628 mov r0, r5 - 8012324: f7ed ff54 bl 80001d0 - 8012328: b108 cbz r0, 801232e <_printf_i+0x1ea> - 801232a: 1b40 subs r0, r0, r5 - 801232c: 6060 str r0, [r4, #4] - 801232e: 6863 ldr r3, [r4, #4] - 8012330: 6123 str r3, [r4, #16] - 8012332: 2300 movs r3, #0 - 8012334: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 8012338: e7aa b.n 8012290 <_printf_i+0x14c> - 801233a: 6923 ldr r3, [r4, #16] - 801233c: 462a mov r2, r5 - 801233e: 4649 mov r1, r9 - 8012340: 4640 mov r0, r8 - 8012342: 47d0 blx sl - 8012344: 3001 adds r0, #1 - 8012346: d0ad beq.n 80122a4 <_printf_i+0x160> - 8012348: 6823 ldr r3, [r4, #0] - 801234a: 079b lsls r3, r3, #30 - 801234c: d413 bmi.n 8012376 <_printf_i+0x232> - 801234e: 68e0 ldr r0, [r4, #12] - 8012350: 9b03 ldr r3, [sp, #12] - 8012352: 4298 cmp r0, r3 - 8012354: bfb8 it lt - 8012356: 4618 movlt r0, r3 - 8012358: e7a6 b.n 80122a8 <_printf_i+0x164> - 801235a: 2301 movs r3, #1 - 801235c: 4632 mov r2, r6 - 801235e: 4649 mov r1, r9 - 8012360: 4640 mov r0, r8 - 8012362: 47d0 blx sl - 8012364: 3001 adds r0, #1 - 8012366: d09d beq.n 80122a4 <_printf_i+0x160> - 8012368: 3501 adds r5, #1 - 801236a: 68e3 ldr r3, [r4, #12] - 801236c: 9903 ldr r1, [sp, #12] - 801236e: 1a5b subs r3, r3, r1 - 8012370: 42ab cmp r3, r5 - 8012372: dcf2 bgt.n 801235a <_printf_i+0x216> - 8012374: e7eb b.n 801234e <_printf_i+0x20a> - 8012376: 2500 movs r5, #0 - 8012378: f104 0619 add.w r6, r4, #25 - 801237c: e7f5 b.n 801236a <_printf_i+0x226> - 801237e: bf00 nop - 8012380: 0801887b .word 0x0801887b - 8012384: 0801888c .word 0x0801888c - -08012388 <_scanf_float>: - 8012388: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 801238c: b087 sub sp, #28 - 801238e: 4617 mov r7, r2 - 8012390: 9303 str r3, [sp, #12] - 8012392: 688b ldr r3, [r1, #8] - 8012394: 1e5a subs r2, r3, #1 - 8012396: f5b2 7fae cmp.w r2, #348 ; 0x15c - 801239a: bf83 ittte hi - 801239c: f46f 75ae mvnhi.w r5, #348 ; 0x15c - 80123a0: 195b addhi r3, r3, r5 - 80123a2: 9302 strhi r3, [sp, #8] - 80123a4: 2300 movls r3, #0 - 80123a6: bf86 itte hi - 80123a8: f240 135d movwhi r3, #349 ; 0x15d - 80123ac: 608b strhi r3, [r1, #8] - 80123ae: 9302 strls r3, [sp, #8] - 80123b0: 680b ldr r3, [r1, #0] - 80123b2: 468b mov fp, r1 - 80123b4: 2500 movs r5, #0 - 80123b6: f443 63f0 orr.w r3, r3, #1920 ; 0x780 - 80123ba: f84b 3b1c str.w r3, [fp], #28 - 80123be: e9cd 5504 strd r5, r5, [sp, #16] - 80123c2: 4680 mov r8, r0 - 80123c4: 460c mov r4, r1 - 80123c6: 465e mov r6, fp - 80123c8: 46aa mov sl, r5 - 80123ca: 46a9 mov r9, r5 - 80123cc: 9501 str r5, [sp, #4] - 80123ce: 68a2 ldr r2, [r4, #8] - 80123d0: b152 cbz r2, 80123e8 <_scanf_float+0x60> - 80123d2: 683b ldr r3, [r7, #0] - 80123d4: 781b ldrb r3, [r3, #0] - 80123d6: 2b4e cmp r3, #78 ; 0x4e - 80123d8: d864 bhi.n 80124a4 <_scanf_float+0x11c> - 80123da: 2b40 cmp r3, #64 ; 0x40 - 80123dc: d83c bhi.n 8012458 <_scanf_float+0xd0> - 80123de: f1a3 012b sub.w r1, r3, #43 ; 0x2b - 80123e2: b2c8 uxtb r0, r1 - 80123e4: 280e cmp r0, #14 - 80123e6: d93a bls.n 801245e <_scanf_float+0xd6> - 80123e8: f1b9 0f00 cmp.w r9, #0 - 80123ec: d003 beq.n 80123f6 <_scanf_float+0x6e> - 80123ee: 6823 ldr r3, [r4, #0] - 80123f0: f423 7380 bic.w r3, r3, #256 ; 0x100 - 80123f4: 6023 str r3, [r4, #0] - 80123f6: f10a 3aff add.w sl, sl, #4294967295 - 80123fa: f1ba 0f01 cmp.w sl, #1 - 80123fe: f200 8113 bhi.w 8012628 <_scanf_float+0x2a0> - 8012402: 455e cmp r6, fp - 8012404: f200 8105 bhi.w 8012612 <_scanf_float+0x28a> - 8012408: 2501 movs r5, #1 - 801240a: 4628 mov r0, r5 - 801240c: b007 add sp, #28 - 801240e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8012412: f1a3 0261 sub.w r2, r3, #97 ; 0x61 - 8012416: 2a0d cmp r2, #13 - 8012418: d8e6 bhi.n 80123e8 <_scanf_float+0x60> - 801241a: a101 add r1, pc, #4 ; (adr r1, 8012420 <_scanf_float+0x98>) - 801241c: f851 f022 ldr.w pc, [r1, r2, lsl #2] - 8012420: 0801255f .word 0x0801255f - 8012424: 080123e9 .word 0x080123e9 - 8012428: 080123e9 .word 0x080123e9 - 801242c: 080123e9 .word 0x080123e9 - 8012430: 080125bf .word 0x080125bf - 8012434: 08012597 .word 0x08012597 - 8012438: 080123e9 .word 0x080123e9 - 801243c: 080123e9 .word 0x080123e9 - 8012440: 0801256d .word 0x0801256d - 8012444: 080123e9 .word 0x080123e9 - 8012448: 080123e9 .word 0x080123e9 - 801244c: 080123e9 .word 0x080123e9 - 8012450: 080123e9 .word 0x080123e9 - 8012454: 08012525 .word 0x08012525 - 8012458: f1a3 0241 sub.w r2, r3, #65 ; 0x41 - 801245c: e7db b.n 8012416 <_scanf_float+0x8e> - 801245e: 290e cmp r1, #14 - 8012460: d8c2 bhi.n 80123e8 <_scanf_float+0x60> - 8012462: a001 add r0, pc, #4 ; (adr r0, 8012468 <_scanf_float+0xe0>) - 8012464: f850 f021 ldr.w pc, [r0, r1, lsl #2] - 8012468: 08012517 .word 0x08012517 - 801246c: 080123e9 .word 0x080123e9 - 8012470: 08012517 .word 0x08012517 - 8012474: 080125ab .word 0x080125ab - 8012478: 080123e9 .word 0x080123e9 - 801247c: 080124c5 .word 0x080124c5 - 8012480: 08012501 .word 0x08012501 - 8012484: 08012501 .word 0x08012501 - 8012488: 08012501 .word 0x08012501 - 801248c: 08012501 .word 0x08012501 - 8012490: 08012501 .word 0x08012501 - 8012494: 08012501 .word 0x08012501 - 8012498: 08012501 .word 0x08012501 - 801249c: 08012501 .word 0x08012501 - 80124a0: 08012501 .word 0x08012501 - 80124a4: 2b6e cmp r3, #110 ; 0x6e - 80124a6: d809 bhi.n 80124bc <_scanf_float+0x134> - 80124a8: 2b60 cmp r3, #96 ; 0x60 - 80124aa: d8b2 bhi.n 8012412 <_scanf_float+0x8a> - 80124ac: 2b54 cmp r3, #84 ; 0x54 - 80124ae: d077 beq.n 80125a0 <_scanf_float+0x218> - 80124b0: 2b59 cmp r3, #89 ; 0x59 - 80124b2: d199 bne.n 80123e8 <_scanf_float+0x60> - 80124b4: 2d07 cmp r5, #7 - 80124b6: d197 bne.n 80123e8 <_scanf_float+0x60> - 80124b8: 2508 movs r5, #8 - 80124ba: e029 b.n 8012510 <_scanf_float+0x188> - 80124bc: 2b74 cmp r3, #116 ; 0x74 - 80124be: d06f beq.n 80125a0 <_scanf_float+0x218> - 80124c0: 2b79 cmp r3, #121 ; 0x79 - 80124c2: e7f6 b.n 80124b2 <_scanf_float+0x12a> - 80124c4: 6821 ldr r1, [r4, #0] - 80124c6: 05c8 lsls r0, r1, #23 - 80124c8: d51a bpl.n 8012500 <_scanf_float+0x178> - 80124ca: 9b02 ldr r3, [sp, #8] - 80124cc: f021 0180 bic.w r1, r1, #128 ; 0x80 - 80124d0: 6021 str r1, [r4, #0] - 80124d2: f109 0901 add.w r9, r9, #1 - 80124d6: b11b cbz r3, 80124e0 <_scanf_float+0x158> - 80124d8: 3b01 subs r3, #1 - 80124da: 3201 adds r2, #1 - 80124dc: 9302 str r3, [sp, #8] - 80124de: 60a2 str r2, [r4, #8] - 80124e0: 68a3 ldr r3, [r4, #8] - 80124e2: 3b01 subs r3, #1 - 80124e4: 60a3 str r3, [r4, #8] - 80124e6: 6923 ldr r3, [r4, #16] - 80124e8: 3301 adds r3, #1 - 80124ea: 6123 str r3, [r4, #16] - 80124ec: 687b ldr r3, [r7, #4] - 80124ee: 3b01 subs r3, #1 - 80124f0: 2b00 cmp r3, #0 - 80124f2: 607b str r3, [r7, #4] - 80124f4: f340 8084 ble.w 8012600 <_scanf_float+0x278> - 80124f8: 683b ldr r3, [r7, #0] - 80124fa: 3301 adds r3, #1 - 80124fc: 603b str r3, [r7, #0] - 80124fe: e766 b.n 80123ce <_scanf_float+0x46> - 8012500: eb1a 0f05 cmn.w sl, r5 - 8012504: f47f af70 bne.w 80123e8 <_scanf_float+0x60> - 8012508: 6822 ldr r2, [r4, #0] - 801250a: f422 72c0 bic.w r2, r2, #384 ; 0x180 - 801250e: 6022 str r2, [r4, #0] - 8012510: f806 3b01 strb.w r3, [r6], #1 - 8012514: e7e4 b.n 80124e0 <_scanf_float+0x158> - 8012516: 6822 ldr r2, [r4, #0] - 8012518: 0610 lsls r0, r2, #24 - 801251a: f57f af65 bpl.w 80123e8 <_scanf_float+0x60> - 801251e: f022 0280 bic.w r2, r2, #128 ; 0x80 - 8012522: e7f4 b.n 801250e <_scanf_float+0x186> - 8012524: f1ba 0f00 cmp.w sl, #0 - 8012528: d10e bne.n 8012548 <_scanf_float+0x1c0> - 801252a: f1b9 0f00 cmp.w r9, #0 - 801252e: d10e bne.n 801254e <_scanf_float+0x1c6> - 8012530: 6822 ldr r2, [r4, #0] - 8012532: f402 61e0 and.w r1, r2, #1792 ; 0x700 - 8012536: f5b1 6fe0 cmp.w r1, #1792 ; 0x700 - 801253a: d108 bne.n 801254e <_scanf_float+0x1c6> - 801253c: f422 62f0 bic.w r2, r2, #1920 ; 0x780 - 8012540: 6022 str r2, [r4, #0] - 8012542: f04f 0a01 mov.w sl, #1 - 8012546: e7e3 b.n 8012510 <_scanf_float+0x188> - 8012548: f1ba 0f02 cmp.w sl, #2 - 801254c: d055 beq.n 80125fa <_scanf_float+0x272> - 801254e: 2d01 cmp r5, #1 - 8012550: d002 beq.n 8012558 <_scanf_float+0x1d0> - 8012552: 2d04 cmp r5, #4 - 8012554: f47f af48 bne.w 80123e8 <_scanf_float+0x60> - 8012558: 3501 adds r5, #1 - 801255a: b2ed uxtb r5, r5 - 801255c: e7d8 b.n 8012510 <_scanf_float+0x188> - 801255e: f1ba 0f01 cmp.w sl, #1 - 8012562: f47f af41 bne.w 80123e8 <_scanf_float+0x60> - 8012566: f04f 0a02 mov.w sl, #2 - 801256a: e7d1 b.n 8012510 <_scanf_float+0x188> - 801256c: b97d cbnz r5, 801258e <_scanf_float+0x206> - 801256e: f1b9 0f00 cmp.w r9, #0 - 8012572: f47f af3c bne.w 80123ee <_scanf_float+0x66> - 8012576: 6822 ldr r2, [r4, #0] - 8012578: f402 61e0 and.w r1, r2, #1792 ; 0x700 - 801257c: f5b1 6fe0 cmp.w r1, #1792 ; 0x700 - 8012580: f47f af39 bne.w 80123f6 <_scanf_float+0x6e> - 8012584: f422 62f0 bic.w r2, r2, #1920 ; 0x780 - 8012588: 6022 str r2, [r4, #0] - 801258a: 2501 movs r5, #1 - 801258c: e7c0 b.n 8012510 <_scanf_float+0x188> - 801258e: 2d03 cmp r5, #3 - 8012590: d0e2 beq.n 8012558 <_scanf_float+0x1d0> - 8012592: 2d05 cmp r5, #5 - 8012594: e7de b.n 8012554 <_scanf_float+0x1cc> - 8012596: 2d02 cmp r5, #2 - 8012598: f47f af26 bne.w 80123e8 <_scanf_float+0x60> - 801259c: 2503 movs r5, #3 - 801259e: e7b7 b.n 8012510 <_scanf_float+0x188> - 80125a0: 2d06 cmp r5, #6 - 80125a2: f47f af21 bne.w 80123e8 <_scanf_float+0x60> - 80125a6: 2507 movs r5, #7 - 80125a8: e7b2 b.n 8012510 <_scanf_float+0x188> - 80125aa: 6822 ldr r2, [r4, #0] - 80125ac: 0591 lsls r1, r2, #22 - 80125ae: f57f af1b bpl.w 80123e8 <_scanf_float+0x60> - 80125b2: f422 7220 bic.w r2, r2, #640 ; 0x280 - 80125b6: 6022 str r2, [r4, #0] - 80125b8: f8cd 9004 str.w r9, [sp, #4] - 80125bc: e7a8 b.n 8012510 <_scanf_float+0x188> - 80125be: 6822 ldr r2, [r4, #0] - 80125c0: f402 61a0 and.w r1, r2, #1280 ; 0x500 - 80125c4: f5b1 6f80 cmp.w r1, #1024 ; 0x400 - 80125c8: d006 beq.n 80125d8 <_scanf_float+0x250> - 80125ca: 0550 lsls r0, r2, #21 - 80125cc: f57f af0c bpl.w 80123e8 <_scanf_float+0x60> - 80125d0: f1b9 0f00 cmp.w r9, #0 - 80125d4: f43f af0f beq.w 80123f6 <_scanf_float+0x6e> - 80125d8: 0591 lsls r1, r2, #22 - 80125da: bf58 it pl - 80125dc: 9901 ldrpl r1, [sp, #4] - 80125de: f422 62f0 bic.w r2, r2, #1920 ; 0x780 - 80125e2: bf58 it pl - 80125e4: eba9 0101 subpl.w r1, r9, r1 - 80125e8: f442 72c0 orr.w r2, r2, #384 ; 0x180 - 80125ec: bf58 it pl - 80125ee: e9cd 1604 strdpl r1, r6, [sp, #16] - 80125f2: 6022 str r2, [r4, #0] - 80125f4: f04f 0900 mov.w r9, #0 - 80125f8: e78a b.n 8012510 <_scanf_float+0x188> - 80125fa: f04f 0a03 mov.w sl, #3 - 80125fe: e787 b.n 8012510 <_scanf_float+0x188> - 8012600: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 - 8012604: 4639 mov r1, r7 - 8012606: 4640 mov r0, r8 - 8012608: 4798 blx r3 - 801260a: 2800 cmp r0, #0 - 801260c: f43f aedf beq.w 80123ce <_scanf_float+0x46> - 8012610: e6ea b.n 80123e8 <_scanf_float+0x60> - 8012612: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 8012616: f816 1d01 ldrb.w r1, [r6, #-1]! - 801261a: 463a mov r2, r7 - 801261c: 4640 mov r0, r8 - 801261e: 4798 blx r3 - 8012620: 6923 ldr r3, [r4, #16] - 8012622: 3b01 subs r3, #1 - 8012624: 6123 str r3, [r4, #16] - 8012626: e6ec b.n 8012402 <_scanf_float+0x7a> - 8012628: 1e6b subs r3, r5, #1 - 801262a: 2b06 cmp r3, #6 - 801262c: d825 bhi.n 801267a <_scanf_float+0x2f2> - 801262e: 2d02 cmp r5, #2 - 8012630: d836 bhi.n 80126a0 <_scanf_float+0x318> - 8012632: 455e cmp r6, fp - 8012634: f67f aee8 bls.w 8012408 <_scanf_float+0x80> - 8012638: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 801263c: f816 1d01 ldrb.w r1, [r6, #-1]! - 8012640: 463a mov r2, r7 - 8012642: 4640 mov r0, r8 - 8012644: 4798 blx r3 - 8012646: 6923 ldr r3, [r4, #16] - 8012648: 3b01 subs r3, #1 - 801264a: 6123 str r3, [r4, #16] - 801264c: e7f1 b.n 8012632 <_scanf_float+0x2aa> - 801264e: 9802 ldr r0, [sp, #8] - 8012650: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 8012654: f810 1d01 ldrb.w r1, [r0, #-1]! - 8012658: 9002 str r0, [sp, #8] - 801265a: 463a mov r2, r7 - 801265c: 4640 mov r0, r8 - 801265e: 4798 blx r3 - 8012660: 6923 ldr r3, [r4, #16] - 8012662: 3b01 subs r3, #1 - 8012664: 6123 str r3, [r4, #16] - 8012666: f10a 3aff add.w sl, sl, #4294967295 - 801266a: fa5f fa8a uxtb.w sl, sl - 801266e: f1ba 0f02 cmp.w sl, #2 - 8012672: d1ec bne.n 801264e <_scanf_float+0x2c6> - 8012674: 3d03 subs r5, #3 - 8012676: b2ed uxtb r5, r5 - 8012678: 1b76 subs r6, r6, r5 - 801267a: 6823 ldr r3, [r4, #0] - 801267c: 05da lsls r2, r3, #23 - 801267e: d52f bpl.n 80126e0 <_scanf_float+0x358> - 8012680: 055b lsls r3, r3, #21 - 8012682: d510 bpl.n 80126a6 <_scanf_float+0x31e> - 8012684: 455e cmp r6, fp - 8012686: f67f aebf bls.w 8012408 <_scanf_float+0x80> - 801268a: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 801268e: f816 1d01 ldrb.w r1, [r6, #-1]! - 8012692: 463a mov r2, r7 - 8012694: 4640 mov r0, r8 - 8012696: 4798 blx r3 - 8012698: 6923 ldr r3, [r4, #16] - 801269a: 3b01 subs r3, #1 - 801269c: 6123 str r3, [r4, #16] - 801269e: e7f1 b.n 8012684 <_scanf_float+0x2fc> - 80126a0: 46aa mov sl, r5 - 80126a2: 9602 str r6, [sp, #8] - 80126a4: e7df b.n 8012666 <_scanf_float+0x2de> - 80126a6: f816 1c01 ldrb.w r1, [r6, #-1] - 80126aa: 6923 ldr r3, [r4, #16] - 80126ac: 2965 cmp r1, #101 ; 0x65 - 80126ae: f103 33ff add.w r3, r3, #4294967295 - 80126b2: f106 35ff add.w r5, r6, #4294967295 - 80126b6: 6123 str r3, [r4, #16] - 80126b8: d00c beq.n 80126d4 <_scanf_float+0x34c> - 80126ba: 2945 cmp r1, #69 ; 0x45 - 80126bc: d00a beq.n 80126d4 <_scanf_float+0x34c> - 80126be: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 80126c2: 463a mov r2, r7 - 80126c4: 4640 mov r0, r8 - 80126c6: 4798 blx r3 - 80126c8: 6923 ldr r3, [r4, #16] - 80126ca: f816 1c02 ldrb.w r1, [r6, #-2] - 80126ce: 3b01 subs r3, #1 - 80126d0: 1eb5 subs r5, r6, #2 - 80126d2: 6123 str r3, [r4, #16] - 80126d4: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c - 80126d8: 463a mov r2, r7 - 80126da: 4640 mov r0, r8 - 80126dc: 4798 blx r3 - 80126de: 462e mov r6, r5 - 80126e0: 6825 ldr r5, [r4, #0] - 80126e2: f015 0510 ands.w r5, r5, #16 - 80126e6: d158 bne.n 801279a <_scanf_float+0x412> - 80126e8: 7035 strb r5, [r6, #0] - 80126ea: 6823 ldr r3, [r4, #0] - 80126ec: f403 63c0 and.w r3, r3, #1536 ; 0x600 - 80126f0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 80126f4: d11c bne.n 8012730 <_scanf_float+0x3a8> - 80126f6: 9b01 ldr r3, [sp, #4] - 80126f8: 454b cmp r3, r9 - 80126fa: eba3 0209 sub.w r2, r3, r9 - 80126fe: d124 bne.n 801274a <_scanf_float+0x3c2> - 8012700: 2200 movs r2, #0 - 8012702: 4659 mov r1, fp - 8012704: 4640 mov r0, r8 - 8012706: f7ff f8df bl 80118c8 <_strtod_r> - 801270a: 9b03 ldr r3, [sp, #12] - 801270c: 6821 ldr r1, [r4, #0] - 801270e: 681b ldr r3, [r3, #0] - 8012710: f011 0f02 tst.w r1, #2 - 8012714: ec57 6b10 vmov r6, r7, d0 - 8012718: f103 0204 add.w r2, r3, #4 - 801271c: d020 beq.n 8012760 <_scanf_float+0x3d8> - 801271e: 9903 ldr r1, [sp, #12] - 8012720: 600a str r2, [r1, #0] - 8012722: 681b ldr r3, [r3, #0] - 8012724: e9c3 6700 strd r6, r7, [r3] - 8012728: 68e3 ldr r3, [r4, #12] - 801272a: 3301 adds r3, #1 - 801272c: 60e3 str r3, [r4, #12] - 801272e: e66c b.n 801240a <_scanf_float+0x82> - 8012730: 9b04 ldr r3, [sp, #16] - 8012732: 2b00 cmp r3, #0 - 8012734: d0e4 beq.n 8012700 <_scanf_float+0x378> - 8012736: 9905 ldr r1, [sp, #20] - 8012738: 230a movs r3, #10 - 801273a: 462a mov r2, r5 - 801273c: 3101 adds r1, #1 - 801273e: 4640 mov r0, r8 - 8012740: f7ff f9b0 bl 8011aa4 <_strtol_r> - 8012744: 9b04 ldr r3, [sp, #16] - 8012746: 9e05 ldr r6, [sp, #20] - 8012748: 1ac2 subs r2, r0, r3 - 801274a: f204 136f addw r3, r4, #367 ; 0x16f - 801274e: 429e cmp r6, r3 - 8012750: bf28 it cs - 8012752: f504 76b7 addcs.w r6, r4, #366 ; 0x16e - 8012756: 4912 ldr r1, [pc, #72] ; (80127a0 <_scanf_float+0x418>) - 8012758: 4630 mov r0, r6 - 801275a: f000 f91b bl 8012994 - 801275e: e7cf b.n 8012700 <_scanf_float+0x378> - 8012760: f011 0f04 tst.w r1, #4 - 8012764: 9903 ldr r1, [sp, #12] - 8012766: 600a str r2, [r1, #0] - 8012768: d1db bne.n 8012722 <_scanf_float+0x39a> - 801276a: f8d3 8000 ldr.w r8, [r3] - 801276e: ee10 2a10 vmov r2, s0 - 8012772: ee10 0a10 vmov r0, s0 - 8012776: 463b mov r3, r7 - 8012778: 4639 mov r1, r7 - 801277a: f7ee f9d7 bl 8000b2c <__aeabi_dcmpun> - 801277e: b128 cbz r0, 801278c <_scanf_float+0x404> - 8012780: 4808 ldr r0, [pc, #32] ; (80127a4 <_scanf_float+0x41c>) - 8012782: f000 fa9d bl 8012cc0 - 8012786: ed88 0a00 vstr s0, [r8] - 801278a: e7cd b.n 8012728 <_scanf_float+0x3a0> - 801278c: 4630 mov r0, r6 - 801278e: 4639 mov r1, r7 - 8012790: f7ee fa2a bl 8000be8 <__aeabi_d2f> - 8012794: f8c8 0000 str.w r0, [r8] - 8012798: e7c6 b.n 8012728 <_scanf_float+0x3a0> - 801279a: 2500 movs r5, #0 - 801279c: e635 b.n 801240a <_scanf_float+0x82> - 801279e: bf00 nop - 80127a0: 0801889d .word 0x0801889d - 80127a4: 08018956 .word 0x08018956 - -080127a8 : - 80127a8: 2300 movs r3, #0 - 80127aa: b510 push {r4, lr} - 80127ac: 4604 mov r4, r0 - 80127ae: e9c0 3300 strd r3, r3, [r0] - 80127b2: e9c0 3304 strd r3, r3, [r0, #16] - 80127b6: 6083 str r3, [r0, #8] - 80127b8: 8181 strh r1, [r0, #12] - 80127ba: 6643 str r3, [r0, #100] ; 0x64 - 80127bc: 81c2 strh r2, [r0, #14] - 80127be: 6183 str r3, [r0, #24] - 80127c0: 4619 mov r1, r3 - 80127c2: 2208 movs r2, #8 - 80127c4: 305c adds r0, #92 ; 0x5c - 80127c6: f000 f948 bl 8012a5a - 80127ca: 4b0d ldr r3, [pc, #52] ; (8012800 ) - 80127cc: 6263 str r3, [r4, #36] ; 0x24 - 80127ce: 4b0d ldr r3, [pc, #52] ; (8012804 ) - 80127d0: 62a3 str r3, [r4, #40] ; 0x28 - 80127d2: 4b0d ldr r3, [pc, #52] ; (8012808 ) - 80127d4: 62e3 str r3, [r4, #44] ; 0x2c - 80127d6: 4b0d ldr r3, [pc, #52] ; (801280c ) - 80127d8: 6323 str r3, [r4, #48] ; 0x30 - 80127da: 4b0d ldr r3, [pc, #52] ; (8012810 ) - 80127dc: 6224 str r4, [r4, #32] - 80127de: 429c cmp r4, r3 - 80127e0: d006 beq.n 80127f0 - 80127e2: f103 0268 add.w r2, r3, #104 ; 0x68 - 80127e6: 4294 cmp r4, r2 - 80127e8: d002 beq.n 80127f0 - 80127ea: 33d0 adds r3, #208 ; 0xd0 - 80127ec: 429c cmp r4, r3 - 80127ee: d105 bne.n 80127fc - 80127f0: f104 0058 add.w r0, r4, #88 ; 0x58 - 80127f4: e8bd 4010 ldmia.w sp!, {r4, lr} - 80127f8: f000 ba40 b.w 8012c7c <__retarget_lock_init_recursive> - 80127fc: bd10 pop {r4, pc} - 80127fe: bf00 nop - 8012800: 080129d5 .word 0x080129d5 - 8012804: 080129f7 .word 0x080129f7 - 8012808: 08012a2f .word 0x08012a2f - 801280c: 08012a53 .word 0x08012a53 - 8012810: 20001494 .word 0x20001494 - -08012814 : - 8012814: 4a02 ldr r2, [pc, #8] ; (8012820 ) - 8012816: 4903 ldr r1, [pc, #12] ; (8012824 ) - 8012818: 4803 ldr r0, [pc, #12] ; (8012828 ) - 801281a: f000 b869 b.w 80128f0 <_fwalk_sglue> - 801281e: bf00 nop - 8012820: 2000014c .word 0x2000014c - 8012824: 08014e99 .word 0x08014e99 - 8012828: 200002c4 .word 0x200002c4 - -0801282c : - 801282c: 6841 ldr r1, [r0, #4] - 801282e: 4b0c ldr r3, [pc, #48] ; (8012860 ) - 8012830: 4299 cmp r1, r3 - 8012832: b510 push {r4, lr} - 8012834: 4604 mov r4, r0 - 8012836: d001 beq.n 801283c - 8012838: f002 fb2e bl 8014e98 <_fflush_r> - 801283c: 68a1 ldr r1, [r4, #8] - 801283e: 4b09 ldr r3, [pc, #36] ; (8012864 ) - 8012840: 4299 cmp r1, r3 - 8012842: d002 beq.n 801284a - 8012844: 4620 mov r0, r4 - 8012846: f002 fb27 bl 8014e98 <_fflush_r> - 801284a: 68e1 ldr r1, [r4, #12] - 801284c: 4b06 ldr r3, [pc, #24] ; (8012868 ) - 801284e: 4299 cmp r1, r3 - 8012850: d004 beq.n 801285c - 8012852: 4620 mov r0, r4 - 8012854: e8bd 4010 ldmia.w sp!, {r4, lr} - 8012858: f002 bb1e b.w 8014e98 <_fflush_r> - 801285c: bd10 pop {r4, pc} - 801285e: bf00 nop - 8012860: 20001494 .word 0x20001494 - 8012864: 200014fc .word 0x200014fc - 8012868: 20001564 .word 0x20001564 - -0801286c : - 801286c: b510 push {r4, lr} - 801286e: 4b0b ldr r3, [pc, #44] ; (801289c ) - 8012870: 4c0b ldr r4, [pc, #44] ; (80128a0 ) - 8012872: 4a0c ldr r2, [pc, #48] ; (80128a4 ) - 8012874: 601a str r2, [r3, #0] - 8012876: 4620 mov r0, r4 - 8012878: 2200 movs r2, #0 - 801287a: 2104 movs r1, #4 - 801287c: f7ff ff94 bl 80127a8 - 8012880: f104 0068 add.w r0, r4, #104 ; 0x68 - 8012884: 2201 movs r2, #1 - 8012886: 2109 movs r1, #9 - 8012888: f7ff ff8e bl 80127a8 - 801288c: f104 00d0 add.w r0, r4, #208 ; 0xd0 - 8012890: 2202 movs r2, #2 - 8012892: e8bd 4010 ldmia.w sp!, {r4, lr} - 8012896: 2112 movs r1, #18 - 8012898: f7ff bf86 b.w 80127a8 - 801289c: 200015cc .word 0x200015cc - 80128a0: 20001494 .word 0x20001494 - 80128a4: 08012815 .word 0x08012815 - -080128a8 <__sfp_lock_acquire>: - 80128a8: 4801 ldr r0, [pc, #4] ; (80128b0 <__sfp_lock_acquire+0x8>) - 80128aa: f000 b9e8 b.w 8012c7e <__retarget_lock_acquire_recursive> - 80128ae: bf00 nop - 80128b0: 200015d5 .word 0x200015d5 - -080128b4 <__sfp_lock_release>: - 80128b4: 4801 ldr r0, [pc, #4] ; (80128bc <__sfp_lock_release+0x8>) - 80128b6: f000 b9e3 b.w 8012c80 <__retarget_lock_release_recursive> - 80128ba: bf00 nop - 80128bc: 200015d5 .word 0x200015d5 - -080128c0 <__sinit>: - 80128c0: b510 push {r4, lr} - 80128c2: 4604 mov r4, r0 - 80128c4: f7ff fff0 bl 80128a8 <__sfp_lock_acquire> - 80128c8: 6a23 ldr r3, [r4, #32] - 80128ca: b11b cbz r3, 80128d4 <__sinit+0x14> - 80128cc: e8bd 4010 ldmia.w sp!, {r4, lr} - 80128d0: f7ff bff0 b.w 80128b4 <__sfp_lock_release> - 80128d4: 4b04 ldr r3, [pc, #16] ; (80128e8 <__sinit+0x28>) - 80128d6: 6223 str r3, [r4, #32] - 80128d8: 4b04 ldr r3, [pc, #16] ; (80128ec <__sinit+0x2c>) - 80128da: 681b ldr r3, [r3, #0] - 80128dc: 2b00 cmp r3, #0 - 80128de: d1f5 bne.n 80128cc <__sinit+0xc> - 80128e0: f7ff ffc4 bl 801286c - 80128e4: e7f2 b.n 80128cc <__sinit+0xc> - 80128e6: bf00 nop - 80128e8: 0801282d .word 0x0801282d - 80128ec: 200015cc .word 0x200015cc - -080128f0 <_fwalk_sglue>: - 80128f0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 80128f4: 4607 mov r7, r0 - 80128f6: 4688 mov r8, r1 - 80128f8: 4614 mov r4, r2 - 80128fa: 2600 movs r6, #0 - 80128fc: e9d4 9501 ldrd r9, r5, [r4, #4] - 8012900: f1b9 0901 subs.w r9, r9, #1 - 8012904: d505 bpl.n 8012912 <_fwalk_sglue+0x22> - 8012906: 6824 ldr r4, [r4, #0] - 8012908: 2c00 cmp r4, #0 - 801290a: d1f7 bne.n 80128fc <_fwalk_sglue+0xc> - 801290c: 4630 mov r0, r6 - 801290e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8012912: 89ab ldrh r3, [r5, #12] - 8012914: 2b01 cmp r3, #1 - 8012916: d907 bls.n 8012928 <_fwalk_sglue+0x38> - 8012918: f9b5 300e ldrsh.w r3, [r5, #14] - 801291c: 3301 adds r3, #1 - 801291e: d003 beq.n 8012928 <_fwalk_sglue+0x38> - 8012920: 4629 mov r1, r5 - 8012922: 4638 mov r0, r7 - 8012924: 47c0 blx r8 - 8012926: 4306 orrs r6, r0 - 8012928: 3568 adds r5, #104 ; 0x68 - 801292a: e7e9 b.n 8012900 <_fwalk_sglue+0x10> - -0801292c : - 801292c: b40c push {r2, r3} - 801292e: b530 push {r4, r5, lr} - 8012930: 4b17 ldr r3, [pc, #92] ; (8012990 ) - 8012932: 1e0c subs r4, r1, #0 - 8012934: 681d ldr r5, [r3, #0] - 8012936: b09d sub sp, #116 ; 0x74 - 8012938: da08 bge.n 801294c - 801293a: 238b movs r3, #139 ; 0x8b - 801293c: 602b str r3, [r5, #0] - 801293e: f04f 30ff mov.w r0, #4294967295 - 8012942: b01d add sp, #116 ; 0x74 - 8012944: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8012948: b002 add sp, #8 - 801294a: 4770 bx lr - 801294c: f44f 7302 mov.w r3, #520 ; 0x208 - 8012950: f8ad 3014 strh.w r3, [sp, #20] - 8012954: bf14 ite ne - 8012956: f104 33ff addne.w r3, r4, #4294967295 - 801295a: 4623 moveq r3, r4 - 801295c: 9304 str r3, [sp, #16] - 801295e: 9307 str r3, [sp, #28] - 8012960: f64f 73ff movw r3, #65535 ; 0xffff - 8012964: 9002 str r0, [sp, #8] - 8012966: 9006 str r0, [sp, #24] - 8012968: f8ad 3016 strh.w r3, [sp, #22] - 801296c: 9a20 ldr r2, [sp, #128] ; 0x80 - 801296e: ab21 add r3, sp, #132 ; 0x84 - 8012970: a902 add r1, sp, #8 - 8012972: 4628 mov r0, r5 - 8012974: 9301 str r3, [sp, #4] - 8012976: f002 f90b bl 8014b90 <_svfiprintf_r> - 801297a: 1c43 adds r3, r0, #1 - 801297c: bfbc itt lt - 801297e: 238b movlt r3, #139 ; 0x8b - 8012980: 602b strlt r3, [r5, #0] - 8012982: 2c00 cmp r4, #0 - 8012984: d0dd beq.n 8012942 - 8012986: 9b02 ldr r3, [sp, #8] - 8012988: 2200 movs r2, #0 - 801298a: 701a strb r2, [r3, #0] - 801298c: e7d9 b.n 8012942 - 801298e: bf00 nop - 8012990: 20000310 .word 0x20000310 - -08012994 : - 8012994: b40e push {r1, r2, r3} - 8012996: b500 push {lr} - 8012998: b09c sub sp, #112 ; 0x70 - 801299a: ab1d add r3, sp, #116 ; 0x74 - 801299c: 9002 str r0, [sp, #8] - 801299e: 9006 str r0, [sp, #24] - 80129a0: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 - 80129a4: 4809 ldr r0, [pc, #36] ; (80129cc ) - 80129a6: 9107 str r1, [sp, #28] - 80129a8: 9104 str r1, [sp, #16] - 80129aa: 4909 ldr r1, [pc, #36] ; (80129d0 ) - 80129ac: f853 2b04 ldr.w r2, [r3], #4 - 80129b0: 9105 str r1, [sp, #20] - 80129b2: 6800 ldr r0, [r0, #0] - 80129b4: 9301 str r3, [sp, #4] - 80129b6: a902 add r1, sp, #8 - 80129b8: f002 f8ea bl 8014b90 <_svfiprintf_r> - 80129bc: 9b02 ldr r3, [sp, #8] - 80129be: 2200 movs r2, #0 - 80129c0: 701a strb r2, [r3, #0] - 80129c2: b01c add sp, #112 ; 0x70 - 80129c4: f85d eb04 ldr.w lr, [sp], #4 - 80129c8: b003 add sp, #12 - 80129ca: 4770 bx lr - 80129cc: 20000310 .word 0x20000310 - 80129d0: ffff0208 .word 0xffff0208 - -080129d4 <__sread>: - 80129d4: b510 push {r4, lr} - 80129d6: 460c mov r4, r1 - 80129d8: f9b1 100e ldrsh.w r1, [r1, #14] - 80129dc: f000 f8f0 bl 8012bc0 <_read_r> - 80129e0: 2800 cmp r0, #0 - 80129e2: bfab itete ge - 80129e4: 6d63 ldrge r3, [r4, #84] ; 0x54 - 80129e6: 89a3 ldrhlt r3, [r4, #12] - 80129e8: 181b addge r3, r3, r0 - 80129ea: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 - 80129ee: bfac ite ge - 80129f0: 6563 strge r3, [r4, #84] ; 0x54 - 80129f2: 81a3 strhlt r3, [r4, #12] - 80129f4: bd10 pop {r4, pc} - -080129f6 <__swrite>: - 80129f6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 80129fa: 461f mov r7, r3 - 80129fc: 898b ldrh r3, [r1, #12] - 80129fe: 05db lsls r3, r3, #23 - 8012a00: 4605 mov r5, r0 - 8012a02: 460c mov r4, r1 - 8012a04: 4616 mov r6, r2 - 8012a06: d505 bpl.n 8012a14 <__swrite+0x1e> - 8012a08: f9b1 100e ldrsh.w r1, [r1, #14] - 8012a0c: 2302 movs r3, #2 - 8012a0e: 2200 movs r2, #0 - 8012a10: f000 f8c4 bl 8012b9c <_lseek_r> - 8012a14: 89a3 ldrh r3, [r4, #12] - 8012a16: f9b4 100e ldrsh.w r1, [r4, #14] - 8012a1a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 - 8012a1e: 81a3 strh r3, [r4, #12] - 8012a20: 4632 mov r2, r6 - 8012a22: 463b mov r3, r7 - 8012a24: 4628 mov r0, r5 - 8012a26: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 8012a2a: f000 b8eb b.w 8012c04 <_write_r> - -08012a2e <__sseek>: - 8012a2e: b510 push {r4, lr} - 8012a30: 460c mov r4, r1 - 8012a32: f9b1 100e ldrsh.w r1, [r1, #14] - 8012a36: f000 f8b1 bl 8012b9c <_lseek_r> - 8012a3a: 1c43 adds r3, r0, #1 - 8012a3c: 89a3 ldrh r3, [r4, #12] - 8012a3e: bf15 itete ne - 8012a40: 6560 strne r0, [r4, #84] ; 0x54 - 8012a42: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 - 8012a46: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 - 8012a4a: 81a3 strheq r3, [r4, #12] - 8012a4c: bf18 it ne - 8012a4e: 81a3 strhne r3, [r4, #12] - 8012a50: bd10 pop {r4, pc} - -08012a52 <__sclose>: - 8012a52: f9b1 100e ldrsh.w r1, [r1, #14] - 8012a56: f000 b891 b.w 8012b7c <_close_r> - -08012a5a : - 8012a5a: 4402 add r2, r0 - 8012a5c: 4603 mov r3, r0 - 8012a5e: 4293 cmp r3, r2 - 8012a60: d100 bne.n 8012a64 - 8012a62: 4770 bx lr - 8012a64: f803 1b01 strb.w r1, [r3], #1 - 8012a68: e7f9 b.n 8012a5e - -08012a6a : - 8012a6a: b510 push {r4, lr} - 8012a6c: b16a cbz r2, 8012a8a - 8012a6e: 3901 subs r1, #1 - 8012a70: 1884 adds r4, r0, r2 - 8012a72: f810 2b01 ldrb.w r2, [r0], #1 - 8012a76: f811 3f01 ldrb.w r3, [r1, #1]! - 8012a7a: 429a cmp r2, r3 - 8012a7c: d103 bne.n 8012a86 - 8012a7e: 42a0 cmp r0, r4 - 8012a80: d001 beq.n 8012a86 - 8012a82: 2a00 cmp r2, #0 - 8012a84: d1f5 bne.n 8012a72 - 8012a86: 1ad0 subs r0, r2, r3 - 8012a88: bd10 pop {r4, pc} - 8012a8a: 4610 mov r0, r2 - 8012a8c: e7fc b.n 8012a88 +080145f4 <_printf_i>: + 80145f4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 80145f8: 7e0f ldrb r7, [r1, #24] + 80145fa: 9d0c ldr r5, [sp, #48] ; 0x30 + 80145fc: 2f78 cmp r7, #120 ; 0x78 + 80145fe: 4691 mov r9, r2 + 8014600: 4680 mov r8, r0 + 8014602: 460c mov r4, r1 + 8014604: 469a mov sl, r3 + 8014606: f101 0243 add.w r2, r1, #67 ; 0x43 + 801460a: d807 bhi.n 801461c <_printf_i+0x28> + 801460c: 2f62 cmp r7, #98 ; 0x62 + 801460e: d80a bhi.n 8014626 <_printf_i+0x32> + 8014610: 2f00 cmp r7, #0 + 8014612: f000 80d4 beq.w 80147be <_printf_i+0x1ca> + 8014616: 2f58 cmp r7, #88 ; 0x58 + 8014618: f000 80c0 beq.w 801479c <_printf_i+0x1a8> + 801461c: f104 0542 add.w r5, r4, #66 ; 0x42 + 8014620: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 8014624: e03a b.n 801469c <_printf_i+0xa8> + 8014626: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 801462a: 2b15 cmp r3, #21 + 801462c: d8f6 bhi.n 801461c <_printf_i+0x28> + 801462e: a101 add r1, pc, #4 ; (adr r1, 8014634 <_printf_i+0x40>) + 8014630: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 8014634: 0801468d .word 0x0801468d + 8014638: 080146a1 .word 0x080146a1 + 801463c: 0801461d .word 0x0801461d + 8014640: 0801461d .word 0x0801461d + 8014644: 0801461d .word 0x0801461d + 8014648: 0801461d .word 0x0801461d + 801464c: 080146a1 .word 0x080146a1 + 8014650: 0801461d .word 0x0801461d + 8014654: 0801461d .word 0x0801461d + 8014658: 0801461d .word 0x0801461d + 801465c: 0801461d .word 0x0801461d + 8014660: 080147a5 .word 0x080147a5 + 8014664: 080146cd .word 0x080146cd + 8014668: 0801475f .word 0x0801475f + 801466c: 0801461d .word 0x0801461d + 8014670: 0801461d .word 0x0801461d + 8014674: 080147c7 .word 0x080147c7 + 8014678: 0801461d .word 0x0801461d + 801467c: 080146cd .word 0x080146cd + 8014680: 0801461d .word 0x0801461d + 8014684: 0801461d .word 0x0801461d + 8014688: 08014767 .word 0x08014767 + 801468c: 682b ldr r3, [r5, #0] + 801468e: 1d1a adds r2, r3, #4 + 8014690: 681b ldr r3, [r3, #0] + 8014692: 602a str r2, [r5, #0] + 8014694: f104 0542 add.w r5, r4, #66 ; 0x42 + 8014698: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 801469c: 2301 movs r3, #1 + 801469e: e09f b.n 80147e0 <_printf_i+0x1ec> + 80146a0: 6820 ldr r0, [r4, #0] + 80146a2: 682b ldr r3, [r5, #0] + 80146a4: 0607 lsls r7, r0, #24 + 80146a6: f103 0104 add.w r1, r3, #4 + 80146aa: 6029 str r1, [r5, #0] + 80146ac: d501 bpl.n 80146b2 <_printf_i+0xbe> + 80146ae: 681e ldr r6, [r3, #0] + 80146b0: e003 b.n 80146ba <_printf_i+0xc6> + 80146b2: 0646 lsls r6, r0, #25 + 80146b4: d5fb bpl.n 80146ae <_printf_i+0xba> + 80146b6: f9b3 6000 ldrsh.w r6, [r3] + 80146ba: 2e00 cmp r6, #0 + 80146bc: da03 bge.n 80146c6 <_printf_i+0xd2> + 80146be: 232d movs r3, #45 ; 0x2d + 80146c0: 4276 negs r6, r6 + 80146c2: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80146c6: 485a ldr r0, [pc, #360] ; (8014830 <_printf_i+0x23c>) + 80146c8: 230a movs r3, #10 + 80146ca: e012 b.n 80146f2 <_printf_i+0xfe> + 80146cc: 682b ldr r3, [r5, #0] + 80146ce: 6820 ldr r0, [r4, #0] + 80146d0: 1d19 adds r1, r3, #4 + 80146d2: 6029 str r1, [r5, #0] + 80146d4: 0605 lsls r5, r0, #24 + 80146d6: d501 bpl.n 80146dc <_printf_i+0xe8> + 80146d8: 681e ldr r6, [r3, #0] + 80146da: e002 b.n 80146e2 <_printf_i+0xee> + 80146dc: 0641 lsls r1, r0, #25 + 80146de: d5fb bpl.n 80146d8 <_printf_i+0xe4> + 80146e0: 881e ldrh r6, [r3, #0] + 80146e2: 4853 ldr r0, [pc, #332] ; (8014830 <_printf_i+0x23c>) + 80146e4: 2f6f cmp r7, #111 ; 0x6f + 80146e6: bf0c ite eq + 80146e8: 2308 moveq r3, #8 + 80146ea: 230a movne r3, #10 + 80146ec: 2100 movs r1, #0 + 80146ee: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 80146f2: 6865 ldr r5, [r4, #4] + 80146f4: 60a5 str r5, [r4, #8] + 80146f6: 2d00 cmp r5, #0 + 80146f8: bfa2 ittt ge + 80146fa: 6821 ldrge r1, [r4, #0] + 80146fc: f021 0104 bicge.w r1, r1, #4 + 8014700: 6021 strge r1, [r4, #0] + 8014702: b90e cbnz r6, 8014708 <_printf_i+0x114> + 8014704: 2d00 cmp r5, #0 + 8014706: d04b beq.n 80147a0 <_printf_i+0x1ac> + 8014708: 4615 mov r5, r2 + 801470a: fbb6 f1f3 udiv r1, r6, r3 + 801470e: fb03 6711 mls r7, r3, r1, r6 + 8014712: 5dc7 ldrb r7, [r0, r7] + 8014714: f805 7d01 strb.w r7, [r5, #-1]! + 8014718: 4637 mov r7, r6 + 801471a: 42bb cmp r3, r7 + 801471c: 460e mov r6, r1 + 801471e: d9f4 bls.n 801470a <_printf_i+0x116> + 8014720: 2b08 cmp r3, #8 + 8014722: d10b bne.n 801473c <_printf_i+0x148> + 8014724: 6823 ldr r3, [r4, #0] + 8014726: 07de lsls r6, r3, #31 + 8014728: d508 bpl.n 801473c <_printf_i+0x148> + 801472a: 6923 ldr r3, [r4, #16] + 801472c: 6861 ldr r1, [r4, #4] + 801472e: 4299 cmp r1, r3 + 8014730: bfde ittt le + 8014732: 2330 movle r3, #48 ; 0x30 + 8014734: f805 3c01 strble.w r3, [r5, #-1] + 8014738: f105 35ff addle.w r5, r5, #4294967295 + 801473c: 1b52 subs r2, r2, r5 + 801473e: 6122 str r2, [r4, #16] + 8014740: f8cd a000 str.w sl, [sp] + 8014744: 464b mov r3, r9 + 8014746: aa03 add r2, sp, #12 + 8014748: 4621 mov r1, r4 + 801474a: 4640 mov r0, r8 + 801474c: f7ff fee4 bl 8014518 <_printf_common> + 8014750: 3001 adds r0, #1 + 8014752: d14a bne.n 80147ea <_printf_i+0x1f6> + 8014754: f04f 30ff mov.w r0, #4294967295 + 8014758: b004 add sp, #16 + 801475a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801475e: 6823 ldr r3, [r4, #0] + 8014760: f043 0320 orr.w r3, r3, #32 + 8014764: 6023 str r3, [r4, #0] + 8014766: 4833 ldr r0, [pc, #204] ; (8014834 <_printf_i+0x240>) + 8014768: 2778 movs r7, #120 ; 0x78 + 801476a: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 801476e: 6823 ldr r3, [r4, #0] + 8014770: 6829 ldr r1, [r5, #0] + 8014772: 061f lsls r7, r3, #24 + 8014774: f851 6b04 ldr.w r6, [r1], #4 + 8014778: d402 bmi.n 8014780 <_printf_i+0x18c> + 801477a: 065f lsls r7, r3, #25 + 801477c: bf48 it mi + 801477e: b2b6 uxthmi r6, r6 + 8014780: 07df lsls r7, r3, #31 + 8014782: bf48 it mi + 8014784: f043 0320 orrmi.w r3, r3, #32 + 8014788: 6029 str r1, [r5, #0] + 801478a: bf48 it mi + 801478c: 6023 strmi r3, [r4, #0] + 801478e: b91e cbnz r6, 8014798 <_printf_i+0x1a4> + 8014790: 6823 ldr r3, [r4, #0] + 8014792: f023 0320 bic.w r3, r3, #32 + 8014796: 6023 str r3, [r4, #0] + 8014798: 2310 movs r3, #16 + 801479a: e7a7 b.n 80146ec <_printf_i+0xf8> + 801479c: 4824 ldr r0, [pc, #144] ; (8014830 <_printf_i+0x23c>) + 801479e: e7e4 b.n 801476a <_printf_i+0x176> + 80147a0: 4615 mov r5, r2 + 80147a2: e7bd b.n 8014720 <_printf_i+0x12c> + 80147a4: 682b ldr r3, [r5, #0] + 80147a6: 6826 ldr r6, [r4, #0] + 80147a8: 6961 ldr r1, [r4, #20] + 80147aa: 1d18 adds r0, r3, #4 + 80147ac: 6028 str r0, [r5, #0] + 80147ae: 0635 lsls r5, r6, #24 + 80147b0: 681b ldr r3, [r3, #0] + 80147b2: d501 bpl.n 80147b8 <_printf_i+0x1c4> + 80147b4: 6019 str r1, [r3, #0] + 80147b6: e002 b.n 80147be <_printf_i+0x1ca> + 80147b8: 0670 lsls r0, r6, #25 + 80147ba: d5fb bpl.n 80147b4 <_printf_i+0x1c0> + 80147bc: 8019 strh r1, [r3, #0] + 80147be: 2300 movs r3, #0 + 80147c0: 6123 str r3, [r4, #16] + 80147c2: 4615 mov r5, r2 + 80147c4: e7bc b.n 8014740 <_printf_i+0x14c> + 80147c6: 682b ldr r3, [r5, #0] + 80147c8: 1d1a adds r2, r3, #4 + 80147ca: 602a str r2, [r5, #0] + 80147cc: 681d ldr r5, [r3, #0] + 80147ce: 6862 ldr r2, [r4, #4] + 80147d0: 2100 movs r1, #0 + 80147d2: 4628 mov r0, r5 + 80147d4: f7eb fcfc bl 80001d0 + 80147d8: b108 cbz r0, 80147de <_printf_i+0x1ea> + 80147da: 1b40 subs r0, r0, r5 + 80147dc: 6060 str r0, [r4, #4] + 80147de: 6863 ldr r3, [r4, #4] + 80147e0: 6123 str r3, [r4, #16] + 80147e2: 2300 movs r3, #0 + 80147e4: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80147e8: e7aa b.n 8014740 <_printf_i+0x14c> + 80147ea: 6923 ldr r3, [r4, #16] + 80147ec: 462a mov r2, r5 + 80147ee: 4649 mov r1, r9 + 80147f0: 4640 mov r0, r8 + 80147f2: 47d0 blx sl + 80147f4: 3001 adds r0, #1 + 80147f6: d0ad beq.n 8014754 <_printf_i+0x160> + 80147f8: 6823 ldr r3, [r4, #0] + 80147fa: 079b lsls r3, r3, #30 + 80147fc: d413 bmi.n 8014826 <_printf_i+0x232> + 80147fe: 68e0 ldr r0, [r4, #12] + 8014800: 9b03 ldr r3, [sp, #12] + 8014802: 4298 cmp r0, r3 + 8014804: bfb8 it lt + 8014806: 4618 movlt r0, r3 + 8014808: e7a6 b.n 8014758 <_printf_i+0x164> + 801480a: 2301 movs r3, #1 + 801480c: 4632 mov r2, r6 + 801480e: 4649 mov r1, r9 + 8014810: 4640 mov r0, r8 + 8014812: 47d0 blx sl + 8014814: 3001 adds r0, #1 + 8014816: d09d beq.n 8014754 <_printf_i+0x160> + 8014818: 3501 adds r5, #1 + 801481a: 68e3 ldr r3, [r4, #12] + 801481c: 9903 ldr r1, [sp, #12] + 801481e: 1a5b subs r3, r3, r1 + 8014820: 42ab cmp r3, r5 + 8014822: dcf2 bgt.n 801480a <_printf_i+0x216> + 8014824: e7eb b.n 80147fe <_printf_i+0x20a> + 8014826: 2500 movs r5, #0 + 8014828: f104 0619 add.w r6, r4, #25 + 801482c: e7f5 b.n 801481a <_printf_i+0x226> + 801482e: bf00 nop + 8014830: 0801ad53 .word 0x0801ad53 + 8014834: 0801ad64 .word 0x0801ad64 + +08014838 <_scanf_float>: + 8014838: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801483c: b087 sub sp, #28 + 801483e: 4617 mov r7, r2 + 8014840: 9303 str r3, [sp, #12] + 8014842: 688b ldr r3, [r1, #8] + 8014844: 1e5a subs r2, r3, #1 + 8014846: f5b2 7fae cmp.w r2, #348 ; 0x15c + 801484a: bf83 ittte hi + 801484c: f46f 75ae mvnhi.w r5, #348 ; 0x15c + 8014850: 195b addhi r3, r3, r5 + 8014852: 9302 strhi r3, [sp, #8] + 8014854: 2300 movls r3, #0 + 8014856: bf86 itte hi + 8014858: f240 135d movwhi r3, #349 ; 0x15d + 801485c: 608b strhi r3, [r1, #8] + 801485e: 9302 strls r3, [sp, #8] + 8014860: 680b ldr r3, [r1, #0] + 8014862: 468b mov fp, r1 + 8014864: 2500 movs r5, #0 + 8014866: f443 63f0 orr.w r3, r3, #1920 ; 0x780 + 801486a: f84b 3b1c str.w r3, [fp], #28 + 801486e: e9cd 5504 strd r5, r5, [sp, #16] + 8014872: 4680 mov r8, r0 + 8014874: 460c mov r4, r1 + 8014876: 465e mov r6, fp + 8014878: 46aa mov sl, r5 + 801487a: 46a9 mov r9, r5 + 801487c: 9501 str r5, [sp, #4] + 801487e: 68a2 ldr r2, [r4, #8] + 8014880: b152 cbz r2, 8014898 <_scanf_float+0x60> + 8014882: 683b ldr r3, [r7, #0] + 8014884: 781b ldrb r3, [r3, #0] + 8014886: 2b4e cmp r3, #78 ; 0x4e + 8014888: d864 bhi.n 8014954 <_scanf_float+0x11c> + 801488a: 2b40 cmp r3, #64 ; 0x40 + 801488c: d83c bhi.n 8014908 <_scanf_float+0xd0> + 801488e: f1a3 012b sub.w r1, r3, #43 ; 0x2b + 8014892: b2c8 uxtb r0, r1 + 8014894: 280e cmp r0, #14 + 8014896: d93a bls.n 801490e <_scanf_float+0xd6> + 8014898: f1b9 0f00 cmp.w r9, #0 + 801489c: d003 beq.n 80148a6 <_scanf_float+0x6e> + 801489e: 6823 ldr r3, [r4, #0] + 80148a0: f423 7380 bic.w r3, r3, #256 ; 0x100 + 80148a4: 6023 str r3, [r4, #0] + 80148a6: f10a 3aff add.w sl, sl, #4294967295 + 80148aa: f1ba 0f01 cmp.w sl, #1 + 80148ae: f200 8113 bhi.w 8014ad8 <_scanf_float+0x2a0> + 80148b2: 455e cmp r6, fp + 80148b4: f200 8105 bhi.w 8014ac2 <_scanf_float+0x28a> + 80148b8: 2501 movs r5, #1 + 80148ba: 4628 mov r0, r5 + 80148bc: b007 add sp, #28 + 80148be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80148c2: f1a3 0261 sub.w r2, r3, #97 ; 0x61 + 80148c6: 2a0d cmp r2, #13 + 80148c8: d8e6 bhi.n 8014898 <_scanf_float+0x60> + 80148ca: a101 add r1, pc, #4 ; (adr r1, 80148d0 <_scanf_float+0x98>) + 80148cc: f851 f022 ldr.w pc, [r1, r2, lsl #2] + 80148d0: 08014a0f .word 0x08014a0f + 80148d4: 08014899 .word 0x08014899 + 80148d8: 08014899 .word 0x08014899 + 80148dc: 08014899 .word 0x08014899 + 80148e0: 08014a6f .word 0x08014a6f + 80148e4: 08014a47 .word 0x08014a47 + 80148e8: 08014899 .word 0x08014899 + 80148ec: 08014899 .word 0x08014899 + 80148f0: 08014a1d .word 0x08014a1d + 80148f4: 08014899 .word 0x08014899 + 80148f8: 08014899 .word 0x08014899 + 80148fc: 08014899 .word 0x08014899 + 8014900: 08014899 .word 0x08014899 + 8014904: 080149d5 .word 0x080149d5 + 8014908: f1a3 0241 sub.w r2, r3, #65 ; 0x41 + 801490c: e7db b.n 80148c6 <_scanf_float+0x8e> + 801490e: 290e cmp r1, #14 + 8014910: d8c2 bhi.n 8014898 <_scanf_float+0x60> + 8014912: a001 add r0, pc, #4 ; (adr r0, 8014918 <_scanf_float+0xe0>) + 8014914: f850 f021 ldr.w pc, [r0, r1, lsl #2] + 8014918: 080149c7 .word 0x080149c7 + 801491c: 08014899 .word 0x08014899 + 8014920: 080149c7 .word 0x080149c7 + 8014924: 08014a5b .word 0x08014a5b + 8014928: 08014899 .word 0x08014899 + 801492c: 08014975 .word 0x08014975 + 8014930: 080149b1 .word 0x080149b1 + 8014934: 080149b1 .word 0x080149b1 + 8014938: 080149b1 .word 0x080149b1 + 801493c: 080149b1 .word 0x080149b1 + 8014940: 080149b1 .word 0x080149b1 + 8014944: 080149b1 .word 0x080149b1 + 8014948: 080149b1 .word 0x080149b1 + 801494c: 080149b1 .word 0x080149b1 + 8014950: 080149b1 .word 0x080149b1 + 8014954: 2b6e cmp r3, #110 ; 0x6e + 8014956: d809 bhi.n 801496c <_scanf_float+0x134> + 8014958: 2b60 cmp r3, #96 ; 0x60 + 801495a: d8b2 bhi.n 80148c2 <_scanf_float+0x8a> + 801495c: 2b54 cmp r3, #84 ; 0x54 + 801495e: d077 beq.n 8014a50 <_scanf_float+0x218> + 8014960: 2b59 cmp r3, #89 ; 0x59 + 8014962: d199 bne.n 8014898 <_scanf_float+0x60> + 8014964: 2d07 cmp r5, #7 + 8014966: d197 bne.n 8014898 <_scanf_float+0x60> + 8014968: 2508 movs r5, #8 + 801496a: e029 b.n 80149c0 <_scanf_float+0x188> + 801496c: 2b74 cmp r3, #116 ; 0x74 + 801496e: d06f beq.n 8014a50 <_scanf_float+0x218> + 8014970: 2b79 cmp r3, #121 ; 0x79 + 8014972: e7f6 b.n 8014962 <_scanf_float+0x12a> + 8014974: 6821 ldr r1, [r4, #0] + 8014976: 05c8 lsls r0, r1, #23 + 8014978: d51a bpl.n 80149b0 <_scanf_float+0x178> + 801497a: 9b02 ldr r3, [sp, #8] + 801497c: f021 0180 bic.w r1, r1, #128 ; 0x80 + 8014980: 6021 str r1, [r4, #0] + 8014982: f109 0901 add.w r9, r9, #1 + 8014986: b11b cbz r3, 8014990 <_scanf_float+0x158> + 8014988: 3b01 subs r3, #1 + 801498a: 3201 adds r2, #1 + 801498c: 9302 str r3, [sp, #8] + 801498e: 60a2 str r2, [r4, #8] + 8014990: 68a3 ldr r3, [r4, #8] + 8014992: 3b01 subs r3, #1 + 8014994: 60a3 str r3, [r4, #8] + 8014996: 6923 ldr r3, [r4, #16] + 8014998: 3301 adds r3, #1 + 801499a: 6123 str r3, [r4, #16] + 801499c: 687b ldr r3, [r7, #4] + 801499e: 3b01 subs r3, #1 + 80149a0: 2b00 cmp r3, #0 + 80149a2: 607b str r3, [r7, #4] + 80149a4: f340 8084 ble.w 8014ab0 <_scanf_float+0x278> + 80149a8: 683b ldr r3, [r7, #0] + 80149aa: 3301 adds r3, #1 + 80149ac: 603b str r3, [r7, #0] + 80149ae: e766 b.n 801487e <_scanf_float+0x46> + 80149b0: eb1a 0f05 cmn.w sl, r5 + 80149b4: f47f af70 bne.w 8014898 <_scanf_float+0x60> + 80149b8: 6822 ldr r2, [r4, #0] + 80149ba: f422 72c0 bic.w r2, r2, #384 ; 0x180 + 80149be: 6022 str r2, [r4, #0] + 80149c0: f806 3b01 strb.w r3, [r6], #1 + 80149c4: e7e4 b.n 8014990 <_scanf_float+0x158> + 80149c6: 6822 ldr r2, [r4, #0] + 80149c8: 0610 lsls r0, r2, #24 + 80149ca: f57f af65 bpl.w 8014898 <_scanf_float+0x60> + 80149ce: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80149d2: e7f4 b.n 80149be <_scanf_float+0x186> + 80149d4: f1ba 0f00 cmp.w sl, #0 + 80149d8: d10e bne.n 80149f8 <_scanf_float+0x1c0> + 80149da: f1b9 0f00 cmp.w r9, #0 + 80149de: d10e bne.n 80149fe <_scanf_float+0x1c6> + 80149e0: 6822 ldr r2, [r4, #0] + 80149e2: f402 61e0 and.w r1, r2, #1792 ; 0x700 + 80149e6: f5b1 6fe0 cmp.w r1, #1792 ; 0x700 + 80149ea: d108 bne.n 80149fe <_scanf_float+0x1c6> + 80149ec: f422 62f0 bic.w r2, r2, #1920 ; 0x780 + 80149f0: 6022 str r2, [r4, #0] + 80149f2: f04f 0a01 mov.w sl, #1 + 80149f6: e7e3 b.n 80149c0 <_scanf_float+0x188> + 80149f8: f1ba 0f02 cmp.w sl, #2 + 80149fc: d055 beq.n 8014aaa <_scanf_float+0x272> + 80149fe: 2d01 cmp r5, #1 + 8014a00: d002 beq.n 8014a08 <_scanf_float+0x1d0> + 8014a02: 2d04 cmp r5, #4 + 8014a04: f47f af48 bne.w 8014898 <_scanf_float+0x60> + 8014a08: 3501 adds r5, #1 + 8014a0a: b2ed uxtb r5, r5 + 8014a0c: e7d8 b.n 80149c0 <_scanf_float+0x188> + 8014a0e: f1ba 0f01 cmp.w sl, #1 + 8014a12: f47f af41 bne.w 8014898 <_scanf_float+0x60> + 8014a16: f04f 0a02 mov.w sl, #2 + 8014a1a: e7d1 b.n 80149c0 <_scanf_float+0x188> + 8014a1c: b97d cbnz r5, 8014a3e <_scanf_float+0x206> + 8014a1e: f1b9 0f00 cmp.w r9, #0 + 8014a22: f47f af3c bne.w 801489e <_scanf_float+0x66> + 8014a26: 6822 ldr r2, [r4, #0] + 8014a28: f402 61e0 and.w r1, r2, #1792 ; 0x700 + 8014a2c: f5b1 6fe0 cmp.w r1, #1792 ; 0x700 + 8014a30: f47f af39 bne.w 80148a6 <_scanf_float+0x6e> + 8014a34: f422 62f0 bic.w r2, r2, #1920 ; 0x780 + 8014a38: 6022 str r2, [r4, #0] + 8014a3a: 2501 movs r5, #1 + 8014a3c: e7c0 b.n 80149c0 <_scanf_float+0x188> + 8014a3e: 2d03 cmp r5, #3 + 8014a40: d0e2 beq.n 8014a08 <_scanf_float+0x1d0> + 8014a42: 2d05 cmp r5, #5 + 8014a44: e7de b.n 8014a04 <_scanf_float+0x1cc> + 8014a46: 2d02 cmp r5, #2 + 8014a48: f47f af26 bne.w 8014898 <_scanf_float+0x60> + 8014a4c: 2503 movs r5, #3 + 8014a4e: e7b7 b.n 80149c0 <_scanf_float+0x188> + 8014a50: 2d06 cmp r5, #6 + 8014a52: f47f af21 bne.w 8014898 <_scanf_float+0x60> + 8014a56: 2507 movs r5, #7 + 8014a58: e7b2 b.n 80149c0 <_scanf_float+0x188> + 8014a5a: 6822 ldr r2, [r4, #0] + 8014a5c: 0591 lsls r1, r2, #22 + 8014a5e: f57f af1b bpl.w 8014898 <_scanf_float+0x60> + 8014a62: f422 7220 bic.w r2, r2, #640 ; 0x280 + 8014a66: 6022 str r2, [r4, #0] + 8014a68: f8cd 9004 str.w r9, [sp, #4] + 8014a6c: e7a8 b.n 80149c0 <_scanf_float+0x188> + 8014a6e: 6822 ldr r2, [r4, #0] + 8014a70: f402 61a0 and.w r1, r2, #1280 ; 0x500 + 8014a74: f5b1 6f80 cmp.w r1, #1024 ; 0x400 + 8014a78: d006 beq.n 8014a88 <_scanf_float+0x250> + 8014a7a: 0550 lsls r0, r2, #21 + 8014a7c: f57f af0c bpl.w 8014898 <_scanf_float+0x60> + 8014a80: f1b9 0f00 cmp.w r9, #0 + 8014a84: f43f af0f beq.w 80148a6 <_scanf_float+0x6e> + 8014a88: 0591 lsls r1, r2, #22 + 8014a8a: bf58 it pl + 8014a8c: 9901 ldrpl r1, [sp, #4] + 8014a8e: f422 62f0 bic.w r2, r2, #1920 ; 0x780 + 8014a92: bf58 it pl + 8014a94: eba9 0101 subpl.w r1, r9, r1 + 8014a98: f442 72c0 orr.w r2, r2, #384 ; 0x180 + 8014a9c: bf58 it pl + 8014a9e: e9cd 1604 strdpl r1, r6, [sp, #16] + 8014aa2: 6022 str r2, [r4, #0] + 8014aa4: f04f 0900 mov.w r9, #0 + 8014aa8: e78a b.n 80149c0 <_scanf_float+0x188> + 8014aaa: f04f 0a03 mov.w sl, #3 + 8014aae: e787 b.n 80149c0 <_scanf_float+0x188> + 8014ab0: f8d4 3180 ldr.w r3, [r4, #384] ; 0x180 + 8014ab4: 4639 mov r1, r7 + 8014ab6: 4640 mov r0, r8 + 8014ab8: 4798 blx r3 + 8014aba: 2800 cmp r0, #0 + 8014abc: f43f aedf beq.w 801487e <_scanf_float+0x46> + 8014ac0: e6ea b.n 8014898 <_scanf_float+0x60> + 8014ac2: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014ac6: f816 1d01 ldrb.w r1, [r6, #-1]! + 8014aca: 463a mov r2, r7 + 8014acc: 4640 mov r0, r8 + 8014ace: 4798 blx r3 + 8014ad0: 6923 ldr r3, [r4, #16] + 8014ad2: 3b01 subs r3, #1 + 8014ad4: 6123 str r3, [r4, #16] + 8014ad6: e6ec b.n 80148b2 <_scanf_float+0x7a> + 8014ad8: 1e6b subs r3, r5, #1 + 8014ada: 2b06 cmp r3, #6 + 8014adc: d825 bhi.n 8014b2a <_scanf_float+0x2f2> + 8014ade: 2d02 cmp r5, #2 + 8014ae0: d836 bhi.n 8014b50 <_scanf_float+0x318> + 8014ae2: 455e cmp r6, fp + 8014ae4: f67f aee8 bls.w 80148b8 <_scanf_float+0x80> + 8014ae8: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014aec: f816 1d01 ldrb.w r1, [r6, #-1]! + 8014af0: 463a mov r2, r7 + 8014af2: 4640 mov r0, r8 + 8014af4: 4798 blx r3 + 8014af6: 6923 ldr r3, [r4, #16] + 8014af8: 3b01 subs r3, #1 + 8014afa: 6123 str r3, [r4, #16] + 8014afc: e7f1 b.n 8014ae2 <_scanf_float+0x2aa> + 8014afe: 9802 ldr r0, [sp, #8] + 8014b00: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014b04: f810 1d01 ldrb.w r1, [r0, #-1]! + 8014b08: 9002 str r0, [sp, #8] + 8014b0a: 463a mov r2, r7 + 8014b0c: 4640 mov r0, r8 + 8014b0e: 4798 blx r3 + 8014b10: 6923 ldr r3, [r4, #16] + 8014b12: 3b01 subs r3, #1 + 8014b14: 6123 str r3, [r4, #16] + 8014b16: f10a 3aff add.w sl, sl, #4294967295 + 8014b1a: fa5f fa8a uxtb.w sl, sl + 8014b1e: f1ba 0f02 cmp.w sl, #2 + 8014b22: d1ec bne.n 8014afe <_scanf_float+0x2c6> + 8014b24: 3d03 subs r5, #3 + 8014b26: b2ed uxtb r5, r5 + 8014b28: 1b76 subs r6, r6, r5 + 8014b2a: 6823 ldr r3, [r4, #0] + 8014b2c: 05da lsls r2, r3, #23 + 8014b2e: d52f bpl.n 8014b90 <_scanf_float+0x358> + 8014b30: 055b lsls r3, r3, #21 + 8014b32: d510 bpl.n 8014b56 <_scanf_float+0x31e> + 8014b34: 455e cmp r6, fp + 8014b36: f67f aebf bls.w 80148b8 <_scanf_float+0x80> + 8014b3a: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014b3e: f816 1d01 ldrb.w r1, [r6, #-1]! + 8014b42: 463a mov r2, r7 + 8014b44: 4640 mov r0, r8 + 8014b46: 4798 blx r3 + 8014b48: 6923 ldr r3, [r4, #16] + 8014b4a: 3b01 subs r3, #1 + 8014b4c: 6123 str r3, [r4, #16] + 8014b4e: e7f1 b.n 8014b34 <_scanf_float+0x2fc> + 8014b50: 46aa mov sl, r5 + 8014b52: 9602 str r6, [sp, #8] + 8014b54: e7df b.n 8014b16 <_scanf_float+0x2de> + 8014b56: f816 1c01 ldrb.w r1, [r6, #-1] + 8014b5a: 6923 ldr r3, [r4, #16] + 8014b5c: 2965 cmp r1, #101 ; 0x65 + 8014b5e: f103 33ff add.w r3, r3, #4294967295 + 8014b62: f106 35ff add.w r5, r6, #4294967295 + 8014b66: 6123 str r3, [r4, #16] + 8014b68: d00c beq.n 8014b84 <_scanf_float+0x34c> + 8014b6a: 2945 cmp r1, #69 ; 0x45 + 8014b6c: d00a beq.n 8014b84 <_scanf_float+0x34c> + 8014b6e: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014b72: 463a mov r2, r7 + 8014b74: 4640 mov r0, r8 + 8014b76: 4798 blx r3 + 8014b78: 6923 ldr r3, [r4, #16] + 8014b7a: f816 1c02 ldrb.w r1, [r6, #-2] + 8014b7e: 3b01 subs r3, #1 + 8014b80: 1eb5 subs r5, r6, #2 + 8014b82: 6123 str r3, [r4, #16] + 8014b84: f8d4 317c ldr.w r3, [r4, #380] ; 0x17c + 8014b88: 463a mov r2, r7 + 8014b8a: 4640 mov r0, r8 + 8014b8c: 4798 blx r3 + 8014b8e: 462e mov r6, r5 + 8014b90: 6825 ldr r5, [r4, #0] + 8014b92: f015 0510 ands.w r5, r5, #16 + 8014b96: d158 bne.n 8014c4a <_scanf_float+0x412> + 8014b98: 7035 strb r5, [r6, #0] + 8014b9a: 6823 ldr r3, [r4, #0] + 8014b9c: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8014ba0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8014ba4: d11c bne.n 8014be0 <_scanf_float+0x3a8> + 8014ba6: 9b01 ldr r3, [sp, #4] + 8014ba8: 454b cmp r3, r9 + 8014baa: eba3 0209 sub.w r2, r3, r9 + 8014bae: d124 bne.n 8014bfa <_scanf_float+0x3c2> + 8014bb0: 2200 movs r2, #0 + 8014bb2: 4659 mov r1, fp + 8014bb4: 4640 mov r0, r8 + 8014bb6: f7ff f8df bl 8013d78 <_strtod_r> + 8014bba: 9b03 ldr r3, [sp, #12] + 8014bbc: 6821 ldr r1, [r4, #0] + 8014bbe: 681b ldr r3, [r3, #0] + 8014bc0: f011 0f02 tst.w r1, #2 + 8014bc4: ec57 6b10 vmov r6, r7, d0 + 8014bc8: f103 0204 add.w r2, r3, #4 + 8014bcc: d020 beq.n 8014c10 <_scanf_float+0x3d8> + 8014bce: 9903 ldr r1, [sp, #12] + 8014bd0: 600a str r2, [r1, #0] + 8014bd2: 681b ldr r3, [r3, #0] + 8014bd4: e9c3 6700 strd r6, r7, [r3] + 8014bd8: 68e3 ldr r3, [r4, #12] + 8014bda: 3301 adds r3, #1 + 8014bdc: 60e3 str r3, [r4, #12] + 8014bde: e66c b.n 80148ba <_scanf_float+0x82> + 8014be0: 9b04 ldr r3, [sp, #16] + 8014be2: 2b00 cmp r3, #0 + 8014be4: d0e4 beq.n 8014bb0 <_scanf_float+0x378> + 8014be6: 9905 ldr r1, [sp, #20] + 8014be8: 230a movs r3, #10 + 8014bea: 462a mov r2, r5 + 8014bec: 3101 adds r1, #1 + 8014bee: 4640 mov r0, r8 + 8014bf0: f7ff f9b0 bl 8013f54 <_strtol_r> + 8014bf4: 9b04 ldr r3, [sp, #16] + 8014bf6: 9e05 ldr r6, [sp, #20] + 8014bf8: 1ac2 subs r2, r0, r3 + 8014bfa: f204 136f addw r3, r4, #367 ; 0x16f + 8014bfe: 429e cmp r6, r3 + 8014c00: bf28 it cs + 8014c02: f504 76b7 addcs.w r6, r4, #366 ; 0x16e + 8014c06: 4912 ldr r1, [pc, #72] ; (8014c50 <_scanf_float+0x418>) + 8014c08: 4630 mov r0, r6 + 8014c0a: f000 f91b bl 8014e44 + 8014c0e: e7cf b.n 8014bb0 <_scanf_float+0x378> + 8014c10: f011 0f04 tst.w r1, #4 + 8014c14: 9903 ldr r1, [sp, #12] + 8014c16: 600a str r2, [r1, #0] + 8014c18: d1db bne.n 8014bd2 <_scanf_float+0x39a> + 8014c1a: f8d3 8000 ldr.w r8, [r3] + 8014c1e: ee10 2a10 vmov r2, s0 + 8014c22: ee10 0a10 vmov r0, s0 + 8014c26: 463b mov r3, r7 + 8014c28: 4639 mov r1, r7 + 8014c2a: f7eb ff7f bl 8000b2c <__aeabi_dcmpun> + 8014c2e: b128 cbz r0, 8014c3c <_scanf_float+0x404> + 8014c30: 4808 ldr r0, [pc, #32] ; (8014c54 <_scanf_float+0x41c>) + 8014c32: f000 fa9d bl 8015170 + 8014c36: ed88 0a00 vstr s0, [r8] + 8014c3a: e7cd b.n 8014bd8 <_scanf_float+0x3a0> + 8014c3c: 4630 mov r0, r6 + 8014c3e: 4639 mov r1, r7 + 8014c40: f7eb ffd2 bl 8000be8 <__aeabi_d2f> + 8014c44: f8c8 0000 str.w r0, [r8] + 8014c48: e7c6 b.n 8014bd8 <_scanf_float+0x3a0> + 8014c4a: 2500 movs r5, #0 + 8014c4c: e635 b.n 80148ba <_scanf_float+0x82> + 8014c4e: bf00 nop + 8014c50: 0801ad75 .word 0x0801ad75 + 8014c54: 0801ae2e .word 0x0801ae2e + +08014c58 : + 8014c58: 2300 movs r3, #0 + 8014c5a: b510 push {r4, lr} + 8014c5c: 4604 mov r4, r0 + 8014c5e: e9c0 3300 strd r3, r3, [r0] + 8014c62: e9c0 3304 strd r3, r3, [r0, #16] + 8014c66: 6083 str r3, [r0, #8] + 8014c68: 8181 strh r1, [r0, #12] + 8014c6a: 6643 str r3, [r0, #100] ; 0x64 + 8014c6c: 81c2 strh r2, [r0, #14] + 8014c6e: 6183 str r3, [r0, #24] + 8014c70: 4619 mov r1, r3 + 8014c72: 2208 movs r2, #8 + 8014c74: 305c adds r0, #92 ; 0x5c + 8014c76: f000 f948 bl 8014f0a + 8014c7a: 4b0d ldr r3, [pc, #52] ; (8014cb0 ) + 8014c7c: 6263 str r3, [r4, #36] ; 0x24 + 8014c7e: 4b0d ldr r3, [pc, #52] ; (8014cb4 ) + 8014c80: 62a3 str r3, [r4, #40] ; 0x28 + 8014c82: 4b0d ldr r3, [pc, #52] ; (8014cb8 ) + 8014c84: 62e3 str r3, [r4, #44] ; 0x2c + 8014c86: 4b0d ldr r3, [pc, #52] ; (8014cbc ) + 8014c88: 6323 str r3, [r4, #48] ; 0x30 + 8014c8a: 4b0d ldr r3, [pc, #52] ; (8014cc0 ) + 8014c8c: 6224 str r4, [r4, #32] + 8014c8e: 429c cmp r4, r3 + 8014c90: d006 beq.n 8014ca0 + 8014c92: f103 0268 add.w r2, r3, #104 ; 0x68 + 8014c96: 4294 cmp r4, r2 + 8014c98: d002 beq.n 8014ca0 + 8014c9a: 33d0 adds r3, #208 ; 0xd0 + 8014c9c: 429c cmp r4, r3 + 8014c9e: d105 bne.n 8014cac + 8014ca0: f104 0058 add.w r0, r4, #88 ; 0x58 + 8014ca4: e8bd 4010 ldmia.w sp!, {r4, lr} + 8014ca8: f000 ba40 b.w 801512c <__retarget_lock_init_recursive> + 8014cac: bd10 pop {r4, pc} + 8014cae: bf00 nop + 8014cb0: 08014e85 .word 0x08014e85 + 8014cb4: 08014ea7 .word 0x08014ea7 + 8014cb8: 08014edf .word 0x08014edf + 8014cbc: 08014f03 .word 0x08014f03 + 8014cc0: 2000224c .word 0x2000224c + +08014cc4 : + 8014cc4: 4a02 ldr r2, [pc, #8] ; (8014cd0 ) + 8014cc6: 4903 ldr r1, [pc, #12] ; (8014cd4 ) + 8014cc8: 4803 ldr r0, [pc, #12] ; (8014cd8 ) + 8014cca: f000 b869 b.w 8014da0 <_fwalk_sglue> + 8014cce: bf00 nop + 8014cd0: 2000012c .word 0x2000012c + 8014cd4: 08017349 .word 0x08017349 + 8014cd8: 200002a4 .word 0x200002a4 + +08014cdc : + 8014cdc: 6841 ldr r1, [r0, #4] + 8014cde: 4b0c ldr r3, [pc, #48] ; (8014d10 ) + 8014ce0: 4299 cmp r1, r3 + 8014ce2: b510 push {r4, lr} + 8014ce4: 4604 mov r4, r0 + 8014ce6: d001 beq.n 8014cec + 8014ce8: f002 fb2e bl 8017348 <_fflush_r> + 8014cec: 68a1 ldr r1, [r4, #8] + 8014cee: 4b09 ldr r3, [pc, #36] ; (8014d14 ) + 8014cf0: 4299 cmp r1, r3 + 8014cf2: d002 beq.n 8014cfa + 8014cf4: 4620 mov r0, r4 + 8014cf6: f002 fb27 bl 8017348 <_fflush_r> + 8014cfa: 68e1 ldr r1, [r4, #12] + 8014cfc: 4b06 ldr r3, [pc, #24] ; (8014d18 ) + 8014cfe: 4299 cmp r1, r3 + 8014d00: d004 beq.n 8014d0c + 8014d02: 4620 mov r0, r4 + 8014d04: e8bd 4010 ldmia.w sp!, {r4, lr} + 8014d08: f002 bb1e b.w 8017348 <_fflush_r> + 8014d0c: bd10 pop {r4, pc} + 8014d0e: bf00 nop + 8014d10: 2000224c .word 0x2000224c + 8014d14: 200022b4 .word 0x200022b4 + 8014d18: 2000231c .word 0x2000231c + +08014d1c : + 8014d1c: b510 push {r4, lr} + 8014d1e: 4b0b ldr r3, [pc, #44] ; (8014d4c ) + 8014d20: 4c0b ldr r4, [pc, #44] ; (8014d50 ) + 8014d22: 4a0c ldr r2, [pc, #48] ; (8014d54 ) + 8014d24: 601a str r2, [r3, #0] + 8014d26: 4620 mov r0, r4 + 8014d28: 2200 movs r2, #0 + 8014d2a: 2104 movs r1, #4 + 8014d2c: f7ff ff94 bl 8014c58 + 8014d30: f104 0068 add.w r0, r4, #104 ; 0x68 + 8014d34: 2201 movs r2, #1 + 8014d36: 2109 movs r1, #9 + 8014d38: f7ff ff8e bl 8014c58 + 8014d3c: f104 00d0 add.w r0, r4, #208 ; 0xd0 + 8014d40: 2202 movs r2, #2 + 8014d42: e8bd 4010 ldmia.w sp!, {r4, lr} + 8014d46: 2112 movs r1, #18 + 8014d48: f7ff bf86 b.w 8014c58 + 8014d4c: 20002384 .word 0x20002384 + 8014d50: 2000224c .word 0x2000224c + 8014d54: 08014cc5 .word 0x08014cc5 + +08014d58 <__sfp_lock_acquire>: + 8014d58: 4801 ldr r0, [pc, #4] ; (8014d60 <__sfp_lock_acquire+0x8>) + 8014d5a: f000 b9e8 b.w 801512e <__retarget_lock_acquire_recursive> + 8014d5e: bf00 nop + 8014d60: 2000238d .word 0x2000238d + +08014d64 <__sfp_lock_release>: + 8014d64: 4801 ldr r0, [pc, #4] ; (8014d6c <__sfp_lock_release+0x8>) + 8014d66: f000 b9e3 b.w 8015130 <__retarget_lock_release_recursive> + 8014d6a: bf00 nop + 8014d6c: 2000238d .word 0x2000238d + +08014d70 <__sinit>: + 8014d70: b510 push {r4, lr} + 8014d72: 4604 mov r4, r0 + 8014d74: f7ff fff0 bl 8014d58 <__sfp_lock_acquire> + 8014d78: 6a23 ldr r3, [r4, #32] + 8014d7a: b11b cbz r3, 8014d84 <__sinit+0x14> + 8014d7c: e8bd 4010 ldmia.w sp!, {r4, lr} + 8014d80: f7ff bff0 b.w 8014d64 <__sfp_lock_release> + 8014d84: 4b04 ldr r3, [pc, #16] ; (8014d98 <__sinit+0x28>) + 8014d86: 6223 str r3, [r4, #32] + 8014d88: 4b04 ldr r3, [pc, #16] ; (8014d9c <__sinit+0x2c>) + 8014d8a: 681b ldr r3, [r3, #0] + 8014d8c: 2b00 cmp r3, #0 + 8014d8e: d1f5 bne.n 8014d7c <__sinit+0xc> + 8014d90: f7ff ffc4 bl 8014d1c + 8014d94: e7f2 b.n 8014d7c <__sinit+0xc> + 8014d96: bf00 nop + 8014d98: 08014cdd .word 0x08014cdd + 8014d9c: 20002384 .word 0x20002384 + +08014da0 <_fwalk_sglue>: + 8014da0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8014da4: 4607 mov r7, r0 + 8014da6: 4688 mov r8, r1 + 8014da8: 4614 mov r4, r2 + 8014daa: 2600 movs r6, #0 + 8014dac: e9d4 9501 ldrd r9, r5, [r4, #4] + 8014db0: f1b9 0901 subs.w r9, r9, #1 + 8014db4: d505 bpl.n 8014dc2 <_fwalk_sglue+0x22> + 8014db6: 6824 ldr r4, [r4, #0] + 8014db8: 2c00 cmp r4, #0 + 8014dba: d1f7 bne.n 8014dac <_fwalk_sglue+0xc> + 8014dbc: 4630 mov r0, r6 + 8014dbe: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8014dc2: 89ab ldrh r3, [r5, #12] + 8014dc4: 2b01 cmp r3, #1 + 8014dc6: d907 bls.n 8014dd8 <_fwalk_sglue+0x38> + 8014dc8: f9b5 300e ldrsh.w r3, [r5, #14] + 8014dcc: 3301 adds r3, #1 + 8014dce: d003 beq.n 8014dd8 <_fwalk_sglue+0x38> + 8014dd0: 4629 mov r1, r5 + 8014dd2: 4638 mov r0, r7 + 8014dd4: 47c0 blx r8 + 8014dd6: 4306 orrs r6, r0 + 8014dd8: 3568 adds r5, #104 ; 0x68 + 8014dda: e7e9 b.n 8014db0 <_fwalk_sglue+0x10> + +08014ddc : + 8014ddc: b40c push {r2, r3} + 8014dde: b530 push {r4, r5, lr} + 8014de0: 4b17 ldr r3, [pc, #92] ; (8014e40 ) + 8014de2: 1e0c subs r4, r1, #0 + 8014de4: 681d ldr r5, [r3, #0] + 8014de6: b09d sub sp, #116 ; 0x74 + 8014de8: da08 bge.n 8014dfc + 8014dea: 238b movs r3, #139 ; 0x8b + 8014dec: 602b str r3, [r5, #0] + 8014dee: f04f 30ff mov.w r0, #4294967295 + 8014df2: b01d add sp, #116 ; 0x74 + 8014df4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8014df8: b002 add sp, #8 + 8014dfa: 4770 bx lr + 8014dfc: f44f 7302 mov.w r3, #520 ; 0x208 + 8014e00: f8ad 3014 strh.w r3, [sp, #20] + 8014e04: bf14 ite ne + 8014e06: f104 33ff addne.w r3, r4, #4294967295 + 8014e0a: 4623 moveq r3, r4 + 8014e0c: 9304 str r3, [sp, #16] + 8014e0e: 9307 str r3, [sp, #28] + 8014e10: f64f 73ff movw r3, #65535 ; 0xffff + 8014e14: 9002 str r0, [sp, #8] + 8014e16: 9006 str r0, [sp, #24] + 8014e18: f8ad 3016 strh.w r3, [sp, #22] + 8014e1c: 9a20 ldr r2, [sp, #128] ; 0x80 + 8014e1e: ab21 add r3, sp, #132 ; 0x84 + 8014e20: a902 add r1, sp, #8 + 8014e22: 4628 mov r0, r5 + 8014e24: 9301 str r3, [sp, #4] + 8014e26: f002 f90b bl 8017040 <_svfiprintf_r> + 8014e2a: 1c43 adds r3, r0, #1 + 8014e2c: bfbc itt lt + 8014e2e: 238b movlt r3, #139 ; 0x8b + 8014e30: 602b strlt r3, [r5, #0] + 8014e32: 2c00 cmp r4, #0 + 8014e34: d0dd beq.n 8014df2 + 8014e36: 9b02 ldr r3, [sp, #8] + 8014e38: 2200 movs r2, #0 + 8014e3a: 701a strb r2, [r3, #0] + 8014e3c: e7d9 b.n 8014df2 + 8014e3e: bf00 nop + 8014e40: 200002f0 .word 0x200002f0 + +08014e44 : + 8014e44: b40e push {r1, r2, r3} + 8014e46: b500 push {lr} + 8014e48: b09c sub sp, #112 ; 0x70 + 8014e4a: ab1d add r3, sp, #116 ; 0x74 + 8014e4c: 9002 str r0, [sp, #8] + 8014e4e: 9006 str r0, [sp, #24] + 8014e50: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 8014e54: 4809 ldr r0, [pc, #36] ; (8014e7c ) + 8014e56: 9107 str r1, [sp, #28] + 8014e58: 9104 str r1, [sp, #16] + 8014e5a: 4909 ldr r1, [pc, #36] ; (8014e80 ) + 8014e5c: f853 2b04 ldr.w r2, [r3], #4 + 8014e60: 9105 str r1, [sp, #20] + 8014e62: 6800 ldr r0, [r0, #0] + 8014e64: 9301 str r3, [sp, #4] + 8014e66: a902 add r1, sp, #8 + 8014e68: f002 f8ea bl 8017040 <_svfiprintf_r> + 8014e6c: 9b02 ldr r3, [sp, #8] + 8014e6e: 2200 movs r2, #0 + 8014e70: 701a strb r2, [r3, #0] + 8014e72: b01c add sp, #112 ; 0x70 + 8014e74: f85d eb04 ldr.w lr, [sp], #4 + 8014e78: b003 add sp, #12 + 8014e7a: 4770 bx lr + 8014e7c: 200002f0 .word 0x200002f0 + 8014e80: ffff0208 .word 0xffff0208 + +08014e84 <__sread>: + 8014e84: b510 push {r4, lr} + 8014e86: 460c mov r4, r1 + 8014e88: f9b1 100e ldrsh.w r1, [r1, #14] + 8014e8c: f000 f8f0 bl 8015070 <_read_r> + 8014e90: 2800 cmp r0, #0 + 8014e92: bfab itete ge + 8014e94: 6d63 ldrge r3, [r4, #84] ; 0x54 + 8014e96: 89a3 ldrhlt r3, [r4, #12] + 8014e98: 181b addge r3, r3, r0 + 8014e9a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 8014e9e: bfac ite ge + 8014ea0: 6563 strge r3, [r4, #84] ; 0x54 + 8014ea2: 81a3 strhlt r3, [r4, #12] + 8014ea4: bd10 pop {r4, pc} + +08014ea6 <__swrite>: + 8014ea6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8014eaa: 461f mov r7, r3 + 8014eac: 898b ldrh r3, [r1, #12] + 8014eae: 05db lsls r3, r3, #23 + 8014eb0: 4605 mov r5, r0 + 8014eb2: 460c mov r4, r1 + 8014eb4: 4616 mov r6, r2 + 8014eb6: d505 bpl.n 8014ec4 <__swrite+0x1e> + 8014eb8: f9b1 100e ldrsh.w r1, [r1, #14] + 8014ebc: 2302 movs r3, #2 + 8014ebe: 2200 movs r2, #0 + 8014ec0: f000 f8c4 bl 801504c <_lseek_r> + 8014ec4: 89a3 ldrh r3, [r4, #12] + 8014ec6: f9b4 100e ldrsh.w r1, [r4, #14] + 8014eca: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8014ece: 81a3 strh r3, [r4, #12] + 8014ed0: 4632 mov r2, r6 + 8014ed2: 463b mov r3, r7 + 8014ed4: 4628 mov r0, r5 + 8014ed6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8014eda: f000 b8eb b.w 80150b4 <_write_r> + +08014ede <__sseek>: + 8014ede: b510 push {r4, lr} + 8014ee0: 460c mov r4, r1 + 8014ee2: f9b1 100e ldrsh.w r1, [r1, #14] + 8014ee6: f000 f8b1 bl 801504c <_lseek_r> + 8014eea: 1c43 adds r3, r0, #1 + 8014eec: 89a3 ldrh r3, [r4, #12] + 8014eee: bf15 itete ne + 8014ef0: 6560 strne r0, [r4, #84] ; 0x54 + 8014ef2: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 8014ef6: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 8014efa: 81a3 strheq r3, [r4, #12] + 8014efc: bf18 it ne + 8014efe: 81a3 strhne r3, [r4, #12] + 8014f00: bd10 pop {r4, pc} + +08014f02 <__sclose>: + 8014f02: f9b1 100e ldrsh.w r1, [r1, #14] + 8014f06: f000 b891 b.w 801502c <_close_r> + +08014f0a : + 8014f0a: 4402 add r2, r0 + 8014f0c: 4603 mov r3, r0 + 8014f0e: 4293 cmp r3, r2 + 8014f10: d100 bne.n 8014f14 + 8014f12: 4770 bx lr + 8014f14: f803 1b01 strb.w r1, [r3], #1 + 8014f18: e7f9 b.n 8014f0e + +08014f1a : + 8014f1a: b510 push {r4, lr} + 8014f1c: b16a cbz r2, 8014f3a + 8014f1e: 3901 subs r1, #1 + 8014f20: 1884 adds r4, r0, r2 + 8014f22: f810 2b01 ldrb.w r2, [r0], #1 + 8014f26: f811 3f01 ldrb.w r3, [r1, #1]! + 8014f2a: 429a cmp r2, r3 + 8014f2c: d103 bne.n 8014f36 + 8014f2e: 42a0 cmp r0, r4 + 8014f30: d001 beq.n 8014f36 + 8014f32: 2a00 cmp r2, #0 + 8014f34: d1f5 bne.n 8014f22 + 8014f36: 1ad0 subs r0, r2, r3 + 8014f38: bd10 pop {r4, pc} + 8014f3a: 4610 mov r0, r2 + 8014f3c: e7fc b.n 8014f38 ... -08012a90 : - 8012a90: 4b16 ldr r3, [pc, #88] ; (8012aec ) - 8012a92: b573 push {r0, r1, r4, r5, r6, lr} - 8012a94: 681e ldr r6, [r3, #0] - 8012a96: 6c74 ldr r4, [r6, #68] ; 0x44 - 8012a98: 4605 mov r5, r0 - 8012a9a: b9fc cbnz r4, 8012adc - 8012a9c: 2050 movs r0, #80 ; 0x50 - 8012a9e: 9101 str r1, [sp, #4] - 8012aa0: f7fe f848 bl 8010b34 - 8012aa4: 9901 ldr r1, [sp, #4] - 8012aa6: 6470 str r0, [r6, #68] ; 0x44 - 8012aa8: 4602 mov r2, r0 - 8012aaa: b920 cbnz r0, 8012ab6 - 8012aac: 4b10 ldr r3, [pc, #64] ; (8012af0 ) - 8012aae: 4811 ldr r0, [pc, #68] ; (8012af4 ) - 8012ab0: 215b movs r1, #91 ; 0x5b - 8012ab2: f000 f90b bl 8012ccc <__assert_func> - 8012ab6: e9c0 4400 strd r4, r4, [r0] - 8012aba: e9c0 4402 strd r4, r4, [r0, #8] - 8012abe: e9c0 4404 strd r4, r4, [r0, #16] - 8012ac2: e9c0 440a strd r4, r4, [r0, #40] ; 0x28 - 8012ac6: e9c0 440c strd r4, r4, [r0, #48] ; 0x30 - 8012aca: e9c0 440e strd r4, r4, [r0, #56] ; 0x38 - 8012ace: e9c0 4410 strd r4, r4, [r0, #64] ; 0x40 - 8012ad2: e9c0 4412 strd r4, r4, [r0, #72] ; 0x48 - 8012ad6: 6184 str r4, [r0, #24] - 8012ad8: 7704 strb r4, [r0, #28] - 8012ada: 6244 str r4, [r0, #36] ; 0x24 - 8012adc: 6c72 ldr r2, [r6, #68] ; 0x44 - 8012ade: 2301 movs r3, #1 - 8012ae0: 4628 mov r0, r5 - 8012ae2: b002 add sp, #8 - 8012ae4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} - 8012ae8: f000 b806 b.w 8012af8 <__strtok_r> - 8012aec: 20000310 .word 0x20000310 - 8012af0: 080188a2 .word 0x080188a2 - 8012af4: 080188b9 .word 0x080188b9 - -08012af8 <__strtok_r>: - 8012af8: b5f0 push {r4, r5, r6, r7, lr} - 8012afa: b908 cbnz r0, 8012b00 <__strtok_r+0x8> - 8012afc: 6810 ldr r0, [r2, #0] - 8012afe: b188 cbz r0, 8012b24 <__strtok_r+0x2c> - 8012b00: 4604 mov r4, r0 - 8012b02: 4620 mov r0, r4 - 8012b04: f814 5b01 ldrb.w r5, [r4], #1 - 8012b08: 460f mov r7, r1 - 8012b0a: f817 6b01 ldrb.w r6, [r7], #1 - 8012b0e: b91e cbnz r6, 8012b18 <__strtok_r+0x20> - 8012b10: b965 cbnz r5, 8012b2c <__strtok_r+0x34> - 8012b12: 6015 str r5, [r2, #0] - 8012b14: 4628 mov r0, r5 - 8012b16: e005 b.n 8012b24 <__strtok_r+0x2c> - 8012b18: 42b5 cmp r5, r6 - 8012b1a: d1f6 bne.n 8012b0a <__strtok_r+0x12> - 8012b1c: 2b00 cmp r3, #0 - 8012b1e: d1f0 bne.n 8012b02 <__strtok_r+0xa> - 8012b20: 6014 str r4, [r2, #0] - 8012b22: 7003 strb r3, [r0, #0] - 8012b24: bdf0 pop {r4, r5, r6, r7, pc} - 8012b26: 461c mov r4, r3 - 8012b28: e00c b.n 8012b44 <__strtok_r+0x4c> - 8012b2a: b915 cbnz r5, 8012b32 <__strtok_r+0x3a> - 8012b2c: f814 3b01 ldrb.w r3, [r4], #1 - 8012b30: 460e mov r6, r1 - 8012b32: f816 5b01 ldrb.w r5, [r6], #1 - 8012b36: 42ab cmp r3, r5 - 8012b38: d1f7 bne.n 8012b2a <__strtok_r+0x32> - 8012b3a: 2b00 cmp r3, #0 - 8012b3c: d0f3 beq.n 8012b26 <__strtok_r+0x2e> - 8012b3e: 2300 movs r3, #0 - 8012b40: f804 3c01 strb.w r3, [r4, #-1] - 8012b44: 6014 str r4, [r2, #0] - 8012b46: e7ed b.n 8012b24 <__strtok_r+0x2c> - -08012b48 : - 8012b48: 780a ldrb r2, [r1, #0] - 8012b4a: b570 push {r4, r5, r6, lr} - 8012b4c: b96a cbnz r2, 8012b6a - 8012b4e: bd70 pop {r4, r5, r6, pc} - 8012b50: 429a cmp r2, r3 - 8012b52: d109 bne.n 8012b68 - 8012b54: 460c mov r4, r1 - 8012b56: 4605 mov r5, r0 - 8012b58: f814 3f01 ldrb.w r3, [r4, #1]! - 8012b5c: 2b00 cmp r3, #0 - 8012b5e: d0f6 beq.n 8012b4e - 8012b60: f815 6f01 ldrb.w r6, [r5, #1]! - 8012b64: 429e cmp r6, r3 - 8012b66: d0f7 beq.n 8012b58 - 8012b68: 3001 adds r0, #1 - 8012b6a: 7803 ldrb r3, [r0, #0] - 8012b6c: 2b00 cmp r3, #0 - 8012b6e: d1ef bne.n 8012b50 - 8012b70: 4618 mov r0, r3 - 8012b72: e7ec b.n 8012b4e - -08012b74 <_localeconv_r>: - 8012b74: 4800 ldr r0, [pc, #0] ; (8012b78 <_localeconv_r+0x4>) - 8012b76: 4770 bx lr - 8012b78: 20000248 .word 0x20000248 - -08012b7c <_close_r>: - 8012b7c: b538 push {r3, r4, r5, lr} - 8012b7e: 4d06 ldr r5, [pc, #24] ; (8012b98 <_close_r+0x1c>) - 8012b80: 2300 movs r3, #0 - 8012b82: 4604 mov r4, r0 - 8012b84: 4608 mov r0, r1 - 8012b86: 602b str r3, [r5, #0] - 8012b88: f7f1 fc09 bl 800439e <_close> - 8012b8c: 1c43 adds r3, r0, #1 - 8012b8e: d102 bne.n 8012b96 <_close_r+0x1a> - 8012b90: 682b ldr r3, [r5, #0] - 8012b92: b103 cbz r3, 8012b96 <_close_r+0x1a> - 8012b94: 6023 str r3, [r4, #0] - 8012b96: bd38 pop {r3, r4, r5, pc} - 8012b98: 200015d0 .word 0x200015d0 - -08012b9c <_lseek_r>: - 8012b9c: b538 push {r3, r4, r5, lr} - 8012b9e: 4d07 ldr r5, [pc, #28] ; (8012bbc <_lseek_r+0x20>) - 8012ba0: 4604 mov r4, r0 - 8012ba2: 4608 mov r0, r1 - 8012ba4: 4611 mov r1, r2 - 8012ba6: 2200 movs r2, #0 - 8012ba8: 602a str r2, [r5, #0] - 8012baa: 461a mov r2, r3 - 8012bac: f7f1 fc1e bl 80043ec <_lseek> - 8012bb0: 1c43 adds r3, r0, #1 - 8012bb2: d102 bne.n 8012bba <_lseek_r+0x1e> - 8012bb4: 682b ldr r3, [r5, #0] - 8012bb6: b103 cbz r3, 8012bba <_lseek_r+0x1e> - 8012bb8: 6023 str r3, [r4, #0] - 8012bba: bd38 pop {r3, r4, r5, pc} - 8012bbc: 200015d0 .word 0x200015d0 - -08012bc0 <_read_r>: - 8012bc0: b538 push {r3, r4, r5, lr} - 8012bc2: 4d07 ldr r5, [pc, #28] ; (8012be0 <_read_r+0x20>) - 8012bc4: 4604 mov r4, r0 - 8012bc6: 4608 mov r0, r1 - 8012bc8: 4611 mov r1, r2 - 8012bca: 2200 movs r2, #0 - 8012bcc: 602a str r2, [r5, #0] - 8012bce: 461a mov r2, r3 - 8012bd0: f7f1 fbac bl 800432c <_read> - 8012bd4: 1c43 adds r3, r0, #1 - 8012bd6: d102 bne.n 8012bde <_read_r+0x1e> - 8012bd8: 682b ldr r3, [r5, #0] - 8012bda: b103 cbz r3, 8012bde <_read_r+0x1e> - 8012bdc: 6023 str r3, [r4, #0] - 8012bde: bd38 pop {r3, r4, r5, pc} - 8012be0: 200015d0 .word 0x200015d0 - -08012be4 <_sbrk_r>: - 8012be4: b538 push {r3, r4, r5, lr} - 8012be6: 4d06 ldr r5, [pc, #24] ; (8012c00 <_sbrk_r+0x1c>) - 8012be8: 2300 movs r3, #0 - 8012bea: 4604 mov r4, r0 - 8012bec: 4608 mov r0, r1 - 8012bee: 602b str r3, [r5, #0] - 8012bf0: f7f1 fc0a bl 8004408 <_sbrk> - 8012bf4: 1c43 adds r3, r0, #1 - 8012bf6: d102 bne.n 8012bfe <_sbrk_r+0x1a> - 8012bf8: 682b ldr r3, [r5, #0] - 8012bfa: b103 cbz r3, 8012bfe <_sbrk_r+0x1a> - 8012bfc: 6023 str r3, [r4, #0] - 8012bfe: bd38 pop {r3, r4, r5, pc} - 8012c00: 200015d0 .word 0x200015d0 - -08012c04 <_write_r>: - 8012c04: b538 push {r3, r4, r5, lr} - 8012c06: 4d07 ldr r5, [pc, #28] ; (8012c24 <_write_r+0x20>) - 8012c08: 4604 mov r4, r0 - 8012c0a: 4608 mov r0, r1 - 8012c0c: 4611 mov r1, r2 - 8012c0e: 2200 movs r2, #0 - 8012c10: 602a str r2, [r5, #0] - 8012c12: 461a mov r2, r3 - 8012c14: f7f1 fba7 bl 8004366 <_write> - 8012c18: 1c43 adds r3, r0, #1 - 8012c1a: d102 bne.n 8012c22 <_write_r+0x1e> - 8012c1c: 682b ldr r3, [r5, #0] - 8012c1e: b103 cbz r3, 8012c22 <_write_r+0x1e> - 8012c20: 6023 str r3, [r4, #0] - 8012c22: bd38 pop {r3, r4, r5, pc} - 8012c24: 200015d0 .word 0x200015d0 - -08012c28 <__errno>: - 8012c28: 4b01 ldr r3, [pc, #4] ; (8012c30 <__errno+0x8>) - 8012c2a: 6818 ldr r0, [r3, #0] - 8012c2c: 4770 bx lr - 8012c2e: bf00 nop - 8012c30: 20000310 .word 0x20000310 - -08012c34 <__libc_init_array>: - 8012c34: b570 push {r4, r5, r6, lr} - 8012c36: 4d0d ldr r5, [pc, #52] ; (8012c6c <__libc_init_array+0x38>) - 8012c38: 4c0d ldr r4, [pc, #52] ; (8012c70 <__libc_init_array+0x3c>) - 8012c3a: 1b64 subs r4, r4, r5 - 8012c3c: 10a4 asrs r4, r4, #2 - 8012c3e: 2600 movs r6, #0 - 8012c40: 42a6 cmp r6, r4 - 8012c42: d109 bne.n 8012c58 <__libc_init_array+0x24> - 8012c44: 4d0b ldr r5, [pc, #44] ; (8012c74 <__libc_init_array+0x40>) - 8012c46: 4c0c ldr r4, [pc, #48] ; (8012c78 <__libc_init_array+0x44>) - 8012c48: f003 fe38 bl 80168bc <_init> - 8012c4c: 1b64 subs r4, r4, r5 - 8012c4e: 10a4 asrs r4, r4, #2 - 8012c50: 2600 movs r6, #0 - 8012c52: 42a6 cmp r6, r4 - 8012c54: d105 bne.n 8012c62 <__libc_init_array+0x2e> - 8012c56: bd70 pop {r4, r5, r6, pc} - 8012c58: f855 3b04 ldr.w r3, [r5], #4 - 8012c5c: 4798 blx r3 - 8012c5e: 3601 adds r6, #1 - 8012c60: e7ee b.n 8012c40 <__libc_init_array+0xc> - 8012c62: f855 3b04 ldr.w r3, [r5], #4 - 8012c66: 4798 blx r3 - 8012c68: 3601 adds r6, #1 - 8012c6a: e7f2 b.n 8012c52 <__libc_init_array+0x1e> - 8012c6c: 08018d90 .word 0x08018d90 - 8012c70: 08018d90 .word 0x08018d90 - 8012c74: 08018d90 .word 0x08018d90 - 8012c78: 08018d94 .word 0x08018d94 - -08012c7c <__retarget_lock_init_recursive>: - 8012c7c: 4770 bx lr - -08012c7e <__retarget_lock_acquire_recursive>: - 8012c7e: 4770 bx lr - -08012c80 <__retarget_lock_release_recursive>: - 8012c80: 4770 bx lr - -08012c82 : - 8012c82: 4603 mov r3, r0 - 8012c84: f811 2b01 ldrb.w r2, [r1], #1 - 8012c88: f803 2b01 strb.w r2, [r3], #1 - 8012c8c: 2a00 cmp r2, #0 - 8012c8e: d1f9 bne.n 8012c84 - 8012c90: 4770 bx lr - -08012c92 : - 8012c92: 440a add r2, r1 - 8012c94: 4291 cmp r1, r2 - 8012c96: f100 33ff add.w r3, r0, #4294967295 - 8012c9a: d100 bne.n 8012c9e - 8012c9c: 4770 bx lr - 8012c9e: b510 push {r4, lr} - 8012ca0: f811 4b01 ldrb.w r4, [r1], #1 - 8012ca4: f803 4f01 strb.w r4, [r3, #1]! - 8012ca8: 4291 cmp r1, r2 - 8012caa: d1f9 bne.n 8012ca0 - 8012cac: bd10 pop {r4, pc} +08014f40 : + 8014f40: 4b16 ldr r3, [pc, #88] ; (8014f9c ) + 8014f42: b573 push {r0, r1, r4, r5, r6, lr} + 8014f44: 681e ldr r6, [r3, #0] + 8014f46: 6c74 ldr r4, [r6, #68] ; 0x44 + 8014f48: 4605 mov r5, r0 + 8014f4a: b9fc cbnz r4, 8014f8c + 8014f4c: 2050 movs r0, #80 ; 0x50 + 8014f4e: 9101 str r1, [sp, #4] + 8014f50: f7fe f848 bl 8012fe4 + 8014f54: 9901 ldr r1, [sp, #4] + 8014f56: 6470 str r0, [r6, #68] ; 0x44 + 8014f58: 4602 mov r2, r0 + 8014f5a: b920 cbnz r0, 8014f66 + 8014f5c: 4b10 ldr r3, [pc, #64] ; (8014fa0 ) + 8014f5e: 4811 ldr r0, [pc, #68] ; (8014fa4 ) + 8014f60: 215b movs r1, #91 ; 0x5b + 8014f62: f000 f90b bl 801517c <__assert_func> + 8014f66: e9c0 4400 strd r4, r4, [r0] + 8014f6a: e9c0 4402 strd r4, r4, [r0, #8] + 8014f6e: e9c0 4404 strd r4, r4, [r0, #16] + 8014f72: e9c0 440a strd r4, r4, [r0, #40] ; 0x28 + 8014f76: e9c0 440c strd r4, r4, [r0, #48] ; 0x30 + 8014f7a: e9c0 440e strd r4, r4, [r0, #56] ; 0x38 + 8014f7e: e9c0 4410 strd r4, r4, [r0, #64] ; 0x40 + 8014f82: e9c0 4412 strd r4, r4, [r0, #72] ; 0x48 + 8014f86: 6184 str r4, [r0, #24] + 8014f88: 7704 strb r4, [r0, #28] + 8014f8a: 6244 str r4, [r0, #36] ; 0x24 + 8014f8c: 6c72 ldr r2, [r6, #68] ; 0x44 + 8014f8e: 2301 movs r3, #1 + 8014f90: 4628 mov r0, r5 + 8014f92: b002 add sp, #8 + 8014f94: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 8014f98: f000 b806 b.w 8014fa8 <__strtok_r> + 8014f9c: 200002f0 .word 0x200002f0 + 8014fa0: 0801ad7a .word 0x0801ad7a + 8014fa4: 0801ad91 .word 0x0801ad91 + +08014fa8 <__strtok_r>: + 8014fa8: b5f0 push {r4, r5, r6, r7, lr} + 8014faa: b908 cbnz r0, 8014fb0 <__strtok_r+0x8> + 8014fac: 6810 ldr r0, [r2, #0] + 8014fae: b188 cbz r0, 8014fd4 <__strtok_r+0x2c> + 8014fb0: 4604 mov r4, r0 + 8014fb2: 4620 mov r0, r4 + 8014fb4: f814 5b01 ldrb.w r5, [r4], #1 + 8014fb8: 460f mov r7, r1 + 8014fba: f817 6b01 ldrb.w r6, [r7], #1 + 8014fbe: b91e cbnz r6, 8014fc8 <__strtok_r+0x20> + 8014fc0: b965 cbnz r5, 8014fdc <__strtok_r+0x34> + 8014fc2: 6015 str r5, [r2, #0] + 8014fc4: 4628 mov r0, r5 + 8014fc6: e005 b.n 8014fd4 <__strtok_r+0x2c> + 8014fc8: 42b5 cmp r5, r6 + 8014fca: d1f6 bne.n 8014fba <__strtok_r+0x12> + 8014fcc: 2b00 cmp r3, #0 + 8014fce: d1f0 bne.n 8014fb2 <__strtok_r+0xa> + 8014fd0: 6014 str r4, [r2, #0] + 8014fd2: 7003 strb r3, [r0, #0] + 8014fd4: bdf0 pop {r4, r5, r6, r7, pc} + 8014fd6: 461c mov r4, r3 + 8014fd8: e00c b.n 8014ff4 <__strtok_r+0x4c> + 8014fda: b915 cbnz r5, 8014fe2 <__strtok_r+0x3a> + 8014fdc: f814 3b01 ldrb.w r3, [r4], #1 + 8014fe0: 460e mov r6, r1 + 8014fe2: f816 5b01 ldrb.w r5, [r6], #1 + 8014fe6: 42ab cmp r3, r5 + 8014fe8: d1f7 bne.n 8014fda <__strtok_r+0x32> + 8014fea: 2b00 cmp r3, #0 + 8014fec: d0f3 beq.n 8014fd6 <__strtok_r+0x2e> + 8014fee: 2300 movs r3, #0 + 8014ff0: f804 3c01 strb.w r3, [r4, #-1] + 8014ff4: 6014 str r4, [r2, #0] + 8014ff6: e7ed b.n 8014fd4 <__strtok_r+0x2c> + +08014ff8 : + 8014ff8: 780a ldrb r2, [r1, #0] + 8014ffa: b570 push {r4, r5, r6, lr} + 8014ffc: b96a cbnz r2, 801501a + 8014ffe: bd70 pop {r4, r5, r6, pc} + 8015000: 429a cmp r2, r3 + 8015002: d109 bne.n 8015018 + 8015004: 460c mov r4, r1 + 8015006: 4605 mov r5, r0 + 8015008: f814 3f01 ldrb.w r3, [r4, #1]! + 801500c: 2b00 cmp r3, #0 + 801500e: d0f6 beq.n 8014ffe + 8015010: f815 6f01 ldrb.w r6, [r5, #1]! + 8015014: 429e cmp r6, r3 + 8015016: d0f7 beq.n 8015008 + 8015018: 3001 adds r0, #1 + 801501a: 7803 ldrb r3, [r0, #0] + 801501c: 2b00 cmp r3, #0 + 801501e: d1ef bne.n 8015000 + 8015020: 4618 mov r0, r3 + 8015022: e7ec b.n 8014ffe + +08015024 <_localeconv_r>: + 8015024: 4800 ldr r0, [pc, #0] ; (8015028 <_localeconv_r+0x4>) + 8015026: 4770 bx lr + 8015028: 20000228 .word 0x20000228 + +0801502c <_close_r>: + 801502c: b538 push {r3, r4, r5, lr} + 801502e: 4d06 ldr r5, [pc, #24] ; (8015048 <_close_r+0x1c>) + 8015030: 2300 movs r3, #0 + 8015032: 4604 mov r4, r0 + 8015034: 4608 mov r0, r1 + 8015036: 602b str r3, [r5, #0] + 8015038: f7ef fdf5 bl 8004c26 <_close> + 801503c: 1c43 adds r3, r0, #1 + 801503e: d102 bne.n 8015046 <_close_r+0x1a> + 8015040: 682b ldr r3, [r5, #0] + 8015042: b103 cbz r3, 8015046 <_close_r+0x1a> + 8015044: 6023 str r3, [r4, #0] + 8015046: bd38 pop {r3, r4, r5, pc} + 8015048: 20002388 .word 0x20002388 + +0801504c <_lseek_r>: + 801504c: b538 push {r3, r4, r5, lr} + 801504e: 4d07 ldr r5, [pc, #28] ; (801506c <_lseek_r+0x20>) + 8015050: 4604 mov r4, r0 + 8015052: 4608 mov r0, r1 + 8015054: 4611 mov r1, r2 + 8015056: 2200 movs r2, #0 + 8015058: 602a str r2, [r5, #0] + 801505a: 461a mov r2, r3 + 801505c: f7ef fe0a bl 8004c74 <_lseek> + 8015060: 1c43 adds r3, r0, #1 + 8015062: d102 bne.n 801506a <_lseek_r+0x1e> + 8015064: 682b ldr r3, [r5, #0] + 8015066: b103 cbz r3, 801506a <_lseek_r+0x1e> + 8015068: 6023 str r3, [r4, #0] + 801506a: bd38 pop {r3, r4, r5, pc} + 801506c: 20002388 .word 0x20002388 + +08015070 <_read_r>: + 8015070: b538 push {r3, r4, r5, lr} + 8015072: 4d07 ldr r5, [pc, #28] ; (8015090 <_read_r+0x20>) + 8015074: 4604 mov r4, r0 + 8015076: 4608 mov r0, r1 + 8015078: 4611 mov r1, r2 + 801507a: 2200 movs r2, #0 + 801507c: 602a str r2, [r5, #0] + 801507e: 461a mov r2, r3 + 8015080: f7ef fd98 bl 8004bb4 <_read> + 8015084: 1c43 adds r3, r0, #1 + 8015086: d102 bne.n 801508e <_read_r+0x1e> + 8015088: 682b ldr r3, [r5, #0] + 801508a: b103 cbz r3, 801508e <_read_r+0x1e> + 801508c: 6023 str r3, [r4, #0] + 801508e: bd38 pop {r3, r4, r5, pc} + 8015090: 20002388 .word 0x20002388 + +08015094 <_sbrk_r>: + 8015094: b538 push {r3, r4, r5, lr} + 8015096: 4d06 ldr r5, [pc, #24] ; (80150b0 <_sbrk_r+0x1c>) + 8015098: 2300 movs r3, #0 + 801509a: 4604 mov r4, r0 + 801509c: 4608 mov r0, r1 + 801509e: 602b str r3, [r5, #0] + 80150a0: f7ef fdf6 bl 8004c90 <_sbrk> + 80150a4: 1c43 adds r3, r0, #1 + 80150a6: d102 bne.n 80150ae <_sbrk_r+0x1a> + 80150a8: 682b ldr r3, [r5, #0] + 80150aa: b103 cbz r3, 80150ae <_sbrk_r+0x1a> + 80150ac: 6023 str r3, [r4, #0] + 80150ae: bd38 pop {r3, r4, r5, pc} + 80150b0: 20002388 .word 0x20002388 + +080150b4 <_write_r>: + 80150b4: b538 push {r3, r4, r5, lr} + 80150b6: 4d07 ldr r5, [pc, #28] ; (80150d4 <_write_r+0x20>) + 80150b8: 4604 mov r4, r0 + 80150ba: 4608 mov r0, r1 + 80150bc: 4611 mov r1, r2 + 80150be: 2200 movs r2, #0 + 80150c0: 602a str r2, [r5, #0] + 80150c2: 461a mov r2, r3 + 80150c4: f7ef fd93 bl 8004bee <_write> + 80150c8: 1c43 adds r3, r0, #1 + 80150ca: d102 bne.n 80150d2 <_write_r+0x1e> + 80150cc: 682b ldr r3, [r5, #0] + 80150ce: b103 cbz r3, 80150d2 <_write_r+0x1e> + 80150d0: 6023 str r3, [r4, #0] + 80150d2: bd38 pop {r3, r4, r5, pc} + 80150d4: 20002388 .word 0x20002388 + +080150d8 <__errno>: + 80150d8: 4b01 ldr r3, [pc, #4] ; (80150e0 <__errno+0x8>) + 80150da: 6818 ldr r0, [r3, #0] + 80150dc: 4770 bx lr + 80150de: bf00 nop + 80150e0: 200002f0 .word 0x200002f0 + +080150e4 <__libc_init_array>: + 80150e4: b570 push {r4, r5, r6, lr} + 80150e6: 4d0d ldr r5, [pc, #52] ; (801511c <__libc_init_array+0x38>) + 80150e8: 4c0d ldr r4, [pc, #52] ; (8015120 <__libc_init_array+0x3c>) + 80150ea: 1b64 subs r4, r4, r5 + 80150ec: 10a4 asrs r4, r4, #2 + 80150ee: 2600 movs r6, #0 + 80150f0: 42a6 cmp r6, r4 + 80150f2: d109 bne.n 8015108 <__libc_init_array+0x24> + 80150f4: 4d0b ldr r5, [pc, #44] ; (8015124 <__libc_init_array+0x40>) + 80150f6: 4c0c ldr r4, [pc, #48] ; (8015128 <__libc_init_array+0x44>) + 80150f8: f003 fe38 bl 8018d6c <_init> + 80150fc: 1b64 subs r4, r4, r5 + 80150fe: 10a4 asrs r4, r4, #2 + 8015100: 2600 movs r6, #0 + 8015102: 42a6 cmp r6, r4 + 8015104: d105 bne.n 8015112 <__libc_init_array+0x2e> + 8015106: bd70 pop {r4, r5, r6, pc} + 8015108: f855 3b04 ldr.w r3, [r5], #4 + 801510c: 4798 blx r3 + 801510e: 3601 adds r6, #1 + 8015110: e7ee b.n 80150f0 <__libc_init_array+0xc> + 8015112: f855 3b04 ldr.w r3, [r5], #4 + 8015116: 4798 blx r3 + 8015118: 3601 adds r6, #1 + 801511a: e7f2 b.n 8015102 <__libc_init_array+0x1e> + 801511c: 0801b268 .word 0x0801b268 + 8015120: 0801b268 .word 0x0801b268 + 8015124: 0801b268 .word 0x0801b268 + 8015128: 0801b26c .word 0x0801b26c + +0801512c <__retarget_lock_init_recursive>: + 801512c: 4770 bx lr + +0801512e <__retarget_lock_acquire_recursive>: + 801512e: 4770 bx lr + +08015130 <__retarget_lock_release_recursive>: + 8015130: 4770 bx lr + +08015132 : + 8015132: 4603 mov r3, r0 + 8015134: f811 2b01 ldrb.w r2, [r1], #1 + 8015138: f803 2b01 strb.w r2, [r3], #1 + 801513c: 2a00 cmp r2, #0 + 801513e: d1f9 bne.n 8015134 + 8015140: 4770 bx lr + +08015142 : + 8015142: 440a add r2, r1 + 8015144: 4291 cmp r1, r2 + 8015146: f100 33ff add.w r3, r0, #4294967295 + 801514a: d100 bne.n 801514e + 801514c: 4770 bx lr + 801514e: b510 push {r4, lr} + 8015150: f811 4b01 ldrb.w r4, [r1], #1 + 8015154: f803 4f01 strb.w r4, [r3, #1]! + 8015158: 4291 cmp r1, r2 + 801515a: d1f9 bne.n 8015150 + 801515c: bd10 pop {r4, pc} ... -08012cb0 : - 8012cb0: ed9f 0b01 vldr d0, [pc, #4] ; 8012cb8 - 8012cb4: 4770 bx lr - 8012cb6: bf00 nop - 8012cb8: 00000000 .word 0x00000000 - 8012cbc: 7ff80000 .word 0x7ff80000 - -08012cc0 : - 8012cc0: ed9f 0a01 vldr s0, [pc, #4] ; 8012cc8 - 8012cc4: 4770 bx lr - 8012cc6: bf00 nop - 8012cc8: 7fc00000 .word 0x7fc00000 - -08012ccc <__assert_func>: - 8012ccc: b51f push {r0, r1, r2, r3, r4, lr} - 8012cce: 4614 mov r4, r2 - 8012cd0: 461a mov r2, r3 - 8012cd2: 4b09 ldr r3, [pc, #36] ; (8012cf8 <__assert_func+0x2c>) - 8012cd4: 681b ldr r3, [r3, #0] - 8012cd6: 4605 mov r5, r0 - 8012cd8: 68d8 ldr r0, [r3, #12] - 8012cda: b14c cbz r4, 8012cf0 <__assert_func+0x24> - 8012cdc: 4b07 ldr r3, [pc, #28] ; (8012cfc <__assert_func+0x30>) - 8012cde: 9100 str r1, [sp, #0] - 8012ce0: e9cd 3401 strd r3, r4, [sp, #4] - 8012ce4: 4906 ldr r1, [pc, #24] ; (8012d00 <__assert_func+0x34>) - 8012ce6: 462b mov r3, r5 - 8012ce8: f002 f8fe bl 8014ee8 - 8012cec: f002 f928 bl 8014f40 - 8012cf0: 4b04 ldr r3, [pc, #16] ; (8012d04 <__assert_func+0x38>) - 8012cf2: 461c mov r4, r3 - 8012cf4: e7f3 b.n 8012cde <__assert_func+0x12> - 8012cf6: bf00 nop - 8012cf8: 20000310 .word 0x20000310 - 8012cfc: 0801891b .word 0x0801891b - 8012d00: 08018928 .word 0x08018928 - 8012d04: 08018956 .word 0x08018956 - -08012d08 : - 8012d08: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8012d0c: 6903 ldr r3, [r0, #16] - 8012d0e: 690c ldr r4, [r1, #16] - 8012d10: 42a3 cmp r3, r4 - 8012d12: 4607 mov r7, r0 - 8012d14: db7e blt.n 8012e14 - 8012d16: 3c01 subs r4, #1 - 8012d18: f101 0814 add.w r8, r1, #20 - 8012d1c: f100 0514 add.w r5, r0, #20 - 8012d20: eb05 0384 add.w r3, r5, r4, lsl #2 - 8012d24: 9301 str r3, [sp, #4] - 8012d26: f858 3024 ldr.w r3, [r8, r4, lsl #2] - 8012d2a: f855 2024 ldr.w r2, [r5, r4, lsl #2] - 8012d2e: 3301 adds r3, #1 - 8012d30: 429a cmp r2, r3 - 8012d32: ea4f 0b84 mov.w fp, r4, lsl #2 - 8012d36: eb08 0984 add.w r9, r8, r4, lsl #2 - 8012d3a: fbb2 f6f3 udiv r6, r2, r3 - 8012d3e: d331 bcc.n 8012da4 - 8012d40: f04f 0e00 mov.w lr, #0 - 8012d44: 4640 mov r0, r8 - 8012d46: 46ac mov ip, r5 - 8012d48: 46f2 mov sl, lr - 8012d4a: f850 2b04 ldr.w r2, [r0], #4 - 8012d4e: b293 uxth r3, r2 - 8012d50: fb06 e303 mla r3, r6, r3, lr - 8012d54: ea4f 4e12 mov.w lr, r2, lsr #16 - 8012d58: 0c1a lsrs r2, r3, #16 - 8012d5a: b29b uxth r3, r3 - 8012d5c: ebaa 0303 sub.w r3, sl, r3 - 8012d60: f8dc a000 ldr.w sl, [ip] - 8012d64: fa13 f38a uxtah r3, r3, sl - 8012d68: fb06 220e mla r2, r6, lr, r2 - 8012d6c: 9300 str r3, [sp, #0] - 8012d6e: 9b00 ldr r3, [sp, #0] - 8012d70: ea4f 4e12 mov.w lr, r2, lsr #16 - 8012d74: b292 uxth r2, r2 - 8012d76: ebc2 421a rsb r2, r2, sl, lsr #16 - 8012d7a: eb02 4223 add.w r2, r2, r3, asr #16 - 8012d7e: f8bd 3000 ldrh.w r3, [sp] - 8012d82: 4581 cmp r9, r0 - 8012d84: ea43 4302 orr.w r3, r3, r2, lsl #16 - 8012d88: f84c 3b04 str.w r3, [ip], #4 - 8012d8c: ea4f 4a22 mov.w sl, r2, asr #16 - 8012d90: d2db bcs.n 8012d4a - 8012d92: f855 300b ldr.w r3, [r5, fp] - 8012d96: b92b cbnz r3, 8012da4 - 8012d98: 9b01 ldr r3, [sp, #4] - 8012d9a: 3b04 subs r3, #4 - 8012d9c: 429d cmp r5, r3 - 8012d9e: 461a mov r2, r3 - 8012da0: d32c bcc.n 8012dfc - 8012da2: 613c str r4, [r7, #16] - 8012da4: 4638 mov r0, r7 - 8012da6: f001 fca5 bl 80146f4 <__mcmp> - 8012daa: 2800 cmp r0, #0 - 8012dac: db22 blt.n 8012df4 - 8012dae: 3601 adds r6, #1 - 8012db0: 4629 mov r1, r5 - 8012db2: 2000 movs r0, #0 - 8012db4: f858 2b04 ldr.w r2, [r8], #4 - 8012db8: f8d1 c000 ldr.w ip, [r1] - 8012dbc: b293 uxth r3, r2 - 8012dbe: 1ac3 subs r3, r0, r3 - 8012dc0: 0c12 lsrs r2, r2, #16 - 8012dc2: fa13 f38c uxtah r3, r3, ip - 8012dc6: ebc2 421c rsb r2, r2, ip, lsr #16 - 8012dca: eb02 4223 add.w r2, r2, r3, asr #16 - 8012dce: b29b uxth r3, r3 - 8012dd0: ea43 4302 orr.w r3, r3, r2, lsl #16 - 8012dd4: 45c1 cmp r9, r8 - 8012dd6: f841 3b04 str.w r3, [r1], #4 - 8012dda: ea4f 4022 mov.w r0, r2, asr #16 - 8012dde: d2e9 bcs.n 8012db4 - 8012de0: f855 2024 ldr.w r2, [r5, r4, lsl #2] - 8012de4: eb05 0384 add.w r3, r5, r4, lsl #2 - 8012de8: b922 cbnz r2, 8012df4 - 8012dea: 3b04 subs r3, #4 - 8012dec: 429d cmp r5, r3 - 8012dee: 461a mov r2, r3 - 8012df0: d30a bcc.n 8012e08 - 8012df2: 613c str r4, [r7, #16] - 8012df4: 4630 mov r0, r6 - 8012df6: b003 add sp, #12 - 8012df8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8012dfc: 6812 ldr r2, [r2, #0] - 8012dfe: 3b04 subs r3, #4 - 8012e00: 2a00 cmp r2, #0 - 8012e02: d1ce bne.n 8012da2 - 8012e04: 3c01 subs r4, #1 - 8012e06: e7c9 b.n 8012d9c - 8012e08: 6812 ldr r2, [r2, #0] - 8012e0a: 3b04 subs r3, #4 - 8012e0c: 2a00 cmp r2, #0 - 8012e0e: d1f0 bne.n 8012df2 - 8012e10: 3c01 subs r4, #1 - 8012e12: e7eb b.n 8012dec - 8012e14: 2000 movs r0, #0 - 8012e16: e7ee b.n 8012df6 - -08012e18 <_dtoa_r>: - 8012e18: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8012e1c: ed2d 8b04 vpush {d8-d9} - 8012e20: 69c5 ldr r5, [r0, #28] - 8012e22: b093 sub sp, #76 ; 0x4c - 8012e24: ed8d 0b02 vstr d0, [sp, #8] - 8012e28: ec57 6b10 vmov r6, r7, d0 - 8012e2c: f8dd 8080 ldr.w r8, [sp, #128] ; 0x80 - 8012e30: 9107 str r1, [sp, #28] - 8012e32: 4604 mov r4, r0 - 8012e34: 920a str r2, [sp, #40] ; 0x28 - 8012e36: 930d str r3, [sp, #52] ; 0x34 - 8012e38: b975 cbnz r5, 8012e58 <_dtoa_r+0x40> - 8012e3a: 2010 movs r0, #16 - 8012e3c: f7fd fe7a bl 8010b34 - 8012e40: 4602 mov r2, r0 - 8012e42: 61e0 str r0, [r4, #28] - 8012e44: b920 cbnz r0, 8012e50 <_dtoa_r+0x38> - 8012e46: 4bae ldr r3, [pc, #696] ; (8013100 <_dtoa_r+0x2e8>) - 8012e48: 21ef movs r1, #239 ; 0xef - 8012e4a: 48ae ldr r0, [pc, #696] ; (8013104 <_dtoa_r+0x2ec>) - 8012e4c: f7ff ff3e bl 8012ccc <__assert_func> - 8012e50: e9c0 5501 strd r5, r5, [r0, #4] - 8012e54: 6005 str r5, [r0, #0] - 8012e56: 60c5 str r5, [r0, #12] - 8012e58: 69e3 ldr r3, [r4, #28] - 8012e5a: 6819 ldr r1, [r3, #0] - 8012e5c: b151 cbz r1, 8012e74 <_dtoa_r+0x5c> - 8012e5e: 685a ldr r2, [r3, #4] - 8012e60: 604a str r2, [r1, #4] - 8012e62: 2301 movs r3, #1 - 8012e64: 4093 lsls r3, r2 - 8012e66: 608b str r3, [r1, #8] - 8012e68: 4620 mov r0, r4 - 8012e6a: f001 f9bd bl 80141e8 <_Bfree> - 8012e6e: 69e3 ldr r3, [r4, #28] - 8012e70: 2200 movs r2, #0 - 8012e72: 601a str r2, [r3, #0] - 8012e74: 1e3b subs r3, r7, #0 - 8012e76: bfbb ittet lt - 8012e78: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 - 8012e7c: 9303 strlt r3, [sp, #12] - 8012e7e: 2300 movge r3, #0 - 8012e80: 2201 movlt r2, #1 - 8012e82: bfac ite ge - 8012e84: f8c8 3000 strge.w r3, [r8] - 8012e88: f8c8 2000 strlt.w r2, [r8] - 8012e8c: 4b9e ldr r3, [pc, #632] ; (8013108 <_dtoa_r+0x2f0>) - 8012e8e: f8dd 800c ldr.w r8, [sp, #12] - 8012e92: ea33 0308 bics.w r3, r3, r8 - 8012e96: d11b bne.n 8012ed0 <_dtoa_r+0xb8> - 8012e98: 9a0d ldr r2, [sp, #52] ; 0x34 - 8012e9a: f242 730f movw r3, #9999 ; 0x270f - 8012e9e: 6013 str r3, [r2, #0] - 8012ea0: f3c8 0313 ubfx r3, r8, #0, #20 - 8012ea4: 4333 orrs r3, r6 - 8012ea6: f000 8593 beq.w 80139d0 <_dtoa_r+0xbb8> - 8012eaa: 9b21 ldr r3, [sp, #132] ; 0x84 - 8012eac: b963 cbnz r3, 8012ec8 <_dtoa_r+0xb0> - 8012eae: 4b97 ldr r3, [pc, #604] ; (801310c <_dtoa_r+0x2f4>) - 8012eb0: e027 b.n 8012f02 <_dtoa_r+0xea> - 8012eb2: 4b97 ldr r3, [pc, #604] ; (8013110 <_dtoa_r+0x2f8>) - 8012eb4: 9300 str r3, [sp, #0] - 8012eb6: 3308 adds r3, #8 - 8012eb8: 9a21 ldr r2, [sp, #132] ; 0x84 - 8012eba: 6013 str r3, [r2, #0] - 8012ebc: 9800 ldr r0, [sp, #0] - 8012ebe: b013 add sp, #76 ; 0x4c - 8012ec0: ecbd 8b04 vpop {d8-d9} - 8012ec4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8012ec8: 4b90 ldr r3, [pc, #576] ; (801310c <_dtoa_r+0x2f4>) - 8012eca: 9300 str r3, [sp, #0] - 8012ecc: 3303 adds r3, #3 - 8012ece: e7f3 b.n 8012eb8 <_dtoa_r+0xa0> - 8012ed0: ed9d 7b02 vldr d7, [sp, #8] - 8012ed4: 2200 movs r2, #0 - 8012ed6: ec51 0b17 vmov r0, r1, d7 - 8012eda: eeb0 8a47 vmov.f32 s16, s14 - 8012ede: eef0 8a67 vmov.f32 s17, s15 - 8012ee2: 2300 movs r3, #0 - 8012ee4: f7ed fdf0 bl 8000ac8 <__aeabi_dcmpeq> - 8012ee8: 4681 mov r9, r0 - 8012eea: b160 cbz r0, 8012f06 <_dtoa_r+0xee> - 8012eec: 9a0d ldr r2, [sp, #52] ; 0x34 - 8012eee: 2301 movs r3, #1 - 8012ef0: 6013 str r3, [r2, #0] - 8012ef2: 9b21 ldr r3, [sp, #132] ; 0x84 - 8012ef4: 2b00 cmp r3, #0 - 8012ef6: f000 8568 beq.w 80139ca <_dtoa_r+0xbb2> - 8012efa: 4b86 ldr r3, [pc, #536] ; (8013114 <_dtoa_r+0x2fc>) - 8012efc: 9a21 ldr r2, [sp, #132] ; 0x84 - 8012efe: 6013 str r3, [r2, #0] - 8012f00: 3b01 subs r3, #1 - 8012f02: 9300 str r3, [sp, #0] - 8012f04: e7da b.n 8012ebc <_dtoa_r+0xa4> - 8012f06: aa10 add r2, sp, #64 ; 0x40 - 8012f08: a911 add r1, sp, #68 ; 0x44 - 8012f0a: 4620 mov r0, r4 - 8012f0c: eeb0 0a48 vmov.f32 s0, s16 - 8012f10: eef0 0a68 vmov.f32 s1, s17 - 8012f14: f001 fd04 bl 8014920 <__d2b> - 8012f18: f3c8 550a ubfx r5, r8, #20, #11 - 8012f1c: 4682 mov sl, r0 - 8012f1e: 2d00 cmp r5, #0 - 8012f20: d07f beq.n 8013022 <_dtoa_r+0x20a> - 8012f22: ee18 3a90 vmov r3, s17 - 8012f26: f3c3 0313 ubfx r3, r3, #0, #20 - 8012f2a: f043 537f orr.w r3, r3, #1069547520 ; 0x3fc00000 - 8012f2e: ec51 0b18 vmov r0, r1, d8 - 8012f32: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 - 8012f36: f2a5 35ff subw r5, r5, #1023 ; 0x3ff - 8012f3a: f8cd 9038 str.w r9, [sp, #56] ; 0x38 - 8012f3e: 4619 mov r1, r3 - 8012f40: 2200 movs r2, #0 - 8012f42: 4b75 ldr r3, [pc, #468] ; (8013118 <_dtoa_r+0x300>) - 8012f44: f7ed f9a0 bl 8000288 <__aeabi_dsub> - 8012f48: a367 add r3, pc, #412 ; (adr r3, 80130e8 <_dtoa_r+0x2d0>) - 8012f4a: e9d3 2300 ldrd r2, r3, [r3] - 8012f4e: f7ed fb53 bl 80005f8 <__aeabi_dmul> - 8012f52: a367 add r3, pc, #412 ; (adr r3, 80130f0 <_dtoa_r+0x2d8>) - 8012f54: e9d3 2300 ldrd r2, r3, [r3] - 8012f58: f7ed f998 bl 800028c <__adddf3> - 8012f5c: 4606 mov r6, r0 - 8012f5e: 4628 mov r0, r5 - 8012f60: 460f mov r7, r1 - 8012f62: f7ed fadf bl 8000524 <__aeabi_i2d> - 8012f66: a364 add r3, pc, #400 ; (adr r3, 80130f8 <_dtoa_r+0x2e0>) - 8012f68: e9d3 2300 ldrd r2, r3, [r3] - 8012f6c: f7ed fb44 bl 80005f8 <__aeabi_dmul> - 8012f70: 4602 mov r2, r0 - 8012f72: 460b mov r3, r1 - 8012f74: 4630 mov r0, r6 - 8012f76: 4639 mov r1, r7 - 8012f78: f7ed f988 bl 800028c <__adddf3> - 8012f7c: 4606 mov r6, r0 - 8012f7e: 460f mov r7, r1 - 8012f80: f7ed fdea bl 8000b58 <__aeabi_d2iz> - 8012f84: 2200 movs r2, #0 - 8012f86: 4683 mov fp, r0 - 8012f88: 2300 movs r3, #0 - 8012f8a: 4630 mov r0, r6 - 8012f8c: 4639 mov r1, r7 - 8012f8e: f7ed fda5 bl 8000adc <__aeabi_dcmplt> - 8012f92: b148 cbz r0, 8012fa8 <_dtoa_r+0x190> - 8012f94: 4658 mov r0, fp - 8012f96: f7ed fac5 bl 8000524 <__aeabi_i2d> - 8012f9a: 4632 mov r2, r6 - 8012f9c: 463b mov r3, r7 - 8012f9e: f7ed fd93 bl 8000ac8 <__aeabi_dcmpeq> - 8012fa2: b908 cbnz r0, 8012fa8 <_dtoa_r+0x190> - 8012fa4: f10b 3bff add.w fp, fp, #4294967295 - 8012fa8: f1bb 0f16 cmp.w fp, #22 - 8012fac: d857 bhi.n 801305e <_dtoa_r+0x246> - 8012fae: 4b5b ldr r3, [pc, #364] ; (801311c <_dtoa_r+0x304>) - 8012fb0: eb03 03cb add.w r3, r3, fp, lsl #3 - 8012fb4: e9d3 2300 ldrd r2, r3, [r3] - 8012fb8: ec51 0b18 vmov r0, r1, d8 - 8012fbc: f7ed fd8e bl 8000adc <__aeabi_dcmplt> - 8012fc0: 2800 cmp r0, #0 - 8012fc2: d04e beq.n 8013062 <_dtoa_r+0x24a> - 8012fc4: f10b 3bff add.w fp, fp, #4294967295 - 8012fc8: 2300 movs r3, #0 - 8012fca: 930c str r3, [sp, #48] ; 0x30 - 8012fcc: 9b10 ldr r3, [sp, #64] ; 0x40 - 8012fce: 1b5b subs r3, r3, r5 - 8012fd0: 1e5a subs r2, r3, #1 - 8012fd2: bf45 ittet mi - 8012fd4: f1c3 0301 rsbmi r3, r3, #1 - 8012fd8: 9305 strmi r3, [sp, #20] - 8012fda: 2300 movpl r3, #0 - 8012fdc: 2300 movmi r3, #0 - 8012fde: 9206 str r2, [sp, #24] - 8012fe0: bf54 ite pl - 8012fe2: 9305 strpl r3, [sp, #20] - 8012fe4: 9306 strmi r3, [sp, #24] - 8012fe6: f1bb 0f00 cmp.w fp, #0 - 8012fea: db3c blt.n 8013066 <_dtoa_r+0x24e> - 8012fec: 9b06 ldr r3, [sp, #24] - 8012fee: f8cd b02c str.w fp, [sp, #44] ; 0x2c - 8012ff2: 445b add r3, fp - 8012ff4: 9306 str r3, [sp, #24] - 8012ff6: 2300 movs r3, #0 - 8012ff8: 9308 str r3, [sp, #32] - 8012ffa: 9b07 ldr r3, [sp, #28] - 8012ffc: 2b09 cmp r3, #9 - 8012ffe: d868 bhi.n 80130d2 <_dtoa_r+0x2ba> - 8013000: 2b05 cmp r3, #5 - 8013002: bfc4 itt gt - 8013004: 3b04 subgt r3, #4 - 8013006: 9307 strgt r3, [sp, #28] - 8013008: 9b07 ldr r3, [sp, #28] - 801300a: f1a3 0302 sub.w r3, r3, #2 - 801300e: bfcc ite gt - 8013010: 2500 movgt r5, #0 - 8013012: 2501 movle r5, #1 - 8013014: 2b03 cmp r3, #3 - 8013016: f200 8085 bhi.w 8013124 <_dtoa_r+0x30c> - 801301a: e8df f003 tbb [pc, r3] - 801301e: 3b2e .short 0x3b2e - 8013020: 5839 .short 0x5839 - 8013022: e9dd 5310 ldrd r5, r3, [sp, #64] ; 0x40 - 8013026: 441d add r5, r3 - 8013028: f205 4332 addw r3, r5, #1074 ; 0x432 - 801302c: 2b20 cmp r3, #32 - 801302e: bfc1 itttt gt - 8013030: f1c3 0340 rsbgt r3, r3, #64 ; 0x40 - 8013034: fa08 f803 lslgt.w r8, r8, r3 - 8013038: f205 4312 addwgt r3, r5, #1042 ; 0x412 - 801303c: fa26 f303 lsrgt.w r3, r6, r3 - 8013040: bfd6 itet le - 8013042: f1c3 0320 rsble r3, r3, #32 - 8013046: ea48 0003 orrgt.w r0, r8, r3 - 801304a: fa06 f003 lslle.w r0, r6, r3 - 801304e: f7ed fa59 bl 8000504 <__aeabi_ui2d> - 8013052: 2201 movs r2, #1 - 8013054: f1a1 73f8 sub.w r3, r1, #32505856 ; 0x1f00000 - 8013058: 3d01 subs r5, #1 - 801305a: 920e str r2, [sp, #56] ; 0x38 - 801305c: e76f b.n 8012f3e <_dtoa_r+0x126> - 801305e: 2301 movs r3, #1 - 8013060: e7b3 b.n 8012fca <_dtoa_r+0x1b2> - 8013062: 900c str r0, [sp, #48] ; 0x30 - 8013064: e7b2 b.n 8012fcc <_dtoa_r+0x1b4> - 8013066: 9b05 ldr r3, [sp, #20] - 8013068: eba3 030b sub.w r3, r3, fp - 801306c: 9305 str r3, [sp, #20] - 801306e: f1cb 0300 rsb r3, fp, #0 - 8013072: 9308 str r3, [sp, #32] - 8013074: 2300 movs r3, #0 - 8013076: 930b str r3, [sp, #44] ; 0x2c - 8013078: e7bf b.n 8012ffa <_dtoa_r+0x1e2> - 801307a: 2300 movs r3, #0 - 801307c: 9309 str r3, [sp, #36] ; 0x24 - 801307e: 9b0a ldr r3, [sp, #40] ; 0x28 - 8013080: 2b00 cmp r3, #0 - 8013082: dc52 bgt.n 801312a <_dtoa_r+0x312> - 8013084: 2301 movs r3, #1 - 8013086: 9301 str r3, [sp, #4] - 8013088: 9304 str r3, [sp, #16] - 801308a: 461a mov r2, r3 - 801308c: 920a str r2, [sp, #40] ; 0x28 - 801308e: e00b b.n 80130a8 <_dtoa_r+0x290> - 8013090: 2301 movs r3, #1 - 8013092: e7f3 b.n 801307c <_dtoa_r+0x264> - 8013094: 2300 movs r3, #0 - 8013096: 9309 str r3, [sp, #36] ; 0x24 - 8013098: 9b0a ldr r3, [sp, #40] ; 0x28 - 801309a: 445b add r3, fp - 801309c: 9301 str r3, [sp, #4] - 801309e: 3301 adds r3, #1 - 80130a0: 2b01 cmp r3, #1 - 80130a2: 9304 str r3, [sp, #16] - 80130a4: bfb8 it lt - 80130a6: 2301 movlt r3, #1 - 80130a8: 69e0 ldr r0, [r4, #28] - 80130aa: 2100 movs r1, #0 - 80130ac: 2204 movs r2, #4 - 80130ae: f102 0614 add.w r6, r2, #20 - 80130b2: 429e cmp r6, r3 - 80130b4: d93d bls.n 8013132 <_dtoa_r+0x31a> - 80130b6: 6041 str r1, [r0, #4] - 80130b8: 4620 mov r0, r4 - 80130ba: f001 f855 bl 8014168 <_Balloc> - 80130be: 9000 str r0, [sp, #0] - 80130c0: 2800 cmp r0, #0 - 80130c2: d139 bne.n 8013138 <_dtoa_r+0x320> - 80130c4: 4b16 ldr r3, [pc, #88] ; (8013120 <_dtoa_r+0x308>) - 80130c6: 4602 mov r2, r0 - 80130c8: f240 11af movw r1, #431 ; 0x1af - 80130cc: e6bd b.n 8012e4a <_dtoa_r+0x32> - 80130ce: 2301 movs r3, #1 - 80130d0: e7e1 b.n 8013096 <_dtoa_r+0x27e> - 80130d2: 2501 movs r5, #1 - 80130d4: 2300 movs r3, #0 - 80130d6: 9307 str r3, [sp, #28] - 80130d8: 9509 str r5, [sp, #36] ; 0x24 - 80130da: f04f 33ff mov.w r3, #4294967295 - 80130de: 9301 str r3, [sp, #4] - 80130e0: 9304 str r3, [sp, #16] - 80130e2: 2200 movs r2, #0 - 80130e4: 2312 movs r3, #18 - 80130e6: e7d1 b.n 801308c <_dtoa_r+0x274> - 80130e8: 636f4361 .word 0x636f4361 - 80130ec: 3fd287a7 .word 0x3fd287a7 - 80130f0: 8b60c8b3 .word 0x8b60c8b3 - 80130f4: 3fc68a28 .word 0x3fc68a28 - 80130f8: 509f79fb .word 0x509f79fb - 80130fc: 3fd34413 .word 0x3fd34413 - 8013100: 080188a2 .word 0x080188a2 - 8013104: 08018964 .word 0x08018964 - 8013108: 7ff00000 .word 0x7ff00000 - 801310c: 08018960 .word 0x08018960 - 8013110: 08018957 .word 0x08018957 - 8013114: 0801887a .word 0x0801887a - 8013118: 3ff80000 .word 0x3ff80000 - 801311c: 08018ab0 .word 0x08018ab0 - 8013120: 080189bc .word 0x080189bc - 8013124: 2301 movs r3, #1 - 8013126: 9309 str r3, [sp, #36] ; 0x24 - 8013128: e7d7 b.n 80130da <_dtoa_r+0x2c2> - 801312a: 9b0a ldr r3, [sp, #40] ; 0x28 - 801312c: 9301 str r3, [sp, #4] - 801312e: 9304 str r3, [sp, #16] - 8013130: e7ba b.n 80130a8 <_dtoa_r+0x290> - 8013132: 3101 adds r1, #1 - 8013134: 0052 lsls r2, r2, #1 - 8013136: e7ba b.n 80130ae <_dtoa_r+0x296> - 8013138: 69e3 ldr r3, [r4, #28] - 801313a: 9a00 ldr r2, [sp, #0] - 801313c: 601a str r2, [r3, #0] - 801313e: 9b04 ldr r3, [sp, #16] - 8013140: 2b0e cmp r3, #14 - 8013142: f200 80a8 bhi.w 8013296 <_dtoa_r+0x47e> - 8013146: 2d00 cmp r5, #0 - 8013148: f000 80a5 beq.w 8013296 <_dtoa_r+0x47e> - 801314c: f1bb 0f00 cmp.w fp, #0 - 8013150: dd38 ble.n 80131c4 <_dtoa_r+0x3ac> - 8013152: 4bc0 ldr r3, [pc, #768] ; (8013454 <_dtoa_r+0x63c>) - 8013154: f00b 020f and.w r2, fp, #15 - 8013158: eb03 03c2 add.w r3, r3, r2, lsl #3 - 801315c: f41b 7f80 tst.w fp, #256 ; 0x100 - 8013160: e9d3 6700 ldrd r6, r7, [r3] - 8013164: ea4f 182b mov.w r8, fp, asr #4 - 8013168: d019 beq.n 801319e <_dtoa_r+0x386> - 801316a: 4bbb ldr r3, [pc, #748] ; (8013458 <_dtoa_r+0x640>) - 801316c: ec51 0b18 vmov r0, r1, d8 - 8013170: e9d3 2308 ldrd r2, r3, [r3, #32] - 8013174: f7ed fb6a bl 800084c <__aeabi_ddiv> - 8013178: e9cd 0102 strd r0, r1, [sp, #8] - 801317c: f008 080f and.w r8, r8, #15 - 8013180: 2503 movs r5, #3 - 8013182: f8df 92d4 ldr.w r9, [pc, #724] ; 8013458 <_dtoa_r+0x640> - 8013186: f1b8 0f00 cmp.w r8, #0 - 801318a: d10a bne.n 80131a2 <_dtoa_r+0x38a> - 801318c: e9dd 0102 ldrd r0, r1, [sp, #8] - 8013190: 4632 mov r2, r6 - 8013192: 463b mov r3, r7 - 8013194: f7ed fb5a bl 800084c <__aeabi_ddiv> - 8013198: e9cd 0102 strd r0, r1, [sp, #8] - 801319c: e02b b.n 80131f6 <_dtoa_r+0x3de> - 801319e: 2502 movs r5, #2 - 80131a0: e7ef b.n 8013182 <_dtoa_r+0x36a> - 80131a2: f018 0f01 tst.w r8, #1 - 80131a6: d008 beq.n 80131ba <_dtoa_r+0x3a2> - 80131a8: 4630 mov r0, r6 - 80131aa: 4639 mov r1, r7 - 80131ac: e9d9 2300 ldrd r2, r3, [r9] - 80131b0: f7ed fa22 bl 80005f8 <__aeabi_dmul> - 80131b4: 3501 adds r5, #1 - 80131b6: 4606 mov r6, r0 - 80131b8: 460f mov r7, r1 - 80131ba: ea4f 0868 mov.w r8, r8, asr #1 - 80131be: f109 0908 add.w r9, r9, #8 - 80131c2: e7e0 b.n 8013186 <_dtoa_r+0x36e> - 80131c4: f000 809f beq.w 8013306 <_dtoa_r+0x4ee> - 80131c8: f1cb 0600 rsb r6, fp, #0 - 80131cc: 4ba1 ldr r3, [pc, #644] ; (8013454 <_dtoa_r+0x63c>) - 80131ce: 4fa2 ldr r7, [pc, #648] ; (8013458 <_dtoa_r+0x640>) - 80131d0: f006 020f and.w r2, r6, #15 - 80131d4: eb03 03c2 add.w r3, r3, r2, lsl #3 - 80131d8: e9d3 2300 ldrd r2, r3, [r3] - 80131dc: ec51 0b18 vmov r0, r1, d8 - 80131e0: f7ed fa0a bl 80005f8 <__aeabi_dmul> - 80131e4: e9cd 0102 strd r0, r1, [sp, #8] - 80131e8: 1136 asrs r6, r6, #4 - 80131ea: 2300 movs r3, #0 - 80131ec: 2502 movs r5, #2 - 80131ee: 2e00 cmp r6, #0 - 80131f0: d17e bne.n 80132f0 <_dtoa_r+0x4d8> - 80131f2: 2b00 cmp r3, #0 - 80131f4: d1d0 bne.n 8013198 <_dtoa_r+0x380> - 80131f6: 9b0c ldr r3, [sp, #48] ; 0x30 - 80131f8: e9dd 8902 ldrd r8, r9, [sp, #8] - 80131fc: 2b00 cmp r3, #0 - 80131fe: f000 8084 beq.w 801330a <_dtoa_r+0x4f2> - 8013202: 4b96 ldr r3, [pc, #600] ; (801345c <_dtoa_r+0x644>) - 8013204: 2200 movs r2, #0 - 8013206: 4640 mov r0, r8 - 8013208: 4649 mov r1, r9 - 801320a: f7ed fc67 bl 8000adc <__aeabi_dcmplt> - 801320e: 2800 cmp r0, #0 - 8013210: d07b beq.n 801330a <_dtoa_r+0x4f2> - 8013212: 9b04 ldr r3, [sp, #16] - 8013214: 2b00 cmp r3, #0 - 8013216: d078 beq.n 801330a <_dtoa_r+0x4f2> - 8013218: 9b01 ldr r3, [sp, #4] - 801321a: 2b00 cmp r3, #0 - 801321c: dd39 ble.n 8013292 <_dtoa_r+0x47a> - 801321e: 4b90 ldr r3, [pc, #576] ; (8013460 <_dtoa_r+0x648>) - 8013220: 2200 movs r2, #0 - 8013222: 4640 mov r0, r8 - 8013224: 4649 mov r1, r9 - 8013226: f7ed f9e7 bl 80005f8 <__aeabi_dmul> - 801322a: e9cd 0102 strd r0, r1, [sp, #8] - 801322e: 9e01 ldr r6, [sp, #4] - 8013230: f10b 37ff add.w r7, fp, #4294967295 - 8013234: 3501 adds r5, #1 - 8013236: e9dd 8902 ldrd r8, r9, [sp, #8] - 801323a: 4628 mov r0, r5 - 801323c: f7ed f972 bl 8000524 <__aeabi_i2d> - 8013240: 4642 mov r2, r8 - 8013242: 464b mov r3, r9 - 8013244: f7ed f9d8 bl 80005f8 <__aeabi_dmul> - 8013248: 4b86 ldr r3, [pc, #536] ; (8013464 <_dtoa_r+0x64c>) - 801324a: 2200 movs r2, #0 - 801324c: f7ed f81e bl 800028c <__adddf3> - 8013250: f1a1 7350 sub.w r3, r1, #54525952 ; 0x3400000 - 8013254: e9cd 0102 strd r0, r1, [sp, #8] - 8013258: 9303 str r3, [sp, #12] - 801325a: 2e00 cmp r6, #0 - 801325c: d158 bne.n 8013310 <_dtoa_r+0x4f8> - 801325e: 4b82 ldr r3, [pc, #520] ; (8013468 <_dtoa_r+0x650>) - 8013260: 2200 movs r2, #0 - 8013262: 4640 mov r0, r8 - 8013264: 4649 mov r1, r9 - 8013266: f7ed f80f bl 8000288 <__aeabi_dsub> - 801326a: e9dd 2302 ldrd r2, r3, [sp, #8] - 801326e: 4680 mov r8, r0 - 8013270: 4689 mov r9, r1 - 8013272: f7ed fc51 bl 8000b18 <__aeabi_dcmpgt> - 8013276: 2800 cmp r0, #0 - 8013278: f040 8296 bne.w 80137a8 <_dtoa_r+0x990> - 801327c: e9dd 2102 ldrd r2, r1, [sp, #8] - 8013280: 4640 mov r0, r8 - 8013282: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8013286: 4649 mov r1, r9 - 8013288: f7ed fc28 bl 8000adc <__aeabi_dcmplt> - 801328c: 2800 cmp r0, #0 - 801328e: f040 8289 bne.w 80137a4 <_dtoa_r+0x98c> - 8013292: ed8d 8b02 vstr d8, [sp, #8] - 8013296: 9b11 ldr r3, [sp, #68] ; 0x44 - 8013298: 2b00 cmp r3, #0 - 801329a: f2c0 814e blt.w 801353a <_dtoa_r+0x722> - 801329e: f1bb 0f0e cmp.w fp, #14 - 80132a2: f300 814a bgt.w 801353a <_dtoa_r+0x722> - 80132a6: 4b6b ldr r3, [pc, #428] ; (8013454 <_dtoa_r+0x63c>) - 80132a8: eb03 03cb add.w r3, r3, fp, lsl #3 - 80132ac: e9d3 8900 ldrd r8, r9, [r3] - 80132b0: 9b0a ldr r3, [sp, #40] ; 0x28 - 80132b2: 2b00 cmp r3, #0 - 80132b4: f280 80dc bge.w 8013470 <_dtoa_r+0x658> - 80132b8: 9b04 ldr r3, [sp, #16] - 80132ba: 2b00 cmp r3, #0 - 80132bc: f300 80d8 bgt.w 8013470 <_dtoa_r+0x658> - 80132c0: f040 826f bne.w 80137a2 <_dtoa_r+0x98a> - 80132c4: 4b68 ldr r3, [pc, #416] ; (8013468 <_dtoa_r+0x650>) - 80132c6: 2200 movs r2, #0 - 80132c8: 4640 mov r0, r8 - 80132ca: 4649 mov r1, r9 - 80132cc: f7ed f994 bl 80005f8 <__aeabi_dmul> - 80132d0: e9dd 2302 ldrd r2, r3, [sp, #8] - 80132d4: f7ed fc16 bl 8000b04 <__aeabi_dcmpge> - 80132d8: 9e04 ldr r6, [sp, #16] - 80132da: 4637 mov r7, r6 - 80132dc: 2800 cmp r0, #0 - 80132de: f040 8245 bne.w 801376c <_dtoa_r+0x954> - 80132e2: 9d00 ldr r5, [sp, #0] - 80132e4: 2331 movs r3, #49 ; 0x31 - 80132e6: f805 3b01 strb.w r3, [r5], #1 - 80132ea: f10b 0b01 add.w fp, fp, #1 - 80132ee: e241 b.n 8013774 <_dtoa_r+0x95c> - 80132f0: 07f2 lsls r2, r6, #31 - 80132f2: d505 bpl.n 8013300 <_dtoa_r+0x4e8> - 80132f4: e9d7 2300 ldrd r2, r3, [r7] - 80132f8: f7ed f97e bl 80005f8 <__aeabi_dmul> - 80132fc: 3501 adds r5, #1 - 80132fe: 2301 movs r3, #1 - 8013300: 1076 asrs r6, r6, #1 - 8013302: 3708 adds r7, #8 - 8013304: e773 b.n 80131ee <_dtoa_r+0x3d6> - 8013306: 2502 movs r5, #2 - 8013308: e775 b.n 80131f6 <_dtoa_r+0x3de> - 801330a: 9e04 ldr r6, [sp, #16] - 801330c: 465f mov r7, fp - 801330e: e792 b.n 8013236 <_dtoa_r+0x41e> - 8013310: 9900 ldr r1, [sp, #0] - 8013312: 4b50 ldr r3, [pc, #320] ; (8013454 <_dtoa_r+0x63c>) - 8013314: ed9d 7b02 vldr d7, [sp, #8] - 8013318: 4431 add r1, r6 - 801331a: 9102 str r1, [sp, #8] - 801331c: 9909 ldr r1, [sp, #36] ; 0x24 - 801331e: eeb0 9a47 vmov.f32 s18, s14 - 8013322: eef0 9a67 vmov.f32 s19, s15 - 8013326: eb03 03c6 add.w r3, r3, r6, lsl #3 - 801332a: e953 2302 ldrd r2, r3, [r3, #-8] - 801332e: 2900 cmp r1, #0 - 8013330: d044 beq.n 80133bc <_dtoa_r+0x5a4> - 8013332: 494e ldr r1, [pc, #312] ; (801346c <_dtoa_r+0x654>) - 8013334: 2000 movs r0, #0 - 8013336: f7ed fa89 bl 800084c <__aeabi_ddiv> - 801333a: ec53 2b19 vmov r2, r3, d9 - 801333e: f7ec ffa3 bl 8000288 <__aeabi_dsub> - 8013342: 9d00 ldr r5, [sp, #0] - 8013344: ec41 0b19 vmov d9, r0, r1 - 8013348: 4649 mov r1, r9 - 801334a: 4640 mov r0, r8 - 801334c: f7ed fc04 bl 8000b58 <__aeabi_d2iz> - 8013350: 4606 mov r6, r0 - 8013352: f7ed f8e7 bl 8000524 <__aeabi_i2d> - 8013356: 4602 mov r2, r0 - 8013358: 460b mov r3, r1 - 801335a: 4640 mov r0, r8 - 801335c: 4649 mov r1, r9 - 801335e: f7ec ff93 bl 8000288 <__aeabi_dsub> - 8013362: 3630 adds r6, #48 ; 0x30 - 8013364: f805 6b01 strb.w r6, [r5], #1 - 8013368: ec53 2b19 vmov r2, r3, d9 - 801336c: 4680 mov r8, r0 - 801336e: 4689 mov r9, r1 - 8013370: f7ed fbb4 bl 8000adc <__aeabi_dcmplt> - 8013374: 2800 cmp r0, #0 - 8013376: d164 bne.n 8013442 <_dtoa_r+0x62a> - 8013378: 4642 mov r2, r8 - 801337a: 464b mov r3, r9 - 801337c: 4937 ldr r1, [pc, #220] ; (801345c <_dtoa_r+0x644>) - 801337e: 2000 movs r0, #0 - 8013380: f7ec ff82 bl 8000288 <__aeabi_dsub> - 8013384: ec53 2b19 vmov r2, r3, d9 - 8013388: f7ed fba8 bl 8000adc <__aeabi_dcmplt> - 801338c: 2800 cmp r0, #0 - 801338e: f040 80b6 bne.w 80134fe <_dtoa_r+0x6e6> - 8013392: 9b02 ldr r3, [sp, #8] - 8013394: 429d cmp r5, r3 - 8013396: f43f af7c beq.w 8013292 <_dtoa_r+0x47a> - 801339a: 4b31 ldr r3, [pc, #196] ; (8013460 <_dtoa_r+0x648>) - 801339c: ec51 0b19 vmov r0, r1, d9 - 80133a0: 2200 movs r2, #0 - 80133a2: f7ed f929 bl 80005f8 <__aeabi_dmul> - 80133a6: 4b2e ldr r3, [pc, #184] ; (8013460 <_dtoa_r+0x648>) - 80133a8: ec41 0b19 vmov d9, r0, r1 - 80133ac: 2200 movs r2, #0 - 80133ae: 4640 mov r0, r8 - 80133b0: 4649 mov r1, r9 - 80133b2: f7ed f921 bl 80005f8 <__aeabi_dmul> - 80133b6: 4680 mov r8, r0 - 80133b8: 4689 mov r9, r1 - 80133ba: e7c5 b.n 8013348 <_dtoa_r+0x530> - 80133bc: ec51 0b17 vmov r0, r1, d7 - 80133c0: f7ed f91a bl 80005f8 <__aeabi_dmul> - 80133c4: 9b02 ldr r3, [sp, #8] - 80133c6: 9d00 ldr r5, [sp, #0] - 80133c8: 930f str r3, [sp, #60] ; 0x3c - 80133ca: ec41 0b19 vmov d9, r0, r1 - 80133ce: 4649 mov r1, r9 - 80133d0: 4640 mov r0, r8 - 80133d2: f7ed fbc1 bl 8000b58 <__aeabi_d2iz> - 80133d6: 4606 mov r6, r0 - 80133d8: f7ed f8a4 bl 8000524 <__aeabi_i2d> - 80133dc: 3630 adds r6, #48 ; 0x30 - 80133de: 4602 mov r2, r0 - 80133e0: 460b mov r3, r1 - 80133e2: 4640 mov r0, r8 - 80133e4: 4649 mov r1, r9 - 80133e6: f7ec ff4f bl 8000288 <__aeabi_dsub> - 80133ea: f805 6b01 strb.w r6, [r5], #1 - 80133ee: 9b02 ldr r3, [sp, #8] - 80133f0: 429d cmp r5, r3 - 80133f2: 4680 mov r8, r0 - 80133f4: 4689 mov r9, r1 - 80133f6: f04f 0200 mov.w r2, #0 - 80133fa: d124 bne.n 8013446 <_dtoa_r+0x62e> - 80133fc: 4b1b ldr r3, [pc, #108] ; (801346c <_dtoa_r+0x654>) - 80133fe: ec51 0b19 vmov r0, r1, d9 - 8013402: f7ec ff43 bl 800028c <__adddf3> - 8013406: 4602 mov r2, r0 - 8013408: 460b mov r3, r1 - 801340a: 4640 mov r0, r8 - 801340c: 4649 mov r1, r9 - 801340e: f7ed fb83 bl 8000b18 <__aeabi_dcmpgt> - 8013412: 2800 cmp r0, #0 - 8013414: d173 bne.n 80134fe <_dtoa_r+0x6e6> - 8013416: ec53 2b19 vmov r2, r3, d9 - 801341a: 4914 ldr r1, [pc, #80] ; (801346c <_dtoa_r+0x654>) - 801341c: 2000 movs r0, #0 - 801341e: f7ec ff33 bl 8000288 <__aeabi_dsub> - 8013422: 4602 mov r2, r0 - 8013424: 460b mov r3, r1 - 8013426: 4640 mov r0, r8 - 8013428: 4649 mov r1, r9 - 801342a: f7ed fb57 bl 8000adc <__aeabi_dcmplt> - 801342e: 2800 cmp r0, #0 - 8013430: f43f af2f beq.w 8013292 <_dtoa_r+0x47a> - 8013434: 9d0f ldr r5, [sp, #60] ; 0x3c - 8013436: 1e6b subs r3, r5, #1 - 8013438: 930f str r3, [sp, #60] ; 0x3c - 801343a: f815 3c01 ldrb.w r3, [r5, #-1] - 801343e: 2b30 cmp r3, #48 ; 0x30 - 8013440: d0f8 beq.n 8013434 <_dtoa_r+0x61c> - 8013442: 46bb mov fp, r7 - 8013444: e04a b.n 80134dc <_dtoa_r+0x6c4> - 8013446: 4b06 ldr r3, [pc, #24] ; (8013460 <_dtoa_r+0x648>) - 8013448: f7ed f8d6 bl 80005f8 <__aeabi_dmul> - 801344c: 4680 mov r8, r0 - 801344e: 4689 mov r9, r1 - 8013450: e7bd b.n 80133ce <_dtoa_r+0x5b6> - 8013452: bf00 nop - 8013454: 08018ab0 .word 0x08018ab0 - 8013458: 08018a88 .word 0x08018a88 - 801345c: 3ff00000 .word 0x3ff00000 - 8013460: 40240000 .word 0x40240000 - 8013464: 401c0000 .word 0x401c0000 - 8013468: 40140000 .word 0x40140000 - 801346c: 3fe00000 .word 0x3fe00000 - 8013470: e9dd 6702 ldrd r6, r7, [sp, #8] - 8013474: 9d00 ldr r5, [sp, #0] - 8013476: 4642 mov r2, r8 - 8013478: 464b mov r3, r9 - 801347a: 4630 mov r0, r6 - 801347c: 4639 mov r1, r7 - 801347e: f7ed f9e5 bl 800084c <__aeabi_ddiv> - 8013482: f7ed fb69 bl 8000b58 <__aeabi_d2iz> - 8013486: 9001 str r0, [sp, #4] - 8013488: f7ed f84c bl 8000524 <__aeabi_i2d> - 801348c: 4642 mov r2, r8 - 801348e: 464b mov r3, r9 - 8013490: f7ed f8b2 bl 80005f8 <__aeabi_dmul> - 8013494: 4602 mov r2, r0 - 8013496: 460b mov r3, r1 - 8013498: 4630 mov r0, r6 - 801349a: 4639 mov r1, r7 - 801349c: f7ec fef4 bl 8000288 <__aeabi_dsub> - 80134a0: 9e01 ldr r6, [sp, #4] - 80134a2: 9f04 ldr r7, [sp, #16] - 80134a4: 3630 adds r6, #48 ; 0x30 - 80134a6: f805 6b01 strb.w r6, [r5], #1 - 80134aa: 9e00 ldr r6, [sp, #0] - 80134ac: 1bae subs r6, r5, r6 - 80134ae: 42b7 cmp r7, r6 - 80134b0: 4602 mov r2, r0 - 80134b2: 460b mov r3, r1 - 80134b4: d134 bne.n 8013520 <_dtoa_r+0x708> - 80134b6: f7ec fee9 bl 800028c <__adddf3> - 80134ba: 4642 mov r2, r8 - 80134bc: 464b mov r3, r9 - 80134be: 4606 mov r6, r0 - 80134c0: 460f mov r7, r1 - 80134c2: f7ed fb29 bl 8000b18 <__aeabi_dcmpgt> - 80134c6: b9c8 cbnz r0, 80134fc <_dtoa_r+0x6e4> - 80134c8: 4642 mov r2, r8 - 80134ca: 464b mov r3, r9 - 80134cc: 4630 mov r0, r6 - 80134ce: 4639 mov r1, r7 - 80134d0: f7ed fafa bl 8000ac8 <__aeabi_dcmpeq> - 80134d4: b110 cbz r0, 80134dc <_dtoa_r+0x6c4> - 80134d6: 9b01 ldr r3, [sp, #4] - 80134d8: 07db lsls r3, r3, #31 - 80134da: d40f bmi.n 80134fc <_dtoa_r+0x6e4> - 80134dc: 4651 mov r1, sl - 80134de: 4620 mov r0, r4 - 80134e0: f000 fe82 bl 80141e8 <_Bfree> - 80134e4: 2300 movs r3, #0 - 80134e6: 9a0d ldr r2, [sp, #52] ; 0x34 - 80134e8: 702b strb r3, [r5, #0] - 80134ea: f10b 0301 add.w r3, fp, #1 - 80134ee: 6013 str r3, [r2, #0] - 80134f0: 9b21 ldr r3, [sp, #132] ; 0x84 - 80134f2: 2b00 cmp r3, #0 - 80134f4: f43f ace2 beq.w 8012ebc <_dtoa_r+0xa4> - 80134f8: 601d str r5, [r3, #0] - 80134fa: e4df b.n 8012ebc <_dtoa_r+0xa4> - 80134fc: 465f mov r7, fp - 80134fe: 462b mov r3, r5 - 8013500: 461d mov r5, r3 - 8013502: f813 2d01 ldrb.w r2, [r3, #-1]! - 8013506: 2a39 cmp r2, #57 ; 0x39 - 8013508: d106 bne.n 8013518 <_dtoa_r+0x700> - 801350a: 9a00 ldr r2, [sp, #0] - 801350c: 429a cmp r2, r3 - 801350e: d1f7 bne.n 8013500 <_dtoa_r+0x6e8> - 8013510: 9900 ldr r1, [sp, #0] - 8013512: 2230 movs r2, #48 ; 0x30 - 8013514: 3701 adds r7, #1 - 8013516: 700a strb r2, [r1, #0] - 8013518: 781a ldrb r2, [r3, #0] - 801351a: 3201 adds r2, #1 - 801351c: 701a strb r2, [r3, #0] - 801351e: e790 b.n 8013442 <_dtoa_r+0x62a> - 8013520: 4ba3 ldr r3, [pc, #652] ; (80137b0 <_dtoa_r+0x998>) - 8013522: 2200 movs r2, #0 - 8013524: f7ed f868 bl 80005f8 <__aeabi_dmul> - 8013528: 2200 movs r2, #0 - 801352a: 2300 movs r3, #0 - 801352c: 4606 mov r6, r0 - 801352e: 460f mov r7, r1 - 8013530: f7ed faca bl 8000ac8 <__aeabi_dcmpeq> - 8013534: 2800 cmp r0, #0 - 8013536: d09e beq.n 8013476 <_dtoa_r+0x65e> - 8013538: e7d0 b.n 80134dc <_dtoa_r+0x6c4> - 801353a: 9a09 ldr r2, [sp, #36] ; 0x24 - 801353c: 2a00 cmp r2, #0 - 801353e: f000 80ca beq.w 80136d6 <_dtoa_r+0x8be> - 8013542: 9a07 ldr r2, [sp, #28] - 8013544: 2a01 cmp r2, #1 - 8013546: f300 80ad bgt.w 80136a4 <_dtoa_r+0x88c> - 801354a: 9a0e ldr r2, [sp, #56] ; 0x38 - 801354c: 2a00 cmp r2, #0 - 801354e: f000 80a5 beq.w 801369c <_dtoa_r+0x884> - 8013552: f203 4333 addw r3, r3, #1075 ; 0x433 - 8013556: 9e08 ldr r6, [sp, #32] - 8013558: 9d05 ldr r5, [sp, #20] - 801355a: 9a05 ldr r2, [sp, #20] - 801355c: 441a add r2, r3 - 801355e: 9205 str r2, [sp, #20] - 8013560: 9a06 ldr r2, [sp, #24] - 8013562: 2101 movs r1, #1 - 8013564: 441a add r2, r3 - 8013566: 4620 mov r0, r4 - 8013568: 9206 str r2, [sp, #24] - 801356a: f000 ff3d bl 80143e8 <__i2b> - 801356e: 4607 mov r7, r0 - 8013570: b165 cbz r5, 801358c <_dtoa_r+0x774> - 8013572: 9b06 ldr r3, [sp, #24] - 8013574: 2b00 cmp r3, #0 - 8013576: dd09 ble.n 801358c <_dtoa_r+0x774> - 8013578: 42ab cmp r3, r5 - 801357a: 9a05 ldr r2, [sp, #20] - 801357c: bfa8 it ge - 801357e: 462b movge r3, r5 - 8013580: 1ad2 subs r2, r2, r3 - 8013582: 9205 str r2, [sp, #20] - 8013584: 9a06 ldr r2, [sp, #24] - 8013586: 1aed subs r5, r5, r3 - 8013588: 1ad3 subs r3, r2, r3 - 801358a: 9306 str r3, [sp, #24] - 801358c: 9b08 ldr r3, [sp, #32] - 801358e: b1f3 cbz r3, 80135ce <_dtoa_r+0x7b6> - 8013590: 9b09 ldr r3, [sp, #36] ; 0x24 - 8013592: 2b00 cmp r3, #0 - 8013594: f000 80a3 beq.w 80136de <_dtoa_r+0x8c6> - 8013598: 2e00 cmp r6, #0 - 801359a: dd10 ble.n 80135be <_dtoa_r+0x7a6> - 801359c: 4639 mov r1, r7 - 801359e: 4632 mov r2, r6 - 80135a0: 4620 mov r0, r4 - 80135a2: f000 ffe1 bl 8014568 <__pow5mult> - 80135a6: 4652 mov r2, sl - 80135a8: 4601 mov r1, r0 - 80135aa: 4607 mov r7, r0 - 80135ac: 4620 mov r0, r4 - 80135ae: f000 ff31 bl 8014414 <__multiply> - 80135b2: 4651 mov r1, sl - 80135b4: 4680 mov r8, r0 - 80135b6: 4620 mov r0, r4 - 80135b8: f000 fe16 bl 80141e8 <_Bfree> - 80135bc: 46c2 mov sl, r8 - 80135be: 9b08 ldr r3, [sp, #32] - 80135c0: 1b9a subs r2, r3, r6 - 80135c2: d004 beq.n 80135ce <_dtoa_r+0x7b6> - 80135c4: 4651 mov r1, sl - 80135c6: 4620 mov r0, r4 - 80135c8: f000 ffce bl 8014568 <__pow5mult> - 80135cc: 4682 mov sl, r0 - 80135ce: 2101 movs r1, #1 - 80135d0: 4620 mov r0, r4 - 80135d2: f000 ff09 bl 80143e8 <__i2b> - 80135d6: 9b0b ldr r3, [sp, #44] ; 0x2c - 80135d8: 2b00 cmp r3, #0 - 80135da: 4606 mov r6, r0 - 80135dc: f340 8081 ble.w 80136e2 <_dtoa_r+0x8ca> - 80135e0: 461a mov r2, r3 - 80135e2: 4601 mov r1, r0 - 80135e4: 4620 mov r0, r4 - 80135e6: f000 ffbf bl 8014568 <__pow5mult> - 80135ea: 9b07 ldr r3, [sp, #28] - 80135ec: 2b01 cmp r3, #1 - 80135ee: 4606 mov r6, r0 - 80135f0: dd7a ble.n 80136e8 <_dtoa_r+0x8d0> - 80135f2: f04f 0800 mov.w r8, #0 - 80135f6: 6933 ldr r3, [r6, #16] - 80135f8: eb06 0383 add.w r3, r6, r3, lsl #2 - 80135fc: 6918 ldr r0, [r3, #16] - 80135fe: f000 fea5 bl 801434c <__hi0bits> - 8013602: f1c0 0020 rsb r0, r0, #32 - 8013606: 9b06 ldr r3, [sp, #24] - 8013608: 4418 add r0, r3 - 801360a: f010 001f ands.w r0, r0, #31 - 801360e: f000 8094 beq.w 801373a <_dtoa_r+0x922> - 8013612: f1c0 0320 rsb r3, r0, #32 - 8013616: 2b04 cmp r3, #4 - 8013618: f340 8085 ble.w 8013726 <_dtoa_r+0x90e> - 801361c: 9b05 ldr r3, [sp, #20] - 801361e: f1c0 001c rsb r0, r0, #28 - 8013622: 4403 add r3, r0 - 8013624: 9305 str r3, [sp, #20] - 8013626: 9b06 ldr r3, [sp, #24] - 8013628: 4403 add r3, r0 - 801362a: 4405 add r5, r0 - 801362c: 9306 str r3, [sp, #24] - 801362e: 9b05 ldr r3, [sp, #20] - 8013630: 2b00 cmp r3, #0 - 8013632: dd05 ble.n 8013640 <_dtoa_r+0x828> - 8013634: 4651 mov r1, sl - 8013636: 461a mov r2, r3 - 8013638: 4620 mov r0, r4 - 801363a: f000 ffef bl 801461c <__lshift> - 801363e: 4682 mov sl, r0 - 8013640: 9b06 ldr r3, [sp, #24] - 8013642: 2b00 cmp r3, #0 - 8013644: dd05 ble.n 8013652 <_dtoa_r+0x83a> - 8013646: 4631 mov r1, r6 - 8013648: 461a mov r2, r3 - 801364a: 4620 mov r0, r4 - 801364c: f000 ffe6 bl 801461c <__lshift> - 8013650: 4606 mov r6, r0 - 8013652: 9b0c ldr r3, [sp, #48] ; 0x30 - 8013654: 2b00 cmp r3, #0 - 8013656: d072 beq.n 801373e <_dtoa_r+0x926> - 8013658: 4631 mov r1, r6 - 801365a: 4650 mov r0, sl - 801365c: f001 f84a bl 80146f4 <__mcmp> - 8013660: 2800 cmp r0, #0 - 8013662: da6c bge.n 801373e <_dtoa_r+0x926> - 8013664: 2300 movs r3, #0 - 8013666: 4651 mov r1, sl - 8013668: 220a movs r2, #10 - 801366a: 4620 mov r0, r4 - 801366c: f000 fdde bl 801422c <__multadd> - 8013670: 9b09 ldr r3, [sp, #36] ; 0x24 - 8013672: f10b 3bff add.w fp, fp, #4294967295 - 8013676: 4682 mov sl, r0 - 8013678: 2b00 cmp r3, #0 - 801367a: f000 81b0 beq.w 80139de <_dtoa_r+0xbc6> - 801367e: 2300 movs r3, #0 - 8013680: 4639 mov r1, r7 - 8013682: 220a movs r2, #10 - 8013684: 4620 mov r0, r4 - 8013686: f000 fdd1 bl 801422c <__multadd> - 801368a: 9b01 ldr r3, [sp, #4] - 801368c: 2b00 cmp r3, #0 - 801368e: 4607 mov r7, r0 - 8013690: f300 8096 bgt.w 80137c0 <_dtoa_r+0x9a8> - 8013694: 9b07 ldr r3, [sp, #28] - 8013696: 2b02 cmp r3, #2 - 8013698: dc59 bgt.n 801374e <_dtoa_r+0x936> - 801369a: e091 b.n 80137c0 <_dtoa_r+0x9a8> - 801369c: 9b10 ldr r3, [sp, #64] ; 0x40 - 801369e: f1c3 0336 rsb r3, r3, #54 ; 0x36 - 80136a2: e758 b.n 8013556 <_dtoa_r+0x73e> - 80136a4: 9b04 ldr r3, [sp, #16] - 80136a6: 1e5e subs r6, r3, #1 - 80136a8: 9b08 ldr r3, [sp, #32] - 80136aa: 42b3 cmp r3, r6 - 80136ac: bfbf itttt lt - 80136ae: 9b08 ldrlt r3, [sp, #32] - 80136b0: 9a0b ldrlt r2, [sp, #44] ; 0x2c - 80136b2: 9608 strlt r6, [sp, #32] - 80136b4: 1af3 sublt r3, r6, r3 - 80136b6: bfb4 ite lt - 80136b8: 18d2 addlt r2, r2, r3 - 80136ba: 1b9e subge r6, r3, r6 - 80136bc: 9b04 ldr r3, [sp, #16] - 80136be: bfbc itt lt - 80136c0: 920b strlt r2, [sp, #44] ; 0x2c - 80136c2: 2600 movlt r6, #0 - 80136c4: 2b00 cmp r3, #0 - 80136c6: bfb7 itett lt - 80136c8: e9dd 2304 ldrdlt r2, r3, [sp, #16] - 80136cc: e9dd 3504 ldrdge r3, r5, [sp, #16] - 80136d0: 1a9d sublt r5, r3, r2 - 80136d2: 2300 movlt r3, #0 - 80136d4: e741 b.n 801355a <_dtoa_r+0x742> - 80136d6: 9e08 ldr r6, [sp, #32] - 80136d8: 9d05 ldr r5, [sp, #20] - 80136da: 9f09 ldr r7, [sp, #36] ; 0x24 - 80136dc: e748 b.n 8013570 <_dtoa_r+0x758> - 80136de: 9a08 ldr r2, [sp, #32] - 80136e0: e770 b.n 80135c4 <_dtoa_r+0x7ac> - 80136e2: 9b07 ldr r3, [sp, #28] - 80136e4: 2b01 cmp r3, #1 - 80136e6: dc19 bgt.n 801371c <_dtoa_r+0x904> - 80136e8: 9b02 ldr r3, [sp, #8] - 80136ea: b9bb cbnz r3, 801371c <_dtoa_r+0x904> - 80136ec: 9b03 ldr r3, [sp, #12] - 80136ee: f3c3 0313 ubfx r3, r3, #0, #20 - 80136f2: b99b cbnz r3, 801371c <_dtoa_r+0x904> - 80136f4: 9b03 ldr r3, [sp, #12] - 80136f6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 - 80136fa: 0d1b lsrs r3, r3, #20 - 80136fc: 051b lsls r3, r3, #20 - 80136fe: b183 cbz r3, 8013722 <_dtoa_r+0x90a> - 8013700: 9b05 ldr r3, [sp, #20] - 8013702: 3301 adds r3, #1 - 8013704: 9305 str r3, [sp, #20] - 8013706: 9b06 ldr r3, [sp, #24] - 8013708: 3301 adds r3, #1 - 801370a: 9306 str r3, [sp, #24] - 801370c: f04f 0801 mov.w r8, #1 - 8013710: 9b0b ldr r3, [sp, #44] ; 0x2c - 8013712: 2b00 cmp r3, #0 - 8013714: f47f af6f bne.w 80135f6 <_dtoa_r+0x7de> - 8013718: 2001 movs r0, #1 - 801371a: e774 b.n 8013606 <_dtoa_r+0x7ee> - 801371c: f04f 0800 mov.w r8, #0 - 8013720: e7f6 b.n 8013710 <_dtoa_r+0x8f8> - 8013722: 4698 mov r8, r3 - 8013724: e7f4 b.n 8013710 <_dtoa_r+0x8f8> - 8013726: d082 beq.n 801362e <_dtoa_r+0x816> - 8013728: 9a05 ldr r2, [sp, #20] - 801372a: 331c adds r3, #28 - 801372c: 441a add r2, r3 - 801372e: 9205 str r2, [sp, #20] - 8013730: 9a06 ldr r2, [sp, #24] - 8013732: 441a add r2, r3 - 8013734: 441d add r5, r3 - 8013736: 9206 str r2, [sp, #24] - 8013738: e779 b.n 801362e <_dtoa_r+0x816> - 801373a: 4603 mov r3, r0 - 801373c: e7f4 b.n 8013728 <_dtoa_r+0x910> - 801373e: 9b04 ldr r3, [sp, #16] - 8013740: 2b00 cmp r3, #0 - 8013742: dc37 bgt.n 80137b4 <_dtoa_r+0x99c> - 8013744: 9b07 ldr r3, [sp, #28] - 8013746: 2b02 cmp r3, #2 - 8013748: dd34 ble.n 80137b4 <_dtoa_r+0x99c> - 801374a: 9b04 ldr r3, [sp, #16] - 801374c: 9301 str r3, [sp, #4] - 801374e: 9b01 ldr r3, [sp, #4] - 8013750: b963 cbnz r3, 801376c <_dtoa_r+0x954> - 8013752: 4631 mov r1, r6 - 8013754: 2205 movs r2, #5 - 8013756: 4620 mov r0, r4 - 8013758: f000 fd68 bl 801422c <__multadd> - 801375c: 4601 mov r1, r0 - 801375e: 4606 mov r6, r0 - 8013760: 4650 mov r0, sl - 8013762: f000 ffc7 bl 80146f4 <__mcmp> - 8013766: 2800 cmp r0, #0 - 8013768: f73f adbb bgt.w 80132e2 <_dtoa_r+0x4ca> - 801376c: 9b0a ldr r3, [sp, #40] ; 0x28 - 801376e: 9d00 ldr r5, [sp, #0] - 8013770: ea6f 0b03 mvn.w fp, r3 - 8013774: f04f 0800 mov.w r8, #0 - 8013778: 4631 mov r1, r6 - 801377a: 4620 mov r0, r4 - 801377c: f000 fd34 bl 80141e8 <_Bfree> - 8013780: 2f00 cmp r7, #0 - 8013782: f43f aeab beq.w 80134dc <_dtoa_r+0x6c4> - 8013786: f1b8 0f00 cmp.w r8, #0 - 801378a: d005 beq.n 8013798 <_dtoa_r+0x980> - 801378c: 45b8 cmp r8, r7 - 801378e: d003 beq.n 8013798 <_dtoa_r+0x980> - 8013790: 4641 mov r1, r8 - 8013792: 4620 mov r0, r4 - 8013794: f000 fd28 bl 80141e8 <_Bfree> - 8013798: 4639 mov r1, r7 - 801379a: 4620 mov r0, r4 - 801379c: f000 fd24 bl 80141e8 <_Bfree> - 80137a0: e69c b.n 80134dc <_dtoa_r+0x6c4> - 80137a2: 2600 movs r6, #0 - 80137a4: 4637 mov r7, r6 - 80137a6: e7e1 b.n 801376c <_dtoa_r+0x954> - 80137a8: 46bb mov fp, r7 - 80137aa: 4637 mov r7, r6 - 80137ac: e599 b.n 80132e2 <_dtoa_r+0x4ca> - 80137ae: bf00 nop - 80137b0: 40240000 .word 0x40240000 - 80137b4: 9b09 ldr r3, [sp, #36] ; 0x24 - 80137b6: 2b00 cmp r3, #0 - 80137b8: f000 80c8 beq.w 801394c <_dtoa_r+0xb34> - 80137bc: 9b04 ldr r3, [sp, #16] - 80137be: 9301 str r3, [sp, #4] - 80137c0: 2d00 cmp r5, #0 - 80137c2: dd05 ble.n 80137d0 <_dtoa_r+0x9b8> - 80137c4: 4639 mov r1, r7 - 80137c6: 462a mov r2, r5 - 80137c8: 4620 mov r0, r4 - 80137ca: f000 ff27 bl 801461c <__lshift> - 80137ce: 4607 mov r7, r0 - 80137d0: f1b8 0f00 cmp.w r8, #0 - 80137d4: d05b beq.n 801388e <_dtoa_r+0xa76> - 80137d6: 6879 ldr r1, [r7, #4] - 80137d8: 4620 mov r0, r4 - 80137da: f000 fcc5 bl 8014168 <_Balloc> - 80137de: 4605 mov r5, r0 - 80137e0: b928 cbnz r0, 80137ee <_dtoa_r+0x9d6> - 80137e2: 4b83 ldr r3, [pc, #524] ; (80139f0 <_dtoa_r+0xbd8>) - 80137e4: 4602 mov r2, r0 - 80137e6: f240 21ef movw r1, #751 ; 0x2ef - 80137ea: f7ff bb2e b.w 8012e4a <_dtoa_r+0x32> - 80137ee: 693a ldr r2, [r7, #16] - 80137f0: 3202 adds r2, #2 - 80137f2: 0092 lsls r2, r2, #2 - 80137f4: f107 010c add.w r1, r7, #12 - 80137f8: 300c adds r0, #12 - 80137fa: f7ff fa4a bl 8012c92 - 80137fe: 2201 movs r2, #1 - 8013800: 4629 mov r1, r5 - 8013802: 4620 mov r0, r4 - 8013804: f000 ff0a bl 801461c <__lshift> - 8013808: 9b00 ldr r3, [sp, #0] - 801380a: 3301 adds r3, #1 - 801380c: 9304 str r3, [sp, #16] - 801380e: e9dd 2300 ldrd r2, r3, [sp] - 8013812: 4413 add r3, r2 - 8013814: 9308 str r3, [sp, #32] - 8013816: 9b02 ldr r3, [sp, #8] - 8013818: f003 0301 and.w r3, r3, #1 - 801381c: 46b8 mov r8, r7 - 801381e: 9306 str r3, [sp, #24] - 8013820: 4607 mov r7, r0 - 8013822: 9b04 ldr r3, [sp, #16] - 8013824: 4631 mov r1, r6 - 8013826: 3b01 subs r3, #1 - 8013828: 4650 mov r0, sl - 801382a: 9301 str r3, [sp, #4] - 801382c: f7ff fa6c bl 8012d08 - 8013830: 4641 mov r1, r8 - 8013832: 9002 str r0, [sp, #8] - 8013834: f100 0930 add.w r9, r0, #48 ; 0x30 - 8013838: 4650 mov r0, sl - 801383a: f000 ff5b bl 80146f4 <__mcmp> - 801383e: 463a mov r2, r7 - 8013840: 9005 str r0, [sp, #20] - 8013842: 4631 mov r1, r6 - 8013844: 4620 mov r0, r4 - 8013846: f000 ff71 bl 801472c <__mdiff> - 801384a: 68c2 ldr r2, [r0, #12] - 801384c: 4605 mov r5, r0 - 801384e: bb02 cbnz r2, 8013892 <_dtoa_r+0xa7a> - 8013850: 4601 mov r1, r0 - 8013852: 4650 mov r0, sl - 8013854: f000 ff4e bl 80146f4 <__mcmp> - 8013858: 4602 mov r2, r0 - 801385a: 4629 mov r1, r5 - 801385c: 4620 mov r0, r4 - 801385e: 9209 str r2, [sp, #36] ; 0x24 - 8013860: f000 fcc2 bl 80141e8 <_Bfree> - 8013864: 9b07 ldr r3, [sp, #28] - 8013866: 9a09 ldr r2, [sp, #36] ; 0x24 - 8013868: 9d04 ldr r5, [sp, #16] - 801386a: ea43 0102 orr.w r1, r3, r2 - 801386e: 9b06 ldr r3, [sp, #24] - 8013870: 4319 orrs r1, r3 - 8013872: d110 bne.n 8013896 <_dtoa_r+0xa7e> - 8013874: f1b9 0f39 cmp.w r9, #57 ; 0x39 - 8013878: d029 beq.n 80138ce <_dtoa_r+0xab6> - 801387a: 9b05 ldr r3, [sp, #20] - 801387c: 2b00 cmp r3, #0 - 801387e: dd02 ble.n 8013886 <_dtoa_r+0xa6e> - 8013880: 9b02 ldr r3, [sp, #8] - 8013882: f103 0931 add.w r9, r3, #49 ; 0x31 - 8013886: 9b01 ldr r3, [sp, #4] - 8013888: f883 9000 strb.w r9, [r3] - 801388c: e774 b.n 8013778 <_dtoa_r+0x960> - 801388e: 4638 mov r0, r7 - 8013890: e7ba b.n 8013808 <_dtoa_r+0x9f0> - 8013892: 2201 movs r2, #1 - 8013894: e7e1 b.n 801385a <_dtoa_r+0xa42> - 8013896: 9b05 ldr r3, [sp, #20] - 8013898: 2b00 cmp r3, #0 - 801389a: db04 blt.n 80138a6 <_dtoa_r+0xa8e> - 801389c: 9907 ldr r1, [sp, #28] - 801389e: 430b orrs r3, r1 - 80138a0: 9906 ldr r1, [sp, #24] - 80138a2: 430b orrs r3, r1 - 80138a4: d120 bne.n 80138e8 <_dtoa_r+0xad0> - 80138a6: 2a00 cmp r2, #0 - 80138a8: dded ble.n 8013886 <_dtoa_r+0xa6e> - 80138aa: 4651 mov r1, sl - 80138ac: 2201 movs r2, #1 - 80138ae: 4620 mov r0, r4 - 80138b0: f000 feb4 bl 801461c <__lshift> - 80138b4: 4631 mov r1, r6 - 80138b6: 4682 mov sl, r0 - 80138b8: f000 ff1c bl 80146f4 <__mcmp> - 80138bc: 2800 cmp r0, #0 - 80138be: dc03 bgt.n 80138c8 <_dtoa_r+0xab0> - 80138c0: d1e1 bne.n 8013886 <_dtoa_r+0xa6e> - 80138c2: f019 0f01 tst.w r9, #1 - 80138c6: d0de beq.n 8013886 <_dtoa_r+0xa6e> - 80138c8: f1b9 0f39 cmp.w r9, #57 ; 0x39 - 80138cc: d1d8 bne.n 8013880 <_dtoa_r+0xa68> - 80138ce: 9a01 ldr r2, [sp, #4] - 80138d0: 2339 movs r3, #57 ; 0x39 - 80138d2: 7013 strb r3, [r2, #0] - 80138d4: 462b mov r3, r5 - 80138d6: 461d mov r5, r3 - 80138d8: 3b01 subs r3, #1 - 80138da: f815 2c01 ldrb.w r2, [r5, #-1] - 80138de: 2a39 cmp r2, #57 ; 0x39 - 80138e0: d06c beq.n 80139bc <_dtoa_r+0xba4> - 80138e2: 3201 adds r2, #1 - 80138e4: 701a strb r2, [r3, #0] - 80138e6: e747 b.n 8013778 <_dtoa_r+0x960> - 80138e8: 2a00 cmp r2, #0 - 80138ea: dd07 ble.n 80138fc <_dtoa_r+0xae4> - 80138ec: f1b9 0f39 cmp.w r9, #57 ; 0x39 - 80138f0: d0ed beq.n 80138ce <_dtoa_r+0xab6> - 80138f2: 9a01 ldr r2, [sp, #4] - 80138f4: f109 0301 add.w r3, r9, #1 - 80138f8: 7013 strb r3, [r2, #0] - 80138fa: e73d b.n 8013778 <_dtoa_r+0x960> - 80138fc: 9b04 ldr r3, [sp, #16] - 80138fe: 9a08 ldr r2, [sp, #32] - 8013900: f803 9c01 strb.w r9, [r3, #-1] - 8013904: 4293 cmp r3, r2 - 8013906: d043 beq.n 8013990 <_dtoa_r+0xb78> - 8013908: 4651 mov r1, sl - 801390a: 2300 movs r3, #0 - 801390c: 220a movs r2, #10 - 801390e: 4620 mov r0, r4 - 8013910: f000 fc8c bl 801422c <__multadd> - 8013914: 45b8 cmp r8, r7 - 8013916: 4682 mov sl, r0 - 8013918: f04f 0300 mov.w r3, #0 - 801391c: f04f 020a mov.w r2, #10 - 8013920: 4641 mov r1, r8 - 8013922: 4620 mov r0, r4 - 8013924: d107 bne.n 8013936 <_dtoa_r+0xb1e> - 8013926: f000 fc81 bl 801422c <__multadd> - 801392a: 4680 mov r8, r0 - 801392c: 4607 mov r7, r0 - 801392e: 9b04 ldr r3, [sp, #16] - 8013930: 3301 adds r3, #1 - 8013932: 9304 str r3, [sp, #16] - 8013934: e775 b.n 8013822 <_dtoa_r+0xa0a> - 8013936: f000 fc79 bl 801422c <__multadd> - 801393a: 4639 mov r1, r7 - 801393c: 4680 mov r8, r0 - 801393e: 2300 movs r3, #0 - 8013940: 220a movs r2, #10 - 8013942: 4620 mov r0, r4 - 8013944: f000 fc72 bl 801422c <__multadd> - 8013948: 4607 mov r7, r0 - 801394a: e7f0 b.n 801392e <_dtoa_r+0xb16> - 801394c: 9b04 ldr r3, [sp, #16] - 801394e: 9301 str r3, [sp, #4] - 8013950: 9d00 ldr r5, [sp, #0] - 8013952: 4631 mov r1, r6 - 8013954: 4650 mov r0, sl - 8013956: f7ff f9d7 bl 8012d08 - 801395a: f100 0930 add.w r9, r0, #48 ; 0x30 - 801395e: 9b00 ldr r3, [sp, #0] - 8013960: f805 9b01 strb.w r9, [r5], #1 - 8013964: 1aea subs r2, r5, r3 - 8013966: 9b01 ldr r3, [sp, #4] - 8013968: 4293 cmp r3, r2 - 801396a: dd07 ble.n 801397c <_dtoa_r+0xb64> - 801396c: 4651 mov r1, sl - 801396e: 2300 movs r3, #0 - 8013970: 220a movs r2, #10 - 8013972: 4620 mov r0, r4 - 8013974: f000 fc5a bl 801422c <__multadd> - 8013978: 4682 mov sl, r0 - 801397a: e7ea b.n 8013952 <_dtoa_r+0xb3a> - 801397c: 9b01 ldr r3, [sp, #4] - 801397e: 2b00 cmp r3, #0 - 8013980: bfc8 it gt - 8013982: 461d movgt r5, r3 - 8013984: 9b00 ldr r3, [sp, #0] - 8013986: bfd8 it le - 8013988: 2501 movle r5, #1 - 801398a: 441d add r5, r3 - 801398c: f04f 0800 mov.w r8, #0 - 8013990: 4651 mov r1, sl - 8013992: 2201 movs r2, #1 - 8013994: 4620 mov r0, r4 - 8013996: f000 fe41 bl 801461c <__lshift> - 801399a: 4631 mov r1, r6 - 801399c: 4682 mov sl, r0 - 801399e: f000 fea9 bl 80146f4 <__mcmp> - 80139a2: 2800 cmp r0, #0 - 80139a4: dc96 bgt.n 80138d4 <_dtoa_r+0xabc> - 80139a6: d102 bne.n 80139ae <_dtoa_r+0xb96> - 80139a8: f019 0f01 tst.w r9, #1 - 80139ac: d192 bne.n 80138d4 <_dtoa_r+0xabc> - 80139ae: 462b mov r3, r5 - 80139b0: 461d mov r5, r3 - 80139b2: f813 2d01 ldrb.w r2, [r3, #-1]! - 80139b6: 2a30 cmp r2, #48 ; 0x30 - 80139b8: d0fa beq.n 80139b0 <_dtoa_r+0xb98> - 80139ba: e6dd b.n 8013778 <_dtoa_r+0x960> - 80139bc: 9a00 ldr r2, [sp, #0] - 80139be: 429a cmp r2, r3 - 80139c0: d189 bne.n 80138d6 <_dtoa_r+0xabe> - 80139c2: f10b 0b01 add.w fp, fp, #1 - 80139c6: 2331 movs r3, #49 ; 0x31 - 80139c8: e796 b.n 80138f8 <_dtoa_r+0xae0> - 80139ca: 4b0a ldr r3, [pc, #40] ; (80139f4 <_dtoa_r+0xbdc>) - 80139cc: f7ff ba99 b.w 8012f02 <_dtoa_r+0xea> - 80139d0: 9b21 ldr r3, [sp, #132] ; 0x84 - 80139d2: 2b00 cmp r3, #0 - 80139d4: f47f aa6d bne.w 8012eb2 <_dtoa_r+0x9a> - 80139d8: 4b07 ldr r3, [pc, #28] ; (80139f8 <_dtoa_r+0xbe0>) - 80139da: f7ff ba92 b.w 8012f02 <_dtoa_r+0xea> - 80139de: 9b01 ldr r3, [sp, #4] - 80139e0: 2b00 cmp r3, #0 - 80139e2: dcb5 bgt.n 8013950 <_dtoa_r+0xb38> - 80139e4: 9b07 ldr r3, [sp, #28] - 80139e6: 2b02 cmp r3, #2 - 80139e8: f73f aeb1 bgt.w 801374e <_dtoa_r+0x936> - 80139ec: e7b0 b.n 8013950 <_dtoa_r+0xb38> - 80139ee: bf00 nop - 80139f0: 080189bc .word 0x080189bc - 80139f4: 08018879 .word 0x08018879 - 80139f8: 08018957 .word 0x08018957 - -080139fc <_free_r>: - 80139fc: b537 push {r0, r1, r2, r4, r5, lr} - 80139fe: 2900 cmp r1, #0 - 8013a00: d044 beq.n 8013a8c <_free_r+0x90> - 8013a02: f851 3c04 ldr.w r3, [r1, #-4] - 8013a06: 9001 str r0, [sp, #4] - 8013a08: 2b00 cmp r3, #0 - 8013a0a: f1a1 0404 sub.w r4, r1, #4 - 8013a0e: bfb8 it lt - 8013a10: 18e4 addlt r4, r4, r3 - 8013a12: f7fd f93f bl 8010c94 <__malloc_lock> - 8013a16: 4a1e ldr r2, [pc, #120] ; (8013a90 <_free_r+0x94>) - 8013a18: 9801 ldr r0, [sp, #4] - 8013a1a: 6813 ldr r3, [r2, #0] - 8013a1c: b933 cbnz r3, 8013a2c <_free_r+0x30> - 8013a1e: 6063 str r3, [r4, #4] - 8013a20: 6014 str r4, [r2, #0] - 8013a22: b003 add sp, #12 - 8013a24: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8013a28: f7fd b93a b.w 8010ca0 <__malloc_unlock> - 8013a2c: 42a3 cmp r3, r4 - 8013a2e: d908 bls.n 8013a42 <_free_r+0x46> - 8013a30: 6825 ldr r5, [r4, #0] - 8013a32: 1961 adds r1, r4, r5 - 8013a34: 428b cmp r3, r1 - 8013a36: bf01 itttt eq - 8013a38: 6819 ldreq r1, [r3, #0] - 8013a3a: 685b ldreq r3, [r3, #4] - 8013a3c: 1949 addeq r1, r1, r5 - 8013a3e: 6021 streq r1, [r4, #0] - 8013a40: e7ed b.n 8013a1e <_free_r+0x22> - 8013a42: 461a mov r2, r3 - 8013a44: 685b ldr r3, [r3, #4] - 8013a46: b10b cbz r3, 8013a4c <_free_r+0x50> - 8013a48: 42a3 cmp r3, r4 - 8013a4a: d9fa bls.n 8013a42 <_free_r+0x46> - 8013a4c: 6811 ldr r1, [r2, #0] - 8013a4e: 1855 adds r5, r2, r1 - 8013a50: 42a5 cmp r5, r4 - 8013a52: d10b bne.n 8013a6c <_free_r+0x70> - 8013a54: 6824 ldr r4, [r4, #0] - 8013a56: 4421 add r1, r4 - 8013a58: 1854 adds r4, r2, r1 - 8013a5a: 42a3 cmp r3, r4 - 8013a5c: 6011 str r1, [r2, #0] - 8013a5e: d1e0 bne.n 8013a22 <_free_r+0x26> - 8013a60: 681c ldr r4, [r3, #0] - 8013a62: 685b ldr r3, [r3, #4] - 8013a64: 6053 str r3, [r2, #4] - 8013a66: 440c add r4, r1 - 8013a68: 6014 str r4, [r2, #0] - 8013a6a: e7da b.n 8013a22 <_free_r+0x26> - 8013a6c: d902 bls.n 8013a74 <_free_r+0x78> - 8013a6e: 230c movs r3, #12 - 8013a70: 6003 str r3, [r0, #0] - 8013a72: e7d6 b.n 8013a22 <_free_r+0x26> - 8013a74: 6825 ldr r5, [r4, #0] - 8013a76: 1961 adds r1, r4, r5 - 8013a78: 428b cmp r3, r1 - 8013a7a: bf04 itt eq - 8013a7c: 6819 ldreq r1, [r3, #0] - 8013a7e: 685b ldreq r3, [r3, #4] - 8013a80: 6063 str r3, [r4, #4] - 8013a82: bf04 itt eq - 8013a84: 1949 addeq r1, r1, r5 - 8013a86: 6021 streq r1, [r4, #0] - 8013a88: 6054 str r4, [r2, #4] - 8013a8a: e7ca b.n 8013a22 <_free_r+0x26> - 8013a8c: b003 add sp, #12 - 8013a8e: bd30 pop {r4, r5, pc} - 8013a90: 2000148c .word 0x2000148c - -08013a94 : - 8013a94: 6903 ldr r3, [r0, #16] - 8013a96: ebb3 1f61 cmp.w r3, r1, asr #5 - 8013a9a: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} - 8013a9e: ea4f 1261 mov.w r2, r1, asr #5 - 8013aa2: f100 0414 add.w r4, r0, #20 - 8013aa6: dd45 ble.n 8013b34 - 8013aa8: f011 011f ands.w r1, r1, #31 - 8013aac: eb04 0683 add.w r6, r4, r3, lsl #2 - 8013ab0: eb04 0582 add.w r5, r4, r2, lsl #2 - 8013ab4: d10c bne.n 8013ad0 - 8013ab6: f100 0710 add.w r7, r0, #16 - 8013aba: 4629 mov r1, r5 - 8013abc: 42b1 cmp r1, r6 - 8013abe: d334 bcc.n 8013b2a - 8013ac0: 1a9b subs r3, r3, r2 - 8013ac2: 009b lsls r3, r3, #2 - 8013ac4: 1eea subs r2, r5, #3 - 8013ac6: 4296 cmp r6, r2 - 8013ac8: bf38 it cc - 8013aca: 2300 movcc r3, #0 - 8013acc: 4423 add r3, r4 - 8013ace: e015 b.n 8013afc - 8013ad0: f854 7022 ldr.w r7, [r4, r2, lsl #2] - 8013ad4: f1c1 0820 rsb r8, r1, #32 - 8013ad8: 40cf lsrs r7, r1 - 8013ada: f105 0e04 add.w lr, r5, #4 - 8013ade: 46a1 mov r9, r4 - 8013ae0: 4576 cmp r6, lr - 8013ae2: 46f4 mov ip, lr - 8013ae4: d815 bhi.n 8013b12 - 8013ae6: 1a9a subs r2, r3, r2 - 8013ae8: 0092 lsls r2, r2, #2 - 8013aea: 3a04 subs r2, #4 - 8013aec: 3501 adds r5, #1 - 8013aee: 42ae cmp r6, r5 - 8013af0: bf38 it cc - 8013af2: 2200 movcc r2, #0 - 8013af4: 18a3 adds r3, r4, r2 - 8013af6: 50a7 str r7, [r4, r2] - 8013af8: b107 cbz r7, 8013afc - 8013afa: 3304 adds r3, #4 - 8013afc: 1b1a subs r2, r3, r4 - 8013afe: 42a3 cmp r3, r4 - 8013b00: ea4f 02a2 mov.w r2, r2, asr #2 - 8013b04: bf08 it eq - 8013b06: 2300 moveq r3, #0 - 8013b08: 6102 str r2, [r0, #16] - 8013b0a: bf08 it eq - 8013b0c: 6143 streq r3, [r0, #20] - 8013b0e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} - 8013b12: f8dc c000 ldr.w ip, [ip] - 8013b16: fa0c fc08 lsl.w ip, ip, r8 - 8013b1a: ea4c 0707 orr.w r7, ip, r7 - 8013b1e: f849 7b04 str.w r7, [r9], #4 - 8013b22: f85e 7b04 ldr.w r7, [lr], #4 - 8013b26: 40cf lsrs r7, r1 - 8013b28: e7da b.n 8013ae0 - 8013b2a: f851 cb04 ldr.w ip, [r1], #4 - 8013b2e: f847 cf04 str.w ip, [r7, #4]! - 8013b32: e7c3 b.n 8013abc - 8013b34: 4623 mov r3, r4 - 8013b36: e7e1 b.n 8013afc - -08013b38 <__hexdig_fun>: - 8013b38: f1a0 0330 sub.w r3, r0, #48 ; 0x30 - 8013b3c: 2b09 cmp r3, #9 - 8013b3e: d802 bhi.n 8013b46 <__hexdig_fun+0xe> - 8013b40: 3820 subs r0, #32 - 8013b42: b2c0 uxtb r0, r0 - 8013b44: 4770 bx lr - 8013b46: f1a0 0361 sub.w r3, r0, #97 ; 0x61 - 8013b4a: 2b05 cmp r3, #5 - 8013b4c: d801 bhi.n 8013b52 <__hexdig_fun+0x1a> - 8013b4e: 3847 subs r0, #71 ; 0x47 - 8013b50: e7f7 b.n 8013b42 <__hexdig_fun+0xa> - 8013b52: f1a0 0341 sub.w r3, r0, #65 ; 0x41 - 8013b56: 2b05 cmp r3, #5 - 8013b58: d801 bhi.n 8013b5e <__hexdig_fun+0x26> - 8013b5a: 3827 subs r0, #39 ; 0x27 - 8013b5c: e7f1 b.n 8013b42 <__hexdig_fun+0xa> - 8013b5e: 2000 movs r0, #0 - 8013b60: 4770 bx lr +08015160 : + 8015160: ed9f 0b01 vldr d0, [pc, #4] ; 8015168 + 8015164: 4770 bx lr + 8015166: bf00 nop + 8015168: 00000000 .word 0x00000000 + 801516c: 7ff80000 .word 0x7ff80000 + +08015170 : + 8015170: ed9f 0a01 vldr s0, [pc, #4] ; 8015178 + 8015174: 4770 bx lr + 8015176: bf00 nop + 8015178: 7fc00000 .word 0x7fc00000 + +0801517c <__assert_func>: + 801517c: b51f push {r0, r1, r2, r3, r4, lr} + 801517e: 4614 mov r4, r2 + 8015180: 461a mov r2, r3 + 8015182: 4b09 ldr r3, [pc, #36] ; (80151a8 <__assert_func+0x2c>) + 8015184: 681b ldr r3, [r3, #0] + 8015186: 4605 mov r5, r0 + 8015188: 68d8 ldr r0, [r3, #12] + 801518a: b14c cbz r4, 80151a0 <__assert_func+0x24> + 801518c: 4b07 ldr r3, [pc, #28] ; (80151ac <__assert_func+0x30>) + 801518e: 9100 str r1, [sp, #0] + 8015190: e9cd 3401 strd r3, r4, [sp, #4] + 8015194: 4906 ldr r1, [pc, #24] ; (80151b0 <__assert_func+0x34>) + 8015196: 462b mov r3, r5 + 8015198: f002 f8fe bl 8017398 + 801519c: f002 f928 bl 80173f0 + 80151a0: 4b04 ldr r3, [pc, #16] ; (80151b4 <__assert_func+0x38>) + 80151a2: 461c mov r4, r3 + 80151a4: e7f3 b.n 801518e <__assert_func+0x12> + 80151a6: bf00 nop + 80151a8: 200002f0 .word 0x200002f0 + 80151ac: 0801adf3 .word 0x0801adf3 + 80151b0: 0801ae00 .word 0x0801ae00 + 80151b4: 0801ae2e .word 0x0801ae2e + +080151b8 : + 80151b8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80151bc: 6903 ldr r3, [r0, #16] + 80151be: 690c ldr r4, [r1, #16] + 80151c0: 42a3 cmp r3, r4 + 80151c2: 4607 mov r7, r0 + 80151c4: db7e blt.n 80152c4 + 80151c6: 3c01 subs r4, #1 + 80151c8: f101 0814 add.w r8, r1, #20 + 80151cc: f100 0514 add.w r5, r0, #20 + 80151d0: eb05 0384 add.w r3, r5, r4, lsl #2 + 80151d4: 9301 str r3, [sp, #4] + 80151d6: f858 3024 ldr.w r3, [r8, r4, lsl #2] + 80151da: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 80151de: 3301 adds r3, #1 + 80151e0: 429a cmp r2, r3 + 80151e2: ea4f 0b84 mov.w fp, r4, lsl #2 + 80151e6: eb08 0984 add.w r9, r8, r4, lsl #2 + 80151ea: fbb2 f6f3 udiv r6, r2, r3 + 80151ee: d331 bcc.n 8015254 + 80151f0: f04f 0e00 mov.w lr, #0 + 80151f4: 4640 mov r0, r8 + 80151f6: 46ac mov ip, r5 + 80151f8: 46f2 mov sl, lr + 80151fa: f850 2b04 ldr.w r2, [r0], #4 + 80151fe: b293 uxth r3, r2 + 8015200: fb06 e303 mla r3, r6, r3, lr + 8015204: ea4f 4e12 mov.w lr, r2, lsr #16 + 8015208: 0c1a lsrs r2, r3, #16 + 801520a: b29b uxth r3, r3 + 801520c: ebaa 0303 sub.w r3, sl, r3 + 8015210: f8dc a000 ldr.w sl, [ip] + 8015214: fa13 f38a uxtah r3, r3, sl + 8015218: fb06 220e mla r2, r6, lr, r2 + 801521c: 9300 str r3, [sp, #0] + 801521e: 9b00 ldr r3, [sp, #0] + 8015220: ea4f 4e12 mov.w lr, r2, lsr #16 + 8015224: b292 uxth r2, r2 + 8015226: ebc2 421a rsb r2, r2, sl, lsr #16 + 801522a: eb02 4223 add.w r2, r2, r3, asr #16 + 801522e: f8bd 3000 ldrh.w r3, [sp] + 8015232: 4581 cmp r9, r0 + 8015234: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8015238: f84c 3b04 str.w r3, [ip], #4 + 801523c: ea4f 4a22 mov.w sl, r2, asr #16 + 8015240: d2db bcs.n 80151fa + 8015242: f855 300b ldr.w r3, [r5, fp] + 8015246: b92b cbnz r3, 8015254 + 8015248: 9b01 ldr r3, [sp, #4] + 801524a: 3b04 subs r3, #4 + 801524c: 429d cmp r5, r3 + 801524e: 461a mov r2, r3 + 8015250: d32c bcc.n 80152ac + 8015252: 613c str r4, [r7, #16] + 8015254: 4638 mov r0, r7 + 8015256: f001 fca5 bl 8016ba4 <__mcmp> + 801525a: 2800 cmp r0, #0 + 801525c: db22 blt.n 80152a4 + 801525e: 3601 adds r6, #1 + 8015260: 4629 mov r1, r5 + 8015262: 2000 movs r0, #0 + 8015264: f858 2b04 ldr.w r2, [r8], #4 + 8015268: f8d1 c000 ldr.w ip, [r1] + 801526c: b293 uxth r3, r2 + 801526e: 1ac3 subs r3, r0, r3 + 8015270: 0c12 lsrs r2, r2, #16 + 8015272: fa13 f38c uxtah r3, r3, ip + 8015276: ebc2 421c rsb r2, r2, ip, lsr #16 + 801527a: eb02 4223 add.w r2, r2, r3, asr #16 + 801527e: b29b uxth r3, r3 + 8015280: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8015284: 45c1 cmp r9, r8 + 8015286: f841 3b04 str.w r3, [r1], #4 + 801528a: ea4f 4022 mov.w r0, r2, asr #16 + 801528e: d2e9 bcs.n 8015264 + 8015290: f855 2024 ldr.w r2, [r5, r4, lsl #2] + 8015294: eb05 0384 add.w r3, r5, r4, lsl #2 + 8015298: b922 cbnz r2, 80152a4 + 801529a: 3b04 subs r3, #4 + 801529c: 429d cmp r5, r3 + 801529e: 461a mov r2, r3 + 80152a0: d30a bcc.n 80152b8 + 80152a2: 613c str r4, [r7, #16] + 80152a4: 4630 mov r0, r6 + 80152a6: b003 add sp, #12 + 80152a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80152ac: 6812 ldr r2, [r2, #0] + 80152ae: 3b04 subs r3, #4 + 80152b0: 2a00 cmp r2, #0 + 80152b2: d1ce bne.n 8015252 + 80152b4: 3c01 subs r4, #1 + 80152b6: e7c9 b.n 801524c + 80152b8: 6812 ldr r2, [r2, #0] + 80152ba: 3b04 subs r3, #4 + 80152bc: 2a00 cmp r2, #0 + 80152be: d1f0 bne.n 80152a2 + 80152c0: 3c01 subs r4, #1 + 80152c2: e7eb b.n 801529c + 80152c4: 2000 movs r0, #0 + 80152c6: e7ee b.n 80152a6 + +080152c8 <_dtoa_r>: + 80152c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80152cc: ed2d 8b04 vpush {d8-d9} + 80152d0: 69c5 ldr r5, [r0, #28] + 80152d2: b093 sub sp, #76 ; 0x4c + 80152d4: ed8d 0b02 vstr d0, [sp, #8] + 80152d8: ec57 6b10 vmov r6, r7, d0 + 80152dc: f8dd 8080 ldr.w r8, [sp, #128] ; 0x80 + 80152e0: 9107 str r1, [sp, #28] + 80152e2: 4604 mov r4, r0 + 80152e4: 920a str r2, [sp, #40] ; 0x28 + 80152e6: 930d str r3, [sp, #52] ; 0x34 + 80152e8: b975 cbnz r5, 8015308 <_dtoa_r+0x40> + 80152ea: 2010 movs r0, #16 + 80152ec: f7fd fe7a bl 8012fe4 + 80152f0: 4602 mov r2, r0 + 80152f2: 61e0 str r0, [r4, #28] + 80152f4: b920 cbnz r0, 8015300 <_dtoa_r+0x38> + 80152f6: 4bae ldr r3, [pc, #696] ; (80155b0 <_dtoa_r+0x2e8>) + 80152f8: 21ef movs r1, #239 ; 0xef + 80152fa: 48ae ldr r0, [pc, #696] ; (80155b4 <_dtoa_r+0x2ec>) + 80152fc: f7ff ff3e bl 801517c <__assert_func> + 8015300: e9c0 5501 strd r5, r5, [r0, #4] + 8015304: 6005 str r5, [r0, #0] + 8015306: 60c5 str r5, [r0, #12] + 8015308: 69e3 ldr r3, [r4, #28] + 801530a: 6819 ldr r1, [r3, #0] + 801530c: b151 cbz r1, 8015324 <_dtoa_r+0x5c> + 801530e: 685a ldr r2, [r3, #4] + 8015310: 604a str r2, [r1, #4] + 8015312: 2301 movs r3, #1 + 8015314: 4093 lsls r3, r2 + 8015316: 608b str r3, [r1, #8] + 8015318: 4620 mov r0, r4 + 801531a: f001 f9bd bl 8016698 <_Bfree> + 801531e: 69e3 ldr r3, [r4, #28] + 8015320: 2200 movs r2, #0 + 8015322: 601a str r2, [r3, #0] + 8015324: 1e3b subs r3, r7, #0 + 8015326: bfbb ittet lt + 8015328: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 + 801532c: 9303 strlt r3, [sp, #12] + 801532e: 2300 movge r3, #0 + 8015330: 2201 movlt r2, #1 + 8015332: bfac ite ge + 8015334: f8c8 3000 strge.w r3, [r8] + 8015338: f8c8 2000 strlt.w r2, [r8] + 801533c: 4b9e ldr r3, [pc, #632] ; (80155b8 <_dtoa_r+0x2f0>) + 801533e: f8dd 800c ldr.w r8, [sp, #12] + 8015342: ea33 0308 bics.w r3, r3, r8 + 8015346: d11b bne.n 8015380 <_dtoa_r+0xb8> + 8015348: 9a0d ldr r2, [sp, #52] ; 0x34 + 801534a: f242 730f movw r3, #9999 ; 0x270f + 801534e: 6013 str r3, [r2, #0] + 8015350: f3c8 0313 ubfx r3, r8, #0, #20 + 8015354: 4333 orrs r3, r6 + 8015356: f000 8593 beq.w 8015e80 <_dtoa_r+0xbb8> + 801535a: 9b21 ldr r3, [sp, #132] ; 0x84 + 801535c: b963 cbnz r3, 8015378 <_dtoa_r+0xb0> + 801535e: 4b97 ldr r3, [pc, #604] ; (80155bc <_dtoa_r+0x2f4>) + 8015360: e027 b.n 80153b2 <_dtoa_r+0xea> + 8015362: 4b97 ldr r3, [pc, #604] ; (80155c0 <_dtoa_r+0x2f8>) + 8015364: 9300 str r3, [sp, #0] + 8015366: 3308 adds r3, #8 + 8015368: 9a21 ldr r2, [sp, #132] ; 0x84 + 801536a: 6013 str r3, [r2, #0] + 801536c: 9800 ldr r0, [sp, #0] + 801536e: b013 add sp, #76 ; 0x4c + 8015370: ecbd 8b04 vpop {d8-d9} + 8015374: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8015378: 4b90 ldr r3, [pc, #576] ; (80155bc <_dtoa_r+0x2f4>) + 801537a: 9300 str r3, [sp, #0] + 801537c: 3303 adds r3, #3 + 801537e: e7f3 b.n 8015368 <_dtoa_r+0xa0> + 8015380: ed9d 7b02 vldr d7, [sp, #8] + 8015384: 2200 movs r2, #0 + 8015386: ec51 0b17 vmov r0, r1, d7 + 801538a: eeb0 8a47 vmov.f32 s16, s14 + 801538e: eef0 8a67 vmov.f32 s17, s15 + 8015392: 2300 movs r3, #0 + 8015394: f7eb fb98 bl 8000ac8 <__aeabi_dcmpeq> + 8015398: 4681 mov r9, r0 + 801539a: b160 cbz r0, 80153b6 <_dtoa_r+0xee> + 801539c: 9a0d ldr r2, [sp, #52] ; 0x34 + 801539e: 2301 movs r3, #1 + 80153a0: 6013 str r3, [r2, #0] + 80153a2: 9b21 ldr r3, [sp, #132] ; 0x84 + 80153a4: 2b00 cmp r3, #0 + 80153a6: f000 8568 beq.w 8015e7a <_dtoa_r+0xbb2> + 80153aa: 4b86 ldr r3, [pc, #536] ; (80155c4 <_dtoa_r+0x2fc>) + 80153ac: 9a21 ldr r2, [sp, #132] ; 0x84 + 80153ae: 6013 str r3, [r2, #0] + 80153b0: 3b01 subs r3, #1 + 80153b2: 9300 str r3, [sp, #0] + 80153b4: e7da b.n 801536c <_dtoa_r+0xa4> + 80153b6: aa10 add r2, sp, #64 ; 0x40 + 80153b8: a911 add r1, sp, #68 ; 0x44 + 80153ba: 4620 mov r0, r4 + 80153bc: eeb0 0a48 vmov.f32 s0, s16 + 80153c0: eef0 0a68 vmov.f32 s1, s17 + 80153c4: f001 fd04 bl 8016dd0 <__d2b> + 80153c8: f3c8 550a ubfx r5, r8, #20, #11 + 80153cc: 4682 mov sl, r0 + 80153ce: 2d00 cmp r5, #0 + 80153d0: d07f beq.n 80154d2 <_dtoa_r+0x20a> + 80153d2: ee18 3a90 vmov r3, s17 + 80153d6: f3c3 0313 ubfx r3, r3, #0, #20 + 80153da: f043 537f orr.w r3, r3, #1069547520 ; 0x3fc00000 + 80153de: ec51 0b18 vmov r0, r1, d8 + 80153e2: f443 1340 orr.w r3, r3, #3145728 ; 0x300000 + 80153e6: f2a5 35ff subw r5, r5, #1023 ; 0x3ff + 80153ea: f8cd 9038 str.w r9, [sp, #56] ; 0x38 + 80153ee: 4619 mov r1, r3 + 80153f0: 2200 movs r2, #0 + 80153f2: 4b75 ldr r3, [pc, #468] ; (80155c8 <_dtoa_r+0x300>) + 80153f4: f7ea ff48 bl 8000288 <__aeabi_dsub> + 80153f8: a367 add r3, pc, #412 ; (adr r3, 8015598 <_dtoa_r+0x2d0>) + 80153fa: e9d3 2300 ldrd r2, r3, [r3] + 80153fe: f7eb f8fb bl 80005f8 <__aeabi_dmul> + 8015402: a367 add r3, pc, #412 ; (adr r3, 80155a0 <_dtoa_r+0x2d8>) + 8015404: e9d3 2300 ldrd r2, r3, [r3] + 8015408: f7ea ff40 bl 800028c <__adddf3> + 801540c: 4606 mov r6, r0 + 801540e: 4628 mov r0, r5 + 8015410: 460f mov r7, r1 + 8015412: f7eb f887 bl 8000524 <__aeabi_i2d> + 8015416: a364 add r3, pc, #400 ; (adr r3, 80155a8 <_dtoa_r+0x2e0>) + 8015418: e9d3 2300 ldrd r2, r3, [r3] + 801541c: f7eb f8ec bl 80005f8 <__aeabi_dmul> + 8015420: 4602 mov r2, r0 + 8015422: 460b mov r3, r1 + 8015424: 4630 mov r0, r6 + 8015426: 4639 mov r1, r7 + 8015428: f7ea ff30 bl 800028c <__adddf3> + 801542c: 4606 mov r6, r0 + 801542e: 460f mov r7, r1 + 8015430: f7eb fb92 bl 8000b58 <__aeabi_d2iz> + 8015434: 2200 movs r2, #0 + 8015436: 4683 mov fp, r0 + 8015438: 2300 movs r3, #0 + 801543a: 4630 mov r0, r6 + 801543c: 4639 mov r1, r7 + 801543e: f7eb fb4d bl 8000adc <__aeabi_dcmplt> + 8015442: b148 cbz r0, 8015458 <_dtoa_r+0x190> + 8015444: 4658 mov r0, fp + 8015446: f7eb f86d bl 8000524 <__aeabi_i2d> + 801544a: 4632 mov r2, r6 + 801544c: 463b mov r3, r7 + 801544e: f7eb fb3b bl 8000ac8 <__aeabi_dcmpeq> + 8015452: b908 cbnz r0, 8015458 <_dtoa_r+0x190> + 8015454: f10b 3bff add.w fp, fp, #4294967295 + 8015458: f1bb 0f16 cmp.w fp, #22 + 801545c: d857 bhi.n 801550e <_dtoa_r+0x246> + 801545e: 4b5b ldr r3, [pc, #364] ; (80155cc <_dtoa_r+0x304>) + 8015460: eb03 03cb add.w r3, r3, fp, lsl #3 + 8015464: e9d3 2300 ldrd r2, r3, [r3] + 8015468: ec51 0b18 vmov r0, r1, d8 + 801546c: f7eb fb36 bl 8000adc <__aeabi_dcmplt> + 8015470: 2800 cmp r0, #0 + 8015472: d04e beq.n 8015512 <_dtoa_r+0x24a> + 8015474: f10b 3bff add.w fp, fp, #4294967295 + 8015478: 2300 movs r3, #0 + 801547a: 930c str r3, [sp, #48] ; 0x30 + 801547c: 9b10 ldr r3, [sp, #64] ; 0x40 + 801547e: 1b5b subs r3, r3, r5 + 8015480: 1e5a subs r2, r3, #1 + 8015482: bf45 ittet mi + 8015484: f1c3 0301 rsbmi r3, r3, #1 + 8015488: 9305 strmi r3, [sp, #20] + 801548a: 2300 movpl r3, #0 + 801548c: 2300 movmi r3, #0 + 801548e: 9206 str r2, [sp, #24] + 8015490: bf54 ite pl + 8015492: 9305 strpl r3, [sp, #20] + 8015494: 9306 strmi r3, [sp, #24] + 8015496: f1bb 0f00 cmp.w fp, #0 + 801549a: db3c blt.n 8015516 <_dtoa_r+0x24e> + 801549c: 9b06 ldr r3, [sp, #24] + 801549e: f8cd b02c str.w fp, [sp, #44] ; 0x2c + 80154a2: 445b add r3, fp + 80154a4: 9306 str r3, [sp, #24] + 80154a6: 2300 movs r3, #0 + 80154a8: 9308 str r3, [sp, #32] + 80154aa: 9b07 ldr r3, [sp, #28] + 80154ac: 2b09 cmp r3, #9 + 80154ae: d868 bhi.n 8015582 <_dtoa_r+0x2ba> + 80154b0: 2b05 cmp r3, #5 + 80154b2: bfc4 itt gt + 80154b4: 3b04 subgt r3, #4 + 80154b6: 9307 strgt r3, [sp, #28] + 80154b8: 9b07 ldr r3, [sp, #28] + 80154ba: f1a3 0302 sub.w r3, r3, #2 + 80154be: bfcc ite gt + 80154c0: 2500 movgt r5, #0 + 80154c2: 2501 movle r5, #1 + 80154c4: 2b03 cmp r3, #3 + 80154c6: f200 8085 bhi.w 80155d4 <_dtoa_r+0x30c> + 80154ca: e8df f003 tbb [pc, r3] + 80154ce: 3b2e .short 0x3b2e + 80154d0: 5839 .short 0x5839 + 80154d2: e9dd 5310 ldrd r5, r3, [sp, #64] ; 0x40 + 80154d6: 441d add r5, r3 + 80154d8: f205 4332 addw r3, r5, #1074 ; 0x432 + 80154dc: 2b20 cmp r3, #32 + 80154de: bfc1 itttt gt + 80154e0: f1c3 0340 rsbgt r3, r3, #64 ; 0x40 + 80154e4: fa08 f803 lslgt.w r8, r8, r3 + 80154e8: f205 4312 addwgt r3, r5, #1042 ; 0x412 + 80154ec: fa26 f303 lsrgt.w r3, r6, r3 + 80154f0: bfd6 itet le + 80154f2: f1c3 0320 rsble r3, r3, #32 + 80154f6: ea48 0003 orrgt.w r0, r8, r3 + 80154fa: fa06 f003 lslle.w r0, r6, r3 + 80154fe: f7eb f801 bl 8000504 <__aeabi_ui2d> + 8015502: 2201 movs r2, #1 + 8015504: f1a1 73f8 sub.w r3, r1, #32505856 ; 0x1f00000 + 8015508: 3d01 subs r5, #1 + 801550a: 920e str r2, [sp, #56] ; 0x38 + 801550c: e76f b.n 80153ee <_dtoa_r+0x126> + 801550e: 2301 movs r3, #1 + 8015510: e7b3 b.n 801547a <_dtoa_r+0x1b2> + 8015512: 900c str r0, [sp, #48] ; 0x30 + 8015514: e7b2 b.n 801547c <_dtoa_r+0x1b4> + 8015516: 9b05 ldr r3, [sp, #20] + 8015518: eba3 030b sub.w r3, r3, fp + 801551c: 9305 str r3, [sp, #20] + 801551e: f1cb 0300 rsb r3, fp, #0 + 8015522: 9308 str r3, [sp, #32] + 8015524: 2300 movs r3, #0 + 8015526: 930b str r3, [sp, #44] ; 0x2c + 8015528: e7bf b.n 80154aa <_dtoa_r+0x1e2> + 801552a: 2300 movs r3, #0 + 801552c: 9309 str r3, [sp, #36] ; 0x24 + 801552e: 9b0a ldr r3, [sp, #40] ; 0x28 + 8015530: 2b00 cmp r3, #0 + 8015532: dc52 bgt.n 80155da <_dtoa_r+0x312> + 8015534: 2301 movs r3, #1 + 8015536: 9301 str r3, [sp, #4] + 8015538: 9304 str r3, [sp, #16] + 801553a: 461a mov r2, r3 + 801553c: 920a str r2, [sp, #40] ; 0x28 + 801553e: e00b b.n 8015558 <_dtoa_r+0x290> + 8015540: 2301 movs r3, #1 + 8015542: e7f3 b.n 801552c <_dtoa_r+0x264> + 8015544: 2300 movs r3, #0 + 8015546: 9309 str r3, [sp, #36] ; 0x24 + 8015548: 9b0a ldr r3, [sp, #40] ; 0x28 + 801554a: 445b add r3, fp + 801554c: 9301 str r3, [sp, #4] + 801554e: 3301 adds r3, #1 + 8015550: 2b01 cmp r3, #1 + 8015552: 9304 str r3, [sp, #16] + 8015554: bfb8 it lt + 8015556: 2301 movlt r3, #1 + 8015558: 69e0 ldr r0, [r4, #28] + 801555a: 2100 movs r1, #0 + 801555c: 2204 movs r2, #4 + 801555e: f102 0614 add.w r6, r2, #20 + 8015562: 429e cmp r6, r3 + 8015564: d93d bls.n 80155e2 <_dtoa_r+0x31a> + 8015566: 6041 str r1, [r0, #4] + 8015568: 4620 mov r0, r4 + 801556a: f001 f855 bl 8016618 <_Balloc> + 801556e: 9000 str r0, [sp, #0] + 8015570: 2800 cmp r0, #0 + 8015572: d139 bne.n 80155e8 <_dtoa_r+0x320> + 8015574: 4b16 ldr r3, [pc, #88] ; (80155d0 <_dtoa_r+0x308>) + 8015576: 4602 mov r2, r0 + 8015578: f240 11af movw r1, #431 ; 0x1af + 801557c: e6bd b.n 80152fa <_dtoa_r+0x32> + 801557e: 2301 movs r3, #1 + 8015580: e7e1 b.n 8015546 <_dtoa_r+0x27e> + 8015582: 2501 movs r5, #1 + 8015584: 2300 movs r3, #0 + 8015586: 9307 str r3, [sp, #28] + 8015588: 9509 str r5, [sp, #36] ; 0x24 + 801558a: f04f 33ff mov.w r3, #4294967295 + 801558e: 9301 str r3, [sp, #4] + 8015590: 9304 str r3, [sp, #16] + 8015592: 2200 movs r2, #0 + 8015594: 2312 movs r3, #18 + 8015596: e7d1 b.n 801553c <_dtoa_r+0x274> + 8015598: 636f4361 .word 0x636f4361 + 801559c: 3fd287a7 .word 0x3fd287a7 + 80155a0: 8b60c8b3 .word 0x8b60c8b3 + 80155a4: 3fc68a28 .word 0x3fc68a28 + 80155a8: 509f79fb .word 0x509f79fb + 80155ac: 3fd34413 .word 0x3fd34413 + 80155b0: 0801ad7a .word 0x0801ad7a + 80155b4: 0801ae3c .word 0x0801ae3c + 80155b8: 7ff00000 .word 0x7ff00000 + 80155bc: 0801ae38 .word 0x0801ae38 + 80155c0: 0801ae2f .word 0x0801ae2f + 80155c4: 0801ad52 .word 0x0801ad52 + 80155c8: 3ff80000 .word 0x3ff80000 + 80155cc: 0801af88 .word 0x0801af88 + 80155d0: 0801ae94 .word 0x0801ae94 + 80155d4: 2301 movs r3, #1 + 80155d6: 9309 str r3, [sp, #36] ; 0x24 + 80155d8: e7d7 b.n 801558a <_dtoa_r+0x2c2> + 80155da: 9b0a ldr r3, [sp, #40] ; 0x28 + 80155dc: 9301 str r3, [sp, #4] + 80155de: 9304 str r3, [sp, #16] + 80155e0: e7ba b.n 8015558 <_dtoa_r+0x290> + 80155e2: 3101 adds r1, #1 + 80155e4: 0052 lsls r2, r2, #1 + 80155e6: e7ba b.n 801555e <_dtoa_r+0x296> + 80155e8: 69e3 ldr r3, [r4, #28] + 80155ea: 9a00 ldr r2, [sp, #0] + 80155ec: 601a str r2, [r3, #0] + 80155ee: 9b04 ldr r3, [sp, #16] + 80155f0: 2b0e cmp r3, #14 + 80155f2: f200 80a8 bhi.w 8015746 <_dtoa_r+0x47e> + 80155f6: 2d00 cmp r5, #0 + 80155f8: f000 80a5 beq.w 8015746 <_dtoa_r+0x47e> + 80155fc: f1bb 0f00 cmp.w fp, #0 + 8015600: dd38 ble.n 8015674 <_dtoa_r+0x3ac> + 8015602: 4bc0 ldr r3, [pc, #768] ; (8015904 <_dtoa_r+0x63c>) + 8015604: f00b 020f and.w r2, fp, #15 + 8015608: eb03 03c2 add.w r3, r3, r2, lsl #3 + 801560c: f41b 7f80 tst.w fp, #256 ; 0x100 + 8015610: e9d3 6700 ldrd r6, r7, [r3] + 8015614: ea4f 182b mov.w r8, fp, asr #4 + 8015618: d019 beq.n 801564e <_dtoa_r+0x386> + 801561a: 4bbb ldr r3, [pc, #748] ; (8015908 <_dtoa_r+0x640>) + 801561c: ec51 0b18 vmov r0, r1, d8 + 8015620: e9d3 2308 ldrd r2, r3, [r3, #32] + 8015624: f7eb f912 bl 800084c <__aeabi_ddiv> + 8015628: e9cd 0102 strd r0, r1, [sp, #8] + 801562c: f008 080f and.w r8, r8, #15 + 8015630: 2503 movs r5, #3 + 8015632: f8df 92d4 ldr.w r9, [pc, #724] ; 8015908 <_dtoa_r+0x640> + 8015636: f1b8 0f00 cmp.w r8, #0 + 801563a: d10a bne.n 8015652 <_dtoa_r+0x38a> + 801563c: e9dd 0102 ldrd r0, r1, [sp, #8] + 8015640: 4632 mov r2, r6 + 8015642: 463b mov r3, r7 + 8015644: f7eb f902 bl 800084c <__aeabi_ddiv> + 8015648: e9cd 0102 strd r0, r1, [sp, #8] + 801564c: e02b b.n 80156a6 <_dtoa_r+0x3de> + 801564e: 2502 movs r5, #2 + 8015650: e7ef b.n 8015632 <_dtoa_r+0x36a> + 8015652: f018 0f01 tst.w r8, #1 + 8015656: d008 beq.n 801566a <_dtoa_r+0x3a2> + 8015658: 4630 mov r0, r6 + 801565a: 4639 mov r1, r7 + 801565c: e9d9 2300 ldrd r2, r3, [r9] + 8015660: f7ea ffca bl 80005f8 <__aeabi_dmul> + 8015664: 3501 adds r5, #1 + 8015666: 4606 mov r6, r0 + 8015668: 460f mov r7, r1 + 801566a: ea4f 0868 mov.w r8, r8, asr #1 + 801566e: f109 0908 add.w r9, r9, #8 + 8015672: e7e0 b.n 8015636 <_dtoa_r+0x36e> + 8015674: f000 809f beq.w 80157b6 <_dtoa_r+0x4ee> + 8015678: f1cb 0600 rsb r6, fp, #0 + 801567c: 4ba1 ldr r3, [pc, #644] ; (8015904 <_dtoa_r+0x63c>) + 801567e: 4fa2 ldr r7, [pc, #648] ; (8015908 <_dtoa_r+0x640>) + 8015680: f006 020f and.w r2, r6, #15 + 8015684: eb03 03c2 add.w r3, r3, r2, lsl #3 + 8015688: e9d3 2300 ldrd r2, r3, [r3] + 801568c: ec51 0b18 vmov r0, r1, d8 + 8015690: f7ea ffb2 bl 80005f8 <__aeabi_dmul> + 8015694: e9cd 0102 strd r0, r1, [sp, #8] + 8015698: 1136 asrs r6, r6, #4 + 801569a: 2300 movs r3, #0 + 801569c: 2502 movs r5, #2 + 801569e: 2e00 cmp r6, #0 + 80156a0: d17e bne.n 80157a0 <_dtoa_r+0x4d8> + 80156a2: 2b00 cmp r3, #0 + 80156a4: d1d0 bne.n 8015648 <_dtoa_r+0x380> + 80156a6: 9b0c ldr r3, [sp, #48] ; 0x30 + 80156a8: e9dd 8902 ldrd r8, r9, [sp, #8] + 80156ac: 2b00 cmp r3, #0 + 80156ae: f000 8084 beq.w 80157ba <_dtoa_r+0x4f2> + 80156b2: 4b96 ldr r3, [pc, #600] ; (801590c <_dtoa_r+0x644>) + 80156b4: 2200 movs r2, #0 + 80156b6: 4640 mov r0, r8 + 80156b8: 4649 mov r1, r9 + 80156ba: f7eb fa0f bl 8000adc <__aeabi_dcmplt> + 80156be: 2800 cmp r0, #0 + 80156c0: d07b beq.n 80157ba <_dtoa_r+0x4f2> + 80156c2: 9b04 ldr r3, [sp, #16] + 80156c4: 2b00 cmp r3, #0 + 80156c6: d078 beq.n 80157ba <_dtoa_r+0x4f2> + 80156c8: 9b01 ldr r3, [sp, #4] + 80156ca: 2b00 cmp r3, #0 + 80156cc: dd39 ble.n 8015742 <_dtoa_r+0x47a> + 80156ce: 4b90 ldr r3, [pc, #576] ; (8015910 <_dtoa_r+0x648>) + 80156d0: 2200 movs r2, #0 + 80156d2: 4640 mov r0, r8 + 80156d4: 4649 mov r1, r9 + 80156d6: f7ea ff8f bl 80005f8 <__aeabi_dmul> + 80156da: e9cd 0102 strd r0, r1, [sp, #8] + 80156de: 9e01 ldr r6, [sp, #4] + 80156e0: f10b 37ff add.w r7, fp, #4294967295 + 80156e4: 3501 adds r5, #1 + 80156e6: e9dd 8902 ldrd r8, r9, [sp, #8] + 80156ea: 4628 mov r0, r5 + 80156ec: f7ea ff1a bl 8000524 <__aeabi_i2d> + 80156f0: 4642 mov r2, r8 + 80156f2: 464b mov r3, r9 + 80156f4: f7ea ff80 bl 80005f8 <__aeabi_dmul> + 80156f8: 4b86 ldr r3, [pc, #536] ; (8015914 <_dtoa_r+0x64c>) + 80156fa: 2200 movs r2, #0 + 80156fc: f7ea fdc6 bl 800028c <__adddf3> + 8015700: f1a1 7350 sub.w r3, r1, #54525952 ; 0x3400000 + 8015704: e9cd 0102 strd r0, r1, [sp, #8] + 8015708: 9303 str r3, [sp, #12] + 801570a: 2e00 cmp r6, #0 + 801570c: d158 bne.n 80157c0 <_dtoa_r+0x4f8> + 801570e: 4b82 ldr r3, [pc, #520] ; (8015918 <_dtoa_r+0x650>) + 8015710: 2200 movs r2, #0 + 8015712: 4640 mov r0, r8 + 8015714: 4649 mov r1, r9 + 8015716: f7ea fdb7 bl 8000288 <__aeabi_dsub> + 801571a: e9dd 2302 ldrd r2, r3, [sp, #8] + 801571e: 4680 mov r8, r0 + 8015720: 4689 mov r9, r1 + 8015722: f7eb f9f9 bl 8000b18 <__aeabi_dcmpgt> + 8015726: 2800 cmp r0, #0 + 8015728: f040 8296 bne.w 8015c58 <_dtoa_r+0x990> + 801572c: e9dd 2102 ldrd r2, r1, [sp, #8] + 8015730: 4640 mov r0, r8 + 8015732: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8015736: 4649 mov r1, r9 + 8015738: f7eb f9d0 bl 8000adc <__aeabi_dcmplt> + 801573c: 2800 cmp r0, #0 + 801573e: f040 8289 bne.w 8015c54 <_dtoa_r+0x98c> + 8015742: ed8d 8b02 vstr d8, [sp, #8] + 8015746: 9b11 ldr r3, [sp, #68] ; 0x44 + 8015748: 2b00 cmp r3, #0 + 801574a: f2c0 814e blt.w 80159ea <_dtoa_r+0x722> + 801574e: f1bb 0f0e cmp.w fp, #14 + 8015752: f300 814a bgt.w 80159ea <_dtoa_r+0x722> + 8015756: 4b6b ldr r3, [pc, #428] ; (8015904 <_dtoa_r+0x63c>) + 8015758: eb03 03cb add.w r3, r3, fp, lsl #3 + 801575c: e9d3 8900 ldrd r8, r9, [r3] + 8015760: 9b0a ldr r3, [sp, #40] ; 0x28 + 8015762: 2b00 cmp r3, #0 + 8015764: f280 80dc bge.w 8015920 <_dtoa_r+0x658> + 8015768: 9b04 ldr r3, [sp, #16] + 801576a: 2b00 cmp r3, #0 + 801576c: f300 80d8 bgt.w 8015920 <_dtoa_r+0x658> + 8015770: f040 826f bne.w 8015c52 <_dtoa_r+0x98a> + 8015774: 4b68 ldr r3, [pc, #416] ; (8015918 <_dtoa_r+0x650>) + 8015776: 2200 movs r2, #0 + 8015778: 4640 mov r0, r8 + 801577a: 4649 mov r1, r9 + 801577c: f7ea ff3c bl 80005f8 <__aeabi_dmul> + 8015780: e9dd 2302 ldrd r2, r3, [sp, #8] + 8015784: f7eb f9be bl 8000b04 <__aeabi_dcmpge> + 8015788: 9e04 ldr r6, [sp, #16] + 801578a: 4637 mov r7, r6 + 801578c: 2800 cmp r0, #0 + 801578e: f040 8245 bne.w 8015c1c <_dtoa_r+0x954> + 8015792: 9d00 ldr r5, [sp, #0] + 8015794: 2331 movs r3, #49 ; 0x31 + 8015796: f805 3b01 strb.w r3, [r5], #1 + 801579a: f10b 0b01 add.w fp, fp, #1 + 801579e: e241 b.n 8015c24 <_dtoa_r+0x95c> + 80157a0: 07f2 lsls r2, r6, #31 + 80157a2: d505 bpl.n 80157b0 <_dtoa_r+0x4e8> + 80157a4: e9d7 2300 ldrd r2, r3, [r7] + 80157a8: f7ea ff26 bl 80005f8 <__aeabi_dmul> + 80157ac: 3501 adds r5, #1 + 80157ae: 2301 movs r3, #1 + 80157b0: 1076 asrs r6, r6, #1 + 80157b2: 3708 adds r7, #8 + 80157b4: e773 b.n 801569e <_dtoa_r+0x3d6> + 80157b6: 2502 movs r5, #2 + 80157b8: e775 b.n 80156a6 <_dtoa_r+0x3de> + 80157ba: 9e04 ldr r6, [sp, #16] + 80157bc: 465f mov r7, fp + 80157be: e792 b.n 80156e6 <_dtoa_r+0x41e> + 80157c0: 9900 ldr r1, [sp, #0] + 80157c2: 4b50 ldr r3, [pc, #320] ; (8015904 <_dtoa_r+0x63c>) + 80157c4: ed9d 7b02 vldr d7, [sp, #8] + 80157c8: 4431 add r1, r6 + 80157ca: 9102 str r1, [sp, #8] + 80157cc: 9909 ldr r1, [sp, #36] ; 0x24 + 80157ce: eeb0 9a47 vmov.f32 s18, s14 + 80157d2: eef0 9a67 vmov.f32 s19, s15 + 80157d6: eb03 03c6 add.w r3, r3, r6, lsl #3 + 80157da: e953 2302 ldrd r2, r3, [r3, #-8] + 80157de: 2900 cmp r1, #0 + 80157e0: d044 beq.n 801586c <_dtoa_r+0x5a4> + 80157e2: 494e ldr r1, [pc, #312] ; (801591c <_dtoa_r+0x654>) + 80157e4: 2000 movs r0, #0 + 80157e6: f7eb f831 bl 800084c <__aeabi_ddiv> + 80157ea: ec53 2b19 vmov r2, r3, d9 + 80157ee: f7ea fd4b bl 8000288 <__aeabi_dsub> + 80157f2: 9d00 ldr r5, [sp, #0] + 80157f4: ec41 0b19 vmov d9, r0, r1 + 80157f8: 4649 mov r1, r9 + 80157fa: 4640 mov r0, r8 + 80157fc: f7eb f9ac bl 8000b58 <__aeabi_d2iz> + 8015800: 4606 mov r6, r0 + 8015802: f7ea fe8f bl 8000524 <__aeabi_i2d> + 8015806: 4602 mov r2, r0 + 8015808: 460b mov r3, r1 + 801580a: 4640 mov r0, r8 + 801580c: 4649 mov r1, r9 + 801580e: f7ea fd3b bl 8000288 <__aeabi_dsub> + 8015812: 3630 adds r6, #48 ; 0x30 + 8015814: f805 6b01 strb.w r6, [r5], #1 + 8015818: ec53 2b19 vmov r2, r3, d9 + 801581c: 4680 mov r8, r0 + 801581e: 4689 mov r9, r1 + 8015820: f7eb f95c bl 8000adc <__aeabi_dcmplt> + 8015824: 2800 cmp r0, #0 + 8015826: d164 bne.n 80158f2 <_dtoa_r+0x62a> + 8015828: 4642 mov r2, r8 + 801582a: 464b mov r3, r9 + 801582c: 4937 ldr r1, [pc, #220] ; (801590c <_dtoa_r+0x644>) + 801582e: 2000 movs r0, #0 + 8015830: f7ea fd2a bl 8000288 <__aeabi_dsub> + 8015834: ec53 2b19 vmov r2, r3, d9 + 8015838: f7eb f950 bl 8000adc <__aeabi_dcmplt> + 801583c: 2800 cmp r0, #0 + 801583e: f040 80b6 bne.w 80159ae <_dtoa_r+0x6e6> + 8015842: 9b02 ldr r3, [sp, #8] + 8015844: 429d cmp r5, r3 + 8015846: f43f af7c beq.w 8015742 <_dtoa_r+0x47a> + 801584a: 4b31 ldr r3, [pc, #196] ; (8015910 <_dtoa_r+0x648>) + 801584c: ec51 0b19 vmov r0, r1, d9 + 8015850: 2200 movs r2, #0 + 8015852: f7ea fed1 bl 80005f8 <__aeabi_dmul> + 8015856: 4b2e ldr r3, [pc, #184] ; (8015910 <_dtoa_r+0x648>) + 8015858: ec41 0b19 vmov d9, r0, r1 + 801585c: 2200 movs r2, #0 + 801585e: 4640 mov r0, r8 + 8015860: 4649 mov r1, r9 + 8015862: f7ea fec9 bl 80005f8 <__aeabi_dmul> + 8015866: 4680 mov r8, r0 + 8015868: 4689 mov r9, r1 + 801586a: e7c5 b.n 80157f8 <_dtoa_r+0x530> + 801586c: ec51 0b17 vmov r0, r1, d7 + 8015870: f7ea fec2 bl 80005f8 <__aeabi_dmul> + 8015874: 9b02 ldr r3, [sp, #8] + 8015876: 9d00 ldr r5, [sp, #0] + 8015878: 930f str r3, [sp, #60] ; 0x3c + 801587a: ec41 0b19 vmov d9, r0, r1 + 801587e: 4649 mov r1, r9 + 8015880: 4640 mov r0, r8 + 8015882: f7eb f969 bl 8000b58 <__aeabi_d2iz> + 8015886: 4606 mov r6, r0 + 8015888: f7ea fe4c bl 8000524 <__aeabi_i2d> + 801588c: 3630 adds r6, #48 ; 0x30 + 801588e: 4602 mov r2, r0 + 8015890: 460b mov r3, r1 + 8015892: 4640 mov r0, r8 + 8015894: 4649 mov r1, r9 + 8015896: f7ea fcf7 bl 8000288 <__aeabi_dsub> + 801589a: f805 6b01 strb.w r6, [r5], #1 + 801589e: 9b02 ldr r3, [sp, #8] + 80158a0: 429d cmp r5, r3 + 80158a2: 4680 mov r8, r0 + 80158a4: 4689 mov r9, r1 + 80158a6: f04f 0200 mov.w r2, #0 + 80158aa: d124 bne.n 80158f6 <_dtoa_r+0x62e> + 80158ac: 4b1b ldr r3, [pc, #108] ; (801591c <_dtoa_r+0x654>) + 80158ae: ec51 0b19 vmov r0, r1, d9 + 80158b2: f7ea fceb bl 800028c <__adddf3> + 80158b6: 4602 mov r2, r0 + 80158b8: 460b mov r3, r1 + 80158ba: 4640 mov r0, r8 + 80158bc: 4649 mov r1, r9 + 80158be: f7eb f92b bl 8000b18 <__aeabi_dcmpgt> + 80158c2: 2800 cmp r0, #0 + 80158c4: d173 bne.n 80159ae <_dtoa_r+0x6e6> + 80158c6: ec53 2b19 vmov r2, r3, d9 + 80158ca: 4914 ldr r1, [pc, #80] ; (801591c <_dtoa_r+0x654>) + 80158cc: 2000 movs r0, #0 + 80158ce: f7ea fcdb bl 8000288 <__aeabi_dsub> + 80158d2: 4602 mov r2, r0 + 80158d4: 460b mov r3, r1 + 80158d6: 4640 mov r0, r8 + 80158d8: 4649 mov r1, r9 + 80158da: f7eb f8ff bl 8000adc <__aeabi_dcmplt> + 80158de: 2800 cmp r0, #0 + 80158e0: f43f af2f beq.w 8015742 <_dtoa_r+0x47a> + 80158e4: 9d0f ldr r5, [sp, #60] ; 0x3c + 80158e6: 1e6b subs r3, r5, #1 + 80158e8: 930f str r3, [sp, #60] ; 0x3c + 80158ea: f815 3c01 ldrb.w r3, [r5, #-1] + 80158ee: 2b30 cmp r3, #48 ; 0x30 + 80158f0: d0f8 beq.n 80158e4 <_dtoa_r+0x61c> + 80158f2: 46bb mov fp, r7 + 80158f4: e04a b.n 801598c <_dtoa_r+0x6c4> + 80158f6: 4b06 ldr r3, [pc, #24] ; (8015910 <_dtoa_r+0x648>) + 80158f8: f7ea fe7e bl 80005f8 <__aeabi_dmul> + 80158fc: 4680 mov r8, r0 + 80158fe: 4689 mov r9, r1 + 8015900: e7bd b.n 801587e <_dtoa_r+0x5b6> + 8015902: bf00 nop + 8015904: 0801af88 .word 0x0801af88 + 8015908: 0801af60 .word 0x0801af60 + 801590c: 3ff00000 .word 0x3ff00000 + 8015910: 40240000 .word 0x40240000 + 8015914: 401c0000 .word 0x401c0000 + 8015918: 40140000 .word 0x40140000 + 801591c: 3fe00000 .word 0x3fe00000 + 8015920: e9dd 6702 ldrd r6, r7, [sp, #8] + 8015924: 9d00 ldr r5, [sp, #0] + 8015926: 4642 mov r2, r8 + 8015928: 464b mov r3, r9 + 801592a: 4630 mov r0, r6 + 801592c: 4639 mov r1, r7 + 801592e: f7ea ff8d bl 800084c <__aeabi_ddiv> + 8015932: f7eb f911 bl 8000b58 <__aeabi_d2iz> + 8015936: 9001 str r0, [sp, #4] + 8015938: f7ea fdf4 bl 8000524 <__aeabi_i2d> + 801593c: 4642 mov r2, r8 + 801593e: 464b mov r3, r9 + 8015940: f7ea fe5a bl 80005f8 <__aeabi_dmul> + 8015944: 4602 mov r2, r0 + 8015946: 460b mov r3, r1 + 8015948: 4630 mov r0, r6 + 801594a: 4639 mov r1, r7 + 801594c: f7ea fc9c bl 8000288 <__aeabi_dsub> + 8015950: 9e01 ldr r6, [sp, #4] + 8015952: 9f04 ldr r7, [sp, #16] + 8015954: 3630 adds r6, #48 ; 0x30 + 8015956: f805 6b01 strb.w r6, [r5], #1 + 801595a: 9e00 ldr r6, [sp, #0] + 801595c: 1bae subs r6, r5, r6 + 801595e: 42b7 cmp r7, r6 + 8015960: 4602 mov r2, r0 + 8015962: 460b mov r3, r1 + 8015964: d134 bne.n 80159d0 <_dtoa_r+0x708> + 8015966: f7ea fc91 bl 800028c <__adddf3> + 801596a: 4642 mov r2, r8 + 801596c: 464b mov r3, r9 + 801596e: 4606 mov r6, r0 + 8015970: 460f mov r7, r1 + 8015972: f7eb f8d1 bl 8000b18 <__aeabi_dcmpgt> + 8015976: b9c8 cbnz r0, 80159ac <_dtoa_r+0x6e4> + 8015978: 4642 mov r2, r8 + 801597a: 464b mov r3, r9 + 801597c: 4630 mov r0, r6 + 801597e: 4639 mov r1, r7 + 8015980: f7eb f8a2 bl 8000ac8 <__aeabi_dcmpeq> + 8015984: b110 cbz r0, 801598c <_dtoa_r+0x6c4> + 8015986: 9b01 ldr r3, [sp, #4] + 8015988: 07db lsls r3, r3, #31 + 801598a: d40f bmi.n 80159ac <_dtoa_r+0x6e4> + 801598c: 4651 mov r1, sl + 801598e: 4620 mov r0, r4 + 8015990: f000 fe82 bl 8016698 <_Bfree> + 8015994: 2300 movs r3, #0 + 8015996: 9a0d ldr r2, [sp, #52] ; 0x34 + 8015998: 702b strb r3, [r5, #0] + 801599a: f10b 0301 add.w r3, fp, #1 + 801599e: 6013 str r3, [r2, #0] + 80159a0: 9b21 ldr r3, [sp, #132] ; 0x84 + 80159a2: 2b00 cmp r3, #0 + 80159a4: f43f ace2 beq.w 801536c <_dtoa_r+0xa4> + 80159a8: 601d str r5, [r3, #0] + 80159aa: e4df b.n 801536c <_dtoa_r+0xa4> + 80159ac: 465f mov r7, fp + 80159ae: 462b mov r3, r5 + 80159b0: 461d mov r5, r3 + 80159b2: f813 2d01 ldrb.w r2, [r3, #-1]! + 80159b6: 2a39 cmp r2, #57 ; 0x39 + 80159b8: d106 bne.n 80159c8 <_dtoa_r+0x700> + 80159ba: 9a00 ldr r2, [sp, #0] + 80159bc: 429a cmp r2, r3 + 80159be: d1f7 bne.n 80159b0 <_dtoa_r+0x6e8> + 80159c0: 9900 ldr r1, [sp, #0] + 80159c2: 2230 movs r2, #48 ; 0x30 + 80159c4: 3701 adds r7, #1 + 80159c6: 700a strb r2, [r1, #0] + 80159c8: 781a ldrb r2, [r3, #0] + 80159ca: 3201 adds r2, #1 + 80159cc: 701a strb r2, [r3, #0] + 80159ce: e790 b.n 80158f2 <_dtoa_r+0x62a> + 80159d0: 4ba3 ldr r3, [pc, #652] ; (8015c60 <_dtoa_r+0x998>) + 80159d2: 2200 movs r2, #0 + 80159d4: f7ea fe10 bl 80005f8 <__aeabi_dmul> + 80159d8: 2200 movs r2, #0 + 80159da: 2300 movs r3, #0 + 80159dc: 4606 mov r6, r0 + 80159de: 460f mov r7, r1 + 80159e0: f7eb f872 bl 8000ac8 <__aeabi_dcmpeq> + 80159e4: 2800 cmp r0, #0 + 80159e6: d09e beq.n 8015926 <_dtoa_r+0x65e> + 80159e8: e7d0 b.n 801598c <_dtoa_r+0x6c4> + 80159ea: 9a09 ldr r2, [sp, #36] ; 0x24 + 80159ec: 2a00 cmp r2, #0 + 80159ee: f000 80ca beq.w 8015b86 <_dtoa_r+0x8be> + 80159f2: 9a07 ldr r2, [sp, #28] + 80159f4: 2a01 cmp r2, #1 + 80159f6: f300 80ad bgt.w 8015b54 <_dtoa_r+0x88c> + 80159fa: 9a0e ldr r2, [sp, #56] ; 0x38 + 80159fc: 2a00 cmp r2, #0 + 80159fe: f000 80a5 beq.w 8015b4c <_dtoa_r+0x884> + 8015a02: f203 4333 addw r3, r3, #1075 ; 0x433 + 8015a06: 9e08 ldr r6, [sp, #32] + 8015a08: 9d05 ldr r5, [sp, #20] + 8015a0a: 9a05 ldr r2, [sp, #20] + 8015a0c: 441a add r2, r3 + 8015a0e: 9205 str r2, [sp, #20] + 8015a10: 9a06 ldr r2, [sp, #24] + 8015a12: 2101 movs r1, #1 + 8015a14: 441a add r2, r3 + 8015a16: 4620 mov r0, r4 + 8015a18: 9206 str r2, [sp, #24] + 8015a1a: f000 ff3d bl 8016898 <__i2b> + 8015a1e: 4607 mov r7, r0 + 8015a20: b165 cbz r5, 8015a3c <_dtoa_r+0x774> + 8015a22: 9b06 ldr r3, [sp, #24] + 8015a24: 2b00 cmp r3, #0 + 8015a26: dd09 ble.n 8015a3c <_dtoa_r+0x774> + 8015a28: 42ab cmp r3, r5 + 8015a2a: 9a05 ldr r2, [sp, #20] + 8015a2c: bfa8 it ge + 8015a2e: 462b movge r3, r5 + 8015a30: 1ad2 subs r2, r2, r3 + 8015a32: 9205 str r2, [sp, #20] + 8015a34: 9a06 ldr r2, [sp, #24] + 8015a36: 1aed subs r5, r5, r3 + 8015a38: 1ad3 subs r3, r2, r3 + 8015a3a: 9306 str r3, [sp, #24] + 8015a3c: 9b08 ldr r3, [sp, #32] + 8015a3e: b1f3 cbz r3, 8015a7e <_dtoa_r+0x7b6> + 8015a40: 9b09 ldr r3, [sp, #36] ; 0x24 + 8015a42: 2b00 cmp r3, #0 + 8015a44: f000 80a3 beq.w 8015b8e <_dtoa_r+0x8c6> + 8015a48: 2e00 cmp r6, #0 + 8015a4a: dd10 ble.n 8015a6e <_dtoa_r+0x7a6> + 8015a4c: 4639 mov r1, r7 + 8015a4e: 4632 mov r2, r6 + 8015a50: 4620 mov r0, r4 + 8015a52: f000 ffe1 bl 8016a18 <__pow5mult> + 8015a56: 4652 mov r2, sl + 8015a58: 4601 mov r1, r0 + 8015a5a: 4607 mov r7, r0 + 8015a5c: 4620 mov r0, r4 + 8015a5e: f000 ff31 bl 80168c4 <__multiply> + 8015a62: 4651 mov r1, sl + 8015a64: 4680 mov r8, r0 + 8015a66: 4620 mov r0, r4 + 8015a68: f000 fe16 bl 8016698 <_Bfree> + 8015a6c: 46c2 mov sl, r8 + 8015a6e: 9b08 ldr r3, [sp, #32] + 8015a70: 1b9a subs r2, r3, r6 + 8015a72: d004 beq.n 8015a7e <_dtoa_r+0x7b6> + 8015a74: 4651 mov r1, sl + 8015a76: 4620 mov r0, r4 + 8015a78: f000 ffce bl 8016a18 <__pow5mult> + 8015a7c: 4682 mov sl, r0 + 8015a7e: 2101 movs r1, #1 + 8015a80: 4620 mov r0, r4 + 8015a82: f000 ff09 bl 8016898 <__i2b> + 8015a86: 9b0b ldr r3, [sp, #44] ; 0x2c + 8015a88: 2b00 cmp r3, #0 + 8015a8a: 4606 mov r6, r0 + 8015a8c: f340 8081 ble.w 8015b92 <_dtoa_r+0x8ca> + 8015a90: 461a mov r2, r3 + 8015a92: 4601 mov r1, r0 + 8015a94: 4620 mov r0, r4 + 8015a96: f000 ffbf bl 8016a18 <__pow5mult> + 8015a9a: 9b07 ldr r3, [sp, #28] + 8015a9c: 2b01 cmp r3, #1 + 8015a9e: 4606 mov r6, r0 + 8015aa0: dd7a ble.n 8015b98 <_dtoa_r+0x8d0> + 8015aa2: f04f 0800 mov.w r8, #0 + 8015aa6: 6933 ldr r3, [r6, #16] + 8015aa8: eb06 0383 add.w r3, r6, r3, lsl #2 + 8015aac: 6918 ldr r0, [r3, #16] + 8015aae: f000 fea5 bl 80167fc <__hi0bits> + 8015ab2: f1c0 0020 rsb r0, r0, #32 + 8015ab6: 9b06 ldr r3, [sp, #24] + 8015ab8: 4418 add r0, r3 + 8015aba: f010 001f ands.w r0, r0, #31 + 8015abe: f000 8094 beq.w 8015bea <_dtoa_r+0x922> + 8015ac2: f1c0 0320 rsb r3, r0, #32 + 8015ac6: 2b04 cmp r3, #4 + 8015ac8: f340 8085 ble.w 8015bd6 <_dtoa_r+0x90e> + 8015acc: 9b05 ldr r3, [sp, #20] + 8015ace: f1c0 001c rsb r0, r0, #28 + 8015ad2: 4403 add r3, r0 + 8015ad4: 9305 str r3, [sp, #20] + 8015ad6: 9b06 ldr r3, [sp, #24] + 8015ad8: 4403 add r3, r0 + 8015ada: 4405 add r5, r0 + 8015adc: 9306 str r3, [sp, #24] + 8015ade: 9b05 ldr r3, [sp, #20] + 8015ae0: 2b00 cmp r3, #0 + 8015ae2: dd05 ble.n 8015af0 <_dtoa_r+0x828> + 8015ae4: 4651 mov r1, sl + 8015ae6: 461a mov r2, r3 + 8015ae8: 4620 mov r0, r4 + 8015aea: f000 ffef bl 8016acc <__lshift> + 8015aee: 4682 mov sl, r0 + 8015af0: 9b06 ldr r3, [sp, #24] + 8015af2: 2b00 cmp r3, #0 + 8015af4: dd05 ble.n 8015b02 <_dtoa_r+0x83a> + 8015af6: 4631 mov r1, r6 + 8015af8: 461a mov r2, r3 + 8015afa: 4620 mov r0, r4 + 8015afc: f000 ffe6 bl 8016acc <__lshift> + 8015b00: 4606 mov r6, r0 + 8015b02: 9b0c ldr r3, [sp, #48] ; 0x30 + 8015b04: 2b00 cmp r3, #0 + 8015b06: d072 beq.n 8015bee <_dtoa_r+0x926> + 8015b08: 4631 mov r1, r6 + 8015b0a: 4650 mov r0, sl + 8015b0c: f001 f84a bl 8016ba4 <__mcmp> + 8015b10: 2800 cmp r0, #0 + 8015b12: da6c bge.n 8015bee <_dtoa_r+0x926> + 8015b14: 2300 movs r3, #0 + 8015b16: 4651 mov r1, sl + 8015b18: 220a movs r2, #10 + 8015b1a: 4620 mov r0, r4 + 8015b1c: f000 fdde bl 80166dc <__multadd> + 8015b20: 9b09 ldr r3, [sp, #36] ; 0x24 + 8015b22: f10b 3bff add.w fp, fp, #4294967295 + 8015b26: 4682 mov sl, r0 + 8015b28: 2b00 cmp r3, #0 + 8015b2a: f000 81b0 beq.w 8015e8e <_dtoa_r+0xbc6> + 8015b2e: 2300 movs r3, #0 + 8015b30: 4639 mov r1, r7 + 8015b32: 220a movs r2, #10 + 8015b34: 4620 mov r0, r4 + 8015b36: f000 fdd1 bl 80166dc <__multadd> + 8015b3a: 9b01 ldr r3, [sp, #4] + 8015b3c: 2b00 cmp r3, #0 + 8015b3e: 4607 mov r7, r0 + 8015b40: f300 8096 bgt.w 8015c70 <_dtoa_r+0x9a8> + 8015b44: 9b07 ldr r3, [sp, #28] + 8015b46: 2b02 cmp r3, #2 + 8015b48: dc59 bgt.n 8015bfe <_dtoa_r+0x936> + 8015b4a: e091 b.n 8015c70 <_dtoa_r+0x9a8> + 8015b4c: 9b10 ldr r3, [sp, #64] ; 0x40 + 8015b4e: f1c3 0336 rsb r3, r3, #54 ; 0x36 + 8015b52: e758 b.n 8015a06 <_dtoa_r+0x73e> + 8015b54: 9b04 ldr r3, [sp, #16] + 8015b56: 1e5e subs r6, r3, #1 + 8015b58: 9b08 ldr r3, [sp, #32] + 8015b5a: 42b3 cmp r3, r6 + 8015b5c: bfbf itttt lt + 8015b5e: 9b08 ldrlt r3, [sp, #32] + 8015b60: 9a0b ldrlt r2, [sp, #44] ; 0x2c + 8015b62: 9608 strlt r6, [sp, #32] + 8015b64: 1af3 sublt r3, r6, r3 + 8015b66: bfb4 ite lt + 8015b68: 18d2 addlt r2, r2, r3 + 8015b6a: 1b9e subge r6, r3, r6 + 8015b6c: 9b04 ldr r3, [sp, #16] + 8015b6e: bfbc itt lt + 8015b70: 920b strlt r2, [sp, #44] ; 0x2c + 8015b72: 2600 movlt r6, #0 + 8015b74: 2b00 cmp r3, #0 + 8015b76: bfb7 itett lt + 8015b78: e9dd 2304 ldrdlt r2, r3, [sp, #16] + 8015b7c: e9dd 3504 ldrdge r3, r5, [sp, #16] + 8015b80: 1a9d sublt r5, r3, r2 + 8015b82: 2300 movlt r3, #0 + 8015b84: e741 b.n 8015a0a <_dtoa_r+0x742> + 8015b86: 9e08 ldr r6, [sp, #32] + 8015b88: 9d05 ldr r5, [sp, #20] + 8015b8a: 9f09 ldr r7, [sp, #36] ; 0x24 + 8015b8c: e748 b.n 8015a20 <_dtoa_r+0x758> + 8015b8e: 9a08 ldr r2, [sp, #32] + 8015b90: e770 b.n 8015a74 <_dtoa_r+0x7ac> + 8015b92: 9b07 ldr r3, [sp, #28] + 8015b94: 2b01 cmp r3, #1 + 8015b96: dc19 bgt.n 8015bcc <_dtoa_r+0x904> + 8015b98: 9b02 ldr r3, [sp, #8] + 8015b9a: b9bb cbnz r3, 8015bcc <_dtoa_r+0x904> + 8015b9c: 9b03 ldr r3, [sp, #12] + 8015b9e: f3c3 0313 ubfx r3, r3, #0, #20 + 8015ba2: b99b cbnz r3, 8015bcc <_dtoa_r+0x904> + 8015ba4: 9b03 ldr r3, [sp, #12] + 8015ba6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8015baa: 0d1b lsrs r3, r3, #20 + 8015bac: 051b lsls r3, r3, #20 + 8015bae: b183 cbz r3, 8015bd2 <_dtoa_r+0x90a> + 8015bb0: 9b05 ldr r3, [sp, #20] + 8015bb2: 3301 adds r3, #1 + 8015bb4: 9305 str r3, [sp, #20] + 8015bb6: 9b06 ldr r3, [sp, #24] + 8015bb8: 3301 adds r3, #1 + 8015bba: 9306 str r3, [sp, #24] + 8015bbc: f04f 0801 mov.w r8, #1 + 8015bc0: 9b0b ldr r3, [sp, #44] ; 0x2c + 8015bc2: 2b00 cmp r3, #0 + 8015bc4: f47f af6f bne.w 8015aa6 <_dtoa_r+0x7de> + 8015bc8: 2001 movs r0, #1 + 8015bca: e774 b.n 8015ab6 <_dtoa_r+0x7ee> + 8015bcc: f04f 0800 mov.w r8, #0 + 8015bd0: e7f6 b.n 8015bc0 <_dtoa_r+0x8f8> + 8015bd2: 4698 mov r8, r3 + 8015bd4: e7f4 b.n 8015bc0 <_dtoa_r+0x8f8> + 8015bd6: d082 beq.n 8015ade <_dtoa_r+0x816> + 8015bd8: 9a05 ldr r2, [sp, #20] + 8015bda: 331c adds r3, #28 + 8015bdc: 441a add r2, r3 + 8015bde: 9205 str r2, [sp, #20] + 8015be0: 9a06 ldr r2, [sp, #24] + 8015be2: 441a add r2, r3 + 8015be4: 441d add r5, r3 + 8015be6: 9206 str r2, [sp, #24] + 8015be8: e779 b.n 8015ade <_dtoa_r+0x816> + 8015bea: 4603 mov r3, r0 + 8015bec: e7f4 b.n 8015bd8 <_dtoa_r+0x910> + 8015bee: 9b04 ldr r3, [sp, #16] + 8015bf0: 2b00 cmp r3, #0 + 8015bf2: dc37 bgt.n 8015c64 <_dtoa_r+0x99c> + 8015bf4: 9b07 ldr r3, [sp, #28] + 8015bf6: 2b02 cmp r3, #2 + 8015bf8: dd34 ble.n 8015c64 <_dtoa_r+0x99c> + 8015bfa: 9b04 ldr r3, [sp, #16] + 8015bfc: 9301 str r3, [sp, #4] + 8015bfe: 9b01 ldr r3, [sp, #4] + 8015c00: b963 cbnz r3, 8015c1c <_dtoa_r+0x954> + 8015c02: 4631 mov r1, r6 + 8015c04: 2205 movs r2, #5 + 8015c06: 4620 mov r0, r4 + 8015c08: f000 fd68 bl 80166dc <__multadd> + 8015c0c: 4601 mov r1, r0 + 8015c0e: 4606 mov r6, r0 + 8015c10: 4650 mov r0, sl + 8015c12: f000 ffc7 bl 8016ba4 <__mcmp> + 8015c16: 2800 cmp r0, #0 + 8015c18: f73f adbb bgt.w 8015792 <_dtoa_r+0x4ca> + 8015c1c: 9b0a ldr r3, [sp, #40] ; 0x28 + 8015c1e: 9d00 ldr r5, [sp, #0] + 8015c20: ea6f 0b03 mvn.w fp, r3 + 8015c24: f04f 0800 mov.w r8, #0 + 8015c28: 4631 mov r1, r6 + 8015c2a: 4620 mov r0, r4 + 8015c2c: f000 fd34 bl 8016698 <_Bfree> + 8015c30: 2f00 cmp r7, #0 + 8015c32: f43f aeab beq.w 801598c <_dtoa_r+0x6c4> + 8015c36: f1b8 0f00 cmp.w r8, #0 + 8015c3a: d005 beq.n 8015c48 <_dtoa_r+0x980> + 8015c3c: 45b8 cmp r8, r7 + 8015c3e: d003 beq.n 8015c48 <_dtoa_r+0x980> + 8015c40: 4641 mov r1, r8 + 8015c42: 4620 mov r0, r4 + 8015c44: f000 fd28 bl 8016698 <_Bfree> + 8015c48: 4639 mov r1, r7 + 8015c4a: 4620 mov r0, r4 + 8015c4c: f000 fd24 bl 8016698 <_Bfree> + 8015c50: e69c b.n 801598c <_dtoa_r+0x6c4> + 8015c52: 2600 movs r6, #0 + 8015c54: 4637 mov r7, r6 + 8015c56: e7e1 b.n 8015c1c <_dtoa_r+0x954> + 8015c58: 46bb mov fp, r7 + 8015c5a: 4637 mov r7, r6 + 8015c5c: e599 b.n 8015792 <_dtoa_r+0x4ca> + 8015c5e: bf00 nop + 8015c60: 40240000 .word 0x40240000 + 8015c64: 9b09 ldr r3, [sp, #36] ; 0x24 + 8015c66: 2b00 cmp r3, #0 + 8015c68: f000 80c8 beq.w 8015dfc <_dtoa_r+0xb34> + 8015c6c: 9b04 ldr r3, [sp, #16] + 8015c6e: 9301 str r3, [sp, #4] + 8015c70: 2d00 cmp r5, #0 + 8015c72: dd05 ble.n 8015c80 <_dtoa_r+0x9b8> + 8015c74: 4639 mov r1, r7 + 8015c76: 462a mov r2, r5 + 8015c78: 4620 mov r0, r4 + 8015c7a: f000 ff27 bl 8016acc <__lshift> + 8015c7e: 4607 mov r7, r0 + 8015c80: f1b8 0f00 cmp.w r8, #0 + 8015c84: d05b beq.n 8015d3e <_dtoa_r+0xa76> + 8015c86: 6879 ldr r1, [r7, #4] + 8015c88: 4620 mov r0, r4 + 8015c8a: f000 fcc5 bl 8016618 <_Balloc> + 8015c8e: 4605 mov r5, r0 + 8015c90: b928 cbnz r0, 8015c9e <_dtoa_r+0x9d6> + 8015c92: 4b83 ldr r3, [pc, #524] ; (8015ea0 <_dtoa_r+0xbd8>) + 8015c94: 4602 mov r2, r0 + 8015c96: f240 21ef movw r1, #751 ; 0x2ef + 8015c9a: f7ff bb2e b.w 80152fa <_dtoa_r+0x32> + 8015c9e: 693a ldr r2, [r7, #16] + 8015ca0: 3202 adds r2, #2 + 8015ca2: 0092 lsls r2, r2, #2 + 8015ca4: f107 010c add.w r1, r7, #12 + 8015ca8: 300c adds r0, #12 + 8015caa: f7ff fa4a bl 8015142 + 8015cae: 2201 movs r2, #1 + 8015cb0: 4629 mov r1, r5 + 8015cb2: 4620 mov r0, r4 + 8015cb4: f000 ff0a bl 8016acc <__lshift> + 8015cb8: 9b00 ldr r3, [sp, #0] + 8015cba: 3301 adds r3, #1 + 8015cbc: 9304 str r3, [sp, #16] + 8015cbe: e9dd 2300 ldrd r2, r3, [sp] + 8015cc2: 4413 add r3, r2 + 8015cc4: 9308 str r3, [sp, #32] + 8015cc6: 9b02 ldr r3, [sp, #8] + 8015cc8: f003 0301 and.w r3, r3, #1 + 8015ccc: 46b8 mov r8, r7 + 8015cce: 9306 str r3, [sp, #24] + 8015cd0: 4607 mov r7, r0 + 8015cd2: 9b04 ldr r3, [sp, #16] + 8015cd4: 4631 mov r1, r6 + 8015cd6: 3b01 subs r3, #1 + 8015cd8: 4650 mov r0, sl + 8015cda: 9301 str r3, [sp, #4] + 8015cdc: f7ff fa6c bl 80151b8 + 8015ce0: 4641 mov r1, r8 + 8015ce2: 9002 str r0, [sp, #8] + 8015ce4: f100 0930 add.w r9, r0, #48 ; 0x30 + 8015ce8: 4650 mov r0, sl + 8015cea: f000 ff5b bl 8016ba4 <__mcmp> + 8015cee: 463a mov r2, r7 + 8015cf0: 9005 str r0, [sp, #20] + 8015cf2: 4631 mov r1, r6 + 8015cf4: 4620 mov r0, r4 + 8015cf6: f000 ff71 bl 8016bdc <__mdiff> + 8015cfa: 68c2 ldr r2, [r0, #12] + 8015cfc: 4605 mov r5, r0 + 8015cfe: bb02 cbnz r2, 8015d42 <_dtoa_r+0xa7a> + 8015d00: 4601 mov r1, r0 + 8015d02: 4650 mov r0, sl + 8015d04: f000 ff4e bl 8016ba4 <__mcmp> + 8015d08: 4602 mov r2, r0 + 8015d0a: 4629 mov r1, r5 + 8015d0c: 4620 mov r0, r4 + 8015d0e: 9209 str r2, [sp, #36] ; 0x24 + 8015d10: f000 fcc2 bl 8016698 <_Bfree> + 8015d14: 9b07 ldr r3, [sp, #28] + 8015d16: 9a09 ldr r2, [sp, #36] ; 0x24 + 8015d18: 9d04 ldr r5, [sp, #16] + 8015d1a: ea43 0102 orr.w r1, r3, r2 + 8015d1e: 9b06 ldr r3, [sp, #24] + 8015d20: 4319 orrs r1, r3 + 8015d22: d110 bne.n 8015d46 <_dtoa_r+0xa7e> + 8015d24: f1b9 0f39 cmp.w r9, #57 ; 0x39 + 8015d28: d029 beq.n 8015d7e <_dtoa_r+0xab6> + 8015d2a: 9b05 ldr r3, [sp, #20] + 8015d2c: 2b00 cmp r3, #0 + 8015d2e: dd02 ble.n 8015d36 <_dtoa_r+0xa6e> + 8015d30: 9b02 ldr r3, [sp, #8] + 8015d32: f103 0931 add.w r9, r3, #49 ; 0x31 + 8015d36: 9b01 ldr r3, [sp, #4] + 8015d38: f883 9000 strb.w r9, [r3] + 8015d3c: e774 b.n 8015c28 <_dtoa_r+0x960> + 8015d3e: 4638 mov r0, r7 + 8015d40: e7ba b.n 8015cb8 <_dtoa_r+0x9f0> + 8015d42: 2201 movs r2, #1 + 8015d44: e7e1 b.n 8015d0a <_dtoa_r+0xa42> + 8015d46: 9b05 ldr r3, [sp, #20] + 8015d48: 2b00 cmp r3, #0 + 8015d4a: db04 blt.n 8015d56 <_dtoa_r+0xa8e> + 8015d4c: 9907 ldr r1, [sp, #28] + 8015d4e: 430b orrs r3, r1 + 8015d50: 9906 ldr r1, [sp, #24] + 8015d52: 430b orrs r3, r1 + 8015d54: d120 bne.n 8015d98 <_dtoa_r+0xad0> + 8015d56: 2a00 cmp r2, #0 + 8015d58: dded ble.n 8015d36 <_dtoa_r+0xa6e> + 8015d5a: 4651 mov r1, sl + 8015d5c: 2201 movs r2, #1 + 8015d5e: 4620 mov r0, r4 + 8015d60: f000 feb4 bl 8016acc <__lshift> + 8015d64: 4631 mov r1, r6 + 8015d66: 4682 mov sl, r0 + 8015d68: f000 ff1c bl 8016ba4 <__mcmp> + 8015d6c: 2800 cmp r0, #0 + 8015d6e: dc03 bgt.n 8015d78 <_dtoa_r+0xab0> + 8015d70: d1e1 bne.n 8015d36 <_dtoa_r+0xa6e> + 8015d72: f019 0f01 tst.w r9, #1 + 8015d76: d0de beq.n 8015d36 <_dtoa_r+0xa6e> + 8015d78: f1b9 0f39 cmp.w r9, #57 ; 0x39 + 8015d7c: d1d8 bne.n 8015d30 <_dtoa_r+0xa68> + 8015d7e: 9a01 ldr r2, [sp, #4] + 8015d80: 2339 movs r3, #57 ; 0x39 + 8015d82: 7013 strb r3, [r2, #0] + 8015d84: 462b mov r3, r5 + 8015d86: 461d mov r5, r3 + 8015d88: 3b01 subs r3, #1 + 8015d8a: f815 2c01 ldrb.w r2, [r5, #-1] + 8015d8e: 2a39 cmp r2, #57 ; 0x39 + 8015d90: d06c beq.n 8015e6c <_dtoa_r+0xba4> + 8015d92: 3201 adds r2, #1 + 8015d94: 701a strb r2, [r3, #0] + 8015d96: e747 b.n 8015c28 <_dtoa_r+0x960> + 8015d98: 2a00 cmp r2, #0 + 8015d9a: dd07 ble.n 8015dac <_dtoa_r+0xae4> + 8015d9c: f1b9 0f39 cmp.w r9, #57 ; 0x39 + 8015da0: d0ed beq.n 8015d7e <_dtoa_r+0xab6> + 8015da2: 9a01 ldr r2, [sp, #4] + 8015da4: f109 0301 add.w r3, r9, #1 + 8015da8: 7013 strb r3, [r2, #0] + 8015daa: e73d b.n 8015c28 <_dtoa_r+0x960> + 8015dac: 9b04 ldr r3, [sp, #16] + 8015dae: 9a08 ldr r2, [sp, #32] + 8015db0: f803 9c01 strb.w r9, [r3, #-1] + 8015db4: 4293 cmp r3, r2 + 8015db6: d043 beq.n 8015e40 <_dtoa_r+0xb78> + 8015db8: 4651 mov r1, sl + 8015dba: 2300 movs r3, #0 + 8015dbc: 220a movs r2, #10 + 8015dbe: 4620 mov r0, r4 + 8015dc0: f000 fc8c bl 80166dc <__multadd> + 8015dc4: 45b8 cmp r8, r7 + 8015dc6: 4682 mov sl, r0 + 8015dc8: f04f 0300 mov.w r3, #0 + 8015dcc: f04f 020a mov.w r2, #10 + 8015dd0: 4641 mov r1, r8 + 8015dd2: 4620 mov r0, r4 + 8015dd4: d107 bne.n 8015de6 <_dtoa_r+0xb1e> + 8015dd6: f000 fc81 bl 80166dc <__multadd> + 8015dda: 4680 mov r8, r0 + 8015ddc: 4607 mov r7, r0 + 8015dde: 9b04 ldr r3, [sp, #16] + 8015de0: 3301 adds r3, #1 + 8015de2: 9304 str r3, [sp, #16] + 8015de4: e775 b.n 8015cd2 <_dtoa_r+0xa0a> + 8015de6: f000 fc79 bl 80166dc <__multadd> + 8015dea: 4639 mov r1, r7 + 8015dec: 4680 mov r8, r0 + 8015dee: 2300 movs r3, #0 + 8015df0: 220a movs r2, #10 + 8015df2: 4620 mov r0, r4 + 8015df4: f000 fc72 bl 80166dc <__multadd> + 8015df8: 4607 mov r7, r0 + 8015dfa: e7f0 b.n 8015dde <_dtoa_r+0xb16> + 8015dfc: 9b04 ldr r3, [sp, #16] + 8015dfe: 9301 str r3, [sp, #4] + 8015e00: 9d00 ldr r5, [sp, #0] + 8015e02: 4631 mov r1, r6 + 8015e04: 4650 mov r0, sl + 8015e06: f7ff f9d7 bl 80151b8 + 8015e0a: f100 0930 add.w r9, r0, #48 ; 0x30 + 8015e0e: 9b00 ldr r3, [sp, #0] + 8015e10: f805 9b01 strb.w r9, [r5], #1 + 8015e14: 1aea subs r2, r5, r3 + 8015e16: 9b01 ldr r3, [sp, #4] + 8015e18: 4293 cmp r3, r2 + 8015e1a: dd07 ble.n 8015e2c <_dtoa_r+0xb64> + 8015e1c: 4651 mov r1, sl + 8015e1e: 2300 movs r3, #0 + 8015e20: 220a movs r2, #10 + 8015e22: 4620 mov r0, r4 + 8015e24: f000 fc5a bl 80166dc <__multadd> + 8015e28: 4682 mov sl, r0 + 8015e2a: e7ea b.n 8015e02 <_dtoa_r+0xb3a> + 8015e2c: 9b01 ldr r3, [sp, #4] + 8015e2e: 2b00 cmp r3, #0 + 8015e30: bfc8 it gt + 8015e32: 461d movgt r5, r3 + 8015e34: 9b00 ldr r3, [sp, #0] + 8015e36: bfd8 it le + 8015e38: 2501 movle r5, #1 + 8015e3a: 441d add r5, r3 + 8015e3c: f04f 0800 mov.w r8, #0 + 8015e40: 4651 mov r1, sl + 8015e42: 2201 movs r2, #1 + 8015e44: 4620 mov r0, r4 + 8015e46: f000 fe41 bl 8016acc <__lshift> + 8015e4a: 4631 mov r1, r6 + 8015e4c: 4682 mov sl, r0 + 8015e4e: f000 fea9 bl 8016ba4 <__mcmp> + 8015e52: 2800 cmp r0, #0 + 8015e54: dc96 bgt.n 8015d84 <_dtoa_r+0xabc> + 8015e56: d102 bne.n 8015e5e <_dtoa_r+0xb96> + 8015e58: f019 0f01 tst.w r9, #1 + 8015e5c: d192 bne.n 8015d84 <_dtoa_r+0xabc> + 8015e5e: 462b mov r3, r5 + 8015e60: 461d mov r5, r3 + 8015e62: f813 2d01 ldrb.w r2, [r3, #-1]! + 8015e66: 2a30 cmp r2, #48 ; 0x30 + 8015e68: d0fa beq.n 8015e60 <_dtoa_r+0xb98> + 8015e6a: e6dd b.n 8015c28 <_dtoa_r+0x960> + 8015e6c: 9a00 ldr r2, [sp, #0] + 8015e6e: 429a cmp r2, r3 + 8015e70: d189 bne.n 8015d86 <_dtoa_r+0xabe> + 8015e72: f10b 0b01 add.w fp, fp, #1 + 8015e76: 2331 movs r3, #49 ; 0x31 + 8015e78: e796 b.n 8015da8 <_dtoa_r+0xae0> + 8015e7a: 4b0a ldr r3, [pc, #40] ; (8015ea4 <_dtoa_r+0xbdc>) + 8015e7c: f7ff ba99 b.w 80153b2 <_dtoa_r+0xea> + 8015e80: 9b21 ldr r3, [sp, #132] ; 0x84 + 8015e82: 2b00 cmp r3, #0 + 8015e84: f47f aa6d bne.w 8015362 <_dtoa_r+0x9a> + 8015e88: 4b07 ldr r3, [pc, #28] ; (8015ea8 <_dtoa_r+0xbe0>) + 8015e8a: f7ff ba92 b.w 80153b2 <_dtoa_r+0xea> + 8015e8e: 9b01 ldr r3, [sp, #4] + 8015e90: 2b00 cmp r3, #0 + 8015e92: dcb5 bgt.n 8015e00 <_dtoa_r+0xb38> + 8015e94: 9b07 ldr r3, [sp, #28] + 8015e96: 2b02 cmp r3, #2 + 8015e98: f73f aeb1 bgt.w 8015bfe <_dtoa_r+0x936> + 8015e9c: e7b0 b.n 8015e00 <_dtoa_r+0xb38> + 8015e9e: bf00 nop + 8015ea0: 0801ae94 .word 0x0801ae94 + 8015ea4: 0801ad51 .word 0x0801ad51 + 8015ea8: 0801ae2f .word 0x0801ae2f + +08015eac <_free_r>: + 8015eac: b537 push {r0, r1, r2, r4, r5, lr} + 8015eae: 2900 cmp r1, #0 + 8015eb0: d044 beq.n 8015f3c <_free_r+0x90> + 8015eb2: f851 3c04 ldr.w r3, [r1, #-4] + 8015eb6: 9001 str r0, [sp, #4] + 8015eb8: 2b00 cmp r3, #0 + 8015eba: f1a1 0404 sub.w r4, r1, #4 + 8015ebe: bfb8 it lt + 8015ec0: 18e4 addlt r4, r4, r3 + 8015ec2: f7fd f93f bl 8013144 <__malloc_lock> + 8015ec6: 4a1e ldr r2, [pc, #120] ; (8015f40 <_free_r+0x94>) + 8015ec8: 9801 ldr r0, [sp, #4] + 8015eca: 6813 ldr r3, [r2, #0] + 8015ecc: b933 cbnz r3, 8015edc <_free_r+0x30> + 8015ece: 6063 str r3, [r4, #4] + 8015ed0: 6014 str r4, [r2, #0] + 8015ed2: b003 add sp, #12 + 8015ed4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8015ed8: f7fd b93a b.w 8013150 <__malloc_unlock> + 8015edc: 42a3 cmp r3, r4 + 8015ede: d908 bls.n 8015ef2 <_free_r+0x46> + 8015ee0: 6825 ldr r5, [r4, #0] + 8015ee2: 1961 adds r1, r4, r5 + 8015ee4: 428b cmp r3, r1 + 8015ee6: bf01 itttt eq + 8015ee8: 6819 ldreq r1, [r3, #0] + 8015eea: 685b ldreq r3, [r3, #4] + 8015eec: 1949 addeq r1, r1, r5 + 8015eee: 6021 streq r1, [r4, #0] + 8015ef0: e7ed b.n 8015ece <_free_r+0x22> + 8015ef2: 461a mov r2, r3 + 8015ef4: 685b ldr r3, [r3, #4] + 8015ef6: b10b cbz r3, 8015efc <_free_r+0x50> + 8015ef8: 42a3 cmp r3, r4 + 8015efa: d9fa bls.n 8015ef2 <_free_r+0x46> + 8015efc: 6811 ldr r1, [r2, #0] + 8015efe: 1855 adds r5, r2, r1 + 8015f00: 42a5 cmp r5, r4 + 8015f02: d10b bne.n 8015f1c <_free_r+0x70> + 8015f04: 6824 ldr r4, [r4, #0] + 8015f06: 4421 add r1, r4 + 8015f08: 1854 adds r4, r2, r1 + 8015f0a: 42a3 cmp r3, r4 + 8015f0c: 6011 str r1, [r2, #0] + 8015f0e: d1e0 bne.n 8015ed2 <_free_r+0x26> + 8015f10: 681c ldr r4, [r3, #0] + 8015f12: 685b ldr r3, [r3, #4] + 8015f14: 6053 str r3, [r2, #4] + 8015f16: 440c add r4, r1 + 8015f18: 6014 str r4, [r2, #0] + 8015f1a: e7da b.n 8015ed2 <_free_r+0x26> + 8015f1c: d902 bls.n 8015f24 <_free_r+0x78> + 8015f1e: 230c movs r3, #12 + 8015f20: 6003 str r3, [r0, #0] + 8015f22: e7d6 b.n 8015ed2 <_free_r+0x26> + 8015f24: 6825 ldr r5, [r4, #0] + 8015f26: 1961 adds r1, r4, r5 + 8015f28: 428b cmp r3, r1 + 8015f2a: bf04 itt eq + 8015f2c: 6819 ldreq r1, [r3, #0] + 8015f2e: 685b ldreq r3, [r3, #4] + 8015f30: 6063 str r3, [r4, #4] + 8015f32: bf04 itt eq + 8015f34: 1949 addeq r1, r1, r5 + 8015f36: 6021 streq r1, [r4, #0] + 8015f38: 6054 str r4, [r2, #4] + 8015f3a: e7ca b.n 8015ed2 <_free_r+0x26> + 8015f3c: b003 add sp, #12 + 8015f3e: bd30 pop {r4, r5, pc} + 8015f40: 20002244 .word 0x20002244 + +08015f44 : + 8015f44: 6903 ldr r3, [r0, #16] + 8015f46: ebb3 1f61 cmp.w r3, r1, asr #5 + 8015f4a: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8015f4e: ea4f 1261 mov.w r2, r1, asr #5 + 8015f52: f100 0414 add.w r4, r0, #20 + 8015f56: dd45 ble.n 8015fe4 + 8015f58: f011 011f ands.w r1, r1, #31 + 8015f5c: eb04 0683 add.w r6, r4, r3, lsl #2 + 8015f60: eb04 0582 add.w r5, r4, r2, lsl #2 + 8015f64: d10c bne.n 8015f80 + 8015f66: f100 0710 add.w r7, r0, #16 + 8015f6a: 4629 mov r1, r5 + 8015f6c: 42b1 cmp r1, r6 + 8015f6e: d334 bcc.n 8015fda + 8015f70: 1a9b subs r3, r3, r2 + 8015f72: 009b lsls r3, r3, #2 + 8015f74: 1eea subs r2, r5, #3 + 8015f76: 4296 cmp r6, r2 + 8015f78: bf38 it cc + 8015f7a: 2300 movcc r3, #0 + 8015f7c: 4423 add r3, r4 + 8015f7e: e015 b.n 8015fac + 8015f80: f854 7022 ldr.w r7, [r4, r2, lsl #2] + 8015f84: f1c1 0820 rsb r8, r1, #32 + 8015f88: 40cf lsrs r7, r1 + 8015f8a: f105 0e04 add.w lr, r5, #4 + 8015f8e: 46a1 mov r9, r4 + 8015f90: 4576 cmp r6, lr + 8015f92: 46f4 mov ip, lr + 8015f94: d815 bhi.n 8015fc2 + 8015f96: 1a9a subs r2, r3, r2 + 8015f98: 0092 lsls r2, r2, #2 + 8015f9a: 3a04 subs r2, #4 + 8015f9c: 3501 adds r5, #1 + 8015f9e: 42ae cmp r6, r5 + 8015fa0: bf38 it cc + 8015fa2: 2200 movcc r2, #0 + 8015fa4: 18a3 adds r3, r4, r2 + 8015fa6: 50a7 str r7, [r4, r2] + 8015fa8: b107 cbz r7, 8015fac + 8015faa: 3304 adds r3, #4 + 8015fac: 1b1a subs r2, r3, r4 + 8015fae: 42a3 cmp r3, r4 + 8015fb0: ea4f 02a2 mov.w r2, r2, asr #2 + 8015fb4: bf08 it eq + 8015fb6: 2300 moveq r3, #0 + 8015fb8: 6102 str r2, [r0, #16] + 8015fba: bf08 it eq + 8015fbc: 6143 streq r3, [r0, #20] + 8015fbe: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8015fc2: f8dc c000 ldr.w ip, [ip] + 8015fc6: fa0c fc08 lsl.w ip, ip, r8 + 8015fca: ea4c 0707 orr.w r7, ip, r7 + 8015fce: f849 7b04 str.w r7, [r9], #4 + 8015fd2: f85e 7b04 ldr.w r7, [lr], #4 + 8015fd6: 40cf lsrs r7, r1 + 8015fd8: e7da b.n 8015f90 + 8015fda: f851 cb04 ldr.w ip, [r1], #4 + 8015fde: f847 cf04 str.w ip, [r7, #4]! + 8015fe2: e7c3 b.n 8015f6c + 8015fe4: 4623 mov r3, r4 + 8015fe6: e7e1 b.n 8015fac + +08015fe8 <__hexdig_fun>: + 8015fe8: f1a0 0330 sub.w r3, r0, #48 ; 0x30 + 8015fec: 2b09 cmp r3, #9 + 8015fee: d802 bhi.n 8015ff6 <__hexdig_fun+0xe> + 8015ff0: 3820 subs r0, #32 + 8015ff2: b2c0 uxtb r0, r0 + 8015ff4: 4770 bx lr + 8015ff6: f1a0 0361 sub.w r3, r0, #97 ; 0x61 + 8015ffa: 2b05 cmp r3, #5 + 8015ffc: d801 bhi.n 8016002 <__hexdig_fun+0x1a> + 8015ffe: 3847 subs r0, #71 ; 0x47 + 8016000: e7f7 b.n 8015ff2 <__hexdig_fun+0xa> + 8016002: f1a0 0341 sub.w r3, r0, #65 ; 0x41 + 8016006: 2b05 cmp r3, #5 + 8016008: d801 bhi.n 801600e <__hexdig_fun+0x26> + 801600a: 3827 subs r0, #39 ; 0x27 + 801600c: e7f1 b.n 8015ff2 <__hexdig_fun+0xa> + 801600e: 2000 movs r0, #0 + 8016010: 4770 bx lr ... -08013b64 <__gethex>: - 8013b64: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8013b68: 4617 mov r7, r2 - 8013b6a: 680a ldr r2, [r1, #0] - 8013b6c: b085 sub sp, #20 - 8013b6e: f102 0b02 add.w fp, r2, #2 - 8013b72: f1c2 22ff rsb r2, r2, #4278255360 ; 0xff00ff00 - 8013b76: f502 027f add.w r2, r2, #16711680 ; 0xff0000 - 8013b7a: 4681 mov r9, r0 - 8013b7c: 468a mov sl, r1 - 8013b7e: 9302 str r3, [sp, #8] - 8013b80: 32fe adds r2, #254 ; 0xfe - 8013b82: eb02 030b add.w r3, r2, fp - 8013b86: 46d8 mov r8, fp - 8013b88: f81b 0b01 ldrb.w r0, [fp], #1 - 8013b8c: 9301 str r3, [sp, #4] - 8013b8e: 2830 cmp r0, #48 ; 0x30 - 8013b90: d0f7 beq.n 8013b82 <__gethex+0x1e> - 8013b92: f7ff ffd1 bl 8013b38 <__hexdig_fun> - 8013b96: 4604 mov r4, r0 - 8013b98: 2800 cmp r0, #0 - 8013b9a: d138 bne.n 8013c0e <__gethex+0xaa> - 8013b9c: 49a7 ldr r1, [pc, #668] ; (8013e3c <__gethex+0x2d8>) - 8013b9e: 2201 movs r2, #1 - 8013ba0: 4640 mov r0, r8 - 8013ba2: f7fe ff62 bl 8012a6a - 8013ba6: 4606 mov r6, r0 - 8013ba8: 2800 cmp r0, #0 - 8013baa: d169 bne.n 8013c80 <__gethex+0x11c> - 8013bac: f898 0001 ldrb.w r0, [r8, #1] - 8013bb0: 465d mov r5, fp - 8013bb2: f7ff ffc1 bl 8013b38 <__hexdig_fun> - 8013bb6: 2800 cmp r0, #0 - 8013bb8: d064 beq.n 8013c84 <__gethex+0x120> - 8013bba: 465a mov r2, fp - 8013bbc: 7810 ldrb r0, [r2, #0] - 8013bbe: 2830 cmp r0, #48 ; 0x30 - 8013bc0: 4690 mov r8, r2 - 8013bc2: f102 0201 add.w r2, r2, #1 - 8013bc6: d0f9 beq.n 8013bbc <__gethex+0x58> - 8013bc8: f7ff ffb6 bl 8013b38 <__hexdig_fun> - 8013bcc: 2301 movs r3, #1 - 8013bce: fab0 f480 clz r4, r0 - 8013bd2: 0964 lsrs r4, r4, #5 - 8013bd4: 465e mov r6, fp - 8013bd6: 9301 str r3, [sp, #4] - 8013bd8: 4642 mov r2, r8 - 8013bda: 4615 mov r5, r2 - 8013bdc: 3201 adds r2, #1 - 8013bde: 7828 ldrb r0, [r5, #0] - 8013be0: f7ff ffaa bl 8013b38 <__hexdig_fun> - 8013be4: 2800 cmp r0, #0 - 8013be6: d1f8 bne.n 8013bda <__gethex+0x76> - 8013be8: 4994 ldr r1, [pc, #592] ; (8013e3c <__gethex+0x2d8>) - 8013bea: 2201 movs r2, #1 - 8013bec: 4628 mov r0, r5 - 8013bee: f7fe ff3c bl 8012a6a - 8013bf2: b978 cbnz r0, 8013c14 <__gethex+0xb0> - 8013bf4: b946 cbnz r6, 8013c08 <__gethex+0xa4> - 8013bf6: 1c6e adds r6, r5, #1 - 8013bf8: 4632 mov r2, r6 - 8013bfa: 4615 mov r5, r2 - 8013bfc: 3201 adds r2, #1 - 8013bfe: 7828 ldrb r0, [r5, #0] - 8013c00: f7ff ff9a bl 8013b38 <__hexdig_fun> - 8013c04: 2800 cmp r0, #0 - 8013c06: d1f8 bne.n 8013bfa <__gethex+0x96> - 8013c08: 1b73 subs r3, r6, r5 - 8013c0a: 009e lsls r6, r3, #2 - 8013c0c: e004 b.n 8013c18 <__gethex+0xb4> - 8013c0e: 2400 movs r4, #0 - 8013c10: 4626 mov r6, r4 - 8013c12: e7e1 b.n 8013bd8 <__gethex+0x74> - 8013c14: 2e00 cmp r6, #0 - 8013c16: d1f7 bne.n 8013c08 <__gethex+0xa4> - 8013c18: 782b ldrb r3, [r5, #0] - 8013c1a: f003 03df and.w r3, r3, #223 ; 0xdf - 8013c1e: 2b50 cmp r3, #80 ; 0x50 - 8013c20: d13d bne.n 8013c9e <__gethex+0x13a> - 8013c22: 786b ldrb r3, [r5, #1] - 8013c24: 2b2b cmp r3, #43 ; 0x2b - 8013c26: d02f beq.n 8013c88 <__gethex+0x124> - 8013c28: 2b2d cmp r3, #45 ; 0x2d - 8013c2a: d031 beq.n 8013c90 <__gethex+0x12c> - 8013c2c: 1c69 adds r1, r5, #1 - 8013c2e: f04f 0b00 mov.w fp, #0 - 8013c32: 7808 ldrb r0, [r1, #0] - 8013c34: f7ff ff80 bl 8013b38 <__hexdig_fun> - 8013c38: 1e42 subs r2, r0, #1 - 8013c3a: b2d2 uxtb r2, r2 - 8013c3c: 2a18 cmp r2, #24 - 8013c3e: d82e bhi.n 8013c9e <__gethex+0x13a> - 8013c40: f1a0 0210 sub.w r2, r0, #16 - 8013c44: f811 0f01 ldrb.w r0, [r1, #1]! - 8013c48: f7ff ff76 bl 8013b38 <__hexdig_fun> - 8013c4c: f100 3cff add.w ip, r0, #4294967295 - 8013c50: fa5f fc8c uxtb.w ip, ip - 8013c54: f1bc 0f18 cmp.w ip, #24 - 8013c58: d91d bls.n 8013c96 <__gethex+0x132> - 8013c5a: f1bb 0f00 cmp.w fp, #0 - 8013c5e: d000 beq.n 8013c62 <__gethex+0xfe> - 8013c60: 4252 negs r2, r2 - 8013c62: 4416 add r6, r2 - 8013c64: f8ca 1000 str.w r1, [sl] - 8013c68: b1dc cbz r4, 8013ca2 <__gethex+0x13e> - 8013c6a: 9b01 ldr r3, [sp, #4] - 8013c6c: 2b00 cmp r3, #0 - 8013c6e: bf14 ite ne - 8013c70: f04f 0800 movne.w r8, #0 - 8013c74: f04f 0806 moveq.w r8, #6 - 8013c78: 4640 mov r0, r8 - 8013c7a: b005 add sp, #20 - 8013c7c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8013c80: 4645 mov r5, r8 - 8013c82: 4626 mov r6, r4 - 8013c84: 2401 movs r4, #1 - 8013c86: e7c7 b.n 8013c18 <__gethex+0xb4> - 8013c88: f04f 0b00 mov.w fp, #0 - 8013c8c: 1ca9 adds r1, r5, #2 - 8013c8e: e7d0 b.n 8013c32 <__gethex+0xce> - 8013c90: f04f 0b01 mov.w fp, #1 - 8013c94: e7fa b.n 8013c8c <__gethex+0x128> - 8013c96: 230a movs r3, #10 - 8013c98: fb03 0002 mla r0, r3, r2, r0 - 8013c9c: e7d0 b.n 8013c40 <__gethex+0xdc> - 8013c9e: 4629 mov r1, r5 - 8013ca0: e7e0 b.n 8013c64 <__gethex+0x100> - 8013ca2: eba5 0308 sub.w r3, r5, r8 - 8013ca6: 3b01 subs r3, #1 - 8013ca8: 4621 mov r1, r4 - 8013caa: 2b07 cmp r3, #7 - 8013cac: dc0a bgt.n 8013cc4 <__gethex+0x160> - 8013cae: 4648 mov r0, r9 - 8013cb0: f000 fa5a bl 8014168 <_Balloc> - 8013cb4: 4604 mov r4, r0 - 8013cb6: b940 cbnz r0, 8013cca <__gethex+0x166> - 8013cb8: 4b61 ldr r3, [pc, #388] ; (8013e40 <__gethex+0x2dc>) - 8013cba: 4602 mov r2, r0 - 8013cbc: 21e4 movs r1, #228 ; 0xe4 - 8013cbe: 4861 ldr r0, [pc, #388] ; (8013e44 <__gethex+0x2e0>) - 8013cc0: f7ff f804 bl 8012ccc <__assert_func> - 8013cc4: 3101 adds r1, #1 - 8013cc6: 105b asrs r3, r3, #1 - 8013cc8: e7ef b.n 8013caa <__gethex+0x146> - 8013cca: f100 0a14 add.w sl, r0, #20 - 8013cce: 2300 movs r3, #0 - 8013cd0: 495a ldr r1, [pc, #360] ; (8013e3c <__gethex+0x2d8>) - 8013cd2: f8cd a004 str.w sl, [sp, #4] - 8013cd6: 469b mov fp, r3 - 8013cd8: 45a8 cmp r8, r5 - 8013cda: d342 bcc.n 8013d62 <__gethex+0x1fe> - 8013cdc: 9801 ldr r0, [sp, #4] - 8013cde: f840 bb04 str.w fp, [r0], #4 - 8013ce2: eba0 000a sub.w r0, r0, sl - 8013ce6: 1080 asrs r0, r0, #2 - 8013ce8: 6120 str r0, [r4, #16] - 8013cea: ea4f 1840 mov.w r8, r0, lsl #5 - 8013cee: 4658 mov r0, fp - 8013cf0: f000 fb2c bl 801434c <__hi0bits> - 8013cf4: 683d ldr r5, [r7, #0] - 8013cf6: eba8 0000 sub.w r0, r8, r0 - 8013cfa: 42a8 cmp r0, r5 - 8013cfc: dd59 ble.n 8013db2 <__gethex+0x24e> - 8013cfe: eba0 0805 sub.w r8, r0, r5 - 8013d02: 4641 mov r1, r8 - 8013d04: 4620 mov r0, r4 - 8013d06: f000 febb bl 8014a80 <__any_on> - 8013d0a: 4683 mov fp, r0 - 8013d0c: b1b8 cbz r0, 8013d3e <__gethex+0x1da> - 8013d0e: f108 33ff add.w r3, r8, #4294967295 - 8013d12: 1159 asrs r1, r3, #5 - 8013d14: f003 021f and.w r2, r3, #31 - 8013d18: f85a 1021 ldr.w r1, [sl, r1, lsl #2] - 8013d1c: f04f 0b01 mov.w fp, #1 - 8013d20: fa0b f202 lsl.w r2, fp, r2 - 8013d24: 420a tst r2, r1 - 8013d26: d00a beq.n 8013d3e <__gethex+0x1da> - 8013d28: 455b cmp r3, fp - 8013d2a: dd06 ble.n 8013d3a <__gethex+0x1d6> - 8013d2c: f1a8 0102 sub.w r1, r8, #2 - 8013d30: 4620 mov r0, r4 - 8013d32: f000 fea5 bl 8014a80 <__any_on> - 8013d36: 2800 cmp r0, #0 - 8013d38: d138 bne.n 8013dac <__gethex+0x248> - 8013d3a: f04f 0b02 mov.w fp, #2 - 8013d3e: 4641 mov r1, r8 - 8013d40: 4620 mov r0, r4 - 8013d42: f7ff fea7 bl 8013a94 - 8013d46: 4446 add r6, r8 - 8013d48: 68bb ldr r3, [r7, #8] - 8013d4a: 42b3 cmp r3, r6 - 8013d4c: da41 bge.n 8013dd2 <__gethex+0x26e> - 8013d4e: 4621 mov r1, r4 - 8013d50: 4648 mov r0, r9 - 8013d52: f000 fa49 bl 80141e8 <_Bfree> - 8013d56: 9a0e ldr r2, [sp, #56] ; 0x38 - 8013d58: 2300 movs r3, #0 - 8013d5a: 6013 str r3, [r2, #0] - 8013d5c: f04f 08a3 mov.w r8, #163 ; 0xa3 - 8013d60: e78a b.n 8013c78 <__gethex+0x114> - 8013d62: f815 2d01 ldrb.w r2, [r5, #-1]! - 8013d66: 2a2e cmp r2, #46 ; 0x2e - 8013d68: d014 beq.n 8013d94 <__gethex+0x230> - 8013d6a: 2b20 cmp r3, #32 - 8013d6c: d106 bne.n 8013d7c <__gethex+0x218> - 8013d6e: 9b01 ldr r3, [sp, #4] - 8013d70: f843 bb04 str.w fp, [r3], #4 - 8013d74: f04f 0b00 mov.w fp, #0 - 8013d78: 9301 str r3, [sp, #4] - 8013d7a: 465b mov r3, fp - 8013d7c: 7828 ldrb r0, [r5, #0] - 8013d7e: 9303 str r3, [sp, #12] - 8013d80: f7ff feda bl 8013b38 <__hexdig_fun> - 8013d84: 9b03 ldr r3, [sp, #12] - 8013d86: f000 000f and.w r0, r0, #15 - 8013d8a: 4098 lsls r0, r3 - 8013d8c: ea4b 0b00 orr.w fp, fp, r0 - 8013d90: 3304 adds r3, #4 - 8013d92: e7a1 b.n 8013cd8 <__gethex+0x174> - 8013d94: 45a8 cmp r8, r5 - 8013d96: d8e8 bhi.n 8013d6a <__gethex+0x206> - 8013d98: 2201 movs r2, #1 - 8013d9a: 4628 mov r0, r5 - 8013d9c: 9303 str r3, [sp, #12] - 8013d9e: f7fe fe64 bl 8012a6a - 8013da2: 4926 ldr r1, [pc, #152] ; (8013e3c <__gethex+0x2d8>) - 8013da4: 9b03 ldr r3, [sp, #12] - 8013da6: 2800 cmp r0, #0 - 8013da8: d1df bne.n 8013d6a <__gethex+0x206> - 8013daa: e795 b.n 8013cd8 <__gethex+0x174> - 8013dac: f04f 0b03 mov.w fp, #3 - 8013db0: e7c5 b.n 8013d3e <__gethex+0x1da> - 8013db2: da0b bge.n 8013dcc <__gethex+0x268> - 8013db4: eba5 0800 sub.w r8, r5, r0 - 8013db8: 4621 mov r1, r4 - 8013dba: 4642 mov r2, r8 - 8013dbc: 4648 mov r0, r9 - 8013dbe: f000 fc2d bl 801461c <__lshift> - 8013dc2: eba6 0608 sub.w r6, r6, r8 - 8013dc6: 4604 mov r4, r0 - 8013dc8: f100 0a14 add.w sl, r0, #20 - 8013dcc: f04f 0b00 mov.w fp, #0 - 8013dd0: e7ba b.n 8013d48 <__gethex+0x1e4> - 8013dd2: 687b ldr r3, [r7, #4] - 8013dd4: 42b3 cmp r3, r6 - 8013dd6: dd73 ble.n 8013ec0 <__gethex+0x35c> - 8013dd8: 1b9e subs r6, r3, r6 - 8013dda: 42b5 cmp r5, r6 - 8013ddc: dc34 bgt.n 8013e48 <__gethex+0x2e4> - 8013dde: 68fb ldr r3, [r7, #12] - 8013de0: 2b02 cmp r3, #2 - 8013de2: d023 beq.n 8013e2c <__gethex+0x2c8> - 8013de4: 2b03 cmp r3, #3 - 8013de6: d025 beq.n 8013e34 <__gethex+0x2d0> - 8013de8: 2b01 cmp r3, #1 - 8013dea: d115 bne.n 8013e18 <__gethex+0x2b4> - 8013dec: 42b5 cmp r5, r6 - 8013dee: d113 bne.n 8013e18 <__gethex+0x2b4> - 8013df0: 2d01 cmp r5, #1 - 8013df2: d10b bne.n 8013e0c <__gethex+0x2a8> - 8013df4: 9a02 ldr r2, [sp, #8] - 8013df6: 687b ldr r3, [r7, #4] - 8013df8: 6013 str r3, [r2, #0] - 8013dfa: 2301 movs r3, #1 - 8013dfc: 6123 str r3, [r4, #16] - 8013dfe: f8ca 3000 str.w r3, [sl] - 8013e02: 9b0e ldr r3, [sp, #56] ; 0x38 - 8013e04: f04f 0862 mov.w r8, #98 ; 0x62 - 8013e08: 601c str r4, [r3, #0] - 8013e0a: e735 b.n 8013c78 <__gethex+0x114> - 8013e0c: 1e69 subs r1, r5, #1 - 8013e0e: 4620 mov r0, r4 - 8013e10: f000 fe36 bl 8014a80 <__any_on> - 8013e14: 2800 cmp r0, #0 - 8013e16: d1ed bne.n 8013df4 <__gethex+0x290> - 8013e18: 4621 mov r1, r4 - 8013e1a: 4648 mov r0, r9 - 8013e1c: f000 f9e4 bl 80141e8 <_Bfree> - 8013e20: 9a0e ldr r2, [sp, #56] ; 0x38 - 8013e22: 2300 movs r3, #0 - 8013e24: 6013 str r3, [r2, #0] - 8013e26: f04f 0850 mov.w r8, #80 ; 0x50 - 8013e2a: e725 b.n 8013c78 <__gethex+0x114> - 8013e2c: 9b0f ldr r3, [sp, #60] ; 0x3c - 8013e2e: 2b00 cmp r3, #0 - 8013e30: d1f2 bne.n 8013e18 <__gethex+0x2b4> - 8013e32: e7df b.n 8013df4 <__gethex+0x290> - 8013e34: 9b0f ldr r3, [sp, #60] ; 0x3c - 8013e36: 2b00 cmp r3, #0 - 8013e38: d1dc bne.n 8013df4 <__gethex+0x290> - 8013e3a: e7ed b.n 8013e18 <__gethex+0x2b4> - 8013e3c: 08018714 .word 0x08018714 - 8013e40: 080189bc .word 0x080189bc - 8013e44: 080189cd .word 0x080189cd - 8013e48: f106 38ff add.w r8, r6, #4294967295 - 8013e4c: f1bb 0f00 cmp.w fp, #0 - 8013e50: d133 bne.n 8013eba <__gethex+0x356> - 8013e52: f1b8 0f00 cmp.w r8, #0 - 8013e56: d004 beq.n 8013e62 <__gethex+0x2fe> - 8013e58: 4641 mov r1, r8 - 8013e5a: 4620 mov r0, r4 - 8013e5c: f000 fe10 bl 8014a80 <__any_on> - 8013e60: 4683 mov fp, r0 - 8013e62: ea4f 1268 mov.w r2, r8, asr #5 - 8013e66: 2301 movs r3, #1 - 8013e68: f85a 2022 ldr.w r2, [sl, r2, lsl #2] - 8013e6c: f008 081f and.w r8, r8, #31 - 8013e70: fa03 f308 lsl.w r3, r3, r8 - 8013e74: 4213 tst r3, r2 - 8013e76: 4631 mov r1, r6 - 8013e78: 4620 mov r0, r4 - 8013e7a: bf18 it ne - 8013e7c: f04b 0b02 orrne.w fp, fp, #2 - 8013e80: 1bad subs r5, r5, r6 - 8013e82: f7ff fe07 bl 8013a94 - 8013e86: 687e ldr r6, [r7, #4] - 8013e88: f04f 0802 mov.w r8, #2 - 8013e8c: f1bb 0f00 cmp.w fp, #0 - 8013e90: d04a beq.n 8013f28 <__gethex+0x3c4> - 8013e92: 68fb ldr r3, [r7, #12] - 8013e94: 2b02 cmp r3, #2 - 8013e96: d016 beq.n 8013ec6 <__gethex+0x362> - 8013e98: 2b03 cmp r3, #3 - 8013e9a: d018 beq.n 8013ece <__gethex+0x36a> - 8013e9c: 2b01 cmp r3, #1 - 8013e9e: d109 bne.n 8013eb4 <__gethex+0x350> - 8013ea0: f01b 0f02 tst.w fp, #2 - 8013ea4: d006 beq.n 8013eb4 <__gethex+0x350> - 8013ea6: f8da 3000 ldr.w r3, [sl] - 8013eaa: ea4b 0b03 orr.w fp, fp, r3 - 8013eae: f01b 0f01 tst.w fp, #1 - 8013eb2: d10f bne.n 8013ed4 <__gethex+0x370> - 8013eb4: f048 0810 orr.w r8, r8, #16 - 8013eb8: e036 b.n 8013f28 <__gethex+0x3c4> - 8013eba: f04f 0b01 mov.w fp, #1 - 8013ebe: e7d0 b.n 8013e62 <__gethex+0x2fe> - 8013ec0: f04f 0801 mov.w r8, #1 - 8013ec4: e7e2 b.n 8013e8c <__gethex+0x328> - 8013ec6: 9b0f ldr r3, [sp, #60] ; 0x3c - 8013ec8: f1c3 0301 rsb r3, r3, #1 - 8013ecc: 930f str r3, [sp, #60] ; 0x3c - 8013ece: 9b0f ldr r3, [sp, #60] ; 0x3c - 8013ed0: 2b00 cmp r3, #0 - 8013ed2: d0ef beq.n 8013eb4 <__gethex+0x350> - 8013ed4: f8d4 b010 ldr.w fp, [r4, #16] - 8013ed8: f104 0214 add.w r2, r4, #20 - 8013edc: ea4f 038b mov.w r3, fp, lsl #2 - 8013ee0: 9301 str r3, [sp, #4] - 8013ee2: eb02 008b add.w r0, r2, fp, lsl #2 - 8013ee6: 2300 movs r3, #0 - 8013ee8: 4694 mov ip, r2 - 8013eea: f852 1b04 ldr.w r1, [r2], #4 - 8013eee: f1b1 3fff cmp.w r1, #4294967295 - 8013ef2: d01e beq.n 8013f32 <__gethex+0x3ce> - 8013ef4: 3101 adds r1, #1 - 8013ef6: f8cc 1000 str.w r1, [ip] - 8013efa: f1b8 0f02 cmp.w r8, #2 - 8013efe: f104 0214 add.w r2, r4, #20 - 8013f02: d13d bne.n 8013f80 <__gethex+0x41c> - 8013f04: 683b ldr r3, [r7, #0] - 8013f06: 3b01 subs r3, #1 - 8013f08: 42ab cmp r3, r5 - 8013f0a: d10b bne.n 8013f24 <__gethex+0x3c0> - 8013f0c: 1169 asrs r1, r5, #5 - 8013f0e: 2301 movs r3, #1 - 8013f10: f005 051f and.w r5, r5, #31 - 8013f14: fa03 f505 lsl.w r5, r3, r5 - 8013f18: f852 3021 ldr.w r3, [r2, r1, lsl #2] - 8013f1c: 421d tst r5, r3 - 8013f1e: bf18 it ne - 8013f20: f04f 0801 movne.w r8, #1 - 8013f24: f048 0820 orr.w r8, r8, #32 - 8013f28: 9b0e ldr r3, [sp, #56] ; 0x38 - 8013f2a: 601c str r4, [r3, #0] - 8013f2c: 9b02 ldr r3, [sp, #8] - 8013f2e: 601e str r6, [r3, #0] - 8013f30: e6a2 b.n 8013c78 <__gethex+0x114> - 8013f32: 4290 cmp r0, r2 - 8013f34: f842 3c04 str.w r3, [r2, #-4] - 8013f38: d8d6 bhi.n 8013ee8 <__gethex+0x384> - 8013f3a: 68a2 ldr r2, [r4, #8] - 8013f3c: 4593 cmp fp, r2 - 8013f3e: db17 blt.n 8013f70 <__gethex+0x40c> - 8013f40: 6861 ldr r1, [r4, #4] - 8013f42: 4648 mov r0, r9 - 8013f44: 3101 adds r1, #1 - 8013f46: f000 f90f bl 8014168 <_Balloc> - 8013f4a: 4682 mov sl, r0 - 8013f4c: b918 cbnz r0, 8013f56 <__gethex+0x3f2> - 8013f4e: 4b1b ldr r3, [pc, #108] ; (8013fbc <__gethex+0x458>) - 8013f50: 4602 mov r2, r0 - 8013f52: 2184 movs r1, #132 ; 0x84 - 8013f54: e6b3 b.n 8013cbe <__gethex+0x15a> - 8013f56: 6922 ldr r2, [r4, #16] - 8013f58: 3202 adds r2, #2 - 8013f5a: f104 010c add.w r1, r4, #12 - 8013f5e: 0092 lsls r2, r2, #2 - 8013f60: 300c adds r0, #12 - 8013f62: f7fe fe96 bl 8012c92 - 8013f66: 4621 mov r1, r4 - 8013f68: 4648 mov r0, r9 - 8013f6a: f000 f93d bl 80141e8 <_Bfree> - 8013f6e: 4654 mov r4, sl - 8013f70: 6922 ldr r2, [r4, #16] - 8013f72: 1c51 adds r1, r2, #1 - 8013f74: eb04 0282 add.w r2, r4, r2, lsl #2 - 8013f78: 6121 str r1, [r4, #16] - 8013f7a: 2101 movs r1, #1 - 8013f7c: 6151 str r1, [r2, #20] - 8013f7e: e7bc b.n 8013efa <__gethex+0x396> - 8013f80: 6921 ldr r1, [r4, #16] - 8013f82: 4559 cmp r1, fp - 8013f84: dd0b ble.n 8013f9e <__gethex+0x43a> - 8013f86: 2101 movs r1, #1 - 8013f88: 4620 mov r0, r4 - 8013f8a: f7ff fd83 bl 8013a94 - 8013f8e: 68bb ldr r3, [r7, #8] - 8013f90: 3601 adds r6, #1 - 8013f92: 42b3 cmp r3, r6 - 8013f94: f6ff aedb blt.w 8013d4e <__gethex+0x1ea> - 8013f98: f04f 0801 mov.w r8, #1 - 8013f9c: e7c2 b.n 8013f24 <__gethex+0x3c0> - 8013f9e: f015 051f ands.w r5, r5, #31 - 8013fa2: d0f9 beq.n 8013f98 <__gethex+0x434> - 8013fa4: 9b01 ldr r3, [sp, #4] - 8013fa6: 441a add r2, r3 - 8013fa8: f1c5 0520 rsb r5, r5, #32 - 8013fac: f852 0c04 ldr.w r0, [r2, #-4] - 8013fb0: f000 f9cc bl 801434c <__hi0bits> - 8013fb4: 42a8 cmp r0, r5 - 8013fb6: dbe6 blt.n 8013f86 <__gethex+0x422> - 8013fb8: e7ee b.n 8013f98 <__gethex+0x434> - 8013fba: bf00 nop - 8013fbc: 080189bc .word 0x080189bc - -08013fc0 : - 8013fc0: f1c2 0208 rsb r2, r2, #8 - 8013fc4: 0092 lsls r2, r2, #2 - 8013fc6: b570 push {r4, r5, r6, lr} - 8013fc8: f1c2 0620 rsb r6, r2, #32 - 8013fcc: 6843 ldr r3, [r0, #4] - 8013fce: 6804 ldr r4, [r0, #0] - 8013fd0: fa03 f506 lsl.w r5, r3, r6 - 8013fd4: 432c orrs r4, r5 - 8013fd6: 40d3 lsrs r3, r2 - 8013fd8: 6004 str r4, [r0, #0] - 8013fda: f840 3f04 str.w r3, [r0, #4]! - 8013fde: 4288 cmp r0, r1 - 8013fe0: d3f4 bcc.n 8013fcc - 8013fe2: bd70 pop {r4, r5, r6, pc} - -08013fe4 <__match>: - 8013fe4: b530 push {r4, r5, lr} - 8013fe6: 6803 ldr r3, [r0, #0] - 8013fe8: 3301 adds r3, #1 - 8013fea: f811 4b01 ldrb.w r4, [r1], #1 - 8013fee: b914 cbnz r4, 8013ff6 <__match+0x12> - 8013ff0: 6003 str r3, [r0, #0] - 8013ff2: 2001 movs r0, #1 - 8013ff4: bd30 pop {r4, r5, pc} - 8013ff6: f813 2b01 ldrb.w r2, [r3], #1 - 8013ffa: f1a2 0541 sub.w r5, r2, #65 ; 0x41 - 8013ffe: 2d19 cmp r5, #25 - 8014000: bf98 it ls - 8014002: 3220 addls r2, #32 - 8014004: 42a2 cmp r2, r4 - 8014006: d0f0 beq.n 8013fea <__match+0x6> - 8014008: 2000 movs r0, #0 - 801400a: e7f3 b.n 8013ff4 <__match+0x10> - -0801400c <__hexnan>: - 801400c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8014010: 680b ldr r3, [r1, #0] - 8014012: 6801 ldr r1, [r0, #0] - 8014014: 115e asrs r6, r3, #5 - 8014016: eb02 0686 add.w r6, r2, r6, lsl #2 - 801401a: f013 031f ands.w r3, r3, #31 - 801401e: b087 sub sp, #28 - 8014020: bf18 it ne - 8014022: 3604 addne r6, #4 - 8014024: 2500 movs r5, #0 - 8014026: 1f37 subs r7, r6, #4 - 8014028: 4682 mov sl, r0 - 801402a: 4690 mov r8, r2 - 801402c: 9301 str r3, [sp, #4] - 801402e: f846 5c04 str.w r5, [r6, #-4] - 8014032: 46b9 mov r9, r7 - 8014034: 463c mov r4, r7 - 8014036: 9502 str r5, [sp, #8] - 8014038: 46ab mov fp, r5 - 801403a: 784a ldrb r2, [r1, #1] - 801403c: 1c4b adds r3, r1, #1 - 801403e: 9303 str r3, [sp, #12] - 8014040: b342 cbz r2, 8014094 <__hexnan+0x88> - 8014042: 4610 mov r0, r2 - 8014044: 9105 str r1, [sp, #20] - 8014046: 9204 str r2, [sp, #16] - 8014048: f7ff fd76 bl 8013b38 <__hexdig_fun> - 801404c: 2800 cmp r0, #0 - 801404e: d14f bne.n 80140f0 <__hexnan+0xe4> - 8014050: 9a04 ldr r2, [sp, #16] - 8014052: 9905 ldr r1, [sp, #20] - 8014054: 2a20 cmp r2, #32 - 8014056: d818 bhi.n 801408a <__hexnan+0x7e> - 8014058: 9b02 ldr r3, [sp, #8] - 801405a: 459b cmp fp, r3 - 801405c: dd13 ble.n 8014086 <__hexnan+0x7a> - 801405e: 454c cmp r4, r9 - 8014060: d206 bcs.n 8014070 <__hexnan+0x64> - 8014062: 2d07 cmp r5, #7 - 8014064: dc04 bgt.n 8014070 <__hexnan+0x64> - 8014066: 462a mov r2, r5 - 8014068: 4649 mov r1, r9 - 801406a: 4620 mov r0, r4 - 801406c: f7ff ffa8 bl 8013fc0 - 8014070: 4544 cmp r4, r8 - 8014072: d950 bls.n 8014116 <__hexnan+0x10a> - 8014074: 2300 movs r3, #0 - 8014076: f1a4 0904 sub.w r9, r4, #4 - 801407a: f844 3c04 str.w r3, [r4, #-4] - 801407e: f8cd b008 str.w fp, [sp, #8] - 8014082: 464c mov r4, r9 - 8014084: 461d mov r5, r3 - 8014086: 9903 ldr r1, [sp, #12] - 8014088: e7d7 b.n 801403a <__hexnan+0x2e> - 801408a: 2a29 cmp r2, #41 ; 0x29 - 801408c: d155 bne.n 801413a <__hexnan+0x12e> - 801408e: 3102 adds r1, #2 - 8014090: f8ca 1000 str.w r1, [sl] - 8014094: f1bb 0f00 cmp.w fp, #0 - 8014098: d04f beq.n 801413a <__hexnan+0x12e> - 801409a: 454c cmp r4, r9 - 801409c: d206 bcs.n 80140ac <__hexnan+0xa0> - 801409e: 2d07 cmp r5, #7 - 80140a0: dc04 bgt.n 80140ac <__hexnan+0xa0> - 80140a2: 462a mov r2, r5 - 80140a4: 4649 mov r1, r9 - 80140a6: 4620 mov r0, r4 - 80140a8: f7ff ff8a bl 8013fc0 - 80140ac: 4544 cmp r4, r8 - 80140ae: d934 bls.n 801411a <__hexnan+0x10e> - 80140b0: f1a8 0204 sub.w r2, r8, #4 - 80140b4: 4623 mov r3, r4 - 80140b6: f853 1b04 ldr.w r1, [r3], #4 - 80140ba: f842 1f04 str.w r1, [r2, #4]! - 80140be: 429f cmp r7, r3 - 80140c0: d2f9 bcs.n 80140b6 <__hexnan+0xaa> - 80140c2: 1b3b subs r3, r7, r4 - 80140c4: f023 0303 bic.w r3, r3, #3 - 80140c8: 3304 adds r3, #4 - 80140ca: 3e03 subs r6, #3 - 80140cc: 3401 adds r4, #1 - 80140ce: 42a6 cmp r6, r4 - 80140d0: bf38 it cc - 80140d2: 2304 movcc r3, #4 - 80140d4: 4443 add r3, r8 - 80140d6: 2200 movs r2, #0 - 80140d8: f843 2b04 str.w r2, [r3], #4 - 80140dc: 429f cmp r7, r3 - 80140de: d2fb bcs.n 80140d8 <__hexnan+0xcc> - 80140e0: 683b ldr r3, [r7, #0] - 80140e2: b91b cbnz r3, 80140ec <__hexnan+0xe0> - 80140e4: 4547 cmp r7, r8 - 80140e6: d126 bne.n 8014136 <__hexnan+0x12a> - 80140e8: 2301 movs r3, #1 - 80140ea: 603b str r3, [r7, #0] - 80140ec: 2005 movs r0, #5 - 80140ee: e025 b.n 801413c <__hexnan+0x130> - 80140f0: 3501 adds r5, #1 - 80140f2: 2d08 cmp r5, #8 - 80140f4: f10b 0b01 add.w fp, fp, #1 - 80140f8: dd06 ble.n 8014108 <__hexnan+0xfc> - 80140fa: 4544 cmp r4, r8 - 80140fc: d9c3 bls.n 8014086 <__hexnan+0x7a> - 80140fe: 2300 movs r3, #0 - 8014100: f844 3c04 str.w r3, [r4, #-4] - 8014104: 2501 movs r5, #1 - 8014106: 3c04 subs r4, #4 - 8014108: 6822 ldr r2, [r4, #0] - 801410a: f000 000f and.w r0, r0, #15 - 801410e: ea40 1002 orr.w r0, r0, r2, lsl #4 - 8014112: 6020 str r0, [r4, #0] - 8014114: e7b7 b.n 8014086 <__hexnan+0x7a> - 8014116: 2508 movs r5, #8 - 8014118: e7b5 b.n 8014086 <__hexnan+0x7a> - 801411a: 9b01 ldr r3, [sp, #4] - 801411c: 2b00 cmp r3, #0 - 801411e: d0df beq.n 80140e0 <__hexnan+0xd4> - 8014120: f1c3 0320 rsb r3, r3, #32 - 8014124: f04f 32ff mov.w r2, #4294967295 - 8014128: 40da lsrs r2, r3 - 801412a: f856 3c04 ldr.w r3, [r6, #-4] - 801412e: 4013 ands r3, r2 - 8014130: f846 3c04 str.w r3, [r6, #-4] - 8014134: e7d4 b.n 80140e0 <__hexnan+0xd4> - 8014136: 3f04 subs r7, #4 - 8014138: e7d2 b.n 80140e0 <__hexnan+0xd4> - 801413a: 2004 movs r0, #4 - 801413c: b007 add sp, #28 - 801413e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - -08014142 <__ascii_mbtowc>: - 8014142: b082 sub sp, #8 - 8014144: b901 cbnz r1, 8014148 <__ascii_mbtowc+0x6> - 8014146: a901 add r1, sp, #4 - 8014148: b142 cbz r2, 801415c <__ascii_mbtowc+0x1a> - 801414a: b14b cbz r3, 8014160 <__ascii_mbtowc+0x1e> - 801414c: 7813 ldrb r3, [r2, #0] - 801414e: 600b str r3, [r1, #0] - 8014150: 7812 ldrb r2, [r2, #0] - 8014152: 1e10 subs r0, r2, #0 - 8014154: bf18 it ne - 8014156: 2001 movne r0, #1 - 8014158: b002 add sp, #8 - 801415a: 4770 bx lr - 801415c: 4610 mov r0, r2 - 801415e: e7fb b.n 8014158 <__ascii_mbtowc+0x16> - 8014160: f06f 0001 mvn.w r0, #1 - 8014164: e7f8 b.n 8014158 <__ascii_mbtowc+0x16> +08016014 <__gethex>: + 8016014: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8016018: 4617 mov r7, r2 + 801601a: 680a ldr r2, [r1, #0] + 801601c: b085 sub sp, #20 + 801601e: f102 0b02 add.w fp, r2, #2 + 8016022: f1c2 22ff rsb r2, r2, #4278255360 ; 0xff00ff00 + 8016026: f502 027f add.w r2, r2, #16711680 ; 0xff0000 + 801602a: 4681 mov r9, r0 + 801602c: 468a mov sl, r1 + 801602e: 9302 str r3, [sp, #8] + 8016030: 32fe adds r2, #254 ; 0xfe + 8016032: eb02 030b add.w r3, r2, fp + 8016036: 46d8 mov r8, fp + 8016038: f81b 0b01 ldrb.w r0, [fp], #1 + 801603c: 9301 str r3, [sp, #4] + 801603e: 2830 cmp r0, #48 ; 0x30 + 8016040: d0f7 beq.n 8016032 <__gethex+0x1e> + 8016042: f7ff ffd1 bl 8015fe8 <__hexdig_fun> + 8016046: 4604 mov r4, r0 + 8016048: 2800 cmp r0, #0 + 801604a: d138 bne.n 80160be <__gethex+0xaa> + 801604c: 49a7 ldr r1, [pc, #668] ; (80162ec <__gethex+0x2d8>) + 801604e: 2201 movs r2, #1 + 8016050: 4640 mov r0, r8 + 8016052: f7fe ff62 bl 8014f1a + 8016056: 4606 mov r6, r0 + 8016058: 2800 cmp r0, #0 + 801605a: d169 bne.n 8016130 <__gethex+0x11c> + 801605c: f898 0001 ldrb.w r0, [r8, #1] + 8016060: 465d mov r5, fp + 8016062: f7ff ffc1 bl 8015fe8 <__hexdig_fun> + 8016066: 2800 cmp r0, #0 + 8016068: d064 beq.n 8016134 <__gethex+0x120> + 801606a: 465a mov r2, fp + 801606c: 7810 ldrb r0, [r2, #0] + 801606e: 2830 cmp r0, #48 ; 0x30 + 8016070: 4690 mov r8, r2 + 8016072: f102 0201 add.w r2, r2, #1 + 8016076: d0f9 beq.n 801606c <__gethex+0x58> + 8016078: f7ff ffb6 bl 8015fe8 <__hexdig_fun> + 801607c: 2301 movs r3, #1 + 801607e: fab0 f480 clz r4, r0 + 8016082: 0964 lsrs r4, r4, #5 + 8016084: 465e mov r6, fp + 8016086: 9301 str r3, [sp, #4] + 8016088: 4642 mov r2, r8 + 801608a: 4615 mov r5, r2 + 801608c: 3201 adds r2, #1 + 801608e: 7828 ldrb r0, [r5, #0] + 8016090: f7ff ffaa bl 8015fe8 <__hexdig_fun> + 8016094: 2800 cmp r0, #0 + 8016096: d1f8 bne.n 801608a <__gethex+0x76> + 8016098: 4994 ldr r1, [pc, #592] ; (80162ec <__gethex+0x2d8>) + 801609a: 2201 movs r2, #1 + 801609c: 4628 mov r0, r5 + 801609e: f7fe ff3c bl 8014f1a + 80160a2: b978 cbnz r0, 80160c4 <__gethex+0xb0> + 80160a4: b946 cbnz r6, 80160b8 <__gethex+0xa4> + 80160a6: 1c6e adds r6, r5, #1 + 80160a8: 4632 mov r2, r6 + 80160aa: 4615 mov r5, r2 + 80160ac: 3201 adds r2, #1 + 80160ae: 7828 ldrb r0, [r5, #0] + 80160b0: f7ff ff9a bl 8015fe8 <__hexdig_fun> + 80160b4: 2800 cmp r0, #0 + 80160b6: d1f8 bne.n 80160aa <__gethex+0x96> + 80160b8: 1b73 subs r3, r6, r5 + 80160ba: 009e lsls r6, r3, #2 + 80160bc: e004 b.n 80160c8 <__gethex+0xb4> + 80160be: 2400 movs r4, #0 + 80160c0: 4626 mov r6, r4 + 80160c2: e7e1 b.n 8016088 <__gethex+0x74> + 80160c4: 2e00 cmp r6, #0 + 80160c6: d1f7 bne.n 80160b8 <__gethex+0xa4> + 80160c8: 782b ldrb r3, [r5, #0] + 80160ca: f003 03df and.w r3, r3, #223 ; 0xdf + 80160ce: 2b50 cmp r3, #80 ; 0x50 + 80160d0: d13d bne.n 801614e <__gethex+0x13a> + 80160d2: 786b ldrb r3, [r5, #1] + 80160d4: 2b2b cmp r3, #43 ; 0x2b + 80160d6: d02f beq.n 8016138 <__gethex+0x124> + 80160d8: 2b2d cmp r3, #45 ; 0x2d + 80160da: d031 beq.n 8016140 <__gethex+0x12c> + 80160dc: 1c69 adds r1, r5, #1 + 80160de: f04f 0b00 mov.w fp, #0 + 80160e2: 7808 ldrb r0, [r1, #0] + 80160e4: f7ff ff80 bl 8015fe8 <__hexdig_fun> + 80160e8: 1e42 subs r2, r0, #1 + 80160ea: b2d2 uxtb r2, r2 + 80160ec: 2a18 cmp r2, #24 + 80160ee: d82e bhi.n 801614e <__gethex+0x13a> + 80160f0: f1a0 0210 sub.w r2, r0, #16 + 80160f4: f811 0f01 ldrb.w r0, [r1, #1]! + 80160f8: f7ff ff76 bl 8015fe8 <__hexdig_fun> + 80160fc: f100 3cff add.w ip, r0, #4294967295 + 8016100: fa5f fc8c uxtb.w ip, ip + 8016104: f1bc 0f18 cmp.w ip, #24 + 8016108: d91d bls.n 8016146 <__gethex+0x132> + 801610a: f1bb 0f00 cmp.w fp, #0 + 801610e: d000 beq.n 8016112 <__gethex+0xfe> + 8016110: 4252 negs r2, r2 + 8016112: 4416 add r6, r2 + 8016114: f8ca 1000 str.w r1, [sl] + 8016118: b1dc cbz r4, 8016152 <__gethex+0x13e> + 801611a: 9b01 ldr r3, [sp, #4] + 801611c: 2b00 cmp r3, #0 + 801611e: bf14 ite ne + 8016120: f04f 0800 movne.w r8, #0 + 8016124: f04f 0806 moveq.w r8, #6 + 8016128: 4640 mov r0, r8 + 801612a: b005 add sp, #20 + 801612c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8016130: 4645 mov r5, r8 + 8016132: 4626 mov r6, r4 + 8016134: 2401 movs r4, #1 + 8016136: e7c7 b.n 80160c8 <__gethex+0xb4> + 8016138: f04f 0b00 mov.w fp, #0 + 801613c: 1ca9 adds r1, r5, #2 + 801613e: e7d0 b.n 80160e2 <__gethex+0xce> + 8016140: f04f 0b01 mov.w fp, #1 + 8016144: e7fa b.n 801613c <__gethex+0x128> + 8016146: 230a movs r3, #10 + 8016148: fb03 0002 mla r0, r3, r2, r0 + 801614c: e7d0 b.n 80160f0 <__gethex+0xdc> + 801614e: 4629 mov r1, r5 + 8016150: e7e0 b.n 8016114 <__gethex+0x100> + 8016152: eba5 0308 sub.w r3, r5, r8 + 8016156: 3b01 subs r3, #1 + 8016158: 4621 mov r1, r4 + 801615a: 2b07 cmp r3, #7 + 801615c: dc0a bgt.n 8016174 <__gethex+0x160> + 801615e: 4648 mov r0, r9 + 8016160: f000 fa5a bl 8016618 <_Balloc> + 8016164: 4604 mov r4, r0 + 8016166: b940 cbnz r0, 801617a <__gethex+0x166> + 8016168: 4b61 ldr r3, [pc, #388] ; (80162f0 <__gethex+0x2dc>) + 801616a: 4602 mov r2, r0 + 801616c: 21e4 movs r1, #228 ; 0xe4 + 801616e: 4861 ldr r0, [pc, #388] ; (80162f4 <__gethex+0x2e0>) + 8016170: f7ff f804 bl 801517c <__assert_func> + 8016174: 3101 adds r1, #1 + 8016176: 105b asrs r3, r3, #1 + 8016178: e7ef b.n 801615a <__gethex+0x146> + 801617a: f100 0a14 add.w sl, r0, #20 + 801617e: 2300 movs r3, #0 + 8016180: 495a ldr r1, [pc, #360] ; (80162ec <__gethex+0x2d8>) + 8016182: f8cd a004 str.w sl, [sp, #4] + 8016186: 469b mov fp, r3 + 8016188: 45a8 cmp r8, r5 + 801618a: d342 bcc.n 8016212 <__gethex+0x1fe> + 801618c: 9801 ldr r0, [sp, #4] + 801618e: f840 bb04 str.w fp, [r0], #4 + 8016192: eba0 000a sub.w r0, r0, sl + 8016196: 1080 asrs r0, r0, #2 + 8016198: 6120 str r0, [r4, #16] + 801619a: ea4f 1840 mov.w r8, r0, lsl #5 + 801619e: 4658 mov r0, fp + 80161a0: f000 fb2c bl 80167fc <__hi0bits> + 80161a4: 683d ldr r5, [r7, #0] + 80161a6: eba8 0000 sub.w r0, r8, r0 + 80161aa: 42a8 cmp r0, r5 + 80161ac: dd59 ble.n 8016262 <__gethex+0x24e> + 80161ae: eba0 0805 sub.w r8, r0, r5 + 80161b2: 4641 mov r1, r8 + 80161b4: 4620 mov r0, r4 + 80161b6: f000 febb bl 8016f30 <__any_on> + 80161ba: 4683 mov fp, r0 + 80161bc: b1b8 cbz r0, 80161ee <__gethex+0x1da> + 80161be: f108 33ff add.w r3, r8, #4294967295 + 80161c2: 1159 asrs r1, r3, #5 + 80161c4: f003 021f and.w r2, r3, #31 + 80161c8: f85a 1021 ldr.w r1, [sl, r1, lsl #2] + 80161cc: f04f 0b01 mov.w fp, #1 + 80161d0: fa0b f202 lsl.w r2, fp, r2 + 80161d4: 420a tst r2, r1 + 80161d6: d00a beq.n 80161ee <__gethex+0x1da> + 80161d8: 455b cmp r3, fp + 80161da: dd06 ble.n 80161ea <__gethex+0x1d6> + 80161dc: f1a8 0102 sub.w r1, r8, #2 + 80161e0: 4620 mov r0, r4 + 80161e2: f000 fea5 bl 8016f30 <__any_on> + 80161e6: 2800 cmp r0, #0 + 80161e8: d138 bne.n 801625c <__gethex+0x248> + 80161ea: f04f 0b02 mov.w fp, #2 + 80161ee: 4641 mov r1, r8 + 80161f0: 4620 mov r0, r4 + 80161f2: f7ff fea7 bl 8015f44 + 80161f6: 4446 add r6, r8 + 80161f8: 68bb ldr r3, [r7, #8] + 80161fa: 42b3 cmp r3, r6 + 80161fc: da41 bge.n 8016282 <__gethex+0x26e> + 80161fe: 4621 mov r1, r4 + 8016200: 4648 mov r0, r9 + 8016202: f000 fa49 bl 8016698 <_Bfree> + 8016206: 9a0e ldr r2, [sp, #56] ; 0x38 + 8016208: 2300 movs r3, #0 + 801620a: 6013 str r3, [r2, #0] + 801620c: f04f 08a3 mov.w r8, #163 ; 0xa3 + 8016210: e78a b.n 8016128 <__gethex+0x114> + 8016212: f815 2d01 ldrb.w r2, [r5, #-1]! + 8016216: 2a2e cmp r2, #46 ; 0x2e + 8016218: d014 beq.n 8016244 <__gethex+0x230> + 801621a: 2b20 cmp r3, #32 + 801621c: d106 bne.n 801622c <__gethex+0x218> + 801621e: 9b01 ldr r3, [sp, #4] + 8016220: f843 bb04 str.w fp, [r3], #4 + 8016224: f04f 0b00 mov.w fp, #0 + 8016228: 9301 str r3, [sp, #4] + 801622a: 465b mov r3, fp + 801622c: 7828 ldrb r0, [r5, #0] + 801622e: 9303 str r3, [sp, #12] + 8016230: f7ff feda bl 8015fe8 <__hexdig_fun> + 8016234: 9b03 ldr r3, [sp, #12] + 8016236: f000 000f and.w r0, r0, #15 + 801623a: 4098 lsls r0, r3 + 801623c: ea4b 0b00 orr.w fp, fp, r0 + 8016240: 3304 adds r3, #4 + 8016242: e7a1 b.n 8016188 <__gethex+0x174> + 8016244: 45a8 cmp r8, r5 + 8016246: d8e8 bhi.n 801621a <__gethex+0x206> + 8016248: 2201 movs r2, #1 + 801624a: 4628 mov r0, r5 + 801624c: 9303 str r3, [sp, #12] + 801624e: f7fe fe64 bl 8014f1a + 8016252: 4926 ldr r1, [pc, #152] ; (80162ec <__gethex+0x2d8>) + 8016254: 9b03 ldr r3, [sp, #12] + 8016256: 2800 cmp r0, #0 + 8016258: d1df bne.n 801621a <__gethex+0x206> + 801625a: e795 b.n 8016188 <__gethex+0x174> + 801625c: f04f 0b03 mov.w fp, #3 + 8016260: e7c5 b.n 80161ee <__gethex+0x1da> + 8016262: da0b bge.n 801627c <__gethex+0x268> + 8016264: eba5 0800 sub.w r8, r5, r0 + 8016268: 4621 mov r1, r4 + 801626a: 4642 mov r2, r8 + 801626c: 4648 mov r0, r9 + 801626e: f000 fc2d bl 8016acc <__lshift> + 8016272: eba6 0608 sub.w r6, r6, r8 + 8016276: 4604 mov r4, r0 + 8016278: f100 0a14 add.w sl, r0, #20 + 801627c: f04f 0b00 mov.w fp, #0 + 8016280: e7ba b.n 80161f8 <__gethex+0x1e4> + 8016282: 687b ldr r3, [r7, #4] + 8016284: 42b3 cmp r3, r6 + 8016286: dd73 ble.n 8016370 <__gethex+0x35c> + 8016288: 1b9e subs r6, r3, r6 + 801628a: 42b5 cmp r5, r6 + 801628c: dc34 bgt.n 80162f8 <__gethex+0x2e4> + 801628e: 68fb ldr r3, [r7, #12] + 8016290: 2b02 cmp r3, #2 + 8016292: d023 beq.n 80162dc <__gethex+0x2c8> + 8016294: 2b03 cmp r3, #3 + 8016296: d025 beq.n 80162e4 <__gethex+0x2d0> + 8016298: 2b01 cmp r3, #1 + 801629a: d115 bne.n 80162c8 <__gethex+0x2b4> + 801629c: 42b5 cmp r5, r6 + 801629e: d113 bne.n 80162c8 <__gethex+0x2b4> + 80162a0: 2d01 cmp r5, #1 + 80162a2: d10b bne.n 80162bc <__gethex+0x2a8> + 80162a4: 9a02 ldr r2, [sp, #8] + 80162a6: 687b ldr r3, [r7, #4] + 80162a8: 6013 str r3, [r2, #0] + 80162aa: 2301 movs r3, #1 + 80162ac: 6123 str r3, [r4, #16] + 80162ae: f8ca 3000 str.w r3, [sl] + 80162b2: 9b0e ldr r3, [sp, #56] ; 0x38 + 80162b4: f04f 0862 mov.w r8, #98 ; 0x62 + 80162b8: 601c str r4, [r3, #0] + 80162ba: e735 b.n 8016128 <__gethex+0x114> + 80162bc: 1e69 subs r1, r5, #1 + 80162be: 4620 mov r0, r4 + 80162c0: f000 fe36 bl 8016f30 <__any_on> + 80162c4: 2800 cmp r0, #0 + 80162c6: d1ed bne.n 80162a4 <__gethex+0x290> + 80162c8: 4621 mov r1, r4 + 80162ca: 4648 mov r0, r9 + 80162cc: f000 f9e4 bl 8016698 <_Bfree> + 80162d0: 9a0e ldr r2, [sp, #56] ; 0x38 + 80162d2: 2300 movs r3, #0 + 80162d4: 6013 str r3, [r2, #0] + 80162d6: f04f 0850 mov.w r8, #80 ; 0x50 + 80162da: e725 b.n 8016128 <__gethex+0x114> + 80162dc: 9b0f ldr r3, [sp, #60] ; 0x3c + 80162de: 2b00 cmp r3, #0 + 80162e0: d1f2 bne.n 80162c8 <__gethex+0x2b4> + 80162e2: e7df b.n 80162a4 <__gethex+0x290> + 80162e4: 9b0f ldr r3, [sp, #60] ; 0x3c + 80162e6: 2b00 cmp r3, #0 + 80162e8: d1dc bne.n 80162a4 <__gethex+0x290> + 80162ea: e7ed b.n 80162c8 <__gethex+0x2b4> + 80162ec: 0801abec .word 0x0801abec + 80162f0: 0801ae94 .word 0x0801ae94 + 80162f4: 0801aea5 .word 0x0801aea5 + 80162f8: f106 38ff add.w r8, r6, #4294967295 + 80162fc: f1bb 0f00 cmp.w fp, #0 + 8016300: d133 bne.n 801636a <__gethex+0x356> + 8016302: f1b8 0f00 cmp.w r8, #0 + 8016306: d004 beq.n 8016312 <__gethex+0x2fe> + 8016308: 4641 mov r1, r8 + 801630a: 4620 mov r0, r4 + 801630c: f000 fe10 bl 8016f30 <__any_on> + 8016310: 4683 mov fp, r0 + 8016312: ea4f 1268 mov.w r2, r8, asr #5 + 8016316: 2301 movs r3, #1 + 8016318: f85a 2022 ldr.w r2, [sl, r2, lsl #2] + 801631c: f008 081f and.w r8, r8, #31 + 8016320: fa03 f308 lsl.w r3, r3, r8 + 8016324: 4213 tst r3, r2 + 8016326: 4631 mov r1, r6 + 8016328: 4620 mov r0, r4 + 801632a: bf18 it ne + 801632c: f04b 0b02 orrne.w fp, fp, #2 + 8016330: 1bad subs r5, r5, r6 + 8016332: f7ff fe07 bl 8015f44 + 8016336: 687e ldr r6, [r7, #4] + 8016338: f04f 0802 mov.w r8, #2 + 801633c: f1bb 0f00 cmp.w fp, #0 + 8016340: d04a beq.n 80163d8 <__gethex+0x3c4> + 8016342: 68fb ldr r3, [r7, #12] + 8016344: 2b02 cmp r3, #2 + 8016346: d016 beq.n 8016376 <__gethex+0x362> + 8016348: 2b03 cmp r3, #3 + 801634a: d018 beq.n 801637e <__gethex+0x36a> + 801634c: 2b01 cmp r3, #1 + 801634e: d109 bne.n 8016364 <__gethex+0x350> + 8016350: f01b 0f02 tst.w fp, #2 + 8016354: d006 beq.n 8016364 <__gethex+0x350> + 8016356: f8da 3000 ldr.w r3, [sl] + 801635a: ea4b 0b03 orr.w fp, fp, r3 + 801635e: f01b 0f01 tst.w fp, #1 + 8016362: d10f bne.n 8016384 <__gethex+0x370> + 8016364: f048 0810 orr.w r8, r8, #16 + 8016368: e036 b.n 80163d8 <__gethex+0x3c4> + 801636a: f04f 0b01 mov.w fp, #1 + 801636e: e7d0 b.n 8016312 <__gethex+0x2fe> + 8016370: f04f 0801 mov.w r8, #1 + 8016374: e7e2 b.n 801633c <__gethex+0x328> + 8016376: 9b0f ldr r3, [sp, #60] ; 0x3c + 8016378: f1c3 0301 rsb r3, r3, #1 + 801637c: 930f str r3, [sp, #60] ; 0x3c + 801637e: 9b0f ldr r3, [sp, #60] ; 0x3c + 8016380: 2b00 cmp r3, #0 + 8016382: d0ef beq.n 8016364 <__gethex+0x350> + 8016384: f8d4 b010 ldr.w fp, [r4, #16] + 8016388: f104 0214 add.w r2, r4, #20 + 801638c: ea4f 038b mov.w r3, fp, lsl #2 + 8016390: 9301 str r3, [sp, #4] + 8016392: eb02 008b add.w r0, r2, fp, lsl #2 + 8016396: 2300 movs r3, #0 + 8016398: 4694 mov ip, r2 + 801639a: f852 1b04 ldr.w r1, [r2], #4 + 801639e: f1b1 3fff cmp.w r1, #4294967295 + 80163a2: d01e beq.n 80163e2 <__gethex+0x3ce> + 80163a4: 3101 adds r1, #1 + 80163a6: f8cc 1000 str.w r1, [ip] + 80163aa: f1b8 0f02 cmp.w r8, #2 + 80163ae: f104 0214 add.w r2, r4, #20 + 80163b2: d13d bne.n 8016430 <__gethex+0x41c> + 80163b4: 683b ldr r3, [r7, #0] + 80163b6: 3b01 subs r3, #1 + 80163b8: 42ab cmp r3, r5 + 80163ba: d10b bne.n 80163d4 <__gethex+0x3c0> + 80163bc: 1169 asrs r1, r5, #5 + 80163be: 2301 movs r3, #1 + 80163c0: f005 051f and.w r5, r5, #31 + 80163c4: fa03 f505 lsl.w r5, r3, r5 + 80163c8: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 80163cc: 421d tst r5, r3 + 80163ce: bf18 it ne + 80163d0: f04f 0801 movne.w r8, #1 + 80163d4: f048 0820 orr.w r8, r8, #32 + 80163d8: 9b0e ldr r3, [sp, #56] ; 0x38 + 80163da: 601c str r4, [r3, #0] + 80163dc: 9b02 ldr r3, [sp, #8] + 80163de: 601e str r6, [r3, #0] + 80163e0: e6a2 b.n 8016128 <__gethex+0x114> + 80163e2: 4290 cmp r0, r2 + 80163e4: f842 3c04 str.w r3, [r2, #-4] + 80163e8: d8d6 bhi.n 8016398 <__gethex+0x384> + 80163ea: 68a2 ldr r2, [r4, #8] + 80163ec: 4593 cmp fp, r2 + 80163ee: db17 blt.n 8016420 <__gethex+0x40c> + 80163f0: 6861 ldr r1, [r4, #4] + 80163f2: 4648 mov r0, r9 + 80163f4: 3101 adds r1, #1 + 80163f6: f000 f90f bl 8016618 <_Balloc> + 80163fa: 4682 mov sl, r0 + 80163fc: b918 cbnz r0, 8016406 <__gethex+0x3f2> + 80163fe: 4b1b ldr r3, [pc, #108] ; (801646c <__gethex+0x458>) + 8016400: 4602 mov r2, r0 + 8016402: 2184 movs r1, #132 ; 0x84 + 8016404: e6b3 b.n 801616e <__gethex+0x15a> + 8016406: 6922 ldr r2, [r4, #16] + 8016408: 3202 adds r2, #2 + 801640a: f104 010c add.w r1, r4, #12 + 801640e: 0092 lsls r2, r2, #2 + 8016410: 300c adds r0, #12 + 8016412: f7fe fe96 bl 8015142 + 8016416: 4621 mov r1, r4 + 8016418: 4648 mov r0, r9 + 801641a: f000 f93d bl 8016698 <_Bfree> + 801641e: 4654 mov r4, sl + 8016420: 6922 ldr r2, [r4, #16] + 8016422: 1c51 adds r1, r2, #1 + 8016424: eb04 0282 add.w r2, r4, r2, lsl #2 + 8016428: 6121 str r1, [r4, #16] + 801642a: 2101 movs r1, #1 + 801642c: 6151 str r1, [r2, #20] + 801642e: e7bc b.n 80163aa <__gethex+0x396> + 8016430: 6921 ldr r1, [r4, #16] + 8016432: 4559 cmp r1, fp + 8016434: dd0b ble.n 801644e <__gethex+0x43a> + 8016436: 2101 movs r1, #1 + 8016438: 4620 mov r0, r4 + 801643a: f7ff fd83 bl 8015f44 + 801643e: 68bb ldr r3, [r7, #8] + 8016440: 3601 adds r6, #1 + 8016442: 42b3 cmp r3, r6 + 8016444: f6ff aedb blt.w 80161fe <__gethex+0x1ea> + 8016448: f04f 0801 mov.w r8, #1 + 801644c: e7c2 b.n 80163d4 <__gethex+0x3c0> + 801644e: f015 051f ands.w r5, r5, #31 + 8016452: d0f9 beq.n 8016448 <__gethex+0x434> + 8016454: 9b01 ldr r3, [sp, #4] + 8016456: 441a add r2, r3 + 8016458: f1c5 0520 rsb r5, r5, #32 + 801645c: f852 0c04 ldr.w r0, [r2, #-4] + 8016460: f000 f9cc bl 80167fc <__hi0bits> + 8016464: 42a8 cmp r0, r5 + 8016466: dbe6 blt.n 8016436 <__gethex+0x422> + 8016468: e7ee b.n 8016448 <__gethex+0x434> + 801646a: bf00 nop + 801646c: 0801ae94 .word 0x0801ae94 + +08016470 : + 8016470: f1c2 0208 rsb r2, r2, #8 + 8016474: 0092 lsls r2, r2, #2 + 8016476: b570 push {r4, r5, r6, lr} + 8016478: f1c2 0620 rsb r6, r2, #32 + 801647c: 6843 ldr r3, [r0, #4] + 801647e: 6804 ldr r4, [r0, #0] + 8016480: fa03 f506 lsl.w r5, r3, r6 + 8016484: 432c orrs r4, r5 + 8016486: 40d3 lsrs r3, r2 + 8016488: 6004 str r4, [r0, #0] + 801648a: f840 3f04 str.w r3, [r0, #4]! + 801648e: 4288 cmp r0, r1 + 8016490: d3f4 bcc.n 801647c + 8016492: bd70 pop {r4, r5, r6, pc} + +08016494 <__match>: + 8016494: b530 push {r4, r5, lr} + 8016496: 6803 ldr r3, [r0, #0] + 8016498: 3301 adds r3, #1 + 801649a: f811 4b01 ldrb.w r4, [r1], #1 + 801649e: b914 cbnz r4, 80164a6 <__match+0x12> + 80164a0: 6003 str r3, [r0, #0] + 80164a2: 2001 movs r0, #1 + 80164a4: bd30 pop {r4, r5, pc} + 80164a6: f813 2b01 ldrb.w r2, [r3], #1 + 80164aa: f1a2 0541 sub.w r5, r2, #65 ; 0x41 + 80164ae: 2d19 cmp r5, #25 + 80164b0: bf98 it ls + 80164b2: 3220 addls r2, #32 + 80164b4: 42a2 cmp r2, r4 + 80164b6: d0f0 beq.n 801649a <__match+0x6> + 80164b8: 2000 movs r0, #0 + 80164ba: e7f3 b.n 80164a4 <__match+0x10> + +080164bc <__hexnan>: + 80164bc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80164c0: 680b ldr r3, [r1, #0] + 80164c2: 6801 ldr r1, [r0, #0] + 80164c4: 115e asrs r6, r3, #5 + 80164c6: eb02 0686 add.w r6, r2, r6, lsl #2 + 80164ca: f013 031f ands.w r3, r3, #31 + 80164ce: b087 sub sp, #28 + 80164d0: bf18 it ne + 80164d2: 3604 addne r6, #4 + 80164d4: 2500 movs r5, #0 + 80164d6: 1f37 subs r7, r6, #4 + 80164d8: 4682 mov sl, r0 + 80164da: 4690 mov r8, r2 + 80164dc: 9301 str r3, [sp, #4] + 80164de: f846 5c04 str.w r5, [r6, #-4] + 80164e2: 46b9 mov r9, r7 + 80164e4: 463c mov r4, r7 + 80164e6: 9502 str r5, [sp, #8] + 80164e8: 46ab mov fp, r5 + 80164ea: 784a ldrb r2, [r1, #1] + 80164ec: 1c4b adds r3, r1, #1 + 80164ee: 9303 str r3, [sp, #12] + 80164f0: b342 cbz r2, 8016544 <__hexnan+0x88> + 80164f2: 4610 mov r0, r2 + 80164f4: 9105 str r1, [sp, #20] + 80164f6: 9204 str r2, [sp, #16] + 80164f8: f7ff fd76 bl 8015fe8 <__hexdig_fun> + 80164fc: 2800 cmp r0, #0 + 80164fe: d14f bne.n 80165a0 <__hexnan+0xe4> + 8016500: 9a04 ldr r2, [sp, #16] + 8016502: 9905 ldr r1, [sp, #20] + 8016504: 2a20 cmp r2, #32 + 8016506: d818 bhi.n 801653a <__hexnan+0x7e> + 8016508: 9b02 ldr r3, [sp, #8] + 801650a: 459b cmp fp, r3 + 801650c: dd13 ble.n 8016536 <__hexnan+0x7a> + 801650e: 454c cmp r4, r9 + 8016510: d206 bcs.n 8016520 <__hexnan+0x64> + 8016512: 2d07 cmp r5, #7 + 8016514: dc04 bgt.n 8016520 <__hexnan+0x64> + 8016516: 462a mov r2, r5 + 8016518: 4649 mov r1, r9 + 801651a: 4620 mov r0, r4 + 801651c: f7ff ffa8 bl 8016470 + 8016520: 4544 cmp r4, r8 + 8016522: d950 bls.n 80165c6 <__hexnan+0x10a> + 8016524: 2300 movs r3, #0 + 8016526: f1a4 0904 sub.w r9, r4, #4 + 801652a: f844 3c04 str.w r3, [r4, #-4] + 801652e: f8cd b008 str.w fp, [sp, #8] + 8016532: 464c mov r4, r9 + 8016534: 461d mov r5, r3 + 8016536: 9903 ldr r1, [sp, #12] + 8016538: e7d7 b.n 80164ea <__hexnan+0x2e> + 801653a: 2a29 cmp r2, #41 ; 0x29 + 801653c: d155 bne.n 80165ea <__hexnan+0x12e> + 801653e: 3102 adds r1, #2 + 8016540: f8ca 1000 str.w r1, [sl] + 8016544: f1bb 0f00 cmp.w fp, #0 + 8016548: d04f beq.n 80165ea <__hexnan+0x12e> + 801654a: 454c cmp r4, r9 + 801654c: d206 bcs.n 801655c <__hexnan+0xa0> + 801654e: 2d07 cmp r5, #7 + 8016550: dc04 bgt.n 801655c <__hexnan+0xa0> + 8016552: 462a mov r2, r5 + 8016554: 4649 mov r1, r9 + 8016556: 4620 mov r0, r4 + 8016558: f7ff ff8a bl 8016470 + 801655c: 4544 cmp r4, r8 + 801655e: d934 bls.n 80165ca <__hexnan+0x10e> + 8016560: f1a8 0204 sub.w r2, r8, #4 + 8016564: 4623 mov r3, r4 + 8016566: f853 1b04 ldr.w r1, [r3], #4 + 801656a: f842 1f04 str.w r1, [r2, #4]! + 801656e: 429f cmp r7, r3 + 8016570: d2f9 bcs.n 8016566 <__hexnan+0xaa> + 8016572: 1b3b subs r3, r7, r4 + 8016574: f023 0303 bic.w r3, r3, #3 + 8016578: 3304 adds r3, #4 + 801657a: 3e03 subs r6, #3 + 801657c: 3401 adds r4, #1 + 801657e: 42a6 cmp r6, r4 + 8016580: bf38 it cc + 8016582: 2304 movcc r3, #4 + 8016584: 4443 add r3, r8 + 8016586: 2200 movs r2, #0 + 8016588: f843 2b04 str.w r2, [r3], #4 + 801658c: 429f cmp r7, r3 + 801658e: d2fb bcs.n 8016588 <__hexnan+0xcc> + 8016590: 683b ldr r3, [r7, #0] + 8016592: b91b cbnz r3, 801659c <__hexnan+0xe0> + 8016594: 4547 cmp r7, r8 + 8016596: d126 bne.n 80165e6 <__hexnan+0x12a> + 8016598: 2301 movs r3, #1 + 801659a: 603b str r3, [r7, #0] + 801659c: 2005 movs r0, #5 + 801659e: e025 b.n 80165ec <__hexnan+0x130> + 80165a0: 3501 adds r5, #1 + 80165a2: 2d08 cmp r5, #8 + 80165a4: f10b 0b01 add.w fp, fp, #1 + 80165a8: dd06 ble.n 80165b8 <__hexnan+0xfc> + 80165aa: 4544 cmp r4, r8 + 80165ac: d9c3 bls.n 8016536 <__hexnan+0x7a> + 80165ae: 2300 movs r3, #0 + 80165b0: f844 3c04 str.w r3, [r4, #-4] + 80165b4: 2501 movs r5, #1 + 80165b6: 3c04 subs r4, #4 + 80165b8: 6822 ldr r2, [r4, #0] + 80165ba: f000 000f and.w r0, r0, #15 + 80165be: ea40 1002 orr.w r0, r0, r2, lsl #4 + 80165c2: 6020 str r0, [r4, #0] + 80165c4: e7b7 b.n 8016536 <__hexnan+0x7a> + 80165c6: 2508 movs r5, #8 + 80165c8: e7b5 b.n 8016536 <__hexnan+0x7a> + 80165ca: 9b01 ldr r3, [sp, #4] + 80165cc: 2b00 cmp r3, #0 + 80165ce: d0df beq.n 8016590 <__hexnan+0xd4> + 80165d0: f1c3 0320 rsb r3, r3, #32 + 80165d4: f04f 32ff mov.w r2, #4294967295 + 80165d8: 40da lsrs r2, r3 + 80165da: f856 3c04 ldr.w r3, [r6, #-4] + 80165de: 4013 ands r3, r2 + 80165e0: f846 3c04 str.w r3, [r6, #-4] + 80165e4: e7d4 b.n 8016590 <__hexnan+0xd4> + 80165e6: 3f04 subs r7, #4 + 80165e8: e7d2 b.n 8016590 <__hexnan+0xd4> + 80165ea: 2004 movs r0, #4 + 80165ec: b007 add sp, #28 + 80165ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +080165f2 <__ascii_mbtowc>: + 80165f2: b082 sub sp, #8 + 80165f4: b901 cbnz r1, 80165f8 <__ascii_mbtowc+0x6> + 80165f6: a901 add r1, sp, #4 + 80165f8: b142 cbz r2, 801660c <__ascii_mbtowc+0x1a> + 80165fa: b14b cbz r3, 8016610 <__ascii_mbtowc+0x1e> + 80165fc: 7813 ldrb r3, [r2, #0] + 80165fe: 600b str r3, [r1, #0] + 8016600: 7812 ldrb r2, [r2, #0] + 8016602: 1e10 subs r0, r2, #0 + 8016604: bf18 it ne + 8016606: 2001 movne r0, #1 + 8016608: b002 add sp, #8 + 801660a: 4770 bx lr + 801660c: 4610 mov r0, r2 + 801660e: e7fb b.n 8016608 <__ascii_mbtowc+0x16> + 8016610: f06f 0001 mvn.w r0, #1 + 8016614: e7f8 b.n 8016608 <__ascii_mbtowc+0x16> ... -08014168 <_Balloc>: - 8014168: b570 push {r4, r5, r6, lr} - 801416a: 69c6 ldr r6, [r0, #28] - 801416c: 4604 mov r4, r0 - 801416e: 460d mov r5, r1 - 8014170: b976 cbnz r6, 8014190 <_Balloc+0x28> - 8014172: 2010 movs r0, #16 - 8014174: f7fc fcde bl 8010b34 - 8014178: 4602 mov r2, r0 - 801417a: 61e0 str r0, [r4, #28] - 801417c: b920 cbnz r0, 8014188 <_Balloc+0x20> - 801417e: 4b18 ldr r3, [pc, #96] ; (80141e0 <_Balloc+0x78>) - 8014180: 4818 ldr r0, [pc, #96] ; (80141e4 <_Balloc+0x7c>) - 8014182: 216b movs r1, #107 ; 0x6b - 8014184: f7fe fda2 bl 8012ccc <__assert_func> - 8014188: e9c0 6601 strd r6, r6, [r0, #4] - 801418c: 6006 str r6, [r0, #0] - 801418e: 60c6 str r6, [r0, #12] - 8014190: 69e6 ldr r6, [r4, #28] - 8014192: 68f3 ldr r3, [r6, #12] - 8014194: b183 cbz r3, 80141b8 <_Balloc+0x50> - 8014196: 69e3 ldr r3, [r4, #28] - 8014198: 68db ldr r3, [r3, #12] - 801419a: f853 0025 ldr.w r0, [r3, r5, lsl #2] - 801419e: b9b8 cbnz r0, 80141d0 <_Balloc+0x68> - 80141a0: 2101 movs r1, #1 - 80141a2: fa01 f605 lsl.w r6, r1, r5 - 80141a6: 1d72 adds r2, r6, #5 - 80141a8: 0092 lsls r2, r2, #2 - 80141aa: 4620 mov r0, r4 - 80141ac: f000 fecf bl 8014f4e <_calloc_r> - 80141b0: b160 cbz r0, 80141cc <_Balloc+0x64> - 80141b2: e9c0 5601 strd r5, r6, [r0, #4] - 80141b6: e00e b.n 80141d6 <_Balloc+0x6e> - 80141b8: 2221 movs r2, #33 ; 0x21 - 80141ba: 2104 movs r1, #4 - 80141bc: 4620 mov r0, r4 - 80141be: f000 fec6 bl 8014f4e <_calloc_r> - 80141c2: 69e3 ldr r3, [r4, #28] - 80141c4: 60f0 str r0, [r6, #12] - 80141c6: 68db ldr r3, [r3, #12] - 80141c8: 2b00 cmp r3, #0 - 80141ca: d1e4 bne.n 8014196 <_Balloc+0x2e> - 80141cc: 2000 movs r0, #0 - 80141ce: bd70 pop {r4, r5, r6, pc} - 80141d0: 6802 ldr r2, [r0, #0] - 80141d2: f843 2025 str.w r2, [r3, r5, lsl #2] - 80141d6: 2300 movs r3, #0 - 80141d8: e9c0 3303 strd r3, r3, [r0, #12] - 80141dc: e7f7 b.n 80141ce <_Balloc+0x66> - 80141de: bf00 nop - 80141e0: 080188a2 .word 0x080188a2 - 80141e4: 08018a2d .word 0x08018a2d - -080141e8 <_Bfree>: - 80141e8: b570 push {r4, r5, r6, lr} - 80141ea: 69c6 ldr r6, [r0, #28] - 80141ec: 4605 mov r5, r0 - 80141ee: 460c mov r4, r1 - 80141f0: b976 cbnz r6, 8014210 <_Bfree+0x28> - 80141f2: 2010 movs r0, #16 - 80141f4: f7fc fc9e bl 8010b34 - 80141f8: 4602 mov r2, r0 - 80141fa: 61e8 str r0, [r5, #28] - 80141fc: b920 cbnz r0, 8014208 <_Bfree+0x20> - 80141fe: 4b09 ldr r3, [pc, #36] ; (8014224 <_Bfree+0x3c>) - 8014200: 4809 ldr r0, [pc, #36] ; (8014228 <_Bfree+0x40>) - 8014202: 218f movs r1, #143 ; 0x8f - 8014204: f7fe fd62 bl 8012ccc <__assert_func> - 8014208: e9c0 6601 strd r6, r6, [r0, #4] - 801420c: 6006 str r6, [r0, #0] - 801420e: 60c6 str r6, [r0, #12] - 8014210: b13c cbz r4, 8014222 <_Bfree+0x3a> - 8014212: 69eb ldr r3, [r5, #28] - 8014214: 6862 ldr r2, [r4, #4] - 8014216: 68db ldr r3, [r3, #12] - 8014218: f853 1022 ldr.w r1, [r3, r2, lsl #2] - 801421c: 6021 str r1, [r4, #0] - 801421e: f843 4022 str.w r4, [r3, r2, lsl #2] - 8014222: bd70 pop {r4, r5, r6, pc} - 8014224: 080188a2 .word 0x080188a2 - 8014228: 08018a2d .word 0x08018a2d - -0801422c <__multadd>: - 801422c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8014230: 690d ldr r5, [r1, #16] - 8014232: 4607 mov r7, r0 - 8014234: 460c mov r4, r1 - 8014236: 461e mov r6, r3 - 8014238: f101 0c14 add.w ip, r1, #20 - 801423c: 2000 movs r0, #0 - 801423e: f8dc 3000 ldr.w r3, [ip] - 8014242: b299 uxth r1, r3 - 8014244: fb02 6101 mla r1, r2, r1, r6 - 8014248: 0c1e lsrs r6, r3, #16 - 801424a: 0c0b lsrs r3, r1, #16 - 801424c: fb02 3306 mla r3, r2, r6, r3 - 8014250: b289 uxth r1, r1 - 8014252: 3001 adds r0, #1 - 8014254: eb01 4103 add.w r1, r1, r3, lsl #16 - 8014258: 4285 cmp r5, r0 - 801425a: f84c 1b04 str.w r1, [ip], #4 - 801425e: ea4f 4613 mov.w r6, r3, lsr #16 - 8014262: dcec bgt.n 801423e <__multadd+0x12> - 8014264: b30e cbz r6, 80142aa <__multadd+0x7e> - 8014266: 68a3 ldr r3, [r4, #8] - 8014268: 42ab cmp r3, r5 - 801426a: dc19 bgt.n 80142a0 <__multadd+0x74> - 801426c: 6861 ldr r1, [r4, #4] - 801426e: 4638 mov r0, r7 - 8014270: 3101 adds r1, #1 - 8014272: f7ff ff79 bl 8014168 <_Balloc> - 8014276: 4680 mov r8, r0 - 8014278: b928 cbnz r0, 8014286 <__multadd+0x5a> - 801427a: 4602 mov r2, r0 - 801427c: 4b0c ldr r3, [pc, #48] ; (80142b0 <__multadd+0x84>) - 801427e: 480d ldr r0, [pc, #52] ; (80142b4 <__multadd+0x88>) - 8014280: 21ba movs r1, #186 ; 0xba - 8014282: f7fe fd23 bl 8012ccc <__assert_func> - 8014286: 6922 ldr r2, [r4, #16] - 8014288: 3202 adds r2, #2 - 801428a: f104 010c add.w r1, r4, #12 - 801428e: 0092 lsls r2, r2, #2 - 8014290: 300c adds r0, #12 - 8014292: f7fe fcfe bl 8012c92 - 8014296: 4621 mov r1, r4 - 8014298: 4638 mov r0, r7 - 801429a: f7ff ffa5 bl 80141e8 <_Bfree> - 801429e: 4644 mov r4, r8 - 80142a0: eb04 0385 add.w r3, r4, r5, lsl #2 - 80142a4: 3501 adds r5, #1 - 80142a6: 615e str r6, [r3, #20] - 80142a8: 6125 str r5, [r4, #16] - 80142aa: 4620 mov r0, r4 - 80142ac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 80142b0: 080189bc .word 0x080189bc - 80142b4: 08018a2d .word 0x08018a2d - -080142b8 <__s2b>: - 80142b8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 80142bc: 460c mov r4, r1 - 80142be: 4615 mov r5, r2 - 80142c0: 461f mov r7, r3 - 80142c2: 2209 movs r2, #9 - 80142c4: 3308 adds r3, #8 - 80142c6: 4606 mov r6, r0 - 80142c8: fb93 f3f2 sdiv r3, r3, r2 - 80142cc: 2100 movs r1, #0 - 80142ce: 2201 movs r2, #1 - 80142d0: 429a cmp r2, r3 - 80142d2: db09 blt.n 80142e8 <__s2b+0x30> - 80142d4: 4630 mov r0, r6 - 80142d6: f7ff ff47 bl 8014168 <_Balloc> - 80142da: b940 cbnz r0, 80142ee <__s2b+0x36> - 80142dc: 4602 mov r2, r0 - 80142de: 4b19 ldr r3, [pc, #100] ; (8014344 <__s2b+0x8c>) - 80142e0: 4819 ldr r0, [pc, #100] ; (8014348 <__s2b+0x90>) - 80142e2: 21d3 movs r1, #211 ; 0xd3 - 80142e4: f7fe fcf2 bl 8012ccc <__assert_func> - 80142e8: 0052 lsls r2, r2, #1 - 80142ea: 3101 adds r1, #1 - 80142ec: e7f0 b.n 80142d0 <__s2b+0x18> - 80142ee: 9b08 ldr r3, [sp, #32] - 80142f0: 6143 str r3, [r0, #20] - 80142f2: 2d09 cmp r5, #9 - 80142f4: f04f 0301 mov.w r3, #1 - 80142f8: 6103 str r3, [r0, #16] - 80142fa: dd16 ble.n 801432a <__s2b+0x72> - 80142fc: f104 0909 add.w r9, r4, #9 - 8014300: 46c8 mov r8, r9 - 8014302: 442c add r4, r5 - 8014304: f818 3b01 ldrb.w r3, [r8], #1 - 8014308: 4601 mov r1, r0 - 801430a: 3b30 subs r3, #48 ; 0x30 - 801430c: 220a movs r2, #10 - 801430e: 4630 mov r0, r6 - 8014310: f7ff ff8c bl 801422c <__multadd> - 8014314: 45a0 cmp r8, r4 - 8014316: d1f5 bne.n 8014304 <__s2b+0x4c> - 8014318: f1a5 0408 sub.w r4, r5, #8 - 801431c: 444c add r4, r9 - 801431e: 1b2d subs r5, r5, r4 - 8014320: 1963 adds r3, r4, r5 - 8014322: 42bb cmp r3, r7 - 8014324: db04 blt.n 8014330 <__s2b+0x78> - 8014326: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 801432a: 340a adds r4, #10 - 801432c: 2509 movs r5, #9 - 801432e: e7f6 b.n 801431e <__s2b+0x66> - 8014330: f814 3b01 ldrb.w r3, [r4], #1 - 8014334: 4601 mov r1, r0 - 8014336: 3b30 subs r3, #48 ; 0x30 - 8014338: 220a movs r2, #10 - 801433a: 4630 mov r0, r6 - 801433c: f7ff ff76 bl 801422c <__multadd> - 8014340: e7ee b.n 8014320 <__s2b+0x68> - 8014342: bf00 nop - 8014344: 080189bc .word 0x080189bc - 8014348: 08018a2d .word 0x08018a2d - -0801434c <__hi0bits>: - 801434c: 0c03 lsrs r3, r0, #16 - 801434e: 041b lsls r3, r3, #16 - 8014350: b9d3 cbnz r3, 8014388 <__hi0bits+0x3c> - 8014352: 0400 lsls r0, r0, #16 - 8014354: 2310 movs r3, #16 - 8014356: f010 4f7f tst.w r0, #4278190080 ; 0xff000000 - 801435a: bf04 itt eq - 801435c: 0200 lsleq r0, r0, #8 - 801435e: 3308 addeq r3, #8 - 8014360: f010 4f70 tst.w r0, #4026531840 ; 0xf0000000 - 8014364: bf04 itt eq - 8014366: 0100 lsleq r0, r0, #4 - 8014368: 3304 addeq r3, #4 - 801436a: f010 4f40 tst.w r0, #3221225472 ; 0xc0000000 - 801436e: bf04 itt eq - 8014370: 0080 lsleq r0, r0, #2 - 8014372: 3302 addeq r3, #2 - 8014374: 2800 cmp r0, #0 - 8014376: db05 blt.n 8014384 <__hi0bits+0x38> - 8014378: f010 4f80 tst.w r0, #1073741824 ; 0x40000000 - 801437c: f103 0301 add.w r3, r3, #1 - 8014380: bf08 it eq - 8014382: 2320 moveq r3, #32 - 8014384: 4618 mov r0, r3 - 8014386: 4770 bx lr - 8014388: 2300 movs r3, #0 - 801438a: e7e4 b.n 8014356 <__hi0bits+0xa> - -0801438c <__lo0bits>: - 801438c: 6803 ldr r3, [r0, #0] - 801438e: f013 0207 ands.w r2, r3, #7 - 8014392: d00c beq.n 80143ae <__lo0bits+0x22> - 8014394: 07d9 lsls r1, r3, #31 - 8014396: d422 bmi.n 80143de <__lo0bits+0x52> - 8014398: 079a lsls r2, r3, #30 - 801439a: bf49 itett mi - 801439c: 085b lsrmi r3, r3, #1 - 801439e: 089b lsrpl r3, r3, #2 - 80143a0: 6003 strmi r3, [r0, #0] - 80143a2: 2201 movmi r2, #1 - 80143a4: bf5c itt pl - 80143a6: 6003 strpl r3, [r0, #0] - 80143a8: 2202 movpl r2, #2 - 80143aa: 4610 mov r0, r2 - 80143ac: 4770 bx lr - 80143ae: b299 uxth r1, r3 - 80143b0: b909 cbnz r1, 80143b6 <__lo0bits+0x2a> - 80143b2: 0c1b lsrs r3, r3, #16 - 80143b4: 2210 movs r2, #16 - 80143b6: b2d9 uxtb r1, r3 - 80143b8: b909 cbnz r1, 80143be <__lo0bits+0x32> - 80143ba: 3208 adds r2, #8 - 80143bc: 0a1b lsrs r3, r3, #8 - 80143be: 0719 lsls r1, r3, #28 - 80143c0: bf04 itt eq - 80143c2: 091b lsreq r3, r3, #4 - 80143c4: 3204 addeq r2, #4 - 80143c6: 0799 lsls r1, r3, #30 - 80143c8: bf04 itt eq - 80143ca: 089b lsreq r3, r3, #2 - 80143cc: 3202 addeq r2, #2 - 80143ce: 07d9 lsls r1, r3, #31 - 80143d0: d403 bmi.n 80143da <__lo0bits+0x4e> - 80143d2: 085b lsrs r3, r3, #1 - 80143d4: f102 0201 add.w r2, r2, #1 - 80143d8: d003 beq.n 80143e2 <__lo0bits+0x56> - 80143da: 6003 str r3, [r0, #0] - 80143dc: e7e5 b.n 80143aa <__lo0bits+0x1e> - 80143de: 2200 movs r2, #0 - 80143e0: e7e3 b.n 80143aa <__lo0bits+0x1e> - 80143e2: 2220 movs r2, #32 - 80143e4: e7e1 b.n 80143aa <__lo0bits+0x1e> +08016618 <_Balloc>: + 8016618: b570 push {r4, r5, r6, lr} + 801661a: 69c6 ldr r6, [r0, #28] + 801661c: 4604 mov r4, r0 + 801661e: 460d mov r5, r1 + 8016620: b976 cbnz r6, 8016640 <_Balloc+0x28> + 8016622: 2010 movs r0, #16 + 8016624: f7fc fcde bl 8012fe4 + 8016628: 4602 mov r2, r0 + 801662a: 61e0 str r0, [r4, #28] + 801662c: b920 cbnz r0, 8016638 <_Balloc+0x20> + 801662e: 4b18 ldr r3, [pc, #96] ; (8016690 <_Balloc+0x78>) + 8016630: 4818 ldr r0, [pc, #96] ; (8016694 <_Balloc+0x7c>) + 8016632: 216b movs r1, #107 ; 0x6b + 8016634: f7fe fda2 bl 801517c <__assert_func> + 8016638: e9c0 6601 strd r6, r6, [r0, #4] + 801663c: 6006 str r6, [r0, #0] + 801663e: 60c6 str r6, [r0, #12] + 8016640: 69e6 ldr r6, [r4, #28] + 8016642: 68f3 ldr r3, [r6, #12] + 8016644: b183 cbz r3, 8016668 <_Balloc+0x50> + 8016646: 69e3 ldr r3, [r4, #28] + 8016648: 68db ldr r3, [r3, #12] + 801664a: f853 0025 ldr.w r0, [r3, r5, lsl #2] + 801664e: b9b8 cbnz r0, 8016680 <_Balloc+0x68> + 8016650: 2101 movs r1, #1 + 8016652: fa01 f605 lsl.w r6, r1, r5 + 8016656: 1d72 adds r2, r6, #5 + 8016658: 0092 lsls r2, r2, #2 + 801665a: 4620 mov r0, r4 + 801665c: f000 fecf bl 80173fe <_calloc_r> + 8016660: b160 cbz r0, 801667c <_Balloc+0x64> + 8016662: e9c0 5601 strd r5, r6, [r0, #4] + 8016666: e00e b.n 8016686 <_Balloc+0x6e> + 8016668: 2221 movs r2, #33 ; 0x21 + 801666a: 2104 movs r1, #4 + 801666c: 4620 mov r0, r4 + 801666e: f000 fec6 bl 80173fe <_calloc_r> + 8016672: 69e3 ldr r3, [r4, #28] + 8016674: 60f0 str r0, [r6, #12] + 8016676: 68db ldr r3, [r3, #12] + 8016678: 2b00 cmp r3, #0 + 801667a: d1e4 bne.n 8016646 <_Balloc+0x2e> + 801667c: 2000 movs r0, #0 + 801667e: bd70 pop {r4, r5, r6, pc} + 8016680: 6802 ldr r2, [r0, #0] + 8016682: f843 2025 str.w r2, [r3, r5, lsl #2] + 8016686: 2300 movs r3, #0 + 8016688: e9c0 3303 strd r3, r3, [r0, #12] + 801668c: e7f7 b.n 801667e <_Balloc+0x66> + 801668e: bf00 nop + 8016690: 0801ad7a .word 0x0801ad7a + 8016694: 0801af05 .word 0x0801af05 + +08016698 <_Bfree>: + 8016698: b570 push {r4, r5, r6, lr} + 801669a: 69c6 ldr r6, [r0, #28] + 801669c: 4605 mov r5, r0 + 801669e: 460c mov r4, r1 + 80166a0: b976 cbnz r6, 80166c0 <_Bfree+0x28> + 80166a2: 2010 movs r0, #16 + 80166a4: f7fc fc9e bl 8012fe4 + 80166a8: 4602 mov r2, r0 + 80166aa: 61e8 str r0, [r5, #28] + 80166ac: b920 cbnz r0, 80166b8 <_Bfree+0x20> + 80166ae: 4b09 ldr r3, [pc, #36] ; (80166d4 <_Bfree+0x3c>) + 80166b0: 4809 ldr r0, [pc, #36] ; (80166d8 <_Bfree+0x40>) + 80166b2: 218f movs r1, #143 ; 0x8f + 80166b4: f7fe fd62 bl 801517c <__assert_func> + 80166b8: e9c0 6601 strd r6, r6, [r0, #4] + 80166bc: 6006 str r6, [r0, #0] + 80166be: 60c6 str r6, [r0, #12] + 80166c0: b13c cbz r4, 80166d2 <_Bfree+0x3a> + 80166c2: 69eb ldr r3, [r5, #28] + 80166c4: 6862 ldr r2, [r4, #4] + 80166c6: 68db ldr r3, [r3, #12] + 80166c8: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 80166cc: 6021 str r1, [r4, #0] + 80166ce: f843 4022 str.w r4, [r3, r2, lsl #2] + 80166d2: bd70 pop {r4, r5, r6, pc} + 80166d4: 0801ad7a .word 0x0801ad7a + 80166d8: 0801af05 .word 0x0801af05 + +080166dc <__multadd>: + 80166dc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80166e0: 690d ldr r5, [r1, #16] + 80166e2: 4607 mov r7, r0 + 80166e4: 460c mov r4, r1 + 80166e6: 461e mov r6, r3 + 80166e8: f101 0c14 add.w ip, r1, #20 + 80166ec: 2000 movs r0, #0 + 80166ee: f8dc 3000 ldr.w r3, [ip] + 80166f2: b299 uxth r1, r3 + 80166f4: fb02 6101 mla r1, r2, r1, r6 + 80166f8: 0c1e lsrs r6, r3, #16 + 80166fa: 0c0b lsrs r3, r1, #16 + 80166fc: fb02 3306 mla r3, r2, r6, r3 + 8016700: b289 uxth r1, r1 + 8016702: 3001 adds r0, #1 + 8016704: eb01 4103 add.w r1, r1, r3, lsl #16 + 8016708: 4285 cmp r5, r0 + 801670a: f84c 1b04 str.w r1, [ip], #4 + 801670e: ea4f 4613 mov.w r6, r3, lsr #16 + 8016712: dcec bgt.n 80166ee <__multadd+0x12> + 8016714: b30e cbz r6, 801675a <__multadd+0x7e> + 8016716: 68a3 ldr r3, [r4, #8] + 8016718: 42ab cmp r3, r5 + 801671a: dc19 bgt.n 8016750 <__multadd+0x74> + 801671c: 6861 ldr r1, [r4, #4] + 801671e: 4638 mov r0, r7 + 8016720: 3101 adds r1, #1 + 8016722: f7ff ff79 bl 8016618 <_Balloc> + 8016726: 4680 mov r8, r0 + 8016728: b928 cbnz r0, 8016736 <__multadd+0x5a> + 801672a: 4602 mov r2, r0 + 801672c: 4b0c ldr r3, [pc, #48] ; (8016760 <__multadd+0x84>) + 801672e: 480d ldr r0, [pc, #52] ; (8016764 <__multadd+0x88>) + 8016730: 21ba movs r1, #186 ; 0xba + 8016732: f7fe fd23 bl 801517c <__assert_func> + 8016736: 6922 ldr r2, [r4, #16] + 8016738: 3202 adds r2, #2 + 801673a: f104 010c add.w r1, r4, #12 + 801673e: 0092 lsls r2, r2, #2 + 8016740: 300c adds r0, #12 + 8016742: f7fe fcfe bl 8015142 + 8016746: 4621 mov r1, r4 + 8016748: 4638 mov r0, r7 + 801674a: f7ff ffa5 bl 8016698 <_Bfree> + 801674e: 4644 mov r4, r8 + 8016750: eb04 0385 add.w r3, r4, r5, lsl #2 + 8016754: 3501 adds r5, #1 + 8016756: 615e str r6, [r3, #20] + 8016758: 6125 str r5, [r4, #16] + 801675a: 4620 mov r0, r4 + 801675c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8016760: 0801ae94 .word 0x0801ae94 + 8016764: 0801af05 .word 0x0801af05 + +08016768 <__s2b>: + 8016768: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 801676c: 460c mov r4, r1 + 801676e: 4615 mov r5, r2 + 8016770: 461f mov r7, r3 + 8016772: 2209 movs r2, #9 + 8016774: 3308 adds r3, #8 + 8016776: 4606 mov r6, r0 + 8016778: fb93 f3f2 sdiv r3, r3, r2 + 801677c: 2100 movs r1, #0 + 801677e: 2201 movs r2, #1 + 8016780: 429a cmp r2, r3 + 8016782: db09 blt.n 8016798 <__s2b+0x30> + 8016784: 4630 mov r0, r6 + 8016786: f7ff ff47 bl 8016618 <_Balloc> + 801678a: b940 cbnz r0, 801679e <__s2b+0x36> + 801678c: 4602 mov r2, r0 + 801678e: 4b19 ldr r3, [pc, #100] ; (80167f4 <__s2b+0x8c>) + 8016790: 4819 ldr r0, [pc, #100] ; (80167f8 <__s2b+0x90>) + 8016792: 21d3 movs r1, #211 ; 0xd3 + 8016794: f7fe fcf2 bl 801517c <__assert_func> + 8016798: 0052 lsls r2, r2, #1 + 801679a: 3101 adds r1, #1 + 801679c: e7f0 b.n 8016780 <__s2b+0x18> + 801679e: 9b08 ldr r3, [sp, #32] + 80167a0: 6143 str r3, [r0, #20] + 80167a2: 2d09 cmp r5, #9 + 80167a4: f04f 0301 mov.w r3, #1 + 80167a8: 6103 str r3, [r0, #16] + 80167aa: dd16 ble.n 80167da <__s2b+0x72> + 80167ac: f104 0909 add.w r9, r4, #9 + 80167b0: 46c8 mov r8, r9 + 80167b2: 442c add r4, r5 + 80167b4: f818 3b01 ldrb.w r3, [r8], #1 + 80167b8: 4601 mov r1, r0 + 80167ba: 3b30 subs r3, #48 ; 0x30 + 80167bc: 220a movs r2, #10 + 80167be: 4630 mov r0, r6 + 80167c0: f7ff ff8c bl 80166dc <__multadd> + 80167c4: 45a0 cmp r8, r4 + 80167c6: d1f5 bne.n 80167b4 <__s2b+0x4c> + 80167c8: f1a5 0408 sub.w r4, r5, #8 + 80167cc: 444c add r4, r9 + 80167ce: 1b2d subs r5, r5, r4 + 80167d0: 1963 adds r3, r4, r5 + 80167d2: 42bb cmp r3, r7 + 80167d4: db04 blt.n 80167e0 <__s2b+0x78> + 80167d6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 80167da: 340a adds r4, #10 + 80167dc: 2509 movs r5, #9 + 80167de: e7f6 b.n 80167ce <__s2b+0x66> + 80167e0: f814 3b01 ldrb.w r3, [r4], #1 + 80167e4: 4601 mov r1, r0 + 80167e6: 3b30 subs r3, #48 ; 0x30 + 80167e8: 220a movs r2, #10 + 80167ea: 4630 mov r0, r6 + 80167ec: f7ff ff76 bl 80166dc <__multadd> + 80167f0: e7ee b.n 80167d0 <__s2b+0x68> + 80167f2: bf00 nop + 80167f4: 0801ae94 .word 0x0801ae94 + 80167f8: 0801af05 .word 0x0801af05 + +080167fc <__hi0bits>: + 80167fc: 0c03 lsrs r3, r0, #16 + 80167fe: 041b lsls r3, r3, #16 + 8016800: b9d3 cbnz r3, 8016838 <__hi0bits+0x3c> + 8016802: 0400 lsls r0, r0, #16 + 8016804: 2310 movs r3, #16 + 8016806: f010 4f7f tst.w r0, #4278190080 ; 0xff000000 + 801680a: bf04 itt eq + 801680c: 0200 lsleq r0, r0, #8 + 801680e: 3308 addeq r3, #8 + 8016810: f010 4f70 tst.w r0, #4026531840 ; 0xf0000000 + 8016814: bf04 itt eq + 8016816: 0100 lsleq r0, r0, #4 + 8016818: 3304 addeq r3, #4 + 801681a: f010 4f40 tst.w r0, #3221225472 ; 0xc0000000 + 801681e: bf04 itt eq + 8016820: 0080 lsleq r0, r0, #2 + 8016822: 3302 addeq r3, #2 + 8016824: 2800 cmp r0, #0 + 8016826: db05 blt.n 8016834 <__hi0bits+0x38> + 8016828: f010 4f80 tst.w r0, #1073741824 ; 0x40000000 + 801682c: f103 0301 add.w r3, r3, #1 + 8016830: bf08 it eq + 8016832: 2320 moveq r3, #32 + 8016834: 4618 mov r0, r3 + 8016836: 4770 bx lr + 8016838: 2300 movs r3, #0 + 801683a: e7e4 b.n 8016806 <__hi0bits+0xa> + +0801683c <__lo0bits>: + 801683c: 6803 ldr r3, [r0, #0] + 801683e: f013 0207 ands.w r2, r3, #7 + 8016842: d00c beq.n 801685e <__lo0bits+0x22> + 8016844: 07d9 lsls r1, r3, #31 + 8016846: d422 bmi.n 801688e <__lo0bits+0x52> + 8016848: 079a lsls r2, r3, #30 + 801684a: bf49 itett mi + 801684c: 085b lsrmi r3, r3, #1 + 801684e: 089b lsrpl r3, r3, #2 + 8016850: 6003 strmi r3, [r0, #0] + 8016852: 2201 movmi r2, #1 + 8016854: bf5c itt pl + 8016856: 6003 strpl r3, [r0, #0] + 8016858: 2202 movpl r2, #2 + 801685a: 4610 mov r0, r2 + 801685c: 4770 bx lr + 801685e: b299 uxth r1, r3 + 8016860: b909 cbnz r1, 8016866 <__lo0bits+0x2a> + 8016862: 0c1b lsrs r3, r3, #16 + 8016864: 2210 movs r2, #16 + 8016866: b2d9 uxtb r1, r3 + 8016868: b909 cbnz r1, 801686e <__lo0bits+0x32> + 801686a: 3208 adds r2, #8 + 801686c: 0a1b lsrs r3, r3, #8 + 801686e: 0719 lsls r1, r3, #28 + 8016870: bf04 itt eq + 8016872: 091b lsreq r3, r3, #4 + 8016874: 3204 addeq r2, #4 + 8016876: 0799 lsls r1, r3, #30 + 8016878: bf04 itt eq + 801687a: 089b lsreq r3, r3, #2 + 801687c: 3202 addeq r2, #2 + 801687e: 07d9 lsls r1, r3, #31 + 8016880: d403 bmi.n 801688a <__lo0bits+0x4e> + 8016882: 085b lsrs r3, r3, #1 + 8016884: f102 0201 add.w r2, r2, #1 + 8016888: d003 beq.n 8016892 <__lo0bits+0x56> + 801688a: 6003 str r3, [r0, #0] + 801688c: e7e5 b.n 801685a <__lo0bits+0x1e> + 801688e: 2200 movs r2, #0 + 8016890: e7e3 b.n 801685a <__lo0bits+0x1e> + 8016892: 2220 movs r2, #32 + 8016894: e7e1 b.n 801685a <__lo0bits+0x1e> ... -080143e8 <__i2b>: - 80143e8: b510 push {r4, lr} - 80143ea: 460c mov r4, r1 - 80143ec: 2101 movs r1, #1 - 80143ee: f7ff febb bl 8014168 <_Balloc> - 80143f2: 4602 mov r2, r0 - 80143f4: b928 cbnz r0, 8014402 <__i2b+0x1a> - 80143f6: 4b05 ldr r3, [pc, #20] ; (801440c <__i2b+0x24>) - 80143f8: 4805 ldr r0, [pc, #20] ; (8014410 <__i2b+0x28>) - 80143fa: f240 1145 movw r1, #325 ; 0x145 - 80143fe: f7fe fc65 bl 8012ccc <__assert_func> - 8014402: 2301 movs r3, #1 - 8014404: 6144 str r4, [r0, #20] - 8014406: 6103 str r3, [r0, #16] - 8014408: bd10 pop {r4, pc} - 801440a: bf00 nop - 801440c: 080189bc .word 0x080189bc - 8014410: 08018a2d .word 0x08018a2d - -08014414 <__multiply>: - 8014414: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8014418: 4691 mov r9, r2 - 801441a: 690a ldr r2, [r1, #16] - 801441c: f8d9 3010 ldr.w r3, [r9, #16] - 8014420: 429a cmp r2, r3 - 8014422: bfb8 it lt - 8014424: 460b movlt r3, r1 - 8014426: 460c mov r4, r1 - 8014428: bfbc itt lt - 801442a: 464c movlt r4, r9 - 801442c: 4699 movlt r9, r3 - 801442e: 6927 ldr r7, [r4, #16] - 8014430: f8d9 a010 ldr.w sl, [r9, #16] - 8014434: 68a3 ldr r3, [r4, #8] - 8014436: 6861 ldr r1, [r4, #4] - 8014438: eb07 060a add.w r6, r7, sl - 801443c: 42b3 cmp r3, r6 - 801443e: b085 sub sp, #20 - 8014440: bfb8 it lt - 8014442: 3101 addlt r1, #1 - 8014444: f7ff fe90 bl 8014168 <_Balloc> - 8014448: b930 cbnz r0, 8014458 <__multiply+0x44> - 801444a: 4602 mov r2, r0 - 801444c: 4b44 ldr r3, [pc, #272] ; (8014560 <__multiply+0x14c>) - 801444e: 4845 ldr r0, [pc, #276] ; (8014564 <__multiply+0x150>) - 8014450: f44f 71b1 mov.w r1, #354 ; 0x162 - 8014454: f7fe fc3a bl 8012ccc <__assert_func> - 8014458: f100 0514 add.w r5, r0, #20 - 801445c: eb05 0886 add.w r8, r5, r6, lsl #2 - 8014460: 462b mov r3, r5 - 8014462: 2200 movs r2, #0 - 8014464: 4543 cmp r3, r8 - 8014466: d321 bcc.n 80144ac <__multiply+0x98> - 8014468: f104 0314 add.w r3, r4, #20 - 801446c: eb03 0787 add.w r7, r3, r7, lsl #2 - 8014470: f109 0314 add.w r3, r9, #20 - 8014474: eb03 028a add.w r2, r3, sl, lsl #2 - 8014478: 9202 str r2, [sp, #8] - 801447a: 1b3a subs r2, r7, r4 - 801447c: 3a15 subs r2, #21 - 801447e: f022 0203 bic.w r2, r2, #3 - 8014482: 3204 adds r2, #4 - 8014484: f104 0115 add.w r1, r4, #21 - 8014488: 428f cmp r7, r1 - 801448a: bf38 it cc - 801448c: 2204 movcc r2, #4 - 801448e: 9201 str r2, [sp, #4] - 8014490: 9a02 ldr r2, [sp, #8] - 8014492: 9303 str r3, [sp, #12] - 8014494: 429a cmp r2, r3 - 8014496: d80c bhi.n 80144b2 <__multiply+0x9e> - 8014498: 2e00 cmp r6, #0 - 801449a: dd03 ble.n 80144a4 <__multiply+0x90> - 801449c: f858 3d04 ldr.w r3, [r8, #-4]! - 80144a0: 2b00 cmp r3, #0 - 80144a2: d05b beq.n 801455c <__multiply+0x148> - 80144a4: 6106 str r6, [r0, #16] - 80144a6: b005 add sp, #20 - 80144a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 80144ac: f843 2b04 str.w r2, [r3], #4 - 80144b0: e7d8 b.n 8014464 <__multiply+0x50> - 80144b2: f8b3 a000 ldrh.w sl, [r3] - 80144b6: f1ba 0f00 cmp.w sl, #0 - 80144ba: d024 beq.n 8014506 <__multiply+0xf2> - 80144bc: f104 0e14 add.w lr, r4, #20 - 80144c0: 46a9 mov r9, r5 - 80144c2: f04f 0c00 mov.w ip, #0 - 80144c6: f85e 2b04 ldr.w r2, [lr], #4 - 80144ca: f8d9 1000 ldr.w r1, [r9] - 80144ce: fa1f fb82 uxth.w fp, r2 - 80144d2: b289 uxth r1, r1 - 80144d4: fb0a 110b mla r1, sl, fp, r1 - 80144d8: ea4f 4b12 mov.w fp, r2, lsr #16 - 80144dc: f8d9 2000 ldr.w r2, [r9] - 80144e0: 4461 add r1, ip - 80144e2: ea4f 4c12 mov.w ip, r2, lsr #16 - 80144e6: fb0a c20b mla r2, sl, fp, ip - 80144ea: eb02 4211 add.w r2, r2, r1, lsr #16 - 80144ee: b289 uxth r1, r1 - 80144f0: ea41 4102 orr.w r1, r1, r2, lsl #16 - 80144f4: 4577 cmp r7, lr - 80144f6: f849 1b04 str.w r1, [r9], #4 - 80144fa: ea4f 4c12 mov.w ip, r2, lsr #16 - 80144fe: d8e2 bhi.n 80144c6 <__multiply+0xb2> - 8014500: 9a01 ldr r2, [sp, #4] - 8014502: f845 c002 str.w ip, [r5, r2] - 8014506: 9a03 ldr r2, [sp, #12] - 8014508: f8b2 9002 ldrh.w r9, [r2, #2] - 801450c: 3304 adds r3, #4 - 801450e: f1b9 0f00 cmp.w r9, #0 - 8014512: d021 beq.n 8014558 <__multiply+0x144> - 8014514: 6829 ldr r1, [r5, #0] - 8014516: f104 0c14 add.w ip, r4, #20 - 801451a: 46ae mov lr, r5 - 801451c: f04f 0a00 mov.w sl, #0 - 8014520: f8bc b000 ldrh.w fp, [ip] - 8014524: f8be 2002 ldrh.w r2, [lr, #2] - 8014528: fb09 220b mla r2, r9, fp, r2 - 801452c: 4452 add r2, sl - 801452e: b289 uxth r1, r1 - 8014530: ea41 4102 orr.w r1, r1, r2, lsl #16 - 8014534: f84e 1b04 str.w r1, [lr], #4 - 8014538: f85c 1b04 ldr.w r1, [ip], #4 - 801453c: ea4f 4a11 mov.w sl, r1, lsr #16 - 8014540: f8be 1000 ldrh.w r1, [lr] - 8014544: fb09 110a mla r1, r9, sl, r1 - 8014548: eb01 4112 add.w r1, r1, r2, lsr #16 - 801454c: 4567 cmp r7, ip - 801454e: ea4f 4a11 mov.w sl, r1, lsr #16 - 8014552: d8e5 bhi.n 8014520 <__multiply+0x10c> - 8014554: 9a01 ldr r2, [sp, #4] - 8014556: 50a9 str r1, [r5, r2] - 8014558: 3504 adds r5, #4 - 801455a: e799 b.n 8014490 <__multiply+0x7c> - 801455c: 3e01 subs r6, #1 - 801455e: e79b b.n 8014498 <__multiply+0x84> - 8014560: 080189bc .word 0x080189bc - 8014564: 08018a2d .word 0x08018a2d - -08014568 <__pow5mult>: - 8014568: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 801456c: 4615 mov r5, r2 - 801456e: f012 0203 ands.w r2, r2, #3 - 8014572: 4606 mov r6, r0 - 8014574: 460f mov r7, r1 - 8014576: d007 beq.n 8014588 <__pow5mult+0x20> - 8014578: 4c25 ldr r4, [pc, #148] ; (8014610 <__pow5mult+0xa8>) - 801457a: 3a01 subs r2, #1 - 801457c: 2300 movs r3, #0 - 801457e: f854 2022 ldr.w r2, [r4, r2, lsl #2] - 8014582: f7ff fe53 bl 801422c <__multadd> - 8014586: 4607 mov r7, r0 - 8014588: 10ad asrs r5, r5, #2 - 801458a: d03d beq.n 8014608 <__pow5mult+0xa0> - 801458c: 69f4 ldr r4, [r6, #28] - 801458e: b97c cbnz r4, 80145b0 <__pow5mult+0x48> - 8014590: 2010 movs r0, #16 - 8014592: f7fc facf bl 8010b34 - 8014596: 4602 mov r2, r0 - 8014598: 61f0 str r0, [r6, #28] - 801459a: b928 cbnz r0, 80145a8 <__pow5mult+0x40> - 801459c: 4b1d ldr r3, [pc, #116] ; (8014614 <__pow5mult+0xac>) - 801459e: 481e ldr r0, [pc, #120] ; (8014618 <__pow5mult+0xb0>) - 80145a0: f240 11b3 movw r1, #435 ; 0x1b3 - 80145a4: f7fe fb92 bl 8012ccc <__assert_func> - 80145a8: e9c0 4401 strd r4, r4, [r0, #4] - 80145ac: 6004 str r4, [r0, #0] - 80145ae: 60c4 str r4, [r0, #12] - 80145b0: f8d6 801c ldr.w r8, [r6, #28] - 80145b4: f8d8 4008 ldr.w r4, [r8, #8] - 80145b8: b94c cbnz r4, 80145ce <__pow5mult+0x66> - 80145ba: f240 2171 movw r1, #625 ; 0x271 - 80145be: 4630 mov r0, r6 - 80145c0: f7ff ff12 bl 80143e8 <__i2b> - 80145c4: 2300 movs r3, #0 - 80145c6: f8c8 0008 str.w r0, [r8, #8] - 80145ca: 4604 mov r4, r0 - 80145cc: 6003 str r3, [r0, #0] - 80145ce: f04f 0900 mov.w r9, #0 - 80145d2: 07eb lsls r3, r5, #31 - 80145d4: d50a bpl.n 80145ec <__pow5mult+0x84> - 80145d6: 4639 mov r1, r7 - 80145d8: 4622 mov r2, r4 - 80145da: 4630 mov r0, r6 - 80145dc: f7ff ff1a bl 8014414 <__multiply> - 80145e0: 4639 mov r1, r7 - 80145e2: 4680 mov r8, r0 - 80145e4: 4630 mov r0, r6 - 80145e6: f7ff fdff bl 80141e8 <_Bfree> - 80145ea: 4647 mov r7, r8 - 80145ec: 106d asrs r5, r5, #1 - 80145ee: d00b beq.n 8014608 <__pow5mult+0xa0> - 80145f0: 6820 ldr r0, [r4, #0] - 80145f2: b938 cbnz r0, 8014604 <__pow5mult+0x9c> - 80145f4: 4622 mov r2, r4 - 80145f6: 4621 mov r1, r4 - 80145f8: 4630 mov r0, r6 - 80145fa: f7ff ff0b bl 8014414 <__multiply> - 80145fe: 6020 str r0, [r4, #0] - 8014600: f8c0 9000 str.w r9, [r0] - 8014604: 4604 mov r4, r0 - 8014606: e7e4 b.n 80145d2 <__pow5mult+0x6a> - 8014608: 4638 mov r0, r7 - 801460a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 801460e: bf00 nop - 8014610: 08018b78 .word 0x08018b78 - 8014614: 080188a2 .word 0x080188a2 - 8014618: 08018a2d .word 0x08018a2d - -0801461c <__lshift>: - 801461c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 8014620: 460c mov r4, r1 - 8014622: 6849 ldr r1, [r1, #4] - 8014624: 6923 ldr r3, [r4, #16] - 8014626: eb03 1862 add.w r8, r3, r2, asr #5 - 801462a: 68a3 ldr r3, [r4, #8] - 801462c: 4607 mov r7, r0 - 801462e: 4691 mov r9, r2 - 8014630: ea4f 1a62 mov.w sl, r2, asr #5 - 8014634: f108 0601 add.w r6, r8, #1 - 8014638: 42b3 cmp r3, r6 - 801463a: db0b blt.n 8014654 <__lshift+0x38> - 801463c: 4638 mov r0, r7 - 801463e: f7ff fd93 bl 8014168 <_Balloc> - 8014642: 4605 mov r5, r0 - 8014644: b948 cbnz r0, 801465a <__lshift+0x3e> - 8014646: 4602 mov r2, r0 - 8014648: 4b28 ldr r3, [pc, #160] ; (80146ec <__lshift+0xd0>) - 801464a: 4829 ldr r0, [pc, #164] ; (80146f0 <__lshift+0xd4>) - 801464c: f44f 71ef mov.w r1, #478 ; 0x1de - 8014650: f7fe fb3c bl 8012ccc <__assert_func> - 8014654: 3101 adds r1, #1 - 8014656: 005b lsls r3, r3, #1 - 8014658: e7ee b.n 8014638 <__lshift+0x1c> - 801465a: 2300 movs r3, #0 - 801465c: f100 0114 add.w r1, r0, #20 - 8014660: f100 0210 add.w r2, r0, #16 - 8014664: 4618 mov r0, r3 - 8014666: 4553 cmp r3, sl - 8014668: db33 blt.n 80146d2 <__lshift+0xb6> - 801466a: 6920 ldr r0, [r4, #16] - 801466c: ea2a 7aea bic.w sl, sl, sl, asr #31 - 8014670: f104 0314 add.w r3, r4, #20 - 8014674: f019 091f ands.w r9, r9, #31 - 8014678: eb01 018a add.w r1, r1, sl, lsl #2 - 801467c: eb03 0c80 add.w ip, r3, r0, lsl #2 - 8014680: d02b beq.n 80146da <__lshift+0xbe> - 8014682: f1c9 0e20 rsb lr, r9, #32 - 8014686: 468a mov sl, r1 - 8014688: 2200 movs r2, #0 - 801468a: 6818 ldr r0, [r3, #0] - 801468c: fa00 f009 lsl.w r0, r0, r9 - 8014690: 4310 orrs r0, r2 - 8014692: f84a 0b04 str.w r0, [sl], #4 - 8014696: f853 2b04 ldr.w r2, [r3], #4 - 801469a: 459c cmp ip, r3 - 801469c: fa22 f20e lsr.w r2, r2, lr - 80146a0: d8f3 bhi.n 801468a <__lshift+0x6e> - 80146a2: ebac 0304 sub.w r3, ip, r4 - 80146a6: 3b15 subs r3, #21 - 80146a8: f023 0303 bic.w r3, r3, #3 - 80146ac: 3304 adds r3, #4 - 80146ae: f104 0015 add.w r0, r4, #21 - 80146b2: 4584 cmp ip, r0 - 80146b4: bf38 it cc - 80146b6: 2304 movcc r3, #4 - 80146b8: 50ca str r2, [r1, r3] - 80146ba: b10a cbz r2, 80146c0 <__lshift+0xa4> - 80146bc: f108 0602 add.w r6, r8, #2 - 80146c0: 3e01 subs r6, #1 - 80146c2: 4638 mov r0, r7 - 80146c4: 612e str r6, [r5, #16] - 80146c6: 4621 mov r1, r4 - 80146c8: f7ff fd8e bl 80141e8 <_Bfree> - 80146cc: 4628 mov r0, r5 - 80146ce: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80146d2: f842 0f04 str.w r0, [r2, #4]! - 80146d6: 3301 adds r3, #1 - 80146d8: e7c5 b.n 8014666 <__lshift+0x4a> - 80146da: 3904 subs r1, #4 - 80146dc: f853 2b04 ldr.w r2, [r3], #4 - 80146e0: f841 2f04 str.w r2, [r1, #4]! - 80146e4: 459c cmp ip, r3 - 80146e6: d8f9 bhi.n 80146dc <__lshift+0xc0> - 80146e8: e7ea b.n 80146c0 <__lshift+0xa4> - 80146ea: bf00 nop - 80146ec: 080189bc .word 0x080189bc - 80146f0: 08018a2d .word 0x08018a2d - -080146f4 <__mcmp>: - 80146f4: b530 push {r4, r5, lr} - 80146f6: 6902 ldr r2, [r0, #16] - 80146f8: 690c ldr r4, [r1, #16] - 80146fa: 1b12 subs r2, r2, r4 - 80146fc: d10e bne.n 801471c <__mcmp+0x28> - 80146fe: f100 0314 add.w r3, r0, #20 - 8014702: 3114 adds r1, #20 - 8014704: eb03 0084 add.w r0, r3, r4, lsl #2 - 8014708: eb01 0184 add.w r1, r1, r4, lsl #2 - 801470c: f850 5d04 ldr.w r5, [r0, #-4]! - 8014710: f851 4d04 ldr.w r4, [r1, #-4]! - 8014714: 42a5 cmp r5, r4 - 8014716: d003 beq.n 8014720 <__mcmp+0x2c> - 8014718: d305 bcc.n 8014726 <__mcmp+0x32> - 801471a: 2201 movs r2, #1 - 801471c: 4610 mov r0, r2 - 801471e: bd30 pop {r4, r5, pc} - 8014720: 4283 cmp r3, r0 - 8014722: d3f3 bcc.n 801470c <__mcmp+0x18> - 8014724: e7fa b.n 801471c <__mcmp+0x28> - 8014726: f04f 32ff mov.w r2, #4294967295 - 801472a: e7f7 b.n 801471c <__mcmp+0x28> - -0801472c <__mdiff>: - 801472c: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8014730: 460c mov r4, r1 - 8014732: 4606 mov r6, r0 - 8014734: 4611 mov r1, r2 - 8014736: 4620 mov r0, r4 - 8014738: 4690 mov r8, r2 - 801473a: f7ff ffdb bl 80146f4 <__mcmp> - 801473e: 1e05 subs r5, r0, #0 - 8014740: d110 bne.n 8014764 <__mdiff+0x38> - 8014742: 4629 mov r1, r5 - 8014744: 4630 mov r0, r6 - 8014746: f7ff fd0f bl 8014168 <_Balloc> - 801474a: b930 cbnz r0, 801475a <__mdiff+0x2e> - 801474c: 4b3a ldr r3, [pc, #232] ; (8014838 <__mdiff+0x10c>) - 801474e: 4602 mov r2, r0 - 8014750: f240 2137 movw r1, #567 ; 0x237 - 8014754: 4839 ldr r0, [pc, #228] ; (801483c <__mdiff+0x110>) - 8014756: f7fe fab9 bl 8012ccc <__assert_func> - 801475a: 2301 movs r3, #1 - 801475c: e9c0 3504 strd r3, r5, [r0, #16] - 8014760: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8014764: bfa4 itt ge - 8014766: 4643 movge r3, r8 - 8014768: 46a0 movge r8, r4 - 801476a: 4630 mov r0, r6 - 801476c: f8d8 1004 ldr.w r1, [r8, #4] - 8014770: bfa6 itte ge - 8014772: 461c movge r4, r3 - 8014774: 2500 movge r5, #0 - 8014776: 2501 movlt r5, #1 - 8014778: f7ff fcf6 bl 8014168 <_Balloc> - 801477c: b920 cbnz r0, 8014788 <__mdiff+0x5c> - 801477e: 4b2e ldr r3, [pc, #184] ; (8014838 <__mdiff+0x10c>) - 8014780: 4602 mov r2, r0 - 8014782: f240 2145 movw r1, #581 ; 0x245 - 8014786: e7e5 b.n 8014754 <__mdiff+0x28> - 8014788: f8d8 7010 ldr.w r7, [r8, #16] - 801478c: 6926 ldr r6, [r4, #16] - 801478e: 60c5 str r5, [r0, #12] - 8014790: f104 0914 add.w r9, r4, #20 - 8014794: f108 0514 add.w r5, r8, #20 - 8014798: f100 0e14 add.w lr, r0, #20 - 801479c: eb05 0c87 add.w ip, r5, r7, lsl #2 - 80147a0: eb09 0686 add.w r6, r9, r6, lsl #2 - 80147a4: f108 0210 add.w r2, r8, #16 - 80147a8: 46f2 mov sl, lr - 80147aa: 2100 movs r1, #0 - 80147ac: f859 3b04 ldr.w r3, [r9], #4 - 80147b0: f852 bf04 ldr.w fp, [r2, #4]! - 80147b4: fa11 f88b uxtah r8, r1, fp - 80147b8: b299 uxth r1, r3 - 80147ba: 0c1b lsrs r3, r3, #16 - 80147bc: eba8 0801 sub.w r8, r8, r1 - 80147c0: ebc3 431b rsb r3, r3, fp, lsr #16 - 80147c4: eb03 4328 add.w r3, r3, r8, asr #16 - 80147c8: fa1f f888 uxth.w r8, r8 - 80147cc: 1419 asrs r1, r3, #16 - 80147ce: 454e cmp r6, r9 - 80147d0: ea48 4303 orr.w r3, r8, r3, lsl #16 - 80147d4: f84a 3b04 str.w r3, [sl], #4 - 80147d8: d8e8 bhi.n 80147ac <__mdiff+0x80> - 80147da: 1b33 subs r3, r6, r4 - 80147dc: 3b15 subs r3, #21 - 80147de: f023 0303 bic.w r3, r3, #3 - 80147e2: 3304 adds r3, #4 - 80147e4: 3415 adds r4, #21 - 80147e6: 42a6 cmp r6, r4 - 80147e8: bf38 it cc - 80147ea: 2304 movcc r3, #4 - 80147ec: 441d add r5, r3 - 80147ee: 4473 add r3, lr - 80147f0: 469e mov lr, r3 - 80147f2: 462e mov r6, r5 - 80147f4: 4566 cmp r6, ip - 80147f6: d30e bcc.n 8014816 <__mdiff+0xea> - 80147f8: f10c 0203 add.w r2, ip, #3 - 80147fc: 1b52 subs r2, r2, r5 - 80147fe: f022 0203 bic.w r2, r2, #3 - 8014802: 3d03 subs r5, #3 - 8014804: 45ac cmp ip, r5 - 8014806: bf38 it cc - 8014808: 2200 movcc r2, #0 - 801480a: 4413 add r3, r2 - 801480c: f853 2d04 ldr.w r2, [r3, #-4]! - 8014810: b17a cbz r2, 8014832 <__mdiff+0x106> - 8014812: 6107 str r7, [r0, #16] - 8014814: e7a4 b.n 8014760 <__mdiff+0x34> - 8014816: f856 8b04 ldr.w r8, [r6], #4 - 801481a: fa11 f288 uxtah r2, r1, r8 - 801481e: 1414 asrs r4, r2, #16 - 8014820: eb04 4418 add.w r4, r4, r8, lsr #16 - 8014824: b292 uxth r2, r2 - 8014826: ea42 4204 orr.w r2, r2, r4, lsl #16 - 801482a: f84e 2b04 str.w r2, [lr], #4 - 801482e: 1421 asrs r1, r4, #16 - 8014830: e7e0 b.n 80147f4 <__mdiff+0xc8> - 8014832: 3f01 subs r7, #1 - 8014834: e7ea b.n 801480c <__mdiff+0xe0> - 8014836: bf00 nop - 8014838: 080189bc .word 0x080189bc - 801483c: 08018a2d .word 0x08018a2d - -08014840 <__ulp>: - 8014840: b082 sub sp, #8 - 8014842: ed8d 0b00 vstr d0, [sp] - 8014846: 9a01 ldr r2, [sp, #4] - 8014848: 4b0f ldr r3, [pc, #60] ; (8014888 <__ulp+0x48>) - 801484a: 4013 ands r3, r2 - 801484c: f1a3 7350 sub.w r3, r3, #54525952 ; 0x3400000 - 8014850: 2b00 cmp r3, #0 - 8014852: dc08 bgt.n 8014866 <__ulp+0x26> - 8014854: 425b negs r3, r3 - 8014856: f1b3 7fa0 cmp.w r3, #20971520 ; 0x1400000 - 801485a: ea4f 5223 mov.w r2, r3, asr #20 - 801485e: da04 bge.n 801486a <__ulp+0x2a> - 8014860: f44f 2300 mov.w r3, #524288 ; 0x80000 - 8014864: 4113 asrs r3, r2 - 8014866: 2200 movs r2, #0 - 8014868: e008 b.n 801487c <__ulp+0x3c> - 801486a: f1a2 0314 sub.w r3, r2, #20 - 801486e: 2b1e cmp r3, #30 - 8014870: bfda itte le - 8014872: f04f 4200 movle.w r2, #2147483648 ; 0x80000000 - 8014876: 40da lsrle r2, r3 - 8014878: 2201 movgt r2, #1 - 801487a: 2300 movs r3, #0 - 801487c: 4619 mov r1, r3 - 801487e: 4610 mov r0, r2 - 8014880: ec41 0b10 vmov d0, r0, r1 - 8014884: b002 add sp, #8 - 8014886: 4770 bx lr - 8014888: 7ff00000 .word 0x7ff00000 - -0801488c <__b2d>: - 801488c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8014890: 6906 ldr r6, [r0, #16] - 8014892: f100 0814 add.w r8, r0, #20 - 8014896: eb08 0686 add.w r6, r8, r6, lsl #2 - 801489a: 1f37 subs r7, r6, #4 - 801489c: f856 2c04 ldr.w r2, [r6, #-4] - 80148a0: 4610 mov r0, r2 - 80148a2: f7ff fd53 bl 801434c <__hi0bits> - 80148a6: f1c0 0320 rsb r3, r0, #32 - 80148aa: 280a cmp r0, #10 - 80148ac: 600b str r3, [r1, #0] - 80148ae: 491b ldr r1, [pc, #108] ; (801491c <__b2d+0x90>) - 80148b0: dc15 bgt.n 80148de <__b2d+0x52> - 80148b2: f1c0 0c0b rsb ip, r0, #11 - 80148b6: fa22 f30c lsr.w r3, r2, ip - 80148ba: 45b8 cmp r8, r7 - 80148bc: ea43 0501 orr.w r5, r3, r1 - 80148c0: bf34 ite cc - 80148c2: f856 3c08 ldrcc.w r3, [r6, #-8] - 80148c6: 2300 movcs r3, #0 - 80148c8: 3015 adds r0, #21 - 80148ca: fa02 f000 lsl.w r0, r2, r0 - 80148ce: fa23 f30c lsr.w r3, r3, ip - 80148d2: 4303 orrs r3, r0 - 80148d4: 461c mov r4, r3 - 80148d6: ec45 4b10 vmov d0, r4, r5 - 80148da: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 80148de: 45b8 cmp r8, r7 - 80148e0: bf3a itte cc - 80148e2: f856 3c08 ldrcc.w r3, [r6, #-8] - 80148e6: f1a6 0708 subcc.w r7, r6, #8 - 80148ea: 2300 movcs r3, #0 - 80148ec: 380b subs r0, #11 - 80148ee: d012 beq.n 8014916 <__b2d+0x8a> - 80148f0: f1c0 0120 rsb r1, r0, #32 - 80148f4: fa23 f401 lsr.w r4, r3, r1 - 80148f8: 4082 lsls r2, r0 - 80148fa: 4322 orrs r2, r4 - 80148fc: 4547 cmp r7, r8 - 80148fe: f042 557f orr.w r5, r2, #1069547520 ; 0x3fc00000 - 8014902: bf8c ite hi - 8014904: f857 2c04 ldrhi.w r2, [r7, #-4] - 8014908: 2200 movls r2, #0 - 801490a: 4083 lsls r3, r0 - 801490c: 40ca lsrs r2, r1 - 801490e: f445 1540 orr.w r5, r5, #3145728 ; 0x300000 - 8014912: 4313 orrs r3, r2 - 8014914: e7de b.n 80148d4 <__b2d+0x48> - 8014916: ea42 0501 orr.w r5, r2, r1 - 801491a: e7db b.n 80148d4 <__b2d+0x48> - 801491c: 3ff00000 .word 0x3ff00000 - -08014920 <__d2b>: - 8014920: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} - 8014924: 460f mov r7, r1 - 8014926: 2101 movs r1, #1 - 8014928: ec59 8b10 vmov r8, r9, d0 - 801492c: 4616 mov r6, r2 - 801492e: f7ff fc1b bl 8014168 <_Balloc> - 8014932: 4604 mov r4, r0 - 8014934: b930 cbnz r0, 8014944 <__d2b+0x24> - 8014936: 4602 mov r2, r0 - 8014938: 4b24 ldr r3, [pc, #144] ; (80149cc <__d2b+0xac>) - 801493a: 4825 ldr r0, [pc, #148] ; (80149d0 <__d2b+0xb0>) - 801493c: f240 310f movw r1, #783 ; 0x30f - 8014940: f7fe f9c4 bl 8012ccc <__assert_func> - 8014944: f3c9 550a ubfx r5, r9, #20, #11 - 8014948: f3c9 0313 ubfx r3, r9, #0, #20 - 801494c: bb2d cbnz r5, 801499a <__d2b+0x7a> - 801494e: 9301 str r3, [sp, #4] - 8014950: f1b8 0300 subs.w r3, r8, #0 - 8014954: d026 beq.n 80149a4 <__d2b+0x84> - 8014956: 4668 mov r0, sp - 8014958: 9300 str r3, [sp, #0] - 801495a: f7ff fd17 bl 801438c <__lo0bits> - 801495e: e9dd 1200 ldrd r1, r2, [sp] - 8014962: b1e8 cbz r0, 80149a0 <__d2b+0x80> - 8014964: f1c0 0320 rsb r3, r0, #32 - 8014968: fa02 f303 lsl.w r3, r2, r3 - 801496c: 430b orrs r3, r1 - 801496e: 40c2 lsrs r2, r0 - 8014970: 6163 str r3, [r4, #20] - 8014972: 9201 str r2, [sp, #4] - 8014974: 9b01 ldr r3, [sp, #4] - 8014976: 61a3 str r3, [r4, #24] - 8014978: 2b00 cmp r3, #0 - 801497a: bf14 ite ne - 801497c: 2202 movne r2, #2 - 801497e: 2201 moveq r2, #1 - 8014980: 6122 str r2, [r4, #16] - 8014982: b1bd cbz r5, 80149b4 <__d2b+0x94> - 8014984: f2a5 4533 subw r5, r5, #1075 ; 0x433 - 8014988: 4405 add r5, r0 - 801498a: 603d str r5, [r7, #0] - 801498c: f1c0 0035 rsb r0, r0, #53 ; 0x35 - 8014990: 6030 str r0, [r6, #0] - 8014992: 4620 mov r0, r4 - 8014994: b003 add sp, #12 - 8014996: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} - 801499a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 - 801499e: e7d6 b.n 801494e <__d2b+0x2e> - 80149a0: 6161 str r1, [r4, #20] - 80149a2: e7e7 b.n 8014974 <__d2b+0x54> - 80149a4: a801 add r0, sp, #4 - 80149a6: f7ff fcf1 bl 801438c <__lo0bits> - 80149aa: 9b01 ldr r3, [sp, #4] - 80149ac: 6163 str r3, [r4, #20] - 80149ae: 3020 adds r0, #32 - 80149b0: 2201 movs r2, #1 - 80149b2: e7e5 b.n 8014980 <__d2b+0x60> - 80149b4: eb04 0382 add.w r3, r4, r2, lsl #2 - 80149b8: f2a0 4032 subw r0, r0, #1074 ; 0x432 - 80149bc: 6038 str r0, [r7, #0] - 80149be: 6918 ldr r0, [r3, #16] - 80149c0: f7ff fcc4 bl 801434c <__hi0bits> - 80149c4: ebc0 1042 rsb r0, r0, r2, lsl #5 - 80149c8: e7e2 b.n 8014990 <__d2b+0x70> - 80149ca: bf00 nop - 80149cc: 080189bc .word 0x080189bc - 80149d0: 08018a2d .word 0x08018a2d - -080149d4 <__ratio>: - 80149d4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 80149d8: 4688 mov r8, r1 - 80149da: 4669 mov r1, sp - 80149dc: 4681 mov r9, r0 - 80149de: f7ff ff55 bl 801488c <__b2d> - 80149e2: a901 add r1, sp, #4 - 80149e4: 4640 mov r0, r8 - 80149e6: ec55 4b10 vmov r4, r5, d0 - 80149ea: f7ff ff4f bl 801488c <__b2d> - 80149ee: f8d9 3010 ldr.w r3, [r9, #16] - 80149f2: f8d8 2010 ldr.w r2, [r8, #16] - 80149f6: eba3 0c02 sub.w ip, r3, r2 - 80149fa: e9dd 3200 ldrd r3, r2, [sp] - 80149fe: 1a9b subs r3, r3, r2 - 8014a00: eb03 134c add.w r3, r3, ip, lsl #5 - 8014a04: ec51 0b10 vmov r0, r1, d0 - 8014a08: 2b00 cmp r3, #0 - 8014a0a: bfd6 itet le - 8014a0c: 460a movle r2, r1 - 8014a0e: 462a movgt r2, r5 - 8014a10: ebc3 3303 rsble r3, r3, r3, lsl #12 - 8014a14: 468b mov fp, r1 - 8014a16: 462f mov r7, r5 - 8014a18: bfd4 ite le - 8014a1a: eb02 5b03 addle.w fp, r2, r3, lsl #20 - 8014a1e: eb02 5703 addgt.w r7, r2, r3, lsl #20 - 8014a22: 4620 mov r0, r4 - 8014a24: ee10 2a10 vmov r2, s0 - 8014a28: 465b mov r3, fp - 8014a2a: 4639 mov r1, r7 - 8014a2c: f7eb ff0e bl 800084c <__aeabi_ddiv> - 8014a30: ec41 0b10 vmov d0, r0, r1 - 8014a34: b003 add sp, #12 - 8014a36: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - -08014a3a <__copybits>: - 8014a3a: 3901 subs r1, #1 - 8014a3c: b570 push {r4, r5, r6, lr} - 8014a3e: 1149 asrs r1, r1, #5 - 8014a40: 6914 ldr r4, [r2, #16] - 8014a42: 3101 adds r1, #1 - 8014a44: f102 0314 add.w r3, r2, #20 - 8014a48: eb00 0181 add.w r1, r0, r1, lsl #2 - 8014a4c: eb03 0484 add.w r4, r3, r4, lsl #2 - 8014a50: 1f05 subs r5, r0, #4 - 8014a52: 42a3 cmp r3, r4 - 8014a54: d30c bcc.n 8014a70 <__copybits+0x36> - 8014a56: 1aa3 subs r3, r4, r2 - 8014a58: 3b11 subs r3, #17 - 8014a5a: f023 0303 bic.w r3, r3, #3 - 8014a5e: 3211 adds r2, #17 - 8014a60: 42a2 cmp r2, r4 - 8014a62: bf88 it hi - 8014a64: 2300 movhi r3, #0 - 8014a66: 4418 add r0, r3 - 8014a68: 2300 movs r3, #0 - 8014a6a: 4288 cmp r0, r1 - 8014a6c: d305 bcc.n 8014a7a <__copybits+0x40> - 8014a6e: bd70 pop {r4, r5, r6, pc} - 8014a70: f853 6b04 ldr.w r6, [r3], #4 - 8014a74: f845 6f04 str.w r6, [r5, #4]! - 8014a78: e7eb b.n 8014a52 <__copybits+0x18> - 8014a7a: f840 3b04 str.w r3, [r0], #4 - 8014a7e: e7f4 b.n 8014a6a <__copybits+0x30> - -08014a80 <__any_on>: - 8014a80: f100 0214 add.w r2, r0, #20 - 8014a84: 6900 ldr r0, [r0, #16] - 8014a86: 114b asrs r3, r1, #5 - 8014a88: 4298 cmp r0, r3 - 8014a8a: b510 push {r4, lr} - 8014a8c: db11 blt.n 8014ab2 <__any_on+0x32> - 8014a8e: dd0a ble.n 8014aa6 <__any_on+0x26> - 8014a90: f011 011f ands.w r1, r1, #31 - 8014a94: d007 beq.n 8014aa6 <__any_on+0x26> - 8014a96: f852 4023 ldr.w r4, [r2, r3, lsl #2] - 8014a9a: fa24 f001 lsr.w r0, r4, r1 - 8014a9e: fa00 f101 lsl.w r1, r0, r1 - 8014aa2: 428c cmp r4, r1 - 8014aa4: d10b bne.n 8014abe <__any_on+0x3e> - 8014aa6: eb02 0383 add.w r3, r2, r3, lsl #2 - 8014aaa: 4293 cmp r3, r2 - 8014aac: d803 bhi.n 8014ab6 <__any_on+0x36> - 8014aae: 2000 movs r0, #0 - 8014ab0: bd10 pop {r4, pc} - 8014ab2: 4603 mov r3, r0 - 8014ab4: e7f7 b.n 8014aa6 <__any_on+0x26> - 8014ab6: f853 1d04 ldr.w r1, [r3, #-4]! - 8014aba: 2900 cmp r1, #0 - 8014abc: d0f5 beq.n 8014aaa <__any_on+0x2a> - 8014abe: 2001 movs r0, #1 - 8014ac0: e7f6 b.n 8014ab0 <__any_on+0x30> - -08014ac2 <__ascii_wctomb>: - 8014ac2: b149 cbz r1, 8014ad8 <__ascii_wctomb+0x16> - 8014ac4: 2aff cmp r2, #255 ; 0xff - 8014ac6: bf85 ittet hi - 8014ac8: 238a movhi r3, #138 ; 0x8a - 8014aca: 6003 strhi r3, [r0, #0] - 8014acc: 700a strbls r2, [r1, #0] - 8014ace: f04f 30ff movhi.w r0, #4294967295 - 8014ad2: bf98 it ls - 8014ad4: 2001 movls r0, #1 - 8014ad6: 4770 bx lr - 8014ad8: 4608 mov r0, r1 - 8014ada: 4770 bx lr - -08014adc <__ssputs_r>: - 8014adc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 8014ae0: 688e ldr r6, [r1, #8] - 8014ae2: 461f mov r7, r3 - 8014ae4: 42be cmp r6, r7 - 8014ae6: 680b ldr r3, [r1, #0] - 8014ae8: 4682 mov sl, r0 - 8014aea: 460c mov r4, r1 - 8014aec: 4690 mov r8, r2 - 8014aee: d82c bhi.n 8014b4a <__ssputs_r+0x6e> - 8014af0: 898a ldrh r2, [r1, #12] - 8014af2: f412 6f90 tst.w r2, #1152 ; 0x480 - 8014af6: d026 beq.n 8014b46 <__ssputs_r+0x6a> - 8014af8: 6965 ldr r5, [r4, #20] - 8014afa: 6909 ldr r1, [r1, #16] - 8014afc: eb05 0545 add.w r5, r5, r5, lsl #1 - 8014b00: eba3 0901 sub.w r9, r3, r1 - 8014b04: eb05 75d5 add.w r5, r5, r5, lsr #31 - 8014b08: 1c7b adds r3, r7, #1 - 8014b0a: 444b add r3, r9 - 8014b0c: 106d asrs r5, r5, #1 - 8014b0e: 429d cmp r5, r3 - 8014b10: bf38 it cc - 8014b12: 461d movcc r5, r3 - 8014b14: 0553 lsls r3, r2, #21 - 8014b16: d527 bpl.n 8014b68 <__ssputs_r+0x8c> - 8014b18: 4629 mov r1, r5 - 8014b1a: f7fc f83b bl 8010b94 <_malloc_r> - 8014b1e: 4606 mov r6, r0 - 8014b20: b360 cbz r0, 8014b7c <__ssputs_r+0xa0> - 8014b22: 6921 ldr r1, [r4, #16] - 8014b24: 464a mov r2, r9 - 8014b26: f7fe f8b4 bl 8012c92 - 8014b2a: 89a3 ldrh r3, [r4, #12] - 8014b2c: f423 6390 bic.w r3, r3, #1152 ; 0x480 - 8014b30: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8014b34: 81a3 strh r3, [r4, #12] - 8014b36: 6126 str r6, [r4, #16] - 8014b38: 6165 str r5, [r4, #20] - 8014b3a: 444e add r6, r9 - 8014b3c: eba5 0509 sub.w r5, r5, r9 - 8014b40: 6026 str r6, [r4, #0] - 8014b42: 60a5 str r5, [r4, #8] - 8014b44: 463e mov r6, r7 - 8014b46: 42be cmp r6, r7 - 8014b48: d900 bls.n 8014b4c <__ssputs_r+0x70> - 8014b4a: 463e mov r6, r7 - 8014b4c: 6820 ldr r0, [r4, #0] - 8014b4e: 4632 mov r2, r6 - 8014b50: 4641 mov r1, r8 - 8014b52: f000 f9db bl 8014f0c - 8014b56: 68a3 ldr r3, [r4, #8] - 8014b58: 1b9b subs r3, r3, r6 - 8014b5a: 60a3 str r3, [r4, #8] - 8014b5c: 6823 ldr r3, [r4, #0] - 8014b5e: 4433 add r3, r6 - 8014b60: 6023 str r3, [r4, #0] - 8014b62: 2000 movs r0, #0 - 8014b64: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8014b68: 462a mov r2, r5 - 8014b6a: f000 fa06 bl 8014f7a <_realloc_r> - 8014b6e: 4606 mov r6, r0 - 8014b70: 2800 cmp r0, #0 - 8014b72: d1e0 bne.n 8014b36 <__ssputs_r+0x5a> - 8014b74: 6921 ldr r1, [r4, #16] - 8014b76: 4650 mov r0, sl - 8014b78: f7fe ff40 bl 80139fc <_free_r> - 8014b7c: 230c movs r3, #12 - 8014b7e: f8ca 3000 str.w r3, [sl] - 8014b82: 89a3 ldrh r3, [r4, #12] - 8014b84: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8014b88: 81a3 strh r3, [r4, #12] - 8014b8a: f04f 30ff mov.w r0, #4294967295 - 8014b8e: e7e9 b.n 8014b64 <__ssputs_r+0x88> - -08014b90 <_svfiprintf_r>: - 8014b90: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8014b94: 4698 mov r8, r3 - 8014b96: 898b ldrh r3, [r1, #12] - 8014b98: 061b lsls r3, r3, #24 - 8014b9a: b09d sub sp, #116 ; 0x74 - 8014b9c: 4607 mov r7, r0 - 8014b9e: 460d mov r5, r1 - 8014ba0: 4614 mov r4, r2 - 8014ba2: d50e bpl.n 8014bc2 <_svfiprintf_r+0x32> - 8014ba4: 690b ldr r3, [r1, #16] - 8014ba6: b963 cbnz r3, 8014bc2 <_svfiprintf_r+0x32> - 8014ba8: 2140 movs r1, #64 ; 0x40 - 8014baa: f7fb fff3 bl 8010b94 <_malloc_r> - 8014bae: 6028 str r0, [r5, #0] - 8014bb0: 6128 str r0, [r5, #16] - 8014bb2: b920 cbnz r0, 8014bbe <_svfiprintf_r+0x2e> - 8014bb4: 230c movs r3, #12 - 8014bb6: 603b str r3, [r7, #0] - 8014bb8: f04f 30ff mov.w r0, #4294967295 - 8014bbc: e0d0 b.n 8014d60 <_svfiprintf_r+0x1d0> - 8014bbe: 2340 movs r3, #64 ; 0x40 - 8014bc0: 616b str r3, [r5, #20] - 8014bc2: 2300 movs r3, #0 - 8014bc4: 9309 str r3, [sp, #36] ; 0x24 - 8014bc6: 2320 movs r3, #32 - 8014bc8: f88d 3029 strb.w r3, [sp, #41] ; 0x29 - 8014bcc: f8cd 800c str.w r8, [sp, #12] - 8014bd0: 2330 movs r3, #48 ; 0x30 - 8014bd2: f8df 81a4 ldr.w r8, [pc, #420] ; 8014d78 <_svfiprintf_r+0x1e8> - 8014bd6: f88d 302a strb.w r3, [sp, #42] ; 0x2a - 8014bda: f04f 0901 mov.w r9, #1 - 8014bde: 4623 mov r3, r4 - 8014be0: 469a mov sl, r3 - 8014be2: f813 2b01 ldrb.w r2, [r3], #1 - 8014be6: b10a cbz r2, 8014bec <_svfiprintf_r+0x5c> - 8014be8: 2a25 cmp r2, #37 ; 0x25 - 8014bea: d1f9 bne.n 8014be0 <_svfiprintf_r+0x50> - 8014bec: ebba 0b04 subs.w fp, sl, r4 - 8014bf0: d00b beq.n 8014c0a <_svfiprintf_r+0x7a> - 8014bf2: 465b mov r3, fp - 8014bf4: 4622 mov r2, r4 - 8014bf6: 4629 mov r1, r5 - 8014bf8: 4638 mov r0, r7 - 8014bfa: f7ff ff6f bl 8014adc <__ssputs_r> - 8014bfe: 3001 adds r0, #1 - 8014c00: f000 80a9 beq.w 8014d56 <_svfiprintf_r+0x1c6> - 8014c04: 9a09 ldr r2, [sp, #36] ; 0x24 - 8014c06: 445a add r2, fp - 8014c08: 9209 str r2, [sp, #36] ; 0x24 - 8014c0a: f89a 3000 ldrb.w r3, [sl] - 8014c0e: 2b00 cmp r3, #0 - 8014c10: f000 80a1 beq.w 8014d56 <_svfiprintf_r+0x1c6> - 8014c14: 2300 movs r3, #0 - 8014c16: f04f 32ff mov.w r2, #4294967295 - 8014c1a: e9cd 2305 strd r2, r3, [sp, #20] - 8014c1e: f10a 0a01 add.w sl, sl, #1 - 8014c22: 9304 str r3, [sp, #16] - 8014c24: 9307 str r3, [sp, #28] - 8014c26: f88d 3053 strb.w r3, [sp, #83] ; 0x53 - 8014c2a: 931a str r3, [sp, #104] ; 0x68 - 8014c2c: 4654 mov r4, sl - 8014c2e: 2205 movs r2, #5 - 8014c30: f814 1b01 ldrb.w r1, [r4], #1 - 8014c34: 4850 ldr r0, [pc, #320] ; (8014d78 <_svfiprintf_r+0x1e8>) - 8014c36: f7eb facb bl 80001d0 - 8014c3a: 9a04 ldr r2, [sp, #16] - 8014c3c: b9d8 cbnz r0, 8014c76 <_svfiprintf_r+0xe6> - 8014c3e: 06d0 lsls r0, r2, #27 - 8014c40: bf44 itt mi - 8014c42: 2320 movmi r3, #32 - 8014c44: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 8014c48: 0711 lsls r1, r2, #28 - 8014c4a: bf44 itt mi - 8014c4c: 232b movmi r3, #43 ; 0x2b - 8014c4e: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 8014c52: f89a 3000 ldrb.w r3, [sl] - 8014c56: 2b2a cmp r3, #42 ; 0x2a - 8014c58: d015 beq.n 8014c86 <_svfiprintf_r+0xf6> - 8014c5a: 9a07 ldr r2, [sp, #28] - 8014c5c: 4654 mov r4, sl - 8014c5e: 2000 movs r0, #0 - 8014c60: f04f 0c0a mov.w ip, #10 - 8014c64: 4621 mov r1, r4 - 8014c66: f811 3b01 ldrb.w r3, [r1], #1 - 8014c6a: 3b30 subs r3, #48 ; 0x30 - 8014c6c: 2b09 cmp r3, #9 - 8014c6e: d94d bls.n 8014d0c <_svfiprintf_r+0x17c> - 8014c70: b1b0 cbz r0, 8014ca0 <_svfiprintf_r+0x110> - 8014c72: 9207 str r2, [sp, #28] - 8014c74: e014 b.n 8014ca0 <_svfiprintf_r+0x110> - 8014c76: eba0 0308 sub.w r3, r0, r8 - 8014c7a: fa09 f303 lsl.w r3, r9, r3 - 8014c7e: 4313 orrs r3, r2 - 8014c80: 9304 str r3, [sp, #16] - 8014c82: 46a2 mov sl, r4 - 8014c84: e7d2 b.n 8014c2c <_svfiprintf_r+0x9c> - 8014c86: 9b03 ldr r3, [sp, #12] - 8014c88: 1d19 adds r1, r3, #4 - 8014c8a: 681b ldr r3, [r3, #0] - 8014c8c: 9103 str r1, [sp, #12] - 8014c8e: 2b00 cmp r3, #0 - 8014c90: bfbb ittet lt - 8014c92: 425b neglt r3, r3 - 8014c94: f042 0202 orrlt.w r2, r2, #2 - 8014c98: 9307 strge r3, [sp, #28] - 8014c9a: 9307 strlt r3, [sp, #28] - 8014c9c: bfb8 it lt - 8014c9e: 9204 strlt r2, [sp, #16] - 8014ca0: 7823 ldrb r3, [r4, #0] - 8014ca2: 2b2e cmp r3, #46 ; 0x2e - 8014ca4: d10c bne.n 8014cc0 <_svfiprintf_r+0x130> - 8014ca6: 7863 ldrb r3, [r4, #1] - 8014ca8: 2b2a cmp r3, #42 ; 0x2a - 8014caa: d134 bne.n 8014d16 <_svfiprintf_r+0x186> - 8014cac: 9b03 ldr r3, [sp, #12] - 8014cae: 1d1a adds r2, r3, #4 - 8014cb0: 681b ldr r3, [r3, #0] - 8014cb2: 9203 str r2, [sp, #12] - 8014cb4: 2b00 cmp r3, #0 - 8014cb6: bfb8 it lt - 8014cb8: f04f 33ff movlt.w r3, #4294967295 - 8014cbc: 3402 adds r4, #2 - 8014cbe: 9305 str r3, [sp, #20] - 8014cc0: f8df a0c4 ldr.w sl, [pc, #196] ; 8014d88 <_svfiprintf_r+0x1f8> - 8014cc4: 7821 ldrb r1, [r4, #0] - 8014cc6: 2203 movs r2, #3 - 8014cc8: 4650 mov r0, sl - 8014cca: f7eb fa81 bl 80001d0 - 8014cce: b138 cbz r0, 8014ce0 <_svfiprintf_r+0x150> - 8014cd0: 9b04 ldr r3, [sp, #16] - 8014cd2: eba0 000a sub.w r0, r0, sl - 8014cd6: 2240 movs r2, #64 ; 0x40 - 8014cd8: 4082 lsls r2, r0 - 8014cda: 4313 orrs r3, r2 - 8014cdc: 3401 adds r4, #1 - 8014cde: 9304 str r3, [sp, #16] - 8014ce0: f814 1b01 ldrb.w r1, [r4], #1 - 8014ce4: 4825 ldr r0, [pc, #148] ; (8014d7c <_svfiprintf_r+0x1ec>) - 8014ce6: f88d 1028 strb.w r1, [sp, #40] ; 0x28 - 8014cea: 2206 movs r2, #6 - 8014cec: f7eb fa70 bl 80001d0 - 8014cf0: 2800 cmp r0, #0 - 8014cf2: d038 beq.n 8014d66 <_svfiprintf_r+0x1d6> - 8014cf4: 4b22 ldr r3, [pc, #136] ; (8014d80 <_svfiprintf_r+0x1f0>) - 8014cf6: bb1b cbnz r3, 8014d40 <_svfiprintf_r+0x1b0> - 8014cf8: 9b03 ldr r3, [sp, #12] - 8014cfa: 3307 adds r3, #7 - 8014cfc: f023 0307 bic.w r3, r3, #7 - 8014d00: 3308 adds r3, #8 - 8014d02: 9303 str r3, [sp, #12] - 8014d04: 9b09 ldr r3, [sp, #36] ; 0x24 - 8014d06: 4433 add r3, r6 - 8014d08: 9309 str r3, [sp, #36] ; 0x24 - 8014d0a: e768 b.n 8014bde <_svfiprintf_r+0x4e> - 8014d0c: fb0c 3202 mla r2, ip, r2, r3 - 8014d10: 460c mov r4, r1 - 8014d12: 2001 movs r0, #1 - 8014d14: e7a6 b.n 8014c64 <_svfiprintf_r+0xd4> - 8014d16: 2300 movs r3, #0 - 8014d18: 3401 adds r4, #1 - 8014d1a: 9305 str r3, [sp, #20] - 8014d1c: 4619 mov r1, r3 - 8014d1e: f04f 0c0a mov.w ip, #10 - 8014d22: 4620 mov r0, r4 - 8014d24: f810 2b01 ldrb.w r2, [r0], #1 - 8014d28: 3a30 subs r2, #48 ; 0x30 - 8014d2a: 2a09 cmp r2, #9 - 8014d2c: d903 bls.n 8014d36 <_svfiprintf_r+0x1a6> - 8014d2e: 2b00 cmp r3, #0 - 8014d30: d0c6 beq.n 8014cc0 <_svfiprintf_r+0x130> - 8014d32: 9105 str r1, [sp, #20] - 8014d34: e7c4 b.n 8014cc0 <_svfiprintf_r+0x130> - 8014d36: fb0c 2101 mla r1, ip, r1, r2 - 8014d3a: 4604 mov r4, r0 - 8014d3c: 2301 movs r3, #1 - 8014d3e: e7f0 b.n 8014d22 <_svfiprintf_r+0x192> - 8014d40: ab03 add r3, sp, #12 - 8014d42: 9300 str r3, [sp, #0] - 8014d44: 462a mov r2, r5 - 8014d46: 4b0f ldr r3, [pc, #60] ; (8014d84 <_svfiprintf_r+0x1f4>) - 8014d48: a904 add r1, sp, #16 - 8014d4a: 4638 mov r0, r7 - 8014d4c: f7fc ff56 bl 8011bfc <_printf_float> - 8014d50: 1c42 adds r2, r0, #1 - 8014d52: 4606 mov r6, r0 - 8014d54: d1d6 bne.n 8014d04 <_svfiprintf_r+0x174> - 8014d56: 89ab ldrh r3, [r5, #12] - 8014d58: 065b lsls r3, r3, #25 - 8014d5a: f53f af2d bmi.w 8014bb8 <_svfiprintf_r+0x28> - 8014d5e: 9809 ldr r0, [sp, #36] ; 0x24 - 8014d60: b01d add sp, #116 ; 0x74 - 8014d62: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8014d66: ab03 add r3, sp, #12 - 8014d68: 9300 str r3, [sp, #0] - 8014d6a: 462a mov r2, r5 - 8014d6c: 4b05 ldr r3, [pc, #20] ; (8014d84 <_svfiprintf_r+0x1f4>) - 8014d6e: a904 add r1, sp, #16 - 8014d70: 4638 mov r0, r7 - 8014d72: f7fd f9e7 bl 8012144 <_printf_i> - 8014d76: e7eb b.n 8014d50 <_svfiprintf_r+0x1c0> - 8014d78: 08018b84 .word 0x08018b84 - 8014d7c: 08018b8e .word 0x08018b8e - 8014d80: 08011bfd .word 0x08011bfd - 8014d84: 08014add .word 0x08014add - 8014d88: 08018b8a .word 0x08018b8a - -08014d8c <__sflush_r>: - 8014d8c: 898a ldrh r2, [r1, #12] - 8014d8e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8014d92: 4605 mov r5, r0 - 8014d94: 0710 lsls r0, r2, #28 - 8014d96: 460c mov r4, r1 - 8014d98: d458 bmi.n 8014e4c <__sflush_r+0xc0> - 8014d9a: 684b ldr r3, [r1, #4] - 8014d9c: 2b00 cmp r3, #0 - 8014d9e: dc05 bgt.n 8014dac <__sflush_r+0x20> - 8014da0: 6c0b ldr r3, [r1, #64] ; 0x40 - 8014da2: 2b00 cmp r3, #0 - 8014da4: dc02 bgt.n 8014dac <__sflush_r+0x20> - 8014da6: 2000 movs r0, #0 - 8014da8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 8014dac: 6ae6 ldr r6, [r4, #44] ; 0x2c - 8014dae: 2e00 cmp r6, #0 - 8014db0: d0f9 beq.n 8014da6 <__sflush_r+0x1a> - 8014db2: 2300 movs r3, #0 - 8014db4: f412 5280 ands.w r2, r2, #4096 ; 0x1000 - 8014db8: 682f ldr r7, [r5, #0] - 8014dba: 6a21 ldr r1, [r4, #32] - 8014dbc: 602b str r3, [r5, #0] - 8014dbe: d032 beq.n 8014e26 <__sflush_r+0x9a> - 8014dc0: 6d60 ldr r0, [r4, #84] ; 0x54 - 8014dc2: 89a3 ldrh r3, [r4, #12] - 8014dc4: 075a lsls r2, r3, #29 - 8014dc6: d505 bpl.n 8014dd4 <__sflush_r+0x48> - 8014dc8: 6863 ldr r3, [r4, #4] - 8014dca: 1ac0 subs r0, r0, r3 - 8014dcc: 6b63 ldr r3, [r4, #52] ; 0x34 - 8014dce: b10b cbz r3, 8014dd4 <__sflush_r+0x48> - 8014dd0: 6c23 ldr r3, [r4, #64] ; 0x40 - 8014dd2: 1ac0 subs r0, r0, r3 - 8014dd4: 2300 movs r3, #0 - 8014dd6: 4602 mov r2, r0 - 8014dd8: 6ae6 ldr r6, [r4, #44] ; 0x2c - 8014dda: 6a21 ldr r1, [r4, #32] - 8014ddc: 4628 mov r0, r5 - 8014dde: 47b0 blx r6 - 8014de0: 1c43 adds r3, r0, #1 - 8014de2: 89a3 ldrh r3, [r4, #12] - 8014de4: d106 bne.n 8014df4 <__sflush_r+0x68> - 8014de6: 6829 ldr r1, [r5, #0] - 8014de8: 291d cmp r1, #29 - 8014dea: d82b bhi.n 8014e44 <__sflush_r+0xb8> - 8014dec: 4a29 ldr r2, [pc, #164] ; (8014e94 <__sflush_r+0x108>) - 8014dee: 410a asrs r2, r1 - 8014df0: 07d6 lsls r6, r2, #31 - 8014df2: d427 bmi.n 8014e44 <__sflush_r+0xb8> - 8014df4: 2200 movs r2, #0 - 8014df6: 6062 str r2, [r4, #4] - 8014df8: 04d9 lsls r1, r3, #19 - 8014dfa: 6922 ldr r2, [r4, #16] - 8014dfc: 6022 str r2, [r4, #0] - 8014dfe: d504 bpl.n 8014e0a <__sflush_r+0x7e> - 8014e00: 1c42 adds r2, r0, #1 - 8014e02: d101 bne.n 8014e08 <__sflush_r+0x7c> - 8014e04: 682b ldr r3, [r5, #0] - 8014e06: b903 cbnz r3, 8014e0a <__sflush_r+0x7e> - 8014e08: 6560 str r0, [r4, #84] ; 0x54 - 8014e0a: 6b61 ldr r1, [r4, #52] ; 0x34 - 8014e0c: 602f str r7, [r5, #0] - 8014e0e: 2900 cmp r1, #0 - 8014e10: d0c9 beq.n 8014da6 <__sflush_r+0x1a> - 8014e12: f104 0344 add.w r3, r4, #68 ; 0x44 - 8014e16: 4299 cmp r1, r3 - 8014e18: d002 beq.n 8014e20 <__sflush_r+0x94> - 8014e1a: 4628 mov r0, r5 - 8014e1c: f7fe fdee bl 80139fc <_free_r> - 8014e20: 2000 movs r0, #0 - 8014e22: 6360 str r0, [r4, #52] ; 0x34 - 8014e24: e7c0 b.n 8014da8 <__sflush_r+0x1c> - 8014e26: 2301 movs r3, #1 - 8014e28: 4628 mov r0, r5 - 8014e2a: 47b0 blx r6 - 8014e2c: 1c41 adds r1, r0, #1 - 8014e2e: d1c8 bne.n 8014dc2 <__sflush_r+0x36> - 8014e30: 682b ldr r3, [r5, #0] - 8014e32: 2b00 cmp r3, #0 - 8014e34: d0c5 beq.n 8014dc2 <__sflush_r+0x36> - 8014e36: 2b1d cmp r3, #29 - 8014e38: d001 beq.n 8014e3e <__sflush_r+0xb2> - 8014e3a: 2b16 cmp r3, #22 - 8014e3c: d101 bne.n 8014e42 <__sflush_r+0xb6> - 8014e3e: 602f str r7, [r5, #0] - 8014e40: e7b1 b.n 8014da6 <__sflush_r+0x1a> - 8014e42: 89a3 ldrh r3, [r4, #12] - 8014e44: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8014e48: 81a3 strh r3, [r4, #12] - 8014e4a: e7ad b.n 8014da8 <__sflush_r+0x1c> - 8014e4c: 690f ldr r7, [r1, #16] - 8014e4e: 2f00 cmp r7, #0 - 8014e50: d0a9 beq.n 8014da6 <__sflush_r+0x1a> - 8014e52: 0793 lsls r3, r2, #30 - 8014e54: 680e ldr r6, [r1, #0] - 8014e56: bf08 it eq - 8014e58: 694b ldreq r3, [r1, #20] - 8014e5a: 600f str r7, [r1, #0] - 8014e5c: bf18 it ne - 8014e5e: 2300 movne r3, #0 - 8014e60: eba6 0807 sub.w r8, r6, r7 - 8014e64: 608b str r3, [r1, #8] - 8014e66: f1b8 0f00 cmp.w r8, #0 - 8014e6a: dd9c ble.n 8014da6 <__sflush_r+0x1a> - 8014e6c: 6a21 ldr r1, [r4, #32] - 8014e6e: 6aa6 ldr r6, [r4, #40] ; 0x28 - 8014e70: 4643 mov r3, r8 - 8014e72: 463a mov r2, r7 - 8014e74: 4628 mov r0, r5 - 8014e76: 47b0 blx r6 - 8014e78: 2800 cmp r0, #0 - 8014e7a: dc06 bgt.n 8014e8a <__sflush_r+0xfe> - 8014e7c: 89a3 ldrh r3, [r4, #12] - 8014e7e: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8014e82: 81a3 strh r3, [r4, #12] - 8014e84: f04f 30ff mov.w r0, #4294967295 - 8014e88: e78e b.n 8014da8 <__sflush_r+0x1c> - 8014e8a: 4407 add r7, r0 - 8014e8c: eba8 0800 sub.w r8, r8, r0 - 8014e90: e7e9 b.n 8014e66 <__sflush_r+0xda> - 8014e92: bf00 nop - 8014e94: dfbffffe .word 0xdfbffffe - -08014e98 <_fflush_r>: - 8014e98: b538 push {r3, r4, r5, lr} - 8014e9a: 690b ldr r3, [r1, #16] - 8014e9c: 4605 mov r5, r0 - 8014e9e: 460c mov r4, r1 - 8014ea0: b913 cbnz r3, 8014ea8 <_fflush_r+0x10> - 8014ea2: 2500 movs r5, #0 - 8014ea4: 4628 mov r0, r5 - 8014ea6: bd38 pop {r3, r4, r5, pc} - 8014ea8: b118 cbz r0, 8014eb2 <_fflush_r+0x1a> - 8014eaa: 6a03 ldr r3, [r0, #32] - 8014eac: b90b cbnz r3, 8014eb2 <_fflush_r+0x1a> - 8014eae: f7fd fd07 bl 80128c0 <__sinit> - 8014eb2: f9b4 300c ldrsh.w r3, [r4, #12] - 8014eb6: 2b00 cmp r3, #0 - 8014eb8: d0f3 beq.n 8014ea2 <_fflush_r+0xa> - 8014eba: 6e62 ldr r2, [r4, #100] ; 0x64 - 8014ebc: 07d0 lsls r0, r2, #31 - 8014ebe: d404 bmi.n 8014eca <_fflush_r+0x32> - 8014ec0: 0599 lsls r1, r3, #22 - 8014ec2: d402 bmi.n 8014eca <_fflush_r+0x32> - 8014ec4: 6da0 ldr r0, [r4, #88] ; 0x58 - 8014ec6: f7fd feda bl 8012c7e <__retarget_lock_acquire_recursive> - 8014eca: 4628 mov r0, r5 - 8014ecc: 4621 mov r1, r4 - 8014ece: f7ff ff5d bl 8014d8c <__sflush_r> - 8014ed2: 6e63 ldr r3, [r4, #100] ; 0x64 - 8014ed4: 07da lsls r2, r3, #31 - 8014ed6: 4605 mov r5, r0 - 8014ed8: d4e4 bmi.n 8014ea4 <_fflush_r+0xc> - 8014eda: 89a3 ldrh r3, [r4, #12] - 8014edc: 059b lsls r3, r3, #22 - 8014ede: d4e1 bmi.n 8014ea4 <_fflush_r+0xc> - 8014ee0: 6da0 ldr r0, [r4, #88] ; 0x58 - 8014ee2: f7fd fecd bl 8012c80 <__retarget_lock_release_recursive> - 8014ee6: e7dd b.n 8014ea4 <_fflush_r+0xc> - -08014ee8 : - 8014ee8: b40e push {r1, r2, r3} - 8014eea: b503 push {r0, r1, lr} - 8014eec: 4601 mov r1, r0 - 8014eee: ab03 add r3, sp, #12 - 8014ef0: 4805 ldr r0, [pc, #20] ; (8014f08 ) - 8014ef2: f853 2b04 ldr.w r2, [r3], #4 - 8014ef6: 6800 ldr r0, [r0, #0] - 8014ef8: 9301 str r3, [sp, #4] - 8014efa: f000 f897 bl 801502c <_vfiprintf_r> - 8014efe: b002 add sp, #8 - 8014f00: f85d eb04 ldr.w lr, [sp], #4 - 8014f04: b003 add sp, #12 - 8014f06: 4770 bx lr - 8014f08: 20000310 .word 0x20000310 - -08014f0c : - 8014f0c: 4288 cmp r0, r1 - 8014f0e: b510 push {r4, lr} - 8014f10: eb01 0402 add.w r4, r1, r2 - 8014f14: d902 bls.n 8014f1c - 8014f16: 4284 cmp r4, r0 - 8014f18: 4623 mov r3, r4 - 8014f1a: d807 bhi.n 8014f2c - 8014f1c: 1e43 subs r3, r0, #1 - 8014f1e: 42a1 cmp r1, r4 - 8014f20: d008 beq.n 8014f34 - 8014f22: f811 2b01 ldrb.w r2, [r1], #1 - 8014f26: f803 2f01 strb.w r2, [r3, #1]! - 8014f2a: e7f8 b.n 8014f1e - 8014f2c: 4402 add r2, r0 - 8014f2e: 4601 mov r1, r0 - 8014f30: 428a cmp r2, r1 - 8014f32: d100 bne.n 8014f36 - 8014f34: bd10 pop {r4, pc} - 8014f36: f813 4d01 ldrb.w r4, [r3, #-1]! - 8014f3a: f802 4d01 strb.w r4, [r2, #-1]! - 8014f3e: e7f7 b.n 8014f30 - -08014f40 : - 8014f40: b508 push {r3, lr} - 8014f42: 2006 movs r0, #6 - 8014f44: f000 fa4a bl 80153dc - 8014f48: 2001 movs r0, #1 - 8014f4a: f7ef f9e5 bl 8004318 <_exit> - -08014f4e <_calloc_r>: - 8014f4e: b537 push {r0, r1, r2, r4, r5, lr} - 8014f50: fba1 2402 umull r2, r4, r1, r2 - 8014f54: b94c cbnz r4, 8014f6a <_calloc_r+0x1c> - 8014f56: 4611 mov r1, r2 - 8014f58: 9201 str r2, [sp, #4] - 8014f5a: f7fb fe1b bl 8010b94 <_malloc_r> - 8014f5e: 9a01 ldr r2, [sp, #4] - 8014f60: 4605 mov r5, r0 - 8014f62: b930 cbnz r0, 8014f72 <_calloc_r+0x24> - 8014f64: 4628 mov r0, r5 - 8014f66: b003 add sp, #12 - 8014f68: bd30 pop {r4, r5, pc} - 8014f6a: 220c movs r2, #12 - 8014f6c: 6002 str r2, [r0, #0] - 8014f6e: 2500 movs r5, #0 - 8014f70: e7f8 b.n 8014f64 <_calloc_r+0x16> - 8014f72: 4621 mov r1, r4 - 8014f74: f7fd fd71 bl 8012a5a - 8014f78: e7f4 b.n 8014f64 <_calloc_r+0x16> - -08014f7a <_realloc_r>: - 8014f7a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8014f7e: 4680 mov r8, r0 - 8014f80: 4614 mov r4, r2 - 8014f82: 460e mov r6, r1 - 8014f84: b921 cbnz r1, 8014f90 <_realloc_r+0x16> - 8014f86: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 8014f8a: 4611 mov r1, r2 - 8014f8c: f7fb be02 b.w 8010b94 <_malloc_r> - 8014f90: b92a cbnz r2, 8014f9e <_realloc_r+0x24> - 8014f92: f7fe fd33 bl 80139fc <_free_r> - 8014f96: 4625 mov r5, r4 - 8014f98: 4628 mov r0, r5 - 8014f9a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 8014f9e: f000 fa39 bl 8015414 <_malloc_usable_size_r> - 8014fa2: 4284 cmp r4, r0 - 8014fa4: 4607 mov r7, r0 - 8014fa6: d802 bhi.n 8014fae <_realloc_r+0x34> - 8014fa8: ebb4 0f50 cmp.w r4, r0, lsr #1 - 8014fac: d812 bhi.n 8014fd4 <_realloc_r+0x5a> - 8014fae: 4621 mov r1, r4 - 8014fb0: 4640 mov r0, r8 - 8014fb2: f7fb fdef bl 8010b94 <_malloc_r> - 8014fb6: 4605 mov r5, r0 - 8014fb8: 2800 cmp r0, #0 - 8014fba: d0ed beq.n 8014f98 <_realloc_r+0x1e> - 8014fbc: 42bc cmp r4, r7 - 8014fbe: 4622 mov r2, r4 - 8014fc0: 4631 mov r1, r6 - 8014fc2: bf28 it cs - 8014fc4: 463a movcs r2, r7 - 8014fc6: f7fd fe64 bl 8012c92 - 8014fca: 4631 mov r1, r6 - 8014fcc: 4640 mov r0, r8 - 8014fce: f7fe fd15 bl 80139fc <_free_r> - 8014fd2: e7e1 b.n 8014f98 <_realloc_r+0x1e> - 8014fd4: 4635 mov r5, r6 - 8014fd6: e7df b.n 8014f98 <_realloc_r+0x1e> - -08014fd8 <__sfputc_r>: - 8014fd8: 6893 ldr r3, [r2, #8] - 8014fda: 3b01 subs r3, #1 - 8014fdc: 2b00 cmp r3, #0 - 8014fde: b410 push {r4} - 8014fe0: 6093 str r3, [r2, #8] - 8014fe2: da08 bge.n 8014ff6 <__sfputc_r+0x1e> - 8014fe4: 6994 ldr r4, [r2, #24] - 8014fe6: 42a3 cmp r3, r4 - 8014fe8: db01 blt.n 8014fee <__sfputc_r+0x16> - 8014fea: 290a cmp r1, #10 - 8014fec: d103 bne.n 8014ff6 <__sfputc_r+0x1e> - 8014fee: f85d 4b04 ldr.w r4, [sp], #4 - 8014ff2: f000 b935 b.w 8015260 <__swbuf_r> - 8014ff6: 6813 ldr r3, [r2, #0] - 8014ff8: 1c58 adds r0, r3, #1 - 8014ffa: 6010 str r0, [r2, #0] - 8014ffc: 7019 strb r1, [r3, #0] - 8014ffe: 4608 mov r0, r1 - 8015000: f85d 4b04 ldr.w r4, [sp], #4 - 8015004: 4770 bx lr - -08015006 <__sfputs_r>: - 8015006: b5f8 push {r3, r4, r5, r6, r7, lr} - 8015008: 4606 mov r6, r0 - 801500a: 460f mov r7, r1 - 801500c: 4614 mov r4, r2 - 801500e: 18d5 adds r5, r2, r3 - 8015010: 42ac cmp r4, r5 - 8015012: d101 bne.n 8015018 <__sfputs_r+0x12> - 8015014: 2000 movs r0, #0 - 8015016: e007 b.n 8015028 <__sfputs_r+0x22> - 8015018: f814 1b01 ldrb.w r1, [r4], #1 - 801501c: 463a mov r2, r7 - 801501e: 4630 mov r0, r6 - 8015020: f7ff ffda bl 8014fd8 <__sfputc_r> - 8015024: 1c43 adds r3, r0, #1 - 8015026: d1f3 bne.n 8015010 <__sfputs_r+0xa> - 8015028: bdf8 pop {r3, r4, r5, r6, r7, pc} +08016898 <__i2b>: + 8016898: b510 push {r4, lr} + 801689a: 460c mov r4, r1 + 801689c: 2101 movs r1, #1 + 801689e: f7ff febb bl 8016618 <_Balloc> + 80168a2: 4602 mov r2, r0 + 80168a4: b928 cbnz r0, 80168b2 <__i2b+0x1a> + 80168a6: 4b05 ldr r3, [pc, #20] ; (80168bc <__i2b+0x24>) + 80168a8: 4805 ldr r0, [pc, #20] ; (80168c0 <__i2b+0x28>) + 80168aa: f240 1145 movw r1, #325 ; 0x145 + 80168ae: f7fe fc65 bl 801517c <__assert_func> + 80168b2: 2301 movs r3, #1 + 80168b4: 6144 str r4, [r0, #20] + 80168b6: 6103 str r3, [r0, #16] + 80168b8: bd10 pop {r4, pc} + 80168ba: bf00 nop + 80168bc: 0801ae94 .word 0x0801ae94 + 80168c0: 0801af05 .word 0x0801af05 + +080168c4 <__multiply>: + 80168c4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80168c8: 4691 mov r9, r2 + 80168ca: 690a ldr r2, [r1, #16] + 80168cc: f8d9 3010 ldr.w r3, [r9, #16] + 80168d0: 429a cmp r2, r3 + 80168d2: bfb8 it lt + 80168d4: 460b movlt r3, r1 + 80168d6: 460c mov r4, r1 + 80168d8: bfbc itt lt + 80168da: 464c movlt r4, r9 + 80168dc: 4699 movlt r9, r3 + 80168de: 6927 ldr r7, [r4, #16] + 80168e0: f8d9 a010 ldr.w sl, [r9, #16] + 80168e4: 68a3 ldr r3, [r4, #8] + 80168e6: 6861 ldr r1, [r4, #4] + 80168e8: eb07 060a add.w r6, r7, sl + 80168ec: 42b3 cmp r3, r6 + 80168ee: b085 sub sp, #20 + 80168f0: bfb8 it lt + 80168f2: 3101 addlt r1, #1 + 80168f4: f7ff fe90 bl 8016618 <_Balloc> + 80168f8: b930 cbnz r0, 8016908 <__multiply+0x44> + 80168fa: 4602 mov r2, r0 + 80168fc: 4b44 ldr r3, [pc, #272] ; (8016a10 <__multiply+0x14c>) + 80168fe: 4845 ldr r0, [pc, #276] ; (8016a14 <__multiply+0x150>) + 8016900: f44f 71b1 mov.w r1, #354 ; 0x162 + 8016904: f7fe fc3a bl 801517c <__assert_func> + 8016908: f100 0514 add.w r5, r0, #20 + 801690c: eb05 0886 add.w r8, r5, r6, lsl #2 + 8016910: 462b mov r3, r5 + 8016912: 2200 movs r2, #0 + 8016914: 4543 cmp r3, r8 + 8016916: d321 bcc.n 801695c <__multiply+0x98> + 8016918: f104 0314 add.w r3, r4, #20 + 801691c: eb03 0787 add.w r7, r3, r7, lsl #2 + 8016920: f109 0314 add.w r3, r9, #20 + 8016924: eb03 028a add.w r2, r3, sl, lsl #2 + 8016928: 9202 str r2, [sp, #8] + 801692a: 1b3a subs r2, r7, r4 + 801692c: 3a15 subs r2, #21 + 801692e: f022 0203 bic.w r2, r2, #3 + 8016932: 3204 adds r2, #4 + 8016934: f104 0115 add.w r1, r4, #21 + 8016938: 428f cmp r7, r1 + 801693a: bf38 it cc + 801693c: 2204 movcc r2, #4 + 801693e: 9201 str r2, [sp, #4] + 8016940: 9a02 ldr r2, [sp, #8] + 8016942: 9303 str r3, [sp, #12] + 8016944: 429a cmp r2, r3 + 8016946: d80c bhi.n 8016962 <__multiply+0x9e> + 8016948: 2e00 cmp r6, #0 + 801694a: dd03 ble.n 8016954 <__multiply+0x90> + 801694c: f858 3d04 ldr.w r3, [r8, #-4]! + 8016950: 2b00 cmp r3, #0 + 8016952: d05b beq.n 8016a0c <__multiply+0x148> + 8016954: 6106 str r6, [r0, #16] + 8016956: b005 add sp, #20 + 8016958: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801695c: f843 2b04 str.w r2, [r3], #4 + 8016960: e7d8 b.n 8016914 <__multiply+0x50> + 8016962: f8b3 a000 ldrh.w sl, [r3] + 8016966: f1ba 0f00 cmp.w sl, #0 + 801696a: d024 beq.n 80169b6 <__multiply+0xf2> + 801696c: f104 0e14 add.w lr, r4, #20 + 8016970: 46a9 mov r9, r5 + 8016972: f04f 0c00 mov.w ip, #0 + 8016976: f85e 2b04 ldr.w r2, [lr], #4 + 801697a: f8d9 1000 ldr.w r1, [r9] + 801697e: fa1f fb82 uxth.w fp, r2 + 8016982: b289 uxth r1, r1 + 8016984: fb0a 110b mla r1, sl, fp, r1 + 8016988: ea4f 4b12 mov.w fp, r2, lsr #16 + 801698c: f8d9 2000 ldr.w r2, [r9] + 8016990: 4461 add r1, ip + 8016992: ea4f 4c12 mov.w ip, r2, lsr #16 + 8016996: fb0a c20b mla r2, sl, fp, ip + 801699a: eb02 4211 add.w r2, r2, r1, lsr #16 + 801699e: b289 uxth r1, r1 + 80169a0: ea41 4102 orr.w r1, r1, r2, lsl #16 + 80169a4: 4577 cmp r7, lr + 80169a6: f849 1b04 str.w r1, [r9], #4 + 80169aa: ea4f 4c12 mov.w ip, r2, lsr #16 + 80169ae: d8e2 bhi.n 8016976 <__multiply+0xb2> + 80169b0: 9a01 ldr r2, [sp, #4] + 80169b2: f845 c002 str.w ip, [r5, r2] + 80169b6: 9a03 ldr r2, [sp, #12] + 80169b8: f8b2 9002 ldrh.w r9, [r2, #2] + 80169bc: 3304 adds r3, #4 + 80169be: f1b9 0f00 cmp.w r9, #0 + 80169c2: d021 beq.n 8016a08 <__multiply+0x144> + 80169c4: 6829 ldr r1, [r5, #0] + 80169c6: f104 0c14 add.w ip, r4, #20 + 80169ca: 46ae mov lr, r5 + 80169cc: f04f 0a00 mov.w sl, #0 + 80169d0: f8bc b000 ldrh.w fp, [ip] + 80169d4: f8be 2002 ldrh.w r2, [lr, #2] + 80169d8: fb09 220b mla r2, r9, fp, r2 + 80169dc: 4452 add r2, sl + 80169de: b289 uxth r1, r1 + 80169e0: ea41 4102 orr.w r1, r1, r2, lsl #16 + 80169e4: f84e 1b04 str.w r1, [lr], #4 + 80169e8: f85c 1b04 ldr.w r1, [ip], #4 + 80169ec: ea4f 4a11 mov.w sl, r1, lsr #16 + 80169f0: f8be 1000 ldrh.w r1, [lr] + 80169f4: fb09 110a mla r1, r9, sl, r1 + 80169f8: eb01 4112 add.w r1, r1, r2, lsr #16 + 80169fc: 4567 cmp r7, ip + 80169fe: ea4f 4a11 mov.w sl, r1, lsr #16 + 8016a02: d8e5 bhi.n 80169d0 <__multiply+0x10c> + 8016a04: 9a01 ldr r2, [sp, #4] + 8016a06: 50a9 str r1, [r5, r2] + 8016a08: 3504 adds r5, #4 + 8016a0a: e799 b.n 8016940 <__multiply+0x7c> + 8016a0c: 3e01 subs r6, #1 + 8016a0e: e79b b.n 8016948 <__multiply+0x84> + 8016a10: 0801ae94 .word 0x0801ae94 + 8016a14: 0801af05 .word 0x0801af05 + +08016a18 <__pow5mult>: + 8016a18: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8016a1c: 4615 mov r5, r2 + 8016a1e: f012 0203 ands.w r2, r2, #3 + 8016a22: 4606 mov r6, r0 + 8016a24: 460f mov r7, r1 + 8016a26: d007 beq.n 8016a38 <__pow5mult+0x20> + 8016a28: 4c25 ldr r4, [pc, #148] ; (8016ac0 <__pow5mult+0xa8>) + 8016a2a: 3a01 subs r2, #1 + 8016a2c: 2300 movs r3, #0 + 8016a2e: f854 2022 ldr.w r2, [r4, r2, lsl #2] + 8016a32: f7ff fe53 bl 80166dc <__multadd> + 8016a36: 4607 mov r7, r0 + 8016a38: 10ad asrs r5, r5, #2 + 8016a3a: d03d beq.n 8016ab8 <__pow5mult+0xa0> + 8016a3c: 69f4 ldr r4, [r6, #28] + 8016a3e: b97c cbnz r4, 8016a60 <__pow5mult+0x48> + 8016a40: 2010 movs r0, #16 + 8016a42: f7fc facf bl 8012fe4 + 8016a46: 4602 mov r2, r0 + 8016a48: 61f0 str r0, [r6, #28] + 8016a4a: b928 cbnz r0, 8016a58 <__pow5mult+0x40> + 8016a4c: 4b1d ldr r3, [pc, #116] ; (8016ac4 <__pow5mult+0xac>) + 8016a4e: 481e ldr r0, [pc, #120] ; (8016ac8 <__pow5mult+0xb0>) + 8016a50: f240 11b3 movw r1, #435 ; 0x1b3 + 8016a54: f7fe fb92 bl 801517c <__assert_func> + 8016a58: e9c0 4401 strd r4, r4, [r0, #4] + 8016a5c: 6004 str r4, [r0, #0] + 8016a5e: 60c4 str r4, [r0, #12] + 8016a60: f8d6 801c ldr.w r8, [r6, #28] + 8016a64: f8d8 4008 ldr.w r4, [r8, #8] + 8016a68: b94c cbnz r4, 8016a7e <__pow5mult+0x66> + 8016a6a: f240 2171 movw r1, #625 ; 0x271 + 8016a6e: 4630 mov r0, r6 + 8016a70: f7ff ff12 bl 8016898 <__i2b> + 8016a74: 2300 movs r3, #0 + 8016a76: f8c8 0008 str.w r0, [r8, #8] + 8016a7a: 4604 mov r4, r0 + 8016a7c: 6003 str r3, [r0, #0] + 8016a7e: f04f 0900 mov.w r9, #0 + 8016a82: 07eb lsls r3, r5, #31 + 8016a84: d50a bpl.n 8016a9c <__pow5mult+0x84> + 8016a86: 4639 mov r1, r7 + 8016a88: 4622 mov r2, r4 + 8016a8a: 4630 mov r0, r6 + 8016a8c: f7ff ff1a bl 80168c4 <__multiply> + 8016a90: 4639 mov r1, r7 + 8016a92: 4680 mov r8, r0 + 8016a94: 4630 mov r0, r6 + 8016a96: f7ff fdff bl 8016698 <_Bfree> + 8016a9a: 4647 mov r7, r8 + 8016a9c: 106d asrs r5, r5, #1 + 8016a9e: d00b beq.n 8016ab8 <__pow5mult+0xa0> + 8016aa0: 6820 ldr r0, [r4, #0] + 8016aa2: b938 cbnz r0, 8016ab4 <__pow5mult+0x9c> + 8016aa4: 4622 mov r2, r4 + 8016aa6: 4621 mov r1, r4 + 8016aa8: 4630 mov r0, r6 + 8016aaa: f7ff ff0b bl 80168c4 <__multiply> + 8016aae: 6020 str r0, [r4, #0] + 8016ab0: f8c0 9000 str.w r9, [r0] + 8016ab4: 4604 mov r4, r0 + 8016ab6: e7e4 b.n 8016a82 <__pow5mult+0x6a> + 8016ab8: 4638 mov r0, r7 + 8016aba: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8016abe: bf00 nop + 8016ac0: 0801b050 .word 0x0801b050 + 8016ac4: 0801ad7a .word 0x0801ad7a + 8016ac8: 0801af05 .word 0x0801af05 + +08016acc <__lshift>: + 8016acc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8016ad0: 460c mov r4, r1 + 8016ad2: 6849 ldr r1, [r1, #4] + 8016ad4: 6923 ldr r3, [r4, #16] + 8016ad6: eb03 1862 add.w r8, r3, r2, asr #5 + 8016ada: 68a3 ldr r3, [r4, #8] + 8016adc: 4607 mov r7, r0 + 8016ade: 4691 mov r9, r2 + 8016ae0: ea4f 1a62 mov.w sl, r2, asr #5 + 8016ae4: f108 0601 add.w r6, r8, #1 + 8016ae8: 42b3 cmp r3, r6 + 8016aea: db0b blt.n 8016b04 <__lshift+0x38> + 8016aec: 4638 mov r0, r7 + 8016aee: f7ff fd93 bl 8016618 <_Balloc> + 8016af2: 4605 mov r5, r0 + 8016af4: b948 cbnz r0, 8016b0a <__lshift+0x3e> + 8016af6: 4602 mov r2, r0 + 8016af8: 4b28 ldr r3, [pc, #160] ; (8016b9c <__lshift+0xd0>) + 8016afa: 4829 ldr r0, [pc, #164] ; (8016ba0 <__lshift+0xd4>) + 8016afc: f44f 71ef mov.w r1, #478 ; 0x1de + 8016b00: f7fe fb3c bl 801517c <__assert_func> + 8016b04: 3101 adds r1, #1 + 8016b06: 005b lsls r3, r3, #1 + 8016b08: e7ee b.n 8016ae8 <__lshift+0x1c> + 8016b0a: 2300 movs r3, #0 + 8016b0c: f100 0114 add.w r1, r0, #20 + 8016b10: f100 0210 add.w r2, r0, #16 + 8016b14: 4618 mov r0, r3 + 8016b16: 4553 cmp r3, sl + 8016b18: db33 blt.n 8016b82 <__lshift+0xb6> + 8016b1a: 6920 ldr r0, [r4, #16] + 8016b1c: ea2a 7aea bic.w sl, sl, sl, asr #31 + 8016b20: f104 0314 add.w r3, r4, #20 + 8016b24: f019 091f ands.w r9, r9, #31 + 8016b28: eb01 018a add.w r1, r1, sl, lsl #2 + 8016b2c: eb03 0c80 add.w ip, r3, r0, lsl #2 + 8016b30: d02b beq.n 8016b8a <__lshift+0xbe> + 8016b32: f1c9 0e20 rsb lr, r9, #32 + 8016b36: 468a mov sl, r1 + 8016b38: 2200 movs r2, #0 + 8016b3a: 6818 ldr r0, [r3, #0] + 8016b3c: fa00 f009 lsl.w r0, r0, r9 + 8016b40: 4310 orrs r0, r2 + 8016b42: f84a 0b04 str.w r0, [sl], #4 + 8016b46: f853 2b04 ldr.w r2, [r3], #4 + 8016b4a: 459c cmp ip, r3 + 8016b4c: fa22 f20e lsr.w r2, r2, lr + 8016b50: d8f3 bhi.n 8016b3a <__lshift+0x6e> + 8016b52: ebac 0304 sub.w r3, ip, r4 + 8016b56: 3b15 subs r3, #21 + 8016b58: f023 0303 bic.w r3, r3, #3 + 8016b5c: 3304 adds r3, #4 + 8016b5e: f104 0015 add.w r0, r4, #21 + 8016b62: 4584 cmp ip, r0 + 8016b64: bf38 it cc + 8016b66: 2304 movcc r3, #4 + 8016b68: 50ca str r2, [r1, r3] + 8016b6a: b10a cbz r2, 8016b70 <__lshift+0xa4> + 8016b6c: f108 0602 add.w r6, r8, #2 + 8016b70: 3e01 subs r6, #1 + 8016b72: 4638 mov r0, r7 + 8016b74: 612e str r6, [r5, #16] + 8016b76: 4621 mov r1, r4 + 8016b78: f7ff fd8e bl 8016698 <_Bfree> + 8016b7c: 4628 mov r0, r5 + 8016b7e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8016b82: f842 0f04 str.w r0, [r2, #4]! + 8016b86: 3301 adds r3, #1 + 8016b88: e7c5 b.n 8016b16 <__lshift+0x4a> + 8016b8a: 3904 subs r1, #4 + 8016b8c: f853 2b04 ldr.w r2, [r3], #4 + 8016b90: f841 2f04 str.w r2, [r1, #4]! + 8016b94: 459c cmp ip, r3 + 8016b96: d8f9 bhi.n 8016b8c <__lshift+0xc0> + 8016b98: e7ea b.n 8016b70 <__lshift+0xa4> + 8016b9a: bf00 nop + 8016b9c: 0801ae94 .word 0x0801ae94 + 8016ba0: 0801af05 .word 0x0801af05 + +08016ba4 <__mcmp>: + 8016ba4: b530 push {r4, r5, lr} + 8016ba6: 6902 ldr r2, [r0, #16] + 8016ba8: 690c ldr r4, [r1, #16] + 8016baa: 1b12 subs r2, r2, r4 + 8016bac: d10e bne.n 8016bcc <__mcmp+0x28> + 8016bae: f100 0314 add.w r3, r0, #20 + 8016bb2: 3114 adds r1, #20 + 8016bb4: eb03 0084 add.w r0, r3, r4, lsl #2 + 8016bb8: eb01 0184 add.w r1, r1, r4, lsl #2 + 8016bbc: f850 5d04 ldr.w r5, [r0, #-4]! + 8016bc0: f851 4d04 ldr.w r4, [r1, #-4]! + 8016bc4: 42a5 cmp r5, r4 + 8016bc6: d003 beq.n 8016bd0 <__mcmp+0x2c> + 8016bc8: d305 bcc.n 8016bd6 <__mcmp+0x32> + 8016bca: 2201 movs r2, #1 + 8016bcc: 4610 mov r0, r2 + 8016bce: bd30 pop {r4, r5, pc} + 8016bd0: 4283 cmp r3, r0 + 8016bd2: d3f3 bcc.n 8016bbc <__mcmp+0x18> + 8016bd4: e7fa b.n 8016bcc <__mcmp+0x28> + 8016bd6: f04f 32ff mov.w r2, #4294967295 + 8016bda: e7f7 b.n 8016bcc <__mcmp+0x28> + +08016bdc <__mdiff>: + 8016bdc: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8016be0: 460c mov r4, r1 + 8016be2: 4606 mov r6, r0 + 8016be4: 4611 mov r1, r2 + 8016be6: 4620 mov r0, r4 + 8016be8: 4690 mov r8, r2 + 8016bea: f7ff ffdb bl 8016ba4 <__mcmp> + 8016bee: 1e05 subs r5, r0, #0 + 8016bf0: d110 bne.n 8016c14 <__mdiff+0x38> + 8016bf2: 4629 mov r1, r5 + 8016bf4: 4630 mov r0, r6 + 8016bf6: f7ff fd0f bl 8016618 <_Balloc> + 8016bfa: b930 cbnz r0, 8016c0a <__mdiff+0x2e> + 8016bfc: 4b3a ldr r3, [pc, #232] ; (8016ce8 <__mdiff+0x10c>) + 8016bfe: 4602 mov r2, r0 + 8016c00: f240 2137 movw r1, #567 ; 0x237 + 8016c04: 4839 ldr r0, [pc, #228] ; (8016cec <__mdiff+0x110>) + 8016c06: f7fe fab9 bl 801517c <__assert_func> + 8016c0a: 2301 movs r3, #1 + 8016c0c: e9c0 3504 strd r3, r5, [r0, #16] + 8016c10: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8016c14: bfa4 itt ge + 8016c16: 4643 movge r3, r8 + 8016c18: 46a0 movge r8, r4 + 8016c1a: 4630 mov r0, r6 + 8016c1c: f8d8 1004 ldr.w r1, [r8, #4] + 8016c20: bfa6 itte ge + 8016c22: 461c movge r4, r3 + 8016c24: 2500 movge r5, #0 + 8016c26: 2501 movlt r5, #1 + 8016c28: f7ff fcf6 bl 8016618 <_Balloc> + 8016c2c: b920 cbnz r0, 8016c38 <__mdiff+0x5c> + 8016c2e: 4b2e ldr r3, [pc, #184] ; (8016ce8 <__mdiff+0x10c>) + 8016c30: 4602 mov r2, r0 + 8016c32: f240 2145 movw r1, #581 ; 0x245 + 8016c36: e7e5 b.n 8016c04 <__mdiff+0x28> + 8016c38: f8d8 7010 ldr.w r7, [r8, #16] + 8016c3c: 6926 ldr r6, [r4, #16] + 8016c3e: 60c5 str r5, [r0, #12] + 8016c40: f104 0914 add.w r9, r4, #20 + 8016c44: f108 0514 add.w r5, r8, #20 + 8016c48: f100 0e14 add.w lr, r0, #20 + 8016c4c: eb05 0c87 add.w ip, r5, r7, lsl #2 + 8016c50: eb09 0686 add.w r6, r9, r6, lsl #2 + 8016c54: f108 0210 add.w r2, r8, #16 + 8016c58: 46f2 mov sl, lr + 8016c5a: 2100 movs r1, #0 + 8016c5c: f859 3b04 ldr.w r3, [r9], #4 + 8016c60: f852 bf04 ldr.w fp, [r2, #4]! + 8016c64: fa11 f88b uxtah r8, r1, fp + 8016c68: b299 uxth r1, r3 + 8016c6a: 0c1b lsrs r3, r3, #16 + 8016c6c: eba8 0801 sub.w r8, r8, r1 + 8016c70: ebc3 431b rsb r3, r3, fp, lsr #16 + 8016c74: eb03 4328 add.w r3, r3, r8, asr #16 + 8016c78: fa1f f888 uxth.w r8, r8 + 8016c7c: 1419 asrs r1, r3, #16 + 8016c7e: 454e cmp r6, r9 + 8016c80: ea48 4303 orr.w r3, r8, r3, lsl #16 + 8016c84: f84a 3b04 str.w r3, [sl], #4 + 8016c88: d8e8 bhi.n 8016c5c <__mdiff+0x80> + 8016c8a: 1b33 subs r3, r6, r4 + 8016c8c: 3b15 subs r3, #21 + 8016c8e: f023 0303 bic.w r3, r3, #3 + 8016c92: 3304 adds r3, #4 + 8016c94: 3415 adds r4, #21 + 8016c96: 42a6 cmp r6, r4 + 8016c98: bf38 it cc + 8016c9a: 2304 movcc r3, #4 + 8016c9c: 441d add r5, r3 + 8016c9e: 4473 add r3, lr + 8016ca0: 469e mov lr, r3 + 8016ca2: 462e mov r6, r5 + 8016ca4: 4566 cmp r6, ip + 8016ca6: d30e bcc.n 8016cc6 <__mdiff+0xea> + 8016ca8: f10c 0203 add.w r2, ip, #3 + 8016cac: 1b52 subs r2, r2, r5 + 8016cae: f022 0203 bic.w r2, r2, #3 + 8016cb2: 3d03 subs r5, #3 + 8016cb4: 45ac cmp ip, r5 + 8016cb6: bf38 it cc + 8016cb8: 2200 movcc r2, #0 + 8016cba: 4413 add r3, r2 + 8016cbc: f853 2d04 ldr.w r2, [r3, #-4]! + 8016cc0: b17a cbz r2, 8016ce2 <__mdiff+0x106> + 8016cc2: 6107 str r7, [r0, #16] + 8016cc4: e7a4 b.n 8016c10 <__mdiff+0x34> + 8016cc6: f856 8b04 ldr.w r8, [r6], #4 + 8016cca: fa11 f288 uxtah r2, r1, r8 + 8016cce: 1414 asrs r4, r2, #16 + 8016cd0: eb04 4418 add.w r4, r4, r8, lsr #16 + 8016cd4: b292 uxth r2, r2 + 8016cd6: ea42 4204 orr.w r2, r2, r4, lsl #16 + 8016cda: f84e 2b04 str.w r2, [lr], #4 + 8016cde: 1421 asrs r1, r4, #16 + 8016ce0: e7e0 b.n 8016ca4 <__mdiff+0xc8> + 8016ce2: 3f01 subs r7, #1 + 8016ce4: e7ea b.n 8016cbc <__mdiff+0xe0> + 8016ce6: bf00 nop + 8016ce8: 0801ae94 .word 0x0801ae94 + 8016cec: 0801af05 .word 0x0801af05 + +08016cf0 <__ulp>: + 8016cf0: b082 sub sp, #8 + 8016cf2: ed8d 0b00 vstr d0, [sp] + 8016cf6: 9a01 ldr r2, [sp, #4] + 8016cf8: 4b0f ldr r3, [pc, #60] ; (8016d38 <__ulp+0x48>) + 8016cfa: 4013 ands r3, r2 + 8016cfc: f1a3 7350 sub.w r3, r3, #54525952 ; 0x3400000 + 8016d00: 2b00 cmp r3, #0 + 8016d02: dc08 bgt.n 8016d16 <__ulp+0x26> + 8016d04: 425b negs r3, r3 + 8016d06: f1b3 7fa0 cmp.w r3, #20971520 ; 0x1400000 + 8016d0a: ea4f 5223 mov.w r2, r3, asr #20 + 8016d0e: da04 bge.n 8016d1a <__ulp+0x2a> + 8016d10: f44f 2300 mov.w r3, #524288 ; 0x80000 + 8016d14: 4113 asrs r3, r2 + 8016d16: 2200 movs r2, #0 + 8016d18: e008 b.n 8016d2c <__ulp+0x3c> + 8016d1a: f1a2 0314 sub.w r3, r2, #20 + 8016d1e: 2b1e cmp r3, #30 + 8016d20: bfda itte le + 8016d22: f04f 4200 movle.w r2, #2147483648 ; 0x80000000 + 8016d26: 40da lsrle r2, r3 + 8016d28: 2201 movgt r2, #1 + 8016d2a: 2300 movs r3, #0 + 8016d2c: 4619 mov r1, r3 + 8016d2e: 4610 mov r0, r2 + 8016d30: ec41 0b10 vmov d0, r0, r1 + 8016d34: b002 add sp, #8 + 8016d36: 4770 bx lr + 8016d38: 7ff00000 .word 0x7ff00000 + +08016d3c <__b2d>: + 8016d3c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8016d40: 6906 ldr r6, [r0, #16] + 8016d42: f100 0814 add.w r8, r0, #20 + 8016d46: eb08 0686 add.w r6, r8, r6, lsl #2 + 8016d4a: 1f37 subs r7, r6, #4 + 8016d4c: f856 2c04 ldr.w r2, [r6, #-4] + 8016d50: 4610 mov r0, r2 + 8016d52: f7ff fd53 bl 80167fc <__hi0bits> + 8016d56: f1c0 0320 rsb r3, r0, #32 + 8016d5a: 280a cmp r0, #10 + 8016d5c: 600b str r3, [r1, #0] + 8016d5e: 491b ldr r1, [pc, #108] ; (8016dcc <__b2d+0x90>) + 8016d60: dc15 bgt.n 8016d8e <__b2d+0x52> + 8016d62: f1c0 0c0b rsb ip, r0, #11 + 8016d66: fa22 f30c lsr.w r3, r2, ip + 8016d6a: 45b8 cmp r8, r7 + 8016d6c: ea43 0501 orr.w r5, r3, r1 + 8016d70: bf34 ite cc + 8016d72: f856 3c08 ldrcc.w r3, [r6, #-8] + 8016d76: 2300 movcs r3, #0 + 8016d78: 3015 adds r0, #21 + 8016d7a: fa02 f000 lsl.w r0, r2, r0 + 8016d7e: fa23 f30c lsr.w r3, r3, ip + 8016d82: 4303 orrs r3, r0 + 8016d84: 461c mov r4, r3 + 8016d86: ec45 4b10 vmov d0, r4, r5 + 8016d8a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8016d8e: 45b8 cmp r8, r7 + 8016d90: bf3a itte cc + 8016d92: f856 3c08 ldrcc.w r3, [r6, #-8] + 8016d96: f1a6 0708 subcc.w r7, r6, #8 + 8016d9a: 2300 movcs r3, #0 + 8016d9c: 380b subs r0, #11 + 8016d9e: d012 beq.n 8016dc6 <__b2d+0x8a> + 8016da0: f1c0 0120 rsb r1, r0, #32 + 8016da4: fa23 f401 lsr.w r4, r3, r1 + 8016da8: 4082 lsls r2, r0 + 8016daa: 4322 orrs r2, r4 + 8016dac: 4547 cmp r7, r8 + 8016dae: f042 557f orr.w r5, r2, #1069547520 ; 0x3fc00000 + 8016db2: bf8c ite hi + 8016db4: f857 2c04 ldrhi.w r2, [r7, #-4] + 8016db8: 2200 movls r2, #0 + 8016dba: 4083 lsls r3, r0 + 8016dbc: 40ca lsrs r2, r1 + 8016dbe: f445 1540 orr.w r5, r5, #3145728 ; 0x300000 + 8016dc2: 4313 orrs r3, r2 + 8016dc4: e7de b.n 8016d84 <__b2d+0x48> + 8016dc6: ea42 0501 orr.w r5, r2, r1 + 8016dca: e7db b.n 8016d84 <__b2d+0x48> + 8016dcc: 3ff00000 .word 0x3ff00000 + +08016dd0 <__d2b>: + 8016dd0: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + 8016dd4: 460f mov r7, r1 + 8016dd6: 2101 movs r1, #1 + 8016dd8: ec59 8b10 vmov r8, r9, d0 + 8016ddc: 4616 mov r6, r2 + 8016dde: f7ff fc1b bl 8016618 <_Balloc> + 8016de2: 4604 mov r4, r0 + 8016de4: b930 cbnz r0, 8016df4 <__d2b+0x24> + 8016de6: 4602 mov r2, r0 + 8016de8: 4b24 ldr r3, [pc, #144] ; (8016e7c <__d2b+0xac>) + 8016dea: 4825 ldr r0, [pc, #148] ; (8016e80 <__d2b+0xb0>) + 8016dec: f240 310f movw r1, #783 ; 0x30f + 8016df0: f7fe f9c4 bl 801517c <__assert_func> + 8016df4: f3c9 550a ubfx r5, r9, #20, #11 + 8016df8: f3c9 0313 ubfx r3, r9, #0, #20 + 8016dfc: bb2d cbnz r5, 8016e4a <__d2b+0x7a> + 8016dfe: 9301 str r3, [sp, #4] + 8016e00: f1b8 0300 subs.w r3, r8, #0 + 8016e04: d026 beq.n 8016e54 <__d2b+0x84> + 8016e06: 4668 mov r0, sp + 8016e08: 9300 str r3, [sp, #0] + 8016e0a: f7ff fd17 bl 801683c <__lo0bits> + 8016e0e: e9dd 1200 ldrd r1, r2, [sp] + 8016e12: b1e8 cbz r0, 8016e50 <__d2b+0x80> + 8016e14: f1c0 0320 rsb r3, r0, #32 + 8016e18: fa02 f303 lsl.w r3, r2, r3 + 8016e1c: 430b orrs r3, r1 + 8016e1e: 40c2 lsrs r2, r0 + 8016e20: 6163 str r3, [r4, #20] + 8016e22: 9201 str r2, [sp, #4] + 8016e24: 9b01 ldr r3, [sp, #4] + 8016e26: 61a3 str r3, [r4, #24] + 8016e28: 2b00 cmp r3, #0 + 8016e2a: bf14 ite ne + 8016e2c: 2202 movne r2, #2 + 8016e2e: 2201 moveq r2, #1 + 8016e30: 6122 str r2, [r4, #16] + 8016e32: b1bd cbz r5, 8016e64 <__d2b+0x94> + 8016e34: f2a5 4533 subw r5, r5, #1075 ; 0x433 + 8016e38: 4405 add r5, r0 + 8016e3a: 603d str r5, [r7, #0] + 8016e3c: f1c0 0035 rsb r0, r0, #53 ; 0x35 + 8016e40: 6030 str r0, [r6, #0] + 8016e42: 4620 mov r0, r4 + 8016e44: b003 add sp, #12 + 8016e46: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8016e4a: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8016e4e: e7d6 b.n 8016dfe <__d2b+0x2e> + 8016e50: 6161 str r1, [r4, #20] + 8016e52: e7e7 b.n 8016e24 <__d2b+0x54> + 8016e54: a801 add r0, sp, #4 + 8016e56: f7ff fcf1 bl 801683c <__lo0bits> + 8016e5a: 9b01 ldr r3, [sp, #4] + 8016e5c: 6163 str r3, [r4, #20] + 8016e5e: 3020 adds r0, #32 + 8016e60: 2201 movs r2, #1 + 8016e62: e7e5 b.n 8016e30 <__d2b+0x60> + 8016e64: eb04 0382 add.w r3, r4, r2, lsl #2 + 8016e68: f2a0 4032 subw r0, r0, #1074 ; 0x432 + 8016e6c: 6038 str r0, [r7, #0] + 8016e6e: 6918 ldr r0, [r3, #16] + 8016e70: f7ff fcc4 bl 80167fc <__hi0bits> + 8016e74: ebc0 1042 rsb r0, r0, r2, lsl #5 + 8016e78: e7e2 b.n 8016e40 <__d2b+0x70> + 8016e7a: bf00 nop + 8016e7c: 0801ae94 .word 0x0801ae94 + 8016e80: 0801af05 .word 0x0801af05 + +08016e84 <__ratio>: + 8016e84: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8016e88: 4688 mov r8, r1 + 8016e8a: 4669 mov r1, sp + 8016e8c: 4681 mov r9, r0 + 8016e8e: f7ff ff55 bl 8016d3c <__b2d> + 8016e92: a901 add r1, sp, #4 + 8016e94: 4640 mov r0, r8 + 8016e96: ec55 4b10 vmov r4, r5, d0 + 8016e9a: f7ff ff4f bl 8016d3c <__b2d> + 8016e9e: f8d9 3010 ldr.w r3, [r9, #16] + 8016ea2: f8d8 2010 ldr.w r2, [r8, #16] + 8016ea6: eba3 0c02 sub.w ip, r3, r2 + 8016eaa: e9dd 3200 ldrd r3, r2, [sp] + 8016eae: 1a9b subs r3, r3, r2 + 8016eb0: eb03 134c add.w r3, r3, ip, lsl #5 + 8016eb4: ec51 0b10 vmov r0, r1, d0 + 8016eb8: 2b00 cmp r3, #0 + 8016eba: bfd6 itet le + 8016ebc: 460a movle r2, r1 + 8016ebe: 462a movgt r2, r5 + 8016ec0: ebc3 3303 rsble r3, r3, r3, lsl #12 + 8016ec4: 468b mov fp, r1 + 8016ec6: 462f mov r7, r5 + 8016ec8: bfd4 ite le + 8016eca: eb02 5b03 addle.w fp, r2, r3, lsl #20 + 8016ece: eb02 5703 addgt.w r7, r2, r3, lsl #20 + 8016ed2: 4620 mov r0, r4 + 8016ed4: ee10 2a10 vmov r2, s0 + 8016ed8: 465b mov r3, fp + 8016eda: 4639 mov r1, r7 + 8016edc: f7e9 fcb6 bl 800084c <__aeabi_ddiv> + 8016ee0: ec41 0b10 vmov d0, r0, r1 + 8016ee4: b003 add sp, #12 + 8016ee6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +08016eea <__copybits>: + 8016eea: 3901 subs r1, #1 + 8016eec: b570 push {r4, r5, r6, lr} + 8016eee: 1149 asrs r1, r1, #5 + 8016ef0: 6914 ldr r4, [r2, #16] + 8016ef2: 3101 adds r1, #1 + 8016ef4: f102 0314 add.w r3, r2, #20 + 8016ef8: eb00 0181 add.w r1, r0, r1, lsl #2 + 8016efc: eb03 0484 add.w r4, r3, r4, lsl #2 + 8016f00: 1f05 subs r5, r0, #4 + 8016f02: 42a3 cmp r3, r4 + 8016f04: d30c bcc.n 8016f20 <__copybits+0x36> + 8016f06: 1aa3 subs r3, r4, r2 + 8016f08: 3b11 subs r3, #17 + 8016f0a: f023 0303 bic.w r3, r3, #3 + 8016f0e: 3211 adds r2, #17 + 8016f10: 42a2 cmp r2, r4 + 8016f12: bf88 it hi + 8016f14: 2300 movhi r3, #0 + 8016f16: 4418 add r0, r3 + 8016f18: 2300 movs r3, #0 + 8016f1a: 4288 cmp r0, r1 + 8016f1c: d305 bcc.n 8016f2a <__copybits+0x40> + 8016f1e: bd70 pop {r4, r5, r6, pc} + 8016f20: f853 6b04 ldr.w r6, [r3], #4 + 8016f24: f845 6f04 str.w r6, [r5, #4]! + 8016f28: e7eb b.n 8016f02 <__copybits+0x18> + 8016f2a: f840 3b04 str.w r3, [r0], #4 + 8016f2e: e7f4 b.n 8016f1a <__copybits+0x30> + +08016f30 <__any_on>: + 8016f30: f100 0214 add.w r2, r0, #20 + 8016f34: 6900 ldr r0, [r0, #16] + 8016f36: 114b asrs r3, r1, #5 + 8016f38: 4298 cmp r0, r3 + 8016f3a: b510 push {r4, lr} + 8016f3c: db11 blt.n 8016f62 <__any_on+0x32> + 8016f3e: dd0a ble.n 8016f56 <__any_on+0x26> + 8016f40: f011 011f ands.w r1, r1, #31 + 8016f44: d007 beq.n 8016f56 <__any_on+0x26> + 8016f46: f852 4023 ldr.w r4, [r2, r3, lsl #2] + 8016f4a: fa24 f001 lsr.w r0, r4, r1 + 8016f4e: fa00 f101 lsl.w r1, r0, r1 + 8016f52: 428c cmp r4, r1 + 8016f54: d10b bne.n 8016f6e <__any_on+0x3e> + 8016f56: eb02 0383 add.w r3, r2, r3, lsl #2 + 8016f5a: 4293 cmp r3, r2 + 8016f5c: d803 bhi.n 8016f66 <__any_on+0x36> + 8016f5e: 2000 movs r0, #0 + 8016f60: bd10 pop {r4, pc} + 8016f62: 4603 mov r3, r0 + 8016f64: e7f7 b.n 8016f56 <__any_on+0x26> + 8016f66: f853 1d04 ldr.w r1, [r3, #-4]! + 8016f6a: 2900 cmp r1, #0 + 8016f6c: d0f5 beq.n 8016f5a <__any_on+0x2a> + 8016f6e: 2001 movs r0, #1 + 8016f70: e7f6 b.n 8016f60 <__any_on+0x30> + +08016f72 <__ascii_wctomb>: + 8016f72: b149 cbz r1, 8016f88 <__ascii_wctomb+0x16> + 8016f74: 2aff cmp r2, #255 ; 0xff + 8016f76: bf85 ittet hi + 8016f78: 238a movhi r3, #138 ; 0x8a + 8016f7a: 6003 strhi r3, [r0, #0] + 8016f7c: 700a strbls r2, [r1, #0] + 8016f7e: f04f 30ff movhi.w r0, #4294967295 + 8016f82: bf98 it ls + 8016f84: 2001 movls r0, #1 + 8016f86: 4770 bx lr + 8016f88: 4608 mov r0, r1 + 8016f8a: 4770 bx lr + +08016f8c <__ssputs_r>: + 8016f8c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8016f90: 688e ldr r6, [r1, #8] + 8016f92: 461f mov r7, r3 + 8016f94: 42be cmp r6, r7 + 8016f96: 680b ldr r3, [r1, #0] + 8016f98: 4682 mov sl, r0 + 8016f9a: 460c mov r4, r1 + 8016f9c: 4690 mov r8, r2 + 8016f9e: d82c bhi.n 8016ffa <__ssputs_r+0x6e> + 8016fa0: 898a ldrh r2, [r1, #12] + 8016fa2: f412 6f90 tst.w r2, #1152 ; 0x480 + 8016fa6: d026 beq.n 8016ff6 <__ssputs_r+0x6a> + 8016fa8: 6965 ldr r5, [r4, #20] + 8016faa: 6909 ldr r1, [r1, #16] + 8016fac: eb05 0545 add.w r5, r5, r5, lsl #1 + 8016fb0: eba3 0901 sub.w r9, r3, r1 + 8016fb4: eb05 75d5 add.w r5, r5, r5, lsr #31 + 8016fb8: 1c7b adds r3, r7, #1 + 8016fba: 444b add r3, r9 + 8016fbc: 106d asrs r5, r5, #1 + 8016fbe: 429d cmp r5, r3 + 8016fc0: bf38 it cc + 8016fc2: 461d movcc r5, r3 + 8016fc4: 0553 lsls r3, r2, #21 + 8016fc6: d527 bpl.n 8017018 <__ssputs_r+0x8c> + 8016fc8: 4629 mov r1, r5 + 8016fca: f7fc f83b bl 8013044 <_malloc_r> + 8016fce: 4606 mov r6, r0 + 8016fd0: b360 cbz r0, 801702c <__ssputs_r+0xa0> + 8016fd2: 6921 ldr r1, [r4, #16] + 8016fd4: 464a mov r2, r9 + 8016fd6: f7fe f8b4 bl 8015142 + 8016fda: 89a3 ldrh r3, [r4, #12] + 8016fdc: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 8016fe0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8016fe4: 81a3 strh r3, [r4, #12] + 8016fe6: 6126 str r6, [r4, #16] + 8016fe8: 6165 str r5, [r4, #20] + 8016fea: 444e add r6, r9 + 8016fec: eba5 0509 sub.w r5, r5, r9 + 8016ff0: 6026 str r6, [r4, #0] + 8016ff2: 60a5 str r5, [r4, #8] + 8016ff4: 463e mov r6, r7 + 8016ff6: 42be cmp r6, r7 + 8016ff8: d900 bls.n 8016ffc <__ssputs_r+0x70> + 8016ffa: 463e mov r6, r7 + 8016ffc: 6820 ldr r0, [r4, #0] + 8016ffe: 4632 mov r2, r6 + 8017000: 4641 mov r1, r8 + 8017002: f000 f9db bl 80173bc + 8017006: 68a3 ldr r3, [r4, #8] + 8017008: 1b9b subs r3, r3, r6 + 801700a: 60a3 str r3, [r4, #8] + 801700c: 6823 ldr r3, [r4, #0] + 801700e: 4433 add r3, r6 + 8017010: 6023 str r3, [r4, #0] + 8017012: 2000 movs r0, #0 + 8017014: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8017018: 462a mov r2, r5 + 801701a: f000 fa06 bl 801742a <_realloc_r> + 801701e: 4606 mov r6, r0 + 8017020: 2800 cmp r0, #0 + 8017022: d1e0 bne.n 8016fe6 <__ssputs_r+0x5a> + 8017024: 6921 ldr r1, [r4, #16] + 8017026: 4650 mov r0, sl + 8017028: f7fe ff40 bl 8015eac <_free_r> + 801702c: 230c movs r3, #12 + 801702e: f8ca 3000 str.w r3, [sl] + 8017032: 89a3 ldrh r3, [r4, #12] + 8017034: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8017038: 81a3 strh r3, [r4, #12] + 801703a: f04f 30ff mov.w r0, #4294967295 + 801703e: e7e9 b.n 8017014 <__ssputs_r+0x88> + +08017040 <_svfiprintf_r>: + 8017040: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8017044: 4698 mov r8, r3 + 8017046: 898b ldrh r3, [r1, #12] + 8017048: 061b lsls r3, r3, #24 + 801704a: b09d sub sp, #116 ; 0x74 + 801704c: 4607 mov r7, r0 + 801704e: 460d mov r5, r1 + 8017050: 4614 mov r4, r2 + 8017052: d50e bpl.n 8017072 <_svfiprintf_r+0x32> + 8017054: 690b ldr r3, [r1, #16] + 8017056: b963 cbnz r3, 8017072 <_svfiprintf_r+0x32> + 8017058: 2140 movs r1, #64 ; 0x40 + 801705a: f7fb fff3 bl 8013044 <_malloc_r> + 801705e: 6028 str r0, [r5, #0] + 8017060: 6128 str r0, [r5, #16] + 8017062: b920 cbnz r0, 801706e <_svfiprintf_r+0x2e> + 8017064: 230c movs r3, #12 + 8017066: 603b str r3, [r7, #0] + 8017068: f04f 30ff mov.w r0, #4294967295 + 801706c: e0d0 b.n 8017210 <_svfiprintf_r+0x1d0> + 801706e: 2340 movs r3, #64 ; 0x40 + 8017070: 616b str r3, [r5, #20] + 8017072: 2300 movs r3, #0 + 8017074: 9309 str r3, [sp, #36] ; 0x24 + 8017076: 2320 movs r3, #32 + 8017078: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 801707c: f8cd 800c str.w r8, [sp, #12] + 8017080: 2330 movs r3, #48 ; 0x30 + 8017082: f8df 81a4 ldr.w r8, [pc, #420] ; 8017228 <_svfiprintf_r+0x1e8> + 8017086: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 801708a: f04f 0901 mov.w r9, #1 + 801708e: 4623 mov r3, r4 + 8017090: 469a mov sl, r3 + 8017092: f813 2b01 ldrb.w r2, [r3], #1 + 8017096: b10a cbz r2, 801709c <_svfiprintf_r+0x5c> + 8017098: 2a25 cmp r2, #37 ; 0x25 + 801709a: d1f9 bne.n 8017090 <_svfiprintf_r+0x50> + 801709c: ebba 0b04 subs.w fp, sl, r4 + 80170a0: d00b beq.n 80170ba <_svfiprintf_r+0x7a> + 80170a2: 465b mov r3, fp + 80170a4: 4622 mov r2, r4 + 80170a6: 4629 mov r1, r5 + 80170a8: 4638 mov r0, r7 + 80170aa: f7ff ff6f bl 8016f8c <__ssputs_r> + 80170ae: 3001 adds r0, #1 + 80170b0: f000 80a9 beq.w 8017206 <_svfiprintf_r+0x1c6> + 80170b4: 9a09 ldr r2, [sp, #36] ; 0x24 + 80170b6: 445a add r2, fp + 80170b8: 9209 str r2, [sp, #36] ; 0x24 + 80170ba: f89a 3000 ldrb.w r3, [sl] + 80170be: 2b00 cmp r3, #0 + 80170c0: f000 80a1 beq.w 8017206 <_svfiprintf_r+0x1c6> + 80170c4: 2300 movs r3, #0 + 80170c6: f04f 32ff mov.w r2, #4294967295 + 80170ca: e9cd 2305 strd r2, r3, [sp, #20] + 80170ce: f10a 0a01 add.w sl, sl, #1 + 80170d2: 9304 str r3, [sp, #16] + 80170d4: 9307 str r3, [sp, #28] + 80170d6: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 80170da: 931a str r3, [sp, #104] ; 0x68 + 80170dc: 4654 mov r4, sl + 80170de: 2205 movs r2, #5 + 80170e0: f814 1b01 ldrb.w r1, [r4], #1 + 80170e4: 4850 ldr r0, [pc, #320] ; (8017228 <_svfiprintf_r+0x1e8>) + 80170e6: f7e9 f873 bl 80001d0 + 80170ea: 9a04 ldr r2, [sp, #16] + 80170ec: b9d8 cbnz r0, 8017126 <_svfiprintf_r+0xe6> + 80170ee: 06d0 lsls r0, r2, #27 + 80170f0: bf44 itt mi + 80170f2: 2320 movmi r3, #32 + 80170f4: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80170f8: 0711 lsls r1, r2, #28 + 80170fa: bf44 itt mi + 80170fc: 232b movmi r3, #43 ; 0x2b + 80170fe: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 8017102: f89a 3000 ldrb.w r3, [sl] + 8017106: 2b2a cmp r3, #42 ; 0x2a + 8017108: d015 beq.n 8017136 <_svfiprintf_r+0xf6> + 801710a: 9a07 ldr r2, [sp, #28] + 801710c: 4654 mov r4, sl + 801710e: 2000 movs r0, #0 + 8017110: f04f 0c0a mov.w ip, #10 + 8017114: 4621 mov r1, r4 + 8017116: f811 3b01 ldrb.w r3, [r1], #1 + 801711a: 3b30 subs r3, #48 ; 0x30 + 801711c: 2b09 cmp r3, #9 + 801711e: d94d bls.n 80171bc <_svfiprintf_r+0x17c> + 8017120: b1b0 cbz r0, 8017150 <_svfiprintf_r+0x110> + 8017122: 9207 str r2, [sp, #28] + 8017124: e014 b.n 8017150 <_svfiprintf_r+0x110> + 8017126: eba0 0308 sub.w r3, r0, r8 + 801712a: fa09 f303 lsl.w r3, r9, r3 + 801712e: 4313 orrs r3, r2 + 8017130: 9304 str r3, [sp, #16] + 8017132: 46a2 mov sl, r4 + 8017134: e7d2 b.n 80170dc <_svfiprintf_r+0x9c> + 8017136: 9b03 ldr r3, [sp, #12] + 8017138: 1d19 adds r1, r3, #4 + 801713a: 681b ldr r3, [r3, #0] + 801713c: 9103 str r1, [sp, #12] + 801713e: 2b00 cmp r3, #0 + 8017140: bfbb ittet lt + 8017142: 425b neglt r3, r3 + 8017144: f042 0202 orrlt.w r2, r2, #2 + 8017148: 9307 strge r3, [sp, #28] + 801714a: 9307 strlt r3, [sp, #28] + 801714c: bfb8 it lt + 801714e: 9204 strlt r2, [sp, #16] + 8017150: 7823 ldrb r3, [r4, #0] + 8017152: 2b2e cmp r3, #46 ; 0x2e + 8017154: d10c bne.n 8017170 <_svfiprintf_r+0x130> + 8017156: 7863 ldrb r3, [r4, #1] + 8017158: 2b2a cmp r3, #42 ; 0x2a + 801715a: d134 bne.n 80171c6 <_svfiprintf_r+0x186> + 801715c: 9b03 ldr r3, [sp, #12] + 801715e: 1d1a adds r2, r3, #4 + 8017160: 681b ldr r3, [r3, #0] + 8017162: 9203 str r2, [sp, #12] + 8017164: 2b00 cmp r3, #0 + 8017166: bfb8 it lt + 8017168: f04f 33ff movlt.w r3, #4294967295 + 801716c: 3402 adds r4, #2 + 801716e: 9305 str r3, [sp, #20] + 8017170: f8df a0c4 ldr.w sl, [pc, #196] ; 8017238 <_svfiprintf_r+0x1f8> + 8017174: 7821 ldrb r1, [r4, #0] + 8017176: 2203 movs r2, #3 + 8017178: 4650 mov r0, sl + 801717a: f7e9 f829 bl 80001d0 + 801717e: b138 cbz r0, 8017190 <_svfiprintf_r+0x150> + 8017180: 9b04 ldr r3, [sp, #16] + 8017182: eba0 000a sub.w r0, r0, sl + 8017186: 2240 movs r2, #64 ; 0x40 + 8017188: 4082 lsls r2, r0 + 801718a: 4313 orrs r3, r2 + 801718c: 3401 adds r4, #1 + 801718e: 9304 str r3, [sp, #16] + 8017190: f814 1b01 ldrb.w r1, [r4], #1 + 8017194: 4825 ldr r0, [pc, #148] ; (801722c <_svfiprintf_r+0x1ec>) + 8017196: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 801719a: 2206 movs r2, #6 + 801719c: f7e9 f818 bl 80001d0 + 80171a0: 2800 cmp r0, #0 + 80171a2: d038 beq.n 8017216 <_svfiprintf_r+0x1d6> + 80171a4: 4b22 ldr r3, [pc, #136] ; (8017230 <_svfiprintf_r+0x1f0>) + 80171a6: bb1b cbnz r3, 80171f0 <_svfiprintf_r+0x1b0> + 80171a8: 9b03 ldr r3, [sp, #12] + 80171aa: 3307 adds r3, #7 + 80171ac: f023 0307 bic.w r3, r3, #7 + 80171b0: 3308 adds r3, #8 + 80171b2: 9303 str r3, [sp, #12] + 80171b4: 9b09 ldr r3, [sp, #36] ; 0x24 + 80171b6: 4433 add r3, r6 + 80171b8: 9309 str r3, [sp, #36] ; 0x24 + 80171ba: e768 b.n 801708e <_svfiprintf_r+0x4e> + 80171bc: fb0c 3202 mla r2, ip, r2, r3 + 80171c0: 460c mov r4, r1 + 80171c2: 2001 movs r0, #1 + 80171c4: e7a6 b.n 8017114 <_svfiprintf_r+0xd4> + 80171c6: 2300 movs r3, #0 + 80171c8: 3401 adds r4, #1 + 80171ca: 9305 str r3, [sp, #20] + 80171cc: 4619 mov r1, r3 + 80171ce: f04f 0c0a mov.w ip, #10 + 80171d2: 4620 mov r0, r4 + 80171d4: f810 2b01 ldrb.w r2, [r0], #1 + 80171d8: 3a30 subs r2, #48 ; 0x30 + 80171da: 2a09 cmp r2, #9 + 80171dc: d903 bls.n 80171e6 <_svfiprintf_r+0x1a6> + 80171de: 2b00 cmp r3, #0 + 80171e0: d0c6 beq.n 8017170 <_svfiprintf_r+0x130> + 80171e2: 9105 str r1, [sp, #20] + 80171e4: e7c4 b.n 8017170 <_svfiprintf_r+0x130> + 80171e6: fb0c 2101 mla r1, ip, r1, r2 + 80171ea: 4604 mov r4, r0 + 80171ec: 2301 movs r3, #1 + 80171ee: e7f0 b.n 80171d2 <_svfiprintf_r+0x192> + 80171f0: ab03 add r3, sp, #12 + 80171f2: 9300 str r3, [sp, #0] + 80171f4: 462a mov r2, r5 + 80171f6: 4b0f ldr r3, [pc, #60] ; (8017234 <_svfiprintf_r+0x1f4>) + 80171f8: a904 add r1, sp, #16 + 80171fa: 4638 mov r0, r7 + 80171fc: f7fc ff56 bl 80140ac <_printf_float> + 8017200: 1c42 adds r2, r0, #1 + 8017202: 4606 mov r6, r0 + 8017204: d1d6 bne.n 80171b4 <_svfiprintf_r+0x174> + 8017206: 89ab ldrh r3, [r5, #12] + 8017208: 065b lsls r3, r3, #25 + 801720a: f53f af2d bmi.w 8017068 <_svfiprintf_r+0x28> + 801720e: 9809 ldr r0, [sp, #36] ; 0x24 + 8017210: b01d add sp, #116 ; 0x74 + 8017212: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8017216: ab03 add r3, sp, #12 + 8017218: 9300 str r3, [sp, #0] + 801721a: 462a mov r2, r5 + 801721c: 4b05 ldr r3, [pc, #20] ; (8017234 <_svfiprintf_r+0x1f4>) + 801721e: a904 add r1, sp, #16 + 8017220: 4638 mov r0, r7 + 8017222: f7fd f9e7 bl 80145f4 <_printf_i> + 8017226: e7eb b.n 8017200 <_svfiprintf_r+0x1c0> + 8017228: 0801b05c .word 0x0801b05c + 801722c: 0801b066 .word 0x0801b066 + 8017230: 080140ad .word 0x080140ad + 8017234: 08016f8d .word 0x08016f8d + 8017238: 0801b062 .word 0x0801b062 + +0801723c <__sflush_r>: + 801723c: 898a ldrh r2, [r1, #12] + 801723e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8017242: 4605 mov r5, r0 + 8017244: 0710 lsls r0, r2, #28 + 8017246: 460c mov r4, r1 + 8017248: d458 bmi.n 80172fc <__sflush_r+0xc0> + 801724a: 684b ldr r3, [r1, #4] + 801724c: 2b00 cmp r3, #0 + 801724e: dc05 bgt.n 801725c <__sflush_r+0x20> + 8017250: 6c0b ldr r3, [r1, #64] ; 0x40 + 8017252: 2b00 cmp r3, #0 + 8017254: dc02 bgt.n 801725c <__sflush_r+0x20> + 8017256: 2000 movs r0, #0 + 8017258: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801725c: 6ae6 ldr r6, [r4, #44] ; 0x2c + 801725e: 2e00 cmp r6, #0 + 8017260: d0f9 beq.n 8017256 <__sflush_r+0x1a> + 8017262: 2300 movs r3, #0 + 8017264: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 8017268: 682f ldr r7, [r5, #0] + 801726a: 6a21 ldr r1, [r4, #32] + 801726c: 602b str r3, [r5, #0] + 801726e: d032 beq.n 80172d6 <__sflush_r+0x9a> + 8017270: 6d60 ldr r0, [r4, #84] ; 0x54 + 8017272: 89a3 ldrh r3, [r4, #12] + 8017274: 075a lsls r2, r3, #29 + 8017276: d505 bpl.n 8017284 <__sflush_r+0x48> + 8017278: 6863 ldr r3, [r4, #4] + 801727a: 1ac0 subs r0, r0, r3 + 801727c: 6b63 ldr r3, [r4, #52] ; 0x34 + 801727e: b10b cbz r3, 8017284 <__sflush_r+0x48> + 8017280: 6c23 ldr r3, [r4, #64] ; 0x40 + 8017282: 1ac0 subs r0, r0, r3 + 8017284: 2300 movs r3, #0 + 8017286: 4602 mov r2, r0 + 8017288: 6ae6 ldr r6, [r4, #44] ; 0x2c + 801728a: 6a21 ldr r1, [r4, #32] + 801728c: 4628 mov r0, r5 + 801728e: 47b0 blx r6 + 8017290: 1c43 adds r3, r0, #1 + 8017292: 89a3 ldrh r3, [r4, #12] + 8017294: d106 bne.n 80172a4 <__sflush_r+0x68> + 8017296: 6829 ldr r1, [r5, #0] + 8017298: 291d cmp r1, #29 + 801729a: d82b bhi.n 80172f4 <__sflush_r+0xb8> + 801729c: 4a29 ldr r2, [pc, #164] ; (8017344 <__sflush_r+0x108>) + 801729e: 410a asrs r2, r1 + 80172a0: 07d6 lsls r6, r2, #31 + 80172a2: d427 bmi.n 80172f4 <__sflush_r+0xb8> + 80172a4: 2200 movs r2, #0 + 80172a6: 6062 str r2, [r4, #4] + 80172a8: 04d9 lsls r1, r3, #19 + 80172aa: 6922 ldr r2, [r4, #16] + 80172ac: 6022 str r2, [r4, #0] + 80172ae: d504 bpl.n 80172ba <__sflush_r+0x7e> + 80172b0: 1c42 adds r2, r0, #1 + 80172b2: d101 bne.n 80172b8 <__sflush_r+0x7c> + 80172b4: 682b ldr r3, [r5, #0] + 80172b6: b903 cbnz r3, 80172ba <__sflush_r+0x7e> + 80172b8: 6560 str r0, [r4, #84] ; 0x54 + 80172ba: 6b61 ldr r1, [r4, #52] ; 0x34 + 80172bc: 602f str r7, [r5, #0] + 80172be: 2900 cmp r1, #0 + 80172c0: d0c9 beq.n 8017256 <__sflush_r+0x1a> + 80172c2: f104 0344 add.w r3, r4, #68 ; 0x44 + 80172c6: 4299 cmp r1, r3 + 80172c8: d002 beq.n 80172d0 <__sflush_r+0x94> + 80172ca: 4628 mov r0, r5 + 80172cc: f7fe fdee bl 8015eac <_free_r> + 80172d0: 2000 movs r0, #0 + 80172d2: 6360 str r0, [r4, #52] ; 0x34 + 80172d4: e7c0 b.n 8017258 <__sflush_r+0x1c> + 80172d6: 2301 movs r3, #1 + 80172d8: 4628 mov r0, r5 + 80172da: 47b0 blx r6 + 80172dc: 1c41 adds r1, r0, #1 + 80172de: d1c8 bne.n 8017272 <__sflush_r+0x36> + 80172e0: 682b ldr r3, [r5, #0] + 80172e2: 2b00 cmp r3, #0 + 80172e4: d0c5 beq.n 8017272 <__sflush_r+0x36> + 80172e6: 2b1d cmp r3, #29 + 80172e8: d001 beq.n 80172ee <__sflush_r+0xb2> + 80172ea: 2b16 cmp r3, #22 + 80172ec: d101 bne.n 80172f2 <__sflush_r+0xb6> + 80172ee: 602f str r7, [r5, #0] + 80172f0: e7b1 b.n 8017256 <__sflush_r+0x1a> + 80172f2: 89a3 ldrh r3, [r4, #12] + 80172f4: f043 0340 orr.w r3, r3, #64 ; 0x40 + 80172f8: 81a3 strh r3, [r4, #12] + 80172fa: e7ad b.n 8017258 <__sflush_r+0x1c> + 80172fc: 690f ldr r7, [r1, #16] + 80172fe: 2f00 cmp r7, #0 + 8017300: d0a9 beq.n 8017256 <__sflush_r+0x1a> + 8017302: 0793 lsls r3, r2, #30 + 8017304: 680e ldr r6, [r1, #0] + 8017306: bf08 it eq + 8017308: 694b ldreq r3, [r1, #20] + 801730a: 600f str r7, [r1, #0] + 801730c: bf18 it ne + 801730e: 2300 movne r3, #0 + 8017310: eba6 0807 sub.w r8, r6, r7 + 8017314: 608b str r3, [r1, #8] + 8017316: f1b8 0f00 cmp.w r8, #0 + 801731a: dd9c ble.n 8017256 <__sflush_r+0x1a> + 801731c: 6a21 ldr r1, [r4, #32] + 801731e: 6aa6 ldr r6, [r4, #40] ; 0x28 + 8017320: 4643 mov r3, r8 + 8017322: 463a mov r2, r7 + 8017324: 4628 mov r0, r5 + 8017326: 47b0 blx r6 + 8017328: 2800 cmp r0, #0 + 801732a: dc06 bgt.n 801733a <__sflush_r+0xfe> + 801732c: 89a3 ldrh r3, [r4, #12] + 801732e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8017332: 81a3 strh r3, [r4, #12] + 8017334: f04f 30ff mov.w r0, #4294967295 + 8017338: e78e b.n 8017258 <__sflush_r+0x1c> + 801733a: 4407 add r7, r0 + 801733c: eba8 0800 sub.w r8, r8, r0 + 8017340: e7e9 b.n 8017316 <__sflush_r+0xda> + 8017342: bf00 nop + 8017344: dfbffffe .word 0xdfbffffe + +08017348 <_fflush_r>: + 8017348: b538 push {r3, r4, r5, lr} + 801734a: 690b ldr r3, [r1, #16] + 801734c: 4605 mov r5, r0 + 801734e: 460c mov r4, r1 + 8017350: b913 cbnz r3, 8017358 <_fflush_r+0x10> + 8017352: 2500 movs r5, #0 + 8017354: 4628 mov r0, r5 + 8017356: bd38 pop {r3, r4, r5, pc} + 8017358: b118 cbz r0, 8017362 <_fflush_r+0x1a> + 801735a: 6a03 ldr r3, [r0, #32] + 801735c: b90b cbnz r3, 8017362 <_fflush_r+0x1a> + 801735e: f7fd fd07 bl 8014d70 <__sinit> + 8017362: f9b4 300c ldrsh.w r3, [r4, #12] + 8017366: 2b00 cmp r3, #0 + 8017368: d0f3 beq.n 8017352 <_fflush_r+0xa> + 801736a: 6e62 ldr r2, [r4, #100] ; 0x64 + 801736c: 07d0 lsls r0, r2, #31 + 801736e: d404 bmi.n 801737a <_fflush_r+0x32> + 8017370: 0599 lsls r1, r3, #22 + 8017372: d402 bmi.n 801737a <_fflush_r+0x32> + 8017374: 6da0 ldr r0, [r4, #88] ; 0x58 + 8017376: f7fd feda bl 801512e <__retarget_lock_acquire_recursive> + 801737a: 4628 mov r0, r5 + 801737c: 4621 mov r1, r4 + 801737e: f7ff ff5d bl 801723c <__sflush_r> + 8017382: 6e63 ldr r3, [r4, #100] ; 0x64 + 8017384: 07da lsls r2, r3, #31 + 8017386: 4605 mov r5, r0 + 8017388: d4e4 bmi.n 8017354 <_fflush_r+0xc> + 801738a: 89a3 ldrh r3, [r4, #12] + 801738c: 059b lsls r3, r3, #22 + 801738e: d4e1 bmi.n 8017354 <_fflush_r+0xc> + 8017390: 6da0 ldr r0, [r4, #88] ; 0x58 + 8017392: f7fd fecd bl 8015130 <__retarget_lock_release_recursive> + 8017396: e7dd b.n 8017354 <_fflush_r+0xc> + +08017398 : + 8017398: b40e push {r1, r2, r3} + 801739a: b503 push {r0, r1, lr} + 801739c: 4601 mov r1, r0 + 801739e: ab03 add r3, sp, #12 + 80173a0: 4805 ldr r0, [pc, #20] ; (80173b8 ) + 80173a2: f853 2b04 ldr.w r2, [r3], #4 + 80173a6: 6800 ldr r0, [r0, #0] + 80173a8: 9301 str r3, [sp, #4] + 80173aa: f000 f897 bl 80174dc <_vfiprintf_r> + 80173ae: b002 add sp, #8 + 80173b0: f85d eb04 ldr.w lr, [sp], #4 + 80173b4: b003 add sp, #12 + 80173b6: 4770 bx lr + 80173b8: 200002f0 .word 0x200002f0 + +080173bc : + 80173bc: 4288 cmp r0, r1 + 80173be: b510 push {r4, lr} + 80173c0: eb01 0402 add.w r4, r1, r2 + 80173c4: d902 bls.n 80173cc + 80173c6: 4284 cmp r4, r0 + 80173c8: 4623 mov r3, r4 + 80173ca: d807 bhi.n 80173dc + 80173cc: 1e43 subs r3, r0, #1 + 80173ce: 42a1 cmp r1, r4 + 80173d0: d008 beq.n 80173e4 + 80173d2: f811 2b01 ldrb.w r2, [r1], #1 + 80173d6: f803 2f01 strb.w r2, [r3, #1]! + 80173da: e7f8 b.n 80173ce + 80173dc: 4402 add r2, r0 + 80173de: 4601 mov r1, r0 + 80173e0: 428a cmp r2, r1 + 80173e2: d100 bne.n 80173e6 + 80173e4: bd10 pop {r4, pc} + 80173e6: f813 4d01 ldrb.w r4, [r3, #-1]! + 80173ea: f802 4d01 strb.w r4, [r2, #-1]! + 80173ee: e7f7 b.n 80173e0 + +080173f0 : + 80173f0: b508 push {r3, lr} + 80173f2: 2006 movs r0, #6 + 80173f4: f000 fa4a bl 801788c + 80173f8: 2001 movs r0, #1 + 80173fa: f7ed fbd1 bl 8004ba0 <_exit> + +080173fe <_calloc_r>: + 80173fe: b537 push {r0, r1, r2, r4, r5, lr} + 8017400: fba1 2402 umull r2, r4, r1, r2 + 8017404: b94c cbnz r4, 801741a <_calloc_r+0x1c> + 8017406: 4611 mov r1, r2 + 8017408: 9201 str r2, [sp, #4] + 801740a: f7fb fe1b bl 8013044 <_malloc_r> + 801740e: 9a01 ldr r2, [sp, #4] + 8017410: 4605 mov r5, r0 + 8017412: b930 cbnz r0, 8017422 <_calloc_r+0x24> + 8017414: 4628 mov r0, r5 + 8017416: b003 add sp, #12 + 8017418: bd30 pop {r4, r5, pc} + 801741a: 220c movs r2, #12 + 801741c: 6002 str r2, [r0, #0] + 801741e: 2500 movs r5, #0 + 8017420: e7f8 b.n 8017414 <_calloc_r+0x16> + 8017422: 4621 mov r1, r4 + 8017424: f7fd fd71 bl 8014f0a + 8017428: e7f4 b.n 8017414 <_calloc_r+0x16> + +0801742a <_realloc_r>: + 801742a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801742e: 4680 mov r8, r0 + 8017430: 4614 mov r4, r2 + 8017432: 460e mov r6, r1 + 8017434: b921 cbnz r1, 8017440 <_realloc_r+0x16> + 8017436: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 801743a: 4611 mov r1, r2 + 801743c: f7fb be02 b.w 8013044 <_malloc_r> + 8017440: b92a cbnz r2, 801744e <_realloc_r+0x24> + 8017442: f7fe fd33 bl 8015eac <_free_r> + 8017446: 4625 mov r5, r4 + 8017448: 4628 mov r0, r5 + 801744a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 801744e: f000 fa39 bl 80178c4 <_malloc_usable_size_r> + 8017452: 4284 cmp r4, r0 + 8017454: 4607 mov r7, r0 + 8017456: d802 bhi.n 801745e <_realloc_r+0x34> + 8017458: ebb4 0f50 cmp.w r4, r0, lsr #1 + 801745c: d812 bhi.n 8017484 <_realloc_r+0x5a> + 801745e: 4621 mov r1, r4 + 8017460: 4640 mov r0, r8 + 8017462: f7fb fdef bl 8013044 <_malloc_r> + 8017466: 4605 mov r5, r0 + 8017468: 2800 cmp r0, #0 + 801746a: d0ed beq.n 8017448 <_realloc_r+0x1e> + 801746c: 42bc cmp r4, r7 + 801746e: 4622 mov r2, r4 + 8017470: 4631 mov r1, r6 + 8017472: bf28 it cs + 8017474: 463a movcs r2, r7 + 8017476: f7fd fe64 bl 8015142 + 801747a: 4631 mov r1, r6 + 801747c: 4640 mov r0, r8 + 801747e: f7fe fd15 bl 8015eac <_free_r> + 8017482: e7e1 b.n 8017448 <_realloc_r+0x1e> + 8017484: 4635 mov r5, r6 + 8017486: e7df b.n 8017448 <_realloc_r+0x1e> + +08017488 <__sfputc_r>: + 8017488: 6893 ldr r3, [r2, #8] + 801748a: 3b01 subs r3, #1 + 801748c: 2b00 cmp r3, #0 + 801748e: b410 push {r4} + 8017490: 6093 str r3, [r2, #8] + 8017492: da08 bge.n 80174a6 <__sfputc_r+0x1e> + 8017494: 6994 ldr r4, [r2, #24] + 8017496: 42a3 cmp r3, r4 + 8017498: db01 blt.n 801749e <__sfputc_r+0x16> + 801749a: 290a cmp r1, #10 + 801749c: d103 bne.n 80174a6 <__sfputc_r+0x1e> + 801749e: f85d 4b04 ldr.w r4, [sp], #4 + 80174a2: f000 b935 b.w 8017710 <__swbuf_r> + 80174a6: 6813 ldr r3, [r2, #0] + 80174a8: 1c58 adds r0, r3, #1 + 80174aa: 6010 str r0, [r2, #0] + 80174ac: 7019 strb r1, [r3, #0] + 80174ae: 4608 mov r0, r1 + 80174b0: f85d 4b04 ldr.w r4, [sp], #4 + 80174b4: 4770 bx lr + +080174b6 <__sfputs_r>: + 80174b6: b5f8 push {r3, r4, r5, r6, r7, lr} + 80174b8: 4606 mov r6, r0 + 80174ba: 460f mov r7, r1 + 80174bc: 4614 mov r4, r2 + 80174be: 18d5 adds r5, r2, r3 + 80174c0: 42ac cmp r4, r5 + 80174c2: d101 bne.n 80174c8 <__sfputs_r+0x12> + 80174c4: 2000 movs r0, #0 + 80174c6: e007 b.n 80174d8 <__sfputs_r+0x22> + 80174c8: f814 1b01 ldrb.w r1, [r4], #1 + 80174cc: 463a mov r2, r7 + 80174ce: 4630 mov r0, r6 + 80174d0: f7ff ffda bl 8017488 <__sfputc_r> + 80174d4: 1c43 adds r3, r0, #1 + 80174d6: d1f3 bne.n 80174c0 <__sfputs_r+0xa> + 80174d8: bdf8 pop {r3, r4, r5, r6, r7, pc} ... -0801502c <_vfiprintf_r>: - 801502c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8015030: 460d mov r5, r1 - 8015032: b09d sub sp, #116 ; 0x74 - 8015034: 4614 mov r4, r2 - 8015036: 4698 mov r8, r3 - 8015038: 4606 mov r6, r0 - 801503a: b118 cbz r0, 8015044 <_vfiprintf_r+0x18> - 801503c: 6a03 ldr r3, [r0, #32] - 801503e: b90b cbnz r3, 8015044 <_vfiprintf_r+0x18> - 8015040: f7fd fc3e bl 80128c0 <__sinit> - 8015044: 6e6b ldr r3, [r5, #100] ; 0x64 - 8015046: 07d9 lsls r1, r3, #31 - 8015048: d405 bmi.n 8015056 <_vfiprintf_r+0x2a> - 801504a: 89ab ldrh r3, [r5, #12] - 801504c: 059a lsls r2, r3, #22 - 801504e: d402 bmi.n 8015056 <_vfiprintf_r+0x2a> - 8015050: 6da8 ldr r0, [r5, #88] ; 0x58 - 8015052: f7fd fe14 bl 8012c7e <__retarget_lock_acquire_recursive> - 8015056: 89ab ldrh r3, [r5, #12] - 8015058: 071b lsls r3, r3, #28 - 801505a: d501 bpl.n 8015060 <_vfiprintf_r+0x34> - 801505c: 692b ldr r3, [r5, #16] - 801505e: b99b cbnz r3, 8015088 <_vfiprintf_r+0x5c> - 8015060: 4629 mov r1, r5 - 8015062: 4630 mov r0, r6 - 8015064: f000 f93a bl 80152dc <__swsetup_r> - 8015068: b170 cbz r0, 8015088 <_vfiprintf_r+0x5c> - 801506a: 6e6b ldr r3, [r5, #100] ; 0x64 - 801506c: 07dc lsls r4, r3, #31 - 801506e: d504 bpl.n 801507a <_vfiprintf_r+0x4e> - 8015070: f04f 30ff mov.w r0, #4294967295 - 8015074: b01d add sp, #116 ; 0x74 - 8015076: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 801507a: 89ab ldrh r3, [r5, #12] - 801507c: 0598 lsls r0, r3, #22 - 801507e: d4f7 bmi.n 8015070 <_vfiprintf_r+0x44> - 8015080: 6da8 ldr r0, [r5, #88] ; 0x58 - 8015082: f7fd fdfd bl 8012c80 <__retarget_lock_release_recursive> - 8015086: e7f3 b.n 8015070 <_vfiprintf_r+0x44> - 8015088: 2300 movs r3, #0 - 801508a: 9309 str r3, [sp, #36] ; 0x24 - 801508c: 2320 movs r3, #32 - 801508e: f88d 3029 strb.w r3, [sp, #41] ; 0x29 - 8015092: f8cd 800c str.w r8, [sp, #12] - 8015096: 2330 movs r3, #48 ; 0x30 - 8015098: f8df 81b0 ldr.w r8, [pc, #432] ; 801524c <_vfiprintf_r+0x220> - 801509c: f88d 302a strb.w r3, [sp, #42] ; 0x2a - 80150a0: f04f 0901 mov.w r9, #1 - 80150a4: 4623 mov r3, r4 - 80150a6: 469a mov sl, r3 - 80150a8: f813 2b01 ldrb.w r2, [r3], #1 - 80150ac: b10a cbz r2, 80150b2 <_vfiprintf_r+0x86> - 80150ae: 2a25 cmp r2, #37 ; 0x25 - 80150b0: d1f9 bne.n 80150a6 <_vfiprintf_r+0x7a> - 80150b2: ebba 0b04 subs.w fp, sl, r4 - 80150b6: d00b beq.n 80150d0 <_vfiprintf_r+0xa4> - 80150b8: 465b mov r3, fp - 80150ba: 4622 mov r2, r4 - 80150bc: 4629 mov r1, r5 - 80150be: 4630 mov r0, r6 - 80150c0: f7ff ffa1 bl 8015006 <__sfputs_r> - 80150c4: 3001 adds r0, #1 - 80150c6: f000 80a9 beq.w 801521c <_vfiprintf_r+0x1f0> - 80150ca: 9a09 ldr r2, [sp, #36] ; 0x24 - 80150cc: 445a add r2, fp - 80150ce: 9209 str r2, [sp, #36] ; 0x24 - 80150d0: f89a 3000 ldrb.w r3, [sl] - 80150d4: 2b00 cmp r3, #0 - 80150d6: f000 80a1 beq.w 801521c <_vfiprintf_r+0x1f0> - 80150da: 2300 movs r3, #0 - 80150dc: f04f 32ff mov.w r2, #4294967295 - 80150e0: e9cd 2305 strd r2, r3, [sp, #20] - 80150e4: f10a 0a01 add.w sl, sl, #1 - 80150e8: 9304 str r3, [sp, #16] - 80150ea: 9307 str r3, [sp, #28] - 80150ec: f88d 3053 strb.w r3, [sp, #83] ; 0x53 - 80150f0: 931a str r3, [sp, #104] ; 0x68 - 80150f2: 4654 mov r4, sl - 80150f4: 2205 movs r2, #5 - 80150f6: f814 1b01 ldrb.w r1, [r4], #1 - 80150fa: 4854 ldr r0, [pc, #336] ; (801524c <_vfiprintf_r+0x220>) - 80150fc: f7eb f868 bl 80001d0 - 8015100: 9a04 ldr r2, [sp, #16] - 8015102: b9d8 cbnz r0, 801513c <_vfiprintf_r+0x110> - 8015104: 06d1 lsls r1, r2, #27 - 8015106: bf44 itt mi - 8015108: 2320 movmi r3, #32 - 801510a: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 801510e: 0713 lsls r3, r2, #28 - 8015110: bf44 itt mi - 8015112: 232b movmi r3, #43 ; 0x2b - 8015114: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 8015118: f89a 3000 ldrb.w r3, [sl] - 801511c: 2b2a cmp r3, #42 ; 0x2a - 801511e: d015 beq.n 801514c <_vfiprintf_r+0x120> - 8015120: 9a07 ldr r2, [sp, #28] - 8015122: 4654 mov r4, sl - 8015124: 2000 movs r0, #0 - 8015126: f04f 0c0a mov.w ip, #10 - 801512a: 4621 mov r1, r4 - 801512c: f811 3b01 ldrb.w r3, [r1], #1 - 8015130: 3b30 subs r3, #48 ; 0x30 - 8015132: 2b09 cmp r3, #9 - 8015134: d94d bls.n 80151d2 <_vfiprintf_r+0x1a6> - 8015136: b1b0 cbz r0, 8015166 <_vfiprintf_r+0x13a> - 8015138: 9207 str r2, [sp, #28] - 801513a: e014 b.n 8015166 <_vfiprintf_r+0x13a> - 801513c: eba0 0308 sub.w r3, r0, r8 - 8015140: fa09 f303 lsl.w r3, r9, r3 - 8015144: 4313 orrs r3, r2 - 8015146: 9304 str r3, [sp, #16] - 8015148: 46a2 mov sl, r4 - 801514a: e7d2 b.n 80150f2 <_vfiprintf_r+0xc6> - 801514c: 9b03 ldr r3, [sp, #12] - 801514e: 1d19 adds r1, r3, #4 - 8015150: 681b ldr r3, [r3, #0] - 8015152: 9103 str r1, [sp, #12] - 8015154: 2b00 cmp r3, #0 - 8015156: bfbb ittet lt - 8015158: 425b neglt r3, r3 - 801515a: f042 0202 orrlt.w r2, r2, #2 - 801515e: 9307 strge r3, [sp, #28] - 8015160: 9307 strlt r3, [sp, #28] - 8015162: bfb8 it lt - 8015164: 9204 strlt r2, [sp, #16] - 8015166: 7823 ldrb r3, [r4, #0] - 8015168: 2b2e cmp r3, #46 ; 0x2e - 801516a: d10c bne.n 8015186 <_vfiprintf_r+0x15a> - 801516c: 7863 ldrb r3, [r4, #1] - 801516e: 2b2a cmp r3, #42 ; 0x2a - 8015170: d134 bne.n 80151dc <_vfiprintf_r+0x1b0> - 8015172: 9b03 ldr r3, [sp, #12] - 8015174: 1d1a adds r2, r3, #4 - 8015176: 681b ldr r3, [r3, #0] - 8015178: 9203 str r2, [sp, #12] - 801517a: 2b00 cmp r3, #0 - 801517c: bfb8 it lt - 801517e: f04f 33ff movlt.w r3, #4294967295 - 8015182: 3402 adds r4, #2 - 8015184: 9305 str r3, [sp, #20] - 8015186: f8df a0d4 ldr.w sl, [pc, #212] ; 801525c <_vfiprintf_r+0x230> - 801518a: 7821 ldrb r1, [r4, #0] - 801518c: 2203 movs r2, #3 - 801518e: 4650 mov r0, sl - 8015190: f7eb f81e bl 80001d0 - 8015194: b138 cbz r0, 80151a6 <_vfiprintf_r+0x17a> - 8015196: 9b04 ldr r3, [sp, #16] - 8015198: eba0 000a sub.w r0, r0, sl - 801519c: 2240 movs r2, #64 ; 0x40 - 801519e: 4082 lsls r2, r0 - 80151a0: 4313 orrs r3, r2 - 80151a2: 3401 adds r4, #1 - 80151a4: 9304 str r3, [sp, #16] - 80151a6: f814 1b01 ldrb.w r1, [r4], #1 - 80151aa: 4829 ldr r0, [pc, #164] ; (8015250 <_vfiprintf_r+0x224>) - 80151ac: f88d 1028 strb.w r1, [sp, #40] ; 0x28 - 80151b0: 2206 movs r2, #6 - 80151b2: f7eb f80d bl 80001d0 - 80151b6: 2800 cmp r0, #0 - 80151b8: d03f beq.n 801523a <_vfiprintf_r+0x20e> - 80151ba: 4b26 ldr r3, [pc, #152] ; (8015254 <_vfiprintf_r+0x228>) - 80151bc: bb1b cbnz r3, 8015206 <_vfiprintf_r+0x1da> - 80151be: 9b03 ldr r3, [sp, #12] - 80151c0: 3307 adds r3, #7 - 80151c2: f023 0307 bic.w r3, r3, #7 - 80151c6: 3308 adds r3, #8 - 80151c8: 9303 str r3, [sp, #12] - 80151ca: 9b09 ldr r3, [sp, #36] ; 0x24 - 80151cc: 443b add r3, r7 - 80151ce: 9309 str r3, [sp, #36] ; 0x24 - 80151d0: e768 b.n 80150a4 <_vfiprintf_r+0x78> - 80151d2: fb0c 3202 mla r2, ip, r2, r3 - 80151d6: 460c mov r4, r1 - 80151d8: 2001 movs r0, #1 - 80151da: e7a6 b.n 801512a <_vfiprintf_r+0xfe> - 80151dc: 2300 movs r3, #0 - 80151de: 3401 adds r4, #1 - 80151e0: 9305 str r3, [sp, #20] - 80151e2: 4619 mov r1, r3 - 80151e4: f04f 0c0a mov.w ip, #10 - 80151e8: 4620 mov r0, r4 - 80151ea: f810 2b01 ldrb.w r2, [r0], #1 - 80151ee: 3a30 subs r2, #48 ; 0x30 - 80151f0: 2a09 cmp r2, #9 - 80151f2: d903 bls.n 80151fc <_vfiprintf_r+0x1d0> - 80151f4: 2b00 cmp r3, #0 - 80151f6: d0c6 beq.n 8015186 <_vfiprintf_r+0x15a> - 80151f8: 9105 str r1, [sp, #20] - 80151fa: e7c4 b.n 8015186 <_vfiprintf_r+0x15a> - 80151fc: fb0c 2101 mla r1, ip, r1, r2 - 8015200: 4604 mov r4, r0 - 8015202: 2301 movs r3, #1 - 8015204: e7f0 b.n 80151e8 <_vfiprintf_r+0x1bc> - 8015206: ab03 add r3, sp, #12 - 8015208: 9300 str r3, [sp, #0] - 801520a: 462a mov r2, r5 - 801520c: 4b12 ldr r3, [pc, #72] ; (8015258 <_vfiprintf_r+0x22c>) - 801520e: a904 add r1, sp, #16 - 8015210: 4630 mov r0, r6 - 8015212: f7fc fcf3 bl 8011bfc <_printf_float> - 8015216: 4607 mov r7, r0 - 8015218: 1c78 adds r0, r7, #1 - 801521a: d1d6 bne.n 80151ca <_vfiprintf_r+0x19e> - 801521c: 6e6b ldr r3, [r5, #100] ; 0x64 - 801521e: 07d9 lsls r1, r3, #31 - 8015220: d405 bmi.n 801522e <_vfiprintf_r+0x202> - 8015222: 89ab ldrh r3, [r5, #12] - 8015224: 059a lsls r2, r3, #22 - 8015226: d402 bmi.n 801522e <_vfiprintf_r+0x202> - 8015228: 6da8 ldr r0, [r5, #88] ; 0x58 - 801522a: f7fd fd29 bl 8012c80 <__retarget_lock_release_recursive> - 801522e: 89ab ldrh r3, [r5, #12] - 8015230: 065b lsls r3, r3, #25 - 8015232: f53f af1d bmi.w 8015070 <_vfiprintf_r+0x44> - 8015236: 9809 ldr r0, [sp, #36] ; 0x24 - 8015238: e71c b.n 8015074 <_vfiprintf_r+0x48> - 801523a: ab03 add r3, sp, #12 - 801523c: 9300 str r3, [sp, #0] - 801523e: 462a mov r2, r5 - 8015240: 4b05 ldr r3, [pc, #20] ; (8015258 <_vfiprintf_r+0x22c>) - 8015242: a904 add r1, sp, #16 - 8015244: 4630 mov r0, r6 - 8015246: f7fc ff7d bl 8012144 <_printf_i> - 801524a: e7e4 b.n 8015216 <_vfiprintf_r+0x1ea> - 801524c: 08018b84 .word 0x08018b84 - 8015250: 08018b8e .word 0x08018b8e - 8015254: 08011bfd .word 0x08011bfd - 8015258: 08015007 .word 0x08015007 - 801525c: 08018b8a .word 0x08018b8a - -08015260 <__swbuf_r>: - 8015260: b5f8 push {r3, r4, r5, r6, r7, lr} - 8015262: 460e mov r6, r1 - 8015264: 4614 mov r4, r2 - 8015266: 4605 mov r5, r0 - 8015268: b118 cbz r0, 8015272 <__swbuf_r+0x12> - 801526a: 6a03 ldr r3, [r0, #32] - 801526c: b90b cbnz r3, 8015272 <__swbuf_r+0x12> - 801526e: f7fd fb27 bl 80128c0 <__sinit> - 8015272: 69a3 ldr r3, [r4, #24] - 8015274: 60a3 str r3, [r4, #8] - 8015276: 89a3 ldrh r3, [r4, #12] - 8015278: 071a lsls r2, r3, #28 - 801527a: d525 bpl.n 80152c8 <__swbuf_r+0x68> - 801527c: 6923 ldr r3, [r4, #16] - 801527e: b31b cbz r3, 80152c8 <__swbuf_r+0x68> - 8015280: 6823 ldr r3, [r4, #0] - 8015282: 6922 ldr r2, [r4, #16] - 8015284: 1a98 subs r0, r3, r2 - 8015286: 6963 ldr r3, [r4, #20] - 8015288: b2f6 uxtb r6, r6 - 801528a: 4283 cmp r3, r0 - 801528c: 4637 mov r7, r6 - 801528e: dc04 bgt.n 801529a <__swbuf_r+0x3a> - 8015290: 4621 mov r1, r4 - 8015292: 4628 mov r0, r5 - 8015294: f7ff fe00 bl 8014e98 <_fflush_r> - 8015298: b9e0 cbnz r0, 80152d4 <__swbuf_r+0x74> - 801529a: 68a3 ldr r3, [r4, #8] - 801529c: 3b01 subs r3, #1 - 801529e: 60a3 str r3, [r4, #8] - 80152a0: 6823 ldr r3, [r4, #0] - 80152a2: 1c5a adds r2, r3, #1 - 80152a4: 6022 str r2, [r4, #0] - 80152a6: 701e strb r6, [r3, #0] - 80152a8: 6962 ldr r2, [r4, #20] - 80152aa: 1c43 adds r3, r0, #1 - 80152ac: 429a cmp r2, r3 - 80152ae: d004 beq.n 80152ba <__swbuf_r+0x5a> - 80152b0: 89a3 ldrh r3, [r4, #12] - 80152b2: 07db lsls r3, r3, #31 - 80152b4: d506 bpl.n 80152c4 <__swbuf_r+0x64> - 80152b6: 2e0a cmp r6, #10 - 80152b8: d104 bne.n 80152c4 <__swbuf_r+0x64> - 80152ba: 4621 mov r1, r4 - 80152bc: 4628 mov r0, r5 - 80152be: f7ff fdeb bl 8014e98 <_fflush_r> - 80152c2: b938 cbnz r0, 80152d4 <__swbuf_r+0x74> - 80152c4: 4638 mov r0, r7 - 80152c6: bdf8 pop {r3, r4, r5, r6, r7, pc} - 80152c8: 4621 mov r1, r4 - 80152ca: 4628 mov r0, r5 - 80152cc: f000 f806 bl 80152dc <__swsetup_r> - 80152d0: 2800 cmp r0, #0 - 80152d2: d0d5 beq.n 8015280 <__swbuf_r+0x20> - 80152d4: f04f 37ff mov.w r7, #4294967295 - 80152d8: e7f4 b.n 80152c4 <__swbuf_r+0x64> +080174dc <_vfiprintf_r>: + 80174dc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80174e0: 460d mov r5, r1 + 80174e2: b09d sub sp, #116 ; 0x74 + 80174e4: 4614 mov r4, r2 + 80174e6: 4698 mov r8, r3 + 80174e8: 4606 mov r6, r0 + 80174ea: b118 cbz r0, 80174f4 <_vfiprintf_r+0x18> + 80174ec: 6a03 ldr r3, [r0, #32] + 80174ee: b90b cbnz r3, 80174f4 <_vfiprintf_r+0x18> + 80174f0: f7fd fc3e bl 8014d70 <__sinit> + 80174f4: 6e6b ldr r3, [r5, #100] ; 0x64 + 80174f6: 07d9 lsls r1, r3, #31 + 80174f8: d405 bmi.n 8017506 <_vfiprintf_r+0x2a> + 80174fa: 89ab ldrh r3, [r5, #12] + 80174fc: 059a lsls r2, r3, #22 + 80174fe: d402 bmi.n 8017506 <_vfiprintf_r+0x2a> + 8017500: 6da8 ldr r0, [r5, #88] ; 0x58 + 8017502: f7fd fe14 bl 801512e <__retarget_lock_acquire_recursive> + 8017506: 89ab ldrh r3, [r5, #12] + 8017508: 071b lsls r3, r3, #28 + 801750a: d501 bpl.n 8017510 <_vfiprintf_r+0x34> + 801750c: 692b ldr r3, [r5, #16] + 801750e: b99b cbnz r3, 8017538 <_vfiprintf_r+0x5c> + 8017510: 4629 mov r1, r5 + 8017512: 4630 mov r0, r6 + 8017514: f000 f93a bl 801778c <__swsetup_r> + 8017518: b170 cbz r0, 8017538 <_vfiprintf_r+0x5c> + 801751a: 6e6b ldr r3, [r5, #100] ; 0x64 + 801751c: 07dc lsls r4, r3, #31 + 801751e: d504 bpl.n 801752a <_vfiprintf_r+0x4e> + 8017520: f04f 30ff mov.w r0, #4294967295 + 8017524: b01d add sp, #116 ; 0x74 + 8017526: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801752a: 89ab ldrh r3, [r5, #12] + 801752c: 0598 lsls r0, r3, #22 + 801752e: d4f7 bmi.n 8017520 <_vfiprintf_r+0x44> + 8017530: 6da8 ldr r0, [r5, #88] ; 0x58 + 8017532: f7fd fdfd bl 8015130 <__retarget_lock_release_recursive> + 8017536: e7f3 b.n 8017520 <_vfiprintf_r+0x44> + 8017538: 2300 movs r3, #0 + 801753a: 9309 str r3, [sp, #36] ; 0x24 + 801753c: 2320 movs r3, #32 + 801753e: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 8017542: f8cd 800c str.w r8, [sp, #12] + 8017546: 2330 movs r3, #48 ; 0x30 + 8017548: f8df 81b0 ldr.w r8, [pc, #432] ; 80176fc <_vfiprintf_r+0x220> + 801754c: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 8017550: f04f 0901 mov.w r9, #1 + 8017554: 4623 mov r3, r4 + 8017556: 469a mov sl, r3 + 8017558: f813 2b01 ldrb.w r2, [r3], #1 + 801755c: b10a cbz r2, 8017562 <_vfiprintf_r+0x86> + 801755e: 2a25 cmp r2, #37 ; 0x25 + 8017560: d1f9 bne.n 8017556 <_vfiprintf_r+0x7a> + 8017562: ebba 0b04 subs.w fp, sl, r4 + 8017566: d00b beq.n 8017580 <_vfiprintf_r+0xa4> + 8017568: 465b mov r3, fp + 801756a: 4622 mov r2, r4 + 801756c: 4629 mov r1, r5 + 801756e: 4630 mov r0, r6 + 8017570: f7ff ffa1 bl 80174b6 <__sfputs_r> + 8017574: 3001 adds r0, #1 + 8017576: f000 80a9 beq.w 80176cc <_vfiprintf_r+0x1f0> + 801757a: 9a09 ldr r2, [sp, #36] ; 0x24 + 801757c: 445a add r2, fp + 801757e: 9209 str r2, [sp, #36] ; 0x24 + 8017580: f89a 3000 ldrb.w r3, [sl] + 8017584: 2b00 cmp r3, #0 + 8017586: f000 80a1 beq.w 80176cc <_vfiprintf_r+0x1f0> + 801758a: 2300 movs r3, #0 + 801758c: f04f 32ff mov.w r2, #4294967295 + 8017590: e9cd 2305 strd r2, r3, [sp, #20] + 8017594: f10a 0a01 add.w sl, sl, #1 + 8017598: 9304 str r3, [sp, #16] + 801759a: 9307 str r3, [sp, #28] + 801759c: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 80175a0: 931a str r3, [sp, #104] ; 0x68 + 80175a2: 4654 mov r4, sl + 80175a4: 2205 movs r2, #5 + 80175a6: f814 1b01 ldrb.w r1, [r4], #1 + 80175aa: 4854 ldr r0, [pc, #336] ; (80176fc <_vfiprintf_r+0x220>) + 80175ac: f7e8 fe10 bl 80001d0 + 80175b0: 9a04 ldr r2, [sp, #16] + 80175b2: b9d8 cbnz r0, 80175ec <_vfiprintf_r+0x110> + 80175b4: 06d1 lsls r1, r2, #27 + 80175b6: bf44 itt mi + 80175b8: 2320 movmi r3, #32 + 80175ba: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80175be: 0713 lsls r3, r2, #28 + 80175c0: bf44 itt mi + 80175c2: 232b movmi r3, #43 ; 0x2b + 80175c4: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80175c8: f89a 3000 ldrb.w r3, [sl] + 80175cc: 2b2a cmp r3, #42 ; 0x2a + 80175ce: d015 beq.n 80175fc <_vfiprintf_r+0x120> + 80175d0: 9a07 ldr r2, [sp, #28] + 80175d2: 4654 mov r4, sl + 80175d4: 2000 movs r0, #0 + 80175d6: f04f 0c0a mov.w ip, #10 + 80175da: 4621 mov r1, r4 + 80175dc: f811 3b01 ldrb.w r3, [r1], #1 + 80175e0: 3b30 subs r3, #48 ; 0x30 + 80175e2: 2b09 cmp r3, #9 + 80175e4: d94d bls.n 8017682 <_vfiprintf_r+0x1a6> + 80175e6: b1b0 cbz r0, 8017616 <_vfiprintf_r+0x13a> + 80175e8: 9207 str r2, [sp, #28] + 80175ea: e014 b.n 8017616 <_vfiprintf_r+0x13a> + 80175ec: eba0 0308 sub.w r3, r0, r8 + 80175f0: fa09 f303 lsl.w r3, r9, r3 + 80175f4: 4313 orrs r3, r2 + 80175f6: 9304 str r3, [sp, #16] + 80175f8: 46a2 mov sl, r4 + 80175fa: e7d2 b.n 80175a2 <_vfiprintf_r+0xc6> + 80175fc: 9b03 ldr r3, [sp, #12] + 80175fe: 1d19 adds r1, r3, #4 + 8017600: 681b ldr r3, [r3, #0] + 8017602: 9103 str r1, [sp, #12] + 8017604: 2b00 cmp r3, #0 + 8017606: bfbb ittet lt + 8017608: 425b neglt r3, r3 + 801760a: f042 0202 orrlt.w r2, r2, #2 + 801760e: 9307 strge r3, [sp, #28] + 8017610: 9307 strlt r3, [sp, #28] + 8017612: bfb8 it lt + 8017614: 9204 strlt r2, [sp, #16] + 8017616: 7823 ldrb r3, [r4, #0] + 8017618: 2b2e cmp r3, #46 ; 0x2e + 801761a: d10c bne.n 8017636 <_vfiprintf_r+0x15a> + 801761c: 7863 ldrb r3, [r4, #1] + 801761e: 2b2a cmp r3, #42 ; 0x2a + 8017620: d134 bne.n 801768c <_vfiprintf_r+0x1b0> + 8017622: 9b03 ldr r3, [sp, #12] + 8017624: 1d1a adds r2, r3, #4 + 8017626: 681b ldr r3, [r3, #0] + 8017628: 9203 str r2, [sp, #12] + 801762a: 2b00 cmp r3, #0 + 801762c: bfb8 it lt + 801762e: f04f 33ff movlt.w r3, #4294967295 + 8017632: 3402 adds r4, #2 + 8017634: 9305 str r3, [sp, #20] + 8017636: f8df a0d4 ldr.w sl, [pc, #212] ; 801770c <_vfiprintf_r+0x230> + 801763a: 7821 ldrb r1, [r4, #0] + 801763c: 2203 movs r2, #3 + 801763e: 4650 mov r0, sl + 8017640: f7e8 fdc6 bl 80001d0 + 8017644: b138 cbz r0, 8017656 <_vfiprintf_r+0x17a> + 8017646: 9b04 ldr r3, [sp, #16] + 8017648: eba0 000a sub.w r0, r0, sl + 801764c: 2240 movs r2, #64 ; 0x40 + 801764e: 4082 lsls r2, r0 + 8017650: 4313 orrs r3, r2 + 8017652: 3401 adds r4, #1 + 8017654: 9304 str r3, [sp, #16] + 8017656: f814 1b01 ldrb.w r1, [r4], #1 + 801765a: 4829 ldr r0, [pc, #164] ; (8017700 <_vfiprintf_r+0x224>) + 801765c: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 8017660: 2206 movs r2, #6 + 8017662: f7e8 fdb5 bl 80001d0 + 8017666: 2800 cmp r0, #0 + 8017668: d03f beq.n 80176ea <_vfiprintf_r+0x20e> + 801766a: 4b26 ldr r3, [pc, #152] ; (8017704 <_vfiprintf_r+0x228>) + 801766c: bb1b cbnz r3, 80176b6 <_vfiprintf_r+0x1da> + 801766e: 9b03 ldr r3, [sp, #12] + 8017670: 3307 adds r3, #7 + 8017672: f023 0307 bic.w r3, r3, #7 + 8017676: 3308 adds r3, #8 + 8017678: 9303 str r3, [sp, #12] + 801767a: 9b09 ldr r3, [sp, #36] ; 0x24 + 801767c: 443b add r3, r7 + 801767e: 9309 str r3, [sp, #36] ; 0x24 + 8017680: e768 b.n 8017554 <_vfiprintf_r+0x78> + 8017682: fb0c 3202 mla r2, ip, r2, r3 + 8017686: 460c mov r4, r1 + 8017688: 2001 movs r0, #1 + 801768a: e7a6 b.n 80175da <_vfiprintf_r+0xfe> + 801768c: 2300 movs r3, #0 + 801768e: 3401 adds r4, #1 + 8017690: 9305 str r3, [sp, #20] + 8017692: 4619 mov r1, r3 + 8017694: f04f 0c0a mov.w ip, #10 + 8017698: 4620 mov r0, r4 + 801769a: f810 2b01 ldrb.w r2, [r0], #1 + 801769e: 3a30 subs r2, #48 ; 0x30 + 80176a0: 2a09 cmp r2, #9 + 80176a2: d903 bls.n 80176ac <_vfiprintf_r+0x1d0> + 80176a4: 2b00 cmp r3, #0 + 80176a6: d0c6 beq.n 8017636 <_vfiprintf_r+0x15a> + 80176a8: 9105 str r1, [sp, #20] + 80176aa: e7c4 b.n 8017636 <_vfiprintf_r+0x15a> + 80176ac: fb0c 2101 mla r1, ip, r1, r2 + 80176b0: 4604 mov r4, r0 + 80176b2: 2301 movs r3, #1 + 80176b4: e7f0 b.n 8017698 <_vfiprintf_r+0x1bc> + 80176b6: ab03 add r3, sp, #12 + 80176b8: 9300 str r3, [sp, #0] + 80176ba: 462a mov r2, r5 + 80176bc: 4b12 ldr r3, [pc, #72] ; (8017708 <_vfiprintf_r+0x22c>) + 80176be: a904 add r1, sp, #16 + 80176c0: 4630 mov r0, r6 + 80176c2: f7fc fcf3 bl 80140ac <_printf_float> + 80176c6: 4607 mov r7, r0 + 80176c8: 1c78 adds r0, r7, #1 + 80176ca: d1d6 bne.n 801767a <_vfiprintf_r+0x19e> + 80176cc: 6e6b ldr r3, [r5, #100] ; 0x64 + 80176ce: 07d9 lsls r1, r3, #31 + 80176d0: d405 bmi.n 80176de <_vfiprintf_r+0x202> + 80176d2: 89ab ldrh r3, [r5, #12] + 80176d4: 059a lsls r2, r3, #22 + 80176d6: d402 bmi.n 80176de <_vfiprintf_r+0x202> + 80176d8: 6da8 ldr r0, [r5, #88] ; 0x58 + 80176da: f7fd fd29 bl 8015130 <__retarget_lock_release_recursive> + 80176de: 89ab ldrh r3, [r5, #12] + 80176e0: 065b lsls r3, r3, #25 + 80176e2: f53f af1d bmi.w 8017520 <_vfiprintf_r+0x44> + 80176e6: 9809 ldr r0, [sp, #36] ; 0x24 + 80176e8: e71c b.n 8017524 <_vfiprintf_r+0x48> + 80176ea: ab03 add r3, sp, #12 + 80176ec: 9300 str r3, [sp, #0] + 80176ee: 462a mov r2, r5 + 80176f0: 4b05 ldr r3, [pc, #20] ; (8017708 <_vfiprintf_r+0x22c>) + 80176f2: a904 add r1, sp, #16 + 80176f4: 4630 mov r0, r6 + 80176f6: f7fc ff7d bl 80145f4 <_printf_i> + 80176fa: e7e4 b.n 80176c6 <_vfiprintf_r+0x1ea> + 80176fc: 0801b05c .word 0x0801b05c + 8017700: 0801b066 .word 0x0801b066 + 8017704: 080140ad .word 0x080140ad + 8017708: 080174b7 .word 0x080174b7 + 801770c: 0801b062 .word 0x0801b062 + +08017710 <__swbuf_r>: + 8017710: b5f8 push {r3, r4, r5, r6, r7, lr} + 8017712: 460e mov r6, r1 + 8017714: 4614 mov r4, r2 + 8017716: 4605 mov r5, r0 + 8017718: b118 cbz r0, 8017722 <__swbuf_r+0x12> + 801771a: 6a03 ldr r3, [r0, #32] + 801771c: b90b cbnz r3, 8017722 <__swbuf_r+0x12> + 801771e: f7fd fb27 bl 8014d70 <__sinit> + 8017722: 69a3 ldr r3, [r4, #24] + 8017724: 60a3 str r3, [r4, #8] + 8017726: 89a3 ldrh r3, [r4, #12] + 8017728: 071a lsls r2, r3, #28 + 801772a: d525 bpl.n 8017778 <__swbuf_r+0x68> + 801772c: 6923 ldr r3, [r4, #16] + 801772e: b31b cbz r3, 8017778 <__swbuf_r+0x68> + 8017730: 6823 ldr r3, [r4, #0] + 8017732: 6922 ldr r2, [r4, #16] + 8017734: 1a98 subs r0, r3, r2 + 8017736: 6963 ldr r3, [r4, #20] + 8017738: b2f6 uxtb r6, r6 + 801773a: 4283 cmp r3, r0 + 801773c: 4637 mov r7, r6 + 801773e: dc04 bgt.n 801774a <__swbuf_r+0x3a> + 8017740: 4621 mov r1, r4 + 8017742: 4628 mov r0, r5 + 8017744: f7ff fe00 bl 8017348 <_fflush_r> + 8017748: b9e0 cbnz r0, 8017784 <__swbuf_r+0x74> + 801774a: 68a3 ldr r3, [r4, #8] + 801774c: 3b01 subs r3, #1 + 801774e: 60a3 str r3, [r4, #8] + 8017750: 6823 ldr r3, [r4, #0] + 8017752: 1c5a adds r2, r3, #1 + 8017754: 6022 str r2, [r4, #0] + 8017756: 701e strb r6, [r3, #0] + 8017758: 6962 ldr r2, [r4, #20] + 801775a: 1c43 adds r3, r0, #1 + 801775c: 429a cmp r2, r3 + 801775e: d004 beq.n 801776a <__swbuf_r+0x5a> + 8017760: 89a3 ldrh r3, [r4, #12] + 8017762: 07db lsls r3, r3, #31 + 8017764: d506 bpl.n 8017774 <__swbuf_r+0x64> + 8017766: 2e0a cmp r6, #10 + 8017768: d104 bne.n 8017774 <__swbuf_r+0x64> + 801776a: 4621 mov r1, r4 + 801776c: 4628 mov r0, r5 + 801776e: f7ff fdeb bl 8017348 <_fflush_r> + 8017772: b938 cbnz r0, 8017784 <__swbuf_r+0x74> + 8017774: 4638 mov r0, r7 + 8017776: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8017778: 4621 mov r1, r4 + 801777a: 4628 mov r0, r5 + 801777c: f000 f806 bl 801778c <__swsetup_r> + 8017780: 2800 cmp r0, #0 + 8017782: d0d5 beq.n 8017730 <__swbuf_r+0x20> + 8017784: f04f 37ff mov.w r7, #4294967295 + 8017788: e7f4 b.n 8017774 <__swbuf_r+0x64> ... -080152dc <__swsetup_r>: - 80152dc: b538 push {r3, r4, r5, lr} - 80152de: 4b2a ldr r3, [pc, #168] ; (8015388 <__swsetup_r+0xac>) - 80152e0: 4605 mov r5, r0 - 80152e2: 6818 ldr r0, [r3, #0] - 80152e4: 460c mov r4, r1 - 80152e6: b118 cbz r0, 80152f0 <__swsetup_r+0x14> - 80152e8: 6a03 ldr r3, [r0, #32] - 80152ea: b90b cbnz r3, 80152f0 <__swsetup_r+0x14> - 80152ec: f7fd fae8 bl 80128c0 <__sinit> - 80152f0: 89a3 ldrh r3, [r4, #12] - 80152f2: f9b4 200c ldrsh.w r2, [r4, #12] - 80152f6: 0718 lsls r0, r3, #28 - 80152f8: d422 bmi.n 8015340 <__swsetup_r+0x64> - 80152fa: 06d9 lsls r1, r3, #27 - 80152fc: d407 bmi.n 801530e <__swsetup_r+0x32> - 80152fe: 2309 movs r3, #9 - 8015300: 602b str r3, [r5, #0] - 8015302: f042 0340 orr.w r3, r2, #64 ; 0x40 - 8015306: 81a3 strh r3, [r4, #12] - 8015308: f04f 30ff mov.w r0, #4294967295 - 801530c: e034 b.n 8015378 <__swsetup_r+0x9c> - 801530e: 0758 lsls r0, r3, #29 - 8015310: d512 bpl.n 8015338 <__swsetup_r+0x5c> - 8015312: 6b61 ldr r1, [r4, #52] ; 0x34 - 8015314: b141 cbz r1, 8015328 <__swsetup_r+0x4c> - 8015316: f104 0344 add.w r3, r4, #68 ; 0x44 - 801531a: 4299 cmp r1, r3 - 801531c: d002 beq.n 8015324 <__swsetup_r+0x48> - 801531e: 4628 mov r0, r5 - 8015320: f7fe fb6c bl 80139fc <_free_r> - 8015324: 2300 movs r3, #0 - 8015326: 6363 str r3, [r4, #52] ; 0x34 - 8015328: 89a3 ldrh r3, [r4, #12] - 801532a: f023 0324 bic.w r3, r3, #36 ; 0x24 - 801532e: 81a3 strh r3, [r4, #12] - 8015330: 2300 movs r3, #0 - 8015332: 6063 str r3, [r4, #4] - 8015334: 6923 ldr r3, [r4, #16] - 8015336: 6023 str r3, [r4, #0] - 8015338: 89a3 ldrh r3, [r4, #12] - 801533a: f043 0308 orr.w r3, r3, #8 - 801533e: 81a3 strh r3, [r4, #12] - 8015340: 6923 ldr r3, [r4, #16] - 8015342: b94b cbnz r3, 8015358 <__swsetup_r+0x7c> - 8015344: 89a3 ldrh r3, [r4, #12] - 8015346: f403 7320 and.w r3, r3, #640 ; 0x280 - 801534a: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 801534e: d003 beq.n 8015358 <__swsetup_r+0x7c> - 8015350: 4621 mov r1, r4 - 8015352: 4628 mov r0, r5 - 8015354: f000 f88c bl 8015470 <__smakebuf_r> - 8015358: 89a0 ldrh r0, [r4, #12] - 801535a: f9b4 200c ldrsh.w r2, [r4, #12] - 801535e: f010 0301 ands.w r3, r0, #1 - 8015362: d00a beq.n 801537a <__swsetup_r+0x9e> - 8015364: 2300 movs r3, #0 - 8015366: 60a3 str r3, [r4, #8] - 8015368: 6963 ldr r3, [r4, #20] - 801536a: 425b negs r3, r3 - 801536c: 61a3 str r3, [r4, #24] - 801536e: 6923 ldr r3, [r4, #16] - 8015370: b943 cbnz r3, 8015384 <__swsetup_r+0xa8> - 8015372: f010 0080 ands.w r0, r0, #128 ; 0x80 - 8015376: d1c4 bne.n 8015302 <__swsetup_r+0x26> - 8015378: bd38 pop {r3, r4, r5, pc} - 801537a: 0781 lsls r1, r0, #30 - 801537c: bf58 it pl - 801537e: 6963 ldrpl r3, [r4, #20] - 8015380: 60a3 str r3, [r4, #8] - 8015382: e7f4 b.n 801536e <__swsetup_r+0x92> - 8015384: 2000 movs r0, #0 - 8015386: e7f7 b.n 8015378 <__swsetup_r+0x9c> - 8015388: 20000310 .word 0x20000310 - -0801538c <_raise_r>: - 801538c: 291f cmp r1, #31 - 801538e: b538 push {r3, r4, r5, lr} - 8015390: 4604 mov r4, r0 - 8015392: 460d mov r5, r1 - 8015394: d904 bls.n 80153a0 <_raise_r+0x14> - 8015396: 2316 movs r3, #22 - 8015398: 6003 str r3, [r0, #0] - 801539a: f04f 30ff mov.w r0, #4294967295 - 801539e: bd38 pop {r3, r4, r5, pc} - 80153a0: 6bc2 ldr r2, [r0, #60] ; 0x3c - 80153a2: b112 cbz r2, 80153aa <_raise_r+0x1e> - 80153a4: f852 3021 ldr.w r3, [r2, r1, lsl #2] - 80153a8: b94b cbnz r3, 80153be <_raise_r+0x32> - 80153aa: 4620 mov r0, r4 - 80153ac: f000 f830 bl 8015410 <_getpid_r> - 80153b0: 462a mov r2, r5 - 80153b2: 4601 mov r1, r0 - 80153b4: 4620 mov r0, r4 - 80153b6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} - 80153ba: f000 b817 b.w 80153ec <_kill_r> - 80153be: 2b01 cmp r3, #1 - 80153c0: d00a beq.n 80153d8 <_raise_r+0x4c> - 80153c2: 1c59 adds r1, r3, #1 - 80153c4: d103 bne.n 80153ce <_raise_r+0x42> - 80153c6: 2316 movs r3, #22 - 80153c8: 6003 str r3, [r0, #0] - 80153ca: 2001 movs r0, #1 - 80153cc: e7e7 b.n 801539e <_raise_r+0x12> - 80153ce: 2400 movs r4, #0 - 80153d0: f842 4025 str.w r4, [r2, r5, lsl #2] - 80153d4: 4628 mov r0, r5 - 80153d6: 4798 blx r3 - 80153d8: 2000 movs r0, #0 - 80153da: e7e0 b.n 801539e <_raise_r+0x12> - -080153dc : - 80153dc: 4b02 ldr r3, [pc, #8] ; (80153e8 ) - 80153de: 4601 mov r1, r0 - 80153e0: 6818 ldr r0, [r3, #0] - 80153e2: f7ff bfd3 b.w 801538c <_raise_r> - 80153e6: bf00 nop - 80153e8: 20000310 .word 0x20000310 - -080153ec <_kill_r>: - 80153ec: b538 push {r3, r4, r5, lr} - 80153ee: 4d07 ldr r5, [pc, #28] ; (801540c <_kill_r+0x20>) - 80153f0: 2300 movs r3, #0 - 80153f2: 4604 mov r4, r0 - 80153f4: 4608 mov r0, r1 - 80153f6: 4611 mov r1, r2 - 80153f8: 602b str r3, [r5, #0] - 80153fa: f7ee ff7d bl 80042f8 <_kill> - 80153fe: 1c43 adds r3, r0, #1 - 8015400: d102 bne.n 8015408 <_kill_r+0x1c> - 8015402: 682b ldr r3, [r5, #0] - 8015404: b103 cbz r3, 8015408 <_kill_r+0x1c> - 8015406: 6023 str r3, [r4, #0] - 8015408: bd38 pop {r3, r4, r5, pc} - 801540a: bf00 nop - 801540c: 200015d0 .word 0x200015d0 - -08015410 <_getpid_r>: - 8015410: f7ee bf6a b.w 80042e8 <_getpid> - -08015414 <_malloc_usable_size_r>: - 8015414: f851 3c04 ldr.w r3, [r1, #-4] - 8015418: 1f18 subs r0, r3, #4 - 801541a: 2b00 cmp r3, #0 - 801541c: bfbc itt lt - 801541e: 580b ldrlt r3, [r1, r0] - 8015420: 18c0 addlt r0, r0, r3 - 8015422: 4770 bx lr - -08015424 <__swhatbuf_r>: - 8015424: b570 push {r4, r5, r6, lr} - 8015426: 460c mov r4, r1 - 8015428: f9b1 100e ldrsh.w r1, [r1, #14] - 801542c: 2900 cmp r1, #0 - 801542e: b096 sub sp, #88 ; 0x58 - 8015430: 4615 mov r5, r2 - 8015432: 461e mov r6, r3 - 8015434: da0d bge.n 8015452 <__swhatbuf_r+0x2e> - 8015436: 89a3 ldrh r3, [r4, #12] - 8015438: f013 0f80 tst.w r3, #128 ; 0x80 - 801543c: f04f 0100 mov.w r1, #0 - 8015440: bf0c ite eq - 8015442: f44f 6380 moveq.w r3, #1024 ; 0x400 - 8015446: 2340 movne r3, #64 ; 0x40 - 8015448: 2000 movs r0, #0 - 801544a: 6031 str r1, [r6, #0] - 801544c: 602b str r3, [r5, #0] - 801544e: b016 add sp, #88 ; 0x58 - 8015450: bd70 pop {r4, r5, r6, pc} - 8015452: 466a mov r2, sp - 8015454: f000 f848 bl 80154e8 <_fstat_r> - 8015458: 2800 cmp r0, #0 - 801545a: dbec blt.n 8015436 <__swhatbuf_r+0x12> - 801545c: 9901 ldr r1, [sp, #4] - 801545e: f401 4170 and.w r1, r1, #61440 ; 0xf000 - 8015462: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000 - 8015466: 4259 negs r1, r3 - 8015468: 4159 adcs r1, r3 - 801546a: f44f 6380 mov.w r3, #1024 ; 0x400 - 801546e: e7eb b.n 8015448 <__swhatbuf_r+0x24> - -08015470 <__smakebuf_r>: - 8015470: 898b ldrh r3, [r1, #12] - 8015472: b573 push {r0, r1, r4, r5, r6, lr} - 8015474: 079d lsls r5, r3, #30 - 8015476: 4606 mov r6, r0 - 8015478: 460c mov r4, r1 - 801547a: d507 bpl.n 801548c <__smakebuf_r+0x1c> - 801547c: f104 0347 add.w r3, r4, #71 ; 0x47 - 8015480: 6023 str r3, [r4, #0] - 8015482: 6123 str r3, [r4, #16] - 8015484: 2301 movs r3, #1 - 8015486: 6163 str r3, [r4, #20] - 8015488: b002 add sp, #8 - 801548a: bd70 pop {r4, r5, r6, pc} - 801548c: ab01 add r3, sp, #4 - 801548e: 466a mov r2, sp - 8015490: f7ff ffc8 bl 8015424 <__swhatbuf_r> - 8015494: 9900 ldr r1, [sp, #0] - 8015496: 4605 mov r5, r0 - 8015498: 4630 mov r0, r6 - 801549a: f7fb fb7b bl 8010b94 <_malloc_r> - 801549e: b948 cbnz r0, 80154b4 <__smakebuf_r+0x44> - 80154a0: f9b4 300c ldrsh.w r3, [r4, #12] - 80154a4: 059a lsls r2, r3, #22 - 80154a6: d4ef bmi.n 8015488 <__smakebuf_r+0x18> - 80154a8: f023 0303 bic.w r3, r3, #3 - 80154ac: f043 0302 orr.w r3, r3, #2 - 80154b0: 81a3 strh r3, [r4, #12] - 80154b2: e7e3 b.n 801547c <__smakebuf_r+0xc> - 80154b4: 89a3 ldrh r3, [r4, #12] - 80154b6: 6020 str r0, [r4, #0] - 80154b8: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80154bc: 81a3 strh r3, [r4, #12] - 80154be: 9b00 ldr r3, [sp, #0] - 80154c0: 6163 str r3, [r4, #20] - 80154c2: 9b01 ldr r3, [sp, #4] - 80154c4: 6120 str r0, [r4, #16] - 80154c6: b15b cbz r3, 80154e0 <__smakebuf_r+0x70> - 80154c8: f9b4 100e ldrsh.w r1, [r4, #14] - 80154cc: 4630 mov r0, r6 - 80154ce: f000 f81d bl 801550c <_isatty_r> - 80154d2: b128 cbz r0, 80154e0 <__smakebuf_r+0x70> - 80154d4: 89a3 ldrh r3, [r4, #12] - 80154d6: f023 0303 bic.w r3, r3, #3 - 80154da: f043 0301 orr.w r3, r3, #1 - 80154de: 81a3 strh r3, [r4, #12] - 80154e0: 89a3 ldrh r3, [r4, #12] - 80154e2: 431d orrs r5, r3 - 80154e4: 81a5 strh r5, [r4, #12] - 80154e6: e7cf b.n 8015488 <__smakebuf_r+0x18> - -080154e8 <_fstat_r>: - 80154e8: b538 push {r3, r4, r5, lr} - 80154ea: 4d07 ldr r5, [pc, #28] ; (8015508 <_fstat_r+0x20>) - 80154ec: 2300 movs r3, #0 - 80154ee: 4604 mov r4, r0 - 80154f0: 4608 mov r0, r1 - 80154f2: 4611 mov r1, r2 - 80154f4: 602b str r3, [r5, #0] - 80154f6: f7ee ff5e bl 80043b6 <_fstat> - 80154fa: 1c43 adds r3, r0, #1 - 80154fc: d102 bne.n 8015504 <_fstat_r+0x1c> - 80154fe: 682b ldr r3, [r5, #0] - 8015500: b103 cbz r3, 8015504 <_fstat_r+0x1c> - 8015502: 6023 str r3, [r4, #0] - 8015504: bd38 pop {r3, r4, r5, pc} - 8015506: bf00 nop - 8015508: 200015d0 .word 0x200015d0 - -0801550c <_isatty_r>: - 801550c: b538 push {r3, r4, r5, lr} - 801550e: 4d06 ldr r5, [pc, #24] ; (8015528 <_isatty_r+0x1c>) - 8015510: 2300 movs r3, #0 - 8015512: 4604 mov r4, r0 - 8015514: 4608 mov r0, r1 - 8015516: 602b str r3, [r5, #0] - 8015518: f7ee ff5d bl 80043d6 <_isatty> - 801551c: 1c43 adds r3, r0, #1 - 801551e: d102 bne.n 8015526 <_isatty_r+0x1a> - 8015520: 682b ldr r3, [r5, #0] - 8015522: b103 cbz r3, 8015526 <_isatty_r+0x1a> - 8015524: 6023 str r3, [r4, #0] - 8015526: bd38 pop {r3, r4, r5, pc} - 8015528: 200015d0 .word 0x200015d0 - 801552c: 00000000 .word 0x00000000 - -08015530 : - 8015530: b51f push {r0, r1, r2, r3, r4, lr} - 8015532: ec53 2b10 vmov r2, r3, d0 - 8015536: 4826 ldr r0, [pc, #152] ; (80155d0 ) - 8015538: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 - 801553c: 4281 cmp r1, r0 - 801553e: dc06 bgt.n 801554e - 8015540: ed9f 1b21 vldr d1, [pc, #132] ; 80155c8 - 8015544: b005 add sp, #20 - 8015546: f85d eb04 ldr.w lr, [sp], #4 - 801554a: f000 b961 b.w 8015810 <__kernel_cos> - 801554e: 4821 ldr r0, [pc, #132] ; (80155d4 ) - 8015550: 4281 cmp r1, r0 - 8015552: dd09 ble.n 8015568 - 8015554: ee10 0a10 vmov r0, s0 - 8015558: 4619 mov r1, r3 - 801555a: f7ea fe95 bl 8000288 <__aeabi_dsub> - 801555e: ec41 0b10 vmov d0, r0, r1 - 8015562: b005 add sp, #20 - 8015564: f85d fb04 ldr.w pc, [sp], #4 - 8015568: 4668 mov r0, sp - 801556a: f000 fad9 bl 8015b20 <__ieee754_rem_pio2> - 801556e: f000 0003 and.w r0, r0, #3 - 8015572: 2801 cmp r0, #1 - 8015574: d00b beq.n 801558e - 8015576: 2802 cmp r0, #2 - 8015578: d016 beq.n 80155a8 - 801557a: b9e0 cbnz r0, 80155b6 - 801557c: ed9d 1b02 vldr d1, [sp, #8] - 8015580: ed9d 0b00 vldr d0, [sp] - 8015584: f000 f944 bl 8015810 <__kernel_cos> - 8015588: ec51 0b10 vmov r0, r1, d0 - 801558c: e7e7 b.n 801555e - 801558e: ed9d 1b02 vldr d1, [sp, #8] - 8015592: ed9d 0b00 vldr d0, [sp] - 8015596: f000 fa03 bl 80159a0 <__kernel_sin> - 801559a: ec53 2b10 vmov r2, r3, d0 - 801559e: ee10 0a10 vmov r0, s0 - 80155a2: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 - 80155a6: e7da b.n 801555e - 80155a8: ed9d 1b02 vldr d1, [sp, #8] - 80155ac: ed9d 0b00 vldr d0, [sp] - 80155b0: f000 f92e bl 8015810 <__kernel_cos> - 80155b4: e7f1 b.n 801559a - 80155b6: ed9d 1b02 vldr d1, [sp, #8] - 80155ba: ed9d 0b00 vldr d0, [sp] - 80155be: 2001 movs r0, #1 - 80155c0: f000 f9ee bl 80159a0 <__kernel_sin> - 80155c4: e7e0 b.n 8015588 - 80155c6: bf00 nop +0801778c <__swsetup_r>: + 801778c: b538 push {r3, r4, r5, lr} + 801778e: 4b2a ldr r3, [pc, #168] ; (8017838 <__swsetup_r+0xac>) + 8017790: 4605 mov r5, r0 + 8017792: 6818 ldr r0, [r3, #0] + 8017794: 460c mov r4, r1 + 8017796: b118 cbz r0, 80177a0 <__swsetup_r+0x14> + 8017798: 6a03 ldr r3, [r0, #32] + 801779a: b90b cbnz r3, 80177a0 <__swsetup_r+0x14> + 801779c: f7fd fae8 bl 8014d70 <__sinit> + 80177a0: 89a3 ldrh r3, [r4, #12] + 80177a2: f9b4 200c ldrsh.w r2, [r4, #12] + 80177a6: 0718 lsls r0, r3, #28 + 80177a8: d422 bmi.n 80177f0 <__swsetup_r+0x64> + 80177aa: 06d9 lsls r1, r3, #27 + 80177ac: d407 bmi.n 80177be <__swsetup_r+0x32> + 80177ae: 2309 movs r3, #9 + 80177b0: 602b str r3, [r5, #0] + 80177b2: f042 0340 orr.w r3, r2, #64 ; 0x40 + 80177b6: 81a3 strh r3, [r4, #12] + 80177b8: f04f 30ff mov.w r0, #4294967295 + 80177bc: e034 b.n 8017828 <__swsetup_r+0x9c> + 80177be: 0758 lsls r0, r3, #29 + 80177c0: d512 bpl.n 80177e8 <__swsetup_r+0x5c> + 80177c2: 6b61 ldr r1, [r4, #52] ; 0x34 + 80177c4: b141 cbz r1, 80177d8 <__swsetup_r+0x4c> + 80177c6: f104 0344 add.w r3, r4, #68 ; 0x44 + 80177ca: 4299 cmp r1, r3 + 80177cc: d002 beq.n 80177d4 <__swsetup_r+0x48> + 80177ce: 4628 mov r0, r5 + 80177d0: f7fe fb6c bl 8015eac <_free_r> + 80177d4: 2300 movs r3, #0 + 80177d6: 6363 str r3, [r4, #52] ; 0x34 + 80177d8: 89a3 ldrh r3, [r4, #12] + 80177da: f023 0324 bic.w r3, r3, #36 ; 0x24 + 80177de: 81a3 strh r3, [r4, #12] + 80177e0: 2300 movs r3, #0 + 80177e2: 6063 str r3, [r4, #4] + 80177e4: 6923 ldr r3, [r4, #16] + 80177e6: 6023 str r3, [r4, #0] + 80177e8: 89a3 ldrh r3, [r4, #12] + 80177ea: f043 0308 orr.w r3, r3, #8 + 80177ee: 81a3 strh r3, [r4, #12] + 80177f0: 6923 ldr r3, [r4, #16] + 80177f2: b94b cbnz r3, 8017808 <__swsetup_r+0x7c> + 80177f4: 89a3 ldrh r3, [r4, #12] + 80177f6: f403 7320 and.w r3, r3, #640 ; 0x280 + 80177fa: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80177fe: d003 beq.n 8017808 <__swsetup_r+0x7c> + 8017800: 4621 mov r1, r4 + 8017802: 4628 mov r0, r5 + 8017804: f000 f88c bl 8017920 <__smakebuf_r> + 8017808: 89a0 ldrh r0, [r4, #12] + 801780a: f9b4 200c ldrsh.w r2, [r4, #12] + 801780e: f010 0301 ands.w r3, r0, #1 + 8017812: d00a beq.n 801782a <__swsetup_r+0x9e> + 8017814: 2300 movs r3, #0 + 8017816: 60a3 str r3, [r4, #8] + 8017818: 6963 ldr r3, [r4, #20] + 801781a: 425b negs r3, r3 + 801781c: 61a3 str r3, [r4, #24] + 801781e: 6923 ldr r3, [r4, #16] + 8017820: b943 cbnz r3, 8017834 <__swsetup_r+0xa8> + 8017822: f010 0080 ands.w r0, r0, #128 ; 0x80 + 8017826: d1c4 bne.n 80177b2 <__swsetup_r+0x26> + 8017828: bd38 pop {r3, r4, r5, pc} + 801782a: 0781 lsls r1, r0, #30 + 801782c: bf58 it pl + 801782e: 6963 ldrpl r3, [r4, #20] + 8017830: 60a3 str r3, [r4, #8] + 8017832: e7f4 b.n 801781e <__swsetup_r+0x92> + 8017834: 2000 movs r0, #0 + 8017836: e7f7 b.n 8017828 <__swsetup_r+0x9c> + 8017838: 200002f0 .word 0x200002f0 + +0801783c <_raise_r>: + 801783c: 291f cmp r1, #31 + 801783e: b538 push {r3, r4, r5, lr} + 8017840: 4604 mov r4, r0 + 8017842: 460d mov r5, r1 + 8017844: d904 bls.n 8017850 <_raise_r+0x14> + 8017846: 2316 movs r3, #22 + 8017848: 6003 str r3, [r0, #0] + 801784a: f04f 30ff mov.w r0, #4294967295 + 801784e: bd38 pop {r3, r4, r5, pc} + 8017850: 6bc2 ldr r2, [r0, #60] ; 0x3c + 8017852: b112 cbz r2, 801785a <_raise_r+0x1e> + 8017854: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 8017858: b94b cbnz r3, 801786e <_raise_r+0x32> + 801785a: 4620 mov r0, r4 + 801785c: f000 f830 bl 80178c0 <_getpid_r> + 8017860: 462a mov r2, r5 + 8017862: 4601 mov r1, r0 + 8017864: 4620 mov r0, r4 + 8017866: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 801786a: f000 b817 b.w 801789c <_kill_r> + 801786e: 2b01 cmp r3, #1 + 8017870: d00a beq.n 8017888 <_raise_r+0x4c> + 8017872: 1c59 adds r1, r3, #1 + 8017874: d103 bne.n 801787e <_raise_r+0x42> + 8017876: 2316 movs r3, #22 + 8017878: 6003 str r3, [r0, #0] + 801787a: 2001 movs r0, #1 + 801787c: e7e7 b.n 801784e <_raise_r+0x12> + 801787e: 2400 movs r4, #0 + 8017880: f842 4025 str.w r4, [r2, r5, lsl #2] + 8017884: 4628 mov r0, r5 + 8017886: 4798 blx r3 + 8017888: 2000 movs r0, #0 + 801788a: e7e0 b.n 801784e <_raise_r+0x12> + +0801788c : + 801788c: 4b02 ldr r3, [pc, #8] ; (8017898 ) + 801788e: 4601 mov r1, r0 + 8017890: 6818 ldr r0, [r3, #0] + 8017892: f7ff bfd3 b.w 801783c <_raise_r> + 8017896: bf00 nop + 8017898: 200002f0 .word 0x200002f0 + +0801789c <_kill_r>: + 801789c: b538 push {r3, r4, r5, lr} + 801789e: 4d07 ldr r5, [pc, #28] ; (80178bc <_kill_r+0x20>) + 80178a0: 2300 movs r3, #0 + 80178a2: 4604 mov r4, r0 + 80178a4: 4608 mov r0, r1 + 80178a6: 4611 mov r1, r2 + 80178a8: 602b str r3, [r5, #0] + 80178aa: f7ed f969 bl 8004b80 <_kill> + 80178ae: 1c43 adds r3, r0, #1 + 80178b0: d102 bne.n 80178b8 <_kill_r+0x1c> + 80178b2: 682b ldr r3, [r5, #0] + 80178b4: b103 cbz r3, 80178b8 <_kill_r+0x1c> + 80178b6: 6023 str r3, [r4, #0] + 80178b8: bd38 pop {r3, r4, r5, pc} + 80178ba: bf00 nop + 80178bc: 20002388 .word 0x20002388 + +080178c0 <_getpid_r>: + 80178c0: f7ed b956 b.w 8004b70 <_getpid> + +080178c4 <_malloc_usable_size_r>: + 80178c4: f851 3c04 ldr.w r3, [r1, #-4] + 80178c8: 1f18 subs r0, r3, #4 + 80178ca: 2b00 cmp r3, #0 + 80178cc: bfbc itt lt + 80178ce: 580b ldrlt r3, [r1, r0] + 80178d0: 18c0 addlt r0, r0, r3 + 80178d2: 4770 bx lr + +080178d4 <__swhatbuf_r>: + 80178d4: b570 push {r4, r5, r6, lr} + 80178d6: 460c mov r4, r1 + 80178d8: f9b1 100e ldrsh.w r1, [r1, #14] + 80178dc: 2900 cmp r1, #0 + 80178de: b096 sub sp, #88 ; 0x58 + 80178e0: 4615 mov r5, r2 + 80178e2: 461e mov r6, r3 + 80178e4: da0d bge.n 8017902 <__swhatbuf_r+0x2e> + 80178e6: 89a3 ldrh r3, [r4, #12] + 80178e8: f013 0f80 tst.w r3, #128 ; 0x80 + 80178ec: f04f 0100 mov.w r1, #0 + 80178f0: bf0c ite eq + 80178f2: f44f 6380 moveq.w r3, #1024 ; 0x400 + 80178f6: 2340 movne r3, #64 ; 0x40 + 80178f8: 2000 movs r0, #0 + 80178fa: 6031 str r1, [r6, #0] + 80178fc: 602b str r3, [r5, #0] + 80178fe: b016 add sp, #88 ; 0x58 + 8017900: bd70 pop {r4, r5, r6, pc} + 8017902: 466a mov r2, sp + 8017904: f000 f848 bl 8017998 <_fstat_r> + 8017908: 2800 cmp r0, #0 + 801790a: dbec blt.n 80178e6 <__swhatbuf_r+0x12> + 801790c: 9901 ldr r1, [sp, #4] + 801790e: f401 4170 and.w r1, r1, #61440 ; 0xf000 + 8017912: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000 + 8017916: 4259 negs r1, r3 + 8017918: 4159 adcs r1, r3 + 801791a: f44f 6380 mov.w r3, #1024 ; 0x400 + 801791e: e7eb b.n 80178f8 <__swhatbuf_r+0x24> + +08017920 <__smakebuf_r>: + 8017920: 898b ldrh r3, [r1, #12] + 8017922: b573 push {r0, r1, r4, r5, r6, lr} + 8017924: 079d lsls r5, r3, #30 + 8017926: 4606 mov r6, r0 + 8017928: 460c mov r4, r1 + 801792a: d507 bpl.n 801793c <__smakebuf_r+0x1c> + 801792c: f104 0347 add.w r3, r4, #71 ; 0x47 + 8017930: 6023 str r3, [r4, #0] + 8017932: 6123 str r3, [r4, #16] + 8017934: 2301 movs r3, #1 + 8017936: 6163 str r3, [r4, #20] + 8017938: b002 add sp, #8 + 801793a: bd70 pop {r4, r5, r6, pc} + 801793c: ab01 add r3, sp, #4 + 801793e: 466a mov r2, sp + 8017940: f7ff ffc8 bl 80178d4 <__swhatbuf_r> + 8017944: 9900 ldr r1, [sp, #0] + 8017946: 4605 mov r5, r0 + 8017948: 4630 mov r0, r6 + 801794a: f7fb fb7b bl 8013044 <_malloc_r> + 801794e: b948 cbnz r0, 8017964 <__smakebuf_r+0x44> + 8017950: f9b4 300c ldrsh.w r3, [r4, #12] + 8017954: 059a lsls r2, r3, #22 + 8017956: d4ef bmi.n 8017938 <__smakebuf_r+0x18> + 8017958: f023 0303 bic.w r3, r3, #3 + 801795c: f043 0302 orr.w r3, r3, #2 + 8017960: 81a3 strh r3, [r4, #12] + 8017962: e7e3 b.n 801792c <__smakebuf_r+0xc> + 8017964: 89a3 ldrh r3, [r4, #12] + 8017966: 6020 str r0, [r4, #0] + 8017968: f043 0380 orr.w r3, r3, #128 ; 0x80 + 801796c: 81a3 strh r3, [r4, #12] + 801796e: 9b00 ldr r3, [sp, #0] + 8017970: 6163 str r3, [r4, #20] + 8017972: 9b01 ldr r3, [sp, #4] + 8017974: 6120 str r0, [r4, #16] + 8017976: b15b cbz r3, 8017990 <__smakebuf_r+0x70> + 8017978: f9b4 100e ldrsh.w r1, [r4, #14] + 801797c: 4630 mov r0, r6 + 801797e: f000 f81d bl 80179bc <_isatty_r> + 8017982: b128 cbz r0, 8017990 <__smakebuf_r+0x70> + 8017984: 89a3 ldrh r3, [r4, #12] + 8017986: f023 0303 bic.w r3, r3, #3 + 801798a: f043 0301 orr.w r3, r3, #1 + 801798e: 81a3 strh r3, [r4, #12] + 8017990: 89a3 ldrh r3, [r4, #12] + 8017992: 431d orrs r5, r3 + 8017994: 81a5 strh r5, [r4, #12] + 8017996: e7cf b.n 8017938 <__smakebuf_r+0x18> + +08017998 <_fstat_r>: + 8017998: b538 push {r3, r4, r5, lr} + 801799a: 4d07 ldr r5, [pc, #28] ; (80179b8 <_fstat_r+0x20>) + 801799c: 2300 movs r3, #0 + 801799e: 4604 mov r4, r0 + 80179a0: 4608 mov r0, r1 + 80179a2: 4611 mov r1, r2 + 80179a4: 602b str r3, [r5, #0] + 80179a6: f7ed f94a bl 8004c3e <_fstat> + 80179aa: 1c43 adds r3, r0, #1 + 80179ac: d102 bne.n 80179b4 <_fstat_r+0x1c> + 80179ae: 682b ldr r3, [r5, #0] + 80179b0: b103 cbz r3, 80179b4 <_fstat_r+0x1c> + 80179b2: 6023 str r3, [r4, #0] + 80179b4: bd38 pop {r3, r4, r5, pc} + 80179b6: bf00 nop + 80179b8: 20002388 .word 0x20002388 + +080179bc <_isatty_r>: + 80179bc: b538 push {r3, r4, r5, lr} + 80179be: 4d06 ldr r5, [pc, #24] ; (80179d8 <_isatty_r+0x1c>) + 80179c0: 2300 movs r3, #0 + 80179c2: 4604 mov r4, r0 + 80179c4: 4608 mov r0, r1 + 80179c6: 602b str r3, [r5, #0] + 80179c8: f7ed f949 bl 8004c5e <_isatty> + 80179cc: 1c43 adds r3, r0, #1 + 80179ce: d102 bne.n 80179d6 <_isatty_r+0x1a> + 80179d0: 682b ldr r3, [r5, #0] + 80179d2: b103 cbz r3, 80179d6 <_isatty_r+0x1a> + 80179d4: 6023 str r3, [r4, #0] + 80179d6: bd38 pop {r3, r4, r5, pc} + 80179d8: 20002388 .word 0x20002388 + 80179dc: 00000000 .word 0x00000000 + +080179e0 : + 80179e0: b51f push {r0, r1, r2, r3, r4, lr} + 80179e2: ec53 2b10 vmov r2, r3, d0 + 80179e6: 4826 ldr r0, [pc, #152] ; (8017a80 ) + 80179e8: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 + 80179ec: 4281 cmp r1, r0 + 80179ee: dc06 bgt.n 80179fe + 80179f0: ed9f 1b21 vldr d1, [pc, #132] ; 8017a78 + 80179f4: b005 add sp, #20 + 80179f6: f85d eb04 ldr.w lr, [sp], #4 + 80179fa: f000 b961 b.w 8017cc0 <__kernel_cos> + 80179fe: 4821 ldr r0, [pc, #132] ; (8017a84 ) + 8017a00: 4281 cmp r1, r0 + 8017a02: dd09 ble.n 8017a18 + 8017a04: ee10 0a10 vmov r0, s0 + 8017a08: 4619 mov r1, r3 + 8017a0a: f7e8 fc3d bl 8000288 <__aeabi_dsub> + 8017a0e: ec41 0b10 vmov d0, r0, r1 + 8017a12: b005 add sp, #20 + 8017a14: f85d fb04 ldr.w pc, [sp], #4 + 8017a18: 4668 mov r0, sp + 8017a1a: f000 fad9 bl 8017fd0 <__ieee754_rem_pio2> + 8017a1e: f000 0003 and.w r0, r0, #3 + 8017a22: 2801 cmp r0, #1 + 8017a24: d00b beq.n 8017a3e + 8017a26: 2802 cmp r0, #2 + 8017a28: d016 beq.n 8017a58 + 8017a2a: b9e0 cbnz r0, 8017a66 + 8017a2c: ed9d 1b02 vldr d1, [sp, #8] + 8017a30: ed9d 0b00 vldr d0, [sp] + 8017a34: f000 f944 bl 8017cc0 <__kernel_cos> + 8017a38: ec51 0b10 vmov r0, r1, d0 + 8017a3c: e7e7 b.n 8017a0e + 8017a3e: ed9d 1b02 vldr d1, [sp, #8] + 8017a42: ed9d 0b00 vldr d0, [sp] + 8017a46: f000 fa03 bl 8017e50 <__kernel_sin> + 8017a4a: ec53 2b10 vmov r2, r3, d0 + 8017a4e: ee10 0a10 vmov r0, s0 + 8017a52: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 8017a56: e7da b.n 8017a0e + 8017a58: ed9d 1b02 vldr d1, [sp, #8] + 8017a5c: ed9d 0b00 vldr d0, [sp] + 8017a60: f000 f92e bl 8017cc0 <__kernel_cos> + 8017a64: e7f1 b.n 8017a4a + 8017a66: ed9d 1b02 vldr d1, [sp, #8] + 8017a6a: ed9d 0b00 vldr d0, [sp] + 8017a6e: 2001 movs r0, #1 + 8017a70: f000 f9ee bl 8017e50 <__kernel_sin> + 8017a74: e7e0 b.n 8017a38 + 8017a76: bf00 nop ... - 80155d0: 3fe921fb .word 0x3fe921fb - 80155d4: 7fefffff .word 0x7fefffff - -080155d8 : - 80155d8: b51f push {r0, r1, r2, r3, r4, lr} - 80155da: ec53 2b10 vmov r2, r3, d0 - 80155de: 4828 ldr r0, [pc, #160] ; (8015680 ) - 80155e0: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 - 80155e4: 4281 cmp r1, r0 - 80155e6: dc07 bgt.n 80155f8 - 80155e8: ed9f 1b23 vldr d1, [pc, #140] ; 8015678 - 80155ec: 2000 movs r0, #0 - 80155ee: b005 add sp, #20 - 80155f0: f85d eb04 ldr.w lr, [sp], #4 - 80155f4: f000 b9d4 b.w 80159a0 <__kernel_sin> - 80155f8: 4822 ldr r0, [pc, #136] ; (8015684 ) - 80155fa: 4281 cmp r1, r0 - 80155fc: dd09 ble.n 8015612 - 80155fe: ee10 0a10 vmov r0, s0 - 8015602: 4619 mov r1, r3 - 8015604: f7ea fe40 bl 8000288 <__aeabi_dsub> - 8015608: ec41 0b10 vmov d0, r0, r1 - 801560c: b005 add sp, #20 - 801560e: f85d fb04 ldr.w pc, [sp], #4 - 8015612: 4668 mov r0, sp - 8015614: f000 fa84 bl 8015b20 <__ieee754_rem_pio2> - 8015618: f000 0003 and.w r0, r0, #3 - 801561c: 2801 cmp r0, #1 - 801561e: d00c beq.n 801563a - 8015620: 2802 cmp r0, #2 - 8015622: d011 beq.n 8015648 - 8015624: b9f0 cbnz r0, 8015664 - 8015626: ed9d 1b02 vldr d1, [sp, #8] - 801562a: ed9d 0b00 vldr d0, [sp] - 801562e: 2001 movs r0, #1 - 8015630: f000 f9b6 bl 80159a0 <__kernel_sin> - 8015634: ec51 0b10 vmov r0, r1, d0 - 8015638: e7e6 b.n 8015608 - 801563a: ed9d 1b02 vldr d1, [sp, #8] - 801563e: ed9d 0b00 vldr d0, [sp] - 8015642: f000 f8e5 bl 8015810 <__kernel_cos> - 8015646: e7f5 b.n 8015634 - 8015648: ed9d 1b02 vldr d1, [sp, #8] - 801564c: ed9d 0b00 vldr d0, [sp] - 8015650: 2001 movs r0, #1 - 8015652: f000 f9a5 bl 80159a0 <__kernel_sin> - 8015656: ec53 2b10 vmov r2, r3, d0 - 801565a: ee10 0a10 vmov r0, s0 - 801565e: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 - 8015662: e7d1 b.n 8015608 - 8015664: ed9d 1b02 vldr d1, [sp, #8] - 8015668: ed9d 0b00 vldr d0, [sp] - 801566c: f000 f8d0 bl 8015810 <__kernel_cos> - 8015670: e7f1 b.n 8015656 - 8015672: bf00 nop - 8015674: f3af 8000 nop.w + 8017a80: 3fe921fb .word 0x3fe921fb + 8017a84: 7fefffff .word 0x7fefffff + +08017a88 : + 8017a88: b51f push {r0, r1, r2, r3, r4, lr} + 8017a8a: ec53 2b10 vmov r2, r3, d0 + 8017a8e: 4828 ldr r0, [pc, #160] ; (8017b30 ) + 8017a90: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 + 8017a94: 4281 cmp r1, r0 + 8017a96: dc07 bgt.n 8017aa8 + 8017a98: ed9f 1b23 vldr d1, [pc, #140] ; 8017b28 + 8017a9c: 2000 movs r0, #0 + 8017a9e: b005 add sp, #20 + 8017aa0: f85d eb04 ldr.w lr, [sp], #4 + 8017aa4: f000 b9d4 b.w 8017e50 <__kernel_sin> + 8017aa8: 4822 ldr r0, [pc, #136] ; (8017b34 ) + 8017aaa: 4281 cmp r1, r0 + 8017aac: dd09 ble.n 8017ac2 + 8017aae: ee10 0a10 vmov r0, s0 + 8017ab2: 4619 mov r1, r3 + 8017ab4: f7e8 fbe8 bl 8000288 <__aeabi_dsub> + 8017ab8: ec41 0b10 vmov d0, r0, r1 + 8017abc: b005 add sp, #20 + 8017abe: f85d fb04 ldr.w pc, [sp], #4 + 8017ac2: 4668 mov r0, sp + 8017ac4: f000 fa84 bl 8017fd0 <__ieee754_rem_pio2> + 8017ac8: f000 0003 and.w r0, r0, #3 + 8017acc: 2801 cmp r0, #1 + 8017ace: d00c beq.n 8017aea + 8017ad0: 2802 cmp r0, #2 + 8017ad2: d011 beq.n 8017af8 + 8017ad4: b9f0 cbnz r0, 8017b14 + 8017ad6: ed9d 1b02 vldr d1, [sp, #8] + 8017ada: ed9d 0b00 vldr d0, [sp] + 8017ade: 2001 movs r0, #1 + 8017ae0: f000 f9b6 bl 8017e50 <__kernel_sin> + 8017ae4: ec51 0b10 vmov r0, r1, d0 + 8017ae8: e7e6 b.n 8017ab8 + 8017aea: ed9d 1b02 vldr d1, [sp, #8] + 8017aee: ed9d 0b00 vldr d0, [sp] + 8017af2: f000 f8e5 bl 8017cc0 <__kernel_cos> + 8017af6: e7f5 b.n 8017ae4 + 8017af8: ed9d 1b02 vldr d1, [sp, #8] + 8017afc: ed9d 0b00 vldr d0, [sp] + 8017b00: 2001 movs r0, #1 + 8017b02: f000 f9a5 bl 8017e50 <__kernel_sin> + 8017b06: ec53 2b10 vmov r2, r3, d0 + 8017b0a: ee10 0a10 vmov r0, s0 + 8017b0e: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 8017b12: e7d1 b.n 8017ab8 + 8017b14: ed9d 1b02 vldr d1, [sp, #8] + 8017b18: ed9d 0b00 vldr d0, [sp] + 8017b1c: f000 f8d0 bl 8017cc0 <__kernel_cos> + 8017b20: e7f1 b.n 8017b06 + 8017b22: bf00 nop + 8017b24: f3af 8000 nop.w ... - 8015680: 3fe921fb .word 0x3fe921fb - 8015684: 7fefffff .word 0x7fefffff - -08015688 : - 8015688: b508 push {r3, lr} - 801568a: ed2d 8b02 vpush {d8} - 801568e: eef0 8a40 vmov.f32 s17, s0 - 8015692: f000 fc55 bl 8015f40 <__ieee754_expf> - 8015696: eeb0 8a40 vmov.f32 s16, s0 - 801569a: eeb0 0a68 vmov.f32 s0, s17 - 801569e: f000 f829 bl 80156f4 - 80156a2: b160 cbz r0, 80156be - 80156a4: eddf 7a0f vldr s15, [pc, #60] ; 80156e4 - 80156a8: eef4 8ae7 vcmpe.f32 s17, s15 - 80156ac: eef1 fa10 vmrs APSR_nzcv, fpscr - 80156b0: dd0a ble.n 80156c8 - 80156b2: f7fd fab9 bl 8012c28 <__errno> - 80156b6: ed9f 8a0c vldr s16, [pc, #48] ; 80156e8 - 80156ba: 2322 movs r3, #34 ; 0x22 - 80156bc: 6003 str r3, [r0, #0] - 80156be: eeb0 0a48 vmov.f32 s0, s16 - 80156c2: ecbd 8b02 vpop {d8} - 80156c6: bd08 pop {r3, pc} - 80156c8: eddf 7a08 vldr s15, [pc, #32] ; 80156ec - 80156cc: eef4 8ae7 vcmpe.f32 s17, s15 - 80156d0: eef1 fa10 vmrs APSR_nzcv, fpscr - 80156d4: d5f3 bpl.n 80156be - 80156d6: f7fd faa7 bl 8012c28 <__errno> - 80156da: 2322 movs r3, #34 ; 0x22 - 80156dc: ed9f 8a04 vldr s16, [pc, #16] ; 80156f0 - 80156e0: 6003 str r3, [r0, #0] - 80156e2: e7ec b.n 80156be - 80156e4: 42b17217 .word 0x42b17217 - 80156e8: 7f800000 .word 0x7f800000 - 80156ec: c2cff1b5 .word 0xc2cff1b5 - 80156f0: 00000000 .word 0x00000000 - -080156f4 : - 80156f4: b082 sub sp, #8 - 80156f6: ed8d 0a01 vstr s0, [sp, #4] - 80156fa: 9801 ldr r0, [sp, #4] - 80156fc: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 - 8015700: f1b0 4fff cmp.w r0, #2139095040 ; 0x7f800000 - 8015704: bfac ite ge - 8015706: 2000 movge r0, #0 - 8015708: 2001 movlt r0, #1 - 801570a: b002 add sp, #8 - 801570c: 4770 bx lr + 8017b30: 3fe921fb .word 0x3fe921fb + 8017b34: 7fefffff .word 0x7fefffff + +08017b38 : + 8017b38: b508 push {r3, lr} + 8017b3a: ed2d 8b02 vpush {d8} + 8017b3e: eef0 8a40 vmov.f32 s17, s0 + 8017b42: f000 fc55 bl 80183f0 <__ieee754_expf> + 8017b46: eeb0 8a40 vmov.f32 s16, s0 + 8017b4a: eeb0 0a68 vmov.f32 s0, s17 + 8017b4e: f000 f829 bl 8017ba4 + 8017b52: b160 cbz r0, 8017b6e + 8017b54: eddf 7a0f vldr s15, [pc, #60] ; 8017b94 + 8017b58: eef4 8ae7 vcmpe.f32 s17, s15 + 8017b5c: eef1 fa10 vmrs APSR_nzcv, fpscr + 8017b60: dd0a ble.n 8017b78 + 8017b62: f7fd fab9 bl 80150d8 <__errno> + 8017b66: ed9f 8a0c vldr s16, [pc, #48] ; 8017b98 + 8017b6a: 2322 movs r3, #34 ; 0x22 + 8017b6c: 6003 str r3, [r0, #0] + 8017b6e: eeb0 0a48 vmov.f32 s0, s16 + 8017b72: ecbd 8b02 vpop {d8} + 8017b76: bd08 pop {r3, pc} + 8017b78: eddf 7a08 vldr s15, [pc, #32] ; 8017b9c + 8017b7c: eef4 8ae7 vcmpe.f32 s17, s15 + 8017b80: eef1 fa10 vmrs APSR_nzcv, fpscr + 8017b84: d5f3 bpl.n 8017b6e + 8017b86: f7fd faa7 bl 80150d8 <__errno> + 8017b8a: 2322 movs r3, #34 ; 0x22 + 8017b8c: ed9f 8a04 vldr s16, [pc, #16] ; 8017ba0 + 8017b90: 6003 str r3, [r0, #0] + 8017b92: e7ec b.n 8017b6e + 8017b94: 42b17217 .word 0x42b17217 + 8017b98: 7f800000 .word 0x7f800000 + 8017b9c: c2cff1b5 .word 0xc2cff1b5 + 8017ba0: 00000000 .word 0x00000000 + +08017ba4 : + 8017ba4: b082 sub sp, #8 + 8017ba6: ed8d 0a01 vstr s0, [sp, #4] + 8017baa: 9801 ldr r0, [sp, #4] + 8017bac: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 + 8017bb0: f1b0 4fff cmp.w r0, #2139095040 ; 0x7f800000 + 8017bb4: bfac ite ge + 8017bb6: 2000 movge r0, #0 + 8017bb8: 2001 movlt r0, #1 + 8017bba: b002 add sp, #8 + 8017bbc: 4770 bx lr ... -08015710 : - 8015710: ec51 0b10 vmov r0, r1, d0 - 8015714: f3c1 530a ubfx r3, r1, #20, #11 - 8015718: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 801571c: f2a3 36ff subw r6, r3, #1023 ; 0x3ff - 8015720: 2e13 cmp r6, #19 - 8015722: ee10 5a10 vmov r5, s0 - 8015726: ee10 8a10 vmov r8, s0 - 801572a: 460c mov r4, r1 - 801572c: dc31 bgt.n 8015792 - 801572e: 2e00 cmp r6, #0 - 8015730: da14 bge.n 801575c - 8015732: a333 add r3, pc, #204 ; (adr r3, 8015800 ) - 8015734: e9d3 2300 ldrd r2, r3, [r3] - 8015738: f7ea fda8 bl 800028c <__adddf3> - 801573c: 2200 movs r2, #0 - 801573e: 2300 movs r3, #0 - 8015740: f7eb f9ea bl 8000b18 <__aeabi_dcmpgt> - 8015744: b138 cbz r0, 8015756 - 8015746: 2c00 cmp r4, #0 - 8015748: da53 bge.n 80157f2 - 801574a: f024 4400 bic.w r4, r4, #2147483648 ; 0x80000000 - 801574e: 4325 orrs r5, r4 - 8015750: d052 beq.n 80157f8 - 8015752: 4c2d ldr r4, [pc, #180] ; (8015808 ) - 8015754: 2500 movs r5, #0 - 8015756: 4621 mov r1, r4 - 8015758: 4628 mov r0, r5 - 801575a: e024 b.n 80157a6 - 801575c: 4f2b ldr r7, [pc, #172] ; (801580c ) - 801575e: 4137 asrs r7, r6 - 8015760: ea01 0307 and.w r3, r1, r7 - 8015764: 4303 orrs r3, r0 - 8015766: d01e beq.n 80157a6 - 8015768: a325 add r3, pc, #148 ; (adr r3, 8015800 ) - 801576a: e9d3 2300 ldrd r2, r3, [r3] - 801576e: f7ea fd8d bl 800028c <__adddf3> - 8015772: 2200 movs r2, #0 - 8015774: 2300 movs r3, #0 - 8015776: f7eb f9cf bl 8000b18 <__aeabi_dcmpgt> - 801577a: 2800 cmp r0, #0 - 801577c: d0eb beq.n 8015756 - 801577e: 2c00 cmp r4, #0 - 8015780: bfbe ittt lt - 8015782: f44f 1380 movlt.w r3, #1048576 ; 0x100000 - 8015786: 4133 asrlt r3, r6 - 8015788: 18e4 addlt r4, r4, r3 - 801578a: ea24 0407 bic.w r4, r4, r7 - 801578e: 2500 movs r5, #0 - 8015790: e7e1 b.n 8015756 - 8015792: 2e33 cmp r6, #51 ; 0x33 - 8015794: dd0b ble.n 80157ae - 8015796: f5b6 6f80 cmp.w r6, #1024 ; 0x400 - 801579a: d104 bne.n 80157a6 - 801579c: ee10 2a10 vmov r2, s0 - 80157a0: 460b mov r3, r1 - 80157a2: f7ea fd73 bl 800028c <__adddf3> - 80157a6: ec41 0b10 vmov d0, r0, r1 - 80157aa: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 80157ae: f2a3 4313 subw r3, r3, #1043 ; 0x413 - 80157b2: f04f 37ff mov.w r7, #4294967295 - 80157b6: 40df lsrs r7, r3 - 80157b8: 4238 tst r0, r7 - 80157ba: d0f4 beq.n 80157a6 - 80157bc: a310 add r3, pc, #64 ; (adr r3, 8015800 ) - 80157be: e9d3 2300 ldrd r2, r3, [r3] - 80157c2: f7ea fd63 bl 800028c <__adddf3> - 80157c6: 2200 movs r2, #0 - 80157c8: 2300 movs r3, #0 - 80157ca: f7eb f9a5 bl 8000b18 <__aeabi_dcmpgt> - 80157ce: 2800 cmp r0, #0 - 80157d0: d0c1 beq.n 8015756 - 80157d2: 2c00 cmp r4, #0 - 80157d4: da0a bge.n 80157ec - 80157d6: 2e14 cmp r6, #20 - 80157d8: d101 bne.n 80157de - 80157da: 3401 adds r4, #1 - 80157dc: e006 b.n 80157ec - 80157de: f1c6 0634 rsb r6, r6, #52 ; 0x34 - 80157e2: 2301 movs r3, #1 - 80157e4: 40b3 lsls r3, r6 - 80157e6: 441d add r5, r3 - 80157e8: 45a8 cmp r8, r5 - 80157ea: d8f6 bhi.n 80157da - 80157ec: ea25 0507 bic.w r5, r5, r7 - 80157f0: e7b1 b.n 8015756 - 80157f2: 2500 movs r5, #0 - 80157f4: 462c mov r4, r5 - 80157f6: e7ae b.n 8015756 - 80157f8: f04f 4400 mov.w r4, #2147483648 ; 0x80000000 - 80157fc: e7ab b.n 8015756 - 80157fe: bf00 nop - 8015800: 8800759c .word 0x8800759c - 8015804: 7e37e43c .word 0x7e37e43c - 8015808: bff00000 .word 0xbff00000 - 801580c: 000fffff .word 0x000fffff - -08015810 <__kernel_cos>: - 8015810: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8015814: ec57 6b10 vmov r6, r7, d0 - 8015818: f027 4800 bic.w r8, r7, #2147483648 ; 0x80000000 - 801581c: f1b8 5f79 cmp.w r8, #1044381696 ; 0x3e400000 - 8015820: ed8d 1b00 vstr d1, [sp] - 8015824: da07 bge.n 8015836 <__kernel_cos+0x26> - 8015826: ee10 0a10 vmov r0, s0 - 801582a: 4639 mov r1, r7 - 801582c: f7eb f994 bl 8000b58 <__aeabi_d2iz> - 8015830: 2800 cmp r0, #0 - 8015832: f000 8088 beq.w 8015946 <__kernel_cos+0x136> - 8015836: 4632 mov r2, r6 - 8015838: 463b mov r3, r7 - 801583a: 4630 mov r0, r6 - 801583c: 4639 mov r1, r7 - 801583e: f7ea fedb bl 80005f8 <__aeabi_dmul> - 8015842: 4b51 ldr r3, [pc, #324] ; (8015988 <__kernel_cos+0x178>) - 8015844: 2200 movs r2, #0 - 8015846: 4604 mov r4, r0 - 8015848: 460d mov r5, r1 - 801584a: f7ea fed5 bl 80005f8 <__aeabi_dmul> - 801584e: a340 add r3, pc, #256 ; (adr r3, 8015950 <__kernel_cos+0x140>) - 8015850: e9d3 2300 ldrd r2, r3, [r3] - 8015854: 4682 mov sl, r0 - 8015856: 468b mov fp, r1 - 8015858: 4620 mov r0, r4 - 801585a: 4629 mov r1, r5 - 801585c: f7ea fecc bl 80005f8 <__aeabi_dmul> - 8015860: a33d add r3, pc, #244 ; (adr r3, 8015958 <__kernel_cos+0x148>) - 8015862: e9d3 2300 ldrd r2, r3, [r3] - 8015866: f7ea fd11 bl 800028c <__adddf3> - 801586a: 4622 mov r2, r4 - 801586c: 462b mov r3, r5 - 801586e: f7ea fec3 bl 80005f8 <__aeabi_dmul> - 8015872: a33b add r3, pc, #236 ; (adr r3, 8015960 <__kernel_cos+0x150>) - 8015874: e9d3 2300 ldrd r2, r3, [r3] - 8015878: f7ea fd06 bl 8000288 <__aeabi_dsub> - 801587c: 4622 mov r2, r4 - 801587e: 462b mov r3, r5 - 8015880: f7ea feba bl 80005f8 <__aeabi_dmul> - 8015884: a338 add r3, pc, #224 ; (adr r3, 8015968 <__kernel_cos+0x158>) - 8015886: e9d3 2300 ldrd r2, r3, [r3] - 801588a: f7ea fcff bl 800028c <__adddf3> - 801588e: 4622 mov r2, r4 - 8015890: 462b mov r3, r5 - 8015892: f7ea feb1 bl 80005f8 <__aeabi_dmul> - 8015896: a336 add r3, pc, #216 ; (adr r3, 8015970 <__kernel_cos+0x160>) - 8015898: e9d3 2300 ldrd r2, r3, [r3] - 801589c: f7ea fcf4 bl 8000288 <__aeabi_dsub> - 80158a0: 4622 mov r2, r4 - 80158a2: 462b mov r3, r5 - 80158a4: f7ea fea8 bl 80005f8 <__aeabi_dmul> - 80158a8: a333 add r3, pc, #204 ; (adr r3, 8015978 <__kernel_cos+0x168>) - 80158aa: e9d3 2300 ldrd r2, r3, [r3] - 80158ae: f7ea fced bl 800028c <__adddf3> - 80158b2: 4622 mov r2, r4 - 80158b4: 462b mov r3, r5 - 80158b6: f7ea fe9f bl 80005f8 <__aeabi_dmul> - 80158ba: 4622 mov r2, r4 - 80158bc: 462b mov r3, r5 - 80158be: f7ea fe9b bl 80005f8 <__aeabi_dmul> - 80158c2: e9dd 2300 ldrd r2, r3, [sp] - 80158c6: 4604 mov r4, r0 - 80158c8: 460d mov r5, r1 - 80158ca: 4630 mov r0, r6 - 80158cc: 4639 mov r1, r7 - 80158ce: f7ea fe93 bl 80005f8 <__aeabi_dmul> - 80158d2: 460b mov r3, r1 - 80158d4: 4602 mov r2, r0 - 80158d6: 4629 mov r1, r5 - 80158d8: 4620 mov r0, r4 - 80158da: f7ea fcd5 bl 8000288 <__aeabi_dsub> - 80158de: 4b2b ldr r3, [pc, #172] ; (801598c <__kernel_cos+0x17c>) - 80158e0: 4598 cmp r8, r3 - 80158e2: 4606 mov r6, r0 - 80158e4: 460f mov r7, r1 - 80158e6: dc10 bgt.n 801590a <__kernel_cos+0xfa> - 80158e8: 4602 mov r2, r0 - 80158ea: 460b mov r3, r1 - 80158ec: 4650 mov r0, sl - 80158ee: 4659 mov r1, fp - 80158f0: f7ea fcca bl 8000288 <__aeabi_dsub> - 80158f4: 460b mov r3, r1 - 80158f6: 4926 ldr r1, [pc, #152] ; (8015990 <__kernel_cos+0x180>) - 80158f8: 4602 mov r2, r0 - 80158fa: 2000 movs r0, #0 - 80158fc: f7ea fcc4 bl 8000288 <__aeabi_dsub> - 8015900: ec41 0b10 vmov d0, r0, r1 - 8015904: b003 add sp, #12 - 8015906: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 801590a: 4b22 ldr r3, [pc, #136] ; (8015994 <__kernel_cos+0x184>) - 801590c: 4920 ldr r1, [pc, #128] ; (8015990 <__kernel_cos+0x180>) - 801590e: 4598 cmp r8, r3 - 8015910: bfcc ite gt - 8015912: 4d21 ldrgt r5, [pc, #132] ; (8015998 <__kernel_cos+0x188>) - 8015914: f5a8 1500 suble.w r5, r8, #2097152 ; 0x200000 - 8015918: 2400 movs r4, #0 - 801591a: 4622 mov r2, r4 - 801591c: 462b mov r3, r5 - 801591e: 2000 movs r0, #0 - 8015920: f7ea fcb2 bl 8000288 <__aeabi_dsub> - 8015924: 4622 mov r2, r4 - 8015926: 4680 mov r8, r0 - 8015928: 4689 mov r9, r1 - 801592a: 462b mov r3, r5 - 801592c: 4650 mov r0, sl - 801592e: 4659 mov r1, fp - 8015930: f7ea fcaa bl 8000288 <__aeabi_dsub> - 8015934: 4632 mov r2, r6 - 8015936: 463b mov r3, r7 - 8015938: f7ea fca6 bl 8000288 <__aeabi_dsub> - 801593c: 4602 mov r2, r0 - 801593e: 460b mov r3, r1 - 8015940: 4640 mov r0, r8 - 8015942: 4649 mov r1, r9 - 8015944: e7da b.n 80158fc <__kernel_cos+0xec> - 8015946: ed9f 0b0e vldr d0, [pc, #56] ; 8015980 <__kernel_cos+0x170> - 801594a: e7db b.n 8015904 <__kernel_cos+0xf4> - 801594c: f3af 8000 nop.w - 8015950: be8838d4 .word 0xbe8838d4 - 8015954: bda8fae9 .word 0xbda8fae9 - 8015958: bdb4b1c4 .word 0xbdb4b1c4 - 801595c: 3e21ee9e .word 0x3e21ee9e - 8015960: 809c52ad .word 0x809c52ad - 8015964: 3e927e4f .word 0x3e927e4f - 8015968: 19cb1590 .word 0x19cb1590 - 801596c: 3efa01a0 .word 0x3efa01a0 - 8015970: 16c15177 .word 0x16c15177 - 8015974: 3f56c16c .word 0x3f56c16c - 8015978: 5555554c .word 0x5555554c - 801597c: 3fa55555 .word 0x3fa55555 - 8015980: 00000000 .word 0x00000000 - 8015984: 3ff00000 .word 0x3ff00000 - 8015988: 3fe00000 .word 0x3fe00000 - 801598c: 3fd33332 .word 0x3fd33332 - 8015990: 3ff00000 .word 0x3ff00000 - 8015994: 3fe90000 .word 0x3fe90000 - 8015998: 3fd20000 .word 0x3fd20000 - 801599c: 00000000 .word 0x00000000 - -080159a0 <__kernel_sin>: - 80159a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 80159a4: ed2d 8b04 vpush {d8-d9} - 80159a8: eeb0 8a41 vmov.f32 s16, s2 - 80159ac: eef0 8a61 vmov.f32 s17, s3 - 80159b0: ec55 4b10 vmov r4, r5, d0 - 80159b4: b083 sub sp, #12 - 80159b6: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 - 80159ba: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 - 80159be: 9001 str r0, [sp, #4] - 80159c0: da06 bge.n 80159d0 <__kernel_sin+0x30> - 80159c2: ee10 0a10 vmov r0, s0 - 80159c6: 4629 mov r1, r5 - 80159c8: f7eb f8c6 bl 8000b58 <__aeabi_d2iz> - 80159cc: 2800 cmp r0, #0 - 80159ce: d051 beq.n 8015a74 <__kernel_sin+0xd4> - 80159d0: 4622 mov r2, r4 - 80159d2: 462b mov r3, r5 - 80159d4: 4620 mov r0, r4 - 80159d6: 4629 mov r1, r5 - 80159d8: f7ea fe0e bl 80005f8 <__aeabi_dmul> - 80159dc: 4682 mov sl, r0 - 80159de: 468b mov fp, r1 - 80159e0: 4602 mov r2, r0 - 80159e2: 460b mov r3, r1 - 80159e4: 4620 mov r0, r4 - 80159e6: 4629 mov r1, r5 - 80159e8: f7ea fe06 bl 80005f8 <__aeabi_dmul> - 80159ec: a341 add r3, pc, #260 ; (adr r3, 8015af4 <__kernel_sin+0x154>) - 80159ee: e9d3 2300 ldrd r2, r3, [r3] - 80159f2: 4680 mov r8, r0 - 80159f4: 4689 mov r9, r1 - 80159f6: 4650 mov r0, sl - 80159f8: 4659 mov r1, fp - 80159fa: f7ea fdfd bl 80005f8 <__aeabi_dmul> - 80159fe: a33f add r3, pc, #252 ; (adr r3, 8015afc <__kernel_sin+0x15c>) - 8015a00: e9d3 2300 ldrd r2, r3, [r3] - 8015a04: f7ea fc40 bl 8000288 <__aeabi_dsub> - 8015a08: 4652 mov r2, sl - 8015a0a: 465b mov r3, fp - 8015a0c: f7ea fdf4 bl 80005f8 <__aeabi_dmul> - 8015a10: a33c add r3, pc, #240 ; (adr r3, 8015b04 <__kernel_sin+0x164>) - 8015a12: e9d3 2300 ldrd r2, r3, [r3] - 8015a16: f7ea fc39 bl 800028c <__adddf3> - 8015a1a: 4652 mov r2, sl - 8015a1c: 465b mov r3, fp - 8015a1e: f7ea fdeb bl 80005f8 <__aeabi_dmul> - 8015a22: a33a add r3, pc, #232 ; (adr r3, 8015b0c <__kernel_sin+0x16c>) - 8015a24: e9d3 2300 ldrd r2, r3, [r3] - 8015a28: f7ea fc2e bl 8000288 <__aeabi_dsub> - 8015a2c: 4652 mov r2, sl - 8015a2e: 465b mov r3, fp - 8015a30: f7ea fde2 bl 80005f8 <__aeabi_dmul> - 8015a34: a337 add r3, pc, #220 ; (adr r3, 8015b14 <__kernel_sin+0x174>) - 8015a36: e9d3 2300 ldrd r2, r3, [r3] - 8015a3a: f7ea fc27 bl 800028c <__adddf3> - 8015a3e: 9b01 ldr r3, [sp, #4] - 8015a40: 4606 mov r6, r0 - 8015a42: 460f mov r7, r1 - 8015a44: b9eb cbnz r3, 8015a82 <__kernel_sin+0xe2> - 8015a46: 4602 mov r2, r0 - 8015a48: 460b mov r3, r1 - 8015a4a: 4650 mov r0, sl - 8015a4c: 4659 mov r1, fp - 8015a4e: f7ea fdd3 bl 80005f8 <__aeabi_dmul> - 8015a52: a325 add r3, pc, #148 ; (adr r3, 8015ae8 <__kernel_sin+0x148>) - 8015a54: e9d3 2300 ldrd r2, r3, [r3] - 8015a58: f7ea fc16 bl 8000288 <__aeabi_dsub> - 8015a5c: 4642 mov r2, r8 - 8015a5e: 464b mov r3, r9 - 8015a60: f7ea fdca bl 80005f8 <__aeabi_dmul> - 8015a64: 4602 mov r2, r0 - 8015a66: 460b mov r3, r1 - 8015a68: 4620 mov r0, r4 - 8015a6a: 4629 mov r1, r5 - 8015a6c: f7ea fc0e bl 800028c <__adddf3> - 8015a70: 4604 mov r4, r0 - 8015a72: 460d mov r5, r1 - 8015a74: ec45 4b10 vmov d0, r4, r5 - 8015a78: b003 add sp, #12 - 8015a7a: ecbd 8b04 vpop {d8-d9} - 8015a7e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8015a82: 4b1b ldr r3, [pc, #108] ; (8015af0 <__kernel_sin+0x150>) - 8015a84: ec51 0b18 vmov r0, r1, d8 - 8015a88: 2200 movs r2, #0 - 8015a8a: f7ea fdb5 bl 80005f8 <__aeabi_dmul> - 8015a8e: 4632 mov r2, r6 - 8015a90: ec41 0b19 vmov d9, r0, r1 - 8015a94: 463b mov r3, r7 - 8015a96: 4640 mov r0, r8 - 8015a98: 4649 mov r1, r9 - 8015a9a: f7ea fdad bl 80005f8 <__aeabi_dmul> - 8015a9e: 4602 mov r2, r0 - 8015aa0: 460b mov r3, r1 - 8015aa2: ec51 0b19 vmov r0, r1, d9 - 8015aa6: f7ea fbef bl 8000288 <__aeabi_dsub> - 8015aaa: 4652 mov r2, sl - 8015aac: 465b mov r3, fp - 8015aae: f7ea fda3 bl 80005f8 <__aeabi_dmul> - 8015ab2: ec53 2b18 vmov r2, r3, d8 - 8015ab6: f7ea fbe7 bl 8000288 <__aeabi_dsub> - 8015aba: a30b add r3, pc, #44 ; (adr r3, 8015ae8 <__kernel_sin+0x148>) - 8015abc: e9d3 2300 ldrd r2, r3, [r3] - 8015ac0: 4606 mov r6, r0 - 8015ac2: 460f mov r7, r1 - 8015ac4: 4640 mov r0, r8 - 8015ac6: 4649 mov r1, r9 - 8015ac8: f7ea fd96 bl 80005f8 <__aeabi_dmul> - 8015acc: 4602 mov r2, r0 - 8015ace: 460b mov r3, r1 - 8015ad0: 4630 mov r0, r6 - 8015ad2: 4639 mov r1, r7 - 8015ad4: f7ea fbda bl 800028c <__adddf3> - 8015ad8: 4602 mov r2, r0 - 8015ada: 460b mov r3, r1 - 8015adc: 4620 mov r0, r4 - 8015ade: 4629 mov r1, r5 - 8015ae0: f7ea fbd2 bl 8000288 <__aeabi_dsub> - 8015ae4: e7c4 b.n 8015a70 <__kernel_sin+0xd0> - 8015ae6: bf00 nop - 8015ae8: 55555549 .word 0x55555549 - 8015aec: 3fc55555 .word 0x3fc55555 - 8015af0: 3fe00000 .word 0x3fe00000 - 8015af4: 5acfd57c .word 0x5acfd57c - 8015af8: 3de5d93a .word 0x3de5d93a - 8015afc: 8a2b9ceb .word 0x8a2b9ceb - 8015b00: 3e5ae5e6 .word 0x3e5ae5e6 - 8015b04: 57b1fe7d .word 0x57b1fe7d - 8015b08: 3ec71de3 .word 0x3ec71de3 - 8015b0c: 19c161d5 .word 0x19c161d5 - 8015b10: 3f2a01a0 .word 0x3f2a01a0 - 8015b14: 1110f8a6 .word 0x1110f8a6 - 8015b18: 3f811111 .word 0x3f811111 - 8015b1c: 00000000 .word 0x00000000 - -08015b20 <__ieee754_rem_pio2>: - 8015b20: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8015b24: ed2d 8b02 vpush {d8} - 8015b28: ec55 4b10 vmov r4, r5, d0 - 8015b2c: 4bca ldr r3, [pc, #808] ; (8015e58 <__ieee754_rem_pio2+0x338>) - 8015b2e: b08b sub sp, #44 ; 0x2c - 8015b30: f025 4800 bic.w r8, r5, #2147483648 ; 0x80000000 - 8015b34: 4598 cmp r8, r3 - 8015b36: 4682 mov sl, r0 - 8015b38: 9502 str r5, [sp, #8] - 8015b3a: dc08 bgt.n 8015b4e <__ieee754_rem_pio2+0x2e> - 8015b3c: 2200 movs r2, #0 - 8015b3e: 2300 movs r3, #0 - 8015b40: ed80 0b00 vstr d0, [r0] - 8015b44: e9c0 2302 strd r2, r3, [r0, #8] - 8015b48: f04f 0b00 mov.w fp, #0 - 8015b4c: e028 b.n 8015ba0 <__ieee754_rem_pio2+0x80> - 8015b4e: 4bc3 ldr r3, [pc, #780] ; (8015e5c <__ieee754_rem_pio2+0x33c>) - 8015b50: 4598 cmp r8, r3 - 8015b52: dc78 bgt.n 8015c46 <__ieee754_rem_pio2+0x126> - 8015b54: 9b02 ldr r3, [sp, #8] - 8015b56: 4ec2 ldr r6, [pc, #776] ; (8015e60 <__ieee754_rem_pio2+0x340>) - 8015b58: 2b00 cmp r3, #0 - 8015b5a: ee10 0a10 vmov r0, s0 - 8015b5e: a3b0 add r3, pc, #704 ; (adr r3, 8015e20 <__ieee754_rem_pio2+0x300>) - 8015b60: e9d3 2300 ldrd r2, r3, [r3] - 8015b64: 4629 mov r1, r5 - 8015b66: dd39 ble.n 8015bdc <__ieee754_rem_pio2+0xbc> - 8015b68: f7ea fb8e bl 8000288 <__aeabi_dsub> - 8015b6c: 45b0 cmp r8, r6 - 8015b6e: 4604 mov r4, r0 - 8015b70: 460d mov r5, r1 - 8015b72: d01b beq.n 8015bac <__ieee754_rem_pio2+0x8c> - 8015b74: a3ac add r3, pc, #688 ; (adr r3, 8015e28 <__ieee754_rem_pio2+0x308>) - 8015b76: e9d3 2300 ldrd r2, r3, [r3] - 8015b7a: f7ea fb85 bl 8000288 <__aeabi_dsub> - 8015b7e: 4602 mov r2, r0 - 8015b80: 460b mov r3, r1 - 8015b82: e9ca 2300 strd r2, r3, [sl] - 8015b86: 4620 mov r0, r4 - 8015b88: 4629 mov r1, r5 - 8015b8a: f7ea fb7d bl 8000288 <__aeabi_dsub> - 8015b8e: a3a6 add r3, pc, #664 ; (adr r3, 8015e28 <__ieee754_rem_pio2+0x308>) - 8015b90: e9d3 2300 ldrd r2, r3, [r3] - 8015b94: f7ea fb78 bl 8000288 <__aeabi_dsub> - 8015b98: e9ca 0102 strd r0, r1, [sl, #8] - 8015b9c: f04f 0b01 mov.w fp, #1 - 8015ba0: 4658 mov r0, fp - 8015ba2: b00b add sp, #44 ; 0x2c - 8015ba4: ecbd 8b02 vpop {d8} - 8015ba8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8015bac: a3a0 add r3, pc, #640 ; (adr r3, 8015e30 <__ieee754_rem_pio2+0x310>) - 8015bae: e9d3 2300 ldrd r2, r3, [r3] - 8015bb2: f7ea fb69 bl 8000288 <__aeabi_dsub> - 8015bb6: a3a0 add r3, pc, #640 ; (adr r3, 8015e38 <__ieee754_rem_pio2+0x318>) - 8015bb8: e9d3 2300 ldrd r2, r3, [r3] - 8015bbc: 4604 mov r4, r0 - 8015bbe: 460d mov r5, r1 - 8015bc0: f7ea fb62 bl 8000288 <__aeabi_dsub> - 8015bc4: 4602 mov r2, r0 - 8015bc6: 460b mov r3, r1 - 8015bc8: e9ca 2300 strd r2, r3, [sl] - 8015bcc: 4620 mov r0, r4 - 8015bce: 4629 mov r1, r5 - 8015bd0: f7ea fb5a bl 8000288 <__aeabi_dsub> - 8015bd4: a398 add r3, pc, #608 ; (adr r3, 8015e38 <__ieee754_rem_pio2+0x318>) - 8015bd6: e9d3 2300 ldrd r2, r3, [r3] - 8015bda: e7db b.n 8015b94 <__ieee754_rem_pio2+0x74> - 8015bdc: f7ea fb56 bl 800028c <__adddf3> - 8015be0: 45b0 cmp r8, r6 - 8015be2: 4604 mov r4, r0 - 8015be4: 460d mov r5, r1 - 8015be6: d016 beq.n 8015c16 <__ieee754_rem_pio2+0xf6> - 8015be8: a38f add r3, pc, #572 ; (adr r3, 8015e28 <__ieee754_rem_pio2+0x308>) - 8015bea: e9d3 2300 ldrd r2, r3, [r3] - 8015bee: f7ea fb4d bl 800028c <__adddf3> - 8015bf2: 4602 mov r2, r0 - 8015bf4: 460b mov r3, r1 - 8015bf6: e9ca 2300 strd r2, r3, [sl] - 8015bfa: 4620 mov r0, r4 - 8015bfc: 4629 mov r1, r5 - 8015bfe: f7ea fb43 bl 8000288 <__aeabi_dsub> - 8015c02: a389 add r3, pc, #548 ; (adr r3, 8015e28 <__ieee754_rem_pio2+0x308>) - 8015c04: e9d3 2300 ldrd r2, r3, [r3] - 8015c08: f7ea fb40 bl 800028c <__adddf3> - 8015c0c: f04f 3bff mov.w fp, #4294967295 - 8015c10: e9ca 0102 strd r0, r1, [sl, #8] - 8015c14: e7c4 b.n 8015ba0 <__ieee754_rem_pio2+0x80> - 8015c16: a386 add r3, pc, #536 ; (adr r3, 8015e30 <__ieee754_rem_pio2+0x310>) - 8015c18: e9d3 2300 ldrd r2, r3, [r3] - 8015c1c: f7ea fb36 bl 800028c <__adddf3> - 8015c20: a385 add r3, pc, #532 ; (adr r3, 8015e38 <__ieee754_rem_pio2+0x318>) - 8015c22: e9d3 2300 ldrd r2, r3, [r3] - 8015c26: 4604 mov r4, r0 - 8015c28: 460d mov r5, r1 - 8015c2a: f7ea fb2f bl 800028c <__adddf3> - 8015c2e: 4602 mov r2, r0 - 8015c30: 460b mov r3, r1 - 8015c32: e9ca 2300 strd r2, r3, [sl] - 8015c36: 4620 mov r0, r4 - 8015c38: 4629 mov r1, r5 - 8015c3a: f7ea fb25 bl 8000288 <__aeabi_dsub> - 8015c3e: a37e add r3, pc, #504 ; (adr r3, 8015e38 <__ieee754_rem_pio2+0x318>) - 8015c40: e9d3 2300 ldrd r2, r3, [r3] - 8015c44: e7e0 b.n 8015c08 <__ieee754_rem_pio2+0xe8> - 8015c46: 4b87 ldr r3, [pc, #540] ; (8015e64 <__ieee754_rem_pio2+0x344>) - 8015c48: 4598 cmp r8, r3 - 8015c4a: f300 80d8 bgt.w 8015dfe <__ieee754_rem_pio2+0x2de> - 8015c4e: f000 f96d bl 8015f2c - 8015c52: ec55 4b10 vmov r4, r5, d0 - 8015c56: ee10 0a10 vmov r0, s0 - 8015c5a: a379 add r3, pc, #484 ; (adr r3, 8015e40 <__ieee754_rem_pio2+0x320>) - 8015c5c: e9d3 2300 ldrd r2, r3, [r3] - 8015c60: 4629 mov r1, r5 - 8015c62: f7ea fcc9 bl 80005f8 <__aeabi_dmul> - 8015c66: 4b80 ldr r3, [pc, #512] ; (8015e68 <__ieee754_rem_pio2+0x348>) - 8015c68: 2200 movs r2, #0 - 8015c6a: f7ea fb0f bl 800028c <__adddf3> - 8015c6e: f7ea ff73 bl 8000b58 <__aeabi_d2iz> - 8015c72: 4683 mov fp, r0 - 8015c74: f7ea fc56 bl 8000524 <__aeabi_i2d> - 8015c78: 4602 mov r2, r0 - 8015c7a: 460b mov r3, r1 - 8015c7c: ec43 2b18 vmov d8, r2, r3 - 8015c80: a367 add r3, pc, #412 ; (adr r3, 8015e20 <__ieee754_rem_pio2+0x300>) - 8015c82: e9d3 2300 ldrd r2, r3, [r3] - 8015c86: f7ea fcb7 bl 80005f8 <__aeabi_dmul> - 8015c8a: 4602 mov r2, r0 - 8015c8c: 460b mov r3, r1 - 8015c8e: 4620 mov r0, r4 - 8015c90: 4629 mov r1, r5 - 8015c92: f7ea faf9 bl 8000288 <__aeabi_dsub> - 8015c96: a364 add r3, pc, #400 ; (adr r3, 8015e28 <__ieee754_rem_pio2+0x308>) - 8015c98: e9d3 2300 ldrd r2, r3, [r3] - 8015c9c: 4606 mov r6, r0 - 8015c9e: 460f mov r7, r1 - 8015ca0: ec51 0b18 vmov r0, r1, d8 - 8015ca4: f7ea fca8 bl 80005f8 <__aeabi_dmul> - 8015ca8: f1bb 0f1f cmp.w fp, #31 - 8015cac: 4604 mov r4, r0 - 8015cae: 460d mov r5, r1 - 8015cb0: dc0d bgt.n 8015cce <__ieee754_rem_pio2+0x1ae> - 8015cb2: 4b6e ldr r3, [pc, #440] ; (8015e6c <__ieee754_rem_pio2+0x34c>) - 8015cb4: f10b 32ff add.w r2, fp, #4294967295 - 8015cb8: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8015cbc: 4543 cmp r3, r8 - 8015cbe: d006 beq.n 8015cce <__ieee754_rem_pio2+0x1ae> - 8015cc0: 4622 mov r2, r4 - 8015cc2: 462b mov r3, r5 - 8015cc4: 4630 mov r0, r6 - 8015cc6: 4639 mov r1, r7 - 8015cc8: f7ea fade bl 8000288 <__aeabi_dsub> - 8015ccc: e00e b.n 8015cec <__ieee754_rem_pio2+0x1cc> - 8015cce: 462b mov r3, r5 - 8015cd0: 4622 mov r2, r4 - 8015cd2: 4630 mov r0, r6 - 8015cd4: 4639 mov r1, r7 - 8015cd6: f7ea fad7 bl 8000288 <__aeabi_dsub> - 8015cda: ea4f 5328 mov.w r3, r8, asr #20 - 8015cde: 9303 str r3, [sp, #12] - 8015ce0: f3c1 530a ubfx r3, r1, #20, #11 - 8015ce4: ebc3 5318 rsb r3, r3, r8, lsr #20 - 8015ce8: 2b10 cmp r3, #16 - 8015cea: dc02 bgt.n 8015cf2 <__ieee754_rem_pio2+0x1d2> - 8015cec: e9ca 0100 strd r0, r1, [sl] - 8015cf0: e039 b.n 8015d66 <__ieee754_rem_pio2+0x246> - 8015cf2: a34f add r3, pc, #316 ; (adr r3, 8015e30 <__ieee754_rem_pio2+0x310>) - 8015cf4: e9d3 2300 ldrd r2, r3, [r3] - 8015cf8: ec51 0b18 vmov r0, r1, d8 - 8015cfc: f7ea fc7c bl 80005f8 <__aeabi_dmul> - 8015d00: 4604 mov r4, r0 - 8015d02: 460d mov r5, r1 - 8015d04: 4602 mov r2, r0 - 8015d06: 460b mov r3, r1 - 8015d08: 4630 mov r0, r6 - 8015d0a: 4639 mov r1, r7 - 8015d0c: f7ea fabc bl 8000288 <__aeabi_dsub> - 8015d10: 4602 mov r2, r0 - 8015d12: 460b mov r3, r1 - 8015d14: 4680 mov r8, r0 - 8015d16: 4689 mov r9, r1 - 8015d18: 4630 mov r0, r6 - 8015d1a: 4639 mov r1, r7 - 8015d1c: f7ea fab4 bl 8000288 <__aeabi_dsub> - 8015d20: 4622 mov r2, r4 - 8015d22: 462b mov r3, r5 - 8015d24: f7ea fab0 bl 8000288 <__aeabi_dsub> - 8015d28: a343 add r3, pc, #268 ; (adr r3, 8015e38 <__ieee754_rem_pio2+0x318>) - 8015d2a: e9d3 2300 ldrd r2, r3, [r3] - 8015d2e: 4604 mov r4, r0 - 8015d30: 460d mov r5, r1 - 8015d32: ec51 0b18 vmov r0, r1, d8 - 8015d36: f7ea fc5f bl 80005f8 <__aeabi_dmul> - 8015d3a: 4622 mov r2, r4 - 8015d3c: 462b mov r3, r5 - 8015d3e: f7ea faa3 bl 8000288 <__aeabi_dsub> - 8015d42: 4602 mov r2, r0 - 8015d44: 460b mov r3, r1 - 8015d46: 4604 mov r4, r0 - 8015d48: 460d mov r5, r1 - 8015d4a: 4640 mov r0, r8 - 8015d4c: 4649 mov r1, r9 - 8015d4e: f7ea fa9b bl 8000288 <__aeabi_dsub> - 8015d52: 9a03 ldr r2, [sp, #12] - 8015d54: f3c1 530a ubfx r3, r1, #20, #11 - 8015d58: 1ad3 subs r3, r2, r3 - 8015d5a: 2b31 cmp r3, #49 ; 0x31 - 8015d5c: dc24 bgt.n 8015da8 <__ieee754_rem_pio2+0x288> - 8015d5e: e9ca 0100 strd r0, r1, [sl] - 8015d62: 4646 mov r6, r8 - 8015d64: 464f mov r7, r9 - 8015d66: e9da 8900 ldrd r8, r9, [sl] - 8015d6a: 4630 mov r0, r6 - 8015d6c: 4642 mov r2, r8 - 8015d6e: 464b mov r3, r9 - 8015d70: 4639 mov r1, r7 - 8015d72: f7ea fa89 bl 8000288 <__aeabi_dsub> - 8015d76: 462b mov r3, r5 - 8015d78: 4622 mov r2, r4 - 8015d7a: f7ea fa85 bl 8000288 <__aeabi_dsub> - 8015d7e: 9b02 ldr r3, [sp, #8] - 8015d80: 2b00 cmp r3, #0 - 8015d82: e9ca 0102 strd r0, r1, [sl, #8] - 8015d86: f6bf af0b bge.w 8015ba0 <__ieee754_rem_pio2+0x80> - 8015d8a: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 - 8015d8e: f8ca 3004 str.w r3, [sl, #4] - 8015d92: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8015d96: f8ca 8000 str.w r8, [sl] - 8015d9a: f8ca 0008 str.w r0, [sl, #8] - 8015d9e: f8ca 300c str.w r3, [sl, #12] - 8015da2: f1cb 0b00 rsb fp, fp, #0 - 8015da6: e6fb b.n 8015ba0 <__ieee754_rem_pio2+0x80> - 8015da8: a327 add r3, pc, #156 ; (adr r3, 8015e48 <__ieee754_rem_pio2+0x328>) - 8015daa: e9d3 2300 ldrd r2, r3, [r3] - 8015dae: ec51 0b18 vmov r0, r1, d8 - 8015db2: f7ea fc21 bl 80005f8 <__aeabi_dmul> - 8015db6: 4604 mov r4, r0 - 8015db8: 460d mov r5, r1 - 8015dba: 4602 mov r2, r0 - 8015dbc: 460b mov r3, r1 - 8015dbe: 4640 mov r0, r8 - 8015dc0: 4649 mov r1, r9 - 8015dc2: f7ea fa61 bl 8000288 <__aeabi_dsub> - 8015dc6: 4602 mov r2, r0 - 8015dc8: 460b mov r3, r1 - 8015dca: 4606 mov r6, r0 - 8015dcc: 460f mov r7, r1 - 8015dce: 4640 mov r0, r8 - 8015dd0: 4649 mov r1, r9 - 8015dd2: f7ea fa59 bl 8000288 <__aeabi_dsub> - 8015dd6: 4622 mov r2, r4 - 8015dd8: 462b mov r3, r5 - 8015dda: f7ea fa55 bl 8000288 <__aeabi_dsub> - 8015dde: a31c add r3, pc, #112 ; (adr r3, 8015e50 <__ieee754_rem_pio2+0x330>) - 8015de0: e9d3 2300 ldrd r2, r3, [r3] - 8015de4: 4604 mov r4, r0 - 8015de6: 460d mov r5, r1 - 8015de8: ec51 0b18 vmov r0, r1, d8 - 8015dec: f7ea fc04 bl 80005f8 <__aeabi_dmul> - 8015df0: 4622 mov r2, r4 - 8015df2: 462b mov r3, r5 - 8015df4: f7ea fa48 bl 8000288 <__aeabi_dsub> - 8015df8: 4604 mov r4, r0 - 8015dfa: 460d mov r5, r1 - 8015dfc: e760 b.n 8015cc0 <__ieee754_rem_pio2+0x1a0> - 8015dfe: 4b1c ldr r3, [pc, #112] ; (8015e70 <__ieee754_rem_pio2+0x350>) - 8015e00: 4598 cmp r8, r3 - 8015e02: dd37 ble.n 8015e74 <__ieee754_rem_pio2+0x354> - 8015e04: ee10 2a10 vmov r2, s0 - 8015e08: 462b mov r3, r5 - 8015e0a: 4620 mov r0, r4 - 8015e0c: 4629 mov r1, r5 - 8015e0e: f7ea fa3b bl 8000288 <__aeabi_dsub> - 8015e12: e9ca 0102 strd r0, r1, [sl, #8] - 8015e16: e9ca 0100 strd r0, r1, [sl] - 8015e1a: e695 b.n 8015b48 <__ieee754_rem_pio2+0x28> - 8015e1c: f3af 8000 nop.w - 8015e20: 54400000 .word 0x54400000 - 8015e24: 3ff921fb .word 0x3ff921fb - 8015e28: 1a626331 .word 0x1a626331 - 8015e2c: 3dd0b461 .word 0x3dd0b461 - 8015e30: 1a600000 .word 0x1a600000 - 8015e34: 3dd0b461 .word 0x3dd0b461 - 8015e38: 2e037073 .word 0x2e037073 - 8015e3c: 3ba3198a .word 0x3ba3198a - 8015e40: 6dc9c883 .word 0x6dc9c883 - 8015e44: 3fe45f30 .word 0x3fe45f30 - 8015e48: 2e000000 .word 0x2e000000 - 8015e4c: 3ba3198a .word 0x3ba3198a - 8015e50: 252049c1 .word 0x252049c1 - 8015e54: 397b839a .word 0x397b839a - 8015e58: 3fe921fb .word 0x3fe921fb - 8015e5c: 4002d97b .word 0x4002d97b - 8015e60: 3ff921fb .word 0x3ff921fb - 8015e64: 413921fb .word 0x413921fb - 8015e68: 3fe00000 .word 0x3fe00000 - 8015e6c: 08018b98 .word 0x08018b98 - 8015e70: 7fefffff .word 0x7fefffff - 8015e74: ea4f 5628 mov.w r6, r8, asr #20 - 8015e78: f2a6 4616 subw r6, r6, #1046 ; 0x416 - 8015e7c: eba8 5106 sub.w r1, r8, r6, lsl #20 - 8015e80: 4620 mov r0, r4 - 8015e82: 460d mov r5, r1 - 8015e84: f7ea fe68 bl 8000b58 <__aeabi_d2iz> - 8015e88: f7ea fb4c bl 8000524 <__aeabi_i2d> - 8015e8c: 4602 mov r2, r0 - 8015e8e: 460b mov r3, r1 - 8015e90: 4620 mov r0, r4 - 8015e92: 4629 mov r1, r5 - 8015e94: e9cd 2304 strd r2, r3, [sp, #16] - 8015e98: f7ea f9f6 bl 8000288 <__aeabi_dsub> - 8015e9c: 4b21 ldr r3, [pc, #132] ; (8015f24 <__ieee754_rem_pio2+0x404>) - 8015e9e: 2200 movs r2, #0 - 8015ea0: f7ea fbaa bl 80005f8 <__aeabi_dmul> - 8015ea4: 460d mov r5, r1 - 8015ea6: 4604 mov r4, r0 - 8015ea8: f7ea fe56 bl 8000b58 <__aeabi_d2iz> - 8015eac: f7ea fb3a bl 8000524 <__aeabi_i2d> - 8015eb0: 4602 mov r2, r0 - 8015eb2: 460b mov r3, r1 - 8015eb4: 4620 mov r0, r4 - 8015eb6: 4629 mov r1, r5 - 8015eb8: e9cd 2306 strd r2, r3, [sp, #24] - 8015ebc: f7ea f9e4 bl 8000288 <__aeabi_dsub> - 8015ec0: 4b18 ldr r3, [pc, #96] ; (8015f24 <__ieee754_rem_pio2+0x404>) - 8015ec2: 2200 movs r2, #0 - 8015ec4: f7ea fb98 bl 80005f8 <__aeabi_dmul> - 8015ec8: e9cd 0108 strd r0, r1, [sp, #32] - 8015ecc: f10d 0828 add.w r8, sp, #40 ; 0x28 - 8015ed0: 2703 movs r7, #3 - 8015ed2: 2400 movs r4, #0 - 8015ed4: 2500 movs r5, #0 - 8015ed6: e978 0102 ldrd r0, r1, [r8, #-8]! - 8015eda: 4622 mov r2, r4 - 8015edc: 462b mov r3, r5 - 8015ede: 46b9 mov r9, r7 - 8015ee0: 3f01 subs r7, #1 - 8015ee2: f7ea fdf1 bl 8000ac8 <__aeabi_dcmpeq> - 8015ee6: 2800 cmp r0, #0 - 8015ee8: d1f5 bne.n 8015ed6 <__ieee754_rem_pio2+0x3b6> - 8015eea: 4b0f ldr r3, [pc, #60] ; (8015f28 <__ieee754_rem_pio2+0x408>) - 8015eec: 9301 str r3, [sp, #4] - 8015eee: 2302 movs r3, #2 - 8015ef0: 9300 str r3, [sp, #0] - 8015ef2: 4632 mov r2, r6 - 8015ef4: 464b mov r3, r9 - 8015ef6: 4651 mov r1, sl - 8015ef8: a804 add r0, sp, #16 - 8015efa: f000 f911 bl 8016120 <__kernel_rem_pio2> - 8015efe: 9b02 ldr r3, [sp, #8] - 8015f00: 2b00 cmp r3, #0 - 8015f02: 4683 mov fp, r0 - 8015f04: f6bf ae4c bge.w 8015ba0 <__ieee754_rem_pio2+0x80> - 8015f08: e9da 2100 ldrd r2, r1, [sl] - 8015f0c: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8015f10: e9ca 2300 strd r2, r3, [sl] - 8015f14: e9da 2102 ldrd r2, r1, [sl, #8] - 8015f18: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8015f1c: e9ca 2302 strd r2, r3, [sl, #8] - 8015f20: e73f b.n 8015da2 <__ieee754_rem_pio2+0x282> - 8015f22: bf00 nop - 8015f24: 41700000 .word 0x41700000 - 8015f28: 08018c18 .word 0x08018c18 - -08015f2c : - 8015f2c: ec51 0b10 vmov r0, r1, d0 - 8015f30: ee10 2a10 vmov r2, s0 - 8015f34: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 - 8015f38: ec43 2b10 vmov d0, r2, r3 - 8015f3c: 4770 bx lr +08017bc0 : + 8017bc0: ec51 0b10 vmov r0, r1, d0 + 8017bc4: f3c1 530a ubfx r3, r1, #20, #11 + 8017bc8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8017bcc: f2a3 36ff subw r6, r3, #1023 ; 0x3ff + 8017bd0: 2e13 cmp r6, #19 + 8017bd2: ee10 5a10 vmov r5, s0 + 8017bd6: ee10 8a10 vmov r8, s0 + 8017bda: 460c mov r4, r1 + 8017bdc: dc31 bgt.n 8017c42 + 8017bde: 2e00 cmp r6, #0 + 8017be0: da14 bge.n 8017c0c + 8017be2: a333 add r3, pc, #204 ; (adr r3, 8017cb0 ) + 8017be4: e9d3 2300 ldrd r2, r3, [r3] + 8017be8: f7e8 fb50 bl 800028c <__adddf3> + 8017bec: 2200 movs r2, #0 + 8017bee: 2300 movs r3, #0 + 8017bf0: f7e8 ff92 bl 8000b18 <__aeabi_dcmpgt> + 8017bf4: b138 cbz r0, 8017c06 + 8017bf6: 2c00 cmp r4, #0 + 8017bf8: da53 bge.n 8017ca2 + 8017bfa: f024 4400 bic.w r4, r4, #2147483648 ; 0x80000000 + 8017bfe: 4325 orrs r5, r4 + 8017c00: d052 beq.n 8017ca8 + 8017c02: 4c2d ldr r4, [pc, #180] ; (8017cb8 ) + 8017c04: 2500 movs r5, #0 + 8017c06: 4621 mov r1, r4 + 8017c08: 4628 mov r0, r5 + 8017c0a: e024 b.n 8017c56 + 8017c0c: 4f2b ldr r7, [pc, #172] ; (8017cbc ) + 8017c0e: 4137 asrs r7, r6 + 8017c10: ea01 0307 and.w r3, r1, r7 + 8017c14: 4303 orrs r3, r0 + 8017c16: d01e beq.n 8017c56 + 8017c18: a325 add r3, pc, #148 ; (adr r3, 8017cb0 ) + 8017c1a: e9d3 2300 ldrd r2, r3, [r3] + 8017c1e: f7e8 fb35 bl 800028c <__adddf3> + 8017c22: 2200 movs r2, #0 + 8017c24: 2300 movs r3, #0 + 8017c26: f7e8 ff77 bl 8000b18 <__aeabi_dcmpgt> + 8017c2a: 2800 cmp r0, #0 + 8017c2c: d0eb beq.n 8017c06 + 8017c2e: 2c00 cmp r4, #0 + 8017c30: bfbe ittt lt + 8017c32: f44f 1380 movlt.w r3, #1048576 ; 0x100000 + 8017c36: 4133 asrlt r3, r6 + 8017c38: 18e4 addlt r4, r4, r3 + 8017c3a: ea24 0407 bic.w r4, r4, r7 + 8017c3e: 2500 movs r5, #0 + 8017c40: e7e1 b.n 8017c06 + 8017c42: 2e33 cmp r6, #51 ; 0x33 + 8017c44: dd0b ble.n 8017c5e + 8017c46: f5b6 6f80 cmp.w r6, #1024 ; 0x400 + 8017c4a: d104 bne.n 8017c56 + 8017c4c: ee10 2a10 vmov r2, s0 + 8017c50: 460b mov r3, r1 + 8017c52: f7e8 fb1b bl 800028c <__adddf3> + 8017c56: ec41 0b10 vmov d0, r0, r1 + 8017c5a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8017c5e: f2a3 4313 subw r3, r3, #1043 ; 0x413 + 8017c62: f04f 37ff mov.w r7, #4294967295 + 8017c66: 40df lsrs r7, r3 + 8017c68: 4238 tst r0, r7 + 8017c6a: d0f4 beq.n 8017c56 + 8017c6c: a310 add r3, pc, #64 ; (adr r3, 8017cb0 ) + 8017c6e: e9d3 2300 ldrd r2, r3, [r3] + 8017c72: f7e8 fb0b bl 800028c <__adddf3> + 8017c76: 2200 movs r2, #0 + 8017c78: 2300 movs r3, #0 + 8017c7a: f7e8 ff4d bl 8000b18 <__aeabi_dcmpgt> + 8017c7e: 2800 cmp r0, #0 + 8017c80: d0c1 beq.n 8017c06 + 8017c82: 2c00 cmp r4, #0 + 8017c84: da0a bge.n 8017c9c + 8017c86: 2e14 cmp r6, #20 + 8017c88: d101 bne.n 8017c8e + 8017c8a: 3401 adds r4, #1 + 8017c8c: e006 b.n 8017c9c + 8017c8e: f1c6 0634 rsb r6, r6, #52 ; 0x34 + 8017c92: 2301 movs r3, #1 + 8017c94: 40b3 lsls r3, r6 + 8017c96: 441d add r5, r3 + 8017c98: 45a8 cmp r8, r5 + 8017c9a: d8f6 bhi.n 8017c8a + 8017c9c: ea25 0507 bic.w r5, r5, r7 + 8017ca0: e7b1 b.n 8017c06 + 8017ca2: 2500 movs r5, #0 + 8017ca4: 462c mov r4, r5 + 8017ca6: e7ae b.n 8017c06 + 8017ca8: f04f 4400 mov.w r4, #2147483648 ; 0x80000000 + 8017cac: e7ab b.n 8017c06 + 8017cae: bf00 nop + 8017cb0: 8800759c .word 0x8800759c + 8017cb4: 7e37e43c .word 0x7e37e43c + 8017cb8: bff00000 .word 0xbff00000 + 8017cbc: 000fffff .word 0x000fffff + +08017cc0 <__kernel_cos>: + 8017cc0: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8017cc4: ec57 6b10 vmov r6, r7, d0 + 8017cc8: f027 4800 bic.w r8, r7, #2147483648 ; 0x80000000 + 8017ccc: f1b8 5f79 cmp.w r8, #1044381696 ; 0x3e400000 + 8017cd0: ed8d 1b00 vstr d1, [sp] + 8017cd4: da07 bge.n 8017ce6 <__kernel_cos+0x26> + 8017cd6: ee10 0a10 vmov r0, s0 + 8017cda: 4639 mov r1, r7 + 8017cdc: f7e8 ff3c bl 8000b58 <__aeabi_d2iz> + 8017ce0: 2800 cmp r0, #0 + 8017ce2: f000 8088 beq.w 8017df6 <__kernel_cos+0x136> + 8017ce6: 4632 mov r2, r6 + 8017ce8: 463b mov r3, r7 + 8017cea: 4630 mov r0, r6 + 8017cec: 4639 mov r1, r7 + 8017cee: f7e8 fc83 bl 80005f8 <__aeabi_dmul> + 8017cf2: 4b51 ldr r3, [pc, #324] ; (8017e38 <__kernel_cos+0x178>) + 8017cf4: 2200 movs r2, #0 + 8017cf6: 4604 mov r4, r0 + 8017cf8: 460d mov r5, r1 + 8017cfa: f7e8 fc7d bl 80005f8 <__aeabi_dmul> + 8017cfe: a340 add r3, pc, #256 ; (adr r3, 8017e00 <__kernel_cos+0x140>) + 8017d00: e9d3 2300 ldrd r2, r3, [r3] + 8017d04: 4682 mov sl, r0 + 8017d06: 468b mov fp, r1 + 8017d08: 4620 mov r0, r4 + 8017d0a: 4629 mov r1, r5 + 8017d0c: f7e8 fc74 bl 80005f8 <__aeabi_dmul> + 8017d10: a33d add r3, pc, #244 ; (adr r3, 8017e08 <__kernel_cos+0x148>) + 8017d12: e9d3 2300 ldrd r2, r3, [r3] + 8017d16: f7e8 fab9 bl 800028c <__adddf3> + 8017d1a: 4622 mov r2, r4 + 8017d1c: 462b mov r3, r5 + 8017d1e: f7e8 fc6b bl 80005f8 <__aeabi_dmul> + 8017d22: a33b add r3, pc, #236 ; (adr r3, 8017e10 <__kernel_cos+0x150>) + 8017d24: e9d3 2300 ldrd r2, r3, [r3] + 8017d28: f7e8 faae bl 8000288 <__aeabi_dsub> + 8017d2c: 4622 mov r2, r4 + 8017d2e: 462b mov r3, r5 + 8017d30: f7e8 fc62 bl 80005f8 <__aeabi_dmul> + 8017d34: a338 add r3, pc, #224 ; (adr r3, 8017e18 <__kernel_cos+0x158>) + 8017d36: e9d3 2300 ldrd r2, r3, [r3] + 8017d3a: f7e8 faa7 bl 800028c <__adddf3> + 8017d3e: 4622 mov r2, r4 + 8017d40: 462b mov r3, r5 + 8017d42: f7e8 fc59 bl 80005f8 <__aeabi_dmul> + 8017d46: a336 add r3, pc, #216 ; (adr r3, 8017e20 <__kernel_cos+0x160>) + 8017d48: e9d3 2300 ldrd r2, r3, [r3] + 8017d4c: f7e8 fa9c bl 8000288 <__aeabi_dsub> + 8017d50: 4622 mov r2, r4 + 8017d52: 462b mov r3, r5 + 8017d54: f7e8 fc50 bl 80005f8 <__aeabi_dmul> + 8017d58: a333 add r3, pc, #204 ; (adr r3, 8017e28 <__kernel_cos+0x168>) + 8017d5a: e9d3 2300 ldrd r2, r3, [r3] + 8017d5e: f7e8 fa95 bl 800028c <__adddf3> + 8017d62: 4622 mov r2, r4 + 8017d64: 462b mov r3, r5 + 8017d66: f7e8 fc47 bl 80005f8 <__aeabi_dmul> + 8017d6a: 4622 mov r2, r4 + 8017d6c: 462b mov r3, r5 + 8017d6e: f7e8 fc43 bl 80005f8 <__aeabi_dmul> + 8017d72: e9dd 2300 ldrd r2, r3, [sp] + 8017d76: 4604 mov r4, r0 + 8017d78: 460d mov r5, r1 + 8017d7a: 4630 mov r0, r6 + 8017d7c: 4639 mov r1, r7 + 8017d7e: f7e8 fc3b bl 80005f8 <__aeabi_dmul> + 8017d82: 460b mov r3, r1 + 8017d84: 4602 mov r2, r0 + 8017d86: 4629 mov r1, r5 + 8017d88: 4620 mov r0, r4 + 8017d8a: f7e8 fa7d bl 8000288 <__aeabi_dsub> + 8017d8e: 4b2b ldr r3, [pc, #172] ; (8017e3c <__kernel_cos+0x17c>) + 8017d90: 4598 cmp r8, r3 + 8017d92: 4606 mov r6, r0 + 8017d94: 460f mov r7, r1 + 8017d96: dc10 bgt.n 8017dba <__kernel_cos+0xfa> + 8017d98: 4602 mov r2, r0 + 8017d9a: 460b mov r3, r1 + 8017d9c: 4650 mov r0, sl + 8017d9e: 4659 mov r1, fp + 8017da0: f7e8 fa72 bl 8000288 <__aeabi_dsub> + 8017da4: 460b mov r3, r1 + 8017da6: 4926 ldr r1, [pc, #152] ; (8017e40 <__kernel_cos+0x180>) + 8017da8: 4602 mov r2, r0 + 8017daa: 2000 movs r0, #0 + 8017dac: f7e8 fa6c bl 8000288 <__aeabi_dsub> + 8017db0: ec41 0b10 vmov d0, r0, r1 + 8017db4: b003 add sp, #12 + 8017db6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8017dba: 4b22 ldr r3, [pc, #136] ; (8017e44 <__kernel_cos+0x184>) + 8017dbc: 4920 ldr r1, [pc, #128] ; (8017e40 <__kernel_cos+0x180>) + 8017dbe: 4598 cmp r8, r3 + 8017dc0: bfcc ite gt + 8017dc2: 4d21 ldrgt r5, [pc, #132] ; (8017e48 <__kernel_cos+0x188>) + 8017dc4: f5a8 1500 suble.w r5, r8, #2097152 ; 0x200000 + 8017dc8: 2400 movs r4, #0 + 8017dca: 4622 mov r2, r4 + 8017dcc: 462b mov r3, r5 + 8017dce: 2000 movs r0, #0 + 8017dd0: f7e8 fa5a bl 8000288 <__aeabi_dsub> + 8017dd4: 4622 mov r2, r4 + 8017dd6: 4680 mov r8, r0 + 8017dd8: 4689 mov r9, r1 + 8017dda: 462b mov r3, r5 + 8017ddc: 4650 mov r0, sl + 8017dde: 4659 mov r1, fp + 8017de0: f7e8 fa52 bl 8000288 <__aeabi_dsub> + 8017de4: 4632 mov r2, r6 + 8017de6: 463b mov r3, r7 + 8017de8: f7e8 fa4e bl 8000288 <__aeabi_dsub> + 8017dec: 4602 mov r2, r0 + 8017dee: 460b mov r3, r1 + 8017df0: 4640 mov r0, r8 + 8017df2: 4649 mov r1, r9 + 8017df4: e7da b.n 8017dac <__kernel_cos+0xec> + 8017df6: ed9f 0b0e vldr d0, [pc, #56] ; 8017e30 <__kernel_cos+0x170> + 8017dfa: e7db b.n 8017db4 <__kernel_cos+0xf4> + 8017dfc: f3af 8000 nop.w + 8017e00: be8838d4 .word 0xbe8838d4 + 8017e04: bda8fae9 .word 0xbda8fae9 + 8017e08: bdb4b1c4 .word 0xbdb4b1c4 + 8017e0c: 3e21ee9e .word 0x3e21ee9e + 8017e10: 809c52ad .word 0x809c52ad + 8017e14: 3e927e4f .word 0x3e927e4f + 8017e18: 19cb1590 .word 0x19cb1590 + 8017e1c: 3efa01a0 .word 0x3efa01a0 + 8017e20: 16c15177 .word 0x16c15177 + 8017e24: 3f56c16c .word 0x3f56c16c + 8017e28: 5555554c .word 0x5555554c + 8017e2c: 3fa55555 .word 0x3fa55555 + 8017e30: 00000000 .word 0x00000000 + 8017e34: 3ff00000 .word 0x3ff00000 + 8017e38: 3fe00000 .word 0x3fe00000 + 8017e3c: 3fd33332 .word 0x3fd33332 + 8017e40: 3ff00000 .word 0x3ff00000 + 8017e44: 3fe90000 .word 0x3fe90000 + 8017e48: 3fd20000 .word 0x3fd20000 + 8017e4c: 00000000 .word 0x00000000 + +08017e50 <__kernel_sin>: + 8017e50: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8017e54: ed2d 8b04 vpush {d8-d9} + 8017e58: eeb0 8a41 vmov.f32 s16, s2 + 8017e5c: eef0 8a61 vmov.f32 s17, s3 + 8017e60: ec55 4b10 vmov r4, r5, d0 + 8017e64: b083 sub sp, #12 + 8017e66: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 8017e6a: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 + 8017e6e: 9001 str r0, [sp, #4] + 8017e70: da06 bge.n 8017e80 <__kernel_sin+0x30> + 8017e72: ee10 0a10 vmov r0, s0 + 8017e76: 4629 mov r1, r5 + 8017e78: f7e8 fe6e bl 8000b58 <__aeabi_d2iz> + 8017e7c: 2800 cmp r0, #0 + 8017e7e: d051 beq.n 8017f24 <__kernel_sin+0xd4> + 8017e80: 4622 mov r2, r4 + 8017e82: 462b mov r3, r5 + 8017e84: 4620 mov r0, r4 + 8017e86: 4629 mov r1, r5 + 8017e88: f7e8 fbb6 bl 80005f8 <__aeabi_dmul> + 8017e8c: 4682 mov sl, r0 + 8017e8e: 468b mov fp, r1 + 8017e90: 4602 mov r2, r0 + 8017e92: 460b mov r3, r1 + 8017e94: 4620 mov r0, r4 + 8017e96: 4629 mov r1, r5 + 8017e98: f7e8 fbae bl 80005f8 <__aeabi_dmul> + 8017e9c: a341 add r3, pc, #260 ; (adr r3, 8017fa4 <__kernel_sin+0x154>) + 8017e9e: e9d3 2300 ldrd r2, r3, [r3] + 8017ea2: 4680 mov r8, r0 + 8017ea4: 4689 mov r9, r1 + 8017ea6: 4650 mov r0, sl + 8017ea8: 4659 mov r1, fp + 8017eaa: f7e8 fba5 bl 80005f8 <__aeabi_dmul> + 8017eae: a33f add r3, pc, #252 ; (adr r3, 8017fac <__kernel_sin+0x15c>) + 8017eb0: e9d3 2300 ldrd r2, r3, [r3] + 8017eb4: f7e8 f9e8 bl 8000288 <__aeabi_dsub> + 8017eb8: 4652 mov r2, sl + 8017eba: 465b mov r3, fp + 8017ebc: f7e8 fb9c bl 80005f8 <__aeabi_dmul> + 8017ec0: a33c add r3, pc, #240 ; (adr r3, 8017fb4 <__kernel_sin+0x164>) + 8017ec2: e9d3 2300 ldrd r2, r3, [r3] + 8017ec6: f7e8 f9e1 bl 800028c <__adddf3> + 8017eca: 4652 mov r2, sl + 8017ecc: 465b mov r3, fp + 8017ece: f7e8 fb93 bl 80005f8 <__aeabi_dmul> + 8017ed2: a33a add r3, pc, #232 ; (adr r3, 8017fbc <__kernel_sin+0x16c>) + 8017ed4: e9d3 2300 ldrd r2, r3, [r3] + 8017ed8: f7e8 f9d6 bl 8000288 <__aeabi_dsub> + 8017edc: 4652 mov r2, sl + 8017ede: 465b mov r3, fp + 8017ee0: f7e8 fb8a bl 80005f8 <__aeabi_dmul> + 8017ee4: a337 add r3, pc, #220 ; (adr r3, 8017fc4 <__kernel_sin+0x174>) + 8017ee6: e9d3 2300 ldrd r2, r3, [r3] + 8017eea: f7e8 f9cf bl 800028c <__adddf3> + 8017eee: 9b01 ldr r3, [sp, #4] + 8017ef0: 4606 mov r6, r0 + 8017ef2: 460f mov r7, r1 + 8017ef4: b9eb cbnz r3, 8017f32 <__kernel_sin+0xe2> + 8017ef6: 4602 mov r2, r0 + 8017ef8: 460b mov r3, r1 + 8017efa: 4650 mov r0, sl + 8017efc: 4659 mov r1, fp + 8017efe: f7e8 fb7b bl 80005f8 <__aeabi_dmul> + 8017f02: a325 add r3, pc, #148 ; (adr r3, 8017f98 <__kernel_sin+0x148>) + 8017f04: e9d3 2300 ldrd r2, r3, [r3] + 8017f08: f7e8 f9be bl 8000288 <__aeabi_dsub> + 8017f0c: 4642 mov r2, r8 + 8017f0e: 464b mov r3, r9 + 8017f10: f7e8 fb72 bl 80005f8 <__aeabi_dmul> + 8017f14: 4602 mov r2, r0 + 8017f16: 460b mov r3, r1 + 8017f18: 4620 mov r0, r4 + 8017f1a: 4629 mov r1, r5 + 8017f1c: f7e8 f9b6 bl 800028c <__adddf3> + 8017f20: 4604 mov r4, r0 + 8017f22: 460d mov r5, r1 + 8017f24: ec45 4b10 vmov d0, r4, r5 + 8017f28: b003 add sp, #12 + 8017f2a: ecbd 8b04 vpop {d8-d9} + 8017f2e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8017f32: 4b1b ldr r3, [pc, #108] ; (8017fa0 <__kernel_sin+0x150>) + 8017f34: ec51 0b18 vmov r0, r1, d8 + 8017f38: 2200 movs r2, #0 + 8017f3a: f7e8 fb5d bl 80005f8 <__aeabi_dmul> + 8017f3e: 4632 mov r2, r6 + 8017f40: ec41 0b19 vmov d9, r0, r1 + 8017f44: 463b mov r3, r7 + 8017f46: 4640 mov r0, r8 + 8017f48: 4649 mov r1, r9 + 8017f4a: f7e8 fb55 bl 80005f8 <__aeabi_dmul> + 8017f4e: 4602 mov r2, r0 + 8017f50: 460b mov r3, r1 + 8017f52: ec51 0b19 vmov r0, r1, d9 + 8017f56: f7e8 f997 bl 8000288 <__aeabi_dsub> + 8017f5a: 4652 mov r2, sl + 8017f5c: 465b mov r3, fp + 8017f5e: f7e8 fb4b bl 80005f8 <__aeabi_dmul> + 8017f62: ec53 2b18 vmov r2, r3, d8 + 8017f66: f7e8 f98f bl 8000288 <__aeabi_dsub> + 8017f6a: a30b add r3, pc, #44 ; (adr r3, 8017f98 <__kernel_sin+0x148>) + 8017f6c: e9d3 2300 ldrd r2, r3, [r3] + 8017f70: 4606 mov r6, r0 + 8017f72: 460f mov r7, r1 + 8017f74: 4640 mov r0, r8 + 8017f76: 4649 mov r1, r9 + 8017f78: f7e8 fb3e bl 80005f8 <__aeabi_dmul> + 8017f7c: 4602 mov r2, r0 + 8017f7e: 460b mov r3, r1 + 8017f80: 4630 mov r0, r6 + 8017f82: 4639 mov r1, r7 + 8017f84: f7e8 f982 bl 800028c <__adddf3> + 8017f88: 4602 mov r2, r0 + 8017f8a: 460b mov r3, r1 + 8017f8c: 4620 mov r0, r4 + 8017f8e: 4629 mov r1, r5 + 8017f90: f7e8 f97a bl 8000288 <__aeabi_dsub> + 8017f94: e7c4 b.n 8017f20 <__kernel_sin+0xd0> + 8017f96: bf00 nop + 8017f98: 55555549 .word 0x55555549 + 8017f9c: 3fc55555 .word 0x3fc55555 + 8017fa0: 3fe00000 .word 0x3fe00000 + 8017fa4: 5acfd57c .word 0x5acfd57c + 8017fa8: 3de5d93a .word 0x3de5d93a + 8017fac: 8a2b9ceb .word 0x8a2b9ceb + 8017fb0: 3e5ae5e6 .word 0x3e5ae5e6 + 8017fb4: 57b1fe7d .word 0x57b1fe7d + 8017fb8: 3ec71de3 .word 0x3ec71de3 + 8017fbc: 19c161d5 .word 0x19c161d5 + 8017fc0: 3f2a01a0 .word 0x3f2a01a0 + 8017fc4: 1110f8a6 .word 0x1110f8a6 + 8017fc8: 3f811111 .word 0x3f811111 + 8017fcc: 00000000 .word 0x00000000 + +08017fd0 <__ieee754_rem_pio2>: + 8017fd0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8017fd4: ed2d 8b02 vpush {d8} + 8017fd8: ec55 4b10 vmov r4, r5, d0 + 8017fdc: 4bca ldr r3, [pc, #808] ; (8018308 <__ieee754_rem_pio2+0x338>) + 8017fde: b08b sub sp, #44 ; 0x2c + 8017fe0: f025 4800 bic.w r8, r5, #2147483648 ; 0x80000000 + 8017fe4: 4598 cmp r8, r3 + 8017fe6: 4682 mov sl, r0 + 8017fe8: 9502 str r5, [sp, #8] + 8017fea: dc08 bgt.n 8017ffe <__ieee754_rem_pio2+0x2e> + 8017fec: 2200 movs r2, #0 + 8017fee: 2300 movs r3, #0 + 8017ff0: ed80 0b00 vstr d0, [r0] + 8017ff4: e9c0 2302 strd r2, r3, [r0, #8] + 8017ff8: f04f 0b00 mov.w fp, #0 + 8017ffc: e028 b.n 8018050 <__ieee754_rem_pio2+0x80> + 8017ffe: 4bc3 ldr r3, [pc, #780] ; (801830c <__ieee754_rem_pio2+0x33c>) + 8018000: 4598 cmp r8, r3 + 8018002: dc78 bgt.n 80180f6 <__ieee754_rem_pio2+0x126> + 8018004: 9b02 ldr r3, [sp, #8] + 8018006: 4ec2 ldr r6, [pc, #776] ; (8018310 <__ieee754_rem_pio2+0x340>) + 8018008: 2b00 cmp r3, #0 + 801800a: ee10 0a10 vmov r0, s0 + 801800e: a3b0 add r3, pc, #704 ; (adr r3, 80182d0 <__ieee754_rem_pio2+0x300>) + 8018010: e9d3 2300 ldrd r2, r3, [r3] + 8018014: 4629 mov r1, r5 + 8018016: dd39 ble.n 801808c <__ieee754_rem_pio2+0xbc> + 8018018: f7e8 f936 bl 8000288 <__aeabi_dsub> + 801801c: 45b0 cmp r8, r6 + 801801e: 4604 mov r4, r0 + 8018020: 460d mov r5, r1 + 8018022: d01b beq.n 801805c <__ieee754_rem_pio2+0x8c> + 8018024: a3ac add r3, pc, #688 ; (adr r3, 80182d8 <__ieee754_rem_pio2+0x308>) + 8018026: e9d3 2300 ldrd r2, r3, [r3] + 801802a: f7e8 f92d bl 8000288 <__aeabi_dsub> + 801802e: 4602 mov r2, r0 + 8018030: 460b mov r3, r1 + 8018032: e9ca 2300 strd r2, r3, [sl] + 8018036: 4620 mov r0, r4 + 8018038: 4629 mov r1, r5 + 801803a: f7e8 f925 bl 8000288 <__aeabi_dsub> + 801803e: a3a6 add r3, pc, #664 ; (adr r3, 80182d8 <__ieee754_rem_pio2+0x308>) + 8018040: e9d3 2300 ldrd r2, r3, [r3] + 8018044: f7e8 f920 bl 8000288 <__aeabi_dsub> + 8018048: e9ca 0102 strd r0, r1, [sl, #8] + 801804c: f04f 0b01 mov.w fp, #1 + 8018050: 4658 mov r0, fp + 8018052: b00b add sp, #44 ; 0x2c + 8018054: ecbd 8b02 vpop {d8} + 8018058: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 801805c: a3a0 add r3, pc, #640 ; (adr r3, 80182e0 <__ieee754_rem_pio2+0x310>) + 801805e: e9d3 2300 ldrd r2, r3, [r3] + 8018062: f7e8 f911 bl 8000288 <__aeabi_dsub> + 8018066: a3a0 add r3, pc, #640 ; (adr r3, 80182e8 <__ieee754_rem_pio2+0x318>) + 8018068: e9d3 2300 ldrd r2, r3, [r3] + 801806c: 4604 mov r4, r0 + 801806e: 460d mov r5, r1 + 8018070: f7e8 f90a bl 8000288 <__aeabi_dsub> + 8018074: 4602 mov r2, r0 + 8018076: 460b mov r3, r1 + 8018078: e9ca 2300 strd r2, r3, [sl] + 801807c: 4620 mov r0, r4 + 801807e: 4629 mov r1, r5 + 8018080: f7e8 f902 bl 8000288 <__aeabi_dsub> + 8018084: a398 add r3, pc, #608 ; (adr r3, 80182e8 <__ieee754_rem_pio2+0x318>) + 8018086: e9d3 2300 ldrd r2, r3, [r3] + 801808a: e7db b.n 8018044 <__ieee754_rem_pio2+0x74> + 801808c: f7e8 f8fe bl 800028c <__adddf3> + 8018090: 45b0 cmp r8, r6 + 8018092: 4604 mov r4, r0 + 8018094: 460d mov r5, r1 + 8018096: d016 beq.n 80180c6 <__ieee754_rem_pio2+0xf6> + 8018098: a38f add r3, pc, #572 ; (adr r3, 80182d8 <__ieee754_rem_pio2+0x308>) + 801809a: e9d3 2300 ldrd r2, r3, [r3] + 801809e: f7e8 f8f5 bl 800028c <__adddf3> + 80180a2: 4602 mov r2, r0 + 80180a4: 460b mov r3, r1 + 80180a6: e9ca 2300 strd r2, r3, [sl] + 80180aa: 4620 mov r0, r4 + 80180ac: 4629 mov r1, r5 + 80180ae: f7e8 f8eb bl 8000288 <__aeabi_dsub> + 80180b2: a389 add r3, pc, #548 ; (adr r3, 80182d8 <__ieee754_rem_pio2+0x308>) + 80180b4: e9d3 2300 ldrd r2, r3, [r3] + 80180b8: f7e8 f8e8 bl 800028c <__adddf3> + 80180bc: f04f 3bff mov.w fp, #4294967295 + 80180c0: e9ca 0102 strd r0, r1, [sl, #8] + 80180c4: e7c4 b.n 8018050 <__ieee754_rem_pio2+0x80> + 80180c6: a386 add r3, pc, #536 ; (adr r3, 80182e0 <__ieee754_rem_pio2+0x310>) + 80180c8: e9d3 2300 ldrd r2, r3, [r3] + 80180cc: f7e8 f8de bl 800028c <__adddf3> + 80180d0: a385 add r3, pc, #532 ; (adr r3, 80182e8 <__ieee754_rem_pio2+0x318>) + 80180d2: e9d3 2300 ldrd r2, r3, [r3] + 80180d6: 4604 mov r4, r0 + 80180d8: 460d mov r5, r1 + 80180da: f7e8 f8d7 bl 800028c <__adddf3> + 80180de: 4602 mov r2, r0 + 80180e0: 460b mov r3, r1 + 80180e2: e9ca 2300 strd r2, r3, [sl] + 80180e6: 4620 mov r0, r4 + 80180e8: 4629 mov r1, r5 + 80180ea: f7e8 f8cd bl 8000288 <__aeabi_dsub> + 80180ee: a37e add r3, pc, #504 ; (adr r3, 80182e8 <__ieee754_rem_pio2+0x318>) + 80180f0: e9d3 2300 ldrd r2, r3, [r3] + 80180f4: e7e0 b.n 80180b8 <__ieee754_rem_pio2+0xe8> + 80180f6: 4b87 ldr r3, [pc, #540] ; (8018314 <__ieee754_rem_pio2+0x344>) + 80180f8: 4598 cmp r8, r3 + 80180fa: f300 80d8 bgt.w 80182ae <__ieee754_rem_pio2+0x2de> + 80180fe: f000 f96d bl 80183dc + 8018102: ec55 4b10 vmov r4, r5, d0 + 8018106: ee10 0a10 vmov r0, s0 + 801810a: a379 add r3, pc, #484 ; (adr r3, 80182f0 <__ieee754_rem_pio2+0x320>) + 801810c: e9d3 2300 ldrd r2, r3, [r3] + 8018110: 4629 mov r1, r5 + 8018112: f7e8 fa71 bl 80005f8 <__aeabi_dmul> + 8018116: 4b80 ldr r3, [pc, #512] ; (8018318 <__ieee754_rem_pio2+0x348>) + 8018118: 2200 movs r2, #0 + 801811a: f7e8 f8b7 bl 800028c <__adddf3> + 801811e: f7e8 fd1b bl 8000b58 <__aeabi_d2iz> + 8018122: 4683 mov fp, r0 + 8018124: f7e8 f9fe bl 8000524 <__aeabi_i2d> + 8018128: 4602 mov r2, r0 + 801812a: 460b mov r3, r1 + 801812c: ec43 2b18 vmov d8, r2, r3 + 8018130: a367 add r3, pc, #412 ; (adr r3, 80182d0 <__ieee754_rem_pio2+0x300>) + 8018132: e9d3 2300 ldrd r2, r3, [r3] + 8018136: f7e8 fa5f bl 80005f8 <__aeabi_dmul> + 801813a: 4602 mov r2, r0 + 801813c: 460b mov r3, r1 + 801813e: 4620 mov r0, r4 + 8018140: 4629 mov r1, r5 + 8018142: f7e8 f8a1 bl 8000288 <__aeabi_dsub> + 8018146: a364 add r3, pc, #400 ; (adr r3, 80182d8 <__ieee754_rem_pio2+0x308>) + 8018148: e9d3 2300 ldrd r2, r3, [r3] + 801814c: 4606 mov r6, r0 + 801814e: 460f mov r7, r1 + 8018150: ec51 0b18 vmov r0, r1, d8 + 8018154: f7e8 fa50 bl 80005f8 <__aeabi_dmul> + 8018158: f1bb 0f1f cmp.w fp, #31 + 801815c: 4604 mov r4, r0 + 801815e: 460d mov r5, r1 + 8018160: dc0d bgt.n 801817e <__ieee754_rem_pio2+0x1ae> + 8018162: 4b6e ldr r3, [pc, #440] ; (801831c <__ieee754_rem_pio2+0x34c>) + 8018164: f10b 32ff add.w r2, fp, #4294967295 + 8018168: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801816c: 4543 cmp r3, r8 + 801816e: d006 beq.n 801817e <__ieee754_rem_pio2+0x1ae> + 8018170: 4622 mov r2, r4 + 8018172: 462b mov r3, r5 + 8018174: 4630 mov r0, r6 + 8018176: 4639 mov r1, r7 + 8018178: f7e8 f886 bl 8000288 <__aeabi_dsub> + 801817c: e00e b.n 801819c <__ieee754_rem_pio2+0x1cc> + 801817e: 462b mov r3, r5 + 8018180: 4622 mov r2, r4 + 8018182: 4630 mov r0, r6 + 8018184: 4639 mov r1, r7 + 8018186: f7e8 f87f bl 8000288 <__aeabi_dsub> + 801818a: ea4f 5328 mov.w r3, r8, asr #20 + 801818e: 9303 str r3, [sp, #12] + 8018190: f3c1 530a ubfx r3, r1, #20, #11 + 8018194: ebc3 5318 rsb r3, r3, r8, lsr #20 + 8018198: 2b10 cmp r3, #16 + 801819a: dc02 bgt.n 80181a2 <__ieee754_rem_pio2+0x1d2> + 801819c: e9ca 0100 strd r0, r1, [sl] + 80181a0: e039 b.n 8018216 <__ieee754_rem_pio2+0x246> + 80181a2: a34f add r3, pc, #316 ; (adr r3, 80182e0 <__ieee754_rem_pio2+0x310>) + 80181a4: e9d3 2300 ldrd r2, r3, [r3] + 80181a8: ec51 0b18 vmov r0, r1, d8 + 80181ac: f7e8 fa24 bl 80005f8 <__aeabi_dmul> + 80181b0: 4604 mov r4, r0 + 80181b2: 460d mov r5, r1 + 80181b4: 4602 mov r2, r0 + 80181b6: 460b mov r3, r1 + 80181b8: 4630 mov r0, r6 + 80181ba: 4639 mov r1, r7 + 80181bc: f7e8 f864 bl 8000288 <__aeabi_dsub> + 80181c0: 4602 mov r2, r0 + 80181c2: 460b mov r3, r1 + 80181c4: 4680 mov r8, r0 + 80181c6: 4689 mov r9, r1 + 80181c8: 4630 mov r0, r6 + 80181ca: 4639 mov r1, r7 + 80181cc: f7e8 f85c bl 8000288 <__aeabi_dsub> + 80181d0: 4622 mov r2, r4 + 80181d2: 462b mov r3, r5 + 80181d4: f7e8 f858 bl 8000288 <__aeabi_dsub> + 80181d8: a343 add r3, pc, #268 ; (adr r3, 80182e8 <__ieee754_rem_pio2+0x318>) + 80181da: e9d3 2300 ldrd r2, r3, [r3] + 80181de: 4604 mov r4, r0 + 80181e0: 460d mov r5, r1 + 80181e2: ec51 0b18 vmov r0, r1, d8 + 80181e6: f7e8 fa07 bl 80005f8 <__aeabi_dmul> + 80181ea: 4622 mov r2, r4 + 80181ec: 462b mov r3, r5 + 80181ee: f7e8 f84b bl 8000288 <__aeabi_dsub> + 80181f2: 4602 mov r2, r0 + 80181f4: 460b mov r3, r1 + 80181f6: 4604 mov r4, r0 + 80181f8: 460d mov r5, r1 + 80181fa: 4640 mov r0, r8 + 80181fc: 4649 mov r1, r9 + 80181fe: f7e8 f843 bl 8000288 <__aeabi_dsub> + 8018202: 9a03 ldr r2, [sp, #12] + 8018204: f3c1 530a ubfx r3, r1, #20, #11 + 8018208: 1ad3 subs r3, r2, r3 + 801820a: 2b31 cmp r3, #49 ; 0x31 + 801820c: dc24 bgt.n 8018258 <__ieee754_rem_pio2+0x288> + 801820e: e9ca 0100 strd r0, r1, [sl] + 8018212: 4646 mov r6, r8 + 8018214: 464f mov r7, r9 + 8018216: e9da 8900 ldrd r8, r9, [sl] + 801821a: 4630 mov r0, r6 + 801821c: 4642 mov r2, r8 + 801821e: 464b mov r3, r9 + 8018220: 4639 mov r1, r7 + 8018222: f7e8 f831 bl 8000288 <__aeabi_dsub> + 8018226: 462b mov r3, r5 + 8018228: 4622 mov r2, r4 + 801822a: f7e8 f82d bl 8000288 <__aeabi_dsub> + 801822e: 9b02 ldr r3, [sp, #8] + 8018230: 2b00 cmp r3, #0 + 8018232: e9ca 0102 strd r0, r1, [sl, #8] + 8018236: f6bf af0b bge.w 8018050 <__ieee754_rem_pio2+0x80> + 801823a: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 + 801823e: f8ca 3004 str.w r3, [sl, #4] + 8018242: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8018246: f8ca 8000 str.w r8, [sl] + 801824a: f8ca 0008 str.w r0, [sl, #8] + 801824e: f8ca 300c str.w r3, [sl, #12] + 8018252: f1cb 0b00 rsb fp, fp, #0 + 8018256: e6fb b.n 8018050 <__ieee754_rem_pio2+0x80> + 8018258: a327 add r3, pc, #156 ; (adr r3, 80182f8 <__ieee754_rem_pio2+0x328>) + 801825a: e9d3 2300 ldrd r2, r3, [r3] + 801825e: ec51 0b18 vmov r0, r1, d8 + 8018262: f7e8 f9c9 bl 80005f8 <__aeabi_dmul> + 8018266: 4604 mov r4, r0 + 8018268: 460d mov r5, r1 + 801826a: 4602 mov r2, r0 + 801826c: 460b mov r3, r1 + 801826e: 4640 mov r0, r8 + 8018270: 4649 mov r1, r9 + 8018272: f7e8 f809 bl 8000288 <__aeabi_dsub> + 8018276: 4602 mov r2, r0 + 8018278: 460b mov r3, r1 + 801827a: 4606 mov r6, r0 + 801827c: 460f mov r7, r1 + 801827e: 4640 mov r0, r8 + 8018280: 4649 mov r1, r9 + 8018282: f7e8 f801 bl 8000288 <__aeabi_dsub> + 8018286: 4622 mov r2, r4 + 8018288: 462b mov r3, r5 + 801828a: f7e7 fffd bl 8000288 <__aeabi_dsub> + 801828e: a31c add r3, pc, #112 ; (adr r3, 8018300 <__ieee754_rem_pio2+0x330>) + 8018290: e9d3 2300 ldrd r2, r3, [r3] + 8018294: 4604 mov r4, r0 + 8018296: 460d mov r5, r1 + 8018298: ec51 0b18 vmov r0, r1, d8 + 801829c: f7e8 f9ac bl 80005f8 <__aeabi_dmul> + 80182a0: 4622 mov r2, r4 + 80182a2: 462b mov r3, r5 + 80182a4: f7e7 fff0 bl 8000288 <__aeabi_dsub> + 80182a8: 4604 mov r4, r0 + 80182aa: 460d mov r5, r1 + 80182ac: e760 b.n 8018170 <__ieee754_rem_pio2+0x1a0> + 80182ae: 4b1c ldr r3, [pc, #112] ; (8018320 <__ieee754_rem_pio2+0x350>) + 80182b0: 4598 cmp r8, r3 + 80182b2: dd37 ble.n 8018324 <__ieee754_rem_pio2+0x354> + 80182b4: ee10 2a10 vmov r2, s0 + 80182b8: 462b mov r3, r5 + 80182ba: 4620 mov r0, r4 + 80182bc: 4629 mov r1, r5 + 80182be: f7e7 ffe3 bl 8000288 <__aeabi_dsub> + 80182c2: e9ca 0102 strd r0, r1, [sl, #8] + 80182c6: e9ca 0100 strd r0, r1, [sl] + 80182ca: e695 b.n 8017ff8 <__ieee754_rem_pio2+0x28> + 80182cc: f3af 8000 nop.w + 80182d0: 54400000 .word 0x54400000 + 80182d4: 3ff921fb .word 0x3ff921fb + 80182d8: 1a626331 .word 0x1a626331 + 80182dc: 3dd0b461 .word 0x3dd0b461 + 80182e0: 1a600000 .word 0x1a600000 + 80182e4: 3dd0b461 .word 0x3dd0b461 + 80182e8: 2e037073 .word 0x2e037073 + 80182ec: 3ba3198a .word 0x3ba3198a + 80182f0: 6dc9c883 .word 0x6dc9c883 + 80182f4: 3fe45f30 .word 0x3fe45f30 + 80182f8: 2e000000 .word 0x2e000000 + 80182fc: 3ba3198a .word 0x3ba3198a + 8018300: 252049c1 .word 0x252049c1 + 8018304: 397b839a .word 0x397b839a + 8018308: 3fe921fb .word 0x3fe921fb + 801830c: 4002d97b .word 0x4002d97b + 8018310: 3ff921fb .word 0x3ff921fb + 8018314: 413921fb .word 0x413921fb + 8018318: 3fe00000 .word 0x3fe00000 + 801831c: 0801b070 .word 0x0801b070 + 8018320: 7fefffff .word 0x7fefffff + 8018324: ea4f 5628 mov.w r6, r8, asr #20 + 8018328: f2a6 4616 subw r6, r6, #1046 ; 0x416 + 801832c: eba8 5106 sub.w r1, r8, r6, lsl #20 + 8018330: 4620 mov r0, r4 + 8018332: 460d mov r5, r1 + 8018334: f7e8 fc10 bl 8000b58 <__aeabi_d2iz> + 8018338: f7e8 f8f4 bl 8000524 <__aeabi_i2d> + 801833c: 4602 mov r2, r0 + 801833e: 460b mov r3, r1 + 8018340: 4620 mov r0, r4 + 8018342: 4629 mov r1, r5 + 8018344: e9cd 2304 strd r2, r3, [sp, #16] + 8018348: f7e7 ff9e bl 8000288 <__aeabi_dsub> + 801834c: 4b21 ldr r3, [pc, #132] ; (80183d4 <__ieee754_rem_pio2+0x404>) + 801834e: 2200 movs r2, #0 + 8018350: f7e8 f952 bl 80005f8 <__aeabi_dmul> + 8018354: 460d mov r5, r1 + 8018356: 4604 mov r4, r0 + 8018358: f7e8 fbfe bl 8000b58 <__aeabi_d2iz> + 801835c: f7e8 f8e2 bl 8000524 <__aeabi_i2d> + 8018360: 4602 mov r2, r0 + 8018362: 460b mov r3, r1 + 8018364: 4620 mov r0, r4 + 8018366: 4629 mov r1, r5 + 8018368: e9cd 2306 strd r2, r3, [sp, #24] + 801836c: f7e7 ff8c bl 8000288 <__aeabi_dsub> + 8018370: 4b18 ldr r3, [pc, #96] ; (80183d4 <__ieee754_rem_pio2+0x404>) + 8018372: 2200 movs r2, #0 + 8018374: f7e8 f940 bl 80005f8 <__aeabi_dmul> + 8018378: e9cd 0108 strd r0, r1, [sp, #32] + 801837c: f10d 0828 add.w r8, sp, #40 ; 0x28 + 8018380: 2703 movs r7, #3 + 8018382: 2400 movs r4, #0 + 8018384: 2500 movs r5, #0 + 8018386: e978 0102 ldrd r0, r1, [r8, #-8]! + 801838a: 4622 mov r2, r4 + 801838c: 462b mov r3, r5 + 801838e: 46b9 mov r9, r7 + 8018390: 3f01 subs r7, #1 + 8018392: f7e8 fb99 bl 8000ac8 <__aeabi_dcmpeq> + 8018396: 2800 cmp r0, #0 + 8018398: d1f5 bne.n 8018386 <__ieee754_rem_pio2+0x3b6> + 801839a: 4b0f ldr r3, [pc, #60] ; (80183d8 <__ieee754_rem_pio2+0x408>) + 801839c: 9301 str r3, [sp, #4] + 801839e: 2302 movs r3, #2 + 80183a0: 9300 str r3, [sp, #0] + 80183a2: 4632 mov r2, r6 + 80183a4: 464b mov r3, r9 + 80183a6: 4651 mov r1, sl + 80183a8: a804 add r0, sp, #16 + 80183aa: f000 f911 bl 80185d0 <__kernel_rem_pio2> + 80183ae: 9b02 ldr r3, [sp, #8] + 80183b0: 2b00 cmp r3, #0 + 80183b2: 4683 mov fp, r0 + 80183b4: f6bf ae4c bge.w 8018050 <__ieee754_rem_pio2+0x80> + 80183b8: e9da 2100 ldrd r2, r1, [sl] + 80183bc: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 80183c0: e9ca 2300 strd r2, r3, [sl] + 80183c4: e9da 2102 ldrd r2, r1, [sl, #8] + 80183c8: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 80183cc: e9ca 2302 strd r2, r3, [sl, #8] + 80183d0: e73f b.n 8018252 <__ieee754_rem_pio2+0x282> + 80183d2: bf00 nop + 80183d4: 41700000 .word 0x41700000 + 80183d8: 0801b0f0 .word 0x0801b0f0 + +080183dc : + 80183dc: ec51 0b10 vmov r0, r1, d0 + 80183e0: ee10 2a10 vmov r2, s0 + 80183e4: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 80183e8: ec43 2b10 vmov d0, r2, r3 + 80183ec: 4770 bx lr ... -08015f40 <__ieee754_expf>: - 8015f40: ee10 2a10 vmov r2, s0 - 8015f44: f022 4300 bic.w r3, r2, #2147483648 ; 0x80000000 - 8015f48: f1b3 4fff cmp.w r3, #2139095040 ; 0x7f800000 - 8015f4c: d902 bls.n 8015f54 <__ieee754_expf+0x14> - 8015f4e: ee30 0a00 vadd.f32 s0, s0, s0 - 8015f52: 4770 bx lr - 8015f54: ea4f 71d2 mov.w r1, r2, lsr #31 - 8015f58: d106 bne.n 8015f68 <__ieee754_expf+0x28> - 8015f5a: eddf 7a4e vldr s15, [pc, #312] ; 8016094 <__ieee754_expf+0x154> - 8015f5e: 2900 cmp r1, #0 - 8015f60: bf18 it ne - 8015f62: eeb0 0a67 vmovne.f32 s0, s15 - 8015f66: 4770 bx lr - 8015f68: 484b ldr r0, [pc, #300] ; (8016098 <__ieee754_expf+0x158>) - 8015f6a: 4282 cmp r2, r0 - 8015f6c: dd02 ble.n 8015f74 <__ieee754_expf+0x34> - 8015f6e: 2000 movs r0, #0 - 8015f70: f000 b8d0 b.w 8016114 <__math_oflowf> - 8015f74: 2a00 cmp r2, #0 - 8015f76: da05 bge.n 8015f84 <__ieee754_expf+0x44> - 8015f78: 4a48 ldr r2, [pc, #288] ; (801609c <__ieee754_expf+0x15c>) - 8015f7a: 4293 cmp r3, r2 - 8015f7c: d902 bls.n 8015f84 <__ieee754_expf+0x44> - 8015f7e: 2000 movs r0, #0 - 8015f80: f000 b8c2 b.w 8016108 <__math_uflowf> - 8015f84: 4a46 ldr r2, [pc, #280] ; (80160a0 <__ieee754_expf+0x160>) - 8015f86: 4293 cmp r3, r2 - 8015f88: eef7 5a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 - 8015f8c: d952 bls.n 8016034 <__ieee754_expf+0xf4> - 8015f8e: 4a45 ldr r2, [pc, #276] ; (80160a4 <__ieee754_expf+0x164>) - 8015f90: 4293 cmp r3, r2 - 8015f92: ea4f 0281 mov.w r2, r1, lsl #2 - 8015f96: d834 bhi.n 8016002 <__ieee754_expf+0xc2> - 8015f98: 4b43 ldr r3, [pc, #268] ; (80160a8 <__ieee754_expf+0x168>) - 8015f9a: 4413 add r3, r2 - 8015f9c: ed93 7a00 vldr s14, [r3] - 8015fa0: 4b42 ldr r3, [pc, #264] ; (80160ac <__ieee754_expf+0x16c>) - 8015fa2: 4413 add r3, r2 - 8015fa4: ee30 7a47 vsub.f32 s14, s0, s14 - 8015fa8: f1c1 0201 rsb r2, r1, #1 - 8015fac: edd3 7a00 vldr s15, [r3] - 8015fb0: 1a52 subs r2, r2, r1 - 8015fb2: ee37 0a67 vsub.f32 s0, s14, s15 - 8015fb6: ee20 6a00 vmul.f32 s12, s0, s0 - 8015fba: ed9f 5a3d vldr s10, [pc, #244] ; 80160b0 <__ieee754_expf+0x170> - 8015fbe: eddf 6a3d vldr s13, [pc, #244] ; 80160b4 <__ieee754_expf+0x174> - 8015fc2: eee6 6a05 vfma.f32 s13, s12, s10 - 8015fc6: ed9f 5a3c vldr s10, [pc, #240] ; 80160b8 <__ieee754_expf+0x178> - 8015fca: eea6 5a86 vfma.f32 s10, s13, s12 - 8015fce: eddf 6a3b vldr s13, [pc, #236] ; 80160bc <__ieee754_expf+0x17c> - 8015fd2: eee5 6a06 vfma.f32 s13, s10, s12 - 8015fd6: ed9f 5a3a vldr s10, [pc, #232] ; 80160c0 <__ieee754_expf+0x180> - 8015fda: eea6 5a86 vfma.f32 s10, s13, s12 - 8015fde: eef0 6a40 vmov.f32 s13, s0 - 8015fe2: eee5 6a46 vfms.f32 s13, s10, s12 - 8015fe6: eeb0 6a00 vmov.f32 s12, #0 ; 0x40000000 2.0 - 8015fea: ee20 5a26 vmul.f32 s10, s0, s13 - 8015fee: bb92 cbnz r2, 8016056 <__ieee754_expf+0x116> - 8015ff0: ee76 6ac6 vsub.f32 s13, s13, s12 - 8015ff4: eec5 7a26 vdiv.f32 s15, s10, s13 - 8015ff8: ee37 0ac0 vsub.f32 s0, s15, s0 - 8015ffc: ee35 0ac0 vsub.f32 s0, s11, s0 - 8016000: 4770 bx lr - 8016002: 4b30 ldr r3, [pc, #192] ; (80160c4 <__ieee754_expf+0x184>) - 8016004: ed9f 7a30 vldr s14, [pc, #192] ; 80160c8 <__ieee754_expf+0x188> - 8016008: eddf 6a30 vldr s13, [pc, #192] ; 80160cc <__ieee754_expf+0x18c> - 801600c: 4413 add r3, r2 - 801600e: edd3 7a00 vldr s15, [r3] - 8016012: eee0 7a07 vfma.f32 s15, s0, s14 - 8016016: eeb0 7a40 vmov.f32 s14, s0 - 801601a: eefd 7ae7 vcvt.s32.f32 s15, s15 - 801601e: ee17 2a90 vmov r2, s15 - 8016022: eef8 7ae7 vcvt.f32.s32 s15, s15 - 8016026: eea7 7ae6 vfms.f32 s14, s15, s13 - 801602a: eddf 6a29 vldr s13, [pc, #164] ; 80160d0 <__ieee754_expf+0x190> - 801602e: ee67 7aa6 vmul.f32 s15, s15, s13 - 8016032: e7be b.n 8015fb2 <__ieee754_expf+0x72> - 8016034: f1b3 5f50 cmp.w r3, #872415232 ; 0x34000000 - 8016038: d20b bcs.n 8016052 <__ieee754_expf+0x112> - 801603a: eddf 6a26 vldr s13, [pc, #152] ; 80160d4 <__ieee754_expf+0x194> - 801603e: ee70 6a26 vadd.f32 s13, s0, s13 - 8016042: eef4 6ae5 vcmpe.f32 s13, s11 - 8016046: eef1 fa10 vmrs APSR_nzcv, fpscr - 801604a: dd02 ble.n 8016052 <__ieee754_expf+0x112> - 801604c: ee30 0a25 vadd.f32 s0, s0, s11 - 8016050: 4770 bx lr - 8016052: 2200 movs r2, #0 - 8016054: e7af b.n 8015fb6 <__ieee754_expf+0x76> - 8016056: ee36 6a66 vsub.f32 s12, s12, s13 - 801605a: f112 0f7d cmn.w r2, #125 ; 0x7d - 801605e: eec5 6a06 vdiv.f32 s13, s10, s12 - 8016062: bfb8 it lt - 8016064: 3264 addlt r2, #100 ; 0x64 - 8016066: ee77 7ae6 vsub.f32 s15, s15, s13 - 801606a: ee77 7ac7 vsub.f32 s15, s15, s14 - 801606e: ee75 7ae7 vsub.f32 s15, s11, s15 - 8016072: ee17 3a90 vmov r3, s15 - 8016076: bfab itete ge - 8016078: eb03 53c2 addge.w r3, r3, r2, lsl #23 - 801607c: eb03 53c2 addlt.w r3, r3, r2, lsl #23 - 8016080: ee00 3a10 vmovge s0, r3 - 8016084: eddf 7a14 vldrlt s15, [pc, #80] ; 80160d8 <__ieee754_expf+0x198> - 8016088: bfbc itt lt - 801608a: ee00 3a10 vmovlt s0, r3 - 801608e: ee20 0a27 vmullt.f32 s0, s0, s15 - 8016092: 4770 bx lr - 8016094: 00000000 .word 0x00000000 - 8016098: 42b17217 .word 0x42b17217 - 801609c: 42cff1b5 .word 0x42cff1b5 - 80160a0: 3eb17218 .word 0x3eb17218 - 80160a4: 3f851591 .word 0x3f851591 - 80160a8: 08018d28 .word 0x08018d28 - 80160ac: 08018d30 .word 0x08018d30 - 80160b0: 3331bb4c .word 0x3331bb4c - 80160b4: b5ddea0e .word 0xb5ddea0e - 80160b8: 388ab355 .word 0x388ab355 - 80160bc: bb360b61 .word 0xbb360b61 - 80160c0: 3e2aaaab .word 0x3e2aaaab - 80160c4: 08018d20 .word 0x08018d20 - 80160c8: 3fb8aa3b .word 0x3fb8aa3b - 80160cc: 3f317180 .word 0x3f317180 - 80160d0: 3717f7d1 .word 0x3717f7d1 - 80160d4: 7149f2ca .word 0x7149f2ca - 80160d8: 0d800000 .word 0x0d800000 - -080160dc : - 80160dc: b513 push {r0, r1, r4, lr} - 80160de: 4604 mov r4, r0 - 80160e0: ed8d 0a01 vstr s0, [sp, #4] - 80160e4: f7fc fda0 bl 8012c28 <__errno> - 80160e8: ed9d 0a01 vldr s0, [sp, #4] - 80160ec: 6004 str r4, [r0, #0] - 80160ee: b002 add sp, #8 - 80160f0: bd10 pop {r4, pc} - -080160f2 : - 80160f2: b130 cbz r0, 8016102 - 80160f4: eef1 7a40 vneg.f32 s15, s0 - 80160f8: ee27 0a80 vmul.f32 s0, s15, s0 - 80160fc: 2022 movs r0, #34 ; 0x22 - 80160fe: f7ff bfed b.w 80160dc - 8016102: eef0 7a40 vmov.f32 s15, s0 - 8016106: e7f7 b.n 80160f8 - -08016108 <__math_uflowf>: - 8016108: ed9f 0a01 vldr s0, [pc, #4] ; 8016110 <__math_uflowf+0x8> - 801610c: f7ff bff1 b.w 80160f2 - 8016110: 10000000 .word 0x10000000 - -08016114 <__math_oflowf>: - 8016114: ed9f 0a01 vldr s0, [pc, #4] ; 801611c <__math_oflowf+0x8> - 8016118: f7ff bfeb b.w 80160f2 - 801611c: 70000000 .word 0x70000000 - -08016120 <__kernel_rem_pio2>: - 8016120: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8016124: ed2d 8b02 vpush {d8} - 8016128: f5ad 7d19 sub.w sp, sp, #612 ; 0x264 - 801612c: f112 0f14 cmn.w r2, #20 - 8016130: 9306 str r3, [sp, #24] - 8016132: 9104 str r1, [sp, #16] - 8016134: 4bc2 ldr r3, [pc, #776] ; (8016440 <__kernel_rem_pio2+0x320>) - 8016136: 99a4 ldr r1, [sp, #656] ; 0x290 - 8016138: 9009 str r0, [sp, #36] ; 0x24 - 801613a: f853 3021 ldr.w r3, [r3, r1, lsl #2] - 801613e: 9300 str r3, [sp, #0] - 8016140: 9b06 ldr r3, [sp, #24] - 8016142: f103 33ff add.w r3, r3, #4294967295 - 8016146: bfa8 it ge - 8016148: 1ed4 subge r4, r2, #3 - 801614a: 9305 str r3, [sp, #20] - 801614c: bfb2 itee lt - 801614e: 2400 movlt r4, #0 - 8016150: 2318 movge r3, #24 - 8016152: fb94 f4f3 sdivge r4, r4, r3 - 8016156: f06f 0317 mvn.w r3, #23 - 801615a: fb04 3303 mla r3, r4, r3, r3 - 801615e: eb03 0a02 add.w sl, r3, r2 - 8016162: 9b00 ldr r3, [sp, #0] - 8016164: 9a05 ldr r2, [sp, #20] - 8016166: ed9f 8bb2 vldr d8, [pc, #712] ; 8016430 <__kernel_rem_pio2+0x310> - 801616a: eb03 0802 add.w r8, r3, r2 - 801616e: 9ba5 ldr r3, [sp, #660] ; 0x294 - 8016170: 1aa7 subs r7, r4, r2 - 8016172: ae20 add r6, sp, #128 ; 0x80 - 8016174: eb03 0987 add.w r9, r3, r7, lsl #2 - 8016178: 2500 movs r5, #0 - 801617a: 4545 cmp r5, r8 - 801617c: dd13 ble.n 80161a6 <__kernel_rem_pio2+0x86> - 801617e: 9b06 ldr r3, [sp, #24] - 8016180: aa20 add r2, sp, #128 ; 0x80 - 8016182: eb02 05c3 add.w r5, r2, r3, lsl #3 - 8016186: f50d 7be0 add.w fp, sp, #448 ; 0x1c0 - 801618a: f04f 0800 mov.w r8, #0 - 801618e: 9b00 ldr r3, [sp, #0] - 8016190: 4598 cmp r8, r3 - 8016192: dc31 bgt.n 80161f8 <__kernel_rem_pio2+0xd8> - 8016194: ed9f 7ba6 vldr d7, [pc, #664] ; 8016430 <__kernel_rem_pio2+0x310> - 8016198: f8dd 9024 ldr.w r9, [sp, #36] ; 0x24 - 801619c: ed8d 7b02 vstr d7, [sp, #8] - 80161a0: 462f mov r7, r5 - 80161a2: 2600 movs r6, #0 - 80161a4: e01b b.n 80161de <__kernel_rem_pio2+0xbe> - 80161a6: 42ef cmn r7, r5 - 80161a8: d407 bmi.n 80161ba <__kernel_rem_pio2+0x9a> - 80161aa: f859 0025 ldr.w r0, [r9, r5, lsl #2] - 80161ae: f7ea f9b9 bl 8000524 <__aeabi_i2d> - 80161b2: e8e6 0102 strd r0, r1, [r6], #8 - 80161b6: 3501 adds r5, #1 - 80161b8: e7df b.n 801617a <__kernel_rem_pio2+0x5a> - 80161ba: ec51 0b18 vmov r0, r1, d8 - 80161be: e7f8 b.n 80161b2 <__kernel_rem_pio2+0x92> - 80161c0: e9d7 2300 ldrd r2, r3, [r7] - 80161c4: e8f9 0102 ldrd r0, r1, [r9], #8 - 80161c8: f7ea fa16 bl 80005f8 <__aeabi_dmul> - 80161cc: 4602 mov r2, r0 - 80161ce: 460b mov r3, r1 - 80161d0: e9dd 0102 ldrd r0, r1, [sp, #8] - 80161d4: f7ea f85a bl 800028c <__adddf3> - 80161d8: e9cd 0102 strd r0, r1, [sp, #8] - 80161dc: 3601 adds r6, #1 - 80161de: 9b05 ldr r3, [sp, #20] - 80161e0: 429e cmp r6, r3 - 80161e2: f1a7 0708 sub.w r7, r7, #8 - 80161e6: ddeb ble.n 80161c0 <__kernel_rem_pio2+0xa0> - 80161e8: ed9d 7b02 vldr d7, [sp, #8] - 80161ec: f108 0801 add.w r8, r8, #1 - 80161f0: ecab 7b02 vstmia fp!, {d7} - 80161f4: 3508 adds r5, #8 - 80161f6: e7ca b.n 801618e <__kernel_rem_pio2+0x6e> - 80161f8: 9b00 ldr r3, [sp, #0] - 80161fa: aa0c add r2, sp, #48 ; 0x30 - 80161fc: eb02 0383 add.w r3, r2, r3, lsl #2 - 8016200: 930b str r3, [sp, #44] ; 0x2c - 8016202: 9ba5 ldr r3, [sp, #660] ; 0x294 - 8016204: eb03 0384 add.w r3, r3, r4, lsl #2 - 8016208: 9c00 ldr r4, [sp, #0] - 801620a: 930a str r3, [sp, #40] ; 0x28 - 801620c: 00e3 lsls r3, r4, #3 - 801620e: 9308 str r3, [sp, #32] - 8016210: ab98 add r3, sp, #608 ; 0x260 - 8016212: eb03 03c4 add.w r3, r3, r4, lsl #3 - 8016216: e953 6728 ldrd r6, r7, [r3, #-160] ; 0xa0 - 801621a: f10d 0830 add.w r8, sp, #48 ; 0x30 - 801621e: ab70 add r3, sp, #448 ; 0x1c0 - 8016220: eb03 05c4 add.w r5, r3, r4, lsl #3 - 8016224: 46c3 mov fp, r8 - 8016226: 46a1 mov r9, r4 - 8016228: f1b9 0f00 cmp.w r9, #0 - 801622c: f1a5 0508 sub.w r5, r5, #8 - 8016230: dc77 bgt.n 8016322 <__kernel_rem_pio2+0x202> - 8016232: ec47 6b10 vmov d0, r6, r7 - 8016236: 4650 mov r0, sl - 8016238: f000 fac2 bl 80167c0 - 801623c: ec57 6b10 vmov r6, r7, d0 - 8016240: 2200 movs r2, #0 - 8016242: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 - 8016246: ee10 0a10 vmov r0, s0 - 801624a: 4639 mov r1, r7 - 801624c: f7ea f9d4 bl 80005f8 <__aeabi_dmul> - 8016250: ec41 0b10 vmov d0, r0, r1 - 8016254: f7ff fa5c bl 8015710 - 8016258: 4b7a ldr r3, [pc, #488] ; (8016444 <__kernel_rem_pio2+0x324>) - 801625a: ec51 0b10 vmov r0, r1, d0 - 801625e: 2200 movs r2, #0 - 8016260: f7ea f9ca bl 80005f8 <__aeabi_dmul> - 8016264: 4602 mov r2, r0 - 8016266: 460b mov r3, r1 - 8016268: 4630 mov r0, r6 - 801626a: 4639 mov r1, r7 - 801626c: f7ea f80c bl 8000288 <__aeabi_dsub> - 8016270: 460f mov r7, r1 - 8016272: 4606 mov r6, r0 - 8016274: f7ea fc70 bl 8000b58 <__aeabi_d2iz> - 8016278: 9002 str r0, [sp, #8] - 801627a: f7ea f953 bl 8000524 <__aeabi_i2d> - 801627e: 4602 mov r2, r0 - 8016280: 460b mov r3, r1 - 8016282: 4630 mov r0, r6 - 8016284: 4639 mov r1, r7 - 8016286: f7e9 ffff bl 8000288 <__aeabi_dsub> - 801628a: f1ba 0f00 cmp.w sl, #0 - 801628e: 4606 mov r6, r0 - 8016290: 460f mov r7, r1 - 8016292: dd6d ble.n 8016370 <__kernel_rem_pio2+0x250> - 8016294: 1e61 subs r1, r4, #1 - 8016296: ab0c add r3, sp, #48 ; 0x30 - 8016298: 9d02 ldr r5, [sp, #8] - 801629a: f853 3021 ldr.w r3, [r3, r1, lsl #2] - 801629e: f1ca 0018 rsb r0, sl, #24 - 80162a2: fa43 f200 asr.w r2, r3, r0 - 80162a6: 4415 add r5, r2 - 80162a8: 4082 lsls r2, r0 - 80162aa: 1a9b subs r3, r3, r2 - 80162ac: aa0c add r2, sp, #48 ; 0x30 - 80162ae: 9502 str r5, [sp, #8] - 80162b0: f842 3021 str.w r3, [r2, r1, lsl #2] - 80162b4: f1ca 0217 rsb r2, sl, #23 - 80162b8: fa43 fb02 asr.w fp, r3, r2 - 80162bc: f1bb 0f00 cmp.w fp, #0 - 80162c0: dd65 ble.n 801638e <__kernel_rem_pio2+0x26e> - 80162c2: 9b02 ldr r3, [sp, #8] - 80162c4: 2200 movs r2, #0 - 80162c6: 3301 adds r3, #1 - 80162c8: 9302 str r3, [sp, #8] - 80162ca: 4615 mov r5, r2 - 80162cc: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 - 80162d0: 4294 cmp r4, r2 - 80162d2: f300 809f bgt.w 8016414 <__kernel_rem_pio2+0x2f4> - 80162d6: f1ba 0f00 cmp.w sl, #0 - 80162da: dd07 ble.n 80162ec <__kernel_rem_pio2+0x1cc> - 80162dc: f1ba 0f01 cmp.w sl, #1 - 80162e0: f000 80c1 beq.w 8016466 <__kernel_rem_pio2+0x346> - 80162e4: f1ba 0f02 cmp.w sl, #2 - 80162e8: f000 80c7 beq.w 801647a <__kernel_rem_pio2+0x35a> - 80162ec: f1bb 0f02 cmp.w fp, #2 - 80162f0: d14d bne.n 801638e <__kernel_rem_pio2+0x26e> - 80162f2: 4632 mov r2, r6 - 80162f4: 463b mov r3, r7 - 80162f6: 4954 ldr r1, [pc, #336] ; (8016448 <__kernel_rem_pio2+0x328>) - 80162f8: 2000 movs r0, #0 - 80162fa: f7e9 ffc5 bl 8000288 <__aeabi_dsub> - 80162fe: 4606 mov r6, r0 - 8016300: 460f mov r7, r1 - 8016302: 2d00 cmp r5, #0 - 8016304: d043 beq.n 801638e <__kernel_rem_pio2+0x26e> - 8016306: 4650 mov r0, sl - 8016308: ed9f 0b4b vldr d0, [pc, #300] ; 8016438 <__kernel_rem_pio2+0x318> - 801630c: f000 fa58 bl 80167c0 - 8016310: 4630 mov r0, r6 - 8016312: 4639 mov r1, r7 - 8016314: ec53 2b10 vmov r2, r3, d0 - 8016318: f7e9 ffb6 bl 8000288 <__aeabi_dsub> - 801631c: 4606 mov r6, r0 - 801631e: 460f mov r7, r1 - 8016320: e035 b.n 801638e <__kernel_rem_pio2+0x26e> - 8016322: 4b4a ldr r3, [pc, #296] ; (801644c <__kernel_rem_pio2+0x32c>) - 8016324: 2200 movs r2, #0 - 8016326: 4630 mov r0, r6 - 8016328: 4639 mov r1, r7 - 801632a: f7ea f965 bl 80005f8 <__aeabi_dmul> - 801632e: f7ea fc13 bl 8000b58 <__aeabi_d2iz> - 8016332: f7ea f8f7 bl 8000524 <__aeabi_i2d> - 8016336: 4602 mov r2, r0 - 8016338: 460b mov r3, r1 - 801633a: ec43 2b18 vmov d8, r2, r3 - 801633e: 4b44 ldr r3, [pc, #272] ; (8016450 <__kernel_rem_pio2+0x330>) - 8016340: 2200 movs r2, #0 - 8016342: f7ea f959 bl 80005f8 <__aeabi_dmul> - 8016346: 4602 mov r2, r0 - 8016348: 460b mov r3, r1 - 801634a: 4630 mov r0, r6 - 801634c: 4639 mov r1, r7 - 801634e: f7e9 ff9b bl 8000288 <__aeabi_dsub> - 8016352: f7ea fc01 bl 8000b58 <__aeabi_d2iz> - 8016356: e9d5 2300 ldrd r2, r3, [r5] - 801635a: f84b 0b04 str.w r0, [fp], #4 - 801635e: ec51 0b18 vmov r0, r1, d8 - 8016362: f7e9 ff93 bl 800028c <__adddf3> - 8016366: f109 39ff add.w r9, r9, #4294967295 - 801636a: 4606 mov r6, r0 - 801636c: 460f mov r7, r1 - 801636e: e75b b.n 8016228 <__kernel_rem_pio2+0x108> - 8016370: d106 bne.n 8016380 <__kernel_rem_pio2+0x260> - 8016372: 1e63 subs r3, r4, #1 - 8016374: aa0c add r2, sp, #48 ; 0x30 - 8016376: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 801637a: ea4f 5be3 mov.w fp, r3, asr #23 - 801637e: e79d b.n 80162bc <__kernel_rem_pio2+0x19c> - 8016380: 4b34 ldr r3, [pc, #208] ; (8016454 <__kernel_rem_pio2+0x334>) - 8016382: 2200 movs r2, #0 - 8016384: f7ea fbbe bl 8000b04 <__aeabi_dcmpge> - 8016388: 2800 cmp r0, #0 - 801638a: d140 bne.n 801640e <__kernel_rem_pio2+0x2ee> - 801638c: 4683 mov fp, r0 - 801638e: 2200 movs r2, #0 - 8016390: 2300 movs r3, #0 - 8016392: 4630 mov r0, r6 - 8016394: 4639 mov r1, r7 - 8016396: f7ea fb97 bl 8000ac8 <__aeabi_dcmpeq> - 801639a: 2800 cmp r0, #0 - 801639c: f000 80c1 beq.w 8016522 <__kernel_rem_pio2+0x402> - 80163a0: 1e65 subs r5, r4, #1 - 80163a2: 462b mov r3, r5 - 80163a4: 2200 movs r2, #0 - 80163a6: 9900 ldr r1, [sp, #0] - 80163a8: 428b cmp r3, r1 - 80163aa: da6d bge.n 8016488 <__kernel_rem_pio2+0x368> - 80163ac: 2a00 cmp r2, #0 - 80163ae: f000 808a beq.w 80164c6 <__kernel_rem_pio2+0x3a6> - 80163b2: ab0c add r3, sp, #48 ; 0x30 - 80163b4: f1aa 0a18 sub.w sl, sl, #24 - 80163b8: f853 3025 ldr.w r3, [r3, r5, lsl #2] - 80163bc: 2b00 cmp r3, #0 - 80163be: f000 80ae beq.w 801651e <__kernel_rem_pio2+0x3fe> - 80163c2: 4650 mov r0, sl - 80163c4: ed9f 0b1c vldr d0, [pc, #112] ; 8016438 <__kernel_rem_pio2+0x318> - 80163c8: f000 f9fa bl 80167c0 - 80163cc: 1c6b adds r3, r5, #1 - 80163ce: 00da lsls r2, r3, #3 - 80163d0: 9205 str r2, [sp, #20] - 80163d2: ec57 6b10 vmov r6, r7, d0 - 80163d6: aa70 add r2, sp, #448 ; 0x1c0 - 80163d8: f8df 9070 ldr.w r9, [pc, #112] ; 801644c <__kernel_rem_pio2+0x32c> - 80163dc: eb02 0ac3 add.w sl, r2, r3, lsl #3 - 80163e0: 462c mov r4, r5 - 80163e2: f04f 0800 mov.w r8, #0 - 80163e6: 2c00 cmp r4, #0 - 80163e8: f280 80d4 bge.w 8016594 <__kernel_rem_pio2+0x474> - 80163ec: 462c mov r4, r5 - 80163ee: 2c00 cmp r4, #0 - 80163f0: f2c0 8102 blt.w 80165f8 <__kernel_rem_pio2+0x4d8> - 80163f4: 4b18 ldr r3, [pc, #96] ; (8016458 <__kernel_rem_pio2+0x338>) - 80163f6: 461e mov r6, r3 - 80163f8: ab70 add r3, sp, #448 ; 0x1c0 - 80163fa: eb03 08c4 add.w r8, r3, r4, lsl #3 - 80163fe: 1b2b subs r3, r5, r4 - 8016400: f04f 0900 mov.w r9, #0 - 8016404: f04f 0a00 mov.w sl, #0 - 8016408: 2700 movs r7, #0 - 801640a: 9306 str r3, [sp, #24] - 801640c: e0e6 b.n 80165dc <__kernel_rem_pio2+0x4bc> - 801640e: f04f 0b02 mov.w fp, #2 - 8016412: e756 b.n 80162c2 <__kernel_rem_pio2+0x1a2> - 8016414: f8d8 3000 ldr.w r3, [r8] - 8016418: bb05 cbnz r5, 801645c <__kernel_rem_pio2+0x33c> - 801641a: b123 cbz r3, 8016426 <__kernel_rem_pio2+0x306> - 801641c: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 - 8016420: f8c8 3000 str.w r3, [r8] - 8016424: 2301 movs r3, #1 - 8016426: 3201 adds r2, #1 - 8016428: f108 0804 add.w r8, r8, #4 - 801642c: 461d mov r5, r3 - 801642e: e74f b.n 80162d0 <__kernel_rem_pio2+0x1b0> +080183f0 <__ieee754_expf>: + 80183f0: ee10 2a10 vmov r2, s0 + 80183f4: f022 4300 bic.w r3, r2, #2147483648 ; 0x80000000 + 80183f8: f1b3 4fff cmp.w r3, #2139095040 ; 0x7f800000 + 80183fc: d902 bls.n 8018404 <__ieee754_expf+0x14> + 80183fe: ee30 0a00 vadd.f32 s0, s0, s0 + 8018402: 4770 bx lr + 8018404: ea4f 71d2 mov.w r1, r2, lsr #31 + 8018408: d106 bne.n 8018418 <__ieee754_expf+0x28> + 801840a: eddf 7a4e vldr s15, [pc, #312] ; 8018544 <__ieee754_expf+0x154> + 801840e: 2900 cmp r1, #0 + 8018410: bf18 it ne + 8018412: eeb0 0a67 vmovne.f32 s0, s15 + 8018416: 4770 bx lr + 8018418: 484b ldr r0, [pc, #300] ; (8018548 <__ieee754_expf+0x158>) + 801841a: 4282 cmp r2, r0 + 801841c: dd02 ble.n 8018424 <__ieee754_expf+0x34> + 801841e: 2000 movs r0, #0 + 8018420: f000 b8d0 b.w 80185c4 <__math_oflowf> + 8018424: 2a00 cmp r2, #0 + 8018426: da05 bge.n 8018434 <__ieee754_expf+0x44> + 8018428: 4a48 ldr r2, [pc, #288] ; (801854c <__ieee754_expf+0x15c>) + 801842a: 4293 cmp r3, r2 + 801842c: d902 bls.n 8018434 <__ieee754_expf+0x44> + 801842e: 2000 movs r0, #0 + 8018430: f000 b8c2 b.w 80185b8 <__math_uflowf> + 8018434: 4a46 ldr r2, [pc, #280] ; (8018550 <__ieee754_expf+0x160>) + 8018436: 4293 cmp r3, r2 + 8018438: eef7 5a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 + 801843c: d952 bls.n 80184e4 <__ieee754_expf+0xf4> + 801843e: 4a45 ldr r2, [pc, #276] ; (8018554 <__ieee754_expf+0x164>) + 8018440: 4293 cmp r3, r2 + 8018442: ea4f 0281 mov.w r2, r1, lsl #2 + 8018446: d834 bhi.n 80184b2 <__ieee754_expf+0xc2> + 8018448: 4b43 ldr r3, [pc, #268] ; (8018558 <__ieee754_expf+0x168>) + 801844a: 4413 add r3, r2 + 801844c: ed93 7a00 vldr s14, [r3] + 8018450: 4b42 ldr r3, [pc, #264] ; (801855c <__ieee754_expf+0x16c>) + 8018452: 4413 add r3, r2 + 8018454: ee30 7a47 vsub.f32 s14, s0, s14 + 8018458: f1c1 0201 rsb r2, r1, #1 + 801845c: edd3 7a00 vldr s15, [r3] + 8018460: 1a52 subs r2, r2, r1 + 8018462: ee37 0a67 vsub.f32 s0, s14, s15 + 8018466: ee20 6a00 vmul.f32 s12, s0, s0 + 801846a: ed9f 5a3d vldr s10, [pc, #244] ; 8018560 <__ieee754_expf+0x170> + 801846e: eddf 6a3d vldr s13, [pc, #244] ; 8018564 <__ieee754_expf+0x174> + 8018472: eee6 6a05 vfma.f32 s13, s12, s10 + 8018476: ed9f 5a3c vldr s10, [pc, #240] ; 8018568 <__ieee754_expf+0x178> + 801847a: eea6 5a86 vfma.f32 s10, s13, s12 + 801847e: eddf 6a3b vldr s13, [pc, #236] ; 801856c <__ieee754_expf+0x17c> + 8018482: eee5 6a06 vfma.f32 s13, s10, s12 + 8018486: ed9f 5a3a vldr s10, [pc, #232] ; 8018570 <__ieee754_expf+0x180> + 801848a: eea6 5a86 vfma.f32 s10, s13, s12 + 801848e: eef0 6a40 vmov.f32 s13, s0 + 8018492: eee5 6a46 vfms.f32 s13, s10, s12 + 8018496: eeb0 6a00 vmov.f32 s12, #0 ; 0x40000000 2.0 + 801849a: ee20 5a26 vmul.f32 s10, s0, s13 + 801849e: bb92 cbnz r2, 8018506 <__ieee754_expf+0x116> + 80184a0: ee76 6ac6 vsub.f32 s13, s13, s12 + 80184a4: eec5 7a26 vdiv.f32 s15, s10, s13 + 80184a8: ee37 0ac0 vsub.f32 s0, s15, s0 + 80184ac: ee35 0ac0 vsub.f32 s0, s11, s0 + 80184b0: 4770 bx lr + 80184b2: 4b30 ldr r3, [pc, #192] ; (8018574 <__ieee754_expf+0x184>) + 80184b4: ed9f 7a30 vldr s14, [pc, #192] ; 8018578 <__ieee754_expf+0x188> + 80184b8: eddf 6a30 vldr s13, [pc, #192] ; 801857c <__ieee754_expf+0x18c> + 80184bc: 4413 add r3, r2 + 80184be: edd3 7a00 vldr s15, [r3] + 80184c2: eee0 7a07 vfma.f32 s15, s0, s14 + 80184c6: eeb0 7a40 vmov.f32 s14, s0 + 80184ca: eefd 7ae7 vcvt.s32.f32 s15, s15 + 80184ce: ee17 2a90 vmov r2, s15 + 80184d2: eef8 7ae7 vcvt.f32.s32 s15, s15 + 80184d6: eea7 7ae6 vfms.f32 s14, s15, s13 + 80184da: eddf 6a29 vldr s13, [pc, #164] ; 8018580 <__ieee754_expf+0x190> + 80184de: ee67 7aa6 vmul.f32 s15, s15, s13 + 80184e2: e7be b.n 8018462 <__ieee754_expf+0x72> + 80184e4: f1b3 5f50 cmp.w r3, #872415232 ; 0x34000000 + 80184e8: d20b bcs.n 8018502 <__ieee754_expf+0x112> + 80184ea: eddf 6a26 vldr s13, [pc, #152] ; 8018584 <__ieee754_expf+0x194> + 80184ee: ee70 6a26 vadd.f32 s13, s0, s13 + 80184f2: eef4 6ae5 vcmpe.f32 s13, s11 + 80184f6: eef1 fa10 vmrs APSR_nzcv, fpscr + 80184fa: dd02 ble.n 8018502 <__ieee754_expf+0x112> + 80184fc: ee30 0a25 vadd.f32 s0, s0, s11 + 8018500: 4770 bx lr + 8018502: 2200 movs r2, #0 + 8018504: e7af b.n 8018466 <__ieee754_expf+0x76> + 8018506: ee36 6a66 vsub.f32 s12, s12, s13 + 801850a: f112 0f7d cmn.w r2, #125 ; 0x7d + 801850e: eec5 6a06 vdiv.f32 s13, s10, s12 + 8018512: bfb8 it lt + 8018514: 3264 addlt r2, #100 ; 0x64 + 8018516: ee77 7ae6 vsub.f32 s15, s15, s13 + 801851a: ee77 7ac7 vsub.f32 s15, s15, s14 + 801851e: ee75 7ae7 vsub.f32 s15, s11, s15 + 8018522: ee17 3a90 vmov r3, s15 + 8018526: bfab itete ge + 8018528: eb03 53c2 addge.w r3, r3, r2, lsl #23 + 801852c: eb03 53c2 addlt.w r3, r3, r2, lsl #23 + 8018530: ee00 3a10 vmovge s0, r3 + 8018534: eddf 7a14 vldrlt s15, [pc, #80] ; 8018588 <__ieee754_expf+0x198> + 8018538: bfbc itt lt + 801853a: ee00 3a10 vmovlt s0, r3 + 801853e: ee20 0a27 vmullt.f32 s0, s0, s15 + 8018542: 4770 bx lr + 8018544: 00000000 .word 0x00000000 + 8018548: 42b17217 .word 0x42b17217 + 801854c: 42cff1b5 .word 0x42cff1b5 + 8018550: 3eb17218 .word 0x3eb17218 + 8018554: 3f851591 .word 0x3f851591 + 8018558: 0801b200 .word 0x0801b200 + 801855c: 0801b208 .word 0x0801b208 + 8018560: 3331bb4c .word 0x3331bb4c + 8018564: b5ddea0e .word 0xb5ddea0e + 8018568: 388ab355 .word 0x388ab355 + 801856c: bb360b61 .word 0xbb360b61 + 8018570: 3e2aaaab .word 0x3e2aaaab + 8018574: 0801b1f8 .word 0x0801b1f8 + 8018578: 3fb8aa3b .word 0x3fb8aa3b + 801857c: 3f317180 .word 0x3f317180 + 8018580: 3717f7d1 .word 0x3717f7d1 + 8018584: 7149f2ca .word 0x7149f2ca + 8018588: 0d800000 .word 0x0d800000 + +0801858c : + 801858c: b513 push {r0, r1, r4, lr} + 801858e: 4604 mov r4, r0 + 8018590: ed8d 0a01 vstr s0, [sp, #4] + 8018594: f7fc fda0 bl 80150d8 <__errno> + 8018598: ed9d 0a01 vldr s0, [sp, #4] + 801859c: 6004 str r4, [r0, #0] + 801859e: b002 add sp, #8 + 80185a0: bd10 pop {r4, pc} + +080185a2 : + 80185a2: b130 cbz r0, 80185b2 + 80185a4: eef1 7a40 vneg.f32 s15, s0 + 80185a8: ee27 0a80 vmul.f32 s0, s15, s0 + 80185ac: 2022 movs r0, #34 ; 0x22 + 80185ae: f7ff bfed b.w 801858c + 80185b2: eef0 7a40 vmov.f32 s15, s0 + 80185b6: e7f7 b.n 80185a8 + +080185b8 <__math_uflowf>: + 80185b8: ed9f 0a01 vldr s0, [pc, #4] ; 80185c0 <__math_uflowf+0x8> + 80185bc: f7ff bff1 b.w 80185a2 + 80185c0: 10000000 .word 0x10000000 + +080185c4 <__math_oflowf>: + 80185c4: ed9f 0a01 vldr s0, [pc, #4] ; 80185cc <__math_oflowf+0x8> + 80185c8: f7ff bfeb b.w 80185a2 + 80185cc: 70000000 .word 0x70000000 + +080185d0 <__kernel_rem_pio2>: + 80185d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80185d4: ed2d 8b02 vpush {d8} + 80185d8: f5ad 7d19 sub.w sp, sp, #612 ; 0x264 + 80185dc: f112 0f14 cmn.w r2, #20 + 80185e0: 9306 str r3, [sp, #24] + 80185e2: 9104 str r1, [sp, #16] + 80185e4: 4bc2 ldr r3, [pc, #776] ; (80188f0 <__kernel_rem_pio2+0x320>) + 80185e6: 99a4 ldr r1, [sp, #656] ; 0x290 + 80185e8: 9009 str r0, [sp, #36] ; 0x24 + 80185ea: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 80185ee: 9300 str r3, [sp, #0] + 80185f0: 9b06 ldr r3, [sp, #24] + 80185f2: f103 33ff add.w r3, r3, #4294967295 + 80185f6: bfa8 it ge + 80185f8: 1ed4 subge r4, r2, #3 + 80185fa: 9305 str r3, [sp, #20] + 80185fc: bfb2 itee lt + 80185fe: 2400 movlt r4, #0 + 8018600: 2318 movge r3, #24 + 8018602: fb94 f4f3 sdivge r4, r4, r3 + 8018606: f06f 0317 mvn.w r3, #23 + 801860a: fb04 3303 mla r3, r4, r3, r3 + 801860e: eb03 0a02 add.w sl, r3, r2 + 8018612: 9b00 ldr r3, [sp, #0] + 8018614: 9a05 ldr r2, [sp, #20] + 8018616: ed9f 8bb2 vldr d8, [pc, #712] ; 80188e0 <__kernel_rem_pio2+0x310> + 801861a: eb03 0802 add.w r8, r3, r2 + 801861e: 9ba5 ldr r3, [sp, #660] ; 0x294 + 8018620: 1aa7 subs r7, r4, r2 + 8018622: ae20 add r6, sp, #128 ; 0x80 + 8018624: eb03 0987 add.w r9, r3, r7, lsl #2 + 8018628: 2500 movs r5, #0 + 801862a: 4545 cmp r5, r8 + 801862c: dd13 ble.n 8018656 <__kernel_rem_pio2+0x86> + 801862e: 9b06 ldr r3, [sp, #24] + 8018630: aa20 add r2, sp, #128 ; 0x80 + 8018632: eb02 05c3 add.w r5, r2, r3, lsl #3 + 8018636: f50d 7be0 add.w fp, sp, #448 ; 0x1c0 + 801863a: f04f 0800 mov.w r8, #0 + 801863e: 9b00 ldr r3, [sp, #0] + 8018640: 4598 cmp r8, r3 + 8018642: dc31 bgt.n 80186a8 <__kernel_rem_pio2+0xd8> + 8018644: ed9f 7ba6 vldr d7, [pc, #664] ; 80188e0 <__kernel_rem_pio2+0x310> + 8018648: f8dd 9024 ldr.w r9, [sp, #36] ; 0x24 + 801864c: ed8d 7b02 vstr d7, [sp, #8] + 8018650: 462f mov r7, r5 + 8018652: 2600 movs r6, #0 + 8018654: e01b b.n 801868e <__kernel_rem_pio2+0xbe> + 8018656: 42ef cmn r7, r5 + 8018658: d407 bmi.n 801866a <__kernel_rem_pio2+0x9a> + 801865a: f859 0025 ldr.w r0, [r9, r5, lsl #2] + 801865e: f7e7 ff61 bl 8000524 <__aeabi_i2d> + 8018662: e8e6 0102 strd r0, r1, [r6], #8 + 8018666: 3501 adds r5, #1 + 8018668: e7df b.n 801862a <__kernel_rem_pio2+0x5a> + 801866a: ec51 0b18 vmov r0, r1, d8 + 801866e: e7f8 b.n 8018662 <__kernel_rem_pio2+0x92> + 8018670: e9d7 2300 ldrd r2, r3, [r7] + 8018674: e8f9 0102 ldrd r0, r1, [r9], #8 + 8018678: f7e7 ffbe bl 80005f8 <__aeabi_dmul> + 801867c: 4602 mov r2, r0 + 801867e: 460b mov r3, r1 + 8018680: e9dd 0102 ldrd r0, r1, [sp, #8] + 8018684: f7e7 fe02 bl 800028c <__adddf3> + 8018688: e9cd 0102 strd r0, r1, [sp, #8] + 801868c: 3601 adds r6, #1 + 801868e: 9b05 ldr r3, [sp, #20] + 8018690: 429e cmp r6, r3 + 8018692: f1a7 0708 sub.w r7, r7, #8 + 8018696: ddeb ble.n 8018670 <__kernel_rem_pio2+0xa0> + 8018698: ed9d 7b02 vldr d7, [sp, #8] + 801869c: f108 0801 add.w r8, r8, #1 + 80186a0: ecab 7b02 vstmia fp!, {d7} + 80186a4: 3508 adds r5, #8 + 80186a6: e7ca b.n 801863e <__kernel_rem_pio2+0x6e> + 80186a8: 9b00 ldr r3, [sp, #0] + 80186aa: aa0c add r2, sp, #48 ; 0x30 + 80186ac: eb02 0383 add.w r3, r2, r3, lsl #2 + 80186b0: 930b str r3, [sp, #44] ; 0x2c + 80186b2: 9ba5 ldr r3, [sp, #660] ; 0x294 + 80186b4: eb03 0384 add.w r3, r3, r4, lsl #2 + 80186b8: 9c00 ldr r4, [sp, #0] + 80186ba: 930a str r3, [sp, #40] ; 0x28 + 80186bc: 00e3 lsls r3, r4, #3 + 80186be: 9308 str r3, [sp, #32] + 80186c0: ab98 add r3, sp, #608 ; 0x260 + 80186c2: eb03 03c4 add.w r3, r3, r4, lsl #3 + 80186c6: e953 6728 ldrd r6, r7, [r3, #-160] ; 0xa0 + 80186ca: f10d 0830 add.w r8, sp, #48 ; 0x30 + 80186ce: ab70 add r3, sp, #448 ; 0x1c0 + 80186d0: eb03 05c4 add.w r5, r3, r4, lsl #3 + 80186d4: 46c3 mov fp, r8 + 80186d6: 46a1 mov r9, r4 + 80186d8: f1b9 0f00 cmp.w r9, #0 + 80186dc: f1a5 0508 sub.w r5, r5, #8 + 80186e0: dc77 bgt.n 80187d2 <__kernel_rem_pio2+0x202> + 80186e2: ec47 6b10 vmov d0, r6, r7 + 80186e6: 4650 mov r0, sl + 80186e8: f000 fac2 bl 8018c70 + 80186ec: ec57 6b10 vmov r6, r7, d0 + 80186f0: 2200 movs r2, #0 + 80186f2: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 + 80186f6: ee10 0a10 vmov r0, s0 + 80186fa: 4639 mov r1, r7 + 80186fc: f7e7 ff7c bl 80005f8 <__aeabi_dmul> + 8018700: ec41 0b10 vmov d0, r0, r1 + 8018704: f7ff fa5c bl 8017bc0 + 8018708: 4b7a ldr r3, [pc, #488] ; (80188f4 <__kernel_rem_pio2+0x324>) + 801870a: ec51 0b10 vmov r0, r1, d0 + 801870e: 2200 movs r2, #0 + 8018710: f7e7 ff72 bl 80005f8 <__aeabi_dmul> + 8018714: 4602 mov r2, r0 + 8018716: 460b mov r3, r1 + 8018718: 4630 mov r0, r6 + 801871a: 4639 mov r1, r7 + 801871c: f7e7 fdb4 bl 8000288 <__aeabi_dsub> + 8018720: 460f mov r7, r1 + 8018722: 4606 mov r6, r0 + 8018724: f7e8 fa18 bl 8000b58 <__aeabi_d2iz> + 8018728: 9002 str r0, [sp, #8] + 801872a: f7e7 fefb bl 8000524 <__aeabi_i2d> + 801872e: 4602 mov r2, r0 + 8018730: 460b mov r3, r1 + 8018732: 4630 mov r0, r6 + 8018734: 4639 mov r1, r7 + 8018736: f7e7 fda7 bl 8000288 <__aeabi_dsub> + 801873a: f1ba 0f00 cmp.w sl, #0 + 801873e: 4606 mov r6, r0 + 8018740: 460f mov r7, r1 + 8018742: dd6d ble.n 8018820 <__kernel_rem_pio2+0x250> + 8018744: 1e61 subs r1, r4, #1 + 8018746: ab0c add r3, sp, #48 ; 0x30 + 8018748: 9d02 ldr r5, [sp, #8] + 801874a: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 801874e: f1ca 0018 rsb r0, sl, #24 + 8018752: fa43 f200 asr.w r2, r3, r0 + 8018756: 4415 add r5, r2 + 8018758: 4082 lsls r2, r0 + 801875a: 1a9b subs r3, r3, r2 + 801875c: aa0c add r2, sp, #48 ; 0x30 + 801875e: 9502 str r5, [sp, #8] + 8018760: f842 3021 str.w r3, [r2, r1, lsl #2] + 8018764: f1ca 0217 rsb r2, sl, #23 + 8018768: fa43 fb02 asr.w fp, r3, r2 + 801876c: f1bb 0f00 cmp.w fp, #0 + 8018770: dd65 ble.n 801883e <__kernel_rem_pio2+0x26e> + 8018772: 9b02 ldr r3, [sp, #8] + 8018774: 2200 movs r2, #0 + 8018776: 3301 adds r3, #1 + 8018778: 9302 str r3, [sp, #8] + 801877a: 4615 mov r5, r2 + 801877c: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 + 8018780: 4294 cmp r4, r2 + 8018782: f300 809f bgt.w 80188c4 <__kernel_rem_pio2+0x2f4> + 8018786: f1ba 0f00 cmp.w sl, #0 + 801878a: dd07 ble.n 801879c <__kernel_rem_pio2+0x1cc> + 801878c: f1ba 0f01 cmp.w sl, #1 + 8018790: f000 80c1 beq.w 8018916 <__kernel_rem_pio2+0x346> + 8018794: f1ba 0f02 cmp.w sl, #2 + 8018798: f000 80c7 beq.w 801892a <__kernel_rem_pio2+0x35a> + 801879c: f1bb 0f02 cmp.w fp, #2 + 80187a0: d14d bne.n 801883e <__kernel_rem_pio2+0x26e> + 80187a2: 4632 mov r2, r6 + 80187a4: 463b mov r3, r7 + 80187a6: 4954 ldr r1, [pc, #336] ; (80188f8 <__kernel_rem_pio2+0x328>) + 80187a8: 2000 movs r0, #0 + 80187aa: f7e7 fd6d bl 8000288 <__aeabi_dsub> + 80187ae: 4606 mov r6, r0 + 80187b0: 460f mov r7, r1 + 80187b2: 2d00 cmp r5, #0 + 80187b4: d043 beq.n 801883e <__kernel_rem_pio2+0x26e> + 80187b6: 4650 mov r0, sl + 80187b8: ed9f 0b4b vldr d0, [pc, #300] ; 80188e8 <__kernel_rem_pio2+0x318> + 80187bc: f000 fa58 bl 8018c70 + 80187c0: 4630 mov r0, r6 + 80187c2: 4639 mov r1, r7 + 80187c4: ec53 2b10 vmov r2, r3, d0 + 80187c8: f7e7 fd5e bl 8000288 <__aeabi_dsub> + 80187cc: 4606 mov r6, r0 + 80187ce: 460f mov r7, r1 + 80187d0: e035 b.n 801883e <__kernel_rem_pio2+0x26e> + 80187d2: 4b4a ldr r3, [pc, #296] ; (80188fc <__kernel_rem_pio2+0x32c>) + 80187d4: 2200 movs r2, #0 + 80187d6: 4630 mov r0, r6 + 80187d8: 4639 mov r1, r7 + 80187da: f7e7 ff0d bl 80005f8 <__aeabi_dmul> + 80187de: f7e8 f9bb bl 8000b58 <__aeabi_d2iz> + 80187e2: f7e7 fe9f bl 8000524 <__aeabi_i2d> + 80187e6: 4602 mov r2, r0 + 80187e8: 460b mov r3, r1 + 80187ea: ec43 2b18 vmov d8, r2, r3 + 80187ee: 4b44 ldr r3, [pc, #272] ; (8018900 <__kernel_rem_pio2+0x330>) + 80187f0: 2200 movs r2, #0 + 80187f2: f7e7 ff01 bl 80005f8 <__aeabi_dmul> + 80187f6: 4602 mov r2, r0 + 80187f8: 460b mov r3, r1 + 80187fa: 4630 mov r0, r6 + 80187fc: 4639 mov r1, r7 + 80187fe: f7e7 fd43 bl 8000288 <__aeabi_dsub> + 8018802: f7e8 f9a9 bl 8000b58 <__aeabi_d2iz> + 8018806: e9d5 2300 ldrd r2, r3, [r5] + 801880a: f84b 0b04 str.w r0, [fp], #4 + 801880e: ec51 0b18 vmov r0, r1, d8 + 8018812: f7e7 fd3b bl 800028c <__adddf3> + 8018816: f109 39ff add.w r9, r9, #4294967295 + 801881a: 4606 mov r6, r0 + 801881c: 460f mov r7, r1 + 801881e: e75b b.n 80186d8 <__kernel_rem_pio2+0x108> + 8018820: d106 bne.n 8018830 <__kernel_rem_pio2+0x260> + 8018822: 1e63 subs r3, r4, #1 + 8018824: aa0c add r2, sp, #48 ; 0x30 + 8018826: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 801882a: ea4f 5be3 mov.w fp, r3, asr #23 + 801882e: e79d b.n 801876c <__kernel_rem_pio2+0x19c> + 8018830: 4b34 ldr r3, [pc, #208] ; (8018904 <__kernel_rem_pio2+0x334>) + 8018832: 2200 movs r2, #0 + 8018834: f7e8 f966 bl 8000b04 <__aeabi_dcmpge> + 8018838: 2800 cmp r0, #0 + 801883a: d140 bne.n 80188be <__kernel_rem_pio2+0x2ee> + 801883c: 4683 mov fp, r0 + 801883e: 2200 movs r2, #0 + 8018840: 2300 movs r3, #0 + 8018842: 4630 mov r0, r6 + 8018844: 4639 mov r1, r7 + 8018846: f7e8 f93f bl 8000ac8 <__aeabi_dcmpeq> + 801884a: 2800 cmp r0, #0 + 801884c: f000 80c1 beq.w 80189d2 <__kernel_rem_pio2+0x402> + 8018850: 1e65 subs r5, r4, #1 + 8018852: 462b mov r3, r5 + 8018854: 2200 movs r2, #0 + 8018856: 9900 ldr r1, [sp, #0] + 8018858: 428b cmp r3, r1 + 801885a: da6d bge.n 8018938 <__kernel_rem_pio2+0x368> + 801885c: 2a00 cmp r2, #0 + 801885e: f000 808a beq.w 8018976 <__kernel_rem_pio2+0x3a6> + 8018862: ab0c add r3, sp, #48 ; 0x30 + 8018864: f1aa 0a18 sub.w sl, sl, #24 + 8018868: f853 3025 ldr.w r3, [r3, r5, lsl #2] + 801886c: 2b00 cmp r3, #0 + 801886e: f000 80ae beq.w 80189ce <__kernel_rem_pio2+0x3fe> + 8018872: 4650 mov r0, sl + 8018874: ed9f 0b1c vldr d0, [pc, #112] ; 80188e8 <__kernel_rem_pio2+0x318> + 8018878: f000 f9fa bl 8018c70 + 801887c: 1c6b adds r3, r5, #1 + 801887e: 00da lsls r2, r3, #3 + 8018880: 9205 str r2, [sp, #20] + 8018882: ec57 6b10 vmov r6, r7, d0 + 8018886: aa70 add r2, sp, #448 ; 0x1c0 + 8018888: f8df 9070 ldr.w r9, [pc, #112] ; 80188fc <__kernel_rem_pio2+0x32c> + 801888c: eb02 0ac3 add.w sl, r2, r3, lsl #3 + 8018890: 462c mov r4, r5 + 8018892: f04f 0800 mov.w r8, #0 + 8018896: 2c00 cmp r4, #0 + 8018898: f280 80d4 bge.w 8018a44 <__kernel_rem_pio2+0x474> + 801889c: 462c mov r4, r5 + 801889e: 2c00 cmp r4, #0 + 80188a0: f2c0 8102 blt.w 8018aa8 <__kernel_rem_pio2+0x4d8> + 80188a4: 4b18 ldr r3, [pc, #96] ; (8018908 <__kernel_rem_pio2+0x338>) + 80188a6: 461e mov r6, r3 + 80188a8: ab70 add r3, sp, #448 ; 0x1c0 + 80188aa: eb03 08c4 add.w r8, r3, r4, lsl #3 + 80188ae: 1b2b subs r3, r5, r4 + 80188b0: f04f 0900 mov.w r9, #0 + 80188b4: f04f 0a00 mov.w sl, #0 + 80188b8: 2700 movs r7, #0 + 80188ba: 9306 str r3, [sp, #24] + 80188bc: e0e6 b.n 8018a8c <__kernel_rem_pio2+0x4bc> + 80188be: f04f 0b02 mov.w fp, #2 + 80188c2: e756 b.n 8018772 <__kernel_rem_pio2+0x1a2> + 80188c4: f8d8 3000 ldr.w r3, [r8] + 80188c8: bb05 cbnz r5, 801890c <__kernel_rem_pio2+0x33c> + 80188ca: b123 cbz r3, 80188d6 <__kernel_rem_pio2+0x306> + 80188cc: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 + 80188d0: f8c8 3000 str.w r3, [r8] + 80188d4: 2301 movs r3, #1 + 80188d6: 3201 adds r2, #1 + 80188d8: f108 0804 add.w r8, r8, #4 + 80188dc: 461d mov r5, r3 + 80188de: e74f b.n 8018780 <__kernel_rem_pio2+0x1b0> ... - 801643c: 3ff00000 .word 0x3ff00000 - 8016440: 08018d78 .word 0x08018d78 - 8016444: 40200000 .word 0x40200000 - 8016448: 3ff00000 .word 0x3ff00000 - 801644c: 3e700000 .word 0x3e700000 - 8016450: 41700000 .word 0x41700000 - 8016454: 3fe00000 .word 0x3fe00000 - 8016458: 08018d38 .word 0x08018d38 - 801645c: 1acb subs r3, r1, r3 - 801645e: f8c8 3000 str.w r3, [r8] - 8016462: 462b mov r3, r5 - 8016464: e7df b.n 8016426 <__kernel_rem_pio2+0x306> - 8016466: 1e62 subs r2, r4, #1 - 8016468: ab0c add r3, sp, #48 ; 0x30 - 801646a: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 801646e: f3c3 0316 ubfx r3, r3, #0, #23 - 8016472: a90c add r1, sp, #48 ; 0x30 - 8016474: f841 3022 str.w r3, [r1, r2, lsl #2] - 8016478: e738 b.n 80162ec <__kernel_rem_pio2+0x1cc> - 801647a: 1e62 subs r2, r4, #1 - 801647c: ab0c add r3, sp, #48 ; 0x30 - 801647e: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8016482: f3c3 0315 ubfx r3, r3, #0, #22 - 8016486: e7f4 b.n 8016472 <__kernel_rem_pio2+0x352> - 8016488: a90c add r1, sp, #48 ; 0x30 - 801648a: f851 1023 ldr.w r1, [r1, r3, lsl #2] - 801648e: 3b01 subs r3, #1 - 8016490: 430a orrs r2, r1 - 8016492: e788 b.n 80163a6 <__kernel_rem_pio2+0x286> - 8016494: 3301 adds r3, #1 - 8016496: f852 1d04 ldr.w r1, [r2, #-4]! - 801649a: 2900 cmp r1, #0 - 801649c: d0fa beq.n 8016494 <__kernel_rem_pio2+0x374> - 801649e: 9a08 ldr r2, [sp, #32] - 80164a0: f502 7218 add.w r2, r2, #608 ; 0x260 - 80164a4: 446a add r2, sp - 80164a6: 3a98 subs r2, #152 ; 0x98 - 80164a8: 9208 str r2, [sp, #32] - 80164aa: 9a06 ldr r2, [sp, #24] - 80164ac: a920 add r1, sp, #128 ; 0x80 - 80164ae: 18a2 adds r2, r4, r2 - 80164b0: 18e3 adds r3, r4, r3 - 80164b2: f104 0801 add.w r8, r4, #1 - 80164b6: eb01 05c2 add.w r5, r1, r2, lsl #3 - 80164ba: 9302 str r3, [sp, #8] - 80164bc: 9b02 ldr r3, [sp, #8] - 80164be: 4543 cmp r3, r8 - 80164c0: da04 bge.n 80164cc <__kernel_rem_pio2+0x3ac> - 80164c2: 461c mov r4, r3 - 80164c4: e6a2 b.n 801620c <__kernel_rem_pio2+0xec> - 80164c6: 9a0b ldr r2, [sp, #44] ; 0x2c - 80164c8: 2301 movs r3, #1 - 80164ca: e7e4 b.n 8016496 <__kernel_rem_pio2+0x376> - 80164cc: 9b0a ldr r3, [sp, #40] ; 0x28 - 80164ce: f853 0028 ldr.w r0, [r3, r8, lsl #2] - 80164d2: f7ea f827 bl 8000524 <__aeabi_i2d> - 80164d6: e8e5 0102 strd r0, r1, [r5], #8 - 80164da: 9b09 ldr r3, [sp, #36] ; 0x24 - 80164dc: 46ab mov fp, r5 - 80164de: 461c mov r4, r3 - 80164e0: f04f 0900 mov.w r9, #0 - 80164e4: 2600 movs r6, #0 - 80164e6: 2700 movs r7, #0 - 80164e8: 9b05 ldr r3, [sp, #20] - 80164ea: 4599 cmp r9, r3 - 80164ec: dd06 ble.n 80164fc <__kernel_rem_pio2+0x3dc> - 80164ee: 9b08 ldr r3, [sp, #32] - 80164f0: e8e3 6702 strd r6, r7, [r3], #8 - 80164f4: f108 0801 add.w r8, r8, #1 - 80164f8: 9308 str r3, [sp, #32] - 80164fa: e7df b.n 80164bc <__kernel_rem_pio2+0x39c> - 80164fc: e97b 2302 ldrd r2, r3, [fp, #-8]! - 8016500: e8f4 0102 ldrd r0, r1, [r4], #8 - 8016504: f7ea f878 bl 80005f8 <__aeabi_dmul> - 8016508: 4602 mov r2, r0 - 801650a: 460b mov r3, r1 - 801650c: 4630 mov r0, r6 - 801650e: 4639 mov r1, r7 - 8016510: f7e9 febc bl 800028c <__adddf3> - 8016514: f109 0901 add.w r9, r9, #1 - 8016518: 4606 mov r6, r0 - 801651a: 460f mov r7, r1 - 801651c: e7e4 b.n 80164e8 <__kernel_rem_pio2+0x3c8> - 801651e: 3d01 subs r5, #1 - 8016520: e747 b.n 80163b2 <__kernel_rem_pio2+0x292> - 8016522: ec47 6b10 vmov d0, r6, r7 - 8016526: f1ca 0000 rsb r0, sl, #0 - 801652a: f000 f949 bl 80167c0 - 801652e: ec57 6b10 vmov r6, r7, d0 - 8016532: 4ba0 ldr r3, [pc, #640] ; (80167b4 <__kernel_rem_pio2+0x694>) - 8016534: ee10 0a10 vmov r0, s0 - 8016538: 2200 movs r2, #0 - 801653a: 4639 mov r1, r7 - 801653c: f7ea fae2 bl 8000b04 <__aeabi_dcmpge> - 8016540: b1f8 cbz r0, 8016582 <__kernel_rem_pio2+0x462> - 8016542: 4b9d ldr r3, [pc, #628] ; (80167b8 <__kernel_rem_pio2+0x698>) - 8016544: 2200 movs r2, #0 - 8016546: 4630 mov r0, r6 - 8016548: 4639 mov r1, r7 - 801654a: f7ea f855 bl 80005f8 <__aeabi_dmul> - 801654e: f7ea fb03 bl 8000b58 <__aeabi_d2iz> - 8016552: 4680 mov r8, r0 - 8016554: f7e9 ffe6 bl 8000524 <__aeabi_i2d> - 8016558: 4b96 ldr r3, [pc, #600] ; (80167b4 <__kernel_rem_pio2+0x694>) - 801655a: 2200 movs r2, #0 - 801655c: f7ea f84c bl 80005f8 <__aeabi_dmul> - 8016560: 460b mov r3, r1 - 8016562: 4602 mov r2, r0 - 8016564: 4639 mov r1, r7 - 8016566: 4630 mov r0, r6 - 8016568: f7e9 fe8e bl 8000288 <__aeabi_dsub> - 801656c: f7ea faf4 bl 8000b58 <__aeabi_d2iz> - 8016570: 1c65 adds r5, r4, #1 - 8016572: ab0c add r3, sp, #48 ; 0x30 - 8016574: f10a 0a18 add.w sl, sl, #24 - 8016578: f843 0024 str.w r0, [r3, r4, lsl #2] - 801657c: f843 8025 str.w r8, [r3, r5, lsl #2] - 8016580: e71f b.n 80163c2 <__kernel_rem_pio2+0x2a2> - 8016582: 4630 mov r0, r6 - 8016584: 4639 mov r1, r7 - 8016586: f7ea fae7 bl 8000b58 <__aeabi_d2iz> - 801658a: ab0c add r3, sp, #48 ; 0x30 - 801658c: 4625 mov r5, r4 - 801658e: f843 0024 str.w r0, [r3, r4, lsl #2] - 8016592: e716 b.n 80163c2 <__kernel_rem_pio2+0x2a2> - 8016594: ab0c add r3, sp, #48 ; 0x30 - 8016596: f853 0024 ldr.w r0, [r3, r4, lsl #2] - 801659a: f7e9 ffc3 bl 8000524 <__aeabi_i2d> - 801659e: 4632 mov r2, r6 - 80165a0: 463b mov r3, r7 - 80165a2: f7ea f829 bl 80005f8 <__aeabi_dmul> - 80165a6: 4642 mov r2, r8 - 80165a8: e96a 0102 strd r0, r1, [sl, #-8]! - 80165ac: 464b mov r3, r9 - 80165ae: 4630 mov r0, r6 - 80165b0: 4639 mov r1, r7 - 80165b2: f7ea f821 bl 80005f8 <__aeabi_dmul> - 80165b6: 3c01 subs r4, #1 - 80165b8: 4606 mov r6, r0 - 80165ba: 460f mov r7, r1 - 80165bc: e713 b.n 80163e6 <__kernel_rem_pio2+0x2c6> - 80165be: e8f8 2302 ldrd r2, r3, [r8], #8 - 80165c2: e8f6 0102 ldrd r0, r1, [r6], #8 - 80165c6: f7ea f817 bl 80005f8 <__aeabi_dmul> - 80165ca: 4602 mov r2, r0 - 80165cc: 460b mov r3, r1 - 80165ce: 4648 mov r0, r9 - 80165d0: 4651 mov r1, sl - 80165d2: f7e9 fe5b bl 800028c <__adddf3> - 80165d6: 3701 adds r7, #1 - 80165d8: 4681 mov r9, r0 - 80165da: 468a mov sl, r1 - 80165dc: 9b00 ldr r3, [sp, #0] - 80165de: 429f cmp r7, r3 - 80165e0: dc02 bgt.n 80165e8 <__kernel_rem_pio2+0x4c8> - 80165e2: 9b06 ldr r3, [sp, #24] - 80165e4: 429f cmp r7, r3 - 80165e6: ddea ble.n 80165be <__kernel_rem_pio2+0x49e> - 80165e8: 9a06 ldr r2, [sp, #24] - 80165ea: ab48 add r3, sp, #288 ; 0x120 - 80165ec: eb03 06c2 add.w r6, r3, r2, lsl #3 - 80165f0: e9c6 9a00 strd r9, sl, [r6] - 80165f4: 3c01 subs r4, #1 - 80165f6: e6fa b.n 80163ee <__kernel_rem_pio2+0x2ce> - 80165f8: 9ba4 ldr r3, [sp, #656] ; 0x290 - 80165fa: 2b02 cmp r3, #2 - 80165fc: dc0b bgt.n 8016616 <__kernel_rem_pio2+0x4f6> - 80165fe: 2b00 cmp r3, #0 - 8016600: dc39 bgt.n 8016676 <__kernel_rem_pio2+0x556> - 8016602: d05d beq.n 80166c0 <__kernel_rem_pio2+0x5a0> - 8016604: 9b02 ldr r3, [sp, #8] - 8016606: f003 0007 and.w r0, r3, #7 - 801660a: f50d 7d19 add.w sp, sp, #612 ; 0x264 - 801660e: ecbd 8b02 vpop {d8} - 8016612: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8016616: 9ba4 ldr r3, [sp, #656] ; 0x290 - 8016618: 2b03 cmp r3, #3 - 801661a: d1f3 bne.n 8016604 <__kernel_rem_pio2+0x4e4> - 801661c: 9b05 ldr r3, [sp, #20] - 801661e: 9500 str r5, [sp, #0] - 8016620: f503 7318 add.w r3, r3, #608 ; 0x260 - 8016624: eb0d 0403 add.w r4, sp, r3 - 8016628: f5a4 74a4 sub.w r4, r4, #328 ; 0x148 - 801662c: 46a2 mov sl, r4 - 801662e: 9b00 ldr r3, [sp, #0] - 8016630: 2b00 cmp r3, #0 - 8016632: f1aa 0a08 sub.w sl, sl, #8 - 8016636: dc69 bgt.n 801670c <__kernel_rem_pio2+0x5ec> - 8016638: 46aa mov sl, r5 - 801663a: f1ba 0f01 cmp.w sl, #1 - 801663e: f1a4 0408 sub.w r4, r4, #8 - 8016642: f300 8083 bgt.w 801674c <__kernel_rem_pio2+0x62c> - 8016646: 9c05 ldr r4, [sp, #20] - 8016648: ab48 add r3, sp, #288 ; 0x120 - 801664a: 441c add r4, r3 - 801664c: 2000 movs r0, #0 - 801664e: 2100 movs r1, #0 - 8016650: 2d01 cmp r5, #1 - 8016652: f300 809a bgt.w 801678a <__kernel_rem_pio2+0x66a> - 8016656: e9dd 7848 ldrd r7, r8, [sp, #288] ; 0x120 - 801665a: e9dd 564a ldrd r5, r6, [sp, #296] ; 0x128 - 801665e: f1bb 0f00 cmp.w fp, #0 - 8016662: f040 8098 bne.w 8016796 <__kernel_rem_pio2+0x676> - 8016666: 9b04 ldr r3, [sp, #16] - 8016668: e9c3 7800 strd r7, r8, [r3] - 801666c: e9c3 5602 strd r5, r6, [r3, #8] - 8016670: e9c3 0104 strd r0, r1, [r3, #16] - 8016674: e7c6 b.n 8016604 <__kernel_rem_pio2+0x4e4> - 8016676: 9e05 ldr r6, [sp, #20] - 8016678: ab48 add r3, sp, #288 ; 0x120 - 801667a: 441e add r6, r3 - 801667c: 462c mov r4, r5 - 801667e: 2000 movs r0, #0 - 8016680: 2100 movs r1, #0 - 8016682: 2c00 cmp r4, #0 - 8016684: da33 bge.n 80166ee <__kernel_rem_pio2+0x5ce> - 8016686: f1bb 0f00 cmp.w fp, #0 - 801668a: d036 beq.n 80166fa <__kernel_rem_pio2+0x5da> - 801668c: 4602 mov r2, r0 - 801668e: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 8016692: 9c04 ldr r4, [sp, #16] - 8016694: e9c4 2300 strd r2, r3, [r4] - 8016698: 4602 mov r2, r0 - 801669a: 460b mov r3, r1 - 801669c: e9dd 0148 ldrd r0, r1, [sp, #288] ; 0x120 - 80166a0: f7e9 fdf2 bl 8000288 <__aeabi_dsub> - 80166a4: ae4a add r6, sp, #296 ; 0x128 - 80166a6: 2401 movs r4, #1 - 80166a8: 42a5 cmp r5, r4 - 80166aa: da29 bge.n 8016700 <__kernel_rem_pio2+0x5e0> - 80166ac: f1bb 0f00 cmp.w fp, #0 - 80166b0: d002 beq.n 80166b8 <__kernel_rem_pio2+0x598> - 80166b2: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 80166b6: 4619 mov r1, r3 - 80166b8: 9b04 ldr r3, [sp, #16] - 80166ba: e9c3 0102 strd r0, r1, [r3, #8] - 80166be: e7a1 b.n 8016604 <__kernel_rem_pio2+0x4e4> - 80166c0: 9c05 ldr r4, [sp, #20] - 80166c2: ab48 add r3, sp, #288 ; 0x120 - 80166c4: 441c add r4, r3 - 80166c6: 2000 movs r0, #0 - 80166c8: 2100 movs r1, #0 - 80166ca: 2d00 cmp r5, #0 - 80166cc: da09 bge.n 80166e2 <__kernel_rem_pio2+0x5c2> - 80166ce: f1bb 0f00 cmp.w fp, #0 - 80166d2: d002 beq.n 80166da <__kernel_rem_pio2+0x5ba> - 80166d4: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 80166d8: 4619 mov r1, r3 - 80166da: 9b04 ldr r3, [sp, #16] - 80166dc: e9c3 0100 strd r0, r1, [r3] - 80166e0: e790 b.n 8016604 <__kernel_rem_pio2+0x4e4> - 80166e2: e974 2302 ldrd r2, r3, [r4, #-8]! - 80166e6: f7e9 fdd1 bl 800028c <__adddf3> - 80166ea: 3d01 subs r5, #1 - 80166ec: e7ed b.n 80166ca <__kernel_rem_pio2+0x5aa> - 80166ee: e976 2302 ldrd r2, r3, [r6, #-8]! - 80166f2: f7e9 fdcb bl 800028c <__adddf3> - 80166f6: 3c01 subs r4, #1 - 80166f8: e7c3 b.n 8016682 <__kernel_rem_pio2+0x562> - 80166fa: 4602 mov r2, r0 - 80166fc: 460b mov r3, r1 - 80166fe: e7c8 b.n 8016692 <__kernel_rem_pio2+0x572> - 8016700: e8f6 2302 ldrd r2, r3, [r6], #8 - 8016704: f7e9 fdc2 bl 800028c <__adddf3> - 8016708: 3401 adds r4, #1 - 801670a: e7cd b.n 80166a8 <__kernel_rem_pio2+0x588> - 801670c: e9da 8900 ldrd r8, r9, [sl] - 8016710: e9da 6702 ldrd r6, r7, [sl, #8] - 8016714: 9b00 ldr r3, [sp, #0] - 8016716: 3b01 subs r3, #1 - 8016718: 9300 str r3, [sp, #0] - 801671a: 4632 mov r2, r6 - 801671c: 463b mov r3, r7 - 801671e: 4640 mov r0, r8 - 8016720: 4649 mov r1, r9 - 8016722: f7e9 fdb3 bl 800028c <__adddf3> - 8016726: e9cd 0106 strd r0, r1, [sp, #24] - 801672a: 4602 mov r2, r0 - 801672c: 460b mov r3, r1 - 801672e: 4640 mov r0, r8 - 8016730: 4649 mov r1, r9 - 8016732: f7e9 fda9 bl 8000288 <__aeabi_dsub> - 8016736: 4632 mov r2, r6 - 8016738: 463b mov r3, r7 - 801673a: f7e9 fda7 bl 800028c <__adddf3> - 801673e: ed9d 7b06 vldr d7, [sp, #24] - 8016742: e9ca 0102 strd r0, r1, [sl, #8] - 8016746: ed8a 7b00 vstr d7, [sl] - 801674a: e770 b.n 801662e <__kernel_rem_pio2+0x50e> - 801674c: e9d4 8900 ldrd r8, r9, [r4] - 8016750: e9d4 6702 ldrd r6, r7, [r4, #8] - 8016754: 4640 mov r0, r8 - 8016756: 4632 mov r2, r6 - 8016758: 463b mov r3, r7 - 801675a: 4649 mov r1, r9 - 801675c: f7e9 fd96 bl 800028c <__adddf3> - 8016760: e9cd 0100 strd r0, r1, [sp] - 8016764: 4602 mov r2, r0 - 8016766: 460b mov r3, r1 - 8016768: 4640 mov r0, r8 - 801676a: 4649 mov r1, r9 - 801676c: f7e9 fd8c bl 8000288 <__aeabi_dsub> - 8016770: 4632 mov r2, r6 - 8016772: 463b mov r3, r7 - 8016774: f7e9 fd8a bl 800028c <__adddf3> - 8016778: ed9d 7b00 vldr d7, [sp] - 801677c: e9c4 0102 strd r0, r1, [r4, #8] - 8016780: ed84 7b00 vstr d7, [r4] - 8016784: f10a 3aff add.w sl, sl, #4294967295 - 8016788: e757 b.n 801663a <__kernel_rem_pio2+0x51a> - 801678a: e974 2302 ldrd r2, r3, [r4, #-8]! - 801678e: f7e9 fd7d bl 800028c <__adddf3> - 8016792: 3d01 subs r5, #1 - 8016794: e75c b.n 8016650 <__kernel_rem_pio2+0x530> - 8016796: 9b04 ldr r3, [sp, #16] - 8016798: 9a04 ldr r2, [sp, #16] - 801679a: 601f str r7, [r3, #0] - 801679c: f108 4400 add.w r4, r8, #2147483648 ; 0x80000000 - 80167a0: 605c str r4, [r3, #4] - 80167a2: 609d str r5, [r3, #8] - 80167a4: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 - 80167a8: 60d3 str r3, [r2, #12] - 80167aa: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 - 80167ae: 6110 str r0, [r2, #16] - 80167b0: 6153 str r3, [r2, #20] - 80167b2: e727 b.n 8016604 <__kernel_rem_pio2+0x4e4> - 80167b4: 41700000 .word 0x41700000 - 80167b8: 3e700000 .word 0x3e700000 - 80167bc: 00000000 .word 0x00000000 - -080167c0 : - 80167c0: b570 push {r4, r5, r6, lr} - 80167c2: ec55 4b10 vmov r4, r5, d0 - 80167c6: f3c5 510a ubfx r1, r5, #20, #11 - 80167ca: 4606 mov r6, r0 - 80167cc: 462b mov r3, r5 - 80167ce: b999 cbnz r1, 80167f8 - 80167d0: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 - 80167d4: 4323 orrs r3, r4 - 80167d6: d03f beq.n 8016858 - 80167d8: 4b35 ldr r3, [pc, #212] ; (80168b0 ) - 80167da: 4629 mov r1, r5 - 80167dc: ee10 0a10 vmov r0, s0 - 80167e0: 2200 movs r2, #0 - 80167e2: f7e9 ff09 bl 80005f8 <__aeabi_dmul> - 80167e6: 4b33 ldr r3, [pc, #204] ; (80168b4 ) - 80167e8: 429e cmp r6, r3 - 80167ea: 4604 mov r4, r0 - 80167ec: 460d mov r5, r1 - 80167ee: da10 bge.n 8016812 - 80167f0: a327 add r3, pc, #156 ; (adr r3, 8016890 ) - 80167f2: e9d3 2300 ldrd r2, r3, [r3] - 80167f6: e01f b.n 8016838 - 80167f8: f240 72ff movw r2, #2047 ; 0x7ff - 80167fc: 4291 cmp r1, r2 - 80167fe: d10c bne.n 801681a - 8016800: ee10 2a10 vmov r2, s0 - 8016804: 4620 mov r0, r4 - 8016806: 4629 mov r1, r5 - 8016808: f7e9 fd40 bl 800028c <__adddf3> - 801680c: 4604 mov r4, r0 - 801680e: 460d mov r5, r1 - 8016810: e022 b.n 8016858 - 8016812: 460b mov r3, r1 - 8016814: f3c1 510a ubfx r1, r1, #20, #11 - 8016818: 3936 subs r1, #54 ; 0x36 - 801681a: f24c 3250 movw r2, #50000 ; 0xc350 - 801681e: 4296 cmp r6, r2 - 8016820: dd0d ble.n 801683e - 8016822: 2d00 cmp r5, #0 - 8016824: a11c add r1, pc, #112 ; (adr r1, 8016898 ) - 8016826: e9d1 0100 ldrd r0, r1, [r1] - 801682a: da02 bge.n 8016832 - 801682c: a11c add r1, pc, #112 ; (adr r1, 80168a0 ) - 801682e: e9d1 0100 ldrd r0, r1, [r1] - 8016832: a319 add r3, pc, #100 ; (adr r3, 8016898 ) - 8016834: e9d3 2300 ldrd r2, r3, [r3] - 8016838: f7e9 fede bl 80005f8 <__aeabi_dmul> - 801683c: e7e6 b.n 801680c - 801683e: 1872 adds r2, r6, r1 - 8016840: f240 71fe movw r1, #2046 ; 0x7fe - 8016844: 428a cmp r2, r1 - 8016846: dcec bgt.n 8016822 - 8016848: 2a00 cmp r2, #0 - 801684a: dd08 ble.n 801685e - 801684c: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 - 8016850: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 - 8016854: ea43 5502 orr.w r5, r3, r2, lsl #20 - 8016858: ec45 4b10 vmov d0, r4, r5 - 801685c: bd70 pop {r4, r5, r6, pc} - 801685e: f112 0f35 cmn.w r2, #53 ; 0x35 - 8016862: da08 bge.n 8016876 - 8016864: 2d00 cmp r5, #0 - 8016866: a10a add r1, pc, #40 ; (adr r1, 8016890 ) - 8016868: e9d1 0100 ldrd r0, r1, [r1] - 801686c: dac0 bge.n 80167f0 - 801686e: a10e add r1, pc, #56 ; (adr r1, 80168a8 ) - 8016870: e9d1 0100 ldrd r0, r1, [r1] - 8016874: e7bc b.n 80167f0 - 8016876: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 - 801687a: 3236 adds r2, #54 ; 0x36 - 801687c: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 - 8016880: ea43 5102 orr.w r1, r3, r2, lsl #20 - 8016884: 4620 mov r0, r4 - 8016886: 4b0c ldr r3, [pc, #48] ; (80168b8 ) - 8016888: 2200 movs r2, #0 - 801688a: e7d5 b.n 8016838 - 801688c: f3af 8000 nop.w - 8016890: c2f8f359 .word 0xc2f8f359 - 8016894: 01a56e1f .word 0x01a56e1f - 8016898: 8800759c .word 0x8800759c - 801689c: 7e37e43c .word 0x7e37e43c - 80168a0: 8800759c .word 0x8800759c - 80168a4: fe37e43c .word 0xfe37e43c - 80168a8: c2f8f359 .word 0xc2f8f359 - 80168ac: 81a56e1f .word 0x81a56e1f - 80168b0: 43500000 .word 0x43500000 - 80168b4: ffff3cb0 .word 0xffff3cb0 - 80168b8: 3c900000 .word 0x3c900000 - -080168bc <_init>: - 80168bc: b5f8 push {r3, r4, r5, r6, r7, lr} - 80168be: bf00 nop - 80168c0: bcf8 pop {r3, r4, r5, r6, r7} - 80168c2: bc08 pop {r3} - 80168c4: 469e mov lr, r3 - 80168c6: 4770 bx lr - -080168c8 <_fini>: - 80168c8: b5f8 push {r3, r4, r5, r6, r7, lr} - 80168ca: bf00 nop - 80168cc: bcf8 pop {r3, r4, r5, r6, r7} - 80168ce: bc08 pop {r3} - 80168d0: 469e mov lr, r3 - 80168d2: 4770 bx lr + 80188ec: 3ff00000 .word 0x3ff00000 + 80188f0: 0801b250 .word 0x0801b250 + 80188f4: 40200000 .word 0x40200000 + 80188f8: 3ff00000 .word 0x3ff00000 + 80188fc: 3e700000 .word 0x3e700000 + 8018900: 41700000 .word 0x41700000 + 8018904: 3fe00000 .word 0x3fe00000 + 8018908: 0801b210 .word 0x0801b210 + 801890c: 1acb subs r3, r1, r3 + 801890e: f8c8 3000 str.w r3, [r8] + 8018912: 462b mov r3, r5 + 8018914: e7df b.n 80188d6 <__kernel_rem_pio2+0x306> + 8018916: 1e62 subs r2, r4, #1 + 8018918: ab0c add r3, sp, #48 ; 0x30 + 801891a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 801891e: f3c3 0316 ubfx r3, r3, #0, #23 + 8018922: a90c add r1, sp, #48 ; 0x30 + 8018924: f841 3022 str.w r3, [r1, r2, lsl #2] + 8018928: e738 b.n 801879c <__kernel_rem_pio2+0x1cc> + 801892a: 1e62 subs r2, r4, #1 + 801892c: ab0c add r3, sp, #48 ; 0x30 + 801892e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8018932: f3c3 0315 ubfx r3, r3, #0, #22 + 8018936: e7f4 b.n 8018922 <__kernel_rem_pio2+0x352> + 8018938: a90c add r1, sp, #48 ; 0x30 + 801893a: f851 1023 ldr.w r1, [r1, r3, lsl #2] + 801893e: 3b01 subs r3, #1 + 8018940: 430a orrs r2, r1 + 8018942: e788 b.n 8018856 <__kernel_rem_pio2+0x286> + 8018944: 3301 adds r3, #1 + 8018946: f852 1d04 ldr.w r1, [r2, #-4]! + 801894a: 2900 cmp r1, #0 + 801894c: d0fa beq.n 8018944 <__kernel_rem_pio2+0x374> + 801894e: 9a08 ldr r2, [sp, #32] + 8018950: f502 7218 add.w r2, r2, #608 ; 0x260 + 8018954: 446a add r2, sp + 8018956: 3a98 subs r2, #152 ; 0x98 + 8018958: 9208 str r2, [sp, #32] + 801895a: 9a06 ldr r2, [sp, #24] + 801895c: a920 add r1, sp, #128 ; 0x80 + 801895e: 18a2 adds r2, r4, r2 + 8018960: 18e3 adds r3, r4, r3 + 8018962: f104 0801 add.w r8, r4, #1 + 8018966: eb01 05c2 add.w r5, r1, r2, lsl #3 + 801896a: 9302 str r3, [sp, #8] + 801896c: 9b02 ldr r3, [sp, #8] + 801896e: 4543 cmp r3, r8 + 8018970: da04 bge.n 801897c <__kernel_rem_pio2+0x3ac> + 8018972: 461c mov r4, r3 + 8018974: e6a2 b.n 80186bc <__kernel_rem_pio2+0xec> + 8018976: 9a0b ldr r2, [sp, #44] ; 0x2c + 8018978: 2301 movs r3, #1 + 801897a: e7e4 b.n 8018946 <__kernel_rem_pio2+0x376> + 801897c: 9b0a ldr r3, [sp, #40] ; 0x28 + 801897e: f853 0028 ldr.w r0, [r3, r8, lsl #2] + 8018982: f7e7 fdcf bl 8000524 <__aeabi_i2d> + 8018986: e8e5 0102 strd r0, r1, [r5], #8 + 801898a: 9b09 ldr r3, [sp, #36] ; 0x24 + 801898c: 46ab mov fp, r5 + 801898e: 461c mov r4, r3 + 8018990: f04f 0900 mov.w r9, #0 + 8018994: 2600 movs r6, #0 + 8018996: 2700 movs r7, #0 + 8018998: 9b05 ldr r3, [sp, #20] + 801899a: 4599 cmp r9, r3 + 801899c: dd06 ble.n 80189ac <__kernel_rem_pio2+0x3dc> + 801899e: 9b08 ldr r3, [sp, #32] + 80189a0: e8e3 6702 strd r6, r7, [r3], #8 + 80189a4: f108 0801 add.w r8, r8, #1 + 80189a8: 9308 str r3, [sp, #32] + 80189aa: e7df b.n 801896c <__kernel_rem_pio2+0x39c> + 80189ac: e97b 2302 ldrd r2, r3, [fp, #-8]! + 80189b0: e8f4 0102 ldrd r0, r1, [r4], #8 + 80189b4: f7e7 fe20 bl 80005f8 <__aeabi_dmul> + 80189b8: 4602 mov r2, r0 + 80189ba: 460b mov r3, r1 + 80189bc: 4630 mov r0, r6 + 80189be: 4639 mov r1, r7 + 80189c0: f7e7 fc64 bl 800028c <__adddf3> + 80189c4: f109 0901 add.w r9, r9, #1 + 80189c8: 4606 mov r6, r0 + 80189ca: 460f mov r7, r1 + 80189cc: e7e4 b.n 8018998 <__kernel_rem_pio2+0x3c8> + 80189ce: 3d01 subs r5, #1 + 80189d0: e747 b.n 8018862 <__kernel_rem_pio2+0x292> + 80189d2: ec47 6b10 vmov d0, r6, r7 + 80189d6: f1ca 0000 rsb r0, sl, #0 + 80189da: f000 f949 bl 8018c70 + 80189de: ec57 6b10 vmov r6, r7, d0 + 80189e2: 4ba0 ldr r3, [pc, #640] ; (8018c64 <__kernel_rem_pio2+0x694>) + 80189e4: ee10 0a10 vmov r0, s0 + 80189e8: 2200 movs r2, #0 + 80189ea: 4639 mov r1, r7 + 80189ec: f7e8 f88a bl 8000b04 <__aeabi_dcmpge> + 80189f0: b1f8 cbz r0, 8018a32 <__kernel_rem_pio2+0x462> + 80189f2: 4b9d ldr r3, [pc, #628] ; (8018c68 <__kernel_rem_pio2+0x698>) + 80189f4: 2200 movs r2, #0 + 80189f6: 4630 mov r0, r6 + 80189f8: 4639 mov r1, r7 + 80189fa: f7e7 fdfd bl 80005f8 <__aeabi_dmul> + 80189fe: f7e8 f8ab bl 8000b58 <__aeabi_d2iz> + 8018a02: 4680 mov r8, r0 + 8018a04: f7e7 fd8e bl 8000524 <__aeabi_i2d> + 8018a08: 4b96 ldr r3, [pc, #600] ; (8018c64 <__kernel_rem_pio2+0x694>) + 8018a0a: 2200 movs r2, #0 + 8018a0c: f7e7 fdf4 bl 80005f8 <__aeabi_dmul> + 8018a10: 460b mov r3, r1 + 8018a12: 4602 mov r2, r0 + 8018a14: 4639 mov r1, r7 + 8018a16: 4630 mov r0, r6 + 8018a18: f7e7 fc36 bl 8000288 <__aeabi_dsub> + 8018a1c: f7e8 f89c bl 8000b58 <__aeabi_d2iz> + 8018a20: 1c65 adds r5, r4, #1 + 8018a22: ab0c add r3, sp, #48 ; 0x30 + 8018a24: f10a 0a18 add.w sl, sl, #24 + 8018a28: f843 0024 str.w r0, [r3, r4, lsl #2] + 8018a2c: f843 8025 str.w r8, [r3, r5, lsl #2] + 8018a30: e71f b.n 8018872 <__kernel_rem_pio2+0x2a2> + 8018a32: 4630 mov r0, r6 + 8018a34: 4639 mov r1, r7 + 8018a36: f7e8 f88f bl 8000b58 <__aeabi_d2iz> + 8018a3a: ab0c add r3, sp, #48 ; 0x30 + 8018a3c: 4625 mov r5, r4 + 8018a3e: f843 0024 str.w r0, [r3, r4, lsl #2] + 8018a42: e716 b.n 8018872 <__kernel_rem_pio2+0x2a2> + 8018a44: ab0c add r3, sp, #48 ; 0x30 + 8018a46: f853 0024 ldr.w r0, [r3, r4, lsl #2] + 8018a4a: f7e7 fd6b bl 8000524 <__aeabi_i2d> + 8018a4e: 4632 mov r2, r6 + 8018a50: 463b mov r3, r7 + 8018a52: f7e7 fdd1 bl 80005f8 <__aeabi_dmul> + 8018a56: 4642 mov r2, r8 + 8018a58: e96a 0102 strd r0, r1, [sl, #-8]! + 8018a5c: 464b mov r3, r9 + 8018a5e: 4630 mov r0, r6 + 8018a60: 4639 mov r1, r7 + 8018a62: f7e7 fdc9 bl 80005f8 <__aeabi_dmul> + 8018a66: 3c01 subs r4, #1 + 8018a68: 4606 mov r6, r0 + 8018a6a: 460f mov r7, r1 + 8018a6c: e713 b.n 8018896 <__kernel_rem_pio2+0x2c6> + 8018a6e: e8f8 2302 ldrd r2, r3, [r8], #8 + 8018a72: e8f6 0102 ldrd r0, r1, [r6], #8 + 8018a76: f7e7 fdbf bl 80005f8 <__aeabi_dmul> + 8018a7a: 4602 mov r2, r0 + 8018a7c: 460b mov r3, r1 + 8018a7e: 4648 mov r0, r9 + 8018a80: 4651 mov r1, sl + 8018a82: f7e7 fc03 bl 800028c <__adddf3> + 8018a86: 3701 adds r7, #1 + 8018a88: 4681 mov r9, r0 + 8018a8a: 468a mov sl, r1 + 8018a8c: 9b00 ldr r3, [sp, #0] + 8018a8e: 429f cmp r7, r3 + 8018a90: dc02 bgt.n 8018a98 <__kernel_rem_pio2+0x4c8> + 8018a92: 9b06 ldr r3, [sp, #24] + 8018a94: 429f cmp r7, r3 + 8018a96: ddea ble.n 8018a6e <__kernel_rem_pio2+0x49e> + 8018a98: 9a06 ldr r2, [sp, #24] + 8018a9a: ab48 add r3, sp, #288 ; 0x120 + 8018a9c: eb03 06c2 add.w r6, r3, r2, lsl #3 + 8018aa0: e9c6 9a00 strd r9, sl, [r6] + 8018aa4: 3c01 subs r4, #1 + 8018aa6: e6fa b.n 801889e <__kernel_rem_pio2+0x2ce> + 8018aa8: 9ba4 ldr r3, [sp, #656] ; 0x290 + 8018aaa: 2b02 cmp r3, #2 + 8018aac: dc0b bgt.n 8018ac6 <__kernel_rem_pio2+0x4f6> + 8018aae: 2b00 cmp r3, #0 + 8018ab0: dc39 bgt.n 8018b26 <__kernel_rem_pio2+0x556> + 8018ab2: d05d beq.n 8018b70 <__kernel_rem_pio2+0x5a0> + 8018ab4: 9b02 ldr r3, [sp, #8] + 8018ab6: f003 0007 and.w r0, r3, #7 + 8018aba: f50d 7d19 add.w sp, sp, #612 ; 0x264 + 8018abe: ecbd 8b02 vpop {d8} + 8018ac2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8018ac6: 9ba4 ldr r3, [sp, #656] ; 0x290 + 8018ac8: 2b03 cmp r3, #3 + 8018aca: d1f3 bne.n 8018ab4 <__kernel_rem_pio2+0x4e4> + 8018acc: 9b05 ldr r3, [sp, #20] + 8018ace: 9500 str r5, [sp, #0] + 8018ad0: f503 7318 add.w r3, r3, #608 ; 0x260 + 8018ad4: eb0d 0403 add.w r4, sp, r3 + 8018ad8: f5a4 74a4 sub.w r4, r4, #328 ; 0x148 + 8018adc: 46a2 mov sl, r4 + 8018ade: 9b00 ldr r3, [sp, #0] + 8018ae0: 2b00 cmp r3, #0 + 8018ae2: f1aa 0a08 sub.w sl, sl, #8 + 8018ae6: dc69 bgt.n 8018bbc <__kernel_rem_pio2+0x5ec> + 8018ae8: 46aa mov sl, r5 + 8018aea: f1ba 0f01 cmp.w sl, #1 + 8018aee: f1a4 0408 sub.w r4, r4, #8 + 8018af2: f300 8083 bgt.w 8018bfc <__kernel_rem_pio2+0x62c> + 8018af6: 9c05 ldr r4, [sp, #20] + 8018af8: ab48 add r3, sp, #288 ; 0x120 + 8018afa: 441c add r4, r3 + 8018afc: 2000 movs r0, #0 + 8018afe: 2100 movs r1, #0 + 8018b00: 2d01 cmp r5, #1 + 8018b02: f300 809a bgt.w 8018c3a <__kernel_rem_pio2+0x66a> + 8018b06: e9dd 7848 ldrd r7, r8, [sp, #288] ; 0x120 + 8018b0a: e9dd 564a ldrd r5, r6, [sp, #296] ; 0x128 + 8018b0e: f1bb 0f00 cmp.w fp, #0 + 8018b12: f040 8098 bne.w 8018c46 <__kernel_rem_pio2+0x676> + 8018b16: 9b04 ldr r3, [sp, #16] + 8018b18: e9c3 7800 strd r7, r8, [r3] + 8018b1c: e9c3 5602 strd r5, r6, [r3, #8] + 8018b20: e9c3 0104 strd r0, r1, [r3, #16] + 8018b24: e7c6 b.n 8018ab4 <__kernel_rem_pio2+0x4e4> + 8018b26: 9e05 ldr r6, [sp, #20] + 8018b28: ab48 add r3, sp, #288 ; 0x120 + 8018b2a: 441e add r6, r3 + 8018b2c: 462c mov r4, r5 + 8018b2e: 2000 movs r0, #0 + 8018b30: 2100 movs r1, #0 + 8018b32: 2c00 cmp r4, #0 + 8018b34: da33 bge.n 8018b9e <__kernel_rem_pio2+0x5ce> + 8018b36: f1bb 0f00 cmp.w fp, #0 + 8018b3a: d036 beq.n 8018baa <__kernel_rem_pio2+0x5da> + 8018b3c: 4602 mov r2, r0 + 8018b3e: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8018b42: 9c04 ldr r4, [sp, #16] + 8018b44: e9c4 2300 strd r2, r3, [r4] + 8018b48: 4602 mov r2, r0 + 8018b4a: 460b mov r3, r1 + 8018b4c: e9dd 0148 ldrd r0, r1, [sp, #288] ; 0x120 + 8018b50: f7e7 fb9a bl 8000288 <__aeabi_dsub> + 8018b54: ae4a add r6, sp, #296 ; 0x128 + 8018b56: 2401 movs r4, #1 + 8018b58: 42a5 cmp r5, r4 + 8018b5a: da29 bge.n 8018bb0 <__kernel_rem_pio2+0x5e0> + 8018b5c: f1bb 0f00 cmp.w fp, #0 + 8018b60: d002 beq.n 8018b68 <__kernel_rem_pio2+0x598> + 8018b62: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8018b66: 4619 mov r1, r3 + 8018b68: 9b04 ldr r3, [sp, #16] + 8018b6a: e9c3 0102 strd r0, r1, [r3, #8] + 8018b6e: e7a1 b.n 8018ab4 <__kernel_rem_pio2+0x4e4> + 8018b70: 9c05 ldr r4, [sp, #20] + 8018b72: ab48 add r3, sp, #288 ; 0x120 + 8018b74: 441c add r4, r3 + 8018b76: 2000 movs r0, #0 + 8018b78: 2100 movs r1, #0 + 8018b7a: 2d00 cmp r5, #0 + 8018b7c: da09 bge.n 8018b92 <__kernel_rem_pio2+0x5c2> + 8018b7e: f1bb 0f00 cmp.w fp, #0 + 8018b82: d002 beq.n 8018b8a <__kernel_rem_pio2+0x5ba> + 8018b84: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8018b88: 4619 mov r1, r3 + 8018b8a: 9b04 ldr r3, [sp, #16] + 8018b8c: e9c3 0100 strd r0, r1, [r3] + 8018b90: e790 b.n 8018ab4 <__kernel_rem_pio2+0x4e4> + 8018b92: e974 2302 ldrd r2, r3, [r4, #-8]! + 8018b96: f7e7 fb79 bl 800028c <__adddf3> + 8018b9a: 3d01 subs r5, #1 + 8018b9c: e7ed b.n 8018b7a <__kernel_rem_pio2+0x5aa> + 8018b9e: e976 2302 ldrd r2, r3, [r6, #-8]! + 8018ba2: f7e7 fb73 bl 800028c <__adddf3> + 8018ba6: 3c01 subs r4, #1 + 8018ba8: e7c3 b.n 8018b32 <__kernel_rem_pio2+0x562> + 8018baa: 4602 mov r2, r0 + 8018bac: 460b mov r3, r1 + 8018bae: e7c8 b.n 8018b42 <__kernel_rem_pio2+0x572> + 8018bb0: e8f6 2302 ldrd r2, r3, [r6], #8 + 8018bb4: f7e7 fb6a bl 800028c <__adddf3> + 8018bb8: 3401 adds r4, #1 + 8018bba: e7cd b.n 8018b58 <__kernel_rem_pio2+0x588> + 8018bbc: e9da 8900 ldrd r8, r9, [sl] + 8018bc0: e9da 6702 ldrd r6, r7, [sl, #8] + 8018bc4: 9b00 ldr r3, [sp, #0] + 8018bc6: 3b01 subs r3, #1 + 8018bc8: 9300 str r3, [sp, #0] + 8018bca: 4632 mov r2, r6 + 8018bcc: 463b mov r3, r7 + 8018bce: 4640 mov r0, r8 + 8018bd0: 4649 mov r1, r9 + 8018bd2: f7e7 fb5b bl 800028c <__adddf3> + 8018bd6: e9cd 0106 strd r0, r1, [sp, #24] + 8018bda: 4602 mov r2, r0 + 8018bdc: 460b mov r3, r1 + 8018bde: 4640 mov r0, r8 + 8018be0: 4649 mov r1, r9 + 8018be2: f7e7 fb51 bl 8000288 <__aeabi_dsub> + 8018be6: 4632 mov r2, r6 + 8018be8: 463b mov r3, r7 + 8018bea: f7e7 fb4f bl 800028c <__adddf3> + 8018bee: ed9d 7b06 vldr d7, [sp, #24] + 8018bf2: e9ca 0102 strd r0, r1, [sl, #8] + 8018bf6: ed8a 7b00 vstr d7, [sl] + 8018bfa: e770 b.n 8018ade <__kernel_rem_pio2+0x50e> + 8018bfc: e9d4 8900 ldrd r8, r9, [r4] + 8018c00: e9d4 6702 ldrd r6, r7, [r4, #8] + 8018c04: 4640 mov r0, r8 + 8018c06: 4632 mov r2, r6 + 8018c08: 463b mov r3, r7 + 8018c0a: 4649 mov r1, r9 + 8018c0c: f7e7 fb3e bl 800028c <__adddf3> + 8018c10: e9cd 0100 strd r0, r1, [sp] + 8018c14: 4602 mov r2, r0 + 8018c16: 460b mov r3, r1 + 8018c18: 4640 mov r0, r8 + 8018c1a: 4649 mov r1, r9 + 8018c1c: f7e7 fb34 bl 8000288 <__aeabi_dsub> + 8018c20: 4632 mov r2, r6 + 8018c22: 463b mov r3, r7 + 8018c24: f7e7 fb32 bl 800028c <__adddf3> + 8018c28: ed9d 7b00 vldr d7, [sp] + 8018c2c: e9c4 0102 strd r0, r1, [r4, #8] + 8018c30: ed84 7b00 vstr d7, [r4] + 8018c34: f10a 3aff add.w sl, sl, #4294967295 + 8018c38: e757 b.n 8018aea <__kernel_rem_pio2+0x51a> + 8018c3a: e974 2302 ldrd r2, r3, [r4, #-8]! + 8018c3e: f7e7 fb25 bl 800028c <__adddf3> + 8018c42: 3d01 subs r5, #1 + 8018c44: e75c b.n 8018b00 <__kernel_rem_pio2+0x530> + 8018c46: 9b04 ldr r3, [sp, #16] + 8018c48: 9a04 ldr r2, [sp, #16] + 8018c4a: 601f str r7, [r3, #0] + 8018c4c: f108 4400 add.w r4, r8, #2147483648 ; 0x80000000 + 8018c50: 605c str r4, [r3, #4] + 8018c52: 609d str r5, [r3, #8] + 8018c54: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 + 8018c58: 60d3 str r3, [r2, #12] + 8018c5a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8018c5e: 6110 str r0, [r2, #16] + 8018c60: 6153 str r3, [r2, #20] + 8018c62: e727 b.n 8018ab4 <__kernel_rem_pio2+0x4e4> + 8018c64: 41700000 .word 0x41700000 + 8018c68: 3e700000 .word 0x3e700000 + 8018c6c: 00000000 .word 0x00000000 + +08018c70 : + 8018c70: b570 push {r4, r5, r6, lr} + 8018c72: ec55 4b10 vmov r4, r5, d0 + 8018c76: f3c5 510a ubfx r1, r5, #20, #11 + 8018c7a: 4606 mov r6, r0 + 8018c7c: 462b mov r3, r5 + 8018c7e: b999 cbnz r1, 8018ca8 + 8018c80: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 8018c84: 4323 orrs r3, r4 + 8018c86: d03f beq.n 8018d08 + 8018c88: 4b35 ldr r3, [pc, #212] ; (8018d60 ) + 8018c8a: 4629 mov r1, r5 + 8018c8c: ee10 0a10 vmov r0, s0 + 8018c90: 2200 movs r2, #0 + 8018c92: f7e7 fcb1 bl 80005f8 <__aeabi_dmul> + 8018c96: 4b33 ldr r3, [pc, #204] ; (8018d64 ) + 8018c98: 429e cmp r6, r3 + 8018c9a: 4604 mov r4, r0 + 8018c9c: 460d mov r5, r1 + 8018c9e: da10 bge.n 8018cc2 + 8018ca0: a327 add r3, pc, #156 ; (adr r3, 8018d40 ) + 8018ca2: e9d3 2300 ldrd r2, r3, [r3] + 8018ca6: e01f b.n 8018ce8 + 8018ca8: f240 72ff movw r2, #2047 ; 0x7ff + 8018cac: 4291 cmp r1, r2 + 8018cae: d10c bne.n 8018cca + 8018cb0: ee10 2a10 vmov r2, s0 + 8018cb4: 4620 mov r0, r4 + 8018cb6: 4629 mov r1, r5 + 8018cb8: f7e7 fae8 bl 800028c <__adddf3> + 8018cbc: 4604 mov r4, r0 + 8018cbe: 460d mov r5, r1 + 8018cc0: e022 b.n 8018d08 + 8018cc2: 460b mov r3, r1 + 8018cc4: f3c1 510a ubfx r1, r1, #20, #11 + 8018cc8: 3936 subs r1, #54 ; 0x36 + 8018cca: f24c 3250 movw r2, #50000 ; 0xc350 + 8018cce: 4296 cmp r6, r2 + 8018cd0: dd0d ble.n 8018cee + 8018cd2: 2d00 cmp r5, #0 + 8018cd4: a11c add r1, pc, #112 ; (adr r1, 8018d48 ) + 8018cd6: e9d1 0100 ldrd r0, r1, [r1] + 8018cda: da02 bge.n 8018ce2 + 8018cdc: a11c add r1, pc, #112 ; (adr r1, 8018d50 ) + 8018cde: e9d1 0100 ldrd r0, r1, [r1] + 8018ce2: a319 add r3, pc, #100 ; (adr r3, 8018d48 ) + 8018ce4: e9d3 2300 ldrd r2, r3, [r3] + 8018ce8: f7e7 fc86 bl 80005f8 <__aeabi_dmul> + 8018cec: e7e6 b.n 8018cbc + 8018cee: 1872 adds r2, r6, r1 + 8018cf0: f240 71fe movw r1, #2046 ; 0x7fe + 8018cf4: 428a cmp r2, r1 + 8018cf6: dcec bgt.n 8018cd2 + 8018cf8: 2a00 cmp r2, #0 + 8018cfa: dd08 ble.n 8018d0e + 8018cfc: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 8018d00: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 8018d04: ea43 5502 orr.w r5, r3, r2, lsl #20 + 8018d08: ec45 4b10 vmov d0, r4, r5 + 8018d0c: bd70 pop {r4, r5, r6, pc} + 8018d0e: f112 0f35 cmn.w r2, #53 ; 0x35 + 8018d12: da08 bge.n 8018d26 + 8018d14: 2d00 cmp r5, #0 + 8018d16: a10a add r1, pc, #40 ; (adr r1, 8018d40 ) + 8018d18: e9d1 0100 ldrd r0, r1, [r1] + 8018d1c: dac0 bge.n 8018ca0 + 8018d1e: a10e add r1, pc, #56 ; (adr r1, 8018d58 ) + 8018d20: e9d1 0100 ldrd r0, r1, [r1] + 8018d24: e7bc b.n 8018ca0 + 8018d26: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 8018d2a: 3236 adds r2, #54 ; 0x36 + 8018d2c: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 8018d30: ea43 5102 orr.w r1, r3, r2, lsl #20 + 8018d34: 4620 mov r0, r4 + 8018d36: 4b0c ldr r3, [pc, #48] ; (8018d68 ) + 8018d38: 2200 movs r2, #0 + 8018d3a: e7d5 b.n 8018ce8 + 8018d3c: f3af 8000 nop.w + 8018d40: c2f8f359 .word 0xc2f8f359 + 8018d44: 01a56e1f .word 0x01a56e1f + 8018d48: 8800759c .word 0x8800759c + 8018d4c: 7e37e43c .word 0x7e37e43c + 8018d50: 8800759c .word 0x8800759c + 8018d54: fe37e43c .word 0xfe37e43c + 8018d58: c2f8f359 .word 0xc2f8f359 + 8018d5c: 81a56e1f .word 0x81a56e1f + 8018d60: 43500000 .word 0x43500000 + 8018d64: ffff3cb0 .word 0xffff3cb0 + 8018d68: 3c900000 .word 0x3c900000 + +08018d6c <_init>: + 8018d6c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8018d6e: bf00 nop + 8018d70: bcf8 pop {r3, r4, r5, r6, r7} + 8018d72: bc08 pop {r3} + 8018d74: 469e mov lr, r3 + 8018d76: 4770 bx lr + +08018d78 <_fini>: + 8018d78: b5f8 push {r3, r4, r5, r6, r7, lr} + 8018d7a: bf00 nop + 8018d7c: bcf8 pop {r3, r4, r5, r6, r7} + 8018d7e: bc08 pop {r3} + 8018d80: 469e mov lr, r3 + 8018d82: 4770 bx lr diff --git a/Software/stm32project/Debug/projet vf.map b/Software/stm32project/Debug/projet vf.map index 7ab4769..192c3d9 100644 --- a/Software/stm32project/Debug/projet vf.map +++ b/Software/stm32project/Debug/projet vf.map @@ -1,5 +1,7 @@ Archive member included to satisfy reference by file (symbol) +C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) + ./Core/Src/spi.o (atoi) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (exit) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o) @@ -11,7 +13,7 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtod.o) ./Core/Src/nmea_parse.o (strtof) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtol.o) - ./Core/Src/nmea_parse.o (strtol) + C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) (_strtol_r) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-ctype_.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtol.o) (_ctype_) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_float.o) @@ -25,7 +27,7 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) (_fwalk_sglue) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o) - ./Core/Src/statemachine.o (snprintf) + ./Core/Src/main.o (snprintf) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sprintf.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfscanf_float.o) (sprintf) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o) @@ -71,7 +73,7 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o) (memchr) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o) - ./Core/Src/main.o (memcpy) + ./Core/Src/ssd1306.o (memcpy) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o) ./Core/Src/nmea_parse.o (strlen) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libm_a-s_nan.o) @@ -173,21 +175,21 @@ C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.external C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-sf_floor.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-kf_rem_pio2.o) (floorf) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_muldf3.o) - ./Core/Src/main.o (__aeabi_dmul) + ./Core/Src/adc.o (__aeabi_dmul) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_addsubdf3.o) - ./Core/Src/main.o (__aeabi_dsub) + ./Core/Src/adc.o (__aeabi_dsub) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_muldivdf3.o) - ./Core/Src/main.o (__aeabi_ddiv) + ./Core/Src/adc.o (__aeabi_ddiv) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_cmpdf2.o) ./Core/Src/nmea_parse.o (__aeabi_dcmpeq) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_unorddf2.o) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtod.o) (__aeabi_dcmpun) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_fixdfsi.o) - ./Core/Src/ssd1306.o (__aeabi_d2iz) + ./Core/Src/spi.o (__aeabi_d2iz) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_fixunsdfsi.o) ./Core/Src/statemachine.o (__aeabi_d2uiz) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_truncdfsf2.o) - ./Core/Src/main.o (__aeabi_d2f) + ./Core/Src/adc.o (__aeabi_d2f) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o) ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o (__aeabi_uldivmod) C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_fixdfdi.o) @@ -221,6 +223,348 @@ Discarded input sections .debug_str 0x0000000000000000 0xe2 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o .ARM.attributes 0x0000000000000000 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o + .group 0x0000000000000000 0xc ./Core/Src/adc.o + .group 0x0000000000000000 0xc ./Core/Src/adc.o + .group 0x0000000000000000 0xc ./Core/Src/adc.o + .group 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.bss.t1 0x0000000000000000 0x4 ./Core/Src/statemachine.o + .bss.t2 0x0000000000000000 0x4 ./Core/Src/statemachine.o + .bss.t3 0x0000000000000000 0x4 ./Core/Src/statemachine.o + .bss.moy 0x0000000000000000 0x4 ./Core/Src/statemachine.o + .bss.framerate + 0x0000000000000000 0x4 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/statemachine.o - .debug_macro 0x0000000000000000 0x1b9 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/statemachine.o @@ -743,12 +1298,13 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x122 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x356 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x2fe ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0xa98 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x12d ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x5cf ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x44 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x220 ./Core/Src/statemachine.o - .debug_macro 0x0000000000000000 0x10 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x61 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x2a ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x43 ./Core/Src/statemachine.o @@ -772,10 +1328,16 @@ Discarded input sections .debug_macro 0x0000000000000000 0x16 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x16 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x29 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x10 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x16 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x147 ./Core/Src/statemachine.o .debug_macro 0x0000000000000000 0x20f ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x52 ./Core/Src/statemachine.o + .debug_macro 0x0000000000000000 0x58 ./Core/Src/statemachine.o + .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_hal_msp.o @@ -824,14 +1386,8 @@ Discarded input sections .text 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_hal_msp.o .data 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_hal_msp.o .bss 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_hal_msp.o - .text.HAL_ADC_MspDeInit - 0x0000000000000000 0x48 ./Core/Src/stm32l4xx_hal_msp.o - .text.HAL_I2C_MspDeInit - 0x0000000000000000 0x44 ./Core/Src/stm32l4xx_hal_msp.o - .text.HAL_TIM_Base_MspDeInit - 0x0000000000000000 0x4c ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/stm32l4xx_hal_msp.o - .debug_macro 0x0000000000000000 0x1b9 ./Core/Src/stm32l4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l4xx_hal_msp.o @@ -869,18 +1425,13 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x122 ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x356 ./Core/Src/stm32l4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2fe ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0xa98 ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x12d ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x5cf ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x44 ./Core/Src/stm32l4xx_hal_msp.o .debug_macro 0x0000000000000000 0x220 ./Core/Src/stm32l4xx_hal_msp.o - .debug_macro 0x0000000000000000 0x10 ./Core/Src/stm32l4xx_hal_msp.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o - .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o .group 0x0000000000000000 0xc ./Core/Src/stm32l4xx_it.o @@ -930,8 +1481,9 @@ Discarded input sections .text 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_it.o .data 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_it.o .bss 0x0000000000000000 0x0 ./Core/Src/stm32l4xx_it.o + .bss.cont 0x0000000000000000 0x4 ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x1b9 ./Core/Src/stm32l4xx_it.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32l4xx_it.o @@ -969,19 +1521,13 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x122 ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x356 ./Core/Src/stm32l4xx_it.o + .debug_macro 0x0000000000000000 0x2fe ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0xa98 ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x12d ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x5cf ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x44 ./Core/Src/stm32l4xx_it.o .debug_macro 0x0000000000000000 0x220 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x10 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x61 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x2a ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x43 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x34 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x10 ./Core/Src/stm32l4xx_it.o - .debug_macro 0x0000000000000000 0x16 ./Core/Src/stm32l4xx_it.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/stm32l4xx_it.o .group 0x0000000000000000 0xc ./Core/Src/syscalls.o .group 0x0000000000000000 0xc ./Core/Src/syscalls.o .group 0x0000000000000000 0xc ./Core/Src/syscalls.o @@ -1165,6 +1711,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/system_stm32l4xx.o .group 0x0000000000000000 0xc ./Core/Src/system_stm32l4xx.o .group 0x0000000000000000 0xc ./Core/Src/system_stm32l4xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32l4xx.o .text 0x0000000000000000 0x0 ./Core/Src/system_stm32l4xx.o .data 0x0000000000000000 0x0 ./Core/Src/system_stm32l4xx.o .bss 0x0000000000000000 0x0 ./Core/Src/system_stm32l4xx.o @@ -1186,7 +1733,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x11f ./Core/Src/system_stm32l4xx.o .debug_macro 0x0000000000000000 0x147a6 ./Core/Src/system_stm32l4xx.o .debug_macro 0x0000000000000000 0x6d ./Core/Src/system_stm32l4xx.o - .debug_macro 0x0000000000000000 0x1b9 ./Core/Src/system_stm32l4xx.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/system_stm32l4xx.o .debug_macro 0x0000000000000000 0x38e6 ./Core/Src/system_stm32l4xx.o .debug_macro 0x0000000000000000 0x174 ./Core/Src/system_stm32l4xx.o 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+ .text 0x0000000000000000 0x0 ./Core/Src/tim.o + .data 0x0000000000000000 0x0 ./Core/Src/tim.o + .bss 0x0000000000000000 0x0 ./Core/Src/tim.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0x30 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0xfb ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x1011 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.debug_macro 0x0000000000000000 0xd6 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x61 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0xab ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x22d ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x122 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x356 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x2fe ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0xa98 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x12d ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x5cf ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x220 ./Core/Src/tim.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/tim.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o 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0x0000000000000000 0xc ./Core/Src/usart.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o + .group 0x0000000000000000 0xc ./Core/Src/usart.o + .text 0x0000000000000000 0x0 ./Core/Src/usart.o + .data 0x0000000000000000 0x0 ./Core/Src/usart.o + .bss 0x0000000000000000 0x0 ./Core/Src/usart.o + .text.HAL_UART_MspDeInit + 0x0000000000000000 0x70 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1bf ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x2e ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x28 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x8e ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x51 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x103 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x6a ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1df ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x22 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xfb ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1011 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x11f ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x147a6 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x6d ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x38e6 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x174 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x5c ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x11ca ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x53c ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1b9 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x122 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x26b ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x23d ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xde6 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x61d ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x241 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x241 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x375 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xd6 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x22c ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x61 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xa5 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xab ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x22d ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x122 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x356 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x2fe ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0xa98 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x12d ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x5cf ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x44 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x220 ./Core/Src/usart.o + .debug_macro 0x0000000000000000 0x1c ./Core/Src/usart.o .text 0x0000000000000000 0x14 ./Core/Startup/startup_stm32l432kcux.o .data 0x0000000000000000 0x0 ./Core/Startup/startup_stm32l432kcux.o .bss 0x0000000000000000 0x0 ./Core/Startup/startup_stm32l432kcux.o @@ -1261,6 +2003,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o @@ -1315,7 +2058,7 @@ Discarded input sections .text.HAL_SYSCFG_DisableIOAnalogSwitchBooster 0x0000000000000000 0x20 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o @@ -1353,6 +2096,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o @@ -1402,6 +2146,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o @@ -1470,7 +2215,7 @@ Discarded input sections .text.ADC_Disable 0x0000000000000000 0xbe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o @@ -1508,6 +2253,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o @@ -1557,6 +2303,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o @@ -1637,7 +2384,7 @@ Discarded input sections .text.HAL_ADCEx_EnterADCDeepPowerDownMode 0x0000000000000000 0x36 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o @@ -1675,6 +2422,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o @@ -1724,9 +2472,12 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x0000000000000000 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_GetPendingIRQ 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_SetPendingIRQ @@ -1741,6 +2492,8 @@ Discarded input sections 0x0000000000000000 0x6e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_SystemReset 0x0000000000000000 0x2c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.HAL_NVIC_SystemReset 0x0000000000000000 0x8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.HAL_NVIC_GetPriorityGrouping @@ -1768,7 +2521,7 @@ Discarded input sections .text.HAL_MPU_ConfigRegion 0x0000000000000000 0x88 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o @@ -1806,6 +2559,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o @@ -1855,9 +2609,12 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x0000000000000000 0x124 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .text.HAL_DMA_Start 0x0000000000000000 0x86 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .text.HAL_DMA_PollForTransfer @@ -1869,7 +2626,7 @@ Discarded input sections .text.HAL_DMA_GetState 0x0000000000000000 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o @@ -1907,6 +2664,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o @@ -1956,6 +2714,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o @@ -1963,9 +2722,9 @@ Discarded input sections .debug_abbrev 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_aranges 0x0000000000000000 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o - .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x235 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o @@ -2003,13 +2762,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o - .debug_line 0x0000000000000000 0x807 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o - .debug_str 0x0000000000000000 0xd55ad ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .debug_line 0x0000000000000000 0x838 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o + .debug_str 0x0000000000000000 0xd719e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o .ARM.attributes 0x0000000000000000 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o @@ -2057,6 +2817,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o @@ -2084,9 +2845,9 @@ Discarded input sections 0x0000000000000000 0x60 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_rnglists 0x0000000000000000 0x46 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o - .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x241 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o @@ -2124,13 +2885,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o - .debug_line 0x0000000000000000 0xb7e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o - .debug_str 0x0000000000000000 0xd588c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .debug_line 0x0000000000000000 0xbaf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o + .debug_str 0x0000000000000000 0xd747d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .debug_frame 0x0000000000000000 0x174 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.o .ARM.attributes @@ -2179,6 +2941,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o @@ -2217,9 +2980,9 @@ Discarded input sections 0x0000000000000000 0x88 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_rnglists 0x0000000000000000 0x65 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o - .debug_macro 0x0000000000000000 0x226 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x23b ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o @@ -2257,13 +3020,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o - .debug_line 0x0000000000000000 0xbb4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o - .debug_str 0x0000000000000000 0xd5a55 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .debug_line 0x0000000000000000 0xbe5 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o + .debug_str 0x0000000000000000 0xd7646 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .debug_frame 0x0000000000000000 0x204 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o .ARM.attributes @@ -2312,6 +3076,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o @@ -2351,9 +3116,9 @@ Discarded input sections 0x0000000000000000 0x90 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_rnglists 0x0000000000000000 0x6f ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x235 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o @@ -2391,13 +3156,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o - .debug_line 0x0000000000000000 0xd0a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o - .debug_str 0x0000000000000000 0xd5a75 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0xd3b ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0xd7666 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .debug_frame 0x0000000000000000 0x248 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o .ARM.attributes @@ -2446,6 +3212,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o @@ -2456,9 +3223,9 @@ Discarded input sections 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_rnglists 0x0000000000000000 0x19 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x235 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o @@ -2496,13 +3263,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o - .debug_line 0x0000000000000000 0x833 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o - .debug_str 0x0000000000000000 0xd5695 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .debug_line 0x0000000000000000 0x864 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o + .debug_str 0x0000000000000000 0xd7286 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .debug_frame 0x0000000000000000 0x50 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o .ARM.attributes @@ -2551,9 +3319,12 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x0000000000000000 0x194 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .text.HAL_GPIO_ReadPin 0x0000000000000000 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .text.HAL_GPIO_TogglePin @@ -2563,7 +3334,7 @@ Discarded input sections .text.HAL_GPIO_EXTI_Callback 0x0000000000000000 0x16 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o @@ -2601,6 +3372,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o @@ -2650,6 +3422,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o @@ -2798,7 +3571,7 @@ Discarded input sections .text.I2C_ConvertOtherXferOptions 0x0000000000000000 0x36 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o @@ -2836,6 +3609,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o @@ -2885,6 +3659,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o @@ -2895,7 +3670,7 @@ Discarded input sections .text.HAL_I2CEx_DisableFastModePlus 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o @@ -2933,6 +3708,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o @@ -2982,6 +3758,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o @@ -3019,8 +3796,6 @@ Discarded input sections 0x0000000000000000 0x3a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .text.HAL_PCD_DevDisconnect 0x0000000000000000 0x3a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o - .text.HAL_PCD_EP_GetRxCount - 0x0000000000000000 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .text.HAL_PCD_EP_Abort 0x0000000000000000 0x5e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .text.HAL_PCD_EP_Flush @@ -3032,7 +3807,7 @@ Discarded input sections .text.HAL_PCD_GetState 0x0000000000000000 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o @@ -3070,6 +3845,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o @@ -3119,6 +3895,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o @@ -3135,7 +3912,7 @@ Discarded input sections .text.HAL_PCDEx_BCD_Callback 0x0000000000000000 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o @@ -3173,6 +3950,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o @@ -3222,6 +4000,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o @@ -3263,9 +4042,9 @@ Discarded input sections 0x0000000000000000 0x98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_rnglists 0x0000000000000000 0x6e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x238 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x24d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o @@ -3303,13 +4082,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o - .debug_line 0x0000000000000000 0x9db ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o - .debug_str 0x0000000000000000 0xd5b20 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .debug_line 0x0000000000000000 0xa0c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o + .debug_str 0x0000000000000000 0xd7711 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .debug_frame 0x0000000000000000 0x230 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o .ARM.attributes @@ -3358,6 +4138,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o @@ -3424,7 +4205,7 @@ Discarded input sections .text.HAL_PWREx_PVM4Callback 0x0000000000000000 0xe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o @@ -3462,6 +4243,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o @@ -3511,6 +4293,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o @@ -3531,7 +4314,7 @@ Discarded input sections .text.HAL_RCC_GetResetSource 0x0000000000000000 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o @@ -3569,6 +4352,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o @@ -3618,6 +4402,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o @@ -3672,7 +4457,7 @@ Discarded input sections .text.RCCEx_GetSAIxPeriphCLKFreq 0x0000000000000000 0x178 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o @@ -3710,11 +4495,310 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o + .group 0x0000000000000000 0xc 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./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x241 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x241 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x375 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xd6 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x61 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa5 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xab ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_line 0x0000000000000000 0x87b ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_str 0x0000000000000000 0xd7612 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .comment 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .debug_frame 0x0000000000000000 0x38 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .ARM.attributes + 0x0000000000000000 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o @@ -3874,6 +4958,8 @@ Discarded input sections 0x0000000000000000 0x2d8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_Encoder_Stop_DMA 0x0000000000000000 0x1b2 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_IRQHandler + 0x0000000000000000 0x204 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_OC_ConfigChannel 0x0000000000000000 0xf4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_IC_ConfigChannel @@ -3906,12 +4992,22 @@ Discarded input sections 0x0000000000000000 0x84 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_ReadCapturedValue 0x0000000000000000 0x88 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_PeriodElapsedHalfCpltCallback 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_OC_DelayElapsedCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_IC_CaptureCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_IC_CaptureHalfCpltCallback 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .text.HAL_TIM_TriggerCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_TriggerHalfCpltCallback 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .text.HAL_TIM_ErrorCallback @@ -3977,7 +5073,7 @@ Discarded input sections .text.TIM_CCxChannelCmd 0x0000000000000000 0x4a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o @@ -4015,6 +5111,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o @@ -4064,6 +5161,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o @@ -4133,8 +5231,14 @@ Discarded input sections 0x0000000000000000 0x88 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .text.HAL_TIMEx_GroupChannel5 0x0000000000000000 0x66 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .text.HAL_TIMEx_CommutCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .text.HAL_TIMEx_CommutHalfCpltCallback 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .text.HAL_TIMEx_BreakCallback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .text.HAL_TIMEx_Break2Callback + 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .text.HAL_TIMEx_HallSensor_GetState 0x0000000000000000 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .text.HAL_TIMEx_GetChannelNState @@ -4150,7 +5254,7 @@ Discarded input sections .text.TIM_CCxNChannelCmd 0x0000000000000000 0x4a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o @@ -4188,6 +5292,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o @@ -4237,6 +5342,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o @@ -4246,6 +5352,8 @@ Discarded input sections 0x0000000000000000 0xdc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_MultiProcessor_Init 0x0000000000000000 0xd4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .text.HAL_UART_DeInit + 0x0000000000000000 0x7a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_UART_MspInit 0x0000000000000000 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_UART_MspDeInit @@ -4254,6 +5362,8 @@ Discarded input sections 0x0000000000000000 0x114 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_UART_Receive 0x0000000000000000 0x192 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .text.HAL_UART_Transmit_IT + 0x0000000000000000 0xbc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_UART_Receive_IT 0x0000000000000000 0x98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.HAL_UART_Transmit_DMA @@ -4320,12 +5430,16 @@ Discarded input sections 0x0000000000000000 0x2a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.UART_DMARxOnlyAbortCallback 0x0000000000000000 0x4e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .text.UART_TxISR_8BIT + 0x0000000000000000 0xb8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .text.UART_TxISR_16BIT + 0x0000000000000000 0xc0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.UART_RxISR_8BIT 0x0000000000000000 0x1bc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .text.UART_RxISR_16BIT 0x0000000000000000 0x1bc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o @@ -4363,6 +5477,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o @@ -4412,6 +5527,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o @@ -4440,7 +5556,7 @@ Discarded input sections .text.UARTEx_Wakeup_AddressConfig 0x0000000000000000 0x46 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o @@ -4478,6 +5594,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o @@ -4527,6 +5644,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o + .group 0x0000000000000000 0xc ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .text 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .data 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .bss 0x0000000000000000 0x0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o @@ -4553,7 +5671,7 @@ Discarded input sections .text.USB_DeActivateRemoteWakeup 0x0000000000000000 0x2a ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o - .debug_macro 0x0000000000000000 0x1b9 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o + .debug_macro 0x0000000000000000 0x1bf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o @@ -4591,161 +5709,158 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x122 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x356 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o + .debug_macro 0x0000000000000000 0x2fe ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0xa98 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x12d ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x5cf ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .debug_macro 0x0000000000000000 0x220 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc 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./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .text 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .data 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .bss 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .text.USBD_HID_SendReport - 0x0000000000000000 0x60 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .text.USBD_HID_GetPollingInterval - 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0xaa8 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./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x43 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x58 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x8e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x177 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x147 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x35 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x6a ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1df ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0xfb ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1011 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x11f ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x147a6 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x6d ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x38e6 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x11ca ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x53c ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .debug_macro 0x0000000000000000 0x122 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./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .text 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .bss 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xaa8 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x5b ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x2a ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x369 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x8e ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x177 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x147 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1bf ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xfb ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1011 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x11f ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x147a6 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x6d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x38e6 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x11ca ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x53c ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x122 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x26b ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x23d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xde6 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x61d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x241 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x241 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x375 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xd6 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x22c ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x61 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xa5 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xab ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x22d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x122 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x356 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x2fe ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0xa98 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x12d ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x5cf ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x220 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .debug_macro 0x0000000000000000 0x20f ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o @@ -4863,7 +5978,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o - .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x0000000000000000 0x1bf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o @@ -4897,13 +6012,15 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x122 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x356 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x0000000000000000 0x2fe ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0xa98 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x12d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x5cf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .debug_macro 0x0000000000000000 0x220 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o - .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o - .debug_macro 0x0000000000000000 0x65 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .debug_macro 0x0000000000000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o @@ -5009,7 +6126,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o - .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_macro 0x0000000000000000 0x1bf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o @@ -5043,13 +6160,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x122 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x356 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_macro 0x0000000000000000 0x2fe ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0xa98 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x12d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x5cf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x220 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o - .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o - .debug_macro 0x0000000000000000 0x65 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + .debug_macro 0x0000000000000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .debug_macro 0x0000000000000000 0x20f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o @@ -5123,11 +6241,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x0000000000000000 0xc ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .text 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .data 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .bss 0x0000000000000000 0x0 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o - .text.USBD_CtlPrepareRx - 0x0000000000000000 0x3a ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .text.USBD_GetRxCount 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0xaa8 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o @@ -5160,7 +6277,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x16 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x20 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o - .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_macro 0x0000000000000000 0x1bf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x2e ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x28 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x103 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o @@ -5194,14 +6311,180 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x122 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x356 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_macro 0x0000000000000000 0x2fe ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0xa98 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x12d ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x5cf ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x220 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o - .debug_macro 0x0000000000000000 0x10 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o - .debug_macro 0x0000000000000000 0x65 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .debug_macro 0x0000000000000000 0x5f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .debug_macro 0x0000000000000000 0x20f ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 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./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text 0x0000000000000000 0x0 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .data 0x0000000000000000 0x0 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .bss 0x0000000000000000 0x0 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_ReadReg2 + 0x0000000000000000 0x4a ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_ReadReg3 + 0x0000000000000000 0x4a ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteReg1 + 0x0000000000000000 0x96 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteReg2 + 0x0000000000000000 0x96 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteReg3 + 0x0000000000000000 0x96 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_EraseBlock + 0x0000000000000000 0x106 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteAddress + 0x0000000000000000 0xae ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteSector + 0x0000000000000000 0xd4 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_WriteBlock + 0x0000000000000000 0xd4 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_ReadAddress + 0x0000000000000000 0x38 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_ReadSector + 0x0000000000000000 0x56 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .text.SPIF_ReadBlock + 0x0000000000000000 0x56 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xaa8 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x5b ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x2a ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x94 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x174 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x43 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x57 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x34 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x8e ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x177 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x369 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x10 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x35 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x20 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x52 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1bf ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x2e ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x28 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x103 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x6a ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1df ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x22 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xfb ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1011 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x11f ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x147a6 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x6d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x38e6 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x56 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x11ca ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x53c ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1b9 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x122 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x26b ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x23d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xde6 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x61d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x241 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x241 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x375 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xd6 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x22c ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x61 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xa5 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xab ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x22d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x122 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x356 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x2fe ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0xa98 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x12d ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x5cf ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x44 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x220 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x1c ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x16 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x29 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .debug_macro 0x0000000000000000 0x58 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usb_device.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usb_device.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usb_device.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usb_device.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usb_device.o @@ -5294,7 +6577,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x11f ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x147a6 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x6d ./USB_DEVICE/App/usb_device.o - .debug_macro 0x0000000000000000 0x1b9 ./USB_DEVICE/App/usb_device.o + .debug_macro 0x0000000000000000 0x1bf ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x38e6 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x174 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x5c ./USB_DEVICE/App/usb_device.o @@ -5317,6 +6600,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x122 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x356 ./USB_DEVICE/App/usb_device.o + .debug_macro 0x0000000000000000 0x2fe ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0xa98 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x12d ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x5cf ./USB_DEVICE/App/usb_device.o @@ -5346,10 +6630,163 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x20 ./USB_DEVICE/App/usb_device.o - .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usb_device.o - .debug_macro 0x0000000000000000 0x65 ./USB_DEVICE/App/usb_device.o - .debug_macro 0x0000000000000000 0x20f ./USB_DEVICE/App/usb_device.o + .debug_macro 0x0000000000000000 0x22 ./USB_DEVICE/App/usb_device.o .debug_macro 0x0000000000000000 0x5f ./USB_DEVICE/App/usb_device.o + .debug_macro 0x0000000000000000 0x20f ./USB_DEVICE/App/usb_device.o + .debug_macro 0x0000000000000000 0x95 ./USB_DEVICE/App/usb_device.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_cdc_if.o + .text 0x0000000000000000 0x0 ./USB_DEVICE/App/usbd_cdc_if.o + .data 0x0000000000000000 0x0 ./USB_DEVICE/App/usbd_cdc_if.o + .bss 0x0000000000000000 0x0 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xaa8 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x22 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x5b ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x2a ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x94 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x43 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x34 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x57 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x97 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x369 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xfd ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x10 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x43 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x34 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x10 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x58 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x8e ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1c ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x177 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x147 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x35 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x29 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x20 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1bf ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x2e ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x28 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x103 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x6a ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1df ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1c ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x22 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xfb ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1011 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x11f ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x147a6 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x6d ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x38e6 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x56 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x11ca ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x53c ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1b9 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x122 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x26b ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x23d ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xde6 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x61d ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x241 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x241 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x375 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xd6 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x22c ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x61 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xa5 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xab ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x22d ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x122 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x356 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x2fe ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0xa98 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x12d ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x5cf ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x44 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x220 ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x1c ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x5f ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x20f ./USB_DEVICE/App/usbd_cdc_if.o + .debug_macro 0x0000000000000000 0x95 ./USB_DEVICE/App/usbd_cdc_if.o + .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_desc.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_desc.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_desc.o .group 0x0000000000000000 0xc ./USB_DEVICE/App/usbd_desc.o @@ -5456,7 +6893,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x20 ./USB_DEVICE/App/usbd_desc.o - .debug_macro 0x0000000000000000 0x1b9 ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x0000000000000000 0x1bf ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x2e ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x28 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x103 ./USB_DEVICE/App/usbd_desc.o @@ -5490,13 +6927,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x122 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x356 ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x0000000000000000 0x2fe ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0xa98 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x12d ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x5cf ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x44 ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x220 ./USB_DEVICE/App/usbd_desc.o - .debug_macro 0x0000000000000000 0x10 ./USB_DEVICE/App/usbd_desc.o - .debug_macro 0x0000000000000000 0x65 ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x0000000000000000 0x1c ./USB_DEVICE/App/usbd_desc.o + .debug_macro 0x0000000000000000 0x5f ./USB_DEVICE/App/usbd_desc.o .debug_macro 0x0000000000000000 0x215 ./USB_DEVICE/App/usbd_desc.o .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o @@ -5570,6 +7008,7 @@ Discarded input sections .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o + .group 0x0000000000000000 0xc ./USB_DEVICE/Target/usbd_conf.o .text 0x0000000000000000 0x0 ./USB_DEVICE/Target/usbd_conf.o .data 0x0000000000000000 0x0 ./USB_DEVICE/Target/usbd_conf.o .bss 0x0000000000000000 0x0 ./USB_DEVICE/Target/usbd_conf.o @@ -5589,8 +7028,6 @@ Discarded input sections 0x0000000000000000 0x64 ./USB_DEVICE/Target/usbd_conf.o .text.USBD_LL_FlushEP 0x0000000000000000 0x6c ./USB_DEVICE/Target/usbd_conf.o - .text.USBD_LL_GetRxDataSize - 0x0000000000000000 0x26 ./USB_DEVICE/Target/usbd_conf.o .text.USBD_LL_Delay 0x0000000000000000 0x16 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0xaa8 ./USB_DEVICE/Target/usbd_conf.o @@ -5609,7 +7046,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x11f ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x147a6 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x6d ./USB_DEVICE/Target/usbd_conf.o - .debug_macro 0x0000000000000000 0x1b9 ./USB_DEVICE/Target/usbd_conf.o + .debug_macro 0x0000000000000000 0x1bf ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x38e6 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x174 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x5c ./USB_DEVICE/Target/usbd_conf.o @@ -5632,6 +7069,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x22d ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x122 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x356 ./USB_DEVICE/Target/usbd_conf.o + .debug_macro 0x0000000000000000 0x2fe ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0xa98 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x12d ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x5cf ./USB_DEVICE/Target/usbd_conf.o @@ -5661,10 +7099,14 @@ Discarded input sections .debug_macro 0x0000000000000000 0x29 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x20 ./USB_DEVICE/Target/usbd_conf.o - .debug_macro 0x0000000000000000 0x16 ./USB_DEVICE/Target/usbd_conf.o - .debug_macro 0x0000000000000000 0x65 ./USB_DEVICE/Target/usbd_conf.o - .debug_macro 0x0000000000000000 0x20f ./USB_DEVICE/Target/usbd_conf.o + .debug_macro 0x0000000000000000 0x22 ./USB_DEVICE/Target/usbd_conf.o .debug_macro 0x0000000000000000 0x5f ./USB_DEVICE/Target/usbd_conf.o + .debug_macro 0x0000000000000000 0x20f ./USB_DEVICE/Target/usbd_conf.o + .debug_macro 0x0000000000000000 0x95 ./USB_DEVICE/Target/usbd_conf.o + .text 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) + .data 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) + .bss 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) + .text._atoi_r 0x0000000000000000 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-atoi.o) .text 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o) .data 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o) .bss 0x0000000000000000 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o) @@ -6135,8 +7577,13 @@ Linker script and memory map LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/adc.o +LOAD ./Core/Src/dma.o +LOAD ./Core/Src/gpio.o +LOAD ./Core/Src/i2c.o LOAD ./Core/Src/main.o LOAD ./Core/Src/nmea_parse.o +LOAD ./Core/Src/spi.o LOAD ./Core/Src/ssd1306.o LOAD ./Core/Src/ssd1306_fonts.o LOAD ./Core/Src/statemachine.o @@ -6145,6 +7592,8 @@ LOAD ./Core/Src/stm32l4xx_it.o LOAD ./Core/Src/syscalls.o LOAD ./Core/Src/sysmem.o LOAD ./Core/Src/system_stm32l4xx.o +LOAD ./Core/Src/tim.o +LOAD ./Core/Src/usart.o LOAD ./Core/Startup/startup_stm32l432kcux.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o @@ -6165,16 +7614,20 @@ LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o +LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o LOAD ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o -LOAD ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o +LOAD ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o LOAD ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o +LOAD ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o LOAD ./USB_DEVICE/App/usb_device.o +LOAD ./USB_DEVICE/App/usbd_cdc_if.o LOAD ./USB_DEVICE/App/usbd_desc.o LOAD ./USB_DEVICE/Target/usbd_conf.o START GROUP @@ -6208,7 +7661,7 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000008000000 g_pfnVectors 0x000000000800018c . = ALIGN (0x4) -.text 0x0000000008000190 0x16744 +.text 0x0000000008000190 0x18bf4 0x0000000008000190 . = ALIGN (0x4) *(.text) .text 0x0000000008000190 0x40 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -6279,1429 +7732,1538 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000008000fec __aeabi_idiv0 0x0000000008000fec __aeabi_ldiv0 *(.text*) - .text.HAL_GPIO_EXTI_Callback - 0x0000000008000ff0 0x44 ./Core/Src/main.o - 0x0000000008000ff0 HAL_GPIO_EXTI_Callback - .text.HAL_UART_RxCpltCallback - 0x0000000008001034 0xdc ./Core/Src/main.o - 0x0000000008001034 HAL_UART_RxCpltCallback - .text.HAL_ADC_ConvCpltCallback - 0x0000000008001110 0x124 ./Core/Src/main.o - 0x0000000008001110 HAL_ADC_ConvCpltCallback - .text.main 0x0000000008001234 0xc0 ./Core/Src/main.o - 0x0000000008001234 main - .text.SystemClock_Config - 0x00000000080012f4 0xa6 ./Core/Src/main.o - 0x00000000080012f4 SystemClock_Config - .text.PeriphCommonClock_Config - 0x000000000800139a 0x5c ./Core/Src/main.o - 0x000000000800139a PeriphCommonClock_Config - *fill* 0x00000000080013f6 0x2 .text.MX_ADC1_Init - 0x00000000080013f8 0xec ./Core/Src/main.o - .text.MX_I2C3_Init - 0x00000000080014e4 0x88 ./Core/Src/main.o - .text.MX_LPUART1_UART_Init - 0x000000000800156c 0x58 ./Core/Src/main.o - .text.MX_TIM2_Init - 0x00000000080015c4 0x9c ./Core/Src/main.o - .text.MX_TIM7_Init - 0x0000000008001660 0x70 ./Core/Src/main.o + 0x0000000008000ff0 0x10c ./Core/Src/adc.o + 0x0000000008000ff0 MX_ADC1_Init + .text.HAL_ADC_MspInit + 0x00000000080010fc 0xec ./Core/Src/adc.o + 0x00000000080010fc HAL_ADC_MspInit + .text.HAL_ADC_ConvCpltCallback + 0x00000000080011e8 0x188 ./Core/Src/adc.o + 0x00000000080011e8 HAL_ADC_ConvCpltCallback .text.MX_DMA_Init - 0x00000000080016d0 0x64 ./Core/Src/main.o + 0x0000000008001370 0x64 ./Core/Src/dma.o + 0x0000000008001370 MX_DMA_Init .text.MX_GPIO_Init - 0x0000000008001734 0xc4 ./Core/Src/main.o + 0x00000000080013d4 0x100 ./Core/Src/gpio.o + 0x00000000080013d4 MX_GPIO_Init + .text.MX_I2C1_Init + 0x00000000080014d4 0x80 ./Core/Src/i2c.o + 0x00000000080014d4 MX_I2C1_Init + .text.MX_I2C3_Init + 0x0000000008001554 0x88 ./Core/Src/i2c.o + 0x0000000008001554 MX_I2C3_Init + .text.HAL_I2C_MspInit + 0x00000000080015dc 0x17c ./Core/Src/i2c.o + 0x00000000080015dc HAL_I2C_MspInit + .text.HAL_GPIO_EXTI_Callback + 0x0000000008001758 0x40 ./Core/Src/main.o + 0x0000000008001758 HAL_GPIO_EXTI_Callback + .text.main 0x0000000008001798 0x158 ./Core/Src/main.o + 0x0000000008001798 main + .text.SystemClock_Config + 0x00000000080018f0 0xa6 ./Core/Src/main.o + 0x00000000080018f0 SystemClock_Config + .text.PeriphCommonClock_Config + 0x0000000008001996 0x5c ./Core/Src/main.o + 0x0000000008001996 PeriphCommonClock_Config .text.Error_Handler - 0x00000000080017f8 0xa ./Core/Src/main.o - 0x00000000080017f8 Error_Handler + 0x00000000080019f2 0xa ./Core/Src/main.o + 0x00000000080019f2 Error_Handler .text.gps_checksum - 0x0000000008001802 0x92 ./Core/Src/nmea_parse.o - 0x0000000008001802 gps_checksum + 0x00000000080019fc 0x92 ./Core/Src/nmea_parse.o + 0x00000000080019fc gps_checksum + *fill* 0x0000000008001a8e 0x2 .text.nmea_GPGGA - 0x0000000008001894 0x3a4 ./Core/Src/nmea_parse.o - 0x0000000008001894 nmea_GPGGA + 0x0000000008001a90 0x3a4 ./Core/Src/nmea_parse.o + 0x0000000008001a90 nmea_GPGGA .text.nmea_GPGSA - 0x0000000008001c38 0x110 ./Core/Src/nmea_parse.o - 0x0000000008001c38 nmea_GPGSA + 0x0000000008001e34 0x110 ./Core/Src/nmea_parse.o + 0x0000000008001e34 nmea_GPGSA + *fill* 0x0000000008001f44 0x4 .text.nmea_GNRMC - 0x0000000008001d48 0xe4 ./Core/Src/nmea_parse.o - 0x0000000008001d48 nmea_GNRMC + 0x0000000008001f48 0xe4 ./Core/Src/nmea_parse.o + 0x0000000008001f48 nmea_GNRMC .text.nmea_parse - 0x0000000008001e2c 0x160 ./Core/Src/nmea_parse.o - 0x0000000008001e2c nmea_parse + 0x000000000800202c 0x160 ./Core/Src/nmea_parse.o + 0x000000000800202c nmea_parse + .text.MX_SPI1_Init + 0x000000000800218c 0x7c ./Core/Src/spi.o + 0x000000000800218c MX_SPI1_Init + .text.HAL_SPI_MspInit + 0x0000000008002208 0xc0 ./Core/Src/spi.o + 0x0000000008002208 HAL_SPI_MspInit + .text.csvframe + 0x00000000080022c8 0xb0 ./Core/Src/spi.o + 0x00000000080022c8 csvframe + .text.storeindex + 0x0000000008002378 0x7c ./Core/Src/spi.o + 0x0000000008002378 storeindex + .text.getindex + 0x00000000080023f4 0xdc ./Core/Src/spi.o + 0x00000000080023f4 getindex + .text.writebuffertoflash + 0x00000000080024d0 0x118 ./Core/Src/spi.o + 0x00000000080024d0 writebuffertoflash .text.ssd1306_Reset - 0x0000000008001f8c 0xe ./Core/Src/ssd1306.o - 0x0000000008001f8c ssd1306_Reset - *fill* 0x0000000008001f9a 0x2 + 0x00000000080025e8 0xe ./Core/Src/ssd1306.o + 0x00000000080025e8 ssd1306_Reset + *fill* 0x00000000080025f6 0x2 .text.ssd1306_WriteCommand - 0x0000000008001f9c 0x30 ./Core/Src/ssd1306.o - 0x0000000008001f9c ssd1306_WriteCommand + 0x00000000080025f8 0x30 ./Core/Src/ssd1306.o + 0x00000000080025f8 ssd1306_WriteCommand .text.ssd1306_WriteData - 0x0000000008001fcc 0x34 ./Core/Src/ssd1306.o - 0x0000000008001fcc ssd1306_WriteData + 0x0000000008002628 0x34 ./Core/Src/ssd1306.o + 0x0000000008002628 ssd1306_WriteData .text.ssd1306_Init - 0x0000000008002000 0xd4 ./Core/Src/ssd1306.o - 0x0000000008002000 ssd1306_Init + 0x000000000800265c 0xd4 ./Core/Src/ssd1306.o + 0x000000000800265c ssd1306_Init .text.ssd1306_Fill - 0x00000000080020d4 0x30 ./Core/Src/ssd1306.o - 0x00000000080020d4 ssd1306_Fill + 0x0000000008002730 0x30 ./Core/Src/ssd1306.o + 0x0000000008002730 ssd1306_Fill .text.ssd1306_UpdateScreen - 0x0000000008002104 0x50 ./Core/Src/ssd1306.o - 0x0000000008002104 ssd1306_UpdateScreen + 0x0000000008002760 0x50 ./Core/Src/ssd1306.o + 0x0000000008002760 ssd1306_UpdateScreen .text.ssd1306_DrawPixel - 0x0000000008002154 0xa8 ./Core/Src/ssd1306.o - 0x0000000008002154 ssd1306_DrawPixel + 0x00000000080027b0 0xa8 ./Core/Src/ssd1306.o + 0x00000000080027b0 ssd1306_DrawPixel .text.ssd1306_WriteChar - 0x00000000080021fc 0x110 ./Core/Src/ssd1306.o - 0x00000000080021fc ssd1306_WriteChar + 0x0000000008002858 0x110 ./Core/Src/ssd1306.o + 0x0000000008002858 ssd1306_WriteChar .text.ssd1306_WriteString - 0x000000000800230c 0x4c ./Core/Src/ssd1306.o - 0x000000000800230c ssd1306_WriteString + 0x0000000008002968 0x4c ./Core/Src/ssd1306.o + 0x0000000008002968 ssd1306_WriteString .text.ssd1306_SetCursor - 0x0000000008002358 0x30 ./Core/Src/ssd1306.o - 0x0000000008002358 ssd1306_SetCursor + 0x00000000080029b4 0x30 ./Core/Src/ssd1306.o + 0x00000000080029b4 ssd1306_SetCursor .text.ssd1306_Line - 0x0000000008002388 0xd8 ./Core/Src/ssd1306.o - 0x0000000008002388 ssd1306_Line + 0x00000000080029e4 0xd8 ./Core/Src/ssd1306.o + 0x00000000080029e4 ssd1306_Line .text.ssd1306_DrawCircle - 0x0000000008002460 0x10e ./Core/Src/ssd1306.o - 0x0000000008002460 ssd1306_DrawCircle + 0x0000000008002abc 0x10e ./Core/Src/ssd1306.o + 0x0000000008002abc ssd1306_DrawCircle .text.ssd1306_DrawRectangle - 0x000000000800256e 0x6e ./Core/Src/ssd1306.o - 0x000000000800256e ssd1306_DrawRectangle + 0x0000000008002bca 0x6e ./Core/Src/ssd1306.o + 0x0000000008002bca ssd1306_DrawRectangle .text.ssd1306_FillRectangle - 0x00000000080025dc 0x9c ./Core/Src/ssd1306.o - 0x00000000080025dc ssd1306_FillRectangle + 0x0000000008002c38 0x9c ./Core/Src/ssd1306.o + 0x0000000008002c38 ssd1306_FillRectangle .text.ssd1306_DrawBitmap - 0x0000000008002678 0xb6 ./Core/Src/ssd1306.o - 0x0000000008002678 ssd1306_DrawBitmap + 0x0000000008002cd4 0xb6 ./Core/Src/ssd1306.o + 0x0000000008002cd4 ssd1306_DrawBitmap .text.ssd1306_SetContrast - 0x000000000800272e 0x26 ./Core/Src/ssd1306.o - 0x000000000800272e ssd1306_SetContrast + 0x0000000008002d8a 0x26 ./Core/Src/ssd1306.o + 0x0000000008002d8a ssd1306_SetContrast .text.ssd1306_SetDisplayOn - 0x0000000008002754 0x3c ./Core/Src/ssd1306.o - 0x0000000008002754 ssd1306_SetDisplayOn + 0x0000000008002db0 0x3c ./Core/Src/ssd1306.o + 0x0000000008002db0 ssd1306_SetDisplayOn + *fill* 0x0000000008002dec 0x4 + .text.batterygauge + 0x0000000008002df0 0x2f8 ./Core/Src/ssd1306.o + 0x0000000008002df0 batterygauge .text.statemachine - 0x0000000008002790 0x163c ./Core/Src/statemachine.o - 0x0000000008002790 statemachine + 0x00000000080030e8 0x1968 ./Core/Src/statemachine.o + 0x00000000080030e8 statemachine .text.HAL_MspInit - 0x0000000008003dcc 0x48 ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008003dcc HAL_MspInit - .text.HAL_ADC_MspInit - 0x0000000008003e14 0xec ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008003e14 HAL_ADC_MspInit - .text.HAL_I2C_MspInit - 0x0000000008003f00 0xf0 ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008003f00 HAL_I2C_MspInit - .text.HAL_UART_MspInit - 0x0000000008003ff0 0x118 ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008003ff0 HAL_UART_MspInit - .text.HAL_UART_MspDeInit - 0x0000000008004108 0x48 ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008004108 HAL_UART_MspDeInit - .text.HAL_TIM_Base_MspInit - 0x0000000008004150 0x70 ./Core/Src/stm32l4xx_hal_msp.o - 0x0000000008004150 HAL_TIM_Base_MspInit + 0x0000000008004a50 0x48 ./Core/Src/stm32l4xx_hal_msp.o + 0x0000000008004a50 HAL_MspInit .text.NMI_Handler - 0x00000000080041c0 0x6 ./Core/Src/stm32l4xx_it.o - 0x00000000080041c0 NMI_Handler - *fill* 0x00000000080041c6 0x2 + 0x0000000008004a98 0x6 ./Core/Src/stm32l4xx_it.o + 0x0000000008004a98 NMI_Handler .text.HardFault_Handler - 0x00000000080041c8 0x2c ./Core/Src/stm32l4xx_it.o - 0x00000000080041c8 HardFault_Handler + 0x0000000008004a9e 0x6 ./Core/Src/stm32l4xx_it.o + 0x0000000008004a9e HardFault_Handler .text.MemManage_Handler - 0x00000000080041f4 0x6 ./Core/Src/stm32l4xx_it.o - 0x00000000080041f4 MemManage_Handler + 0x0000000008004aa4 0x6 ./Core/Src/stm32l4xx_it.o + 0x0000000008004aa4 MemManage_Handler .text.BusFault_Handler - 0x00000000080041fa 0x6 ./Core/Src/stm32l4xx_it.o - 0x00000000080041fa BusFault_Handler + 0x0000000008004aaa 0x6 ./Core/Src/stm32l4xx_it.o + 0x0000000008004aaa BusFault_Handler .text.UsageFault_Handler - 0x0000000008004200 0x6 ./Core/Src/stm32l4xx_it.o - 0x0000000008004200 UsageFault_Handler + 0x0000000008004ab0 0x6 ./Core/Src/stm32l4xx_it.o + 0x0000000008004ab0 UsageFault_Handler .text.SVC_Handler - 0x0000000008004206 0xe ./Core/Src/stm32l4xx_it.o - 0x0000000008004206 SVC_Handler + 0x0000000008004ab6 0xe ./Core/Src/stm32l4xx_it.o + 0x0000000008004ab6 SVC_Handler .text.DebugMon_Handler - 0x0000000008004214 0xe ./Core/Src/stm32l4xx_it.o - 0x0000000008004214 DebugMon_Handler + 0x0000000008004ac4 0xe ./Core/Src/stm32l4xx_it.o + 0x0000000008004ac4 DebugMon_Handler .text.PendSV_Handler - 0x0000000008004222 0xe ./Core/Src/stm32l4xx_it.o - 0x0000000008004222 PendSV_Handler + 0x0000000008004ad2 0xe ./Core/Src/stm32l4xx_it.o + 0x0000000008004ad2 PendSV_Handler .text.SysTick_Handler - 0x0000000008004230 0x1c ./Core/Src/stm32l4xx_it.o - 0x0000000008004230 SysTick_Handler + 0x0000000008004ae0 0xc ./Core/Src/stm32l4xx_it.o + 0x0000000008004ae0 SysTick_Handler + .text.EXTI1_IRQHandler + 0x0000000008004aec 0xe ./Core/Src/stm32l4xx_it.o + 0x0000000008004aec EXTI1_IRQHandler + *fill* 0x0000000008004afa 0x2 .text.DMA1_Channel1_IRQHandler - 0x000000000800424c 0x14 ./Core/Src/stm32l4xx_it.o - 0x000000000800424c DMA1_Channel1_IRQHandler + 0x0000000008004afc 0x14 ./Core/Src/stm32l4xx_it.o + 0x0000000008004afc DMA1_Channel1_IRQHandler .text.ADC1_IRQHandler - 0x0000000008004260 0x14 ./Core/Src/stm32l4xx_it.o - 0x0000000008004260 ADC1_IRQHandler - .text.EXTI15_10_IRQHandler - 0x0000000008004274 0x18 ./Core/Src/stm32l4xx_it.o - 0x0000000008004274 EXTI15_10_IRQHandler - .text.TIM7_IRQHandler - 0x000000000800428c 0x20 ./Core/Src/stm32l4xx_it.o - 0x000000000800428c TIM7_IRQHandler + 0x0000000008004b10 0x14 ./Core/Src/stm32l4xx_it.o + 0x0000000008004b10 ADC1_IRQHandler + .text.EXTI9_5_IRQHandler + 0x0000000008004b24 0x10 ./Core/Src/stm32l4xx_it.o + 0x0000000008004b24 EXTI9_5_IRQHandler .text.USB_IRQHandler - 0x00000000080042ac 0x14 ./Core/Src/stm32l4xx_it.o - 0x00000000080042ac USB_IRQHandler + 0x0000000008004b34 0x14 ./Core/Src/stm32l4xx_it.o + 0x0000000008004b34 USB_IRQHandler .text.DMA2_Channel7_IRQHandler - 0x00000000080042c0 0x14 ./Core/Src/stm32l4xx_it.o - 0x00000000080042c0 DMA2_Channel7_IRQHandler + 0x0000000008004b48 0x14 ./Core/Src/stm32l4xx_it.o + 0x0000000008004b48 DMA2_Channel7_IRQHandler .text.LPUART1_IRQHandler - 0x00000000080042d4 0x14 ./Core/Src/stm32l4xx_it.o - 0x00000000080042d4 LPUART1_IRQHandler - .text._getpid 0x00000000080042e8 0x10 ./Core/Src/syscalls.o - 0x00000000080042e8 _getpid - .text._kill 0x00000000080042f8 0x20 ./Core/Src/syscalls.o - 0x00000000080042f8 _kill - .text._exit 0x0000000008004318 0x14 ./Core/Src/syscalls.o - 0x0000000008004318 _exit - .text._read 0x000000000800432c 0x3a ./Core/Src/syscalls.o - 0x000000000800432c _read - .text._write 0x0000000008004366 0x38 ./Core/Src/syscalls.o - 0x0000000008004366 _write - .text._close 0x000000000800439e 0x18 ./Core/Src/syscalls.o - 0x000000000800439e _close - .text._fstat 0x00000000080043b6 0x20 ./Core/Src/syscalls.o - 0x00000000080043b6 _fstat - .text._isatty 0x00000000080043d6 0x16 ./Core/Src/syscalls.o - 0x00000000080043d6 _isatty - .text._lseek 0x00000000080043ec 0x1a ./Core/Src/syscalls.o - 0x00000000080043ec _lseek - *fill* 0x0000000008004406 0x2 - .text._sbrk 0x0000000008004408 0x6c ./Core/Src/sysmem.o - 0x0000000008004408 _sbrk + 0x0000000008004b5c 0x14 ./Core/Src/stm32l4xx_it.o + 0x0000000008004b5c LPUART1_IRQHandler + .text._getpid 0x0000000008004b70 0x10 ./Core/Src/syscalls.o + 0x0000000008004b70 _getpid + .text._kill 0x0000000008004b80 0x20 ./Core/Src/syscalls.o + 0x0000000008004b80 _kill + .text._exit 0x0000000008004ba0 0x14 ./Core/Src/syscalls.o + 0x0000000008004ba0 _exit + .text._read 0x0000000008004bb4 0x3a ./Core/Src/syscalls.o + 0x0000000008004bb4 _read + .text._write 0x0000000008004bee 0x38 ./Core/Src/syscalls.o + 0x0000000008004bee _write + .text._close 0x0000000008004c26 0x18 ./Core/Src/syscalls.o + 0x0000000008004c26 _close + .text._fstat 0x0000000008004c3e 0x20 ./Core/Src/syscalls.o + 0x0000000008004c3e _fstat + .text._isatty 0x0000000008004c5e 0x16 ./Core/Src/syscalls.o + 0x0000000008004c5e _isatty + .text._lseek 0x0000000008004c74 0x1a ./Core/Src/syscalls.o + 0x0000000008004c74 _lseek + *fill* 0x0000000008004c8e 0x2 + .text._sbrk 0x0000000008004c90 0x6c ./Core/Src/sysmem.o + 0x0000000008004c90 _sbrk .text.SystemInit - 0x0000000008004474 0x24 ./Core/Src/system_stm32l4xx.o - 0x0000000008004474 SystemInit + 0x0000000008004cfc 0x24 ./Core/Src/system_stm32l4xx.o + 0x0000000008004cfc SystemInit + .text.MX_TIM2_Init + 0x0000000008004d20 0x9c ./Core/Src/tim.o + 0x0000000008004d20 MX_TIM2_Init + .text.HAL_TIM_Base_MspInit + 0x0000000008004dbc 0x3c ./Core/Src/tim.o + 0x0000000008004dbc HAL_TIM_Base_MspInit + .text.MX_LPUART1_UART_Init + 0x0000000008004df8 0x58 ./Core/Src/usart.o + 0x0000000008004df8 MX_LPUART1_UART_Init + .text.MX_USART1_UART_Init + 0x0000000008004e50 0x60 ./Core/Src/usart.o + 0x0000000008004e50 MX_USART1_UART_Init + .text.HAL_UART_MspInit + 0x0000000008004eb0 0x198 ./Core/Src/usart.o + 0x0000000008004eb0 HAL_UART_MspInit + .text.HAL_UART_RxCpltCallback + 0x0000000008005048 0xe4 ./Core/Src/usart.o + 0x0000000008005048 HAL_UART_RxCpltCallback .text.Reset_Handler - 0x0000000008004498 0x50 ./Core/Startup/startup_stm32l432kcux.o - 0x0000000008004498 Reset_Handler + 0x000000000800512c 0x50 ./Core/Startup/startup_stm32l432kcux.o + 0x000000000800512c Reset_Handler .text.Default_Handler - 0x00000000080044e8 0x2 ./Core/Startup/startup_stm32l432kcux.o - 0x00000000080044e8 RTC_Alarm_IRQHandler - 0x00000000080044e8 EXTI2_IRQHandler - 0x00000000080044e8 TIM1_CC_IRQHandler - 0x00000000080044e8 TSC_IRQHandler - 0x00000000080044e8 TAMP_STAMP_IRQHandler - 0x00000000080044e8 EXTI3_IRQHandler - 0x00000000080044e8 LPTIM2_IRQHandler - 0x00000000080044e8 I2C3_ER_IRQHandler - 0x00000000080044e8 EXTI0_IRQHandler - 0x00000000080044e8 CAN1_RX0_IRQHandler - 0x00000000080044e8 FPU_IRQHandler - 0x00000000080044e8 TIM1_UP_TIM16_IRQHandler - 0x00000000080044e8 SPI1_IRQHandler - 0x00000000080044e8 TIM6_DAC_IRQHandler - 0x00000000080044e8 DMA2_Channel2_IRQHandler - 0x00000000080044e8 DMA1_Channel4_IRQHandler - 0x00000000080044e8 DMA1_Channel7_IRQHandler - 0x00000000080044e8 CAN1_RX1_IRQHandler - 0x00000000080044e8 DMA2_Channel1_IRQHandler - 0x00000000080044e8 QUADSPI_IRQHandler - 0x00000000080044e8 I2C1_EV_IRQHandler - 0x00000000080044e8 DMA1_Channel6_IRQHandler - 0x00000000080044e8 DMA2_Channel4_IRQHandler - 0x00000000080044e8 RCC_IRQHandler - 0x00000000080044e8 TIM1_TRG_COM_IRQHandler - 0x00000000080044e8 Default_Handler - 0x00000000080044e8 I2C3_EV_IRQHandler - 0x00000000080044e8 EXTI9_5_IRQHandler - 0x00000000080044e8 RTC_WKUP_IRQHandler - 0x00000000080044e8 PVD_PVM_IRQHandler - 0x00000000080044e8 CAN1_TX_IRQHandler - 0x00000000080044e8 DMA2_Channel5_IRQHandler - 0x00000000080044e8 CRS_IRQHandler - 0x00000000080044e8 DMA1_Channel5_IRQHandler - 0x00000000080044e8 EXTI4_IRQHandler - 0x00000000080044e8 RNG_IRQHandler - 0x00000000080044e8 DMA1_Channel3_IRQHandler - 0x00000000080044e8 COMP_IRQHandler - 0x00000000080044e8 WWDG_IRQHandler - 0x00000000080044e8 DMA2_Channel6_IRQHandler - 0x00000000080044e8 TIM2_IRQHandler - 0x00000000080044e8 EXTI1_IRQHandler - 0x00000000080044e8 USART2_IRQHandler - 0x00000000080044e8 DMA1_Channel2_IRQHandler - 0x00000000080044e8 CAN1_SCE_IRQHandler - 0x00000000080044e8 FLASH_IRQHandler - 0x00000000080044e8 USART1_IRQHandler - 0x00000000080044e8 SPI3_IRQHandler - 0x00000000080044e8 I2C1_ER_IRQHandler - 0x00000000080044e8 SWPMI1_IRQHandler - 0x00000000080044e8 LPTIM1_IRQHandler - 0x00000000080044e8 SAI1_IRQHandler - 0x00000000080044e8 DMA2_Channel3_IRQHandler - 0x00000000080044e8 TIM1_BRK_TIM15_IRQHandler + 0x000000000800517c 0x2 ./Core/Startup/startup_stm32l432kcux.o + 0x000000000800517c RTC_Alarm_IRQHandler + 0x000000000800517c EXTI2_IRQHandler + 0x000000000800517c TIM1_CC_IRQHandler + 0x000000000800517c TSC_IRQHandler + 0x000000000800517c TAMP_STAMP_IRQHandler + 0x000000000800517c EXTI3_IRQHandler + 0x000000000800517c LPTIM2_IRQHandler + 0x000000000800517c I2C3_ER_IRQHandler + 0x000000000800517c EXTI0_IRQHandler + 0x000000000800517c CAN1_RX0_IRQHandler + 0x000000000800517c FPU_IRQHandler + 0x000000000800517c TIM1_UP_TIM16_IRQHandler + 0x000000000800517c SPI1_IRQHandler + 0x000000000800517c TIM6_DAC_IRQHandler + 0x000000000800517c DMA2_Channel2_IRQHandler + 0x000000000800517c DMA1_Channel4_IRQHandler + 0x000000000800517c DMA1_Channel7_IRQHandler + 0x000000000800517c CAN1_RX1_IRQHandler + 0x000000000800517c DMA2_Channel1_IRQHandler + 0x000000000800517c QUADSPI_IRQHandler + 0x000000000800517c I2C1_EV_IRQHandler + 0x000000000800517c DMA1_Channel6_IRQHandler + 0x000000000800517c DMA2_Channel4_IRQHandler + 0x000000000800517c RCC_IRQHandler + 0x000000000800517c TIM1_TRG_COM_IRQHandler + 0x000000000800517c Default_Handler + 0x000000000800517c EXTI15_10_IRQHandler + 0x000000000800517c TIM7_IRQHandler + 0x000000000800517c I2C3_EV_IRQHandler + 0x000000000800517c RTC_WKUP_IRQHandler + 0x000000000800517c PVD_PVM_IRQHandler + 0x000000000800517c CAN1_TX_IRQHandler + 0x000000000800517c DMA2_Channel5_IRQHandler + 0x000000000800517c CRS_IRQHandler + 0x000000000800517c DMA1_Channel5_IRQHandler + 0x000000000800517c EXTI4_IRQHandler + 0x000000000800517c RNG_IRQHandler + 0x000000000800517c DMA1_Channel3_IRQHandler + 0x000000000800517c COMP_IRQHandler + 0x000000000800517c WWDG_IRQHandler + 0x000000000800517c DMA2_Channel6_IRQHandler + 0x000000000800517c TIM2_IRQHandler + 0x000000000800517c USART2_IRQHandler + 0x000000000800517c DMA1_Channel2_IRQHandler + 0x000000000800517c CAN1_SCE_IRQHandler + 0x000000000800517c FLASH_IRQHandler + 0x000000000800517c USART1_IRQHandler + 0x000000000800517c SPI3_IRQHandler + 0x000000000800517c I2C1_ER_IRQHandler + 0x000000000800517c SWPMI1_IRQHandler + 0x000000000800517c LPTIM1_IRQHandler + 0x000000000800517c SAI1_IRQHandler + 0x000000000800517c DMA2_Channel3_IRQHandler + 0x000000000800517c TIM1_BRK_TIM15_IRQHandler .text.HAL_Init - 0x00000000080044ea 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x00000000080044ea HAL_Init - *fill* 0x000000000800451a 0x2 + 0x000000000800517e 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x000000000800517e HAL_Init + *fill* 0x00000000080051ae 0x2 .text.HAL_InitTick - 0x000000000800451c 0x78 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x000000000800451c HAL_InitTick + 0x00000000080051b0 0x78 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x00000000080051b0 HAL_InitTick .text.HAL_IncTick - 0x0000000008004594 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x0000000008004594 HAL_IncTick + 0x0000000008005228 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x0000000008005228 HAL_IncTick .text.HAL_GetTick - 0x00000000080045bc 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x00000000080045bc HAL_GetTick + 0x0000000008005250 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x0000000008005250 HAL_GetTick .text.HAL_Delay - 0x00000000080045d4 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x00000000080045d4 HAL_Delay + 0x0000000008005268 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x0000000008005268 HAL_Delay .text.LL_ADC_SetCommonClock - 0x000000000800461c 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080052b0 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_SetCommonPathInternalCh - 0x0000000008004642 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080052d6 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_GetCommonPathInternalCh - 0x0000000008004668 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080052fc 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_SetOffset - 0x0000000008004684 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005318 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_GetOffsetChannel - 0x00000000080046cc 0x2c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005360 0x2c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_SetOffsetState - 0x00000000080046f8 0x36 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x000000000800538c 0x36 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_REG_IsTriggerSourceSWStart - 0x000000000800472e 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080053c2 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_REG_SetSequencerRanks - 0x0000000008004754 0x58 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080053e8 0x58 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_INJ_IsTriggerSourceSWStart - 0x00000000080047ac 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005440 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_SetChannelSamplingTime - 0x00000000080047d2 0x56 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005466 0x56 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_SetChannelSingleDiff - 0x0000000008004828 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080054bc 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_DisableDeepPowerDown - 0x0000000008004870 0x24 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005504 0x24 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_IsDeepPowerDownEnabled - 0x0000000008004894 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005528 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_EnableInternalRegulator - 0x00000000080048bc 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005550 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_IsInternalRegulatorEnabled - 0x00000000080048e4 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005578 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_Enable - 0x000000000800490c 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080055a0 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_IsEnabled - 0x0000000008004934 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080055c8 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_REG_StartConversion - 0x000000000800495a 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080055ee 0x28 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_REG_IsConversionOngoing - 0x0000000008004982 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005616 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .text.LL_ADC_INJ_IsConversionOngoing - 0x00000000080049a8 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - *fill* 0x00000000080049ce 0x2 + 0x000000000800563c 0x26 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + *fill* 0x0000000008005662 0x2 .text.HAL_ADC_Init - 0x00000000080049d0 0x284 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080049d0 HAL_ADC_Init + 0x0000000008005664 0x284 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005664 HAL_ADC_Init .text.HAL_ADC_Start_DMA - 0x0000000008004c54 0x108 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x0000000008004c54 HAL_ADC_Start_DMA + 0x00000000080058e8 0x108 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080058e8 HAL_ADC_Start_DMA .text.HAL_ADC_IRQHandler - 0x0000000008004d5c 0x368 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x0000000008004d5c HAL_ADC_IRQHandler + 0x00000000080059f0 0x368 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x00000000080059f0 HAL_ADC_IRQHandler .text.HAL_ADC_ConvHalfCpltCallback - 0x00000000080050c4 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080050c4 HAL_ADC_ConvHalfCpltCallback + 0x0000000008005d58 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005d58 HAL_ADC_ConvHalfCpltCallback .text.HAL_ADC_LevelOutOfWindowCallback - 0x00000000080050d8 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080050d8 HAL_ADC_LevelOutOfWindowCallback + 0x0000000008005d6c 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005d6c HAL_ADC_LevelOutOfWindowCallback .text.HAL_ADC_ErrorCallback - 0x00000000080050ec 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080050ec HAL_ADC_ErrorCallback + 0x0000000008005d80 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005d80 HAL_ADC_ErrorCallback .text.HAL_ADC_ConfigChannel - 0x0000000008005100 0x7c4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x0000000008005100 HAL_ADC_ConfigChannel + 0x0000000008005d94 0x7c4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008005d94 HAL_ADC_ConfigChannel .text.ADC_Enable - 0x00000000080058c4 0x10c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080058c4 ADC_Enable + 0x0000000008006558 0x10c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008006558 ADC_Enable .text.ADC_DMAConvCplt - 0x00000000080059d0 0xd8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x00000000080059d0 ADC_DMAConvCplt + 0x0000000008006664 0xd8 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008006664 ADC_DMAConvCplt .text.ADC_DMAHalfConvCplt - 0x0000000008005aa8 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x0000000008005aa8 ADC_DMAHalfConvCplt + 0x000000000800673c 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x000000000800673c ADC_DMAHalfConvCplt .text.ADC_DMAError - 0x0000000008005ac4 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o - 0x0000000008005ac4 ADC_DMAError + 0x0000000008006758 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x0000000008006758 ADC_DMAError .text.HAL_ADCEx_InjectedConvCpltCallback - 0x0000000008005af8 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - 0x0000000008005af8 HAL_ADCEx_InjectedConvCpltCallback + 0x000000000800678c 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x000000000800678c HAL_ADCEx_InjectedConvCpltCallback .text.HAL_ADCEx_InjectedQueueOverflowCallback - 0x0000000008005b0c 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - 0x0000000008005b0c HAL_ADCEx_InjectedQueueOverflowCallback + 0x00000000080067a0 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x00000000080067a0 HAL_ADCEx_InjectedQueueOverflowCallback .text.HAL_ADCEx_LevelOutOfWindow2Callback - 0x0000000008005b20 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - 0x0000000008005b20 HAL_ADCEx_LevelOutOfWindow2Callback + 0x00000000080067b4 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x00000000080067b4 HAL_ADCEx_LevelOutOfWindow2Callback .text.HAL_ADCEx_LevelOutOfWindow3Callback - 0x0000000008005b34 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - 0x0000000008005b34 HAL_ADCEx_LevelOutOfWindow3Callback + 0x00000000080067c8 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x00000000080067c8 HAL_ADCEx_LevelOutOfWindow3Callback .text.HAL_ADCEx_EndOfSamplingCallback - 0x0000000008005b48 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o - 0x0000000008005b48 HAL_ADCEx_EndOfSamplingCallback + 0x00000000080067dc 0x14 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x00000000080067dc HAL_ADCEx_EndOfSamplingCallback .text.__NVIC_SetPriorityGrouping - 0x0000000008005b5c 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x00000000080067f0 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x0000000008005ba4 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x0000000008006838 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_EnableIRQ - 0x0000000008005bc0 0x3c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - .text.__NVIC_DisableIRQ - 0x0000000008005bfc 0x48 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x0000000008006854 0x3c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.__NVIC_SetPriority - 0x0000000008005c44 0x54 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x0000000008006890 0x54 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.NVIC_EncodePriority - 0x0000000008005c98 0x66 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - *fill* 0x0000000008005cfe 0x2 + 0x00000000080068e4 0x66 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + *fill* 0x000000000800694a 0x2 .text.SysTick_Config - 0x0000000008005d00 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x000000000800694c 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x0000000008005d44 0x16 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - 0x0000000008005d44 HAL_NVIC_SetPriorityGrouping + 0x0000000008006990 0x16 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x0000000008006990 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x0000000008005d5a 0x38 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - 0x0000000008005d5a HAL_NVIC_SetPriority + 0x00000000080069a6 0x38 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x00000000080069a6 HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x0000000008005d92 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - 0x0000000008005d92 HAL_NVIC_EnableIRQ - .text.HAL_NVIC_DisableIRQ - 0x0000000008005dae 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - 0x0000000008005dae HAL_NVIC_DisableIRQ + 0x00000000080069de 0x1c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x00000000080069de HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x0000000008005dca 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o - 0x0000000008005dca HAL_SYSTICK_Config - *fill* 0x0000000008005de2 0x2 + 0x00000000080069fa 0x18 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x00000000080069fa HAL_SYSTICK_Config + *fill* 0x0000000008006a12 0x2 .text.HAL_DMA_Init - 0x0000000008005de4 0x170 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o - 0x0000000008005de4 HAL_DMA_Init - .text.HAL_DMA_DeInit - 0x0000000008005f54 0x124 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o - 0x0000000008005f54 HAL_DMA_DeInit + 0x0000000008006a14 0x170 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + 0x0000000008006a14 HAL_DMA_Init .text.HAL_DMA_Start_IT - 0x0000000008006078 0xc0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o - 0x0000000008006078 HAL_DMA_Start_IT + 0x0000000008006b84 0xc0 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + 0x0000000008006b84 HAL_DMA_Start_IT .text.HAL_DMA_Abort - 0x0000000008006138 0x7c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o - 0x0000000008006138 HAL_DMA_Abort + 0x0000000008006c44 0x7c ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + 0x0000000008006c44 HAL_DMA_Abort .text.HAL_DMA_Abort_IT - 0x00000000080061b4 0x82 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./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o - 0x000000000800640c HAL_GPIO_Init - .text.HAL_GPIO_DeInit - 0x00000000080066e0 0x194 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o - 0x00000000080066e0 HAL_GPIO_DeInit + 0x0000000008006f18 0x2d4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + 0x0000000008006f18 HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x0000000008006874 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o - 0x0000000008006874 HAL_GPIO_WritePin + 0x00000000080071ec 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + 0x00000000080071ec HAL_GPIO_WritePin .text.HAL_GPIO_EXTI_IRQHandler - 0x00000000080068a4 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o - 0x00000000080068a4 HAL_GPIO_EXTI_IRQHandler + 0x000000000800721c 0x30 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + 0x000000000800721c HAL_GPIO_EXTI_IRQHandler .text.HAL_I2C_Init - 0x00000000080068d4 0x136 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.rodata.p05.0 0x0000000008018b78 0xc C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mprec.o) + 0x000000000801af88 0xc8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mprec.o) + 0x000000000801af88 __mprec_tens + .rodata.p05.0 0x000000000801b050 0xc C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mprec.o) .rodata._svfprintf_r.str1.1 - 0x0000000008018b84 0x11 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) + 0x000000000801b05c 0x11 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) .rodata._vfprintf_r.str1.1 - 0x0000000008018b95 0x11 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o) - *fill* 0x0000000008018b95 0x3 + 0x000000000801b06d 0x11 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o) + *fill* 0x000000000801b06d 0x3 .rodata.npio2_hw - 0x0000000008018b98 0x80 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-e_rem_pio2.o) + 0x000000000801b070 0x80 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-e_rem_pio2.o) .rodata.two_over_pi - 0x0000000008018c18 0x108 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-e_rem_pio2.o) - .rodata.halF 0x0000000008018d20 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) - .rodata.ln2HI 0x0000000008018d28 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) - .rodata.ln2LO 0x0000000008018d30 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) - .rodata.PIo2 0x0000000008018d38 0x40 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-k_rem_pio2.o) + 0x000000000801b0f0 0x108 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-e_rem_pio2.o) + .rodata.halF 0x000000000801b1f8 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) + .rodata.ln2HI 0x000000000801b200 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) + .rodata.ln2LO 0x000000000801b208 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-ef_exp.o) + .rodata.PIo2 0x000000000801b210 0x40 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-k_rem_pio2.o) .rodata.init_jk - 0x0000000008018d78 0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-k_rem_pio2.o) - 0x0000000008018d88 . = ALIGN (0x4) + 0x000000000801b250 0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a(libm_a-k_rem_pio2.o) + 0x000000000801b260 . = ALIGN (0x4) -.ARM.extab 0x0000000008018d88 0x0 - 0x0000000008018d88 . = ALIGN (0x4) +.ARM.extab 0x000000000801b260 0x0 + 0x000000000801b260 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x0000000008018d88 . = ALIGN (0x4) + 0x000000000801b260 . = ALIGN (0x4) -.ARM 0x0000000008018d88 0x8 - 0x0000000008018d88 . = ALIGN (0x4) - 0x0000000008018d88 __exidx_start = . +.ARM 0x000000000801b260 0x8 + 0x000000000801b260 . = ALIGN (0x4) + 0x000000000801b260 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x0000000008018d88 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) - 0x0000000008018d90 __exidx_end = . - 0x0000000008018d90 . = ALIGN (0x4) + .ARM.exidx 0x000000000801b260 0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) + 0x000000000801b268 __exidx_end = . + 0x000000000801b268 . = ALIGN (0x4) -.rel.dyn 0x0000000008018d90 0x0 - .rel.iplt 0x0000000008018d90 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.rel.dyn 0x000000000801b268 0x0 + .rel.iplt 0x000000000801b268 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.preinit_array 0x0000000008018d90 0x0 - 0x0000000008018d90 . = ALIGN (0x4) - 0x0000000008018d90 PROVIDE (__preinit_array_start = .) +.preinit_array 0x000000000801b268 0x0 + 0x000000000801b268 . = ALIGN (0x4) + 0x000000000801b268 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x0000000008018d90 PROVIDE (__preinit_array_end = .) - 0x0000000008018d90 . = ALIGN (0x4) + 0x000000000801b268 PROVIDE (__preinit_array_end = .) + 0x000000000801b268 . = ALIGN (0x4) -.init_array 0x0000000008018d90 0x4 - 0x0000000008018d90 . = ALIGN (0x4) - 0x0000000008018d90 PROVIDE (__init_array_start = .) +.init_array 0x000000000801b268 0x4 + 0x000000000801b268 . = ALIGN (0x4) + 0x000000000801b268 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x0000000008018d90 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x0000000008018d94 PROVIDE (__init_array_end = .) - 0x0000000008018d94 . = ALIGN (0x4) + .init_array 0x000000000801b268 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x000000000801b26c PROVIDE (__init_array_end = .) + 0x000000000801b26c . = ALIGN (0x4) -.fini_array 0x0000000008018d94 0x4 - 0x0000000008018d94 . = ALIGN (0x4) +.fini_array 0x000000000801b26c 0x4 + 0x000000000801b26c . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x0000000008018d94 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .fini_array 0x000000000801b26c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x0000000008018d98 . = ALIGN (0x4) - 0x0000000008018d98 _sidata = LOADADDR (.data) + 0x000000000801b270 . = ALIGN (0x4) + 0x000000000801b270 _sidata = LOADADDR (.data) -.data 0x0000000020000000 0x314 load address 0x0000000008018d98 +.data 0x0000000020000000 0x2f4 load address 0x000000000801b270 0x0000000020000000 . = ALIGN (0x4) 0x0000000020000000 _sdata = . *(.data) *(.data*) - .data.tscal2 0x0000000020000000 0x4 ./Core/Src/main.o + .data.tscal2 0x0000000020000000 0x4 ./Core/Src/adc.o 0x0000000020000000 tscal2 - .data.tscal1 0x0000000020000004 0x4 ./Core/Src/main.o + .data.tscal1 0x0000000020000004 0x4 ./Core/Src/adc.o 0x0000000020000004 tscal1 .data.Font_6x8 0x0000000020000008 0x8 ./Core/Src/ssd1306_fonts.o @@ -7722,185 +9284,245 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000020000028 0x1 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o 0x0000000020000028 uwTickFreq *fill* 0x0000000020000029 0x3 - .data.USBD_HID - 0x000000002000002c 0x38 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - 0x000000002000002c USBD_HID - .data.USBD_HID_CfgDesc - 0x0000000020000064 0x22 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - *fill* 0x0000000020000086 0x2 - .data.USBD_HID_Desc - 0x0000000020000088 0x9 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - *fill* 0x0000000020000091 0x3 - .data.USBD_HID_DeviceQualifierDesc - 0x0000000020000094 0xa ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - *fill* 0x000000002000009e 0x2 - .data.HID_MOUSE_ReportDesc - 0x00000000200000a0 0x4a ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - .data.HIDInEpAdd - 0x00000000200000ea 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o - *fill* 0x00000000200000eb 0x1 - .data.FS_Desc 0x00000000200000ec 0x20 ./USB_DEVICE/App/usbd_desc.o - 0x00000000200000ec FS_Desc + .data.USBD_CDC_DeviceQualifierDesc + 0x000000002000002c 0xa ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x0000000020000036 0x2 + .data.USBD_CDC + 0x0000000020000038 0x38 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + 0x0000000020000038 USBD_CDC + .data.USBD_CDC_CfgDesc + 0x0000000020000070 0x43 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data.CDCInEpAdd + 0x00000000200000b3 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data.CDCOutEpAdd + 0x00000000200000b4 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + .data.CDCCmdEpAdd + 0x00000000200000b5 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o + *fill* 0x00000000200000b6 0x2 + .data.USBD_Interface_fops_FS + 0x00000000200000b8 0x14 ./USB_DEVICE/App/usbd_cdc_if.o + 0x00000000200000b8 USBD_Interface_fops_FS + .data.FS_Desc 0x00000000200000cc 0x20 ./USB_DEVICE/App/usbd_desc.o + 0x00000000200000cc FS_Desc .data.USBD_FS_DeviceDesc - 0x000000002000010c 0x12 ./USB_DEVICE/App/usbd_desc.o - 0x000000002000010c USBD_FS_DeviceDesc - *fill* 0x000000002000011e 0x2 + 0x00000000200000ec 0x12 ./USB_DEVICE/App/usbd_desc.o + 0x00000000200000ec USBD_FS_DeviceDesc + *fill* 0x00000000200000fe 0x2 .data.USBD_FS_BOSDesc - 0x0000000020000120 0xc ./USB_DEVICE/App/usbd_desc.o - 0x0000000020000120 USBD_FS_BOSDesc + 0x0000000020000100 0xc ./USB_DEVICE/App/usbd_desc.o + 0x0000000020000100 USBD_FS_BOSDesc .data.USBD_LangIDDesc - 0x000000002000012c 0x4 ./USB_DEVICE/App/usbd_desc.o - 0x000000002000012c USBD_LangIDDesc + 0x000000002000010c 0x4 ./USB_DEVICE/App/usbd_desc.o + 0x000000002000010c USBD_LangIDDesc .data.USBD_StringSerial - 0x0000000020000130 0x1a ./USB_DEVICE/App/usbd_desc.o - 0x0000000020000130 USBD_StringSerial - *fill* 0x000000002000014a 0x2 - .data.__sglue 0x000000002000014c 0xc C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) - 0x000000002000014c __sglue + 0x0000000020000110 0x1a ./USB_DEVICE/App/usbd_desc.o + 0x0000000020000110 USBD_StringSerial + *fill* 0x000000002000012a 0x2 + .data.__sglue 0x000000002000012c 0xc C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) + 0x000000002000012c __sglue .data.__global_locale - 0x0000000020000158 0x16c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-locale.o) - 0x0000000020000158 __global_locale + 0x0000000020000138 0x16c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-locale.o) + 0x0000000020000138 __global_locale .data._impure_data - 0x00000000200002c4 0x4c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o) - 0x00000000200002c4 _impure_data + 0x00000000200002a4 0x4c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o) + 0x00000000200002a4 _impure_data .data._impure_ptr - 0x0000000020000310 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o) - 0x0000000020000310 _impure_ptr + 0x00000000200002f0 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o) + 0x00000000200002f0 _impure_ptr *(.RamFunc) *(.RamFunc*) - 0x0000000020000314 . = ALIGN (0x4) - 0x0000000020000314 _edata = . + 0x00000000200002f4 . = ALIGN (0x4) + 0x00000000200002f4 _edata = . -.igot.plt 0x0000000020000314 0x0 load address 0x00000000080190ac - .igot.plt 0x0000000020000314 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x0000000020000314 . = ALIGN (0x4) +.igot.plt 0x00000000200002f4 0x0 load address 0x000000000801b564 + .igot.plt 0x00000000200002f4 0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x00000000200002f4 . = ALIGN (0x4) -.bss 0x0000000020000318 0x12c0 load address 0x00000000080190ac - 0x0000000020000318 _sbss = . - 0x0000000020000318 __bss_start__ = _sbss +.bss 0x00000000200002f8 0x2098 load address 0x000000000801b564 + 0x00000000200002f8 _sbss = . + 0x00000000200002f8 __bss_start__ = _sbss *(.bss) - .bss 0x0000000020000318 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .bss 0x00000000200002f8 0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o *(.bss*) - .bss.hadc1 0x0000000020000334 0x64 ./Core/Src/main.o - 0x0000000020000334 hadc1 + .bss.hadc1 0x0000000020000314 0x64 ./Core/Src/adc.o + 0x0000000020000314 hadc1 .bss.hdma_adc1 - 0x0000000020000398 0x48 ./Core/Src/main.o - 0x0000000020000398 hdma_adc1 - .bss.hi2c3 0x00000000200003e0 0x54 ./Core/Src/main.o - 0x00000000200003e0 hi2c3 - .bss.hlpuart1 0x0000000020000434 0x88 ./Core/Src/main.o - 0x0000000020000434 hlpuart1 - .bss.hdma_lpuart_rx - 0x00000000200004bc 0x48 ./Core/Src/main.o - 0x00000000200004bc hdma_lpuart_rx - .bss.htim2 0x0000000020000504 0x4c ./Core/Src/main.o - 0x0000000020000504 htim2 - .bss.htim7 0x0000000020000550 0x4c ./Core/Src/main.o - 0x0000000020000550 htim7 - .bss.oldPos 0x000000002000059c 0x2 ./Core/Src/main.o - 0x000000002000059c oldPos - .bss.newPos 0x000000002000059e 0x2 ./Core/Src/main.o - 0x000000002000059e newPos - .bss.RxBuffer 0x00000000200005a0 0x40 ./Core/Src/main.o - 0x00000000200005a0 RxBuffer + 0x0000000020000378 0x48 ./Core/Src/adc.o + 0x0000000020000378 hdma_adc1 + .bss.hi2c1 0x00000000200003c0 0x54 ./Core/Src/i2c.o + 0x00000000200003c0 hi2c1 + .bss.hi2c3 0x0000000020000414 0x54 ./Core/Src/i2c.o + 0x0000000020000414 hi2c3 + .bss.oldPos 0x0000000020000468 0x2 ./Core/Src/main.o + 0x0000000020000468 oldPos + .bss.newPos 0x000000002000046a 0x2 ./Core/Src/main.o + 0x000000002000046a newPos + .bss.RxBuffer 0x000000002000046c 0x40 ./Core/Src/main.o + 0x000000002000046c RxBuffer .bss.DataBuffer - 0x00000000200005e0 0x200 ./Core/Src/main.o - 0x00000000200005e0 DataBuffer - .bss.myData 0x00000000200007e0 0x40 ./Core/Src/main.o - 0x00000000200007e0 myData - .bss.BTN_A 0x0000000020000820 0x4 ./Core/Src/main.o - 0x0000000020000820 BTN_A - .bss.BTN_B 0x0000000020000824 0x4 ./Core/Src/main.o - 0x0000000020000824 BTN_B - .bss.state 0x0000000020000828 0x1 ./Core/Src/main.o - 0x0000000020000828 state - .bss.hrstate 0x0000000020000829 0x1 ./Core/Src/main.o - 0x0000000020000829 hrstate - .bss.spdstate 0x000000002000082a 0x1 ./Core/Src/main.o - 0x000000002000082a spdstate - .bss.posstate 0x000000002000082b 0x1 ./Core/Src/main.o - 0x000000002000082b posstate + 0x00000000200004ac 0x200 ./Core/Src/main.o + 0x00000000200004ac DataBuffer + *fill* 0x00000000200006ac 0x4 + .bss.myData 0x00000000200006b0 0x40 ./Core/Src/main.o + 0x00000000200006b0 myData + .bss.BTN_A 0x00000000200006f0 0x4 ./Core/Src/main.o + 0x00000000200006f0 BTN_A + .bss.BTN_B 0x00000000200006f4 0x4 ./Core/Src/main.o + 0x00000000200006f4 BTN_B + .bss.state 0x00000000200006f8 0x1 ./Core/Src/main.o + 0x00000000200006f8 state + .bss.hrstate 0x00000000200006f9 0x1 ./Core/Src/main.o + 0x00000000200006f9 hrstate + .bss.spdstate 0x00000000200006fa 0x1 ./Core/Src/main.o + 0x00000000200006fa spdstate + .bss.posstate 0x00000000200006fb 0x1 ./Core/Src/main.o + 0x00000000200006fb posstate .bss.chronostate - 0x000000002000082c 0x1 ./Core/Src/main.o - 0x000000002000082c chronostate - *fill* 0x000000002000082d 0x3 - .bss.rawdata 0x0000000020000830 0x4 ./Core/Src/main.o - 0x0000000020000830 rawdata - .bss.temp 0x0000000020000834 0x4 ./Core/Src/main.o - 0x0000000020000834 temp - .bss.vrefint 0x0000000020000838 0x4 ./Core/Src/main.o - 0x0000000020000838 vrefint - .bss.data 0x000000002000083c 0x3c ./Core/Src/nmea_parse.o - 0x000000002000083c data + 0x00000000200006fc 0x1 ./Core/Src/main.o + 0x00000000200006fc chronostate + *fill* 0x00000000200006fd 0x3 + .bss.hspif1 0x0000000020000700 0x20 ./Core/Src/main.o + 0x0000000020000700 hspif1 + .bss.rawdata 0x0000000020000720 0x6 ./Core/Src/main.o + 0x0000000020000720 rawdata + *fill* 0x0000000020000726 0x2 + .bss.temp 0x0000000020000728 0x4 ./Core/Src/main.o + 0x0000000020000728 temp + .bss.vrefint 0x000000002000072c 0x4 ./Core/Src/main.o + 0x000000002000072c vrefint + .bss.vbat 0x0000000020000730 0x4 ./Core/Src/main.o + 0x0000000020000730 vbat + .bss.flashwrite + 0x0000000020000734 0x100 ./Core/Src/main.o + 0x0000000020000734 flashwrite + .bss.flashread + 0x0000000020000834 0x100 ./Core/Src/main.o + 0x0000000020000834 flashread + .bss.pageoffset + 0x0000000020000934 0x4 ./Core/Src/main.o + 0x0000000020000934 pageoffset + .bss.pagenumber + 0x0000000020000938 0x4 ./Core/Src/main.o + 0x0000000020000938 pagenumber + .bss.sectoreraseen + 0x000000002000093c 0x4 ./Core/Src/main.o + 0x000000002000093c sectoreraseen + .bss.numbuf1 0x0000000020000940 0xa ./Core/Src/main.o + 0x0000000020000940 numbuf1 + *fill* 0x000000002000094a 0x2 + .bss.numbuf2 0x000000002000094c 0xa ./Core/Src/main.o + 0x000000002000094c numbuf2 + *fill* 0x0000000020000956 0x2 + .bss.data 0x0000000020000958 0x3c ./Core/Src/nmea_parse.o + 0x0000000020000958 data + .bss.indexbuffer + 0x0000000020000994 0x32 ./Core/Src/spi.o + 0x0000000020000994 indexbuffer + *fill* 0x00000000200009c6 0x2 + .bss.hspi1 0x00000000200009c8 0x64 ./Core/Src/spi.o + 0x00000000200009c8 hspi1 .bss.SSD1306_Buffer - 0x0000000020000878 0x400 ./Core/Src/ssd1306.o - .bss.SSD1306 0x0000000020000c78 0x6 ./Core/Src/ssd1306.o - *fill* 0x0000000020000c7e 0x2 - .bss.vitmax 0x0000000020000c80 0x4 ./Core/Src/statemachine.o - 0x0000000020000c80 vitmax - .bss.seconde 0x0000000020000c84 0x4 ./Core/Src/statemachine.o - 0x0000000020000c84 seconde - .bss.min 0x0000000020000c88 0x4 ./Core/Src/statemachine.o - 0x0000000020000c88 min + 0x0000000020000a2c 0x400 ./Core/Src/ssd1306.o + .bss.SSD1306 0x0000000020000e2c 0x6 ./Core/Src/ssd1306.o + .bss.usbstate 0x0000000020000e32 0x1 ./Core/Src/statemachine.o + 0x0000000020000e32 usbstate + .bss.balisestate + 0x0000000020000e33 0x1 ./Core/Src/statemachine.o + 0x0000000020000e33 balisestate + .bss.vitmax 0x0000000020000e34 0x4 ./Core/Src/statemachine.o + 0x0000000020000e34 vitmax + .bss.seconde 0x0000000020000e38 0x4 ./Core/Src/statemachine.o + 0x0000000020000e38 seconde + .bss.min 0x0000000020000e3c 0x4 ./Core/Src/statemachine.o + 0x0000000020000e3c min .bss.starttime - 0x0000000020000c8c 0x4 ./Core/Src/statemachine.o - 0x0000000020000c8c starttime - .bss.calctime 0x0000000020000c90 0x4 ./Core/Src/statemachine.o - 0x0000000020000c90 calctime - .bss.distanceparcouru - 0x0000000020000c94 0x4 ./Core/Src/stm32l4xx_it.o - 0x0000000020000c94 distanceparcouru + 0x0000000020000e40 0x4 ./Core/Src/statemachine.o + 0x0000000020000e40 starttime + .bss.calctime 0x0000000020000e44 0x4 ./Core/Src/statemachine.o + 0x0000000020000e44 calctime + .bss.str 0x0000000020000e48 0x14 ./Core/Src/statemachine.o + 0x0000000020000e48 str + .bss.str1 0x0000000020000e5c 0x32 ./Core/Src/statemachine.o + 0x0000000020000e5c str1 + *fill* 0x0000000020000e8e 0x2 + .bss.flashbufferlen + 0x0000000020000e90 0x4 ./Core/Src/statemachine.o + 0x0000000020000e90 flashbufferlen + .bss.erasetime + 0x0000000020000e94 0x4 ./Core/Src/statemachine.o + 0x0000000020000e94 erasetime + .bss.erasedisplay + 0x0000000020000e98 0x4 ./Core/Src/statemachine.o + 0x0000000020000e98 erasedisplay + .bss.usbtransmiten + 0x0000000020000e9c 0x4 ./Core/Src/statemachine.o + 0x0000000020000e9c usbtransmiten .bss.__sbrk_heap_end - 0x0000000020000c98 0x4 ./Core/Src/sysmem.o - .bss.uwTick 0x0000000020000c9c 0x4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o - 0x0000000020000c9c uwTick - .bss.cfgidx.0 0x0000000020000ca0 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o - *fill* 0x0000000020000ca1 0x3 + 0x0000000020000ea0 0x4 ./Core/Src/sysmem.o + .bss.htim2 0x0000000020000ea4 0x4c ./Core/Src/tim.o + 0x0000000020000ea4 htim2 + .bss.hlpuart1 0x0000000020000ef0 0x88 ./Core/Src/usart.o + 0x0000000020000ef0 hlpuart1 + .bss.huart1 0x0000000020000f78 0x88 ./Core/Src/usart.o + 0x0000000020000f78 huart1 + .bss.hdma_lpuart_rx + 0x0000000020001000 0x48 ./Core/Src/usart.o + 0x0000000020001000 hdma_lpuart_rx + .bss.uwTick 0x0000000020001048 0x4 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x0000000020001048 uwTick + .bss.cfgidx.0 0x000000002000104c 0x1 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + *fill* 0x000000002000104d 0x3 .bss.hUsbDeviceFS - 0x0000000020000ca4 0x2dc ./USB_DEVICE/App/usb_device.o - 0x0000000020000ca4 hUsbDeviceFS + 0x0000000020001050 0x2dc ./USB_DEVICE/App/usb_device.o + 0x0000000020001050 hUsbDeviceFS + .bss.UserRxBufferFS + 0x000000002000132c 0x400 ./USB_DEVICE/App/usbd_cdc_if.o + 0x000000002000132c UserRxBufferFS + .bss.UserTxBufferFS + 0x000000002000172c 0x400 ./USB_DEVICE/App/usbd_cdc_if.o + 0x000000002000172c UserTxBufferFS .bss.USBD_StrDesc - 0x0000000020000f80 0x200 ./USB_DEVICE/App/usbd_desc.o - 0x0000000020000f80 USBD_StrDesc + 0x0000000020001b2c 0x200 ./USB_DEVICE/App/usbd_desc.o + 0x0000000020001b2c USBD_StrDesc .bss.hpcd_USB_FS - 0x0000000020001180 0x2f8 ./USB_DEVICE/Target/usbd_conf.o - 0x0000000020001180 hpcd_USB_FS - .bss.mem.0 0x0000000020001478 0x14 ./USB_DEVICE/Target/usbd_conf.o + 0x0000000020001d2c 0x2f8 ./USB_DEVICE/Target/usbd_conf.o + 0x0000000020001d2c hpcd_USB_FS + .bss.mem.0 0x0000000020002024 0x220 ./USB_DEVICE/Target/usbd_conf.o .bss.__malloc_free_list - 0x000000002000148c 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) - 0x000000002000148c __malloc_free_list + 0x0000000020002244 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) + 0x0000000020002244 __malloc_free_list .bss.__malloc_sbrk_start - 0x0000000020001490 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) - 0x0000000020001490 __malloc_sbrk_start - .bss.__sf 0x0000000020001494 0x138 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) - 0x0000000020001494 __sf + 0x0000000020002248 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) + 0x0000000020002248 __malloc_sbrk_start + .bss.__sf 0x000000002000224c 0x138 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) + 0x000000002000224c __sf .bss.__stdio_exit_handler - 0x00000000200015cc 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) - 0x00000000200015cc __stdio_exit_handler - .bss.errno 0x00000000200015d0 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o) - 0x00000000200015d0 errno + 0x0000000020002384 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) + 0x0000000020002384 __stdio_exit_handler + .bss.errno 0x0000000020002388 0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o) + 0x0000000020002388 errno .bss.__lock___malloc_recursive_mutex - 0x00000000200015d4 0x1 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) - 0x00000000200015d4 __lock___malloc_recursive_mutex + 0x000000002000238c 0x1 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) + 0x000000002000238c __lock___malloc_recursive_mutex .bss.__lock___sfp_recursive_mutex - 0x00000000200015d5 0x1 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) - 0x00000000200015d5 __lock___sfp_recursive_mutex + 0x000000002000238d 0x1 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) + 0x000000002000238d __lock___sfp_recursive_mutex *(COMMON) - 0x00000000200015d8 . = ALIGN (0x4) - *fill* 0x00000000200015d6 0x2 - 0x00000000200015d8 _ebss = . - 0x00000000200015d8 __bss_end__ = _ebss + 0x0000000020002390 . = ALIGN (0x4) + *fill* 0x000000002000238e 0x2 + 0x0000000020002390 _ebss = . + 0x0000000020002390 __bss_end__ = _ebss ._user_heap_stack - 0x00000000200015d8 0x600 load address 0x00000000080190ac - 0x00000000200015d8 . = ALIGN (0x8) + 0x0000000020002390 0x600 load address 0x000000000801b564 + 0x0000000020002390 . = ALIGN (0x8) [!provide] PROVIDE (end = .) - 0x00000000200015d8 PROVIDE (_end = .) - 0x00000000200017d8 . = (. + _Min_Heap_Size) - *fill* 0x00000000200015d8 0x200 - 0x0000000020001bd8 . = (. + _Min_Stack_Size) - *fill* 0x00000000200017d8 0x400 - 0x0000000020001bd8 . = ALIGN (0x8) + 0x0000000020002390 PROVIDE (_end = .) + 0x0000000020002590 . = (. + _Min_Heap_Size) + *fill* 0x0000000020002390 0x200 + 0x0000000020002990 . = (. + _Min_Stack_Size) + *fill* 0x0000000020002590 0x400 + 0x0000000020002990 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -7915,251 +9537,273 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .ARM.attributes 0x000000000000001e 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o .ARM.attributes - 0x0000000000000052 0x34 ./Core/Src/main.o + 0x0000000000000052 0x34 ./Core/Src/adc.o + .ARM.attributes + 0x0000000000000086 0x34 ./Core/Src/dma.o + .ARM.attributes + 0x00000000000000ba 0x34 ./Core/Src/gpio.o + .ARM.attributes + 0x00000000000000ee 0x34 ./Core/Src/i2c.o .ARM.attributes - 0x0000000000000086 0x34 ./Core/Src/nmea_parse.o + 0x0000000000000122 0x34 ./Core/Src/main.o .ARM.attributes - 0x00000000000000ba 0x34 ./Core/Src/ssd1306.o + 0x0000000000000156 0x34 ./Core/Src/nmea_parse.o .ARM.attributes - 0x00000000000000ee 0x34 ./Core/Src/ssd1306_fonts.o + 0x000000000000018a 0x34 ./Core/Src/spi.o .ARM.attributes - 0x0000000000000122 0x34 ./Core/Src/statemachine.o + 0x00000000000001be 0x34 ./Core/Src/ssd1306.o .ARM.attributes - 0x0000000000000156 0x34 ./Core/Src/stm32l4xx_hal_msp.o + 0x00000000000001f2 0x34 ./Core/Src/ssd1306_fonts.o .ARM.attributes - 0x000000000000018a 0x34 ./Core/Src/stm32l4xx_it.o + 0x0000000000000226 0x34 ./Core/Src/statemachine.o .ARM.attributes - 0x00000000000001be 0x34 ./Core/Src/syscalls.o + 0x000000000000025a 0x34 ./Core/Src/stm32l4xx_hal_msp.o .ARM.attributes - 0x00000000000001f2 0x34 ./Core/Src/sysmem.o + 0x000000000000028e 0x34 ./Core/Src/stm32l4xx_it.o .ARM.attributes - 0x0000000000000226 0x34 ./Core/Src/system_stm32l4xx.o + 0x00000000000002c2 0x34 ./Core/Src/syscalls.o .ARM.attributes - 0x000000000000025a 0x21 ./Core/Startup/startup_stm32l432kcux.o + 0x00000000000002f6 0x34 ./Core/Src/sysmem.o .ARM.attributes - 0x000000000000027b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o + 0x000000000000032a 0x34 ./Core/Src/system_stm32l4xx.o .ARM.attributes - 0x00000000000002af 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o + 0x000000000000035e 0x34 ./Core/Src/tim.o .ARM.attributes - 0x00000000000002e3 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o + 0x0000000000000392 0x34 ./Core/Src/usart.o .ARM.attributes - 0x0000000000000317 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o + 0x00000000000003c6 0x21 ./Core/Startup/startup_stm32l432kcux.o .ARM.attributes - 0x000000000000034b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o + 0x00000000000003e7 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .ARM.attributes - 0x000000000000037f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o + 0x000000000000041b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .ARM.attributes - 0x00000000000003b3 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o + 0x000000000000044f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o .ARM.attributes - 0x00000000000003e7 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o + 0x0000000000000483 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o .ARM.attributes - 0x000000000000041b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o + 0x00000000000004b7 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o .ARM.attributes - 0x000000000000044f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o + 0x00000000000004eb 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o .ARM.attributes - 0x0000000000000483 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o + 0x000000000000051f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o .ARM.attributes - 0x00000000000004b7 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o + 0x0000000000000553 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o .ARM.attributes - 0x00000000000004eb 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + 0x0000000000000587 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.o .ARM.attributes - 0x000000000000051f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o + 0x00000000000005bb 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.o .ARM.attributes - 0x0000000000000553 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o + 0x00000000000005ef 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .ARM.attributes - 0x0000000000000587 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o + 0x0000000000000623 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .ARM.attributes - 0x00000000000005bb 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o + 0x0000000000000657 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o .ARM.attributes - 0x00000000000005ef 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o + 0x000000000000068b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o .ARM.attributes - 0x0000000000000623 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + 0x00000000000006bf 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .ARM.attributes - 0x0000000000000657 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o + 0x00000000000006f3 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .ARM.attributes - 0x000000000000068b 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o + 0x0000000000000727 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .ARM.attributes - 0x00000000000006bf 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + 0x000000000000075b 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .ARM.attributes - 0x00000000000006f3 0x34 ./USB_DEVICE/App/usb_device.o + 0x000000000000078f 0x34 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o .ARM.attributes - 0x0000000000000727 0x34 ./USB_DEVICE/App/usbd_desc.o + 0x00000000000007c3 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o .ARM.attributes - 0x000000000000075b 0x34 ./USB_DEVICE/Target/usbd_conf.o + 0x00000000000007f7 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .ARM.attributes - 0x000000000000078f 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o) + 0x000000000000082b 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .ARM.attributes - 0x00000000000007c3 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) + 0x000000000000085f 0x34 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o .ARM.attributes - 0x00000000000007f7 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o) + 0x0000000000000893 0x34 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o .ARM.attributes - 0x000000000000082b 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtod.o) + 0x00000000000008c7 0x34 ./USB_DEVICE/App/usb_device.o .ARM.attributes - 0x000000000000085f 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strtol.o) + 0x00000000000008fb 0x34 ./USB_DEVICE/App/usbd_cdc_if.o .ARM.attributes - 0x0000000000000893 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-ctype_.o) + 0x000000000000092f 0x34 ./USB_DEVICE/App/usbd_desc.o .ARM.attributes - 0x00000000000008c7 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_float.o) 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C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_muldivdf3.o) .ARM.attributes - 0x00000000000017ba 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) + 0x00000000000018da 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_arm_cmpdf2.o) .ARM.attributes - 0x00000000000017ee 0x1e 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C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_fixdfdi.o) + .ARM.attributes + 0x00000000000019c2 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_fixunsdfdi.o) + .ARM.attributes + 0x00000000000019f6 0x34 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000001a2a 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000001a48 0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o OUTPUT(projet vf.elf elf32-littlearm) LOAD linker stubs LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc.a @@ -8169,8 +9813,13 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000000 0x43 .comment 0x0000000000000000 0x43 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o 0x44 (size before relaxing) + .comment 0x0000000000000043 0x44 ./Core/Src/adc.o + .comment 0x0000000000000043 0x44 ./Core/Src/dma.o + .comment 0x0000000000000043 0x44 ./Core/Src/gpio.o + .comment 0x0000000000000043 0x44 ./Core/Src/i2c.o .comment 0x0000000000000043 0x44 ./Core/Src/main.o .comment 0x0000000000000043 0x44 ./Core/Src/nmea_parse.o + .comment 0x0000000000000043 0x44 ./Core/Src/spi.o .comment 0x0000000000000043 0x44 ./Core/Src/ssd1306.o .comment 0x0000000000000043 0x44 ./Core/Src/ssd1306_fonts.o .comment 0x0000000000000043 0x44 ./Core/Src/statemachine.o @@ -8179,6 +9828,8 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000043 0x44 ./Core/Src/syscalls.o .comment 0x0000000000000043 0x44 ./Core/Src/sysmem.o .comment 0x0000000000000043 0x44 ./Core/Src/system_stm32l4xx.o + .comment 0x0000000000000043 0x44 ./Core/Src/tim.o + .comment 0x0000000000000043 0x44 ./Core/Src/usart.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.o @@ -8192,621 +9843,740 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o + .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o .comment 0x0000000000000043 0x44 ./Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.o - .comment 0x0000000000000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.o + .comment 0x0000000000000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.o .comment 0x0000000000000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.o .comment 0x0000000000000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.o .comment 0x0000000000000043 0x44 ./Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.o + .comment 0x0000000000000043 0x44 ./Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.o .comment 0x0000000000000043 0x44 ./USB_DEVICE/App/usb_device.o + .comment 0x0000000000000043 0x44 ./USB_DEVICE/App/usbd_cdc_if.o .comment 0x0000000000000043 0x44 ./USB_DEVICE/App/usbd_desc.o .comment 0x0000000000000043 0x44 ./USB_DEVICE/Target/usbd_conf.o -.debug_info 0x0000000000000000 0x24753 - .debug_info 0x0000000000000000 0x2440 ./Core/Src/main.o - .debug_info 0x0000000000002440 0x747 ./Core/Src/nmea_parse.o - .debug_info 0x0000000000002b87 0x12c4 ./Core/Src/ssd1306.o - .debug_info 0x0000000000003e4b 0x19d ./Core/Src/ssd1306_fonts.o - .debug_info 0x0000000000003fe8 0xfc4 ./Core/Src/statemachine.o - .debug_info 0x0000000000004fac 0x1ad3 ./Core/Src/stm32l4xx_hal_msp.o - .debug_info 0x0000000000006a7f 0x1559 ./Core/Src/stm32l4xx_it.o - .debug_info 0x0000000000007fd8 0x6a3 ./Core/Src/syscalls.o - .debug_info 0x000000000000867b 0x168 ./Core/Src/sysmem.o - .debug_info 0x00000000000087e3 0x5bf ./Core/Src/system_stm32l4xx.o - .debug_info 0x0000000000008da2 0x23 ./Core/Startup/startup_stm32l432kcux.o - .debug_info 0x0000000000008dc5 0x99e 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./Core/Startup/startup_stm32l432kcux.o + 0x90 (size before relaxing) diff --git a/Software/stm32project/Debug/sources.mk b/Software/stm32project/Debug/sources.mk index 19bead6..d9dd27c 100644 --- a/Software/stm32project/Debug/sources.mk +++ b/Software/stm32project/Debug/sources.mk @@ -25,8 +25,9 @@ SUBDIRS := \ Core/Src \ Core/Startup \ Drivers/STM32L4xx_HAL_Driver/Src \ -Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src \ +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src \ Middlewares/ST/STM32_USB_Device_Library/Core/Src \ +Middlewares/Third_Party/NimaLTD_Driver/SPIF \ USB_DEVICE/App \ USB_DEVICE/Target \ diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h similarity index 83% rename from Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h rename to Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h index d7997a3..a7b6b2a 100644 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h +++ b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h @@ -1,12 +1,12 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_spi.h + * @file stm32l4xx_hal_spi.h * @author MCD Application Team * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - * Copyright (c) 2016 STMicroelectronics. + * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -17,17 +17,17 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F4xx_HAL_SPI_H -#define STM32F4xx_HAL_SPI_H +#ifndef STM32L4xx_HAL_SPI_H +#define STM32L4xx_HAL_SPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal_def.h" +#include "stm32l4xx_hal_def.h" -/** @addtogroup STM32F4xx_HAL_Driver +/** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -81,6 +81,17 @@ typedef struct uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + CPOL setting is ignored).. */ } SPI_InitTypeDef; /** @@ -119,6 +130,8 @@ typedef struct __SPI_HandleTypeDef __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ @@ -191,7 +204,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ @@ -222,8 +235,19 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to /** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_8BIT (0x00000000U) -#define SPI_DATASIZE_16BIT SPI_CR1_DFF +#define SPI_DATASIZE_4BIT (0x00000300U) +#define SPI_DATASIZE_5BIT (0x00000400U) +#define SPI_DATASIZE_6BIT (0x00000500U) +#define SPI_DATASIZE_7BIT (0x00000600U) +#define SPI_DATASIZE_8BIT (0x00000700U) +#define SPI_DATASIZE_9BIT (0x00000800U) +#define SPI_DATASIZE_10BIT (0x00000900U) +#define SPI_DATASIZE_11BIT (0x00000A00U) +#define SPI_DATASIZE_12BIT (0x00000B00U) +#define SPI_DATASIZE_13BIT (0x00000C00U) +#define SPI_DATASIZE_14BIT (0x00000D00U) +#define SPI_DATASIZE_15BIT (0x00000E00U) +#define SPI_DATASIZE_16BIT (0x00000F00U) /** * @} */ @@ -256,6 +280,15 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @} */ +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLE (0x00000000U) +/** + * @} + */ + /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ @@ -298,6 +331,35 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @} */ +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + * This parameter can be one of the following values: + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_8BIT : CRC 8bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) +#define SPI_CRC_LENGTH_8BIT (0x00000001U) +#define SPI_CRC_LENGTH_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold + * @{ + * This parameter can be one of the following values: + * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : + * RXNE event is generated if the FIFO + * level is greater or equal to 1/4(8-bits). + * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16 bits). */ +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) +/** + * @} + */ + /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition * @{ */ @@ -318,8 +380,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ - | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +/** + * @} + */ + +/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level + * @{ + */ +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) /** * @} */ @@ -397,6 +484,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_OVR: Overrun flag * @arg SPI_FLAG_BSY: Busy flag * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -502,6 +591,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_OVR: Overrun flag * @arg SPI_FLAG_BSY: Busy flag * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ @@ -555,7 +646,18 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. * @param __CPOL__ specifies the SPI serial clock steady state. @@ -582,6 +684,14 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to ((__NSS__) == SPI_NSS_HARD_INPUT) || \ ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) + /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. * This parameter can be a value of @ref SPI_BaudRate_Prescaler @@ -620,6 +730,15 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) + /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 @@ -639,6 +758,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @} */ +/* Include SPI HAL Extended module */ +#include "stm32l4xx_hal_spi_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPI_Exported_Functions * @{ @@ -725,5 +847,5 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); } #endif -#endif /* STM32F4xx_HAL_SPI_H */ +#endif /* STM32L4xx_HAL_SPI_H */ diff --git a/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h new file mode 100644 index 0000000..359d30e --- /dev/null +++ b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_HAL_SPI_EX_H +#define STM32L4xx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_HAL_SPI_EX_H */ + diff --git a/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h new file mode 100644 index 0000000..d377cca --- /dev/null +++ b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h @@ -0,0 +1,1418 @@ +/** + ****************************************************************************** + * @file stm32l4xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L4xx_LL_SPI_H +#define STM32L4xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx.h" + +/** @addtogroup STM32L4xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ +#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ +#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ +#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ +#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ +#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ +#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ +#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ +#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ +#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ +#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + * @{ + */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ +#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + * @{ + */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + * @{ + */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ +#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ +#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + * @{ + */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ +#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ +#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + * @{ + */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set serial protocol used + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR2 DS LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR2 DS LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); +} + +/** + * @brief Set threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); +} + +/** + * @brief Get threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @brief Enable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); +} + +/** + * @brief Get FIFO reception Level + * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_EMPTY + * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + * @arg @ref LL_SPI_RX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); +} + +/** + * @brief Get FIFO Transmission Level + * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TX_FIFO_EMPTY + * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_TX_FIFO_HALF_FULL + * @arg @ref LL_SPI_TX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +} + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set parity of Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +} + +/** + * @brief Set parity of Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L4xx_LL_SPI_H */ + diff --git a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c similarity index 82% rename from Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c rename to Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c index 62d5d65..5c5efd6 100644 --- a/Software/Flapy Bird/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_spi.c + * @file stm32l4xx_hal_spi.c * @author MCD Application Team * @brief SPI HAL module driver. * This file provides firmware functions to manage the following @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2016 STMicroelectronics. + * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -144,23 +144,23 @@ | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| - | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| - | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| - | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+ DataSize = SPI_DATASIZE_16BIT: @@ -169,25 +169,25 @@ | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| - | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | | R |----------------|----------|----------|-----------|----------|-----------|----------| | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| - | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | | |----------------|----------|----------|-----------|----------|-----------|----------| - | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | +----------------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (8bits, 16bits), + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() @@ -197,9 +197,9 @@ */ /* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" +#include "stm32l4xx_hal.h" -/** @addtogroup STM32F4xx_HAL_Driver +/** @addtogroup STM32L4xx_HAL_Driver * @{ */ @@ -215,7 +215,6 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100U -#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */ /** * @} */ @@ -238,6 +237,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); @@ -293,6 +294,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ (++) TIMode (++) CRC Calculation (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold (+) Call the function HAL_SPI_DeInit() to restore the default configuration of the selected SPIx peripheral. @@ -310,6 +313,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { + uint32_t frxth; + /* Check the SPI handle allocation */ if (hspi == NULL) { @@ -322,6 +327,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); @@ -353,6 +359,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; @@ -392,21 +399,66 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + } + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ - /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | - (hspi->Init.DataSize & SPI_CR1_DFF) | (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | (hspi->Init.CLKPhase & SPI_CR1_CPHA) | (hspi->Init.NSS & SPI_CR1_SSM) | (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } + } +#endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); #if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ @@ -832,7 +884,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } /* Transmit data in 16 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { @@ -856,6 +908,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -866,18 +919,38 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; + hspi->TxXferCount--; + } } while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } } else { @@ -885,6 +958,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -914,9 +988,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -935,10 +1012,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -952,12 +1037,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -988,6 +1067,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { @@ -1004,7 +1095,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Receive data in 8 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { /* Transfer loop */ while (hspi->RxXferCount > 0U) @@ -1023,6 +1114,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1046,6 +1138,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1068,7 +1161,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Receive last data in 16 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; } @@ -1087,9 +1180,37 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Read CRC to Flush DR and RXNE flag */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } } #endif /* USE_SPI_CRC */ @@ -1112,9 +1233,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1133,11 +1257,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t Timeout) { uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; + uint32_t spi_cr1; + uint32_t spi_cr2; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ @@ -1157,6 +1286,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) @@ -1198,6 +1332,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } #endif /* USE_SPI_CRC */ + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1206,13 +1352,27 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Transmit and Receive data in 16 Bit mode */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { @@ -1229,6 +1389,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Enable CRC Transmission */ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ @@ -1246,6 +1411,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1255,18 +1421,49 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; @@ -1274,6 +1471,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Enable CRC Transmission */ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ @@ -1282,15 +1484,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { - (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr++; - hspi->RxXferCount--; + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1309,9 +1526,37 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read CRC */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } } /* Check if CRC error occurred */ @@ -1330,17 +1575,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - goto error; } - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - __HAL_SPI_CLEAR_OVRFLAG(hspi); + errorcode = HAL_ERROR; } - + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1360,8 +1606,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1375,6 +1619,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1414,10 +1661,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1425,8 +1668,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1442,6 +1689,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1449,14 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1464,6 +1710,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1477,13 +1726,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->TxXferCount = 0U; hspi->TxISR = NULL; - /* Set the function for IT treatment */ + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1499,13 +1752,19 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } SPI_RESET_CRC(hspi); } + else + { + hspi->CRCSize = 0U; + } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1517,9 +1776,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1541,9 +1803,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1561,6 +1820,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1592,12 +1854,31 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } SPI_RESET_CRC(hspi); } + else + { + hspi->CRCSize = 0U; + } #endif /* USE_SPI_CRC */ - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + /* Check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1606,9 +1887,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1687,15 +1971,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the DMA AbortCpltCallback */ hspi->hdmatx->XferAbortCallback = NULL; - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, - hspi->TxXferCount)) + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + /* Packing mode is enabled only if the DMA setting is HALWORD */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Check the even/odd of the data size + crc if enabled */ + if ((hspi->TxXferCount & 0x1U) == 0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1735,6 +2035,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1749,12 +2055,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1790,6 +2090,36 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + /* Set the SPI RxDMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; @@ -1810,7 +2140,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1904,6 +2233,52 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif /* USE_SPI_CRC */ + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + + /* The packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if ((hspi->TxXferSize & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ if (hspi->State == HAL_SPI_STATE_BUSY_RX) { @@ -1932,7 +2307,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1954,7 +2328,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -2057,16 +2430,19 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); - /* Wait until TXE flag is set */ - do + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } } } @@ -2089,6 +2465,18 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* Disable peripheral */ __HAL_SPI_DISABLE(hspi); + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + /* Disable Rx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); } @@ -2677,7 +3065,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) tickstart = HAL_GetTick(); /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); @@ -2731,13 +3119,15 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); @@ -2753,9 +3143,35 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } } #endif /* USE_SPI_CRC */ @@ -2820,13 +3236,15 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); @@ -2835,15 +3253,33 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* CRC handling */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait the CRC data */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + else + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } - /* Read CRC to Flush DR and RXNE flag */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ @@ -2996,24 +3432,25 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - __IO uint32_t count; hspi->hdmatx->XferAbortCallback = NULL; - count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - /* Wait until TXE flag is set */ - do + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } /* Check if an Abort process is still ongoing */ if (hspi->hdmarx != NULL) @@ -3070,10 +3507,16 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Disable Rx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - /* Check Busy flag */ - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } /* Check if an Abort process is still ongoing */ @@ -3119,10 +3562,25 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - /* Receive data in 8bit mode */ - *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); - hspi->pRxBuffPtr++; - hspi->RxXferCount--; + /* Receive data in packing mode */ + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + /* Receive data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } /* Check end of the reception */ if (hspi->RxXferCount == 0U) @@ -3130,6 +3588,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_2linesRxISR_8BITCRC; return; } @@ -3164,12 +3623,18 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /* To avoid GCC warning */ UNUSED(tmpreg8); - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + hspi->CRCSize--; - if (hspi->TxXferCount == 0U) + /* Check end of the reception */ + if (hspi->CRCSize == 0U) { - SPI_CloseRxTx_ISR(hspi); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } } } #endif /* USE_SPI_CRC */ @@ -3182,9 +3647,20 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; + /* Transmit data in packing Bit mode */ + if (hspi->TxXferCount >= 2U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + /* Transmit data in 8 Bit mode */ + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) @@ -3322,7 +3798,12 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /* To avoid GCC warning */ UNUSED(tmpreg8); - SPI_CloseRx_ISR(hspi); + hspi->CRCSize--; + + if (hspi->CRCSize == 0U) + { + SPI_CloseRx_ISR(hspi); + } } #endif /* USE_SPI_CRC */ @@ -3535,6 +4016,88 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_OK; } +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + /** * @brief Handle the check of the RX transaction complete. * @param hspi pointer to a SPI_HandleTypeDef structure that contains @@ -3552,32 +4115,18 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t __HAL_SPI_DISABLE(hspi); } - /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ - if (hspi->Init.Mode == SPI_MODE_MASTER) + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY) - { - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - } - else - { - /* Wait the RXNE reset */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - } + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; } - else + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { - /* Wait the RXNE reset */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; @@ -3595,33 +4144,25 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - /* Timeout in µs */ - __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); - /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ - if (hspi->Init.Mode == SPI_MODE_MASTER) + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; } - else + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer - * If Timeout is reached, the transfer is considered as finish. - * User have to calculate the timeout value to fit with the time of 1 byte transfer. - * This time is directly link with the SPI clock from Master device. - */ - do - { - if (count == 0U) - { - break; - } - count--; - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; } return HAL_OK; @@ -3636,7 +4177,6 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -3644,29 +4184,12 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - /* Wait until TXE flag is set */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - break; - } - count--; - } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); - /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - #if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) @@ -3738,12 +4261,6 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } hspi->State = HAL_SPI_STATE_READY; #if (USE_SPI_CRC != 0U) @@ -3794,22 +4311,10 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - /* Wait until TXE flag is set */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - break; - } - count--; - } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); - /* Disable TXE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); @@ -3854,10 +4359,17 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { - __IO uint32_t tmpreg = 0U; - __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + __IO uint32_t count; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Wait until TXE flag is set */ + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ do { if (count == 0U) @@ -3866,18 +4378,19 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) break; } count--; - } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } - /* Flush Data Register by a blank read */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } hspi->State = HAL_SPI_STATE_ABORT; } @@ -3890,12 +4403,67 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Disable TXEIE interrupt */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + /* Check TXEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } hspi->State = HAL_SPI_STATE_ABORT; } diff --git a/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c new file mode 100644 index 0000000..ad50589 --- /dev/null +++ b/Software/stm32project/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPIEx_Private_Constants SPIEx Private Constants + * @{ + */ +#define SPI_FIFO_SIZE 4UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) Rx data flush function: + (++) HAL_SPIEx_FlushRxFifo() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg; + uint8_t count = 0U; + while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + { + count++; + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + if (count == SPI_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Software/stm32project/I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h b/Software/stm32project/I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h new file mode 100644 index 0000000..616c16d --- /dev/null +++ b/Software/stm32project/I-CUBE-SPIF/NimaLTD.I-CUBE-SPIF_conf.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * File Name : NimaLTD.I-CUBE-SPIF_conf.h + * Description : This file provides code for the configuration + * of the NimaLTD.I-CUBE-SPIF_conf.h instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _NIMALTD_I_CUBE_SPIF_CONF_H_ +#define _NIMALTD_I_CUBE_SPIF_CONF_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define SPIF_DEBUG_DISABLE 0 +#define SPIF_DEBUG_MIN 1 +#define SPIF_DEBUG_FULL 2 + +#define SPIF_PLATFORM_HAL 0 +#define SPIF_PLATFORM_HAL_DMA 1 + +#define SPIF_RTOS_DISABLE 0 +#define SPIF_RTOS_CMSIS_V1 1 +#define SPIF_RTOS_CMSIS_V2 2 +#define SPIF_RTOS_THREADX 3 + +/** + MiddleWare name : NimaLTD.I-CUBE-SPIF.2.3.2 + MiddleWare fileName : ./NimaLTD.I-CUBE-SPIF_conf.h +*/ +/*---------- SPIF_DEBUG -----------*/ +#define SPIF_DEBUG SPIF_DEBUG_DISABLE + +/*---------- SPIF_PLATFORM -----------*/ +#define SPIF_PLATFORM SPIF_PLATFORM_HAL + +/*---------- SPIF_RTOS -----------*/ +#define SPIF_RTOS SPIF_RTOS_DISABLE + +#ifdef __cplusplus +} +#endif +#endif /* _NIMALTD_I_CUBE_SPIF_CONF_H_ */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h new file mode 100644 index 0000000..aeac6bf --- /dev/null +++ b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -0,0 +1,184 @@ +/** + ****************************************************************************** + * @file usbd_cdc.h + * @author MCD Application Team + * @brief header file for the usbd_cdc.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc + * @brief This file is the Header file for usbd_cdc.c + * @{ + */ + + +/** @defgroup usbd_cdc_Exported_Defines + * @{ + */ +#ifndef CDC_IN_EP +#define CDC_IN_EP 0x81U /* EP1 for data IN */ +#endif /* CDC_IN_EP */ +#ifndef CDC_OUT_EP +#define CDC_OUT_EP 0x01U /* EP1 for data OUT */ +#endif /* CDC_OUT_EP */ +#ifndef CDC_CMD_EP +#define CDC_CMD_EP 0x82U /* EP2 for CDC commands */ +#endif /* CDC_CMD_EP */ + +#ifndef CDC_HS_BINTERVAL +#define CDC_HS_BINTERVAL 0x10U +#endif /* CDC_HS_BINTERVAL */ + +#ifndef CDC_FS_BINTERVAL +#define CDC_FS_BINTERVAL 0x10U +#endif /* CDC_FS_BINTERVAL */ + +/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_DATA_HS_MAX_PACKET_SIZE 512U /* Endpoint IN & OUT Packet size */ +#define CDC_DATA_FS_MAX_PACKET_SIZE 64U /* Endpoint IN & OUT Packet size */ +#define CDC_CMD_PACKET_SIZE 8U /* Control Endpoint Packet size */ + +#define USB_CDC_CONFIG_DESC_SIZ 67U +#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE +#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE + +#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE +#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE + +#define CDC_REQ_MAX_DATA_SIZE 0x7U +/*---------------------------------------------------------------------*/ +/* CDC definitions */ +/*---------------------------------------------------------------------*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00U +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01U +#define CDC_SET_COMM_FEATURE 0x02U +#define CDC_GET_COMM_FEATURE 0x03U +#define CDC_CLEAR_COMM_FEATURE 0x04U +#define CDC_SET_LINE_CODING 0x20U +#define CDC_GET_LINE_CODING 0x21U +#define CDC_SET_CONTROL_LINE_STATE 0x22U +#define CDC_SEND_BREAK 0x23U + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ +typedef struct +{ + uint32_t bitrate; + uint8_t format; + uint8_t paritytype; + uint8_t datatype; +} USBD_CDC_LineCodingTypeDef; + +typedef struct _USBD_CDC_Itf +{ + int8_t (* Init)(void); + int8_t (* DeInit)(void); + int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); + int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); + int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum); +} USBD_CDC_ItfTypeDef; + + +typedef struct +{ + uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE / 4U]; /* Force 32-bit alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; +} USBD_CDC_HandleTypeDef; + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); + +#ifdef USE_USBD_COMPOSITE +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, + uint32_t length, uint8_t ClassId); +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId); +#else +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, + uint32_t length); +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev); +#endif /* USE_USBD_COMPOSITE */ +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff); +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_H */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c new file mode 100644 index 0000000..ad8da25 --- /dev/null +++ b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -0,0 +1,893 @@ +/** + ****************************************************************************** + * @file usbd_cdc.c + * @author MCD Application Team + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * @verbatim + * + * =================================================================== + * CDC Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + */ + +/* BSPDependencies +- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" +- "stm32xxxxx_{eval}{discovery}_io.c" +EndBSPDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_Private_FunctionPrototypes + * @{ + */ + +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); +#ifndef USE_USBD_COMPOSITE +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length); +#endif /* USE_USBD_COMPOSITE */ + +#ifndef USE_USBD_COMPOSITE +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; +#endif /* USE_USBD_COMPOSITE */ +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Variables + * @{ + */ + + +/* CDC interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, +#ifdef USE_USBD_COMPOSITE + NULL, + NULL, + NULL, + NULL, +#else + USBD_CDC_GetHSCfgDesc, + USBD_CDC_GetFSCfgDesc, + USBD_CDC_GetOtherSpeedCfgDesc, + USBD_CDC_GetDeviceQualifierDescriptor, +#endif /* USE_USBD_COMPOSITE */ +}; + +#ifndef USE_USBD_COMPOSITE +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength */ + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor + describing the configuration */ +#if (USBD_SELF_POWERED == 1U) + 0xC0, /* bmAttributes: Bus Powered according to user configuration */ +#else + 0x80, /* bmAttributes: Bus Powered according to user configuration */ +#endif /* USBD_SELF_POWERED */ + USBD_MAX_POWER, /* MaxPower (mA) */ + + /*---------------------------------------------------------------------------*/ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(CDC_CMD_PACKET_SIZE), + CDC_FS_BINTERVAL, /* bInterval */ + /*---------------------------------------------------------------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00, /* bInterval */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), + 0x00 /* bInterval */ +}; +#endif /* USE_USBD_COMPOSITE */ + +static uint8_t CDCInEpAdd = CDC_IN_EP; +static uint8_t CDCOutEpAdd = CDC_OUT_EP; +static uint8_t CDCCmdEpAdd = CDC_CMD_EP; + +/** + * @} + */ + +/** @defgroup USBD_CDC_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_Init + * Initialize the CDC interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + USBD_CDC_HandleTypeDef *hcdc; + + hcdc = (USBD_CDC_HandleTypeDef *)USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + + if (hcdc == NULL) + { + pdev->pClassDataCmsit[pdev->classId] = NULL; + return (uint8_t)USBD_EMEM; + } + + (void)USBD_memset(hcdc, 0, sizeof(USBD_CDC_HandleTypeDef)); + + pdev->pClassDataCmsit[pdev->classId] = (void *)hcdc; + pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; + + /* Set bInterval for CDC CMD Endpoint */ + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_HS_BINTERVAL; + } + else + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDCInEpAdd, USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDCOutEpAdd, USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 1U; + + /* Set bInterval for CMD Endpoint */ + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = CDC_FS_BINTERVAL; + } + + /* Open Command IN EP */ + (void)USBD_LL_OpenEP(pdev, CDCCmdEpAdd, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 1U; + + hcdc->RxBuffer = NULL; + + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Init(); + + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; + + if (hcdc->RxBuffer == NULL) + { + return (uint8_t)USBD_EMEM; + } + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_Init + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this CDC class instance */ + CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); + CDCCmdEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + /* Close EP IN */ + (void)USBD_LL_CloseEP(pdev, CDCInEpAdd); + pdev->ep_in[CDCInEpAdd & 0xFU].is_used = 0U; + + /* Close EP OUT */ + (void)USBD_LL_CloseEP(pdev, CDCOutEpAdd); + pdev->ep_out[CDCOutEpAdd & 0xFU].is_used = 0U; + + /* Close Command IN EP */ + (void)USBD_LL_CloseEP(pdev, CDCCmdEpAdd); + pdev->ep_in[CDCCmdEpAdd & 0xFU].is_used = 0U; + pdev->ep_in[CDCCmdEpAdd & 0xFU].bInterval = 0U; + + /* DeInit physical Interface components */ + if (pdev->pClassDataCmsit[pdev->classId] != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->DeInit(); + (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); + pdev->pClassDataCmsit[pdev->classId] = NULL; + pdev->pClassData = NULL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + uint16_t len; + uint8_t ifalt = 0U; + uint16_t status_info = 0U; + USBD_StatusTypeDef ret = USBD_OK; + + if (hcdc == NULL) + { + return (uint8_t)USBD_FAIL; + } + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + if (req->wLength != 0U) + { + if ((req->bmRequest & 0x80U) != 0U) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + + len = MIN(CDC_REQ_MAX_DATA_SIZE, req->wLength); + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, len); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)MIN(req->wLength, USB_MAX_EP0_SIZE); + + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, hcdc->CmdLength); + } + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(req->bRequest, + (uint8_t *)req, 0U); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, &ifalt, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return (uint8_t)ret; +} + +/** + * @brief USBD_CDC_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc; + PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef *)pdev->pData; + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + + if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && + ((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U)) + { + /* Update the packet total length */ + pdev->ep_in[epnum & 0xFU].total_length = 0U; + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); + } + else + { + hcdc->TxState = 0U; + + if (((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt != NULL) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); + } + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + { + return (uint8_t)USBD_FAIL; + } + + /* Get the received data length */ + hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_EP0_RxReady + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + + if (hcdc == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if ((pdev->pUserData[pdev->classId] != NULL) && (hcdc->CmdOpCode != 0xFFU)) + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData[pdev->classId])->Control(hcdc->CmdOpCode, + (uint8_t *)hcdc->data, + (uint16_t)hcdc->CmdLength); + hcdc->CmdOpCode = 0xFFU; + } + + return (uint8_t)USBD_OK; +} +#ifndef USE_USBD_COMPOSITE +/** + * @brief USBD_CDC_GetFSCfgDesc + * Return configuration descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + + if (pEpCmdDesc != NULL) + { + pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; + } + + if (pEpOutDesc != NULL) + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + } + + if (pEpInDesc != NULL) + { + pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; +} + +/** + * @brief USBD_CDC_GetHSCfgDesc + * Return configuration descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + + if (pEpCmdDesc != NULL) + { + pEpCmdDesc->bInterval = CDC_HS_BINTERVAL; + } + + if (pEpOutDesc != NULL) + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; + } + + if (pEpInDesc != NULL) + { + pEpInDesc->wMaxPacketSize = CDC_DATA_HS_MAX_PACKET_SIZE; + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; +} + +/** + * @brief USBD_CDC_GetOtherSpeedCfgDesc + * Return configuration descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) +{ + USBD_EpDescTypeDef *pEpCmdDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_CMD_EP); + USBD_EpDescTypeDef *pEpOutDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_OUT_EP); + USBD_EpDescTypeDef *pEpInDesc = USBD_GetEpDesc(USBD_CDC_CfgDesc, CDC_IN_EP); + + if (pEpCmdDesc != NULL) + { + pEpCmdDesc->bInterval = CDC_FS_BINTERVAL; + } + + if (pEpOutDesc != NULL) + { + pEpOutDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + } + + if (pEpInDesc != NULL) + { + pEpInDesc->wMaxPacketSize = CDC_DATA_FS_MAX_PACKET_SIZE; + } + + *length = (uint16_t)sizeof(USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; +} + +/** + * @brief USBD_CDC_GetDeviceQualifierDescriptor + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); + + return USBD_CDC_DeviceQualifierDesc; +} +#endif /* USE_USBD_COMPOSITE */ +/** + * @brief USBD_CDC_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) +{ + if (fops == NULL) + { + return (uint8_t)USBD_FAIL; + } + + pdev->pUserData[pdev->classId] = fops; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @param length: length of data to be sent + * @param ClassId: The Class ID + * @retval status + */ +#ifdef USE_USBD_COMPOSITE +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, uint32_t length, uint8_t ClassId) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; +#else +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, uint32_t length) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; +#endif /* USE_USBD_COMPOSITE */ + + if (hcdc == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + + if (hcdc == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc->RxBuffer = pbuff; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_TransmitPacket + * Transmit packet on IN endpoint + * @param pdev: device instance + * @param ClassId: The Class ID + * @retval status + */ +#ifdef USE_USBD_COMPOSITE +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t ClassId) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; +#else +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; +#endif /* USE_USBD_COMPOSITE */ + + USBD_StatusTypeDef ret = USBD_BUSY; + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + CDCInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_BULK, ClassId); +#endif /* USE_USBD_COMPOSITE */ + + if (hcdc == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if (hcdc->TxState == 0U) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; + + /* Update the packet total length */ + pdev->ep_in[CDCInEpAdd & 0xFU].total_length = hcdc->TxLength; + + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDCInEpAdd, hcdc->TxBuffer, hcdc->TxLength); + + ret = USBD_OK; + } + + return (uint8_t)ret; +} + +/** + * @brief USBD_CDC_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; + +#ifdef USE_USBD_COMPOSITE + /* Get the Endpoints addresses allocated for this class instance */ + CDCOutEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_OUT, USBD_EP_TYPE_BULK, (uint8_t)pdev->classId); +#endif /* USE_USBD_COMPOSITE */ + + if (pdev->pClassDataCmsit[pdev->classId] == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } + else + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDCOutEpAdd, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); + } + + return (uint8_t)USBD_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h deleted file mode 100644 index 8b22a8d..0000000 --- a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_hid.h - * @author MCD Application Team - * @brief Header file for the usbd_hid_core.c file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2015 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_HID_H -#define __USB_HID_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_HID - * @brief This file is the Header file for usbd_hid.c - * @{ - */ - - -/** @defgroup USBD_HID_Exported_Defines - * @{ - */ -#ifndef HID_EPIN_ADDR -#define HID_EPIN_ADDR 0x81U -#endif /* HID_EPIN_ADDR */ -#define HID_EPIN_SIZE 0x04U - -#define USB_HID_CONFIG_DESC_SIZ 34U -#define USB_HID_DESC_SIZ 9U -#define HID_MOUSE_REPORT_DESC_SIZE 74U - -#define HID_DESCRIPTOR_TYPE 0x21U -#define HID_REPORT_DESC 0x22U - -#ifndef HID_HS_BINTERVAL -#define HID_HS_BINTERVAL 0x07U -#endif /* HID_HS_BINTERVAL */ - -#ifndef HID_FS_BINTERVAL -#define HID_FS_BINTERVAL 0x0AU -#endif /* HID_FS_BINTERVAL */ - -#define USBD_HID_REQ_SET_PROTOCOL 0x0BU -#define USBD_HID_REQ_GET_PROTOCOL 0x03U - -#define USBD_HID_REQ_SET_IDLE 0x0AU -#define USBD_HID_REQ_GET_IDLE 0x02U - -#define USBD_HID_REQ_SET_REPORT 0x09U -#define USBD_HID_REQ_GET_REPORT 0x01U -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef enum -{ - USBD_HID_IDLE = 0, - USBD_HID_BUSY, -} USBD_HID_StateTypeDef; - - -typedef struct -{ - uint32_t Protocol; - uint32_t IdleState; - uint32_t AltSetting; - USBD_HID_StateTypeDef state; -} USBD_HID_HandleTypeDef; - -/* - * HID Class specification version 1.1 - * 6.2.1 HID Descriptor - */ - -typedef struct -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdHID; - uint8_t bCountryCode; - uint8_t bNumDescriptors; - uint8_t bHIDDescriptorType; - uint16_t wItemLength; -} __PACKED USBD_HIDDescTypeDef; - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_ClassTypeDef USBD_HID; -#define USBD_HID_CLASS &USBD_HID -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -#ifdef USE_USBD_COMPOSITE -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId); -#else -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len); -#endif /* USE_USBD_COMPOSITE */ -uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_HID_H */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c b/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c deleted file mode 100644 index fdf7578..0000000 --- a/Software/stm32project/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_hid.c - * @author MCD Application Team - * @brief This file provides the HID core functions. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2015 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - * @verbatim - * - * =================================================================== - * HID Class Description - * =================================================================== - * This module manages the HID class V1.11 following the "Device Class Definition - * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse protocol - * - Usage Page : Generic Desktop - * - Usage : Joystick - * - Collection : Application - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - ****************************************************************************** - */ - -/* BSPDependencies -- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" -- "stm32xxxxx_{eval}{discovery}_io.c" -EndBSPDependencies */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_hid.h" -#include "usbd_ctlreq.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_FunctionPrototypes - * @{ - */ - -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); -#ifndef USE_USBD_COMPOSITE -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); -#endif /* USE_USBD_COMPOSITE */ -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -USBD_ClassTypeDef USBD_HID = -{ - USBD_HID_Init, - USBD_HID_DeInit, - USBD_HID_Setup, - NULL, /* EP0_TxSent */ - NULL, /* EP0_RxReady */ - USBD_HID_DataIn, /* DataIn */ - NULL, /* DataOut */ - NULL, /* SOF */ - NULL, - NULL, -#ifdef USE_USBD_COMPOSITE - NULL, - NULL, - NULL, - NULL, -#else - USBD_HID_GetHSCfgDesc, - USBD_HID_GetFSCfgDesc, - USBD_HID_GetOtherSpeedCfgDesc, - USBD_HID_GetDeviceQualifierDesc, -#endif /* USE_USBD_COMPOSITE */ -}; - -#ifndef USE_USBD_COMPOSITE -/* USB HID device FS Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_HID_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor - describing the configuration */ -#if (USBD_SELF_POWERED == 1U) - 0xE0, /* bmAttributes: Bus Powered according to user configuration */ -#else - 0xA0, /* bmAttributes: Bus Powered according to user configuration */ -#endif /* USBD_SELF_POWERED */ - USBD_MAX_POWER, /* MaxPower (mA) */ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/ - - HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_EPIN_SIZE, /* wMaxPacketSize: 4 Bytes max */ - 0x00, - HID_FS_BINTERVAL, /* bInterval: Polling Interval */ - /* 34 */ -}; -#endif /* USE_USBD_COMPOSITE */ - -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = -{ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, -}; - -#ifndef USE_USBD_COMPOSITE -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; -#endif /* USE_USBD_COMPOSITE */ - -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ - 0x09, 0x02, /* Usage (Mouse) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x09, 0x01, /* Usage (Pointer) */ - 0xA1, 0x00, /* Collection (Physical) */ - 0x05, 0x09, /* Usage Page (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x03, /* Usage Maximum (0x03) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x95, 0x03, /* Report Count (3) */ - 0x75, 0x01, /* Report Size (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - 0x95, 0x01, /* Report Count (1) */ - 0x75, 0x05, /* Report Size (5) */ - 0x81, 0x01, /* Input (Const,Array,Abs) */ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ - 0x09, 0x30, /* Usage (X) */ - 0x09, 0x31, /* Usage (Y) */ - 0x09, 0x38, /* Usage (Wheel) */ - 0x15, 0x81, /* Logical Minimum (-127) */ - 0x25, 0x7F, /* Logical Maximum (127) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x03, /* Report Count (3) */ - 0x81, 0x06, /* Input (Data,Var,Rel) */ - 0xC0, /* End Collection */ - 0x09, 0x3C, /* Usage (Motion Wakeup) */ - 0x05, 0xFF, /* Usage Page (Reserved 0xFF) */ - 0x09, 0x01, /* Usage (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x02, /* Report Count (2) */ - 0xB1, 0x22, /* Feature (Data,Var,Abs,NoWrp) */ - 0x75, 0x06, /* Report Size (6) */ - 0x95, 0x01, /* Report Count (1) */ - 0xB1, 0x01, /* Feature (Const,Array,Abs,NoWrp) */ - 0xC0 /* End Collection */ -}; - -static uint8_t HIDInEpAdd = HID_EPIN_ADDR; - -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_HID_Init - * Initialize the HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - UNUSED(cfgidx); - - USBD_HID_HandleTypeDef *hhid; - - hhid = (USBD_HID_HandleTypeDef *)USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); - - if (hhid == NULL) - { - pdev->pClassDataCmsit[pdev->classId] = NULL; - return (uint8_t)USBD_EMEM; - } - - pdev->pClassDataCmsit[pdev->classId] = (void *)hhid; - pdev->pClassData = pdev->pClassDataCmsit[pdev->classId]; - -#ifdef USE_USBD_COMPOSITE - /* Get the Endpoints addresses allocated for this class instance */ - HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); -#endif /* USE_USBD_COMPOSITE */ - - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_HS_BINTERVAL; - } - else /* LOW and FULL-speed endpoints */ - { - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = HID_FS_BINTERVAL; - } - - /* Open EP IN */ - (void)USBD_LL_OpenEP(pdev, HIDInEpAdd, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); - pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 1U; - - hhid->state = USBD_HID_IDLE; - - return (uint8_t)USBD_OK; -} - -/** - * @brief USBD_HID_DeInit - * DeInitialize the HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - UNUSED(cfgidx); - -#ifdef USE_USBD_COMPOSITE - /* Get the Endpoints addresses allocated for this class instance */ - HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, (uint8_t)pdev->classId); -#endif /* USE_USBD_COMPOSITE */ - - /* Close HID EPs */ - (void)USBD_LL_CloseEP(pdev, HIDInEpAdd); - pdev->ep_in[HIDInEpAdd & 0xFU].is_used = 0U; - pdev->ep_in[HIDInEpAdd & 0xFU].bInterval = 0U; - - /* Free allocated memory */ - if (pdev->pClassDataCmsit[pdev->classId] != NULL) - { - (void)USBD_free(pdev->pClassDataCmsit[pdev->classId]); - pdev->pClassDataCmsit[pdev->classId] = NULL; - } - - return (uint8_t)USBD_OK; -} - -/** - * @brief USBD_HID_Setup - * Handle the HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) -{ - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; - USBD_StatusTypeDef ret = USBD_OK; - uint16_t len; - uint8_t *pbuf; - uint16_t status_info = 0U; - - if (hhid == NULL) - { - return (uint8_t)USBD_FAIL; - } - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case USBD_HID_REQ_SET_PROTOCOL: - hhid->Protocol = (uint8_t)(req->wValue); - break; - - case USBD_HID_REQ_GET_PROTOCOL: - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); - break; - - case USBD_HID_REQ_SET_IDLE: - hhid->IdleState = (uint8_t)(req->wValue >> 8); - break; - - case USBD_HID_REQ_GET_IDLE: - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_DESCRIPTOR: - if ((req->wValue >> 8) == HID_REPORT_DESC) - { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); - pbuf = HID_MOUSE_ReportDesc; - } - else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) - { - pbuf = USBD_HID_Desc; - len = MIN(USB_HID_DESC_SIZ, req->wLength); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - (void)USBD_CtlSendData(pdev, pbuf, len); - break; - - case USB_REQ_GET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hhid->AltSetting = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_CLEAR_FEATURE: - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - - return (uint8_t)ret; -} - - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report - * @param ClassId: The Class ID - * @retval status - */ -#ifdef USE_USBD_COMPOSITE -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len, uint8_t ClassId) -{ - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[ClassId]; -#else -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) -{ - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId]; -#endif /* USE_USBD_COMPOSITE */ - - if (hhid == NULL) - { - return (uint8_t)USBD_FAIL; - } - -#ifdef USE_USBD_COMPOSITE - /* Get the Endpoints addresses allocated for this class instance */ - HIDInEpAdd = USBD_CoreGetEPAdd(pdev, USBD_EP_IN, USBD_EP_TYPE_INTR, ClassId); -#endif /* USE_USBD_COMPOSITE */ - - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - if (hhid->state == USBD_HID_IDLE) - { - hhid->state = USBD_HID_BUSY; - (void)USBD_LL_Transmit(pdev, HIDInEpAdd, report, len); - } - } - - return (uint8_t)USBD_OK; -} - -/** - * @brief USBD_HID_GetPollingInterval - * return polling interval from endpoint descriptor - * @param pdev: device instance - * @retval polling interval - */ -uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) -{ - uint32_t polling_interval; - - /* HIGH-speed endpoints */ - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - /* Sets the data transfer polling interval for high speed transfers. - Values between 1..16 are allowed. Values correspond to interval - of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */ - polling_interval = (((1U << (HID_HS_BINTERVAL - 1U))) / 8U); - } - else /* LOW and FULL-speed endpoints */ - { - /* Sets the data transfer polling interval for low and full - speed transfers */ - polling_interval = HID_FS_BINTERVAL; - } - - return ((uint32_t)(polling_interval)); -} - -#ifndef USE_USBD_COMPOSITE -/** - * @brief USBD_HID_GetCfgFSDesc - * return FS configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) -{ - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - - if (pEpDesc != NULL) - { - pEpDesc->bInterval = HID_FS_BINTERVAL; - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} - -/** - * @brief USBD_HID_GetCfgHSDesc - * return HS configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) -{ - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - - if (pEpDesc != NULL) - { - pEpDesc->bInterval = HID_HS_BINTERVAL; - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} - -/** - * @brief USBD_HID_GetOtherSpeedCfgDesc - * return other speed configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) -{ - USBD_EpDescTypeDef *pEpDesc = USBD_GetEpDesc(USBD_HID_CfgDesc, HID_EPIN_ADDR); - - if (pEpDesc != NULL) - { - pEpDesc->bInterval = HID_FS_BINTERVAL; - } - - *length = (uint16_t)sizeof(USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} -#endif /* USE_USBD_COMPOSITE */ - -/** - * @brief USBD_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - UNUSED(epnum); - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - ((USBD_HID_HandleTypeDef *)pdev->pClassDataCmsit[pdev->classId])->state = USBD_HID_IDLE; - - return (uint8_t)USBD_OK; -} - -#ifndef USE_USBD_COMPOSITE -/** - * @brief DeviceQualifierDescriptor - * return Device Qualifier descriptor - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) -{ - *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); - - return USBD_HID_DeviceQualifierDesc; -} -#endif /* USE_USBD_COMPOSITE */ -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - diff --git a/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c b/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c new file mode 100644 index 0000000..c4d3e20 --- /dev/null +++ b/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.c @@ -0,0 +1,1307 @@ + +/************************************************************************************************************ +************** Include Headers +************************************************************************************************************/ + +#include "spif.h" + +#if SPIF_DEBUG == SPIF_DEBUG_DISABLE +#define dprintf(...) +#else +#include +#define dprintf(...) printf(__VA_ARGS__) +#endif + +#if SPIF_RTOS == SPIF_RTOS_DISABLE +#elif SPIF_RTOS == SPIF_RTOS_CMSIS_V1 +#include "cmsis_os.h" +#include "freertos.h" +#elif SPIF_RTOS == SPIF_RTOS_CMSIS_V2 +#include "cmsis_os2.h" +#include "freertos.h" +#elif SPIF_RTOS == SPIF_RTOS_THREADX +#include "app_threadx.h" +#endif + +/************************************************************************************************************ +************** Private Definitions +************************************************************************************************************/ + +#define SPIF_DUMMY_BYTE 0xA5 + +#define SPIF_CMD_READSFDP 0x5A +#define SPIF_CMD_ID 0x90 +#define SPIF_CMD_JEDECID 0x9F +#define SPIF_CMD_UNIQUEID 0x4B +#define SPIF_CMD_WRITEDISABLE 0x04 +#define SPIF_CMD_READSTATUS1 0x05 +#define SPIF_CMD_READSTATUS2 0x35 +#define SPIF_CMD_READSTATUS3 0x15 +#define SPIF_CMD_WRITESTATUSEN 0x50 +#define SPIF_CMD_WRITESTATUS1 0x01 +#define SPIF_CMD_WRITESTATUS2 0x31 +#define SPIF_CMD_WRITESTATUS3 0x11 +#define SPIF_CMD_WRITEENABLE 0x06 +#define SPIF_CMD_ADDR4BYTE_EN 0xB7 +#define SPIF_CMD_ADDR4BYTE_DIS 0xE9 +#define SPIF_CMD_PAGEPROG3ADD 0x02 +#define SPIF_CMD_PAGEPROG4ADD 0x12 +#define SPIF_CMD_READDATA3ADD 0x03 +#define SPIF_CMD_READDATA4ADD 0x13 +#define SPIF_CMD_FASTREAD3ADD 0x0B +#define SPIF_CMD_FASTREAD4ADD 0x0C +#define SPIF_CMD_SECTORERASE3ADD 0x20 +#define SPIF_CMD_SECTORERASE4ADD 0x21 +#define SPIF_CMD_BLOCKERASE3ADD 0xD8 +#define SPIF_CMD_BLOCKERASE4ADD 0xDC +#define SPIF_CMD_CHIPERASE1 0x60 +#define SPIF_CMD_CHIPERASE2 0xC7 +#define SPIF_CMD_SUSPEND 0x75 +#define SPIF_CMD_RESUME 0x7A +#define SPIF_CMD_POWERDOWN 0xB9 +#define SPIF_CMD_RELEASE 0xAB +#define SPIF_CMD_FRAMSERNO 0xC3 + +#define SPIF_STATUS1_BUSY (1 << 0) +#define SPIF_STATUS1_WEL (1 << 1) +#define SPIF_STATUS1_BP0 (1 << 2) +#define SPIF_STATUS1_BP1 (1 << 3) +#define SPIF_STATUS1_BP2 (1 << 4) +#define SPIF_STATUS1_TP (1 << 5) +#define SPIF_STATUS1_SEC (1 << 6) +#define SPIF_STATUS1_SRP0 (1 << 7) + +#define SPIF_STATUS2_SRP1 (1 << 0) +#define SPIF_STATUS2_QE (1 << 1) +#define SPIF_STATUS2_RESERVE1 (1 << 2) +#define SPIF_STATUS2_LB0 (1 << 3) +#define SPIF_STATUS2_LB1 (1 << 4) +#define SPIF_STATUS2_LB2 (1 << 5) +#define SPIF_STATUS2_CMP (1 << 6) +#define SPIF_STATUS2_SUS (1 << 7) + +#define SPIF_STATUS3_RESERVE1 (1 << 0) +#define SPIF_STATUS3_RESERVE2 (1 << 1) +#define SPIF_STATUS3_WPS (1 << 2) +#define SPIF_STATUS3_RESERVE3 (1 << 3) +#define SPIF_STATUS3_RESERVE4 (1 << 4) +#define SPIF_STATUS3_DRV0 (1 << 5) +#define SPIF_STATUS3_DRV1 (1 << 6) +#define SPIF_STATUS3_HOLD (1 << 7) + +/************************************************************************************************************ +************** Private Functions +************************************************************************************************************/ + +void SPIF_Delay(uint32_t Delay); +void SPIF_Lock(SPIF_HandleTypeDef *Handle); +void SPIF_UnLock(SPIF_HandleTypeDef *Handle); +void SPIF_CsPin(SPIF_HandleTypeDef *Handle, bool Select); +bool SPIF_TransmitReceive(SPIF_HandleTypeDef *Handle, uint8_t *Tx, uint8_t *Rx, size_t Size, uint32_t Timeout); +bool SPIF_Transmit(SPIF_HandleTypeDef *Handle, uint8_t *Tx, size_t Size, uint32_t Timeout); +bool SPIF_Receive(SPIF_HandleTypeDef *Handle, uint8_t *Rx, size_t Size, uint32_t Timeout); +bool SPIF_WriteEnable(SPIF_HandleTypeDef *Handle); +bool SPIF_WriteDisable(SPIF_HandleTypeDef *Handle); +uint8_t SPIF_ReadReg1(SPIF_HandleTypeDef *Handle); +uint8_t SPIF_ReadReg2(SPIF_HandleTypeDef *Handle); +uint8_t SPIF_ReadReg3(SPIF_HandleTypeDef *Handle); +bool SPIF_WriteReg1(SPIF_HandleTypeDef *Handle, uint8_t Data); +bool SPIF_WriteReg2(SPIF_HandleTypeDef *Handle, uint8_t Data); +bool SPIF_WriteReg3(SPIF_HandleTypeDef *Handle, uint8_t Data); +bool SPIF_WaitForWriting(SPIF_HandleTypeDef *Handle, uint32_t Timeout); +bool SPIF_FindChip(SPIF_HandleTypeDef *Handle); +bool SPIF_WriteFn(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); +bool SPIF_ReadFn(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size); + +/***********************************************************************************************************/ + +void SPIF_Delay(uint32_t Delay) +{ +#if SPIF_RTOS == SPIF_RTOS_DISABLE + HAL_Delay(Delay); +#elif (SPIF_RTOS == SPIF_RTOS_CMSIS_V1) || (SPIF_RTOS == SPIF_RTOS_CMSIS_V2) + uint32_t d = (configTICK_RATE_HZ * Delay) / 1000; + if (d == 0) + d = 1; + osDelay(d); +#elif SPIF_RTOS == SPIF_RTOS_THREADX + uint32_t d = (TX_TIMER_TICKS_PER_SECOND * Delay) / 1000; + if (d == 0) + d = 1; + tx_thread_sleep(d); +#endif +} + +/***********************************************************************************************************/ + +void SPIF_Lock(SPIF_HandleTypeDef *Handle) +{ + while (Handle->Lock) + { + SPIF_Delay(1); + } + Handle->Lock = 1; +} + +/***********************************************************************************************************/ + +void SPIF_UnLock(SPIF_HandleTypeDef *Handle) +{ + Handle->Lock = 0; +} + +/***********************************************************************************************************/ + +void SPIF_CsPin(SPIF_HandleTypeDef *Handle, bool Select) +{ + HAL_GPIO_WritePin(Handle->Gpio, Handle->Pin, (GPIO_PinState)Select); + for (int i = 0; i < 10; i++); +} + +/***********************************************************************************************************/ + +bool SPIF_TransmitReceive(SPIF_HandleTypeDef *Handle, uint8_t *Tx, uint8_t *Rx, size_t Size, uint32_t Timeout) +{ + bool retVal = false; +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_TransmitReceive(Handle->HSpi, Tx, Rx, Size, Timeout) == HAL_OK) + { + retVal = true; + } + else + { + dprintf("SPIF TIMEOUT\r\n"); + } +#elif (SPIF_PLATFORM == SPIF_PLATFORM_HAL_DMA) + uint32_t startTime = HAL_GetTick(); + if (HAL_SPI_TransmitReceive_DMA(Handle->HSpi, Tx, Rx, Size) != HAL_OK) + { + dprintf("SPIF TRANSFER ERROR\r\n"); + } + else + { + while (1) + { + SPIF_Delay(1); + if (HAL_GetTick() - startTime >= Timeout) + { + dprintf("SPIF TIMEOUT\r\n"); + HAL_SPI_DMAStop(Handle->HSpi); + break; + } + if (HAL_SPI_GetState(Handle->HSpi) == HAL_SPI_STATE_READY) + { + retVal = true; + break; + } + } + } +#endif + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_Transmit(SPIF_HandleTypeDef *Handle, uint8_t *Tx, size_t Size, uint32_t Timeout) +{ + bool retVal = false; +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_Transmit(Handle->HSpi, Tx, Size, Timeout) == HAL_OK) + { + retVal = true; + } + else + { + dprintf("SPIF TIMEOUT\r\n"); + } +#elif (SPIF_PLATFORM == SPIF_PLATFORM_HAL_DMA) + uint32_t startTime = HAL_GetTick(); + if (HAL_SPI_Transmit_DMA(Handle->HSpi, Tx, Size) != HAL_OK) + { + dprintf("SPIF TRANSFER ERROR\r\n"); + } + else + { + while (1) + { + SPIF_Delay(1); + if (HAL_GetTick() - startTime >= Timeout) + { + dprintf("SPIF TIMEOUT\r\n"); + HAL_SPI_DMAStop(Handle->HSpi); + break; + } + if (HAL_SPI_GetState(Handle->HSpi) == HAL_SPI_STATE_READY) + { + retVal = true; + break; + } + } + } +#endif + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_Receive(SPIF_HandleTypeDef *Handle, uint8_t *Rx, size_t Size, uint32_t Timeout) +{ + bool retVal = false; +#if (SPIF_PLATFORM == SPIF_PLATFORM_HAL) + if (HAL_SPI_Receive(Handle->HSpi, Rx, Size, Timeout) == HAL_OK) + { + retVal = true; + } + else + { + dprintf("SPIF TIMEOUT\r\n"); + } +#elif (SPIF_PLATFORM == SPIF_PLATFORM_HAL_DMA) + uint32_t startTime = HAL_GetTick(); + if (HAL_SPI_Receive_DMA(Handle->HSpi, Rx, Size) != HAL_OK) + { + dprintf("SPIF TRANSFER ERROR\r\n"); + } + else + { + while (1) + { + SPIF_Delay(1); + if (HAL_GetTick() - startTime >= Timeout) + { + dprintf("SPIF TIMEOUT\r\n"); + HAL_SPI_DMAStop(Handle->HSpi); + break; + } + if (HAL_SPI_GetState(Handle->HSpi) == HAL_SPI_STATE_READY) + { + retVal = true; + break; + } + } + } +#endif + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteEnable(SPIF_HandleTypeDef *Handle) +{ + bool retVal = true; + uint8_t tx[1] = {SPIF_CMD_WRITEENABLE}; + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + { + retVal = false; + dprintf("SPIF_WriteEnable() Error\r\n"); + } + SPIF_CsPin(Handle, 1); + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteDisable(SPIF_HandleTypeDef *Handle) +{ + bool retVal = true; + uint8_t tx[1] = {SPIF_CMD_WRITEDISABLE}; + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + { + retVal = false; + dprintf("SPIF_WriteDisable() Error\r\n"); + } + SPIF_CsPin(Handle, 1); + return retVal; +} + +/***********************************************************************************************************/ + +uint8_t SPIF_ReadReg1(SPIF_HandleTypeDef *Handle) +{ + uint8_t retVal = 0; + uint8_t tx[2] = {SPIF_CMD_READSTATUS1, SPIF_DUMMY_BYTE}; + uint8_t rx[2]; + SPIF_CsPin(Handle, 0); + if (SPIF_TransmitReceive(Handle, tx, rx, 2, 100) == true) + { + retVal = rx[1]; + } + SPIF_CsPin(Handle, 1); + return retVal; +} + +/***********************************************************************************************************/ + +uint8_t SPIF_ReadReg2(SPIF_HandleTypeDef *Handle) +{ + uint8_t retVal = 0; + uint8_t tx[2] = {SPIF_CMD_READSTATUS2, SPIF_DUMMY_BYTE}; + uint8_t rx[2]; + SPIF_CsPin(Handle, 0); + if (SPIF_TransmitReceive(Handle, tx, rx, 2, 100) == true) + { + retVal = rx[1]; + } + SPIF_CsPin(Handle, 1); + return retVal; +} + +/***********************************************************************************************************/ + +uint8_t SPIF_ReadReg3(SPIF_HandleTypeDef *Handle) +{ + uint8_t retVal = 0; + uint8_t tx[2] = {SPIF_CMD_READSTATUS3, SPIF_DUMMY_BYTE}; + uint8_t rx[2]; + SPIF_CsPin(Handle, 0); + if (SPIF_TransmitReceive(Handle, tx, rx, 2, 100) == true) + { + retVal = rx[1]; + } + SPIF_CsPin(Handle, 1); + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteReg1(SPIF_HandleTypeDef *Handle, uint8_t Data) +{ + bool retVal = true; + uint8_t tx[2] = {SPIF_CMD_WRITESTATUS1, Data}; + uint8_t cmd = SPIF_CMD_WRITESTATUSEN; + do + { + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, &cmd, 1, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 2, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + } while (0); + + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteReg2(SPIF_HandleTypeDef *Handle, uint8_t Data) +{ + bool retVal = true; + uint8_t tx[2] = {SPIF_CMD_WRITESTATUS2, Data}; + uint8_t cmd = SPIF_CMD_WRITESTATUSEN; + do + { + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, &cmd, 1, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 2, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + } while (0); + + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteReg3(SPIF_HandleTypeDef *Handle, uint8_t Data) +{ + bool retVal = true; + uint8_t tx[2] = {SPIF_CMD_WRITESTATUS3, Data}; + uint8_t cmd = SPIF_CMD_WRITESTATUSEN; + do + { + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, &cmd, 1, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 2, 100) == false) + { + retVal = false; + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + } while (0); + + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WaitForWriting(SPIF_HandleTypeDef *Handle, uint32_t Timeout) +{ + bool retVal = false; + uint32_t startTime = HAL_GetTick(); + while (1) + { + SPIF_Delay(1); + if (HAL_GetTick() - startTime >= Timeout) + { + dprintf("SPIF_WaitForWriting() TIMEOUT\r\n"); + break; + } + if ((SPIF_ReadReg1(Handle) & SPIF_STATUS1_BUSY) == 0) + { + retVal = true; + break; + } + } + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_FindChip(SPIF_HandleTypeDef *Handle) +{ + uint8_t tx[4] = {SPIF_CMD_JEDECID, 0xFF, 0xFF, 0xFF}; + uint8_t rx[4]; + bool retVal = false; + do + { + dprintf("SPIF_FindChip()\r\n"); + SPIF_CsPin(Handle, 0); + if (SPIF_TransmitReceive(Handle, tx, rx, 4, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + dprintf("CHIP ID: 0x%02X%02X%02X\r\n", rx[1], rx[2], rx[3]); + Handle->Manufactor = rx[1]; + Handle->MemType = rx[2]; + Handle->Size = rx[3]; + + dprintf("SPIF MANUFACTURE: "); + switch (Handle->Manufactor) + { + case SPIF_MANUFACTOR_WINBOND: + dprintf("WINBOND"); + break; + case SPIF_MANUFACTOR_SPANSION: + dprintf("SPANSION"); + break; + case SPIF_MANUFACTOR_MICRON: + dprintf("MICRON"); + break; + case SPIF_MANUFACTOR_MACRONIX: + dprintf("MACRONIX"); + break; + case SPIF_MANUFACTOR_ISSI: + dprintf("ISSI"); + break; + case SPIF_MANUFACTOR_GIGADEVICE: + dprintf("GIGADEVICE"); + break; + case SPIF_MANUFACTOR_AMIC: + dprintf("AMIC"); + break; + case SPIF_MANUFACTOR_SST: + dprintf("SST"); + break; + case SPIF_MANUFACTOR_HYUNDAI: + dprintf("HYUNDAI"); + break; + case SPIF_MANUFACTOR_FUDAN: + dprintf("FUDAN"); + break; + case SPIF_MANUFACTOR_ESMT: + dprintf("ESMT"); + break; + case SPIF_MANUFACTOR_INTEL: + dprintf("INTEL"); + break; + case SPIF_MANUFACTOR_SANYO: + dprintf("SANYO"); + break; + case SPIF_MANUFACTOR_FUJITSU: + dprintf("FUJITSU"); + break; + case SPIF_MANUFACTOR_EON: + dprintf("EON"); + break; + case SPIF_MANUFACTOR_PUYA: + dprintf("PUYA"); + break; + default: + Handle->Manufactor = SPIF_MANUFACTOR_ERROR; + dprintf("ERROR"); + break; + } + dprintf(" - MEMTYPE: 0x%02X", Handle->MemType); + dprintf(" - SIZE: "); + switch (Handle->Size) + { + case SPIF_SIZE_1MBIT: + Handle->BlockCnt = 2; + dprintf("1 MBIT\r\n"); + break; + case SPIF_SIZE_2MBIT: + Handle->BlockCnt = 4; + dprintf("2 MBIT\r\n"); + break; + case SPIF_SIZE_4MBIT: + Handle->BlockCnt = 8; + dprintf("4 MBIT\r\n"); + break; + case SPIF_SIZE_8MBIT: + Handle->BlockCnt = 16; + dprintf("8 MBIT\r\n"); + break; + case SPIF_SIZE_16MBIT: + Handle->BlockCnt = 32; + dprintf("16 MBIT\r\n"); + break; + case SPIF_SIZE_32MBIT: + Handle->BlockCnt = 64; + dprintf("32 MBIT\r\n"); + break; + case SPIF_SIZE_64MBIT: + Handle->BlockCnt = 128; + dprintf("64 MBIT\r\n"); + break; + case SPIF_SIZE_128MBIT: + Handle->BlockCnt = 256; + dprintf("128 MBIT\r\n"); + break; + case SPIF_SIZE_256MBIT: + Handle->BlockCnt = 512; + dprintf("256 MBIT\r\n"); + break; + case SPIF_SIZE_512MBIT: + Handle->BlockCnt = 1024; + dprintf("512 MBIT\r\n"); + break; + default: + Handle->Size = SPIF_SIZE_ERROR; + dprintf("ERROR\r\n"); + break; + } + + Handle->SectorCnt = Handle->BlockCnt * 16; + Handle->PageCnt = (Handle->SectorCnt * SPIF_SECTOR_SIZE) / SPIF_PAGE_SIZE; + dprintf("SPIF BLOCK CNT: %ld\r\n", Handle->BlockCnt); + dprintf("SPIF SECTOR CNT: %ld\r\n", Handle->SectorCnt); + dprintf("SPIF PAGE CNT: %ld\r\n", Handle->PageCnt); + dprintf("SPIF STATUS1: 0x%02X\r\n", SPIF_ReadReg1(Handle)); + dprintf("SPIF STATUS2: 0x%02X\r\n", SPIF_ReadReg2(Handle)); + dprintf("SPIF STATUS3: 0x%02X\r\n", SPIF_ReadReg3(Handle)); + retVal = true; + + } while (0); + + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_WriteFn(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + bool retVal = false; + uint32_t address = 0, maximum = SPIF_PAGE_SIZE - Offset; + uint8_t tx[5]; + do + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_WritePage() START PAGE %ld\r\n", PageNumber); + if (PageNumber >= Handle->PageCnt) + { + dprintf("SPIF_WritePage() ERROR PageNumber\r\n"); + break; + } + if (Offset >= SPIF_PAGE_SIZE) + { + dprintf("SPIF_WritePage() ERROR Offset\r\n"); + break; + } + if (Size > maximum) + { + Size = maximum; + } + address = SPIF_PageToAddress(PageNumber) + Offset; +#if SPIF_DEBUG == SPIF_DEBUG_FULL + dprintf("SPIF WRITING {\r\n0x%02X", Data[0]); + for (int i = 1; i < Size; i++) + { + if (i % 8 == 0) + { + dprintf("\r\n"); + } + dprintf(", 0x%02X", Data[i]); + } + dprintf("\r\n}\r\n"); +#endif + if (SPIF_WriteEnable(Handle) == false) + { + break; + } + SPIF_CsPin(Handle, 0); + if (Handle->BlockCnt >= 512) + { + tx[0] = SPIF_CMD_PAGEPROG4ADD; + tx[1] = (address & 0xFF000000) >> 24; + tx[2] = (address & 0x00FF0000) >> 16; + tx[3] = (address & 0x0000FF00) >> 8; + tx[4] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + else + { + tx[0] = SPIF_CMD_PAGEPROG3ADD; + tx[1] = (address & 0x00FF0000) >> 16; + tx[2] = (address & 0x0000FF00) >> 8; + tx[3] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + if (SPIF_Transmit(Handle, Data, Size, 1000) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + if (SPIF_WaitForWriting(Handle, 100)) + { + dprintf("SPIF_WritePage() %d BYTES WITERN DONE AFTER %ld ms\r\n", (uint16_t)Size, HAL_GetTick() - dbgTime); + retVal = true; + } + + } while (0); + + SPIF_WriteDisable(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +bool SPIF_ReadFn(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size) +{ + bool retVal = false; + uint8_t tx[5]; + do + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_ReadAddress() START ADDRESS %ld\r\n", Address); + SPIF_CsPin(Handle, 0); + if (Handle->BlockCnt >= 512) + { + tx[0] = SPIF_CMD_READDATA4ADD; + tx[1] = (Address & 0xFF000000) >> 24; + tx[2] = (Address & 0x00FF0000) >> 16; + tx[3] = (Address & 0x0000FF00) >> 8; + tx[4] = (Address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + else + { + tx[0] = SPIF_CMD_READDATA3ADD; + tx[1] = (Address & 0x00FF0000) >> 16; + tx[2] = (Address & 0x0000FF00) >> 8; + tx[3] = (Address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + if (SPIF_Receive(Handle, Data, Size, 2000) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + dprintf("SPIF_ReadAddress() %d BYTES READ DONE AFTER %ld ms\r\n", (uint16_t)Size, HAL_GetTick() - dbgTime); +#if SPIF_DEBUG == SPIF_DEBUG_FULL + dprintf("{\r\n0x%02X", Data[0]); + for (int i = 1; i < Size; i++) + { + if (i % 8 == 0) + { + dprintf("\r\n"); + } + dprintf(", 0x%02X", Data[i]); + } + dprintf("\r\n}\r\n"); +#endif + retVal = true; + + } while (0); + + return retVal; +} + +/************************************************************************************************************ +************** Public Functions +************************************************************************************************************/ + +/** + * @brief Initialize the SPIF. + * @note Enable and configure the SPI and Set GPIO as output for CS pin on the CubeMX + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param *HSpi: Pointer to a SPI_HandleTypeDef structure + * @param *Gpio: Pointer to a GPIO_TypeDef structure for CS + * @param Pin: Pin of CS + * + * @retval bool: true or false + */ +bool SPIF_Init(SPIF_HandleTypeDef *Handle, SPI_HandleTypeDef *HSpi, GPIO_TypeDef *Gpio, uint16_t Pin) +{ + bool retVal = false; + do + { + if ((Handle == NULL) || (HSpi == NULL) || (Gpio == NULL) || (Handle->Inited == 1)) + { + dprintf("SPIF_Init() Error, Wrong Parameter\r\n"); + break; + } + memset(Handle, 0, sizeof(SPIF_HandleTypeDef)); + Handle->HSpi = HSpi; + Handle->Gpio = Gpio; + Handle->Pin = Pin; + SPIF_CsPin(Handle, 1); + /* wait for stable VCC */ + while (HAL_GetTick() < 20) + { + SPIF_Delay(1); + } + if (SPIF_WriteDisable(Handle) == false) + { + break; + } + retVal = SPIF_FindChip(Handle); + if (retVal) + { + Handle->Inited = 1; + dprintf("SPIF_Init() Done\r\n"); + } + + } while (0); + + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Full Erase chip. + * @note Send the Full-Erase-chip command and wait for completion + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * + * @retval bool: true or false + */ +bool SPIF_EraseChip(SPIF_HandleTypeDef *Handle) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint8_t tx[1] = {SPIF_CMD_CHIPERASE1}; + do + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_EraseChip() START\r\n"); + if (SPIF_WriteEnable(Handle) == false) + { + break; + } + SPIF_CsPin(Handle, 0); + if (SPIF_Transmit(Handle, tx, 1, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + SPIF_CsPin(Handle, 1); + if (SPIF_WaitForWriting(Handle, Handle->BlockCnt * 1000)) + { + dprintf("SPIF_EraseChip() DONE AFTER %ld ms\r\n", HAL_GetTick() - dbgTime); + retVal = true; + } + + } while (0); + + SPIF_WriteDisable(Handle); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Erase Sector. + * @note Send the Erase-Sector command and wait for completion + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param Sector: Selected Sector + * + * @retval bool: true or false + */ +bool SPIF_EraseSector(SPIF_HandleTypeDef *Handle, uint32_t Sector) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t address = Sector * SPIF_SECTOR_SIZE; + uint8_t tx[5]; + do + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_EraseSector() START SECTOR %ld\r\n", Sector); + if (Sector >= Handle->SectorCnt) + { + dprintf("SPIF_EraseSector() ERROR Sector NUMBER\r\n"); + break; + } + if (SPIF_WriteEnable(Handle) == false) + { + break; + } + SPIF_CsPin(Handle, 0); + if (Handle->BlockCnt >= 512) + { + tx[0] = SPIF_CMD_SECTORERASE4ADD; + tx[1] = (address & 0xFF000000) >> 24; + tx[2] = (address & 0x00FF0000) >> 16; + tx[3] = (address & 0x0000FF00) >> 8; + tx[4] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + else + { + tx[0] = SPIF_CMD_SECTORERASE3ADD; + tx[1] = (address & 0x00FF0000) >> 16; + tx[2] = (address & 0x0000FF00) >> 8; + tx[3] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + SPIF_CsPin(Handle, 1); + if (SPIF_WaitForWriting(Handle, 1000)) + { + dprintf("SPIF_EraseSector() DONE AFTER %ld ms\r\n", HAL_GetTick() - dbgTime); + retVal = true; + } + + } while (0); + + SPIF_WriteDisable(Handle); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Erase Block. + * @note Send the Erase-Block command and wait for completion + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param Sector: Selected Block + * + * @retval bool: true or false + */ +bool SPIF_EraseBlock(SPIF_HandleTypeDef *Handle, uint32_t Block) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t address = Block * SPIF_BLOCK_SIZE; + uint8_t tx[5]; + do + { +#if SPIF_DEBUG != SPIF_DEBUG_DISABLE + uint32_t dbgTime = HAL_GetTick(); +#endif + dprintf("SPIF_EraseBlock() START PAGE %ld\r\n", Block); + if (Block >= Handle->BlockCnt) + { + dprintf("SPIF_EraseBlock() ERROR Block NUMBER\r\n"); + break; + } + if (SPIF_WriteEnable(Handle) == false) + { + break; + } + SPIF_CsPin(Handle, 0); + if (Handle->BlockCnt >= 512) + { + tx[0] = SPIF_CMD_BLOCKERASE4ADD; + tx[1] = (address & 0xFF000000) >> 24; + tx[2] = (address & 0x00FF0000) >> 16; + tx[3] = (address & 0x0000FF00) >> 8; + tx[4] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 5, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + else + { + tx[0] = SPIF_CMD_BLOCKERASE3ADD; + tx[1] = (address & 0x00FF0000) >> 16; + tx[2] = (address & 0x0000FF00) >> 8; + tx[3] = (address & 0x000000FF); + if (SPIF_Transmit(Handle, tx, 4, 100) == false) + { + SPIF_CsPin(Handle, 1); + break; + } + } + SPIF_CsPin(Handle, 1); + if (SPIF_WaitForWriting(Handle, 3000)) + { + dprintf("SPIF_EraseBlock() DONE AFTER %ld ms\r\n", HAL_GetTick() - dbgTime); + retVal = true; + } + + } while (0); + + SPIF_WriteDisable(Handle); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Write data array to an Address + * @note Write a data array with specified size. + * @note All pages should be erased before write + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param Address: Start Address + * @param *Data: Pointer to Data + * @param Size: The length of data should be written. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_WriteAddress(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t page, add, offset, remaining, length, maximum, index = 0; + add = Address; + remaining = Size; + do + { + page = SPIF_AddressToPage(add); + offset = add % SPIF_PAGE_SIZE; + maximum = SPIF_PAGE_SIZE - offset; + if (remaining <= maximum) + { + length = remaining; + } + else + { + length = maximum; + } + if (SPIF_WriteFn(Handle, page, &Data[index], length, offset) == false) + { + break; + } + add += length; + index += length; + remaining -= length; + if (remaining == 0) + { + retVal = true; + break; + } + + } while (remaining > 0); + + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Write data array to a Page + * @note Write a data array with specified size. + * @note The Page should be erased before write + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param PageNumber: Page Number + * @param *Data: Pointer to Data + * @param Size: The length of data should be written. (in byte) + * @param Offset: The start point for writing data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_WritePage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = false; + retVal = SPIF_WriteFn(Handle, PageNumber, Data, Size, Offset); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Write data array to a Sector + * @note Write a data array with specified size. + * @note The Sector should be erased before write + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param SectorNumber: Sector Number + * @param *Data: Pointer to Data + * @param Size: The length of data should be written. (in byte) + * @param Offset: The start point for writing data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_WriteSector(SPIF_HandleTypeDef *Handle, uint32_t SectorNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = true; + do + { + if (Offset >= SPIF_SECTOR_SIZE) + { + retVal = false; + break; + } + if (Size > (SPIF_SECTOR_SIZE - Offset)) + { + Size = SPIF_SECTOR_SIZE - Offset; + } + uint32_t bytesWritten = 0; + uint32_t pageNumber = SectorNumber * (SPIF_SECTOR_SIZE / SPIF_PAGE_SIZE); + pageNumber += Offset / SPIF_PAGE_SIZE; + uint32_t remainingBytes = Size; + uint32_t pageOffset = Offset % SPIF_PAGE_SIZE; + while (remainingBytes > 0 && pageNumber < ((SectorNumber + 1) * (SPIF_SECTOR_SIZE / SPIF_PAGE_SIZE))) + { + uint32_t bytesToWrite = (remainingBytes > (SPIF_PAGE_SIZE - pageOffset)) ? (SPIF_PAGE_SIZE - pageOffset) : remainingBytes; + if (SPIF_WriteFn(Handle, pageNumber, Data + bytesWritten, bytesToWrite, pageOffset) == false) + { + retVal = false; + break; + } + bytesWritten += bytesToWrite; + remainingBytes -= bytesToWrite; + pageNumber++; + pageOffset = 0; + } + } while (0); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Write data array to a Block + * @note Write a data array with specified size. + * @note The Block should be erased before write + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param SectorNumber: Block Number + * @param *Data: Pointer to Data + * @param Size: The length of data should be written. (in byte) + * @param Offset: The start point for writing data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_WriteBlock(SPIF_HandleTypeDef *Handle, uint32_t BlockNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = true; + do + { + if (Offset >= SPIF_BLOCK_SIZE) + { + retVal = false; + break; + } + if (Size > (SPIF_BLOCK_SIZE - Offset)) + { + Size = SPIF_BLOCK_SIZE - Offset; + } + uint32_t bytesWritten = 0; + uint32_t pageNumber = BlockNumber * (SPIF_BLOCK_SIZE / SPIF_PAGE_SIZE); + pageNumber += Offset / SPIF_PAGE_SIZE; + uint32_t remainingBytes = Size; + uint32_t pageOffset = Offset % SPIF_PAGE_SIZE; + while (remainingBytes > 0 && pageNumber < ((BlockNumber + 1) * (SPIF_BLOCK_SIZE / SPIF_PAGE_SIZE))) + { + uint32_t bytesToWrite = (remainingBytes > (SPIF_PAGE_SIZE - pageOffset)) ? (SPIF_PAGE_SIZE - pageOffset) : remainingBytes; + if (SPIF_WriteFn(Handle, pageNumber, Data + bytesWritten, bytesToWrite, pageOffset) == false) + { + retVal = false; + break; + } + bytesWritten += bytesToWrite; + remainingBytes -= bytesToWrite; + pageNumber++; + pageOffset = 0; + } + + } while (0); + + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Read From Address + * @note Read data from memory and copy to array + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param Address: Start Address + * @param *Data: Pointer to Data (output) + * @param Size: The length of data should be written. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_ReadAddress(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size) +{ + SPIF_Lock(Handle); + bool retVal = false; + retVal = SPIF_ReadFn(Handle, Address, Data, Size); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Read a Page + * @note Read a page and copy to array + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param PageNumber: Page Number + * @param *Data: Pointer to Data (output) + * @param Size: The length of data should be read. (in byte) + * @param Offset: The start point for Reading data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_ReadPage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t address = SPIF_PageToAddress(PageNumber) + Offset; + uint32_t maximum = SPIF_PAGE_SIZE - Offset; + if (Size > maximum) + { + Size = maximum; + } + retVal = SPIF_ReadFn(Handle, address, Data, Size); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Read a Sector + * @note Read a Sector and copy to array + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param SectorNumber: Sector Number + * @param *Data: Pointer to Data (output) + * @param Size: The length of data should be read. (in byte) + * @param Offset: The start point for Reading data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_ReadSector(SPIF_HandleTypeDef *Handle, uint32_t SectorNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t address = SPIF_SectorToAddress(SectorNumber) + Offset; + uint32_t maximum = SPIF_SECTOR_SIZE - Offset; + if (Size > maximum) + { + Size = maximum; + } + retVal = SPIF_ReadFn(Handle, address, Data, Size); + SPIF_UnLock(Handle); + return retVal; +} + +/***********************************************************************************************************/ + +/** + * @brief Read a Block + * @note Read a Block and copy to array + * + * @param *Handle: Pointer to SPIF_HandleTypeDef structure + * @param BlockNumber: Block Number + * @param *Data: Pointer to Data (output) + * @param Size: The length of data should be read. (in byte) + * @param Offset: The start point for Reading data. (in byte) + * + * @retval bool: true or false + */ +bool SPIF_ReadBlock(SPIF_HandleTypeDef *Handle, uint32_t BlockNumber, uint8_t *Data, uint32_t Size, uint32_t Offset) +{ + SPIF_Lock(Handle); + bool retVal = false; + uint32_t address = SPIF_BlockToAddress(BlockNumber) + Offset; + uint32_t maximum = SPIF_BLOCK_SIZE - Offset; + if (Size > maximum) + { + Size = maximum; + } + retVal = SPIF_ReadFn(Handle, address, Data, Size); + SPIF_UnLock(Handle); + return retVal; +} diff --git a/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h b/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h new file mode 100644 index 0000000..02119b3 --- /dev/null +++ b/Software/stm32project/Middlewares/Third_Party/NimaLTD_Driver/SPIF/spif.h @@ -0,0 +1,164 @@ +#ifndef _SPIF_H_ +#define _SPIF_H_ + +/*********************************************************************************************************** + + Author: Nima Askari + Github: https://www.github.com/NimaLTD + LinkedIn: https://www.linkedin.com/in/nimaltd + Youtube: https://www.youtube.com/@nimaltd + Instagram: https://instagram.com/github.NimaLTD + + Version: 2.3.2 + + History: + + 2.3.2 + - Fixed SPIF_Read() offset. Fixed ISSI ID + + 2.3.1 + - Fixed SPIF_WriteSector() and SPIF_WriteBlock() + + 2.3.0 + - Added ThreadX Configuration + + 2.2.2 + - Compile error + + 2.2.1 + - Updated SPIF_WriteAddress() + + 2.2.0 + - Added SPI_Trasmit and SPI_Receive again :) + + 2.1.0 + - Added Support HAL-DMA + - Removed SPI_Trasmit function + + 2.0.1 + - Removed SPI_Receive function + + 2.0.0 + - Rewrite again + - Supported STM32CubeMx Packet installer + +***********************************************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************************************ +************** Include Headers +************************************************************************************************************/ + +#include +#include +#include "NimaLTD.I-CUBE-SPIF_conf.h" +#include "spi.h" + +/************************************************************************************************************ +************** Public Definitions +************************************************************************************************************/ + +#define SPIF_PAGE_SIZE 0x100 +#define SPIF_SECTOR_SIZE 0x1000 +#define SPIF_BLOCK_SIZE 0x10000 + +#define SPIF_PageToSector(PageNumber) ((PageNumber * SPIF_PAGE_SIZE) / SPIF_SECTOR_SIZE) +#define SPIF_PageToBlock(PageNumber) ((PageNumber * SPIF_PAGE_SIZE) / SPIF_BLOCK_SIZE) +#define SPIF_SectorToBlock(SectorNumber) ((SectorNumber * SPIF_SECTOR_SIZE) / SPIF_BLOCK_SIZE) +#define SPIF_SectorToPage(SectorNumber) ((SectorNumber * SPIF_SECTOR_SIZE) / SPIF_PAGE_SIZE) +#define SPIF_BlockToPage(BlockNumber) ((BlockNumber * SPIF_BLOCK_SIZE) / SPIF_PAGE_SIZE) +#define SPIF_PageToAddress(PageNumber) (PageNumber * SPIF_PAGE_SIZE) +#define SPIF_SectorToAddress(SectorNumber) (SectorNumber * SPIF_SECTOR_SIZE) +#define SPIF_BlockToAddress(BlockNumber) (BlockNumber * SPIF_BLOCK_SIZE) +#define SPIF_AddressToPage(Address) (Address / SPIF_PAGE_SIZE) +#define SPIF_AddressToSector(Address) (Address / SPIF_SECTOR_SIZE) +#define SPIF_AddressToBlock(Address) (Address / SPIF_BLOCK_SIZE) + +/************************************************************************************************************ +************** Public struct/enum +************************************************************************************************************/ + +typedef enum +{ + SPIF_MANUFACTOR_ERROR = 0, + SPIF_MANUFACTOR_WINBOND = 0xEF, + SPIF_MANUFACTOR_ISSI = 0x9D, + SPIF_MANUFACTOR_MICRON = 0x20, + SPIF_MANUFACTOR_GIGADEVICE = 0xC8, + SPIF_MANUFACTOR_MACRONIX = 0xC2, + SPIF_MANUFACTOR_SPANSION = 0x01, + SPIF_MANUFACTOR_AMIC = 0x37, + SPIF_MANUFACTOR_SST = 0xBF, + SPIF_MANUFACTOR_HYUNDAI = 0xAD, + SPIF_MANUFACTOR_ATMEL = 0x1F, + SPIF_MANUFACTOR_FUDAN = 0xA1, + SPIF_MANUFACTOR_ESMT = 0x8C, + SPIF_MANUFACTOR_INTEL = 0x89, + SPIF_MANUFACTOR_SANYO = 0x62, + SPIF_MANUFACTOR_FUJITSU = 0x04, + SPIF_MANUFACTOR_EON = 0x1C, + SPIF_MANUFACTOR_PUYA = 0x85, + +} SPIF_ManufactorTypeDef; + +typedef enum +{ + SPIF_SIZE_ERROR = 0, + SPIF_SIZE_1MBIT = 0x11, + SPIF_SIZE_2MBIT = 0x12, + SPIF_SIZE_4MBIT = 0x13, + SPIF_SIZE_8MBIT = 0x14, + SPIF_SIZE_16MBIT = 0x15, + SPIF_SIZE_32MBIT = 0x16, + SPIF_SIZE_64MBIT = 0x17, + SPIF_SIZE_128MBIT = 0x18, + SPIF_SIZE_256MBIT = 0x19, + SPIF_SIZE_512MBIT = 0x20, + +} SPIF_SizeTypeDef; + +typedef struct +{ + SPI_HandleTypeDef *HSpi; + GPIO_TypeDef *Gpio; + SPIF_ManufactorTypeDef Manufactor; + SPIF_SizeTypeDef Size; + uint8_t Inited; + uint8_t MemType; + uint8_t Lock; + uint8_t Reserved; + uint32_t Pin; + uint32_t PageCnt; + uint32_t SectorCnt; + uint32_t BlockCnt; + +} SPIF_HandleTypeDef; + +/************************************************************************************************************ +************** Public Functions +************************************************************************************************************/ + +bool SPIF_Init(SPIF_HandleTypeDef *Handle, SPI_HandleTypeDef *HSpi, GPIO_TypeDef *Gpio, uint16_t Pin); + +bool SPIF_EraseChip(SPIF_HandleTypeDef *Handle); +bool SPIF_EraseSector(SPIF_HandleTypeDef *Handle, uint32_t Sector); +bool SPIF_EraseBlock(SPIF_HandleTypeDef *Handle, uint32_t Block); + +bool SPIF_WriteAddress(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size); +bool SPIF_WritePage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); +bool SPIF_WriteSector(SPIF_HandleTypeDef *Handle, uint32_t SectorNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); +bool SPIF_WriteBlock(SPIF_HandleTypeDef *Handle, uint32_t BlockNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); + +bool SPIF_ReadAddress(SPIF_HandleTypeDef *Handle, uint32_t Address, uint8_t *Data, uint32_t Size); +bool SPIF_ReadPage(SPIF_HandleTypeDef *Handle, uint32_t PageNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); +bool SPIF_ReadSector(SPIF_HandleTypeDef *Handle, uint32_t SectorNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); +bool SPIF_ReadBlock(SPIF_HandleTypeDef *Handle, uint32_t BlockNumber, uint8_t *Data, uint32_t Size, uint32_t Offset); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Software/stm32project/USB_DEVICE/App/usb_device.c b/Software/stm32project/USB_DEVICE/App/usb_device.c index c4220b9..db0c79a 100644 --- a/Software/stm32project/USB_DEVICE/App/usb_device.c +++ b/Software/stm32project/USB_DEVICE/App/usb_device.c @@ -23,7 +23,8 @@ #include "usb_device.h" #include "usbd_core.h" #include "usbd_desc.h" -#include "usbd_hid.h" +#include "usbd_cdc.h" +#include "usbd_cdc_if.h" /* USER CODE BEGIN Includes */ @@ -72,7 +73,11 @@ void MX_USB_DEVICE_Init(void) { Error_Handler(); } - if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_HID) != USBD_OK) + if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) + { + Error_Handler(); + } + if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) { Error_Handler(); } diff --git a/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.c b/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.c new file mode 100644 index 0000000..ae3d499 --- /dev/null +++ b/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.c @@ -0,0 +1,328 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_cdc_if.c + * @version : v2.0_Cube + * @brief : Usb device for Virtual Com Port. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_if.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief Usb device library. + * @{ + */ + +/** @addtogroup USBD_CDC_IF + * @{ + */ + +/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions + * @brief Private types. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_TYPES */ + +/* USER CODE END PRIVATE_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines + * @brief Private defines. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_DEFINES */ +/* USER CODE END PRIVATE_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros + * @brief Private macros. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_MACRO */ + +/* USER CODE END PRIVATE_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables + * @brief Private variables. + * @{ + */ +/* Create buffer for reception and transmission */ +/* It's up to user to redefine and/or remove those define */ +/** Received data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; + +/** Data to send over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; + +/* USER CODE BEGIN PRIVATE_VARIABLES */ + +/* USER CODE END PRIVATE_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. + * @{ + */ + +extern USBD_HandleTypeDef hUsbDeviceFS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes + * @brief Private functions declaration. + * @{ + */ + +static int8_t CDC_Init_FS(void); +static int8_t CDC_DeInit_FS(void); +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); +static int8_t CDC_TransmitCplt_FS(uint8_t *pbuf, uint32_t *Len, uint8_t epnum); + +/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ + +/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ + +/** + * @} + */ + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = +{ + CDC_Init_FS, + CDC_DeInit_FS, + CDC_Control_FS, + CDC_Receive_FS, + CDC_TransmitCplt_FS +}; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) +{ + /* USER CODE BEGIN 3 */ + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + return (USBD_OK); + /* USER CODE END 3 */ +} + +/** + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) +{ + /* USER CODE BEGIN 4 */ + return (USBD_OK); + /* USER CODE END 4 */ +} + +/** + * @brief Manage the CDC class requests + * @param cmd: Command code + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + /* USER CODE BEGIN 5 */ + switch(cmd) + { + case CDC_SEND_ENCAPSULATED_COMMAND: + + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + + break; + + case CDC_SET_COMM_FEATURE: + + break; + + case CDC_GET_COMM_FEATURE: + + break; + + case CDC_CLEAR_COMM_FEATURE: + + break; + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + case CDC_SET_LINE_CODING: + + break; + + case CDC_GET_LINE_CODING: + + break; + + case CDC_SET_CONTROL_LINE_STATE: + + break; + + case CDC_SEND_BREAK: + + break; + + default: + break; + } + + return (USBD_OK); + /* USER CODE END 5 */ +} + +/** + * @brief Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will issue a NAK packet on any OUT packet received on + * USB endpoint until exiting this function. If you exit this function + * before transfer is complete on CDC interface (ie. using DMA controller) + * it will result in receiving more data while previous ones are still + * not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) +{ + /* USER CODE BEGIN 6 */ + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + return (USBD_OK); + /* USER CODE END 6 */ +} + +/** + * @brief CDC_Transmit_FS + * Data to send over USB IN endpoint are sent over CDC interface + * through this function. + * @note + * + * + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +{ + uint8_t result = USBD_OK; + /* USER CODE BEGIN 7 */ + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + if (hcdc->TxState != 0){ + return USBD_BUSY; + } + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + /* USER CODE END 7 */ + return result; +} + +/** + * @brief CDC_TransmitCplt_FS + * Data transmitted callback + * + * @note + * This function is IN transfer complete callback used to inform user that + * the submitted Data is successfully sent over USB. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum) +{ + uint8_t result = USBD_OK; + /* USER CODE BEGIN 13 */ + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); + /* USER CODE END 13 */ + return result; +} + +/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */ + +/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.h b/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.h new file mode 100644 index 0000000..8c32690 --- /dev/null +++ b/Software/stm32project/USB_DEVICE/App/usbd_cdc_if.h @@ -0,0 +1,131 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : usbd_cdc_if.h + * @version : v2.0_Cube + * @brief : Header for usbd_cdc_if.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_IF_H__ +#define __USBD_CDC_IF_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief For Usb device. + * @{ + */ + +/** @defgroup USBD_CDC_IF USBD_CDC_IF + * @brief Usb VCP device module + * @{ + */ + +/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines + * @brief Defines. + * @{ + */ +/* Define size for the receive and transmit buffer over CDC */ +#define APP_RX_DATA_SIZE 1024 +#define APP_TX_DATA_SIZE 1024 +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types + * @brief Types. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros + * @brief Aliases. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** CDC Interface callback. */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + +/** + * @} + */ + +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_CDC_IF_H__ */ + diff --git a/Software/stm32project/USB_DEVICE/App/usbd_desc.c b/Software/stm32project/USB_DEVICE/App/usbd_desc.c index 2759fc8..0d4fa6c 100644 --- a/Software/stm32project/USB_DEVICE/App/usbd_desc.c +++ b/Software/stm32project/USB_DEVICE/App/usbd_desc.c @@ -65,10 +65,10 @@ #define USBD_VID 1155 #define USBD_LANGID_STRING 1033 #define USBD_MANUFACTURER_STRING "STMicroelectronics" -#define USBD_PID_FS 22315 -#define USBD_PRODUCT_STRING_FS "STM32 Human interface" -#define USBD_CONFIGURATION_STRING_FS "HID Config" -#define USBD_INTERFACE_STRING_FS "HID Interface" +#define USBD_PID_FS 22336 +#define USBD_PRODUCT_STRING_FS "BALISE_GPS" +#define USBD_CONFIGURATION_STRING_FS "CDC Config" +#define USBD_INTERFACE_STRING_FS "CDC Interface" #define USB_SIZ_BOS_DESC 0x0C @@ -164,8 +164,8 @@ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = 0x00, /*bcdUSB */ #endif /* (USBD_LPM_ENABLED == 1) */ 0x02, - 0x00, /*bDeviceClass*/ - 0x00, /*bDeviceSubClass*/ + 0x02, /*bDeviceClass*/ + 0x02, /*bDeviceSubClass*/ 0x00, /*bDeviceProtocol*/ USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ LOBYTE(USBD_VID), /*idVendor*/ diff --git a/Software/stm32project/USB_DEVICE/Target/usbd_conf.c b/Software/stm32project/USB_DEVICE/Target/usbd_conf.c index 183c350..587fcd1 100644 --- a/Software/stm32project/USB_DEVICE/Target/usbd_conf.c +++ b/Software/stm32project/USB_DEVICE/Target/usbd_conf.c @@ -23,7 +23,7 @@ #include "stm32l4xx_hal.h" #include "usbd_def.h" #include "usbd_core.h" -#include "usbd_hid.h" +#include "usbd_cdc.h" /* USER CODE BEGIN Includes */ @@ -342,9 +342,11 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); /* USER CODE END EndPoint_Configuration */ - /* USER CODE BEGIN EndPoint_Configuration_HID */ - HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0x100); - /* USER CODE END EndPoint_Configuration_HID */ + /* USER CODE BEGIN EndPoint_Configuration_CDC */ + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); + HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); + /* USER CODE END EndPoint_Configuration_CDC */ return USBD_OK; } @@ -796,7 +798,7 @@ void USBD_LL_Delay(uint32_t Delay) */ void *USBD_static_malloc(uint32_t size) { - static uint32_t mem[(sizeof(USBD_HID_HandleTypeDef)/4)+1];/* On 32-bit boundary */ + static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ return mem; } diff --git a/Software/stm32project/USB_DEVICE/Target/usbd_conf.h b/Software/stm32project/USB_DEVICE/Target/usbd_conf.h index 7903895..adff527 100644 --- a/Software/stm32project/USB_DEVICE/Target/usbd_conf.h +++ b/Software/stm32project/USB_DEVICE/Target/usbd_conf.h @@ -74,8 +74,6 @@ #define USBD_LPM_ENABLED 1U /*---------- -----------*/ #define USBD_SELF_POWERED 1U -/*---------- -----------*/ -#define HID_FS_BINTERVAL 0xAU /****************************************/ /* #define for FS and HS identification */ diff --git a/Software/stm32project/projet vf.ioc b/Software/stm32project/projet vf.ioc index 821f075..2a25647 100644 --- a/Software/stm32project/projet vf.ioc +++ b/Software/stm32project/projet vf.ioc @@ -1,18 +1,22 @@ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_VREFINT ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_TEMPSENSOR +ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_9 ADC1.CommonPathInternal=ADC_CHANNEL_VREFINT|ADC_CHANNEL_TEMPSENSOR|null|null ADC1.ContinuousConvMode=ENABLE ADC1.ExternalTrigConv=ADC_EXTERNALTRIG_T2_TRGO -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,NbrOfConversion,ContinuousConvMode,ExternalTrigConv,master,CommonPathInternal -ADC1.NbrOfConversion=2 +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,NbrOfConversion,ContinuousConvMode,ExternalTrigConv,master,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,CommonPathInternal +ADC1.NbrOfConversion=3 ADC1.NbrOfConversionFlag=1 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE +ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.Rank-1\#ChannelRegularConversion=2 +ADC1.Rank-2\#ChannelRegularConversion=3 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5 +ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_640CYCLES_5 ADC1.master=1 CAD.formats=[] CAD.pinconfig=Dual @@ -40,6 +44,8 @@ Dma.Request1=LPUART_RX Dma.RequestsNb=2 File.Version=6 GPIO.groupedBy=Group By Peripherals +I2C1.IPParameters=Timing +I2C1.Timing=0x00202538 I2C3.CustomTiming=Disabled I2C3.I2C_Speed_Mode=I2C_Fast_Plus I2C3.IPParameters=Timing,I2C_Speed_Mode,CustomTiming @@ -52,49 +58,61 @@ Mcu.CPN=STM32L432KCU6 Mcu.Family=STM32L4 Mcu.IP0=ADC1 Mcu.IP1=DMA -Mcu.IP10=USB_DEVICE -Mcu.IP2=I2C3 -Mcu.IP3=LPUART1 -Mcu.IP4=NVIC -Mcu.IP5=RCC -Mcu.IP6=SYS -Mcu.IP7=TIM2 -Mcu.IP8=TIM7 -Mcu.IP9=USB -Mcu.IPNb=11 +Mcu.IP10=USART1 +Mcu.IP11=USB +Mcu.IP12=USB_DEVICE +Mcu.IP2=I2C1 +Mcu.IP3=I2C3 +Mcu.IP4=LPUART1 +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=SPI1 +Mcu.IP8=SYS +Mcu.IP9=TIM2 +Mcu.IPNb=13 Mcu.Name=STM32L432K(B-C)Ux Mcu.Package=UFQFPN32 -Mcu.Pin0=PC14-OSC32_IN (PC14) -Mcu.Pin1=PC15-OSC32_OUT (PC15) -Mcu.Pin10=PA14 (JTCK-SWCLK) -Mcu.Pin11=PB3 (JTDO-TRACESWO) -Mcu.Pin12=PB4 (NJTRST) -Mcu.Pin13=VP_ADC1_TempSens_Input -Mcu.Pin14=VP_ADC1_Vref_Input -Mcu.Pin15=VP_SYS_VS_Systick -Mcu.Pin16=VP_TIM2_VS_ClockSourceINT -Mcu.Pin17=VP_TIM7_VS_ClockSourceINT -Mcu.Pin18=VP_USB_DEVICE_VS_USB_DEVICE_HID_FS -Mcu.Pin2=PA1 -Mcu.Pin3=PA2 -Mcu.Pin4=PA3 -Mcu.Pin5=PA4 +Mcu.Pin0=PA1 +Mcu.Pin1=PA2 +Mcu.Pin10=PA9 +Mcu.Pin11=PA10 +Mcu.Pin12=PA11 +Mcu.Pin13=PA12 +Mcu.Pin14=PA13 (JTMS-SWDIO) +Mcu.Pin15=PA14 (JTCK-SWCLK) +Mcu.Pin16=PB3 (JTDO-TRACESWO) +Mcu.Pin17=PB4 (NJTRST) +Mcu.Pin18=PB5 +Mcu.Pin19=PB6 +Mcu.Pin2=PA3 +Mcu.Pin20=PB7 +Mcu.Pin21=VP_ADC1_TempSens_Input +Mcu.Pin22=VP_ADC1_Vref_Input +Mcu.Pin23=VP_SYS_VS_Systick +Mcu.Pin24=VP_TIM2_VS_ClockSourceINT +Mcu.Pin25=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS +Mcu.Pin26=VP_NimaLTD.I-CUBE-SPIF_VS_DriverJjSPIF_1.0.0_2.3.2 +Mcu.Pin3=PA4 +Mcu.Pin4=PA5 +Mcu.Pin5=PA6 Mcu.Pin6=PA7 -Mcu.Pin7=PA11 -Mcu.Pin8=PA12 -Mcu.Pin9=PA13 (JTMS-SWDIO) -Mcu.PinsNb=19 -Mcu.ThirdPartyNb=0 +Mcu.Pin7=PB0 +Mcu.Pin8=PB1 +Mcu.Pin9=PA8 +Mcu.PinsNb=27 +Mcu.ThirdParty0=NimaLTD.I-CUBE-SPIF.2.3.2 +Mcu.ThirdPartyNb=1 Mcu.UserConstants= Mcu.UserName=STM32L432KCUx MxCube.Version=6.10.0 MxDb.Version=DB.6.0.100 -NVIC.ADC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.ADC1_IRQn=true\:0\:0\:true\:false\:true\:true\:true\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true -NVIC.DMA2_Channel7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Channel1_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA2_Channel7_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.EXTI1_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true +NVIC.EXTI9_5_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.LPUART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true @@ -104,11 +122,16 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false -NVIC.TIM7_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.USB_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NimaLTD.I-CUBE-SPIF.2.3.2.DriverJjSPIF=true +NimaLTD.I-CUBE-SPIF.2.3.2.DriverJjSPIF_Checked=true +NimaLTD.I-CUBE-SPIF.2.3.2.IPParameters=DriverJjSPIF +NimaLTD.I-CUBE-SPIF.2.3.2_SwParameter=DriverJjSPIF\:true; PA1.Locked=true PA1.Signal=GPIO_Output +PA10.Mode=I2C +PA10.Signal=I2C1_SDA PA11.Mode=Device PA11.Signal=USB_DM PA12.Mode=Device @@ -121,13 +144,30 @@ PA2.Mode=Asynchronous PA2.Signal=LPUART1_TX PA3.Mode=Asynchronous PA3.Signal=LPUART1_RX -PA4.Locked=true PA4.Signal=ADCx_IN9 +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO PA7.GPIOParameters=GPIO_Pu PA7.GPIO_Pu=GPIO_NOPULL PA7.Locked=true PA7.Mode=I2C PA7.Signal=I2C3_SCL +PA8.GPIOParameters=GPIO_ModeDefaultEXTI +PA8.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PA8.Locked=true +PA8.Signal=GPXTI8 +PA9.Mode=I2C +PA9.Signal=I2C1_SCL +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=FLASH_CS +PB0.Locked=true +PB0.Signal=GPIO_Output +PB1.GPIOParameters=GPIO_ModeDefaultEXTI +PB1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PB1.Locked=true +PB1.Signal=GPXTI1 PB3\ (JTDO-TRACESWO).Locked=true PB3\ (JTDO-TRACESWO).Signal=SYS_JTDO-SWO PB4\ (NJTRST).GPIOParameters=GPIO_Pu @@ -135,16 +175,18 @@ PB4\ (NJTRST).GPIO_Pu=GPIO_NOPULL PB4\ (NJTRST).Locked=true PB4\ (NJTRST).Mode=I2C PB4\ (NJTRST).Signal=I2C3_SDA -PC14-OSC32_IN\ (PC14).Locked=true -PC14-OSC32_IN\ (PC14).Signal=GPXTI14 -PC15-OSC32_OUT\ (PC15).Locked=true -PC15-OSC32_OUT\ (PC15).Signal=GPXTI15 +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI1_MOSI +PB6.Mode=Asynchronous +PB6.Signal=USART1_TX +PB7.Mode=Asynchronous +PB7.Signal=USART1_RX PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false +ProjectManager.CoupleFile=true ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true @@ -170,7 +212,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_I2C3_Init-I2C3-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_TIM7_Init-TIM7-false-HAL-true,9-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_I2C3_Init-I2C3-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,9-MX_I2C1_Init-I2C1-false-HAL-true,10-MX_USART1_UART_Init-USART1-false-HAL-true,11-MX_SPI1_Init-SPI1-false-HAL-true RCC.ADCFreq_Value=48000000 RCC.AHBFreq_Value=40000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -220,32 +262,39 @@ RCC.VCOOutputFreq_Value=80000000 RCC.VCOSAI1OutputFreq_Value=96000000 SH.ADCx_IN9.0=ADC1_IN9,IN9-Single-Ended SH.ADCx_IN9.ConfNb=1 -SH.GPXTI14.0=GPIO_EXTI14 -SH.GPXTI14.ConfNb=1 -SH.GPXTI15.0=GPIO_EXTI15 -SH.GPXTI15.ConfNb=1 +SH.GPXTI1.0=GPIO_EXTI1 +SH.GPXTI1.ConfNb=1 +SH.GPXTI8.0=GPIO_EXTI8 +SH.GPXTI8.ConfNb=1 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 +SPI1.CalculateBaudRate=5.0 MBits/s +SPI1.DataSize=SPI_DATASIZE_8BIT +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER TIM2.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger TIM2.Period=10000-1 TIM2.Prescaler=400-1 TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE -TIM7.IPParameters=Prescaler,Period -TIM7.Period=8000-1 -TIM7.Prescaler=10000-1 -USB_DEVICE.CLASS_NAME_FS=HID -USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS -USB_DEVICE.VirtualMode=Hid -USB_DEVICE.VirtualModeFS=Hid_FS +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USB_DEVICE.CLASS_NAME_FS=CDC +USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS,PRODUCT_STRING_CDC_FS +USB_DEVICE.PRODUCT_STRING_CDC_FS=BALISE_GPS +USB_DEVICE.VirtualMode=Cdc +USB_DEVICE.VirtualModeFS=Cdc_FS VP_ADC1_TempSens_Input.Mode=IN-TempSens VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input VP_ADC1_Vref_Input.Mode=IN-Vrefint VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input +VP_NimaLTD.I-CUBE-SPIF_VS_DriverJjSPIF_1.0.0_2.3.2.Mode=DriverJjSPIF +VP_NimaLTD.I-CUBE-SPIF_VS_DriverJjSPIF_1.0.0_2.3.2.Signal=NimaLTD.I-CUBE-SPIF_VS_DriverJjSPIF_1.0.0_2.3.2 VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT -VP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer -VP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT -VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Mode=HID_FS -VP_USB_DEVICE_VS_USB_DEVICE_HID_FS.Signal=USB_DEVICE_VS_USB_DEVICE_HID_FS +VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS +VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS board=custom isbadioc=false