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How to debug
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How to debug
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1. Timming issue
ERROR: [XOCC 18-1000] Routing results verification failed due to partially-conflicted nets (Up to first 10 of violated nets): xcl_design_i/expanded_region/u_ocl_region/dr_i/m_axi_interconnect_M00_AXI/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/first_mi_word_q xcl_design_i/expanded_region/u_ocl_region/dr_i/m_axi_interconnect_M00_AXI/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/first_word xcl_design_i/expanded_region/u_ocl_region/dr_i/m_axi_interconnect_M00_AXI/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/last_beat xcl_design_i/expanded_region/u_ocl_region/dr_i/m_axi_interconnect_M00_AXI/s02_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/p_15_in xcl_design_i/base_region/pr_isolation_expanded/gate_pr/U0/gpio_core_1/gpio_io_o[1] xcl_design_i/base_region/pr_isolation_expanded/regslice_control_mgntpf/inst/ar_pipe/Q[2] xcl_design_i/base_region/pr_isolation_expanded/regslice_control_mgntpf/inst/ar_pipe/Q[24] xcl_design_i/base_region/pr_isolation_expanded/regslice_control_mgntpf/inst/ar_pipe/Q[27] xcl_design_i/base_region/pr_isolation_expanded/regslice_control_mgntpf/inst/ar_pipe/Q[30] xcl_design_i/base_region/pr_isolation_expanded/regslice_control_mgntpf/inst/aw_pipe/Q[18]
vivado->_x/link/vivado/prj/prj.runs/impl_1/pfm_top_wrapper_routed_error.dcp
Tcl-console->
report_timing_summary
report_route_status
2. reports:
a. vivado_hls.log
b. system_estimate_pcaf_fpga.hw_emu.xilinx_vcu1525_dynamic_5_1.xtxt
Latency Information (clock cycles)
Compute Unit Kernel Name Module Name Start Interval Best Case Avg Case Worst Case
------------ ----------- --------------------- -------------- --------- -------- ----------
pcaf_fpga_1 pcaf_fpga read_query_pca 47 47 47 47
pcaf_fpga_1 pcaf_fpga read_query_or 39 39 39 39
pcaf_fpga_1 pcaf_fpga read_feature_pca15614 110 110 110 110
pcaf_fpga_1 pcaf_fpga d_copy_oc2g 21 21 21 21
pcaf_fpga_1 pcaf_fpga pcaf_fpga 440 ~ 19040 439 4539 19039
c._x/link/vivado/prj/prj.run/impl_1/runme.log
Finally sysmte clock frequency
d. _x/link/vivado/prj/prj.run/impl_1/x..rpt
VIOLATED
c.utilization and clk cycles for each function: _x/report/kernelname.sf|hw_emu|hw.../sys....txt
_x/report/link/kernel_unit_placed.rpt
3. The unroll factor doesn't work:
There is some information from the vivado_hls.log
"WARNING: [XFORM 203-505] Ignored pipeline directive for loop 'dist_calc_or21' (/home/xiaojia.song/SDAccel_Examples_2018_2/getting_started/host/PCAF_FPGA_sub_v2s2sub45_BFS_32_05/src/pcaf_fpga.cpp:172) because its parent loop or function is pipelined.
"
SO the resason for this issue is the parent loop is pipilined and then the unroll pragma is ignored.
4. Hanging happpens during hardwareEmulation
a. Increase the hls::stream depth value;
b. Make sure the producer and the consumer produce and consume equal numer of data;