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<!DOCTYPE html>
<html lang = en>
<head>
<meta charset="utf-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<title>My Journey</title>
<link rel="stylesheet" type="text/css" href="./css/style.css">
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<body>
<header>
<div class="navbar container">
<div class="logo"><h1>My Summer Journey</h1></div>
</div>
</header>
<div class="articles">
<div class="article-heading">
<h5>projects</h5>
<h6>Check Out Here</h6>
</div>
<div class="cards container">
<div class="card-container one">
<div class="img-holder">
<a href="https://github.com/BalaDhinesh/Virtual-FPGA-Lab">Code</a>
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<div class="card-text">
<h4>Virtual FPGA Lab</h4>
<p>This project is an amazing project that works by taking the advantage of the VIZ Visualization feature in the Makerchip platform, and hence, provides visualizations of basic peripherals on an FPGA, thereby mimicking the physical lab experience. This aims to help students to learn by visualizing.<br><a href="https://github.com/BalaDhinesh/Virtual-FPGA-Lab">Check Out Here</a></p>
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</div>
<div class="card-container two">
<div class="img-holder">
<a href="https://github.com/mayank-kabra2001/tensor-core-viz">Code</a>
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<div class="card-text">
<h4>TensorCORE</h4>
<p>“Vector architectures grab sets of data elements scattered about memory, place them into large, sequential register files, operate on data in those register files, and then disperse the results back into memory. A single instruction operates on vectors of data, which results in dozens of register–register operations on independent data elements.”
<br><br><a href="https://github.com/mayank-kabra2001/tensor-core-viz">Check Out Here</a></p>
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</div>
<div class="card-container three">
<div class="img-holder">
<a href="https://github.com/mayank-kabra2001/WARPV-TSMC/tree/main">Code</a>
</div>
<div class="card-text">
<h4>Warp-V</h4>
<p>WARP-V is a demonstration and exploration vehicle for the flexibility that is possible using the emerging "transaction-level design" methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable.<br><a href="#">Check Out Here</a><</p>
</div>
</div>
</div>
<div class="article-heading">
<h2>Read the journey below</h2>
<p> Don't forget to check out related tags.</p>
</div>
</div>
<div class="container">
<div class="hero">
</div>
<main>
<h2>Experiencing Google summer of Code, Without Google summer of Code</h2>
<div class="profile-container">
<div class="profile">
<div class="img-container">
</div>
<div class="text">
<h3>Mayank Kabra</h3>
<p>Computer Architect<br> VLSI enthusiast</p>
</div>
</div>
<div class="button">
<a href="https://www.linkedin.com/in/mayank-kabra-6993701ab/" target="_blank" class="btn">Connect</a>
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<div class="content">
<blockquote style="border-radius: 3rem; font-size: 1.6rem; font-weight: bold; line-height: 3rem; letter-spacing: 0.15rem;">"Hi, this summer was very special to me. Though, it started with the disappointment of not being funded by Google for the <a href="https://summerofcode.withgoogle.com/organizations/5307481321897984/"> GSoC </a> project. My mentor <a href="https://www.linkedin.com/in/steve-hoover-a44b607/"> Steven F. Hoover </a> gave me a chance to prove myself that I was worth a shot. This time, instead of working on one particular project, I got something big to do.<br><br>
I am thrilled to share my journey of these 2.5 months with you all.
To begin with, On 17th May 2020, the GSoC result was declared, and for me, it said, “Unfortunately, none of your proposals were accepted this year." I was a bit surprised and tensed. I couldn't think of what to do next.<br><br>However, I was quite confident in myself about my idea and talked to my mentor (Steve Hoover). The next day, he invited me to discuss my summer plans. He gave me an opportunity to choose “any” Gsoc project I want to contribute to for VIRTUAL FPGA LAB.<br><br> After that let's see what happened." </blockquote>
<hr>
<h1 style="text-align: center; text-decoration: underline;">Projects</h1>
<h1>➢ Working on Virtual FPGA Lab</h1>
<blockquote><b>Description:</b> This project works by taking the advantage of the VIZ Visualization feature in the Makerchip platform, and provide visualizations of basic peripherals on an FPGA, thereby mimicking the physical lab experience.</blockquote>
<p>So, I was invited to every GSOC weekly meet along with all the GSoC participants and mentors. We(Me and the GSoC participant) started working on that project together. I found everyone to be very supportive and humble. Also, I got invited to attend every week sync up project meet with project mentors to show our work.<br><br>
After struggling for a few days, we were able to complete our first part, i.e design of the counter and controlling it at pin level and visualization of the actual result of an FPGA on the Makerchip platform. Then we divided our work I shifted my focus to the backend on how to process that TLV (<a href="https://mayank-kabra2001.github.io/My-BlogPost/">Transactional level Verilog file</a>) in an actual FPGA. We then use sandpiper(tool to convert TL-V to system-Verilog/Verilog) to get the Verilog file to run in actual FPGA. Now, if a new user tries to run, it won't be able to run the FPGA flow, so we thought of making it also automata - that’s where the fun started. Vivado and open-source toolchain support TCL flow. Then I created a bash script to automate the workflow for the user, which in the end will call a TCL script that will contain the flow of tools. <br><br>
The best part being that everything was new to me as I was neither exposed to TCL and bash script, and also to the commands for tools.
By working on this project, I understood how the architecture inside FPGA works.
Then we tried to optimized the user experience and also created many works in the maker chip platform. This blog has a huge mention of all our work. Please refer to <a href="https://medium.com/@m.baladhinesh/fpgas-in-your-browser-bb92be1c1fa3">this</a>. <br>
</p>
<div class="tags">
<p>tags:</p>
<a href="https://medium.com/@m.baladhinesh/fpgas-in-your-browser-bb92be1c1fa3">Student Blog</a>
<a href="http://www.makerchip.com/">Makerchip</a>
<a href="https://www.redwoodeda.com/tl-verilog">TLV</a>
<a href="https://www.xilinx.com/products/silicon-devices/fpga/what-is-an-fpga.html">FPGA</a>
<a href="https://www.tutorialspoint.com/tcl-tk/index.htm">TCL</a>
</div>
<br>
<hr style="margin-left: 9rem; margin-right: 9rem;">
<br>
<h1>➢ Working with MYTH CORE</h1>
<blockquote><b>Description:</b> MYTH is a workshop that has recieved a great deal of attention in the RISC-V community for enabling students to learn at a pace never before possible through the use of TL-Verilog and Makerchip where you will understand:<br>
• RISC-V specs<br>
• RISC-V software<br>
• How to implement RISC-V basic specs using TL-Verilog<br>
• Simulate your own RISC-V core</blockquote>
<p>MYTH is a 5 day workshop where we create our own 5 stage RV32I supporting stall and forwarding.
In this project I extended the MYTH core( RV32I written in TLV ) to support it on FPGA and to generate the bitstream also supporting the 7 segment where you can hook your any register to see its value and can also change the speed of your code to see the updating of register properly (e.g 1 seconds). </p>
<div class="tags">
<p>tags:</p>
<a href="#">GSoC Project</a>
<a href="#">Myth Core</a>
<a href="#">FPGA</a>
</div>
<blockquote style="border-radius: 3rem; font-size: 1.6rem; font-weight: bold; line-height: 3rem; letter-spacing: 0.15rem;">But where is the point? This time instead of working on one particular project.<br> Let's see what else I got :</blockquote>
<br>
<hr style="margin-left: 9rem; margin-right: 9rem;">
<br>
<h1>➢ TensorCORE</h1>
<blockquote><b>Description:</b> Vector Processor architectures have seen a resurgence in mainstream ML and DL applications. This project focused on creating a Vector Coprocessor based on the RISCV vector extension that will connect to a Sequential RISC-V processor(e.g., WARP V). This tensor core processor will work as a deep learning accelerator.</blockquote>
<p>The work started after a few struggles to understand ARA(vector processor written in Verilog) architecture. Initially, I was supposed to understand the SRAM design and create a visualization that can mimic the working of SRAM in ARA. Then after that Visualization of the sequencer(to sequence the instruction correctly to handle all stalls and bubbles) was needed.
This project was very new in itself and also very knowledgeable and informative for me to understand the design of the VECTOR processor.
</p>
<div class="tags">
<p>tags:</p>
<a href="#">GSoC Project</a>
<a href="https://medium.com/@nmishra9/tensorcore-extension-for-deep-learning-41728fc22495">Student Blog</a>
<a href="https://github.com/pulp-platform/ara">ARA</a>
<a href="https://en.wikipedia.org/wiki/Vector_processor#:~:text=In%20computing%2C%20a%20vector%20processor,arrays%20of%20data%20called%20vectors">Vector processor</a>
</div>
<br>
<hr style="margin-left: 9rem; margin-right: 9rem;">
<br>
<h1>➢ Warp-V Vizualization</h1>
<blockquote><b>Description:</b> WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging "transaction-level design" methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.</blockquote>
<p> I was also given the task to change the visualization of Warp-V (an open-source RISC-V-based configurable free core)<br> .For that, I understood the working and architecture of Warp-V and then created a visualization that can also support the visualization of a multicore processor by parameterizing the variables. I get to know about the power possessed by M4 macros which can highly parametrize your code.</p>
<div class="tags">
<p>tags:</p>
<a href="https://warp-v.org/">Warp-V</a>
<a href="https://riscv.org/">RISC-V</a>
</div>
<br>
<hr style="margin-left: 9rem; margin-right: 9rem;">
<br>
<h1>➢ Working with Yosys</h1>
<blockquote><b>Description:</b> Yosys is a framework for Verilog RTL synthesis.Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base.</blockquote>
<p>In this project, From the Warp-V which is configurable, we need to generate a 5-stage pipeline(RV32I) processor and integrate that with register file, additional adder, and SRAM that will contain both instruction memory and Data memory(Von Neumann Architecture). Then after customizing our core we need to get a synthesized netlist of the core from the open-source synthesis tool Yosys. In this, I explored more about the Yosys toolchain and how to get a netlist. <br>
I would also like to extend this project to run the whole open-source toolchain for ASIC flow to tape out the core on silicon. </p>
<div class="tags">
<p>tags:</p>
<a href="http://www.clifford.at/yosys/about.html ">Yosys</a>
<a href="">Open-Source</a>
</div>
<br>
<hr>
<br>
<blockquote style="border-radius: 3rem; font-size: 1.6rem; font-weight: bold; line-height: 3rem; letter-spacing: 0.15rem;">"By doing all these projects, I explored a lot of new things related to FPGA flow, understanding the FPGA tools, working on FPGA tools, understanding the design of FPGA, generating netlist, understanding different architectures, and whatnot.
I cannot thank Steve Hoover enough for giving me this opportunity to learn a lot out of this summer."</blockquote>
</div>
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