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Move CSR space to 0x8000_0000
1 parent 2e5319d commit 4c7d979

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5 files changed

+6
-7
lines changed

5 files changed

+6
-7
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MEMORY_MAP.md

+2-3
Original file line numberDiff line numberDiff line change
@@ -21,14 +21,13 @@ Note: might want to take advantage of RV32's single-instruction calls relative t
2121

2222
bit 31 -> cache bypass
2323
bits 26..24 -> region (3 bits)
24-
0 = trap
25-
1 = I/O space
24+
0 = control/status registers (TODO: trap if accessed with bit 31 cleared)
2625
3 = rom
2726
4..7 = sdram (in other words: bit 26 -> SDRAM(1) / non-SDRAM(0))
2827
bit 23..0 -> address within 16M region
2928
(not necessarily fully decoded)
3029

31-
CPU external address bus is effectively 28 bits wide.
30+
CPU external address bus is effectively 27 bits wide (though bit 31 is also used to trap NULL pointer dereferences).
3231

3332

3433
## Detailed description

firmware/prebuilt/test_dhrystone.bin

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firmware/prebuilt/test_dhrystone.objdump.txt

+2-2
Original file line numberDiff line numberDiff line change
@@ -884,10 +884,10 @@ Disassembly of section .text:
884884
040009b0 <_write>:
885885
40009b0: 00060513 mv a0,a2
886886
40009b4: 00000793 li a5,0
887-
40009b8: 810006b7 lui a3,0x81000
887+
40009b8: 800006b7 lui a3,0x80000
888888
40009bc: 00a7c463 blt a5,a0,40009c4 <_write+0x14>
889889
40009c0: 00008067 ret
890-
40009c4: 0106a703 lw a4,16(a3) # 81000010 <__stack+0x7b000010>
890+
40009c4: 0106a703 lw a4,16(a3) # 80000010 <__stack+0x7a000010>
891891
40009c8: 00177713 andi a4,a4,1
892892
40009cc: fe071ce3 bnez a4,40009c4 <_write+0x14>
893893
40009d0: 00f58733 add a4,a1,a5

rtl/memory_map.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
`ifndef MEMORY_MAP_SV
22
`define MEMORY_MAP_SV
33

4-
localparam ADDR_CSR_START = 27'h1000000;
4+
localparam ADDR_CSR_START = 27'h0000000;
55
localparam ADDR_SDRAM_START = 27'h4000000;
66

77
function automatic addr_is_csr(input[26:0] addr);

sdk/include/Poly94_hw.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ enum { SDRAM_START = 0x04000000 };
1111

1212
/* Control/status registers (with cache bypass bit set) */
1313

14-
#define _HW (*(struct top volatile*)0x81000000)
14+
#define _HW (*(struct top volatile*)0x80000000)
1515

1616

1717
/* RISC-V stuff */

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