Spring cleaning of working copy

Author: mcejp

README.md

@@ -33,6 +33,9 @@ make prog
 # Verilator (currently not working with SDRAM model)
 make sim
 
+# Verilator with options
+BOOTROM=firmware/build/test_framebuffer.bin DUMP_FRAMEBUF=framebuffer.ppm NUM_CYCLES=4000000 make sim
+
 # cocotb
 make -f Makefile.coco
 ```

doc/sdram-bandwidth.md

@@ -10,3 +10,7 @@
 | 100 MHz      | 640x480 /8             | 9.2 %                            |
 
 Justifies having separate code RAM to do something in the meantime?
+
+
+TODO: profile access latency
+TODO: render waveforms

rtl/VGA_Timing_Generator.sv

@@ -39,8 +39,8 @@ localparam V_BACK_PORCH = 31;
 localparam V_TOTAL = V_VISIBLE + V_FRONT_PORCH + 2 + V_BACK_PORCH;
 
 // Clock divider; probably should be externalized
-logic[$clog2(CLK_DIV)-1:0] prescaler;
-logic clk_en;       // pipelined to minimize extra cost
+logic[$clog2(CLK_DIV)-1:0] prescaler = 0;
+logic clk_en = 0;       // pipelined to minimize extra cost
 
 // Line/pixel counting
 

rtl/Video_Ctrl.sv

@@ -123,7 +123,7 @@ always @ (posedge clk_i) begin
       end
     end else if (sdram_rd && sdram_rdy && waitstate == 0) begin
 `ifdef VERBOSE
-      $display("VIDEO_CTRL: got data word [%03d] => %04Xh", line_write_ptr, sdram_rdata);
+      $display("VIDEO_CTRL: got data word [%03d:%03d] => %04Xh", line_no, line_write_ptr, sdram_rdata);
 `endif
       if (line_write_ptr[BURST_BITS-1:0] == BURST_LEN - 1) begin
 `ifdef VERBOSE

rtl/top.sv

@@ -31,7 +31,7 @@ module top
     parameter CLK_SYS_HZ = 50_000_000;
 
 `ifndef SYNTHESIS
-    wire pixel_valid /* verilator public */ = timing1.blank_n == 1 && timing1.valid;
+    wire pixel_valid /* verilator public */ = (timing1.blank_n == 1) && timing1.valid;
 `endif
 
     assign sdram_cke = 1'b1;

sim/sim_main.cpp

@@ -54,9 +54,8 @@ int main(int argc, char** argv, char** env) {
    // top.rootp->cpu.resetn = 0;
 
    VerilatedVcdC trace;
-   top.trace(&trace, 99);
 
-   // trace.open("sim.vcd");
+   top.trace(&trace, 99);
 
    // execute $initial commands -- must be done before loading ROM or forcing any registers
    top.eval();
@@ -112,6 +111,12 @@ int main(int argc, char** argv, char** env) {
          framebuffer[pixel_i] = top.top->color2;
          pixel_i++;
       }
+
+      // if (half_cycle == 1000000) {
+      //    ;
+
+      //    trace.open("sim.vcd");
+      // }
    }
 
    fprintf(stderr, "Simulated %ld cycles\n", half_cycle / 2);