From 0b17abd42dd4df3e5a1576d1c41655be0e58845a Mon Sep 17 00:00:00 2001 From: Dominik Arominski Date: Wed, 26 Nov 2025 15:36:47 +0100 Subject: [PATCH] Fix to interleaving interrupts with floating-point operations The size of the array holding the floating point registers was extended by a factor of 8, as many as available PL-PS interrupts on an Ultrascale+ platform. --- src/platform/zynqmp/executor/asm_vectors.S | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/platform/zynqmp/executor/asm_vectors.S b/src/platform/zynqmp/executor/asm_vectors.S index a19f3d5..f2e8a8c 100644 --- a/src/platform/zynqmp/executor/asm_vectors.S +++ b/src/platform/zynqmp/executor/asm_vectors.S @@ -52,14 +52,21 @@ .globl FPUStatus /* - * FPUContextSize is the size of the array where floating point registers are + * FPUContextSize is the size of the array (528) where floating point registers are * stored when required. The default size corresponds to the case when there is no * nested interrupt. If there are nested interrupts in application which are using * floating point operation, the size of FPUContextSize need to be increased as per * requirement */ -.set FPUContextSize, 528 +// The Zynq Ultrascale+ has 16 PL-PS interrupt IDs available, technically allowing +// for that much of interleaving, however it is currently not supported in BMboot: +// the payloads can define 8 priority levels and that is the maximum number of interleaving +// that can be expected in the user code. To fully accomodate that possibility +// and to avoid any issues, the context size below is extended by the same factor as the number +// of priority levels, from 528 to 4224. The solution was tested on an Ultrascale+. + +.set FPUContextSize, 4224 .macro saveregister stp X0,X1, [sp,#-0x10]!