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Fiscarelli
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CEP Release v3.3
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‎README.md

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@@ -8,7 +8,7 @@
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<img src="./doc/cep_logo.jpg" width="721" height="300">
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</p>
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<p align="center">
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<img src="./doc/version3.2.jpg" width="98" height="60">
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<img src="./doc/version3.3.jpg" width="98" height="60">
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</p>
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<p align="center">
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Copyright 2021 Massachusetts Institute of Technology
@@ -25,7 +25,7 @@ For CEP v3.1+, the full LLKI has been added. This includes the Surrogate Root o
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### Please check the [Release Notes](./RELEASE_NOTES.md) to understand what has changed and a list of known issues.
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<br/><br/>
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<br/>
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<p align="center">
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<img src="./doc/cep_v3.1_architecture.jpg">
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./+++++++++++oo+++: +oo++o++++o+o+oo+oo.- `s+++s`-
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.--:---:-:-::-::` -::::::::::::::::::. :::::.
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Common Evaluation Platform v3.20
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Common Evaluation Platform v3.30
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Copyright 2021 Massachusetts Institute of Technology
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Built upon the SiFive Freedom U500 Platform using
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A partial output should be similar to:
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```sh
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*** CEP Tag=CEPTest CEP HW VERSION = v3.20 was built on Apr 15 2021 09:22:15 ***
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*** CEP Tag=CEPTest CEP HW VERSION = v3.30 was built on Apr 15 2021 09:22:15 ***
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CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x0000000700000000, 0x0000000800000000, 0x0000000600000000, 0x0000000c00000000 ScratchPad=0x0000002000800000
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gSkipInit=0/0
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gverbose=0/0

‎RELEASE_NOTES.md

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@@ -121,4 +121,14 @@ v3.2 - (16 April 2021)
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* Linux tests updated and expanded
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* New tests added to cosim focused on LLKI and Scratchpad RAM
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v3.3 - (19 May 2021)
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* Increased capacity for LLKI key size including larger KeyRAM (2048 64-bit words)
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* Added Cosim JTAG/OpenOCD
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* Stability fixes for cep_diag under Linux
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* Virtual Address TLB test suite is added to regression (not 100% complete)
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* Expanded cep_diag
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* New simulation ONLY interrupt tests for CLINT and PLIC modules (on going)
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* Re-capture vectors for unit sim due to changes in LLKI key size
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* Bootrom size is increased to 32K bytes (8kx32) to accomodate new built-in test (execute codes out of bootrom without main memory)
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#### Return to the root CEP [README](./README.md)

‎cosim/Makefile

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@@ -34,7 +34,7 @@ SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
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TEST_GROUP = bareMetalTests \
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bfmTests \
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isaTests \
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vBareTest \
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runAll:
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make cleanAll

‎cosim/README.md

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@@ -16,6 +16,7 @@ Several environments are supported:
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* Linux Mode (tests run on xilinx VC707 development card). Build and installation instructions can be found in: [../README.md](../README.md)
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* Benchmarking on Linux (TBA)
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* Cycle-accurate and translation-level accurate unit level simulations.
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* JTAG support to inferace with Openocd tool (via bitbang adapter) for Open On-Chip debugger (version 3.3 or later)
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## Benefits: ##
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isaTests/rv64mi-p-access
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isaTests/rv64ud-p-ldst
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```
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NOTE: All tests (including the above failed tests) are now passing with version 2.8 or later under Linux machine..
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**NOTE**: All tests (including the above failed tests) are now passing with version 2.8 or later under Linux machine..
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## Verify environment settings and tools: ##
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Also, there are riscv_wrapper.dump (created from objdump to help track the PC), riscv_wrapper.elf (to preload to main memory) and riscv_wrapper.hex files are created by Make under each test directory.
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**Note**: for version 3.3 or later, directory **.../cosim/drivers/bootbare** is removed and the official bootrom generation Makefile is adjusted to also produce the bootrom image for simulation.
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## Building ISA tests for simulation ##
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As of version 2.7 or later, ISA (Instruction-Set-Architecture) tests are added to simulation to improve overall chip coverages.
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For version 2.7 or later, ISA (Instruction-Set-Architecture) tests are added to simulation to improve overall chip coverages.
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**All ISA tests are re-used from https://github.com/riscv/riscv-tests.git repository**.
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cd <CEP_ROOT>/software/riscv-tests
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autoconf
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./configure
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make isa <-- only need to make ISA, without argument benchmark tests will be included (benchmarks have NOT be ported)
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make isa <-- only need to make ISA, without argument benchmark tests will also be included (benchmarks have NOT been ported)
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```
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The make command above will compile **mostly** assembly tests in the directory **isa** under it. These are the ones will be re-used to run in our simulation. **NOTE**: only RV64*-p/v-* tests are used since the cores are 64-bit cores.
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And we are now done for this ISA porting.
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## About JTAG/Debug port testing and Openocd ##
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To test JTAG port in simulation, openocd tool is needed. The Makefile will check for the present of such tool before any jtag related test is allowed to run.
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This JTAG port is connected to the CEP's DTM (DebugTransportModule). It is used to facilitate debugging via GDB. Openocd acts as transport layer between the internal DTM and GDB.
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A short description of what openocd is about:
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```
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OpenOCD provides on-chip programming and debugging support with a
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layered architecture of JTAG interface and TAP support including:
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- (X)SVF playback to facilitate automated boundary scan and FPGA/CPLD
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programming;
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- debug target support (e.g. ARM, MIPS): single-stepping,
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breakpoints/watchpoints, gprof profiling, etc;
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- flash chip drivers (e.g. CFI, NAND, internal flash);
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- embedded TCL interpreter for easy scripting.
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```
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To support simulation, DPI & remote-bitbang must be enable when building openocd tool.
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Download openocd via this link: **https://github.com/riscv/riscv-openocd**
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And follow the README file in there to build the tool or for more details how to use the tool. Instructions are cut/paste below for quick reference:
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```
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To build OpenOCD, use the following sequence of commands:
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./bootstrap (when building from the git repository)
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./configure -enable-remote-bitbang --enable-jtag_dpi [options]
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make
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sudo make install
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```
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To see how this works, run this test: **<...>/cosim/isaTests/dtmTest**
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## How to add your new test for regression ##
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Open ../Makefile (one level up where your test directory is located).
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* By default, under each test directory, one file will be created **if and only if** it is not yet there: **vsim.do**. It is used when **vsim** command is called to control the wave capturing.. If there is a need to override, users are free to modify and change it to anyway to fit the needs. Makefile will not overwrite it as long as it is there.
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* Under bare metal mode, some of main memory locations are used as mailbox to help RISCV core tracking and printing. See .**../cosim/dvt/cep_adrMap.incl** file. **NOTE**: there is also a file under .../cosim/include/cep_adrMap.h This file is auto-generated from the cep_adrMap.incl mentioned. Therefore, any modification should be made to the cep_adrMap.incl file.
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* Below is the short-cut to quickly build cep_diag application for Linux:
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```
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cd <...>/cosim/drivers/linux
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make buildMe
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```
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‎cosim/bareMetalTests/Makefile

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fragmemter \
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csrTest \
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srotMemTest \
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bootViaScratch \
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clintIntr \
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plicPrioIntr \
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TESTINFO_LIST := $(sort $(foreach t,${TALUS_TEST_LIST},${BLD_DIR}/${t}/testInfo.txt))

‎cosim/bareMetalTests/bootViaScratch/Makefile

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#//************************************************************************
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#// Copyright 2021 Massachusetts Institute of Technology
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#// SPDX short identifier: BSD-2-Clause
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#//
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#// File Name:
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#// Program: Common Evaluation Platform (CEP)
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#// Description:
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#// Notes:
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#//
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#//************************************************************************
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#
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#
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#
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COSIM_NAME = $(shell cd ../..; basename `pwd`)
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DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
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BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
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TEST_SUITE = $(shell basename ${BLD_DIR})
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TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
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TEST_NAME = $(shell basename `pwd`)
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SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
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#
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# Top target!!!
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#
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all: .vrun_flag riscv_wrapper.elf
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#
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# override anything here before calling the common file
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#
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include ${BLD_DIR}/common.make
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‎cosim/bareMetalTests/bootViaScratch/c_dispatch.cc

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//************************************************************************
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// Copyright 2021 Massachusetts Institute of Technology
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// SPDX short identifier: BSD-2-Clause
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//
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// File Name:
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// Program: Common Evaluation Platform (CEP)
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// Description:
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// Notes:
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//
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//************************************************************************
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#include <unistd.h>
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#include "v2c_cmds.h"
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#include "access.h"
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#include "c_dispatch.h"
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#include "c_module.h"
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#include "cep_apis.h"
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#include "cep_adrMap.h"
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#include "simPio.h"
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/*
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* main
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*/
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int main(int argc, char *argv[])
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{
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/* ===================================== */
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/* SETUP SECTION FOR SIMULATION */
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/* ===================================== */
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unsigned long seed;
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sscanf(argv[1],"0x%x",&seed);
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printf("Seed = 0x%x\n",seed);
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int errCnt = 0;
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int verbose = 0x1f;
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/* ===================================== */
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/* spawn all the paralle threads */
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/* ===================================== */
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int activeSlot=0; // only 1 board
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//
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// ============================
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// fork all the tests here
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// ============================
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//
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shPthread thr;
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//
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// max number of cores not include the system thread
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//
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int maxHost = MAX_CORES; // number of cores/threads
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//
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// each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
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//
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long unsigned int mask = 0xF;
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//
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// Set the active CPU mask before spawn the threads...
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//
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thr.SetActiveMask(mask);
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//
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// c_module is the threead to run
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//
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for (int i=0;i<maxHost;i++) {
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if ((long unsigned int)(1 << i) & mask) {
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thr.ForkAThread(activeSlot,i,verbose, seed * (1+i), c_module);
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}
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}
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//
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// lastly: Added system thread always
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//
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thr.AddSysThread(SYSTEM_SLOT_ID,SYSTEM_CPU_ID);
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//
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// ============================
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// Turn on the wave here
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// ============================
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//
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int cycle2start=0;
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int cycle2capture=-1; // til end
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int wave_enable=1;
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#ifndef NOWAVE
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dump_wave(cycle2start, cycle2capture, wave_enable);
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#endif
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//
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// Enable main memory logging
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//
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//DUT_WRITE_DVT(DVTF_ENABLE_MAIN_MEM_LOGGING, DVTF_ENABLE_MAIN_MEM_LOGGING, 1);
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//
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// wait for calibration??
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//
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#if 1
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//int calibDone = calibrate_ddr3(50);
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int backdoor_on = 1;
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int verify = 0;
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int srcOffset = 0x1000;
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int destOffset = 0;
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errCnt += load_mainMemory((char *)"./riscv_wrapper.elf", ddr3_base_adr,srcOffset, destOffset, backdoor_on, verify);
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#endif
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DUT_WRITE_DVT(DVTF_DISABLE_MAIN_MEM_LOGGING, DVTF_DISABLE_MAIN_MEM_LOGGING, 1);
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//
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// log the write only
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DUT_WRITE_DVT(DVTF_ENABLE_MAIN_MEMWR_LOGGING, DVTF_ENABLE_MAIN_MEMWR_LOGGING, 1);
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//
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// ============================
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// wait until all the threads are done
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// ============================
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//
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int Done = 0;
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while (!Done) {
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Done = thr.AllThreadDone();
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sleep(2);
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}
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//
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toggleDmiReset();
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//
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/* ===================================== */
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/* END-OF-TEST CHECKING */
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/* ===================================== */
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errCnt += thr.GetErrorCount();
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if (errCnt != 0) {
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LOGE("======== TEST FAIL ========== %x\n",errCnt);
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} else {
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LOGI("%s ======== TEST PASS ========== \n",__FUNCTION__);
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}
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//
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// shutdown HW side
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// dont call this DUT_SetInActiveStatus is used
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thr.Shutdown();
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return(errCnt);
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}

‎cosim/bareMetalTests/bootViaScratch/c_dispatch.h

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//************************************************************************
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// Copyright 2021 Massachusetts Institute of Technology
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// SPDX short identifier: BSD-2-Clause
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//
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// File Name:
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// Program: Common Evaluation Platform (CEP)
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// Description:
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// Notes:
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//
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//************************************************************************
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#ifndef __C_DISPATCH_H
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#define __C_DISPATCH_H
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// Dispatch setup
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#ifdef LONGTEST
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#define MAX_LOOP 50
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#else
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#define MAX_LOOP 5
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#endif
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#endif
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