CEP Release v3.41

Author: Test Dev

.DS_Store

@@ -8,7 +8,7 @@
     <img src="./doc/cep_logo.jpg" width="721" height="300">
 </p>
 <p align="center">
-    <img src="./doc/version3.4.jpg" width="98" height="60">
+    <img src="./doc/version3.41.jpg" width="98" height="60">
 </p>
 <p align="center">
    Copyright 2021 Massachusetts Institute of Technology
@@ -17,11 +17,9 @@
     <img src="./doc/related_logos.jpg" width="450" height="71">
 </p>
 
-The Common Evaluation Platform (CEP) is intended as a surrogate System on a Chip (SoC) that provides users an open-source evaluation platform for the evaluation of custom tools and techniques.  An extensive verification environment is provided to ensure the underlying functionality is maintained even after modification.
+The Common Evaluation Platform (CEP) is an Open Source Hardware (OSH) System on a Chip (SoC).  It has been developed to support the test and evluation of custom tools and techniques.  An extensive verification environment is provided to ensure the underlying functionality is maintained even after modification.
 
-The Logic Locking Key Interface (LLKI) has been provided as a representative means of distributing key / configuration material to LLKI-enabled cores.  
-
-For CEP v3.1+, the full LLKI has been added.  This includes the Surrogate Root of Trust (SRoT) and mock Technique Specific Shims (TSS) for all accelerator cores.
+The Lincoln Laboratory Key Interface (LLKI) has been provided as a representative means of distributing key / configuration material to LLKI-enabled cores.  
 
 ### Please check the [Release Notes](./RELEASE_NOTES.md) to understand what has changed and a list of known issues.
 
@@ -206,7 +204,7 @@ See ./cosim/drivers/diag/cepMacroMix.cc for example code.
 
 As one might be aware: the endianess usage is not consistent thru out the design, expesially where Chisel wrappers are used to connect to various HW cores. For some cores, little endian is used for loading keys/plain text but big-endian is used to produce cipher text as output. This creates confusion and inconsistent as one might try to understand/follow SW driver for these cores. Also, please note, RISCV is little endian.
 
-As of release CEP v2.4 and later, unless otherwise specify, big endian is used thru out the design to match key/plain/ciphertext network order.
+Unless otherwise specified, big endian is used thru out the design to match key/plain/ciphertext network order.
 
 This makes it consistent and easier to debug when key/plain text are printed to match against registers.
 
@@ -311,11 +309,15 @@ make install append
 
 If subsequent changes are made to the source code in <CEP_ROOT>/cosim/drivers/linux, simply copy the changes over to the Linux build by running `make install`.
 
-Next, one needs to build linux.  First, change to the `<CEP ROOT>/software/freedom-u-sdk` directory.  Ensure that the linux variant of the RISC-V toolset is used by executing `unset RISCV`
 
-For Ubuntu 18.04 LTS, the default PERL installation may cause a conflict with the build process.  You may need to execute `unset PERL_MM_OPT` if set.
+Next, one needs to build linux.  First, change to the `<CEP ROOT>/software/freedom-u-sdk` directory.  
+
+A few cautionary notes:
+- Ensure that the linux variant of the RISC-V toolset is used by executing `unset RISCV`
+- For Ubuntu 18.04 LTS, the default PERL installation may cause a conflict with the build process.  You may need to execute `unset PERL_MM_OPT` if set.
+- If you patched the LIBRARY_PATH environment variable to allow for compilation of the Xilinx simulation libraries, this may cause the linux build to fail
 
-Begin the build by running `make -jN BOARD=vc707devkit_nopci all` where N is the numbers of cores you can dedicate to the build.  Ensure that you have NOT sourced the Xilinx Vivado environment setup script before running this step.
+Begin the build by running `make -jN BOARD=vc707devkit_nopci all` where N is the numbers of cores you can dedicate to the build. 
 
 Following the linux build, which can take 30 - 60 minutes, you will have a binary which you can load onto an SD card.
 
@@ -342,7 +344,7 @@ You should see the following logo/text appear:
        ./+++++++++++oo+++:  +oo++o++++o+o+oo+oo.- `s+++s`-
        .--:---:-:-::-::`  -::::::::::::::::::.   :::::.
 
-                      Common Evaluation Platform v3.40
+                      Common Evaluation Platform v3.41
          Copyright 2021 Massachusetts Institute of Technology
 
             Built upon the SiFive Freedom U500 Platform using
@@ -365,7 +367,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`.
 A partial output should be similar to:
 
 ```sh
-*** CEP SW=0x3.40 HW VERSION = v3.40 was built on Aug  5 2021 08:36:41 ***
+*** CEP SW=0x3.41 HW VERSION = v3.41 was built on Aug  5 2021 08:36:41 ***
  CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x700000000, 0x800000000, 0x600000000, 0xc00000000
  ScratchPad=0x2000400000
 gSkipInit=0/0
@@ -428,7 +430,7 @@ The following cores have been integrated into the "standard" CEP build:
 - Infinite Impulse Response
 - GPS code generator
 
-Beginning with the v2.4 release, the following "generated" cores have been added to the repository, but are currently not integrated into the CEP build.
+The following "generated" cores have been added to the repository, but are currently not integrated into the CEP build.
 - A(EE)ES-WB : Advanced Egregiously Extended Encryption Standard - Whitebox Edition [./hdl_cores/aeees/README.md](./hdl_cores/aeees/README.md).
 - (RI)IIR : Randomly Indeterminate Infinite Impulse Response [./hdl_cores/auto-fir/README.md](./hdl_cores/auto-fir/README.md).
 - SHA(AA) : Secure Hash Algorithm Arbitrarily Augment [./hdl_cores/shaaa/README.md](./hdl_cores/shaaa/README.md).

README.md

@@ -144,4 +144,11 @@ v3.4 - (6 August 2021)
 * Scratchpad RAM changed to blackbox implementation to facilitate ASIC development
 * OpenSSL replaced by Cryptopp for crypto-related tests (cosim + linux)
 
+v3.41 - (10 September 2021)
+* CEP Configuration nows includes 4xGPS and 4xSHA-256 cores
+* Integrated configurable co-simulation environment (provide a co-sim that can more easily adapt to CEP architecture changes)
+* Known Issues:
+  - Some idft test vectors fail under QuestaSim (xcellium regression ran successfully)
+  - Multithreaded test (#23) non-functional under linux
+
 #### Return to the root CEP [README](./README.md)

RELEASE_NOTES.md

@@ -1,5 +1,6 @@
 .Xil/
 xil_lib/
+.xil_lib/
 .cxl.ip/
 .cxl*
 *.log*
@@ -8,6 +9,7 @@ xil_lib/
 *.bin
 **/*.o
 **/*.obj
+**/*.bobj
 **/*.hex
 **/*.a
 **/*.KEY
@@ -16,6 +18,7 @@ modelsim.ini*
 **/c_dispatch
 **/testHistory.txt
 vsim.do
+.c_children.mk
 **/transcript
 **/*.wlf
 **/*.dump
@@ -25,4 +28,5 @@ dvt/behav_models/ddr3.v
 include/cep_adrMap.h
 include/v2c_cmds.h
 lib/dll/libvpp.so
-
+lib/libvpp.so
+lib/.buildLibs

cosim/.DS_Store

@@ -6,7 +6,7 @@
 
 # README for CEP co-simulation environment
 
-This SW/HW co-simulation evironment has been developed to support "chip-level" simulation of the CEP.  
+This SW/HW co-simulation evironment has been developed to support "chip-level" simulation of the CEP.
 
 Several environments are supported:
 
@@ -25,19 +25,19 @@ Several environments are supported:
 
 * SW and HW are de-coupled such that mistakes that are found in the test/driver (SW side) during development process can be quickly corrected and rerun without having to rebuild the HW. Sometimes, it might takes minutes (or even hours for big ASIC) just to rebuild the HW if test and DUT (Device Under Test) are tightly coupled
 
-* Makefile is setup to support vendor independent designs such that same design can be used to target FPGA vendor as Xilinx or TSMC for ASIC, for example.
+* Makefile is setup to support vendor independent designs such that the same design can be used to target an FPGA vendor such as Xilinx or TSMC for ASIC.
 
 * To take advantage of multi-core machines, support up to 4K+ threads where all threads can run in parallel and target different HW sections. For example: one core can target the AES block while another core targets the FIR block, etc...
 
 * Mailboxes are setup to support in between thread communication for synchronization, handshaking, etc...
 
-* All are *makefile* driven with scripts to support auto-dependencies generation. Which means anything changes in either HW files or SW files: incremental builds will be called to save time. This is a must in order to support parallel batching.
+* All are *makefile* driven with scripts to support auto-dependencies generation. Which means when anything changes in either HW files or SW files, incremental builds will be called to save time. This is a must in order to support parallel batching.
 
 * Provide 100% visibility to everything in the test bench via wave capturing. From the SW (test) side, any signal in HW can be observed and forced (for negative testing) or to be used to synchronize events (wait for something before sending packet, etc...)
 
 * Same setup can be used for any design. Therefore, it takes only hour to set up new test bench for new design and let designer/verification engineers start writing tests right away.
 
-* Most of the tests can even be re-used across multiple projects such as memory test, register tests, packet generator and checker. They are written as template where only simple read/write methods need to be overload.
+* Most of the tests can even be re-used across multiple projects such as memory test, register tests, packet generator and checker. They are written as templates where only simple read/write methods need to be overload.
 
 * Open source codebase
 
@@ -66,7 +66,19 @@ For CEP, the path to tools required are as listed below (see **common.make**)
     SIMULATOR_PATH  ?= /opt/questa-2019.1/questasim/bin
     RISCV           ?= /opt/riscv
 
-**NOTE**: If they are not matched your setup, dont need to edit the common.make file, use enviroment variables to override as such (assuming bash shell is used). 
+As of release 3.2 or later, Cadence tool set is also supported, all setup related to Cadence tool set can be found in `cadence.make`
+
+If you decide to use Cadence's xcelium for simulation, modify cadence.make or override with environment variables to match the below variables:
+
+```
+export VMGR_VERSION	?= VMANAGERAGILE20.06.001
+export XCELIUM_VERSION	?= XCELIUMAGILE20.09.001
+
+export VMGR_PATH	?= /brewhouse/cad4/x86_64/Cadence/${VMGR_VERSION}
+export XCELIUM_INSTALL  ?= /brewhouse/cad4/x86_64/Cadence/${XCELIUM_VERSION}
+```
+
+**NOTE**: If they are not matched to your setup, you dont need to edit the common.make file. Instead, use enviroment variables to override as such (assuming bash shell is used).
 ```
 export VIVADO_PATH=<Your_path_to_Vivado_tool>
 export SIMULATOR_PATH=<Your_path_to_questa_tool>
@@ -116,7 +128,7 @@ You should see something like this under *cosim* directory:
 
 ## Compiling the Xilinx Simulation Libraries ##
 
-**NOTE**: xil_lib is the generated library packages created via vivado 's compile_simlib command.  Not all Vivado / Modelsim version combinations yield the desired result.  See the following notes:
+**NOTE**: xil_lib is the generated library packages created via vivado's compile_simlib command.  Not all Vivado / Modelsim version combinations yield the desired result.  See the following notes:
 - When Vivado 2019.1 and Questa 2019.1 is selected ,the compilation will stop and not generate the appropriate modelsim.ini file, which is required by the co-simulation environemt.
 - When Vivado 2018.3 and Questa 2019.1 (or Quest 10.7c) is selected, the compilation will return with an error in the qdma_v3_0_0 library.  This library is not required for CEP simulation and thus the error can be safely ignored.
 - When Vivado 2018.3 and Question 10.6c is selected, the compilation will complete without error.  However, it is recommended that Questa 2019.1 be used in order to take advantage of optimizations and bug fixes.  

cosim/.gitignore

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/README.md

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bareMetalTests/.DS_Store

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/Makefile

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/ddr3Test/Makefile

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/fragmentors/cepFragmentorTest.cc

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/fragmentors/cepFragmentorTest.h

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/lockTest/Makefile

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/macroMix/Makefile

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)
@@ -54,27 +54,30 @@ void *c_module(void *arg) {
   // ======================================
   // Test starts here
   // ======================================
-  // MUST
-  // wait until Calibration is done..
-  //int calibDone = calibrate_ddr3(50);
+  // MUST wait until Calibration is done..
   pio.RunClk(1000);
-  //
+  
+  int mask = seed; // seed is used as cpuActiveMask from c_dispatch
 
-  // Select which tests to run.  Core indicies are defined in CEP.h
-  int mask = seed; // seed is used as cpuActiveMask from c_displatch
-  int cryptoMask = 0xFFFFFFFF; // all cores
-// int cryptoMask = 0x00000001; // AES only
-//  int cryptoMask = 0x00000002; // MD5 only
-//  int cryptoMask = 0x00000004; // SHA256 only
-//  int cryptoMask = 0x00000008; // RSA only
-//  int cryptoMask = 0x00000010; // DES3 only
-//  int cryptoMask = 0x00000020; // DFT only
-//  int cryptoMask = 0x00000040; // IDFT only
-//  int cryptoMask = 0x00000080; // FIR only
-//  int cryptoMask = 0x00000100; // IIR only
-//  int cryptoMask = 0x00000200; // GPS only
+  int coreMask = 0xFFFFFFFF; // all cores
+//  int coreMask = 0x00000001;  // AES
+//  int coreMask = 0x00000002;  // MD5
+//  int coreMask = 0x00000004;  // SHA256.0
+//  int coreMask = 0x00000008;  // SHA256.1
+//  int coreMask = 0x00000010;  // SHA256.2
+//  int coreMask = 0x00000020;  // SHA256.3
+//  int coreMask = 0x00000040;  // RSA
+//  int coreMask = 0x00000080;  // DES3
+//  int coreMask = 0x00000100;  // DFT
+//  int coreMask = 0x00000200;  // IDFT
+//  int coreMask = 0x00000400;  // FIR
+//  int coreMask = 0x00000800;  // IIR
+//  int coreMask = 0x00001000;  // GPS.0
+//  int coreMask = 0x00002000;  // GPS.1
+//  int coreMask = 0x00004000;  // GPS.2
+//  int coreMask = 0x00008000;  // GPS.3
 
-  if (!errCnt) { errCnt = cepMacroMix_runTest(cpuId, mask, cryptoMask, seed, verbose); }
+  if (!errCnt) { errCnt = cepMacroMix_runTest(cpuId, mask, coreMask, seed, verbose); }
   //
   pio.RunClk(100);  
   //

cosim/bfmTests/macroMix/c_dispatch.cc

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/macroMix/c_dispatch.h

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/macroMix/c_module.cc

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/macroMix/c_module.h

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/Makefile

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/c_dispatch.cc

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/c_dispatch.h

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/c_module.cc

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/c_module.h

@@ -1,6 +1,6 @@
 #//************************************************************************
 #// Copyright 2021 Massachusetts Institute of Technology
-#// SPDX License Identifier: MIT
+#// SPDX License Identifier: BSD-2-Clause
 #//
 #// File Name:      
 #// Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/memPreload/riscv_wrapper.cc

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)

cosim/bfmTests/multiLock/Makefile

@@ -1,6 +1,6 @@
 //************************************************************************
 // Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
+// SPDX License Identifier: BSD-2-Clause
 //
 // File Name:      
 // Program:        Common Evaluation Platform (CEP)