diff --git a/.github/workflows/test-kg.yml b/.github/workflows/test-kg.yml index 79ec0fc..eb401d3 100644 --- a/.github/workflows/test-kg.yml +++ b/.github/workflows/test-kg.yml @@ -52,7 +52,7 @@ jobs: - name: Clone STMicro Sources run: | - make ext/arm/cmsis/ ext/stmicro/cubehal/ ext/stmicro/header/ + make clone-sources-stmicro - name: Generate Database for ${{ matrix.family_group.name }} run: | diff --git a/.github/workflows/update-archives.yml b/.github/workflows/update-archives.yml index ff3a72f..913ce21 100644 --- a/.github/workflows/update-archives.yml +++ b/.github/workflows/update-archives.yml @@ -9,6 +9,11 @@ jobs: update-pdfs: runs-on: ubuntu-latest steps: + - name: Free up Disk Space + run: | + df -h + sudo rm -rf /usr/lib/jvm /usr/share/dotnet /usr/local/lib/android /opt/microsoft /opt/google + df -h - name: Check out Repository uses: actions/checkout@v4 diff --git a/src/modm_data/cubehal/dmamux_requests.py b/src/modm_data/cubehal/dmamux_requests.py index eb52c67..9be12c5 100644 --- a/src/modm_data/cubehal/dmamux_requests.py +++ b/src/modm_data/cubehal/dmamux_requests.py @@ -7,9 +7,10 @@ from ..kg import DeviceIdentifier _CUBE_PATH = ext_path("stmicro/cubehal") -_DMAMUX_PATTERN = re.compile(r"^\s*#define\s+(?P(LL_DMAMUX_REQ_\w+))\s+(?P(0x[0-9A-Fa-f]+))U") +_DMAMUX_LL_PATTERN = re.compile(r"^\s*#define\s+(?P(LL_DMAMUX?_REQ_\w+))\s+(?P(0x[0-9A-Fa-f]+))U") _REQUEST_PATTERN = re.compile(r"^\s*#define\s+(?P(DMA_REQUEST_\w+))\s+(?P([0-9]+))U") _BDMA_REQUEST_PATTERN = re.compile(r"^\s*#define\s+(?P(BDMA_REQUEST_\w+))\s+(?P([0-9]+))U") +_DMAMUX_PATTERN = re.compile(r"^\s*#define\s+(?P(DMAM?U?X?_REQU?E?S?T?_\w+))\s+(?P(LL_DMAMUX?_REQ_\w+))\s*") def read_request_map(did: DeviceIdentifier) -> dict[str, int]: @@ -27,7 +28,7 @@ def read_request_map(did: DeviceIdentifier) -> dict[str, int]: elif did.family in ["g0", "u0", "wb", "wl"]: request_map = _read_requests_from_ll_dmamux(dma_header, dmamux_header) elif did.family == "l4" and did.name[0] in ["p", "q", "r", "s"]: - request_map = _read_requests_l4(did) + request_map = _read_requests_l4(dma_header, dmamux_header, did) else: raise RuntimeError("No DMAMUX request data available for {}".format(did)) _fix_request_data(request_map, "DMA") @@ -126,62 +127,41 @@ def _read_requests(hal_dma_file, request_pattern): # For G0, WB and WL def _read_requests_from_ll_dmamux(hal_dma_file, ll_dmamux_file): - dmamux_map = _read_map(ll_dmamux_file, _DMAMUX_PATTERN) - request_pattern = re.compile( - r"^\s*#define\s+(?P(DMAM?U?X?_REQU?E?S?T?_\w+))\s+(?P(LL_DMAMUX?_REQ_\w+))\s*" - ) - requests_map = _read_map(hal_dma_file, request_pattern) + dmamux_map = _read_map(ll_dmamux_file, _DMAMUX_LL_PATTERN) + requests_map = _read_map(hal_dma_file, _DMAMUX_PATTERN) out_map = {} for r in requests_map.keys(): out_map[r.replace("DMA_REQUEST_", "", 1).replace("DMAMUX_REQ_", "", 1)] = int(dmamux_map[requests_map[r]], 16) return out_map -# For L4+ -def _read_requests_l4(did): - read_for_p5_q5 = did.name in ["p5", "q5"] +def _read_requests_l4(hal_dma_file, ll_dmamux_file, did): + dmamux_pattern = re.compile(r"^\s*#define\s+(?P(LL_DMAMUX_REQ_\w+))\s+(?P\(? ?\d+)U") + dmamux_map = _read_map(ll_dmamux_file, dmamux_pattern, ignore_duplicates=True) + del dmamux_map["LL_DMAMUX_REQ_ADC2_SHIFT"] + if is_p5_q5 := did.name in ["p5", "q5"]: + dmamux_map = {k: ((int(v[1:]) + 1) if "(" in v else v) for k, v in dmamux_map.items()} + else: + dmamux_map = {k: v.replace("(", "") for k, v in dmamux_map.items() if k != "LL_DMAMUX_REQ_ADC2"} + + requests_map = _read_map(hal_dma_file, _DMAMUX_PATTERN) + if not is_p5_q5: + del requests_map["DMA_REQUEST_ADC2"] + out_map = {} - p5_q5_if = "#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)" - if_pattern = re.compile(r"^\s*#\s*if\s+") - else_pattern = re.compile(r"^\s*#\s*else") - endif_pattern = re.compile(r"^\s*#\s*endif") - in_p5_q5_section = False - ignore = False - with open(_get_hal_dma_header_path(did), "r") as header_file: - if_counter = 0 - for line in header_file.readlines(): - if p5_q5_if in line: - in_p5_q5_section = True - ignore = not read_for_p5_q5 - elif in_p5_q5_section: - if if_pattern.match(line): - if_counter += 1 - elif endif_pattern.match(line): - if if_counter == 0: - in_p5_q5_section = False - ignore = False - else: - if_counter -= 1 - elif else_pattern.match(line) and if_counter == 0: - ignore = read_for_p5_q5 - if not ignore: - m = _REQUEST_PATTERN.match(line) - if m: - name = m.group("name").replace("DMA_REQUEST_", "", 1) - if name in out_map: - raise RuntimeError(f"Duplicate entry {name}") - out_map[name] = int(m.group("id")) + for r in requests_map.keys(): + out_map[r.replace("DMA_REQUEST_", "", 1).replace("DMAMUX_REQ_", "", 1)] = int(dmamux_map[requests_map[r]]) return out_map -def _read_map(filename, pattern): +def _read_map(filename, pattern, ignore_duplicates=False): out_map = {} with open(filename, "r") as header_file: for line in header_file.readlines(): m = pattern.match(line) if m: name = m.group("name") - if name in out_map: - raise RuntimeError(f"Duplicate entry {name}") + if name in out_map and not ignore_duplicates: + raise RuntimeError("Duplicate entry {}".format(name)) out_map[name] = m.group("id") return out_map diff --git a/src/modm_data/cubemx/device_data.py b/src/modm_data/cubemx/device_data.py index 680a014..b84f602 100644 --- a/src/modm_data/cubemx/device_data.py +++ b/src/modm_data/cubemx/device_data.py @@ -14,11 +14,13 @@ from ..cubehal import read_request_map as dmamux_request_map from ..cubehal import read_bdma_request_map as dmamux_bdma_request_map from . import peripherals +from ..header2svd.stmicro import Header LOGGER = logging.getLogger(__file__) -_MCU_PATH = ext_path("stmicro/cubemx/mcu") +_EXT_PATH = ext_path("stmicro/") +_MCU_PATH = _EXT_PATH / "cubemx/mcu" _FAMILY_FILE = None @@ -84,66 +86,95 @@ def devices_from_partname(partname: str) -> list[dict[str]]: LOGGER.info(f"Parsing '{did.string}'") # information about the core and architecture - cores = [c.text.lower().replace("arm ", "") for c in device_file.query("//Core")] + cores = [c.text.lower().replace("arm ", "").replace("+", "plus") for c in device_file.query("//Core")] if len(cores) > 1: did.naming_schema += "@{core}" - devices = [_properties_from_id(comboDeviceName, device_file, did.copy(), c) for c in cores] + devices = [_properties_from_id(partname, comboDeviceName, device_file, did.copy(), c) for c in cores] return [d for d in devices if d is not None] -def _properties_from_id(comboDeviceName, device_file, did, core): - if core.endswith("m4") or core.endswith("m7") or core.endswith("m33"): - core += "f" - if did.family in ["h7"] or (did.family in ["f7"] and (did.name[0] in ("6", "7"))): - core += "d" +def _properties_from_id(partname, comboDeviceName, device_file, did, core): if "@" in did.naming_schema: did.set("core", core[7:9]) - p = {"id": did, "core": core} + p = {"id": did, "die": device_file.query("//Die/text()")[0]} + + dfp_folder = "STM32{}xx_DFP".format(did.family.upper()) + if did.string[5:8] in ["h7r", "h7s"]: + dfp_folder = "STM32H7RSxx_DFP" + elif did.string[5:8] == "wb0": + dfp_folder = "STM32WB0x_DFP" + elif did.string[5:8] == "wba": + dfp_folder = "STM32WBAxx_DFP" + elif did.string[5:8] == "wl3": + dfp_folder = "STM32WL3x_DFP" + + # Find OpenCMSIS pack file + dfp_file = XmlReader(os.path.join(_EXT_PATH, dfp_folder, f"Keil.{dfp_folder}.pdsc")) + + # Find the correct DFP start node + dfp_node = dfp_file.query(f'//variant[starts-with(@Dvariant,"{partname}")]') + if not dfp_node: + dfp_node = dfp_file.query(f'//device[starts-with(@Dname,"{partname}")]') + if not dfp_node: + dfp_node = dfp_file.query(f'//device[starts-with(@Dname,"{partname[:11]}")]') + + if not dfp_node: + LOGGER.error(f"No DFP device entry found for {did.string}: {partname}") + return None + + def dfp_findall(key, attribs=None): + values = [] + node = dfp_node[0] + while node.tag != "devices": + values += node.findall(key) + node = node.getparent() + if core := did.get("core"): + values = [v for v in values if core.upper() in v.get("Pname", core.upper())] + if attribs is not None: + values = {a: v.get(a) for v in values for a in attribs if v.get(a)} + return values + + # Find the correct CMSIS header + dfp_compile = dfp_findall("compile")[0].get("define") + p["cmsis_header"] = cmsis_header = dfp_folder[:-4].lower() + # https://github.com/Open-CMSIS-Pack/STM32H7xx_DFP/pull/7 + if did.string == "stm32h730ibt6q": + dfp_compile = "STM32H730xxQ" + stm_header = Header(did, cmsis_header, dfp_compile) + if not stm_header.is_valid: + LOGGER.error("CMSIS Header invalid for %s", did.string) + return None + p["define"] = stm_header.define + + # Find out about the CPU + p["core"] = core + processor = dfp_findall("processor", ["DcoreVersion", "Dclock", "Dfpu"]) + if (fpu := processor.get("Dfpu")) in ("1", "SP_FPU"): + p["fpu"] = "fpv4-sp-d16" if "m4" in core else "fpv5-sp-d16" + elif fpu == "DP_FPU": + p["fpu"] = "fpv5-d16" + if rev := processor.get("DcoreVersion"): + p["revision"] = rev.lower() # Maximum operating frequency - if max_frequency := device_file.query("//Frequency"): - max_frequency = float(max_frequency[0].text) - else: - max_frequency = stm32_data.getMaxFrequencyForDevice(did) - # H7 dual-core devices run the M4 core at half the frequency as the M7 core - if did.get("core", "") == "m4": - max_frequency /= 2.0 - p["max_frequency"] = int(max_frequency * 1e6) - - # flash and ram sizes - # The and can occur multiple times. - # they are "ordered" in the same way as the `(S-I-Z-E)` ids in the device combo name - # we must first find out which index the current did.size has inside `(S-I-Z-E)` - sizeIndexFlash = 0 - sizeIndexRam = 0 - - match = re.search(r"\(.(-.)*\)", comboDeviceName) - if match: - sizeArray = match.group(0)[1:-1].lower().split("-") - sizeIndexFlash = sizeArray.index(did.size) - sizeIndexRam = sizeIndexFlash - - rams = sorted([int(r.text) for r in device_file.query("//Ram")]) - if sizeIndexRam >= len(rams): - sizeIndexRam = len(rams) - 1 - - flashs = sorted([int(f.text) for f in device_file.query("//Flash")]) - if sizeIndexFlash >= len(flashs): - sizeIndexFlash = len(flashs) - 1 - - p["ram"] = rams[sizeIndexRam] * 1024 - p["flash"] = flashs[sizeIndexFlash] * 1024 - - memories = [] - for mem_name, mem_start, mem_size in stm32_data.getMemoryForDevice(did, p["flash"], p["ram"]): - access = "rwx" - if did.family == "f4" and mem_name == "ccm": - access = "rw" - if "flash" in mem_name: - access = "rx" - memories.append({"name": mem_name, "access": access, "size": mem_size, "start": mem_start}) - - p["memories"] = memories + if max_frequency := processor.get("Dclock"): + max_frequency = int(max_frequency) + elif max_frequency := device_file.query("//Frequency"): + LOGGER.warning(f"Fallback to //Frequency for max frequency for {did.string}!") + max_frequency = int(float(max_frequency[0].text) * 1e6) + p["max_frequency"] = max_frequency + + # Find all internal memories + memories = { + m.get("name", m.get("id")).lower(): { + "access": m.get("access", "rwx"), + "start": int(m.get("start"), 0), + "size": int(m.get("size"), 0), + "alias": m.get("alias", "").lower(), + } + for m in (dfp_findall("memory") + dfp_findall("algorithm")) + } + p["memories"] = stm32_data.fixMemoryForDevice(did, memories, stm_header) # packaging package = device_file.query("//@Package")[0] @@ -216,6 +247,11 @@ def clean_up_version(version): module = ("TIM",) + module[1:] elif module[0] == "MDF" and module[1].startswith("ADF"): module = ("ADF",) + module[1:] + elif module[0] == "USB_DRD_FS": + module = ( + "USB", + "USB", + ) + module[2:] modules.append(tuple([m.lower() for m in module])) diff --git a/src/modm_data/cubemx/stm32_data.py b/src/modm_data/cubemx/stm32_data.py index 0f57079..6b4f1b6 100644 --- a/src/modm_data/cubemx/stm32_data.py +++ b/src/modm_data/cubemx/stm32_data.py @@ -22,6 +22,7 @@ def ignoreDevice(device_id: str) -> bool: return False +# ================================ GPIO REMAP ================================= stm32f1_gpio_remap = { # (position % 32) -> local bit position # MAPR register @@ -32,7 +33,7 @@ def ignoreDevice(device_id: str) -> bool: "usart3": {"position": 4, "mask": 3, "mapping": [0, 1, 3]}, "tim1": {"position": 6, "mask": 3, "mapping": [0, 1, 3]}, "tim2": {"position": 8, "mask": 3, "mapping": [0, 1, 2, 3]}, - "tim3": {"position": 10, "mask": 3, "mapping": [0, 2, 3]}, + "tim3": {"position": 10, "mask": 3, "mapping": [0, 0, 2, 3]}, # CubeMX db bug "tim4": {"position": 12, "mask": 1, "mapping": [0, 1]}, "can": {"position": 13, "mask": 3, "mapping": [0, 2, 3]}, "can1": {"position": 13, "mask": 3, "mapping": [0, 2, 3]}, @@ -79,68 +80,7 @@ def getGpioRemapForModuleConfig(module, config): return mmm -stm32_max_frequency = { - "c0": 48, - "f0": 48, - "f1": [ - {"name": ["00"], "f": 24}, - {"name": ["01"], "f": 36}, - {"name": ["02"], "f": 48}, - 72, - ], - "f2": 120, - "f3": 72, - "f4": [ - {"name": ["01"], "f": 84}, - {"name": ["10", "11", "12", "13", "23"], "f": 100}, - {"name": ["05", "07", "15", "17"], "f": 168}, - 180, - ], - "f7": 216, - "g0": 64, - "g4": 170, - "h5": 250, - "h7": [ - {"name": ["a3", "b0", "b3"], "f": 280}, - {"name": ["23", "25", "30", "33", "35"], "f": 550}, - {"name": ["r3", "s3", "r7", "s7"], "f": 600}, - 480, - ], - "l0": 32, - "l1": 32, - "l4": [ - {"name": ["s5", "s7", "s9", "q5", "p5", "r5", "r7", "r9"], "f": 120}, - 80, - ], - "l5": 110, - "u0": 56, - "u3": 96, - "u5": 160, - "wb": 64, - "wl": 48, -} - - -def getMaxFrequencyForDevice(did): - freq = stm32_max_frequency.get(did.family) - assert freq, f"No max frequency defined for family {did.family}" - if isinstance(freq, int): - return freq - - # Convert MHz to Hz and filter out string keys - def lconv(lt): - if isinstance(lt, int): - return lt - return lt["f"] - - for lt in freq: - if isinstance(lt, int): - return lt - # check if all conditions match - if all(did[k] in v for k, v in lt.items() if not isinstance(v, int)): - return lconv(lt) # return filtered table - - +# =============================== FLASH LATENCY =============================== stm32_flash_latency = { "f0": {1800: [24, 48]}, "f1": [{"name": ["00"], 1800: [24]}, {1800: [24, 48, 72]}], @@ -281,6 +221,7 @@ def lconv(lt): return lconv(lts[-1]) # if non were found, return last table +# ==================================== DMA ==================================== stm32f3_dma_remap = { "dma1ch1": { "tim17_ch1": "tim17_up", @@ -435,514 +376,175 @@ def getDmaRemap(did, dma, channel, driver, inst, signal): return signal -stm32_memory = { - "f0": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [ - { - "name": ["30", "31", "38", "42", "48", "51", "58", "70", "71", "72", "78", "91", "98"], - "memories": {"flash": 0, "sram1": 0}, - } - ], - }, - "c0": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [ - {"name": ["11", "31", "71"], "memories": {"flash": 0, "sram1": 0}}, - {"name": ["51"], "memories": {"flash": 0, "sram1": 12 * 1024}}, - {"name": ["91"], "memories": {"flash": 0, "sram1": 36 * 1024}}, - {"name": ["92"], "memories": {"flash": 0, "sram1": 30 * 1024}}, - ], - }, - "g0": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [ - { - "name": ["30", "31", "41", "50", "51", "61", "70", "71", "81", "b0", "b1", "c0", "c1"], - "memories": {"flash": 0, "sram1": 0}, - } - ], - }, - "g4": { - "start": {"flash": 0x08000000, "ccm": 0x10000000, "sram": 0x20000000}, - "model": [ - {"name": ["31", "41"], "memories": {"flash": 0, "sram1": 0, "sram2": 6 * 1024, "ccm": 10 * 1024}}, - {"name": ["91", "a1"], "memories": {"flash": 0, "sram1": 0, "sram2": 16 * 1024, "ccm": 16 * 1024}}, - { - "name": ["71", "73", "74", "83", "84"], - "memories": {"flash": 0, "sram1": 0, "sram2": 16 * 1024, "ccm": 32 * 1024}, - }, - ], - }, - "f1": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [{"name": ["00", "01", "02", "03", "05", "07"], "memories": {"flash": 0, "sram1": 0}}], - }, - "f2": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [{"name": ["05", "07", "15", "17"], "memories": {"flash": 0, "sram1": 0, "sram2": 16 * 1024}}], - }, - "f3": { - "start": {"flash": 0x08000000, "ccm": 0x10000000, "sram": 0x20000000}, - "model": [ - {"name": ["01", "02", "18", "78", "73"], "memories": {"flash": 0, "sram1": 0}}, - { - "name": ["03", "28", "34"], - "size": ["4", "6", "8"], - "memories": {"flash": 0, "ccm": 4 * 1024, "sram1": 0}, - }, - {"name": ["03", "58"], "size": ["b", "c"], "memories": {"flash": 0, "ccm": 8 * 1024, "sram1": 0}}, - {"name": ["03", "98"], "size": ["d", "e"], "memories": {"flash": 0, "ccm": 16 * 1024, "sram1": 0}}, - ], - }, - "f4": { - "start": {"flash": 0x08000000, "ccm": 0x10000000, "sram": 0x20000000, "backup": 0x40024000}, - "model": [ - {"name": ["01", "10", "11", "12", "46"], "memories": {"flash": 0, "sram1": 0}}, - { - "name": ["05", "07", "15", "17"], - "memories": {"flash": 0, "ccm": 64 * 1024, "sram1": 0, "sram2": 16 * 1024, "backup": 4 * 1024}, - }, - {"name": ["13", "23"], "memories": {"flash": 0, "ccm": 64 * 1024, "sram1": 0, "backup": 4 * 1024}}, - { - "name": ["27", "29", "37", "39"], - "memories": { - "flash": 0, - "ccm": 64 * 1024, - "sram1": 0, - "sram2": 16 * 1024, - "sram3": 64 * 1024, - "backup": 4 * 1024, - }, - }, - { - "name": ["69", "79"], - "memories": { - "flash": 0, - "ccm": 64 * 1024, - "sram1": 0, - "sram2": 32 * 1024, - "sram3": 128 * 1024, - "backup": 4 * 1024, - }, - }, - ], - }, - "f7": { - "start": { - "flash": 0x00200000, - "dtcm": 0x20000000, - "itcm": 0x00000000, - "sram": 0x20010000, - "backup": 0x40024000, - }, - "model": [ - { - "name": ["22", "32", "23", "30", "33", "45", "46", "50", "56"], - "memories": { - "flash": 0, - "itcm": 16 * 1024, - "dtcm": 64 * 1024, - "sram1": 0, - "sram2": 16 * 1024, - "backup": 4 * 1024, - }, - }, - { - "name": ["65", "67", "68", "69", "77", "78", "79"], - "memories": { - "flash": 0, - "itcm": 16 * 1024, - "dtcm": 128 * 1024, - "sram1": 0, - "sram2": 16 * 1024, - "backup": 4 * 1024, - }, - "start": {"sram": 0x20020000}, # overwrite due to bigger dtcm size! - }, - ], - }, - "h5": { - "start": {"flash": 0x08000000, "itcm": 0x00000000, "sram": 0x20000000, "backup": 0x40036400}, - "model": [ - {"name": ["03"], "memories": {"flash": 0, "sram1": 0, "sram2": 16 * 1024, "backup": 2 * 1024}}, - { - "name": ["23", "33"], - "memories": { - "flash": 0, - "sram1": 128 * 1024, - "sram2": 80 * 1024, - "sram3": 64 * 1024, - "backup": 2 * 1024, - }, - }, - { - "name": ["62", "63", "73"], - "memories": { - "flash": 0, - "sram1": 256 * 1024, - "sram2": 64 * 1024, - "sram3": 320 * 1024, - "backup": 4 * 1024, - }, - }, - ], - }, - "h7": { - "start": { - "flash": 0x08000000, - "dtcm": 0x20000000, - "itcm": 0x00000000, - "d1_sram": 0x24000000, - "d2_sram": 0x30000000, - "d3_sram": 0x38000000, - "backup": 0x38800000, - }, - "model": [ - { - "name": ["42"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 128 * 1024, - "backup": 4 * 1024, - "d1_sram": 384 * 1024, - "d2_sram1": 32 * 1024, - "d2_sram2": 16 * 1024, - "d3_sram": 64 * 1024, - }, - }, - { - "name": ["23", "25", "30", "33", "35"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 128 * 1024, - "backup": 4 * 1024, - "d1_sram": 320 * 1024, - "d2_sram1": 16 * 1024, - "d2_sram2": 16 * 1024, - "d3_sram": 16 * 1024, - }, - }, - { - "name": ["40", "43", "50", "53"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 128 * 1024, - "backup": 4 * 1024, - "d1_sram": 512 * 1024, - "d2_sram1": 128 * 1024, - "d2_sram2": 128 * 1024, - "d2_sram3": 32 * 1024, - "d3_sram": 64 * 1024, - }, - }, - { - "name": ["45", "47", "55", "57"], - "core": ["m7"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 128 * 1024, - "backup": 4 * 1024, - "d1_sram": 512 * 1024, - "d2_sram1": 128 * 1024, - "d2_sram2": 128 * 1024, - "d2_sram3": 32 * 1024, - "d3_sram": 64 * 1024, - }, - }, - { - "name": ["45", "47", "55", "57"], - "core": ["m4"], - "memories": { - "flash": 0, - "backup": 4 * 1024, - "d1_sram": 512 * 1024, - "d2_sram1": 128 * 1024, - "d2_sram2": 128 * 1024, - "d2_sram3": 32 * 1024, - "d3_sram": 64 * 1024, - }, - }, - { - "name": ["a0", "a3", "b0", "b3"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 128 * 1024, - "backup": 4 * 1024, - "d1_sram1": 256 * 1024, - "d1_sram2": 384 * 1024, - "d1_sram3": 384 * 1024, - "d2_sram1": 64 * 1024, - "d2_sram2": 64 * 1024, - "d3_sram": 32 * 1024, - }, - }, - { - "name": ["r3", "r7", "s3", "s7"], - "memories": { - "flash": 0, - "itcm": 64 * 1024, - "dtcm": 64 * 1024, - "backup": 4 * 1024, - "d1_sram1": 128 * 1024, - "d1_sram2": 128 * 1024, - "d1_sram3": 128 * 1024, - "d1_sram4": 72 * 1024, - "d2_sram1": 16 * 1024, - "d2_sram2": 16 * 1024, - }, - }, - ], - }, - "l0": { - "start": {"flash": 0x08000000, "eeprom": 0x08080000, "sram": 0x20000000}, - "model": [ - {"name": ["10"], "size": ["4"], "memories": {"flash": 0, "sram1": 0, "eeprom": 128}}, - {"name": ["10"], "size": ["6", "8"], "memories": {"flash": 0, "sram1": 0, "eeprom": 256}}, - { - # CAT1 - "name": ["10", "11", "21"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 512}, - }, - { - # CAT2 - "name": ["31", "41"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 1024}, - }, - { - # CAT3 - "name": ["51", "52", "53", "62", "63"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 2 * 1024}, - }, - { - # CAT5 - "name": ["71", "72", "73", "81", "82", "83"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 6 * 1024}, - }, - ], - }, - "l1": { - "start": {"flash": 0x08000000, "eeprom": 0x08080000, "sram": 0x20000000}, - "model": [ - { - # CAT1 & 2 - "name": ["00", "51", "52"], - "size": ["6", "8", "b"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 4 * 1024}, - }, - { - # CAT3 - "name": ["00", "51", "52", "62"], - "size": ["c"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 8 * 1024}, - }, - { - # CAT4 - "name": ["51", "52", "62"], - "size": ["d"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 12 * 1024}, - }, - { - # CAT5 & 6 - "name": ["51", "52", "62"], - "size": ["e"], - "memories": {"flash": 0, "sram1": 0, "eeprom": 16 * 1024}, - }, - ], - }, - "l4": { - "start": {"flash": 0x08000000, "ccm": 0x10000000, "sram": 0x20000000}, - "model": [ - {"name": ["12", "22"], "memories": {"flash": 0, "sram1": 0, "ccm": 8 * 1024}}, - {"name": ["51", "71", "75", "76", "85", "86"], "memories": {"flash": 0, "sram1": 0, "ccm": 32 * 1024}}, - { - "name": ["31", "32", "33", "42", "43", "52", "62"], - "memories": {"flash": 0, "sram1": 0, "ccm": 16 * 1024}, - }, - {"name": ["96", "a6"], "memories": {"flash": 0, "sram1": 0, "ccm": 64 * 1024}}, - # Technically part of the STM32L4+ family - { - "name": ["r5", "r7", "r9", "s5", "s7", "s9"], - "memories": {"flash": 0, "sram1": 0, "sram2": 64 * 1024, "sram3": 384 * 1024}, - }, - {"name": ["p5", "q5"], "memories": {"flash": 0, "sram1": 0, "sram2": 64 * 1024, "sram3": 128 * 1024}}, - ], - }, - "l5": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [{"name": ["52", "62"], "memories": {"flash": 0, "sram1": 0, "sram2": 64 * 1024}}], - }, - "wb": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [ - {"name": ["05"], "memories": {"flash": 0, "sram0": 12 * 1024, "sram1": 0}}, - { - "name": ["06", "07", "09"], - "memories": { - "flash": 0, - "sram0": 16 * 1024, - "sram1": 16 * 1024, - "sram2": 16 * 1024, - "sram3": 16 * 1024, - }, - }, - {"name": ["10", "15", "1m"], "memories": {"flash": 0, "sram1": 0, "sram2": 36 * 1024}}, - {"name": ["30", "35", "50", "55", "5m"], "memories": {"flash": 0, "sram1": 0, "sram2": 64 * 1024}}, - ], - }, - "wl": { - "start": {"flash": 0x08000000, "sram": 0x20000000}, - "model": [ - {"name": ["30", "31"], "memories": {"flash": 0, "sram0": 0}}, - {"name": ["33"], "memories": {"flash": 0, "sram0": 16 * 1024, "sram1": 0}}, - {"name": ["54", "55", "e4", "e5"], "memories": {"flash": 0, "sram1": 32 * 1024, "sram2": 0}}, - ], - }, - "u0": { - "start": { - "flash": 0x08000000, - "sram2": 0x10000000, - "sram1": 0x20000000, - }, - "model": [ - {"name": ["31", "73", "83"], "memories": {"flash": 0, "sram1": 2 * 1024, "sram2": 1 * 1024}}, - ], - }, - "u3": { - "start": { - "flash": 0x08000000, - "sram": 0x20000000, - }, - "model": [ - {"name": ["75", "85"], "memories": {"flash": 0, "sram1": 0, "sram2": 64 * 1024}}, - ], - }, - "u5": { - "start": { - "flash": 0x08000000, - "sram1": 0x20000000, - "sram2": 0x200C0000, - "sram3": 0x200D0000, - "sram5": 0x201A0000, - "sram6": 0x20270000, - "sram4": 0x28000000, - "bkpsram": 0x40036400, - }, - "model": [ - { - "name": ["35", "45"], - "memories": { - "flash": 0, - "sram1": 192 * 1024, - "sram2": 64 * 1024, - "sram4": 16 * 1024, - "bkpsram": 2 * 1024, - }, - "start": { # overwrite due to smaller sram1/3 sizes - "sram2": 0x20030000, - "sram3": 0x20040000, - }, - }, - { - "name": ["75", "85"], - "memories": { - "flash": 0, - "sram1": 192 * 1024, - "sram2": 64 * 1024, - "sram3": 512 * 1024, - "sram4": 16 * 1024, - "bkpsram": 2 * 1024, - }, - "start": { # overwrite due to smaller sram1/3 sizes - "sram2": 0x20030000, - "sram3": 0x20040000, - }, - }, - { - "name": ["95", "99", "a5", "a9"], - "memories": { - "flash": 0, - "sram1": 768 * 1024, - "sram2": 64 * 1024, - "sram3": 832 * 1024, - "sram4": 16 * 1024, - "sram5": 832 * 1024, - "bkpsram": 2 * 1024, - }, - }, - { - "name": ["f5", "g5", "f7", "g7", "f9", "g9"], - "memories": { - "flash": 0, - "sram1": 768 * 1024, - "sram2": 64 * 1024, - "sram3": 832 * 1024, - "sram4": 16 * 1024, - "sram5": 832 * 1024, - "sram6": 512 * 1024, - "bkpsram": 2 * 1024, - }, - }, - ], - }, -} - - -def getMemoryModel(device_id): - mem_fam = stm32_memory[device_id.family] - mem_model = None - for model in mem_fam["model"]: - if all(device_id[k] in v for k, v in model.items() if k not in ["start", "memories"]): - mem_model = model - break - if mem_model is None: - LOGGER.error(f"Memory model not found for device '{device_id.string}'") - exit(1) - start = dict(mem_fam["start"]) - memories = dict(mem_model["memories"]) - start.update(mem_model.get("start", {})) - return (start, memories) - - -def getMemoryForDevice(device_id, total_flash, total_ram): - mem_start, mem_model = getMemoryModel(device_id) - - # Correct Flash size - mem_model["flash"] = total_flash - - # Correct RAM size - main_sram = next((name for (name, size) in mem_model.items() if size == 0), None) - if main_sram is not None: - main_sram_name = next(ram for ram in mem_start.keys() if main_sram.startswith(ram)) - # compute the size from total ram - mem_model[main_sram] = total_ram - main_sram_index = int(main_sram.split("sram")[-1]) if main_sram[-1].isdigit() else 0 - for name, size in mem_model.items(): - mem_index = int(name.split("sram")[-1]) if name[-1].isdigit() else 0 - if (name.startswith(main_sram_name) and mem_index != main_sram_index) or ( - device_id.family == "g4" and name.startswith("ccm") - ): - mem_model[main_sram] -= size - - # Assemble flattened memories - memories = [] - for name, size in mem_model.items(): - if size <= 0: +# =================================== MEMORY ================================== +def _add_ram(m, name, size, start=None, target=None, access=None): + if name in m: + return + if target: + m[target]["size"] -= size + m[name] = { + "access": "rwx" if access is None else access, + "start": m[target]["start"] + m[target]["size"] if start is None else start, + "size": size, + } + + +def _stm32_memory_rename(name, data): + renames = { + "irom1": "flash", + "main_flash": "flash", + "flash-secure": "flash_s", + "flash-non-secure": "flash_ns", + "flash_bank1": "flash1", + "flash_bank2": "flash2", + "iram1": "sram1", + "iram2": "sram2", + "sram-secure": "sram_s", + "sram-non-secure": "sram_ns", + "sram1_2": "sram1", + "ram_d1": "d1_sram", + "ram_d2": "d2_sram1", + "ram_d2s2": "d2_sram2", + "ram_d2s3": "d2_sram3", + "ram_d3": "d3_sram", + "axi_sram": "d1_sram", + "ahb_sram": "d2_sram1", + "ccm_ram": "ccm", + "dtcmram": "dtcm", + "dtcm_ram": "dtcm", + "bkp_sram": "backup", + } + name = renames.get(name, name) + # also fix any potential aliases + data["alias"] = renames.get(data["alias"], data["alias"]) + + # EEPROM is not explicitly listed in STM32 memory map, but we can deduce it + if "_eeprom.flm" in name: + name = "eeprom" + + return name + + +def fixMemoryForDevice(did, memories: dict[str, dict], header) -> list[dict]: + mems = {} + for name, data in memories.items(): + name = _stm32_memory_rename(name, data) + if ".flm" in name: continue - sram_name = next(ram for ram in mem_start.keys() if name.startswith(ram)) - index = int(name.split("sram")[-1]) if name[-1].isdigit() else 0 - start = mem_start[sram_name] - if index > 1: - # correct start address - for mem_name, mem_size in mem_model.items(): - mem_index = int(mem_name.split("sram")[-1]) if mem_name[-1].isdigit() else 0 - if mem_name.startswith(sram_name) and mem_index < index: - start += mem_size - memories.append((name, start, size)) - - return memories + # remove empty aliases + if not data["alias"]: + del data["alias"] + + # Fix access for FLASH and EEPROM + if "flash" in name: + data["access"] = "rx" + if "eeprom" in name: + data["access"] = "r" + # On STM32F4 CCM memory is rw only + if did.family in ["f4", "l4"] and data["start"] == 0x10000000: + name = "ccm" + data["access"] = "rw" + + mems[name] = data + + # Correct memories for specific devices + if did.string.startswith("stm32l083"): + # https://github.com/Open-CMSIS-Pack/STM32L0xx_DFP/pull/2 + mems["sram"]["size"] = 0x00005000 + + elif did.family == "f2": + # Split SRAM1 into SRAM1/2 + mems["sram1"] = mems.pop("sram") + _add_ram(mems, "sram2", 16 * 1024, target="sram1") + + elif did.family == "f3" and did.name in ["03", "28", "58", "98"]: + ccm = 4 # Add CCM memory manually, since the headers are not helpful + if did.size in ["b", "c"]: + ccm = 8 + elif did.size in ["d", "e"]: + ccm = 16 + _add_ram(mems, "ccm", ccm * 1024, start=0x10000000, target="sram") + # F3x8 devices do not count the CCM memory as part of SRAM1 + if did.name == "58": + mems["sram"]["size"] = 40 * 1024 + if did.name == "98": + mems["sram"]["size"] = 64 * 1024 + + elif did.family == "f4": + # add CCM and Backup SRAM memories manually, since the headers are not helpful + if did.name not in ["01", "10", "11", "12", "46"]: + mems["backup"] = {"start": 0x40024000, "size": 4096, "access": "rwx"} + mems["ccm"] = {"start": 0x10000000, "size": 64 * 1024, "access": "rw"} + # Split SRAM1 into SRAM1/2/3 + sram2, sram3 = 0, 0 + if did.name in ["05", "07", "15", "17"]: + sram2 = 16 + elif did.name in ["27", "29", "37", "39"]: + sram2, sram3 = 16, 64 + elif did.name in ["69", "79"]: + sram2, sram3 = 32, 128 + + if (sram2 or sram3) and "sram" in mems: + mems["sram1"] = mems.pop("sram") + if sram3: + _add_ram(mems, "sram3", sram3 * 1024, target="sram1") + if sram2: + _add_ram(mems, "sram2", sram2 * 1024, target="sram1") + + elif did.family == "f7": + # Fix missing alias, ITCM_FLASH is faster + mems["flash"]["alias"] = "itcm_flash" + + elif did.string.startswith("stm32g0b0vet"): + # https://github.com/Open-CMSIS-Pack/STM32G0xx_DFP/pull/3 + mems["sram"]["size"] = 0x00024000 + + elif did.family == "g4": + # Fix missing CCM and SRAM2 + sizes = header.get_memory_sizes + _add_ram(mems, "ccm", sizes["CCMSRAM"], start=0x10000000, target="sram") + if sram2 := sizes.get("SRAM2"): + mems["sram1"] = mems.pop("sram") + _add_ram(mems, "sram2", sram2, target="sram1") + + elif did.family == "h5": + # Fix missing Backup and SRAM2/3 + sizes = header.get_memory_sizes + if sram3 := sizes.get("SRAM3"): + _add_ram(mems, "sram3", sram3, target="sram1") + if sram2 := sizes.get("SRAM2"): + _add_ram(mems, "sram2", sram2, target="sram1") + mems["backup"] = {"start": 0x40036400, "size": sizes["BKPSRAM"], "access": "rwx"} + + elif did.family == "h7": + # Fix missing ITCM and Backup memory + mems["backup"] = {"start": 0x38800000, "size": 4096, "access": "rwx"} + if "m7" in did.get("core", "m7"): + mems["itcm"] = {"start": 0, "size": 64 * 1024, "access": "rwx"} + + d2_sram2, d2_sram3 = 0, 0 + if did.name[0] in "23": + d2_sram2 = 16 + if did.name[0] in "45" and did.name[1] in "357" and did.get("core", "m4") == "m4": + d2_sram2, d2_sram3 = 128, 32 + # CM4 also missing d3_SRAM + mems["d3_sram"] = {"start": 0x38000000, "size": 64 * 1024, "access": "rwx"} + # STM32H755/57 has the wrong size d2_sram1 + if did.name in ["55", "57"] and did.get("core") == "m4": + # https://github.com/Open-CMSIS-Pack/STM32H7xx_DFP/pull/7 + mems["d2_sram1"]["size"] = 0x40000 + + if d2_sram3: + _add_ram(mems, "d2_sram3", d2_sram3 * 1024, target="d2_sram1") + if d2_sram2: + _add_ram(mems, "d2_sram2", d2_sram2 * 1024, target="d2_sram1") + + for name, data in mems.items(): + if "flash" not in name: + data["access"] = "rwx" + + elif did.family == "u5": + # Fix missing Backup memory + mems["backup"] = {"start": 0x40036400, "size": 2048, "access": "rwx"} + + return [{"name": name} | data for name, data in mems.items()] diff --git a/src/modm_data/dl/stmicro/data/cubemx.patch b/src/modm_data/dl/stmicro/data/cubemx.patch index 28c0dd6..d06a7e1 100644 --- a/src/modm_data/dl/stmicro/data/cubemx.patch +++ b/src/modm_data/dl/stmicro/data/cubemx.patch @@ -44,240 +44,6 @@ index c8a77f2..43d92ee 100644 -diff --git a/mcu/STM32G491C(C-E)Tx.xml b/mcu/STM32G491C(C-E)Tx.xml -index 65f6156..ff9132d 100644 ---- a/mcu/STM32G491C(C-E)Tx.xml -+++ b/mcu/STM32G491C(C-E)Tx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 38 - DIE479 - 256 -diff --git a/mcu/STM32G491C(C-E)Ux.xml b/mcu/STM32G491C(C-E)Ux.xml -index ad99ba7..81b65ca 100644 ---- a/mcu/STM32G491C(C-E)Ux.xml -+++ b/mcu/STM32G491C(C-E)Ux.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 42 - DIE479 - 256 -diff --git a/mcu/STM32G491K(C-E)Ux.xml b/mcu/STM32G491K(C-E)Ux.xml -index e130b99..71c0866 100644 ---- a/mcu/STM32G491K(C-E)Ux.xml -+++ b/mcu/STM32G491K(C-E)Ux.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 26 - DIE479 - 256 -diff --git a/mcu/STM32G491M(C-E)Sx.xml b/mcu/STM32G491M(C-E)Sx.xml -index 251c0da..f280c91 100644 ---- a/mcu/STM32G491M(C-E)Sx.xml -+++ b/mcu/STM32G491M(C-E)Sx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 66 - DIE479 - 256 -diff --git a/mcu/STM32G491M(C-E)Tx.xml b/mcu/STM32G491M(C-E)Tx.xml -index 035e6df..7a6aa05 100644 ---- a/mcu/STM32G491M(C-E)Tx.xml -+++ b/mcu/STM32G491M(C-E)Tx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 66 - DIE479 - 256 -diff --git a/mcu/STM32G491R(C-E)Ix.xml b/mcu/STM32G491R(C-E)Ix.xml -index 6e447a4..17dcde7 100644 ---- a/mcu/STM32G491R(C-E)Ix.xml -+++ b/mcu/STM32G491R(C-E)Ix.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 256 -diff --git a/mcu/STM32G491R(C-E)Tx.xml b/mcu/STM32G491R(C-E)Tx.xml -index 53954a2..20b5b30 100644 ---- a/mcu/STM32G491R(C-E)Tx.xml -+++ b/mcu/STM32G491R(C-E)Tx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 256 -diff --git a/mcu/STM32G491REYx.xml b/mcu/STM32G491REYx.xml -index 86ca3a1..ba7c77c 100644 ---- a/mcu/STM32G491REYx.xml -+++ b/mcu/STM32G491REYx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 512 -diff --git a/mcu/STM32G491V(C-E)Tx.xml b/mcu/STM32G491V(C-E)Tx.xml -index 5a107b2..4db0d98 100644 ---- a/mcu/STM32G491V(C-E)Tx.xml -+++ b/mcu/STM32G491V(C-E)Tx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 86 - DIE479 - 256 -diff --git a/mcu/STM32G4A1CETx.xml b/mcu/STM32G4A1CETx.xml -index 48f57b5..50733a7 100644 ---- a/mcu/STM32G4A1CETx.xml -+++ b/mcu/STM32G4A1CETx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 38 - DIE479 - 512 -diff --git a/mcu/STM32G4A1CEUx.xml b/mcu/STM32G4A1CEUx.xml -index b6f2e9e..d0401b7 100644 ---- a/mcu/STM32G4A1CEUx.xml -+++ b/mcu/STM32G4A1CEUx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 42 - DIE479 - 512 -diff --git a/mcu/STM32G4A1KEUx.xml b/mcu/STM32G4A1KEUx.xml -index 1603692..ccc7c61 100644 ---- a/mcu/STM32G4A1KEUx.xml -+++ b/mcu/STM32G4A1KEUx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 26 - DIE479 - 512 -diff --git a/mcu/STM32G4A1MESx.xml b/mcu/STM32G4A1MESx.xml -index 11d976a..b8e17e4 100644 ---- a/mcu/STM32G4A1MESx.xml -+++ b/mcu/STM32G4A1MESx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 66 - DIE479 - 512 -diff --git a/mcu/STM32G4A1METx.xml b/mcu/STM32G4A1METx.xml -index 5480d7d..1db94a7 100644 ---- a/mcu/STM32G4A1METx.xml -+++ b/mcu/STM32G4A1METx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 66 - DIE479 - 512 -diff --git a/mcu/STM32G4A1REIx.xml b/mcu/STM32G4A1REIx.xml -index cadf888..d6b927c 100644 ---- a/mcu/STM32G4A1REIx.xml -+++ b/mcu/STM32G4A1REIx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 512 -diff --git a/mcu/STM32G4A1RETx.xml b/mcu/STM32G4A1RETx.xml -index 1104460..1937790 100644 ---- a/mcu/STM32G4A1RETx.xml -+++ b/mcu/STM32G4A1RETx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 512 -diff --git a/mcu/STM32G4A1REYx.xml b/mcu/STM32G4A1REYx.xml -index b4429a5..3b6d972 100644 ---- a/mcu/STM32G4A1REYx.xml -+++ b/mcu/STM32G4A1REYx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 52 - DIE479 - 512 -diff --git a/mcu/STM32G4A1VETx.xml b/mcu/STM32G4A1VETx.xml -index 58dcd13..b230c80 100644 ---- a/mcu/STM32G4A1VETx.xml -+++ b/mcu/STM32G4A1VETx.xml -@@ -2,7 +2,7 @@ - - ARM Cortex-M4 - 170 -- 128 -+ 112 - 86 - DIE479 - 512 diff --git a/mcu/IP/DMA-STM32G0B1_dma1_v1_3_Modes.xml b/mcu/IP/DMA-STM32G0B1_dma1_v1_3_Modes.xml index 16f4362..9843602 100644 --- a/mcu/IP/DMA-STM32G0B1_dma1_v1_3_Modes.xml diff --git a/src/modm_data/header2svd/stmicro/header.py b/src/modm_data/header2svd/stmicro/header.py index ff7cd48..b8d1ce5 100644 --- a/src/modm_data/header2svd/stmicro/header.py +++ b/src/modm_data/header2svd/stmicro/header.py @@ -40,9 +40,9 @@ def getDefineForDevice(device_id, familyDefines): # get all defines for this device name devName = "STM32{}{}".format(device_id.family.upper(), device_id.name.upper()) - # Map STM32F7x8 -> STM32F7x7 - if device_id.family == "f7" and devName[8] == "8": - devName = devName[:8] + "7" + # Map STM32WL33 -> STM32WL3X + if device_id.family == "wl" and devName[7:9] in ["30", "31", "33"]: + devName = devName[:-1] + "X" deviceDefines = sorted([define for define in familyDefines if define.startswith(devName)]) # if there is only one define thats the one @@ -67,6 +67,7 @@ def getDefineForDevice(device_id, familyDefines): class Header(CmsisHeader): _HEADER_PATH = ext_path("stmicro/header") _CACHE_PATH = cache_path("cmsis/stm32") + _CACHE_HEADER = defaultdict(dict) _CACHE_FAMILY = defaultdict(dict) _BUILTINS = { "const uint32_t": 4, @@ -77,33 +78,23 @@ class Header(CmsisHeader): "uint8_t": 1, } - def __init__(self, did): + def __init__(self, did, family_header_file, define): self.did = did - self.family_folder = "stm32{}xx".format(self.did.family) - if self.did.string[5:8] in ["h7r", "h7s"]: - self.family_folder = "stm32h7rsxx" - elif self.did.string[5:8] == "wb0": - self.family_folder = "stm32wb0xx" - elif self.did.string[5:8] == "wba": - self.family_folder = "stm32wbaxx" - elif self.did.string[5:8] == "wl3": - self.family_folder = "stm32wl3xx" + self.family_folder = family_header_file + if "xx" not in self.family_folder: + self.family_folder += "x" self.cmsis_folder = Header._HEADER_PATH / self.family_folder / "Include" - self.family_header_file = f"{self.family_folder}.h" - if self.did.string[5:8] == "wb0": - self.family_header_file = "stm32wb0x.h" - elif self.did.string[5:8] == "wl3": - self.family_header_file = "stm32wl3x.h" + self.family_header_file = "{}.h".format(family_header_file) self.family_defines = self._get_family_defines() - self.define = getDefineForDevice(self.did, self.family_defines) - assert self.define is not None + self.define = define[:9].upper() + define[9:] + if self.define not in self.family_defines: + self.define = getDefineForDevice(self.did, self.family_defines) self.is_valid = self.define is not None if not self.is_valid: return - self.header_file = f"{self.define.lower()}.h" - self.device_map = None + self.header_file = "{}.h".format(self.define.lower()) substitutions = { # r"/\* +?(Legacy defines|Legacy aliases|Old .*? legacy purpose|Aliases for .*?) +?\*/.*?\n\n": "", r"/\* +?Legacy (aliases|defines|registers naming) +?\*/.*?\n\n": "", @@ -130,6 +121,17 @@ def memory_map_tree(self): self._cache[self._memory_map_key] = self._get_memmap() return self._cache[self._memory_map_key] + @property + def get_memory_sizes(self): + if "memsizes" not in Header._CACHE_HEADER[self.header_file]: + sizes = { + m.group(1): int(m.group(2), 0) + for d in self.header.defines + if (m := re.match(r"(\w+)_SIZE +\((0x.+?)UL\)", d)) + } + Header._CACHE_HEADER[self.header_file]["memsizes"] = sizes + return Header._CACHE_HEADER[self.header_file]["memsizes"] + @property def interrupt_table(self): if "vectors" not in self._cache: @@ -142,15 +144,11 @@ def interrupt_table(self): def _get_family_defines(self): if self.did.family not in Header._CACHE_FAMILY: + content = (self.cmsis_folder / self.family_header_file).read_text(encoding="utf-8", errors="replace") defines = [] - match = re.findall( - r"if defined\((?PSTM32[A-Z].....)\)", - (self.cmsis_folder / self.family_header_file).read_text(encoding="utf-8", errors="replace"), - ) - if match: - defines = match - else: - LOGGER.error(f"Cannot find family defines for {self.did.string}!") + for include in re.findall(r'#include +"(stm32.*?(?